1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. 4 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) 5 * 6 * Right now, I am very wasteful with the buffers. I allocate memory 7 * pages and then divide them into 2K frame buffers. This way I know I 8 * have buffers large enough to hold one frame within one buffer descriptor. 9 * Once I get this working, I will use 64 or 128 byte CPM buffers, which 10 * will be much more memory efficient and will easily handle lots of 11 * small packets. 12 * 13 * Much better multiple PHY support by Magnus Damm. 14 * Copyright (c) 2000 Ericsson Radio Systems AB. 15 * 16 * Support for FEC controller of ColdFire processors. 17 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) 18 * 19 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) 20 * Copyright (c) 2004-2006 Macq Electronique SA. 21 * 22 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. 23 */ 24 25 #include <linux/module.h> 26 #include <linux/kernel.h> 27 #include <linux/string.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/ptrace.h> 30 #include <linux/errno.h> 31 #include <linux/ioport.h> 32 #include <linux/slab.h> 33 #include <linux/interrupt.h> 34 #include <linux/delay.h> 35 #include <linux/netdevice.h> 36 #include <linux/etherdevice.h> 37 #include <linux/skbuff.h> 38 #include <linux/in.h> 39 #include <linux/ip.h> 40 #include <net/ip.h> 41 #include <net/tso.h> 42 #include <linux/tcp.h> 43 #include <linux/udp.h> 44 #include <linux/icmp.h> 45 #include <linux/spinlock.h> 46 #include <linux/workqueue.h> 47 #include <linux/bitops.h> 48 #include <linux/io.h> 49 #include <linux/irq.h> 50 #include <linux/clk.h> 51 #include <linux/crc32.h> 52 #include <linux/platform_device.h> 53 #include <linux/mdio.h> 54 #include <linux/phy.h> 55 #include <linux/fec.h> 56 #include <linux/of.h> 57 #include <linux/of_device.h> 58 #include <linux/of_gpio.h> 59 #include <linux/of_mdio.h> 60 #include <linux/of_net.h> 61 #include <linux/regulator/consumer.h> 62 #include <linux/if_vlan.h> 63 #include <linux/pinctrl/consumer.h> 64 #include <linux/prefetch.h> 65 #include <linux/mfd/syscon.h> 66 #include <linux/regmap.h> 67 #include <soc/imx/cpuidle.h> 68 69 #include <asm/cacheflush.h> 70 71 #include "fec.h" 72 73 static void set_multicast_list(struct net_device *ndev); 74 static void fec_enet_itr_coal_init(struct net_device *ndev); 75 76 #define DRIVER_NAME "fec" 77 78 /* Pause frame feild and FIFO threshold */ 79 #define FEC_ENET_FCE (1 << 5) 80 #define FEC_ENET_RSEM_V 0x84 81 #define FEC_ENET_RSFL_V 16 82 #define FEC_ENET_RAEM_V 0x8 83 #define FEC_ENET_RAFL_V 0x8 84 #define FEC_ENET_OPD_V 0xFFF0 85 #define FEC_MDIO_PM_TIMEOUT 100 /* ms */ 86 87 struct fec_devinfo { 88 u32 quirks; 89 }; 90 91 static const struct fec_devinfo fec_imx25_info = { 92 .quirks = FEC_QUIRK_USE_GASKET | FEC_QUIRK_MIB_CLEAR | 93 FEC_QUIRK_HAS_FRREG, 94 }; 95 96 static const struct fec_devinfo fec_imx27_info = { 97 .quirks = FEC_QUIRK_MIB_CLEAR | FEC_QUIRK_HAS_FRREG, 98 }; 99 100 static const struct fec_devinfo fec_imx28_info = { 101 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME | 102 FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC | 103 FEC_QUIRK_HAS_FRREG, 104 }; 105 106 static const struct fec_devinfo fec_imx6q_info = { 107 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 108 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 109 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 | 110 FEC_QUIRK_HAS_RACC, 111 }; 112 113 static const struct fec_devinfo fec_mvf600_info = { 114 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC, 115 }; 116 117 static const struct fec_devinfo fec_imx6x_info = { 118 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 119 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 120 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 121 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 122 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE, 123 }; 124 125 static const struct fec_devinfo fec_imx6ul_info = { 126 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 127 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 128 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR007885 | 129 FEC_QUIRK_BUG_CAPTURE | FEC_QUIRK_HAS_RACC | 130 FEC_QUIRK_HAS_COALESCE, 131 }; 132 133 static struct platform_device_id fec_devtype[] = { 134 { 135 /* keep it for coldfire */ 136 .name = DRIVER_NAME, 137 .driver_data = 0, 138 }, { 139 .name = "imx25-fec", 140 .driver_data = (kernel_ulong_t)&fec_imx25_info, 141 }, { 142 .name = "imx27-fec", 143 .driver_data = (kernel_ulong_t)&fec_imx27_info, 144 }, { 145 .name = "imx28-fec", 146 .driver_data = (kernel_ulong_t)&fec_imx28_info, 147 }, { 148 .name = "imx6q-fec", 149 .driver_data = (kernel_ulong_t)&fec_imx6q_info, 150 }, { 151 .name = "mvf600-fec", 152 .driver_data = (kernel_ulong_t)&fec_mvf600_info, 153 }, { 154 .name = "imx6sx-fec", 155 .driver_data = (kernel_ulong_t)&fec_imx6x_info, 156 }, { 157 .name = "imx6ul-fec", 158 .driver_data = (kernel_ulong_t)&fec_imx6ul_info, 159 }, { 160 /* sentinel */ 161 } 162 }; 163 MODULE_DEVICE_TABLE(platform, fec_devtype); 164 165 enum imx_fec_type { 166 IMX25_FEC = 1, /* runs on i.mx25/50/53 */ 167 IMX27_FEC, /* runs on i.mx27/35/51 */ 168 IMX28_FEC, 169 IMX6Q_FEC, 170 MVF600_FEC, 171 IMX6SX_FEC, 172 IMX6UL_FEC, 173 }; 174 175 static const struct of_device_id fec_dt_ids[] = { 176 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], }, 177 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], }, 178 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], }, 179 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], }, 180 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], }, 181 { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], }, 182 { .compatible = "fsl,imx6ul-fec", .data = &fec_devtype[IMX6UL_FEC], }, 183 { /* sentinel */ } 184 }; 185 MODULE_DEVICE_TABLE(of, fec_dt_ids); 186 187 static unsigned char macaddr[ETH_ALEN]; 188 module_param_array(macaddr, byte, NULL, 0); 189 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address"); 190 191 #if defined(CONFIG_M5272) 192 /* 193 * Some hardware gets it MAC address out of local flash memory. 194 * if this is non-zero then assume it is the address to get MAC from. 195 */ 196 #if defined(CONFIG_NETtel) 197 #define FEC_FLASHMAC 0xf0006006 198 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) 199 #define FEC_FLASHMAC 0xf0006000 200 #elif defined(CONFIG_CANCam) 201 #define FEC_FLASHMAC 0xf0020000 202 #elif defined (CONFIG_M5272C3) 203 #define FEC_FLASHMAC (0xffe04000 + 4) 204 #elif defined(CONFIG_MOD5272) 205 #define FEC_FLASHMAC 0xffc0406b 206 #else 207 #define FEC_FLASHMAC 0 208 #endif 209 #endif /* CONFIG_M5272 */ 210 211 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets. 212 * 213 * 2048 byte skbufs are allocated. However, alignment requirements 214 * varies between FEC variants. Worst case is 64, so round down by 64. 215 */ 216 #define PKT_MAXBUF_SIZE (round_down(2048 - 64, 64)) 217 #define PKT_MINBUF_SIZE 64 218 219 /* FEC receive acceleration */ 220 #define FEC_RACC_IPDIS (1 << 1) 221 #define FEC_RACC_PRODIS (1 << 2) 222 #define FEC_RACC_SHIFT16 BIT(7) 223 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS) 224 225 /* MIB Control Register */ 226 #define FEC_MIB_CTRLSTAT_DISABLE BIT(31) 227 228 /* 229 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame 230 * size bits. Other FEC hardware does not, so we need to take that into 231 * account when setting it. 232 */ 233 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 234 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \ 235 defined(CONFIG_ARM64) 236 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) 237 #else 238 #define OPT_FRAME_SIZE 0 239 #endif 240 241 /* FEC MII MMFR bits definition */ 242 #define FEC_MMFR_ST (1 << 30) 243 #define FEC_MMFR_ST_C45 (0) 244 #define FEC_MMFR_OP_READ (2 << 28) 245 #define FEC_MMFR_OP_READ_C45 (3 << 28) 246 #define FEC_MMFR_OP_WRITE (1 << 28) 247 #define FEC_MMFR_OP_ADDR_WRITE (0) 248 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23) 249 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18) 250 #define FEC_MMFR_TA (2 << 16) 251 #define FEC_MMFR_DATA(v) (v & 0xffff) 252 /* FEC ECR bits definition */ 253 #define FEC_ECR_MAGICEN (1 << 2) 254 #define FEC_ECR_SLEEP (1 << 3) 255 256 #define FEC_MII_TIMEOUT 30000 /* us */ 257 258 /* Transmitter timeout */ 259 #define TX_TIMEOUT (2 * HZ) 260 261 #define FEC_PAUSE_FLAG_AUTONEG 0x1 262 #define FEC_PAUSE_FLAG_ENABLE 0x2 263 #define FEC_WOL_HAS_MAGIC_PACKET (0x1 << 0) 264 #define FEC_WOL_FLAG_ENABLE (0x1 << 1) 265 #define FEC_WOL_FLAG_SLEEP_ON (0x1 << 2) 266 267 #define COPYBREAK_DEFAULT 256 268 269 /* Max number of allowed TCP segments for software TSO */ 270 #define FEC_MAX_TSO_SEGS 100 271 #define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) 272 273 #define IS_TSO_HEADER(txq, addr) \ 274 ((addr >= txq->tso_hdrs_dma) && \ 275 (addr < txq->tso_hdrs_dma + txq->bd.ring_size * TSO_HEADER_SIZE)) 276 277 static int mii_cnt; 278 279 static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, 280 struct bufdesc_prop *bd) 281 { 282 return (bdp >= bd->last) ? bd->base 283 : (struct bufdesc *)(((void *)bdp) + bd->dsize); 284 } 285 286 static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, 287 struct bufdesc_prop *bd) 288 { 289 return (bdp <= bd->base) ? bd->last 290 : (struct bufdesc *)(((void *)bdp) - bd->dsize); 291 } 292 293 static int fec_enet_get_bd_index(struct bufdesc *bdp, 294 struct bufdesc_prop *bd) 295 { 296 return ((const char *)bdp - (const char *)bd->base) >> bd->dsize_log2; 297 } 298 299 static int fec_enet_get_free_txdesc_num(struct fec_enet_priv_tx_q *txq) 300 { 301 int entries; 302 303 entries = (((const char *)txq->dirty_tx - 304 (const char *)txq->bd.cur) >> txq->bd.dsize_log2) - 1; 305 306 return entries >= 0 ? entries : entries + txq->bd.ring_size; 307 } 308 309 static void swap_buffer(void *bufaddr, int len) 310 { 311 int i; 312 unsigned int *buf = bufaddr; 313 314 for (i = 0; i < len; i += 4, buf++) 315 swab32s(buf); 316 } 317 318 static void swap_buffer2(void *dst_buf, void *src_buf, int len) 319 { 320 int i; 321 unsigned int *src = src_buf; 322 unsigned int *dst = dst_buf; 323 324 for (i = 0; i < len; i += 4, src++, dst++) 325 *dst = swab32p(src); 326 } 327 328 static void fec_dump(struct net_device *ndev) 329 { 330 struct fec_enet_private *fep = netdev_priv(ndev); 331 struct bufdesc *bdp; 332 struct fec_enet_priv_tx_q *txq; 333 int index = 0; 334 335 netdev_info(ndev, "TX ring dump\n"); 336 pr_info("Nr SC addr len SKB\n"); 337 338 txq = fep->tx_queue[0]; 339 bdp = txq->bd.base; 340 341 do { 342 pr_info("%3u %c%c 0x%04x 0x%08x %4u %p\n", 343 index, 344 bdp == txq->bd.cur ? 'S' : ' ', 345 bdp == txq->dirty_tx ? 'H' : ' ', 346 fec16_to_cpu(bdp->cbd_sc), 347 fec32_to_cpu(bdp->cbd_bufaddr), 348 fec16_to_cpu(bdp->cbd_datlen), 349 txq->tx_skbuff[index]); 350 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 351 index++; 352 } while (bdp != txq->bd.base); 353 } 354 355 static inline bool is_ipv4_pkt(struct sk_buff *skb) 356 { 357 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4; 358 } 359 360 static int 361 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev) 362 { 363 /* Only run for packets requiring a checksum. */ 364 if (skb->ip_summed != CHECKSUM_PARTIAL) 365 return 0; 366 367 if (unlikely(skb_cow_head(skb, 0))) 368 return -1; 369 370 if (is_ipv4_pkt(skb)) 371 ip_hdr(skb)->check = 0; 372 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0; 373 374 return 0; 375 } 376 377 static struct bufdesc * 378 fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq, 379 struct sk_buff *skb, 380 struct net_device *ndev) 381 { 382 struct fec_enet_private *fep = netdev_priv(ndev); 383 struct bufdesc *bdp = txq->bd.cur; 384 struct bufdesc_ex *ebdp; 385 int nr_frags = skb_shinfo(skb)->nr_frags; 386 int frag, frag_len; 387 unsigned short status; 388 unsigned int estatus = 0; 389 skb_frag_t *this_frag; 390 unsigned int index; 391 void *bufaddr; 392 dma_addr_t addr; 393 int i; 394 395 for (frag = 0; frag < nr_frags; frag++) { 396 this_frag = &skb_shinfo(skb)->frags[frag]; 397 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 398 ebdp = (struct bufdesc_ex *)bdp; 399 400 status = fec16_to_cpu(bdp->cbd_sc); 401 status &= ~BD_ENET_TX_STATS; 402 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 403 frag_len = skb_frag_size(&skb_shinfo(skb)->frags[frag]); 404 405 /* Handle the last BD specially */ 406 if (frag == nr_frags - 1) { 407 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 408 if (fep->bufdesc_ex) { 409 estatus |= BD_ENET_TX_INT; 410 if (unlikely(skb_shinfo(skb)->tx_flags & 411 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 412 estatus |= BD_ENET_TX_TS; 413 } 414 } 415 416 if (fep->bufdesc_ex) { 417 if (fep->quirks & FEC_QUIRK_HAS_AVB) 418 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 419 if (skb->ip_summed == CHECKSUM_PARTIAL) 420 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 421 ebdp->cbd_bdu = 0; 422 ebdp->cbd_esc = cpu_to_fec32(estatus); 423 } 424 425 bufaddr = skb_frag_address(this_frag); 426 427 index = fec_enet_get_bd_index(bdp, &txq->bd); 428 if (((unsigned long) bufaddr) & fep->tx_align || 429 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 430 memcpy(txq->tx_bounce[index], bufaddr, frag_len); 431 bufaddr = txq->tx_bounce[index]; 432 433 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 434 swap_buffer(bufaddr, frag_len); 435 } 436 437 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len, 438 DMA_TO_DEVICE); 439 if (dma_mapping_error(&fep->pdev->dev, addr)) { 440 if (net_ratelimit()) 441 netdev_err(ndev, "Tx DMA memory map failed\n"); 442 goto dma_mapping_error; 443 } 444 445 bdp->cbd_bufaddr = cpu_to_fec32(addr); 446 bdp->cbd_datlen = cpu_to_fec16(frag_len); 447 /* Make sure the updates to rest of the descriptor are 448 * performed before transferring ownership. 449 */ 450 wmb(); 451 bdp->cbd_sc = cpu_to_fec16(status); 452 } 453 454 return bdp; 455 dma_mapping_error: 456 bdp = txq->bd.cur; 457 for (i = 0; i < frag; i++) { 458 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 459 dma_unmap_single(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr), 460 fec16_to_cpu(bdp->cbd_datlen), DMA_TO_DEVICE); 461 } 462 return ERR_PTR(-ENOMEM); 463 } 464 465 static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq, 466 struct sk_buff *skb, struct net_device *ndev) 467 { 468 struct fec_enet_private *fep = netdev_priv(ndev); 469 int nr_frags = skb_shinfo(skb)->nr_frags; 470 struct bufdesc *bdp, *last_bdp; 471 void *bufaddr; 472 dma_addr_t addr; 473 unsigned short status; 474 unsigned short buflen; 475 unsigned int estatus = 0; 476 unsigned int index; 477 int entries_free; 478 479 entries_free = fec_enet_get_free_txdesc_num(txq); 480 if (entries_free < MAX_SKB_FRAGS + 1) { 481 dev_kfree_skb_any(skb); 482 if (net_ratelimit()) 483 netdev_err(ndev, "NOT enough BD for SG!\n"); 484 return NETDEV_TX_OK; 485 } 486 487 /* Protocol checksum off-load for TCP and UDP. */ 488 if (fec_enet_clear_csum(skb, ndev)) { 489 dev_kfree_skb_any(skb); 490 return NETDEV_TX_OK; 491 } 492 493 /* Fill in a Tx ring entry */ 494 bdp = txq->bd.cur; 495 last_bdp = bdp; 496 status = fec16_to_cpu(bdp->cbd_sc); 497 status &= ~BD_ENET_TX_STATS; 498 499 /* Set buffer length and buffer pointer */ 500 bufaddr = skb->data; 501 buflen = skb_headlen(skb); 502 503 index = fec_enet_get_bd_index(bdp, &txq->bd); 504 if (((unsigned long) bufaddr) & fep->tx_align || 505 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 506 memcpy(txq->tx_bounce[index], skb->data, buflen); 507 bufaddr = txq->tx_bounce[index]; 508 509 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 510 swap_buffer(bufaddr, buflen); 511 } 512 513 /* Push the data cache so the CPM does not get stale memory data. */ 514 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE); 515 if (dma_mapping_error(&fep->pdev->dev, addr)) { 516 dev_kfree_skb_any(skb); 517 if (net_ratelimit()) 518 netdev_err(ndev, "Tx DMA memory map failed\n"); 519 return NETDEV_TX_OK; 520 } 521 522 if (nr_frags) { 523 last_bdp = fec_enet_txq_submit_frag_skb(txq, skb, ndev); 524 if (IS_ERR(last_bdp)) { 525 dma_unmap_single(&fep->pdev->dev, addr, 526 buflen, DMA_TO_DEVICE); 527 dev_kfree_skb_any(skb); 528 return NETDEV_TX_OK; 529 } 530 } else { 531 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 532 if (fep->bufdesc_ex) { 533 estatus = BD_ENET_TX_INT; 534 if (unlikely(skb_shinfo(skb)->tx_flags & 535 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 536 estatus |= BD_ENET_TX_TS; 537 } 538 } 539 bdp->cbd_bufaddr = cpu_to_fec32(addr); 540 bdp->cbd_datlen = cpu_to_fec16(buflen); 541 542 if (fep->bufdesc_ex) { 543 544 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 545 546 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 547 fep->hwts_tx_en)) 548 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 549 550 if (fep->quirks & FEC_QUIRK_HAS_AVB) 551 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 552 553 if (skb->ip_summed == CHECKSUM_PARTIAL) 554 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 555 556 ebdp->cbd_bdu = 0; 557 ebdp->cbd_esc = cpu_to_fec32(estatus); 558 } 559 560 index = fec_enet_get_bd_index(last_bdp, &txq->bd); 561 /* Save skb pointer */ 562 txq->tx_skbuff[index] = skb; 563 564 /* Make sure the updates to rest of the descriptor are performed before 565 * transferring ownership. 566 */ 567 wmb(); 568 569 /* Send it on its way. Tell FEC it's ready, interrupt when done, 570 * it's the last BD of the frame, and to put the CRC on the end. 571 */ 572 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC); 573 bdp->cbd_sc = cpu_to_fec16(status); 574 575 /* If this was the last BD in the ring, start at the beginning again. */ 576 bdp = fec_enet_get_nextdesc(last_bdp, &txq->bd); 577 578 skb_tx_timestamp(skb); 579 580 /* Make sure the update to bdp and tx_skbuff are performed before 581 * txq->bd.cur. 582 */ 583 wmb(); 584 txq->bd.cur = bdp; 585 586 /* Trigger transmission start */ 587 writel(0, txq->bd.reg_desc_active); 588 589 return 0; 590 } 591 592 static int 593 fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb, 594 struct net_device *ndev, 595 struct bufdesc *bdp, int index, char *data, 596 int size, bool last_tcp, bool is_last) 597 { 598 struct fec_enet_private *fep = netdev_priv(ndev); 599 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 600 unsigned short status; 601 unsigned int estatus = 0; 602 dma_addr_t addr; 603 604 status = fec16_to_cpu(bdp->cbd_sc); 605 status &= ~BD_ENET_TX_STATS; 606 607 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 608 609 if (((unsigned long) data) & fep->tx_align || 610 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 611 memcpy(txq->tx_bounce[index], data, size); 612 data = txq->tx_bounce[index]; 613 614 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 615 swap_buffer(data, size); 616 } 617 618 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE); 619 if (dma_mapping_error(&fep->pdev->dev, addr)) { 620 dev_kfree_skb_any(skb); 621 if (net_ratelimit()) 622 netdev_err(ndev, "Tx DMA memory map failed\n"); 623 return NETDEV_TX_BUSY; 624 } 625 626 bdp->cbd_datlen = cpu_to_fec16(size); 627 bdp->cbd_bufaddr = cpu_to_fec32(addr); 628 629 if (fep->bufdesc_ex) { 630 if (fep->quirks & FEC_QUIRK_HAS_AVB) 631 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 632 if (skb->ip_summed == CHECKSUM_PARTIAL) 633 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 634 ebdp->cbd_bdu = 0; 635 ebdp->cbd_esc = cpu_to_fec32(estatus); 636 } 637 638 /* Handle the last BD specially */ 639 if (last_tcp) 640 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC); 641 if (is_last) { 642 status |= BD_ENET_TX_INTR; 643 if (fep->bufdesc_ex) 644 ebdp->cbd_esc |= cpu_to_fec32(BD_ENET_TX_INT); 645 } 646 647 bdp->cbd_sc = cpu_to_fec16(status); 648 649 return 0; 650 } 651 652 static int 653 fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq, 654 struct sk_buff *skb, struct net_device *ndev, 655 struct bufdesc *bdp, int index) 656 { 657 struct fec_enet_private *fep = netdev_priv(ndev); 658 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 659 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 660 void *bufaddr; 661 unsigned long dmabuf; 662 unsigned short status; 663 unsigned int estatus = 0; 664 665 status = fec16_to_cpu(bdp->cbd_sc); 666 status &= ~BD_ENET_TX_STATS; 667 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 668 669 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 670 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE; 671 if (((unsigned long)bufaddr) & fep->tx_align || 672 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 673 memcpy(txq->tx_bounce[index], skb->data, hdr_len); 674 bufaddr = txq->tx_bounce[index]; 675 676 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 677 swap_buffer(bufaddr, hdr_len); 678 679 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr, 680 hdr_len, DMA_TO_DEVICE); 681 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) { 682 dev_kfree_skb_any(skb); 683 if (net_ratelimit()) 684 netdev_err(ndev, "Tx DMA memory map failed\n"); 685 return NETDEV_TX_BUSY; 686 } 687 } 688 689 bdp->cbd_bufaddr = cpu_to_fec32(dmabuf); 690 bdp->cbd_datlen = cpu_to_fec16(hdr_len); 691 692 if (fep->bufdesc_ex) { 693 if (fep->quirks & FEC_QUIRK_HAS_AVB) 694 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 695 if (skb->ip_summed == CHECKSUM_PARTIAL) 696 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 697 ebdp->cbd_bdu = 0; 698 ebdp->cbd_esc = cpu_to_fec32(estatus); 699 } 700 701 bdp->cbd_sc = cpu_to_fec16(status); 702 703 return 0; 704 } 705 706 static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq, 707 struct sk_buff *skb, 708 struct net_device *ndev) 709 { 710 struct fec_enet_private *fep = netdev_priv(ndev); 711 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 712 int total_len, data_left; 713 struct bufdesc *bdp = txq->bd.cur; 714 struct tso_t tso; 715 unsigned int index = 0; 716 int ret; 717 718 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(txq)) { 719 dev_kfree_skb_any(skb); 720 if (net_ratelimit()) 721 netdev_err(ndev, "NOT enough BD for TSO!\n"); 722 return NETDEV_TX_OK; 723 } 724 725 /* Protocol checksum off-load for TCP and UDP. */ 726 if (fec_enet_clear_csum(skb, ndev)) { 727 dev_kfree_skb_any(skb); 728 return NETDEV_TX_OK; 729 } 730 731 /* Initialize the TSO handler, and prepare the first payload */ 732 tso_start(skb, &tso); 733 734 total_len = skb->len - hdr_len; 735 while (total_len > 0) { 736 char *hdr; 737 738 index = fec_enet_get_bd_index(bdp, &txq->bd); 739 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); 740 total_len -= data_left; 741 742 /* prepare packet headers: MAC + IP + TCP */ 743 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 744 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); 745 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index); 746 if (ret) 747 goto err_release; 748 749 while (data_left > 0) { 750 int size; 751 752 size = min_t(int, tso.size, data_left); 753 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 754 index = fec_enet_get_bd_index(bdp, &txq->bd); 755 ret = fec_enet_txq_put_data_tso(txq, skb, ndev, 756 bdp, index, 757 tso.data, size, 758 size == data_left, 759 total_len == 0); 760 if (ret) 761 goto err_release; 762 763 data_left -= size; 764 tso_build_data(skb, &tso, size); 765 } 766 767 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 768 } 769 770 /* Save skb pointer */ 771 txq->tx_skbuff[index] = skb; 772 773 skb_tx_timestamp(skb); 774 txq->bd.cur = bdp; 775 776 /* Trigger transmission start */ 777 if (!(fep->quirks & FEC_QUIRK_ERR007885) || 778 !readl(txq->bd.reg_desc_active) || 779 !readl(txq->bd.reg_desc_active) || 780 !readl(txq->bd.reg_desc_active) || 781 !readl(txq->bd.reg_desc_active)) 782 writel(0, txq->bd.reg_desc_active); 783 784 return 0; 785 786 err_release: 787 /* TODO: Release all used data descriptors for TSO */ 788 return ret; 789 } 790 791 static netdev_tx_t 792 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) 793 { 794 struct fec_enet_private *fep = netdev_priv(ndev); 795 int entries_free; 796 unsigned short queue; 797 struct fec_enet_priv_tx_q *txq; 798 struct netdev_queue *nq; 799 int ret; 800 801 queue = skb_get_queue_mapping(skb); 802 txq = fep->tx_queue[queue]; 803 nq = netdev_get_tx_queue(ndev, queue); 804 805 if (skb_is_gso(skb)) 806 ret = fec_enet_txq_submit_tso(txq, skb, ndev); 807 else 808 ret = fec_enet_txq_submit_skb(txq, skb, ndev); 809 if (ret) 810 return ret; 811 812 entries_free = fec_enet_get_free_txdesc_num(txq); 813 if (entries_free <= txq->tx_stop_threshold) 814 netif_tx_stop_queue(nq); 815 816 return NETDEV_TX_OK; 817 } 818 819 /* Init RX & TX buffer descriptors 820 */ 821 static void fec_enet_bd_init(struct net_device *dev) 822 { 823 struct fec_enet_private *fep = netdev_priv(dev); 824 struct fec_enet_priv_tx_q *txq; 825 struct fec_enet_priv_rx_q *rxq; 826 struct bufdesc *bdp; 827 unsigned int i; 828 unsigned int q; 829 830 for (q = 0; q < fep->num_rx_queues; q++) { 831 /* Initialize the receive buffer descriptors. */ 832 rxq = fep->rx_queue[q]; 833 bdp = rxq->bd.base; 834 835 for (i = 0; i < rxq->bd.ring_size; i++) { 836 837 /* Initialize the BD for every fragment in the page. */ 838 if (bdp->cbd_bufaddr) 839 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); 840 else 841 bdp->cbd_sc = cpu_to_fec16(0); 842 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 843 } 844 845 /* Set the last buffer to wrap */ 846 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); 847 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 848 849 rxq->bd.cur = rxq->bd.base; 850 } 851 852 for (q = 0; q < fep->num_tx_queues; q++) { 853 /* ...and the same for transmit */ 854 txq = fep->tx_queue[q]; 855 bdp = txq->bd.base; 856 txq->bd.cur = bdp; 857 858 for (i = 0; i < txq->bd.ring_size; i++) { 859 /* Initialize the BD for every fragment in the page. */ 860 bdp->cbd_sc = cpu_to_fec16(0); 861 if (bdp->cbd_bufaddr && 862 !IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr))) 863 dma_unmap_single(&fep->pdev->dev, 864 fec32_to_cpu(bdp->cbd_bufaddr), 865 fec16_to_cpu(bdp->cbd_datlen), 866 DMA_TO_DEVICE); 867 if (txq->tx_skbuff[i]) { 868 dev_kfree_skb_any(txq->tx_skbuff[i]); 869 txq->tx_skbuff[i] = NULL; 870 } 871 bdp->cbd_bufaddr = cpu_to_fec32(0); 872 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 873 } 874 875 /* Set the last buffer to wrap */ 876 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); 877 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 878 txq->dirty_tx = bdp; 879 } 880 } 881 882 static void fec_enet_active_rxring(struct net_device *ndev) 883 { 884 struct fec_enet_private *fep = netdev_priv(ndev); 885 int i; 886 887 for (i = 0; i < fep->num_rx_queues; i++) 888 writel(0, fep->rx_queue[i]->bd.reg_desc_active); 889 } 890 891 static void fec_enet_enable_ring(struct net_device *ndev) 892 { 893 struct fec_enet_private *fep = netdev_priv(ndev); 894 struct fec_enet_priv_tx_q *txq; 895 struct fec_enet_priv_rx_q *rxq; 896 int i; 897 898 for (i = 0; i < fep->num_rx_queues; i++) { 899 rxq = fep->rx_queue[i]; 900 writel(rxq->bd.dma, fep->hwp + FEC_R_DES_START(i)); 901 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i)); 902 903 /* enable DMA1/2 */ 904 if (i) 905 writel(RCMR_MATCHEN | RCMR_CMP(i), 906 fep->hwp + FEC_RCMR(i)); 907 } 908 909 for (i = 0; i < fep->num_tx_queues; i++) { 910 txq = fep->tx_queue[i]; 911 writel(txq->bd.dma, fep->hwp + FEC_X_DES_START(i)); 912 913 /* enable DMA1/2 */ 914 if (i) 915 writel(DMA_CLASS_EN | IDLE_SLOPE(i), 916 fep->hwp + FEC_DMA_CFG(i)); 917 } 918 } 919 920 static void fec_enet_reset_skb(struct net_device *ndev) 921 { 922 struct fec_enet_private *fep = netdev_priv(ndev); 923 struct fec_enet_priv_tx_q *txq; 924 int i, j; 925 926 for (i = 0; i < fep->num_tx_queues; i++) { 927 txq = fep->tx_queue[i]; 928 929 for (j = 0; j < txq->bd.ring_size; j++) { 930 if (txq->tx_skbuff[j]) { 931 dev_kfree_skb_any(txq->tx_skbuff[j]); 932 txq->tx_skbuff[j] = NULL; 933 } 934 } 935 } 936 } 937 938 /* 939 * This function is called to start or restart the FEC during a link 940 * change, transmit timeout, or to reconfigure the FEC. The network 941 * packet processing for this device must be stopped before this call. 942 */ 943 static void 944 fec_restart(struct net_device *ndev) 945 { 946 struct fec_enet_private *fep = netdev_priv(ndev); 947 u32 val; 948 u32 temp_mac[2]; 949 u32 rcntl = OPT_FRAME_SIZE | 0x04; 950 u32 ecntl = 0x2; /* ETHEREN */ 951 952 /* Whack a reset. We should wait for this. 953 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC 954 * instead of reset MAC itself. 955 */ 956 if (fep->quirks & FEC_QUIRK_HAS_AVB) { 957 writel(0, fep->hwp + FEC_ECNTRL); 958 } else { 959 writel(1, fep->hwp + FEC_ECNTRL); 960 udelay(10); 961 } 962 963 /* 964 * enet-mac reset will reset mac address registers too, 965 * so need to reconfigure it. 966 */ 967 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN); 968 writel((__force u32)cpu_to_be32(temp_mac[0]), 969 fep->hwp + FEC_ADDR_LOW); 970 writel((__force u32)cpu_to_be32(temp_mac[1]), 971 fep->hwp + FEC_ADDR_HIGH); 972 973 /* Clear any outstanding interrupt, except MDIO. */ 974 writel((0xffffffff & ~FEC_ENET_MII), fep->hwp + FEC_IEVENT); 975 976 fec_enet_bd_init(ndev); 977 978 fec_enet_enable_ring(ndev); 979 980 /* Reset tx SKB buffers. */ 981 fec_enet_reset_skb(ndev); 982 983 /* Enable MII mode */ 984 if (fep->full_duplex == DUPLEX_FULL) { 985 /* FD enable */ 986 writel(0x04, fep->hwp + FEC_X_CNTRL); 987 } else { 988 /* No Rcv on Xmit */ 989 rcntl |= 0x02; 990 writel(0x0, fep->hwp + FEC_X_CNTRL); 991 } 992 993 /* Set MII speed */ 994 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 995 996 #if !defined(CONFIG_M5272) 997 if (fep->quirks & FEC_QUIRK_HAS_RACC) { 998 val = readl(fep->hwp + FEC_RACC); 999 /* align IP header */ 1000 val |= FEC_RACC_SHIFT16; 1001 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED) 1002 /* set RX checksum */ 1003 val |= FEC_RACC_OPTIONS; 1004 else 1005 val &= ~FEC_RACC_OPTIONS; 1006 writel(val, fep->hwp + FEC_RACC); 1007 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_FTRL); 1008 } 1009 #endif 1010 1011 /* 1012 * The phy interface and speed need to get configured 1013 * differently on enet-mac. 1014 */ 1015 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 1016 /* Enable flow control and length check */ 1017 rcntl |= 0x40000000 | 0x00000020; 1018 1019 /* RGMII, RMII or MII */ 1020 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII || 1021 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 1022 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID || 1023 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) 1024 rcntl |= (1 << 6); 1025 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 1026 rcntl |= (1 << 8); 1027 else 1028 rcntl &= ~(1 << 8); 1029 1030 /* 1G, 100M or 10M */ 1031 if (ndev->phydev) { 1032 if (ndev->phydev->speed == SPEED_1000) 1033 ecntl |= (1 << 5); 1034 else if (ndev->phydev->speed == SPEED_100) 1035 rcntl &= ~(1 << 9); 1036 else 1037 rcntl |= (1 << 9); 1038 } 1039 } else { 1040 #ifdef FEC_MIIGSK_ENR 1041 if (fep->quirks & FEC_QUIRK_USE_GASKET) { 1042 u32 cfgr; 1043 /* disable the gasket and wait */ 1044 writel(0, fep->hwp + FEC_MIIGSK_ENR); 1045 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4) 1046 udelay(1); 1047 1048 /* 1049 * configure the gasket: 1050 * RMII, 50 MHz, no loopback, no echo 1051 * MII, 25 MHz, no loopback, no echo 1052 */ 1053 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 1054 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII; 1055 if (ndev->phydev && ndev->phydev->speed == SPEED_10) 1056 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M; 1057 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR); 1058 1059 /* re-enable the gasket */ 1060 writel(2, fep->hwp + FEC_MIIGSK_ENR); 1061 } 1062 #endif 1063 } 1064 1065 #if !defined(CONFIG_M5272) 1066 /* enable pause frame*/ 1067 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) || 1068 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) && 1069 ndev->phydev && ndev->phydev->pause)) { 1070 rcntl |= FEC_ENET_FCE; 1071 1072 /* set FIFO threshold parameter to reduce overrun */ 1073 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM); 1074 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL); 1075 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM); 1076 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL); 1077 1078 /* OPD */ 1079 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD); 1080 } else { 1081 rcntl &= ~FEC_ENET_FCE; 1082 } 1083 #endif /* !defined(CONFIG_M5272) */ 1084 1085 writel(rcntl, fep->hwp + FEC_R_CNTRL); 1086 1087 /* Setup multicast filter. */ 1088 set_multicast_list(ndev); 1089 #ifndef CONFIG_M5272 1090 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); 1091 writel(0, fep->hwp + FEC_HASH_TABLE_LOW); 1092 #endif 1093 1094 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 1095 /* enable ENET endian swap */ 1096 ecntl |= (1 << 8); 1097 /* enable ENET store and forward mode */ 1098 writel(1 << 8, fep->hwp + FEC_X_WMRK); 1099 } 1100 1101 if (fep->bufdesc_ex) 1102 ecntl |= (1 << 4); 1103 1104 #ifndef CONFIG_M5272 1105 /* Enable the MIB statistic event counters */ 1106 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT); 1107 #endif 1108 1109 /* And last, enable the transmit and receive processing */ 1110 writel(ecntl, fep->hwp + FEC_ECNTRL); 1111 fec_enet_active_rxring(ndev); 1112 1113 if (fep->bufdesc_ex) 1114 fec_ptp_start_cyclecounter(ndev); 1115 1116 /* Enable interrupts we wish to service */ 1117 if (fep->link) 1118 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1119 else 1120 writel(0, fep->hwp + FEC_IMASK); 1121 1122 /* Init the interrupt coalescing */ 1123 fec_enet_itr_coal_init(ndev); 1124 1125 } 1126 1127 static void fec_enet_stop_mode(struct fec_enet_private *fep, bool enabled) 1128 { 1129 struct fec_platform_data *pdata = fep->pdev->dev.platform_data; 1130 struct fec_stop_mode_gpr *stop_gpr = &fep->stop_gpr; 1131 1132 if (stop_gpr->gpr) { 1133 if (enabled) 1134 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg, 1135 BIT(stop_gpr->bit), 1136 BIT(stop_gpr->bit)); 1137 else 1138 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg, 1139 BIT(stop_gpr->bit), 0); 1140 } else if (pdata && pdata->sleep_mode_enable) { 1141 pdata->sleep_mode_enable(enabled); 1142 } 1143 } 1144 1145 static void 1146 fec_stop(struct net_device *ndev) 1147 { 1148 struct fec_enet_private *fep = netdev_priv(ndev); 1149 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8); 1150 u32 val; 1151 1152 /* We cannot expect a graceful transmit stop without link !!! */ 1153 if (fep->link) { 1154 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ 1155 udelay(10); 1156 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) 1157 netdev_err(ndev, "Graceful transmit stop did not complete!\n"); 1158 } 1159 1160 /* Whack a reset. We should wait for this. 1161 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC 1162 * instead of reset MAC itself. 1163 */ 1164 if (!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1165 if (fep->quirks & FEC_QUIRK_HAS_AVB) { 1166 writel(0, fep->hwp + FEC_ECNTRL); 1167 } else { 1168 writel(1, fep->hwp + FEC_ECNTRL); 1169 udelay(10); 1170 } 1171 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1172 } else { 1173 writel(FEC_DEFAULT_IMASK | FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK); 1174 val = readl(fep->hwp + FEC_ECNTRL); 1175 val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP); 1176 writel(val, fep->hwp + FEC_ECNTRL); 1177 fec_enet_stop_mode(fep, true); 1178 } 1179 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1180 1181 /* We have to keep ENET enabled to have MII interrupt stay working */ 1182 if (fep->quirks & FEC_QUIRK_ENET_MAC && 1183 !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1184 writel(2, fep->hwp + FEC_ECNTRL); 1185 writel(rmii_mode, fep->hwp + FEC_R_CNTRL); 1186 } 1187 } 1188 1189 1190 static void 1191 fec_timeout(struct net_device *ndev, unsigned int txqueue) 1192 { 1193 struct fec_enet_private *fep = netdev_priv(ndev); 1194 1195 fec_dump(ndev); 1196 1197 ndev->stats.tx_errors++; 1198 1199 schedule_work(&fep->tx_timeout_work); 1200 } 1201 1202 static void fec_enet_timeout_work(struct work_struct *work) 1203 { 1204 struct fec_enet_private *fep = 1205 container_of(work, struct fec_enet_private, tx_timeout_work); 1206 struct net_device *ndev = fep->netdev; 1207 1208 rtnl_lock(); 1209 if (netif_device_present(ndev) || netif_running(ndev)) { 1210 napi_disable(&fep->napi); 1211 netif_tx_lock_bh(ndev); 1212 fec_restart(ndev); 1213 netif_tx_wake_all_queues(ndev); 1214 netif_tx_unlock_bh(ndev); 1215 napi_enable(&fep->napi); 1216 } 1217 rtnl_unlock(); 1218 } 1219 1220 static void 1221 fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts, 1222 struct skb_shared_hwtstamps *hwtstamps) 1223 { 1224 unsigned long flags; 1225 u64 ns; 1226 1227 spin_lock_irqsave(&fep->tmreg_lock, flags); 1228 ns = timecounter_cyc2time(&fep->tc, ts); 1229 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 1230 1231 memset(hwtstamps, 0, sizeof(*hwtstamps)); 1232 hwtstamps->hwtstamp = ns_to_ktime(ns); 1233 } 1234 1235 static void 1236 fec_enet_tx_queue(struct net_device *ndev, u16 queue_id) 1237 { 1238 struct fec_enet_private *fep; 1239 struct bufdesc *bdp; 1240 unsigned short status; 1241 struct sk_buff *skb; 1242 struct fec_enet_priv_tx_q *txq; 1243 struct netdev_queue *nq; 1244 int index = 0; 1245 int entries_free; 1246 1247 fep = netdev_priv(ndev); 1248 1249 txq = fep->tx_queue[queue_id]; 1250 /* get next bdp of dirty_tx */ 1251 nq = netdev_get_tx_queue(ndev, queue_id); 1252 bdp = txq->dirty_tx; 1253 1254 /* get next bdp of dirty_tx */ 1255 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1256 1257 while (bdp != READ_ONCE(txq->bd.cur)) { 1258 /* Order the load of bd.cur and cbd_sc */ 1259 rmb(); 1260 status = fec16_to_cpu(READ_ONCE(bdp->cbd_sc)); 1261 if (status & BD_ENET_TX_READY) 1262 break; 1263 1264 index = fec_enet_get_bd_index(bdp, &txq->bd); 1265 1266 skb = txq->tx_skbuff[index]; 1267 txq->tx_skbuff[index] = NULL; 1268 if (!IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr))) 1269 dma_unmap_single(&fep->pdev->dev, 1270 fec32_to_cpu(bdp->cbd_bufaddr), 1271 fec16_to_cpu(bdp->cbd_datlen), 1272 DMA_TO_DEVICE); 1273 bdp->cbd_bufaddr = cpu_to_fec32(0); 1274 if (!skb) 1275 goto skb_done; 1276 1277 /* Check for errors. */ 1278 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | 1279 BD_ENET_TX_RL | BD_ENET_TX_UN | 1280 BD_ENET_TX_CSL)) { 1281 ndev->stats.tx_errors++; 1282 if (status & BD_ENET_TX_HB) /* No heartbeat */ 1283 ndev->stats.tx_heartbeat_errors++; 1284 if (status & BD_ENET_TX_LC) /* Late collision */ 1285 ndev->stats.tx_window_errors++; 1286 if (status & BD_ENET_TX_RL) /* Retrans limit */ 1287 ndev->stats.tx_aborted_errors++; 1288 if (status & BD_ENET_TX_UN) /* Underrun */ 1289 ndev->stats.tx_fifo_errors++; 1290 if (status & BD_ENET_TX_CSL) /* Carrier lost */ 1291 ndev->stats.tx_carrier_errors++; 1292 } else { 1293 ndev->stats.tx_packets++; 1294 ndev->stats.tx_bytes += skb->len; 1295 } 1296 1297 /* NOTE: SKBTX_IN_PROGRESS being set does not imply it's we who 1298 * are to time stamp the packet, so we still need to check time 1299 * stamping enabled flag. 1300 */ 1301 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS && 1302 fep->hwts_tx_en) && 1303 fep->bufdesc_ex) { 1304 struct skb_shared_hwtstamps shhwtstamps; 1305 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1306 1307 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), &shhwtstamps); 1308 skb_tstamp_tx(skb, &shhwtstamps); 1309 } 1310 1311 /* Deferred means some collisions occurred during transmit, 1312 * but we eventually sent the packet OK. 1313 */ 1314 if (status & BD_ENET_TX_DEF) 1315 ndev->stats.collisions++; 1316 1317 /* Free the sk buffer associated with this last transmit */ 1318 dev_kfree_skb_any(skb); 1319 skb_done: 1320 /* Make sure the update to bdp and tx_skbuff are performed 1321 * before dirty_tx 1322 */ 1323 wmb(); 1324 txq->dirty_tx = bdp; 1325 1326 /* Update pointer to next buffer descriptor to be transmitted */ 1327 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1328 1329 /* Since we have freed up a buffer, the ring is no longer full 1330 */ 1331 if (netif_tx_queue_stopped(nq)) { 1332 entries_free = fec_enet_get_free_txdesc_num(txq); 1333 if (entries_free >= txq->tx_wake_threshold) 1334 netif_tx_wake_queue(nq); 1335 } 1336 } 1337 1338 /* ERR006358: Keep the transmitter going */ 1339 if (bdp != txq->bd.cur && 1340 readl(txq->bd.reg_desc_active) == 0) 1341 writel(0, txq->bd.reg_desc_active); 1342 } 1343 1344 static void fec_enet_tx(struct net_device *ndev) 1345 { 1346 struct fec_enet_private *fep = netdev_priv(ndev); 1347 int i; 1348 1349 /* Make sure that AVB queues are processed first. */ 1350 for (i = fep->num_tx_queues - 1; i >= 0; i--) 1351 fec_enet_tx_queue(ndev, i); 1352 } 1353 1354 static int 1355 fec_enet_new_rxbdp(struct net_device *ndev, struct bufdesc *bdp, struct sk_buff *skb) 1356 { 1357 struct fec_enet_private *fep = netdev_priv(ndev); 1358 int off; 1359 1360 off = ((unsigned long)skb->data) & fep->rx_align; 1361 if (off) 1362 skb_reserve(skb, fep->rx_align + 1 - off); 1363 1364 bdp->cbd_bufaddr = cpu_to_fec32(dma_map_single(&fep->pdev->dev, skb->data, FEC_ENET_RX_FRSIZE - fep->rx_align, DMA_FROM_DEVICE)); 1365 if (dma_mapping_error(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr))) { 1366 if (net_ratelimit()) 1367 netdev_err(ndev, "Rx DMA memory map failed\n"); 1368 return -ENOMEM; 1369 } 1370 1371 return 0; 1372 } 1373 1374 static bool fec_enet_copybreak(struct net_device *ndev, struct sk_buff **skb, 1375 struct bufdesc *bdp, u32 length, bool swap) 1376 { 1377 struct fec_enet_private *fep = netdev_priv(ndev); 1378 struct sk_buff *new_skb; 1379 1380 if (length > fep->rx_copybreak) 1381 return false; 1382 1383 new_skb = netdev_alloc_skb(ndev, length); 1384 if (!new_skb) 1385 return false; 1386 1387 dma_sync_single_for_cpu(&fep->pdev->dev, 1388 fec32_to_cpu(bdp->cbd_bufaddr), 1389 FEC_ENET_RX_FRSIZE - fep->rx_align, 1390 DMA_FROM_DEVICE); 1391 if (!swap) 1392 memcpy(new_skb->data, (*skb)->data, length); 1393 else 1394 swap_buffer2(new_skb->data, (*skb)->data, length); 1395 *skb = new_skb; 1396 1397 return true; 1398 } 1399 1400 /* During a receive, the bd_rx.cur points to the current incoming buffer. 1401 * When we update through the ring, if the next incoming buffer has 1402 * not been given to the system, we just set the empty indicator, 1403 * effectively tossing the packet. 1404 */ 1405 static int 1406 fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id) 1407 { 1408 struct fec_enet_private *fep = netdev_priv(ndev); 1409 struct fec_enet_priv_rx_q *rxq; 1410 struct bufdesc *bdp; 1411 unsigned short status; 1412 struct sk_buff *skb_new = NULL; 1413 struct sk_buff *skb; 1414 ushort pkt_len; 1415 __u8 *data; 1416 int pkt_received = 0; 1417 struct bufdesc_ex *ebdp = NULL; 1418 bool vlan_packet_rcvd = false; 1419 u16 vlan_tag; 1420 int index = 0; 1421 bool is_copybreak; 1422 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME; 1423 1424 #ifdef CONFIG_M532x 1425 flush_cache_all(); 1426 #endif 1427 rxq = fep->rx_queue[queue_id]; 1428 1429 /* First, grab all of the stats for the incoming packet. 1430 * These get messed up if we get called due to a busy condition. 1431 */ 1432 bdp = rxq->bd.cur; 1433 1434 while (!((status = fec16_to_cpu(bdp->cbd_sc)) & BD_ENET_RX_EMPTY)) { 1435 1436 if (pkt_received >= budget) 1437 break; 1438 pkt_received++; 1439 1440 writel(FEC_ENET_RXF, fep->hwp + FEC_IEVENT); 1441 1442 /* Check for errors. */ 1443 status ^= BD_ENET_RX_LAST; 1444 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | 1445 BD_ENET_RX_CR | BD_ENET_RX_OV | BD_ENET_RX_LAST | 1446 BD_ENET_RX_CL)) { 1447 ndev->stats.rx_errors++; 1448 if (status & BD_ENET_RX_OV) { 1449 /* FIFO overrun */ 1450 ndev->stats.rx_fifo_errors++; 1451 goto rx_processing_done; 1452 } 1453 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH 1454 | BD_ENET_RX_LAST)) { 1455 /* Frame too long or too short. */ 1456 ndev->stats.rx_length_errors++; 1457 if (status & BD_ENET_RX_LAST) 1458 netdev_err(ndev, "rcv is not +last\n"); 1459 } 1460 if (status & BD_ENET_RX_CR) /* CRC Error */ 1461 ndev->stats.rx_crc_errors++; 1462 /* Report late collisions as a frame error. */ 1463 if (status & (BD_ENET_RX_NO | BD_ENET_RX_CL)) 1464 ndev->stats.rx_frame_errors++; 1465 goto rx_processing_done; 1466 } 1467 1468 /* Process the incoming frame. */ 1469 ndev->stats.rx_packets++; 1470 pkt_len = fec16_to_cpu(bdp->cbd_datlen); 1471 ndev->stats.rx_bytes += pkt_len; 1472 1473 index = fec_enet_get_bd_index(bdp, &rxq->bd); 1474 skb = rxq->rx_skbuff[index]; 1475 1476 /* The packet length includes FCS, but we don't want to 1477 * include that when passing upstream as it messes up 1478 * bridging applications. 1479 */ 1480 is_copybreak = fec_enet_copybreak(ndev, &skb, bdp, pkt_len - 4, 1481 need_swap); 1482 if (!is_copybreak) { 1483 skb_new = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE); 1484 if (unlikely(!skb_new)) { 1485 ndev->stats.rx_dropped++; 1486 goto rx_processing_done; 1487 } 1488 dma_unmap_single(&fep->pdev->dev, 1489 fec32_to_cpu(bdp->cbd_bufaddr), 1490 FEC_ENET_RX_FRSIZE - fep->rx_align, 1491 DMA_FROM_DEVICE); 1492 } 1493 1494 prefetch(skb->data - NET_IP_ALIGN); 1495 skb_put(skb, pkt_len - 4); 1496 data = skb->data; 1497 1498 if (!is_copybreak && need_swap) 1499 swap_buffer(data, pkt_len); 1500 1501 #if !defined(CONFIG_M5272) 1502 if (fep->quirks & FEC_QUIRK_HAS_RACC) 1503 data = skb_pull_inline(skb, 2); 1504 #endif 1505 1506 /* Extract the enhanced buffer descriptor */ 1507 ebdp = NULL; 1508 if (fep->bufdesc_ex) 1509 ebdp = (struct bufdesc_ex *)bdp; 1510 1511 /* If this is a VLAN packet remove the VLAN Tag */ 1512 vlan_packet_rcvd = false; 1513 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) && 1514 fep->bufdesc_ex && 1515 (ebdp->cbd_esc & cpu_to_fec32(BD_ENET_RX_VLAN))) { 1516 /* Push and remove the vlan tag */ 1517 struct vlan_hdr *vlan_header = 1518 (struct vlan_hdr *) (data + ETH_HLEN); 1519 vlan_tag = ntohs(vlan_header->h_vlan_TCI); 1520 1521 vlan_packet_rcvd = true; 1522 1523 memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2); 1524 skb_pull(skb, VLAN_HLEN); 1525 } 1526 1527 skb->protocol = eth_type_trans(skb, ndev); 1528 1529 /* Get receive timestamp from the skb */ 1530 if (fep->hwts_rx_en && fep->bufdesc_ex) 1531 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), 1532 skb_hwtstamps(skb)); 1533 1534 if (fep->bufdesc_ex && 1535 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) { 1536 if (!(ebdp->cbd_esc & cpu_to_fec32(FLAG_RX_CSUM_ERROR))) { 1537 /* don't check it */ 1538 skb->ip_summed = CHECKSUM_UNNECESSARY; 1539 } else { 1540 skb_checksum_none_assert(skb); 1541 } 1542 } 1543 1544 /* Handle received VLAN packets */ 1545 if (vlan_packet_rcvd) 1546 __vlan_hwaccel_put_tag(skb, 1547 htons(ETH_P_8021Q), 1548 vlan_tag); 1549 1550 skb_record_rx_queue(skb, queue_id); 1551 napi_gro_receive(&fep->napi, skb); 1552 1553 if (is_copybreak) { 1554 dma_sync_single_for_device(&fep->pdev->dev, 1555 fec32_to_cpu(bdp->cbd_bufaddr), 1556 FEC_ENET_RX_FRSIZE - fep->rx_align, 1557 DMA_FROM_DEVICE); 1558 } else { 1559 rxq->rx_skbuff[index] = skb_new; 1560 fec_enet_new_rxbdp(ndev, bdp, skb_new); 1561 } 1562 1563 rx_processing_done: 1564 /* Clear the status flags for this buffer */ 1565 status &= ~BD_ENET_RX_STATS; 1566 1567 /* Mark the buffer empty */ 1568 status |= BD_ENET_RX_EMPTY; 1569 1570 if (fep->bufdesc_ex) { 1571 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1572 1573 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); 1574 ebdp->cbd_prot = 0; 1575 ebdp->cbd_bdu = 0; 1576 } 1577 /* Make sure the updates to rest of the descriptor are 1578 * performed before transferring ownership. 1579 */ 1580 wmb(); 1581 bdp->cbd_sc = cpu_to_fec16(status); 1582 1583 /* Update BD pointer to next entry */ 1584 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 1585 1586 /* Doing this here will keep the FEC running while we process 1587 * incoming frames. On a heavily loaded network, we should be 1588 * able to keep up at the expense of system resources. 1589 */ 1590 writel(0, rxq->bd.reg_desc_active); 1591 } 1592 rxq->bd.cur = bdp; 1593 return pkt_received; 1594 } 1595 1596 static int fec_enet_rx(struct net_device *ndev, int budget) 1597 { 1598 struct fec_enet_private *fep = netdev_priv(ndev); 1599 int i, done = 0; 1600 1601 /* Make sure that AVB queues are processed first. */ 1602 for (i = fep->num_rx_queues - 1; i >= 0; i--) 1603 done += fec_enet_rx_queue(ndev, budget - done, i); 1604 1605 return done; 1606 } 1607 1608 static bool fec_enet_collect_events(struct fec_enet_private *fep) 1609 { 1610 uint int_events; 1611 1612 int_events = readl(fep->hwp + FEC_IEVENT); 1613 1614 /* Don't clear MDIO events, we poll for those */ 1615 int_events &= ~FEC_ENET_MII; 1616 1617 writel(int_events, fep->hwp + FEC_IEVENT); 1618 1619 return int_events != 0; 1620 } 1621 1622 static irqreturn_t 1623 fec_enet_interrupt(int irq, void *dev_id) 1624 { 1625 struct net_device *ndev = dev_id; 1626 struct fec_enet_private *fep = netdev_priv(ndev); 1627 irqreturn_t ret = IRQ_NONE; 1628 1629 if (fec_enet_collect_events(fep) && fep->link) { 1630 ret = IRQ_HANDLED; 1631 1632 if (napi_schedule_prep(&fep->napi)) { 1633 /* Disable interrupts */ 1634 writel(0, fep->hwp + FEC_IMASK); 1635 __napi_schedule(&fep->napi); 1636 } 1637 } 1638 1639 return ret; 1640 } 1641 1642 static int fec_enet_rx_napi(struct napi_struct *napi, int budget) 1643 { 1644 struct net_device *ndev = napi->dev; 1645 struct fec_enet_private *fep = netdev_priv(ndev); 1646 int done = 0; 1647 1648 do { 1649 done += fec_enet_rx(ndev, budget - done); 1650 fec_enet_tx(ndev); 1651 } while ((done < budget) && fec_enet_collect_events(fep)); 1652 1653 if (done < budget) { 1654 napi_complete_done(napi, done); 1655 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1656 } 1657 1658 return done; 1659 } 1660 1661 /* ------------------------------------------------------------------------- */ 1662 static void fec_get_mac(struct net_device *ndev) 1663 { 1664 struct fec_enet_private *fep = netdev_priv(ndev); 1665 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev); 1666 unsigned char *iap, tmpaddr[ETH_ALEN]; 1667 1668 /* 1669 * try to get mac address in following order: 1670 * 1671 * 1) module parameter via kernel command line in form 1672 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0 1673 */ 1674 iap = macaddr; 1675 1676 /* 1677 * 2) from device tree data 1678 */ 1679 if (!is_valid_ether_addr(iap)) { 1680 struct device_node *np = fep->pdev->dev.of_node; 1681 if (np) { 1682 const char *mac = of_get_mac_address(np); 1683 if (!IS_ERR(mac)) 1684 iap = (unsigned char *) mac; 1685 } 1686 } 1687 1688 /* 1689 * 3) from flash or fuse (via platform data) 1690 */ 1691 if (!is_valid_ether_addr(iap)) { 1692 #ifdef CONFIG_M5272 1693 if (FEC_FLASHMAC) 1694 iap = (unsigned char *)FEC_FLASHMAC; 1695 #else 1696 if (pdata) 1697 iap = (unsigned char *)&pdata->mac; 1698 #endif 1699 } 1700 1701 /* 1702 * 4) FEC mac registers set by bootloader 1703 */ 1704 if (!is_valid_ether_addr(iap)) { 1705 *((__be32 *) &tmpaddr[0]) = 1706 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW)); 1707 *((__be16 *) &tmpaddr[4]) = 1708 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16); 1709 iap = &tmpaddr[0]; 1710 } 1711 1712 /* 1713 * 5) random mac address 1714 */ 1715 if (!is_valid_ether_addr(iap)) { 1716 /* Report it and use a random ethernet address instead */ 1717 dev_err(&fep->pdev->dev, "Invalid MAC address: %pM\n", iap); 1718 eth_hw_addr_random(ndev); 1719 dev_info(&fep->pdev->dev, "Using random MAC address: %pM\n", 1720 ndev->dev_addr); 1721 return; 1722 } 1723 1724 memcpy(ndev->dev_addr, iap, ETH_ALEN); 1725 1726 /* Adjust MAC if using macaddr */ 1727 if (iap == macaddr) 1728 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id; 1729 } 1730 1731 /* ------------------------------------------------------------------------- */ 1732 1733 /* 1734 * Phy section 1735 */ 1736 static void fec_enet_adjust_link(struct net_device *ndev) 1737 { 1738 struct fec_enet_private *fep = netdev_priv(ndev); 1739 struct phy_device *phy_dev = ndev->phydev; 1740 int status_change = 0; 1741 1742 /* 1743 * If the netdev is down, or is going down, we're not interested 1744 * in link state events, so just mark our idea of the link as down 1745 * and ignore the event. 1746 */ 1747 if (!netif_running(ndev) || !netif_device_present(ndev)) { 1748 fep->link = 0; 1749 } else if (phy_dev->link) { 1750 if (!fep->link) { 1751 fep->link = phy_dev->link; 1752 status_change = 1; 1753 } 1754 1755 if (fep->full_duplex != phy_dev->duplex) { 1756 fep->full_duplex = phy_dev->duplex; 1757 status_change = 1; 1758 } 1759 1760 if (phy_dev->speed != fep->speed) { 1761 fep->speed = phy_dev->speed; 1762 status_change = 1; 1763 } 1764 1765 /* if any of the above changed restart the FEC */ 1766 if (status_change) { 1767 napi_disable(&fep->napi); 1768 netif_tx_lock_bh(ndev); 1769 fec_restart(ndev); 1770 netif_tx_wake_all_queues(ndev); 1771 netif_tx_unlock_bh(ndev); 1772 napi_enable(&fep->napi); 1773 } 1774 } else { 1775 if (fep->link) { 1776 napi_disable(&fep->napi); 1777 netif_tx_lock_bh(ndev); 1778 fec_stop(ndev); 1779 netif_tx_unlock_bh(ndev); 1780 napi_enable(&fep->napi); 1781 fep->link = phy_dev->link; 1782 status_change = 1; 1783 } 1784 } 1785 1786 if (status_change) 1787 phy_print_status(phy_dev); 1788 } 1789 1790 static int fec_enet_mdio_wait(struct fec_enet_private *fep) 1791 { 1792 uint ievent; 1793 int ret; 1794 1795 ret = readl_poll_timeout_atomic(fep->hwp + FEC_IEVENT, ievent, 1796 ievent & FEC_ENET_MII, 2, 30000); 1797 1798 if (!ret) 1799 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); 1800 1801 return ret; 1802 } 1803 1804 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) 1805 { 1806 struct fec_enet_private *fep = bus->priv; 1807 struct device *dev = &fep->pdev->dev; 1808 int ret = 0, frame_start, frame_addr, frame_op; 1809 bool is_c45 = !!(regnum & MII_ADDR_C45); 1810 1811 ret = pm_runtime_get_sync(dev); 1812 if (ret < 0) 1813 return ret; 1814 1815 if (is_c45) { 1816 frame_start = FEC_MMFR_ST_C45; 1817 1818 /* write address */ 1819 frame_addr = (regnum >> 16); 1820 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE | 1821 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 1822 FEC_MMFR_TA | (regnum & 0xFFFF), 1823 fep->hwp + FEC_MII_DATA); 1824 1825 /* wait for end of transfer */ 1826 ret = fec_enet_mdio_wait(fep); 1827 if (ret) { 1828 netdev_err(fep->netdev, "MDIO address write timeout\n"); 1829 goto out; 1830 } 1831 1832 frame_op = FEC_MMFR_OP_READ_C45; 1833 1834 } else { 1835 /* C22 read */ 1836 frame_op = FEC_MMFR_OP_READ; 1837 frame_start = FEC_MMFR_ST; 1838 frame_addr = regnum; 1839 } 1840 1841 /* start a read op */ 1842 writel(frame_start | frame_op | 1843 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 1844 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); 1845 1846 /* wait for end of transfer */ 1847 ret = fec_enet_mdio_wait(fep); 1848 if (ret) { 1849 netdev_err(fep->netdev, "MDIO read timeout\n"); 1850 goto out; 1851 } 1852 1853 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); 1854 1855 out: 1856 pm_runtime_mark_last_busy(dev); 1857 pm_runtime_put_autosuspend(dev); 1858 1859 return ret; 1860 } 1861 1862 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, 1863 u16 value) 1864 { 1865 struct fec_enet_private *fep = bus->priv; 1866 struct device *dev = &fep->pdev->dev; 1867 int ret, frame_start, frame_addr; 1868 bool is_c45 = !!(regnum & MII_ADDR_C45); 1869 1870 ret = pm_runtime_get_sync(dev); 1871 if (ret < 0) 1872 return ret; 1873 else 1874 ret = 0; 1875 1876 if (is_c45) { 1877 frame_start = FEC_MMFR_ST_C45; 1878 1879 /* write address */ 1880 frame_addr = (regnum >> 16); 1881 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE | 1882 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 1883 FEC_MMFR_TA | (regnum & 0xFFFF), 1884 fep->hwp + FEC_MII_DATA); 1885 1886 /* wait for end of transfer */ 1887 ret = fec_enet_mdio_wait(fep); 1888 if (ret) { 1889 netdev_err(fep->netdev, "MDIO address write timeout\n"); 1890 goto out; 1891 } 1892 } else { 1893 /* C22 write */ 1894 frame_start = FEC_MMFR_ST; 1895 frame_addr = regnum; 1896 } 1897 1898 /* start a write op */ 1899 writel(frame_start | FEC_MMFR_OP_WRITE | 1900 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 1901 FEC_MMFR_TA | FEC_MMFR_DATA(value), 1902 fep->hwp + FEC_MII_DATA); 1903 1904 /* wait for end of transfer */ 1905 ret = fec_enet_mdio_wait(fep); 1906 if (ret) 1907 netdev_err(fep->netdev, "MDIO write timeout\n"); 1908 1909 out: 1910 pm_runtime_mark_last_busy(dev); 1911 pm_runtime_put_autosuspend(dev); 1912 1913 return ret; 1914 } 1915 1916 static int fec_enet_clk_enable(struct net_device *ndev, bool enable) 1917 { 1918 struct fec_enet_private *fep = netdev_priv(ndev); 1919 int ret; 1920 1921 if (enable) { 1922 ret = clk_prepare_enable(fep->clk_enet_out); 1923 if (ret) 1924 return ret; 1925 1926 if (fep->clk_ptp) { 1927 mutex_lock(&fep->ptp_clk_mutex); 1928 ret = clk_prepare_enable(fep->clk_ptp); 1929 if (ret) { 1930 mutex_unlock(&fep->ptp_clk_mutex); 1931 goto failed_clk_ptp; 1932 } else { 1933 fep->ptp_clk_on = true; 1934 } 1935 mutex_unlock(&fep->ptp_clk_mutex); 1936 } 1937 1938 ret = clk_prepare_enable(fep->clk_ref); 1939 if (ret) 1940 goto failed_clk_ref; 1941 1942 phy_reset_after_clk_enable(ndev->phydev); 1943 } else { 1944 clk_disable_unprepare(fep->clk_enet_out); 1945 if (fep->clk_ptp) { 1946 mutex_lock(&fep->ptp_clk_mutex); 1947 clk_disable_unprepare(fep->clk_ptp); 1948 fep->ptp_clk_on = false; 1949 mutex_unlock(&fep->ptp_clk_mutex); 1950 } 1951 clk_disable_unprepare(fep->clk_ref); 1952 } 1953 1954 return 0; 1955 1956 failed_clk_ref: 1957 if (fep->clk_ptp) { 1958 mutex_lock(&fep->ptp_clk_mutex); 1959 clk_disable_unprepare(fep->clk_ptp); 1960 fep->ptp_clk_on = false; 1961 mutex_unlock(&fep->ptp_clk_mutex); 1962 } 1963 failed_clk_ptp: 1964 if (fep->clk_enet_out) 1965 clk_disable_unprepare(fep->clk_enet_out); 1966 1967 return ret; 1968 } 1969 1970 static int fec_enet_mii_probe(struct net_device *ndev) 1971 { 1972 struct fec_enet_private *fep = netdev_priv(ndev); 1973 struct phy_device *phy_dev = NULL; 1974 char mdio_bus_id[MII_BUS_ID_SIZE]; 1975 char phy_name[MII_BUS_ID_SIZE + 3]; 1976 int phy_id; 1977 int dev_id = fep->dev_id; 1978 1979 if (fep->phy_node) { 1980 phy_dev = of_phy_connect(ndev, fep->phy_node, 1981 &fec_enet_adjust_link, 0, 1982 fep->phy_interface); 1983 if (!phy_dev) { 1984 netdev_err(ndev, "Unable to connect to phy\n"); 1985 return -ENODEV; 1986 } 1987 } else { 1988 /* check for attached phy */ 1989 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) { 1990 if (!mdiobus_is_registered_device(fep->mii_bus, phy_id)) 1991 continue; 1992 if (dev_id--) 1993 continue; 1994 strlcpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE); 1995 break; 1996 } 1997 1998 if (phy_id >= PHY_MAX_ADDR) { 1999 netdev_info(ndev, "no PHY, assuming direct connection to switch\n"); 2000 strlcpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); 2001 phy_id = 0; 2002 } 2003 2004 snprintf(phy_name, sizeof(phy_name), 2005 PHY_ID_FMT, mdio_bus_id, phy_id); 2006 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, 2007 fep->phy_interface); 2008 } 2009 2010 if (IS_ERR(phy_dev)) { 2011 netdev_err(ndev, "could not attach to PHY\n"); 2012 return PTR_ERR(phy_dev); 2013 } 2014 2015 /* mask with MAC supported features */ 2016 if (fep->quirks & FEC_QUIRK_HAS_GBIT) { 2017 phy_set_max_speed(phy_dev, 1000); 2018 phy_remove_link_mode(phy_dev, 2019 ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 2020 #if !defined(CONFIG_M5272) 2021 phy_support_sym_pause(phy_dev); 2022 #endif 2023 } 2024 else 2025 phy_set_max_speed(phy_dev, 100); 2026 2027 fep->link = 0; 2028 fep->full_duplex = 0; 2029 2030 phy_attached_info(phy_dev); 2031 2032 return 0; 2033 } 2034 2035 static int fec_enet_mii_init(struct platform_device *pdev) 2036 { 2037 static struct mii_bus *fec0_mii_bus; 2038 struct net_device *ndev = platform_get_drvdata(pdev); 2039 struct fec_enet_private *fep = netdev_priv(ndev); 2040 bool suppress_preamble = false; 2041 struct device_node *node; 2042 int err = -ENXIO; 2043 u32 mii_speed, holdtime; 2044 u32 bus_freq; 2045 2046 /* 2047 * The i.MX28 dual fec interfaces are not equal. 2048 * Here are the differences: 2049 * 2050 * - fec0 supports MII & RMII modes while fec1 only supports RMII 2051 * - fec0 acts as the 1588 time master while fec1 is slave 2052 * - external phys can only be configured by fec0 2053 * 2054 * That is to say fec1 can not work independently. It only works 2055 * when fec0 is working. The reason behind this design is that the 2056 * second interface is added primarily for Switch mode. 2057 * 2058 * Because of the last point above, both phys are attached on fec0 2059 * mdio interface in board design, and need to be configured by 2060 * fec0 mii_bus. 2061 */ 2062 if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) { 2063 /* fec1 uses fec0 mii_bus */ 2064 if (mii_cnt && fec0_mii_bus) { 2065 fep->mii_bus = fec0_mii_bus; 2066 mii_cnt++; 2067 return 0; 2068 } 2069 return -ENOENT; 2070 } 2071 2072 bus_freq = 2500000; /* 2.5MHz by default */ 2073 node = of_get_child_by_name(pdev->dev.of_node, "mdio"); 2074 if (node) { 2075 of_property_read_u32(node, "clock-frequency", &bus_freq); 2076 suppress_preamble = of_property_read_bool(node, 2077 "suppress-preamble"); 2078 } 2079 2080 /* 2081 * Set MII speed (= clk_get_rate() / 2 * phy_speed) 2082 * 2083 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while 2084 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28 2085 * Reference Manual has an error on this, and gets fixed on i.MX6Q 2086 * document. 2087 */ 2088 mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), bus_freq * 2); 2089 if (fep->quirks & FEC_QUIRK_ENET_MAC) 2090 mii_speed--; 2091 if (mii_speed > 63) { 2092 dev_err(&pdev->dev, 2093 "fec clock (%lu) too fast to get right mii speed\n", 2094 clk_get_rate(fep->clk_ipg)); 2095 err = -EINVAL; 2096 goto err_out; 2097 } 2098 2099 /* 2100 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka 2101 * MII_SPEED) register that defines the MDIO output hold time. Earlier 2102 * versions are RAZ there, so just ignore the difference and write the 2103 * register always. 2104 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns. 2105 * HOLDTIME + 1 is the number of clk cycles the fec is holding the 2106 * output. 2107 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive). 2108 * Given that ceil(clkrate / 5000000) <= 64, the calculation for 2109 * holdtime cannot result in a value greater than 3. 2110 */ 2111 holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1; 2112 2113 fep->phy_speed = mii_speed << 1 | holdtime << 8; 2114 2115 if (suppress_preamble) 2116 fep->phy_speed |= BIT(7); 2117 2118 /* Clear MMFR to avoid to generate MII event by writing MSCR. 2119 * MII event generation condition: 2120 * - writing MSCR: 2121 * - mmfr[31:0]_not_zero & mscr[7:0]_is_zero & 2122 * mscr_reg_data_in[7:0] != 0 2123 * - writing MMFR: 2124 * - mscr[7:0]_not_zero 2125 */ 2126 writel(0, fep->hwp + FEC_MII_DATA); 2127 2128 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 2129 2130 /* Clear any pending transaction complete indication */ 2131 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); 2132 2133 fep->mii_bus = mdiobus_alloc(); 2134 if (fep->mii_bus == NULL) { 2135 err = -ENOMEM; 2136 goto err_out; 2137 } 2138 2139 fep->mii_bus->name = "fec_enet_mii_bus"; 2140 fep->mii_bus->read = fec_enet_mdio_read; 2141 fep->mii_bus->write = fec_enet_mdio_write; 2142 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 2143 pdev->name, fep->dev_id + 1); 2144 fep->mii_bus->priv = fep; 2145 fep->mii_bus->parent = &pdev->dev; 2146 2147 err = of_mdiobus_register(fep->mii_bus, node); 2148 of_node_put(node); 2149 if (err) 2150 goto err_out_free_mdiobus; 2151 2152 mii_cnt++; 2153 2154 /* save fec0 mii_bus */ 2155 if (fep->quirks & FEC_QUIRK_SINGLE_MDIO) 2156 fec0_mii_bus = fep->mii_bus; 2157 2158 return 0; 2159 2160 err_out_free_mdiobus: 2161 mdiobus_free(fep->mii_bus); 2162 err_out: 2163 return err; 2164 } 2165 2166 static void fec_enet_mii_remove(struct fec_enet_private *fep) 2167 { 2168 if (--mii_cnt == 0) { 2169 mdiobus_unregister(fep->mii_bus); 2170 mdiobus_free(fep->mii_bus); 2171 } 2172 } 2173 2174 static void fec_enet_get_drvinfo(struct net_device *ndev, 2175 struct ethtool_drvinfo *info) 2176 { 2177 struct fec_enet_private *fep = netdev_priv(ndev); 2178 2179 strlcpy(info->driver, fep->pdev->dev.driver->name, 2180 sizeof(info->driver)); 2181 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info)); 2182 } 2183 2184 static int fec_enet_get_regs_len(struct net_device *ndev) 2185 { 2186 struct fec_enet_private *fep = netdev_priv(ndev); 2187 struct resource *r; 2188 int s = 0; 2189 2190 r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0); 2191 if (r) 2192 s = resource_size(r); 2193 2194 return s; 2195 } 2196 2197 /* List of registers that can be safety be read to dump them with ethtool */ 2198 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 2199 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \ 2200 defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST) 2201 static __u32 fec_enet_register_version = 2; 2202 static u32 fec_enet_register_offset[] = { 2203 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0, 2204 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL, 2205 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1, 2206 FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH, 2207 FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, 2208 FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1, 2209 FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2, 2210 FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0, 2211 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM, 2212 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2, 2213 FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1, 2214 FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME, 2215 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT, 2216 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG, 2217 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255, 2218 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047, 2219 RMON_T_P_GTE2048, RMON_T_OCTETS, 2220 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF, 2221 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE, 2222 IEEE_T_FDXFC, IEEE_T_OCTETS_OK, 2223 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN, 2224 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB, 2225 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255, 2226 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047, 2227 RMON_R_P_GTE2048, RMON_R_OCTETS, 2228 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR, 2229 IEEE_R_FDXFC, IEEE_R_OCTETS_OK 2230 }; 2231 #else 2232 static __u32 fec_enet_register_version = 1; 2233 static u32 fec_enet_register_offset[] = { 2234 FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0, 2235 FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0, 2236 FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED, 2237 FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL, 2238 FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, 2239 FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0, 2240 FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0, 2241 FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0, 2242 FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2 2243 }; 2244 #endif 2245 2246 static void fec_enet_get_regs(struct net_device *ndev, 2247 struct ethtool_regs *regs, void *regbuf) 2248 { 2249 struct fec_enet_private *fep = netdev_priv(ndev); 2250 u32 __iomem *theregs = (u32 __iomem *)fep->hwp; 2251 struct device *dev = &fep->pdev->dev; 2252 u32 *buf = (u32 *)regbuf; 2253 u32 i, off; 2254 int ret; 2255 2256 ret = pm_runtime_get_sync(dev); 2257 if (ret < 0) 2258 return; 2259 2260 regs->version = fec_enet_register_version; 2261 2262 memset(buf, 0, regs->len); 2263 2264 for (i = 0; i < ARRAY_SIZE(fec_enet_register_offset); i++) { 2265 off = fec_enet_register_offset[i]; 2266 2267 if ((off == FEC_R_BOUND || off == FEC_R_FSTART) && 2268 !(fep->quirks & FEC_QUIRK_HAS_FRREG)) 2269 continue; 2270 2271 off >>= 2; 2272 buf[off] = readl(&theregs[off]); 2273 } 2274 2275 pm_runtime_mark_last_busy(dev); 2276 pm_runtime_put_autosuspend(dev); 2277 } 2278 2279 static int fec_enet_get_ts_info(struct net_device *ndev, 2280 struct ethtool_ts_info *info) 2281 { 2282 struct fec_enet_private *fep = netdev_priv(ndev); 2283 2284 if (fep->bufdesc_ex) { 2285 2286 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 2287 SOF_TIMESTAMPING_RX_SOFTWARE | 2288 SOF_TIMESTAMPING_SOFTWARE | 2289 SOF_TIMESTAMPING_TX_HARDWARE | 2290 SOF_TIMESTAMPING_RX_HARDWARE | 2291 SOF_TIMESTAMPING_RAW_HARDWARE; 2292 if (fep->ptp_clock) 2293 info->phc_index = ptp_clock_index(fep->ptp_clock); 2294 else 2295 info->phc_index = -1; 2296 2297 info->tx_types = (1 << HWTSTAMP_TX_OFF) | 2298 (1 << HWTSTAMP_TX_ON); 2299 2300 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 2301 (1 << HWTSTAMP_FILTER_ALL); 2302 return 0; 2303 } else { 2304 return ethtool_op_get_ts_info(ndev, info); 2305 } 2306 } 2307 2308 #if !defined(CONFIG_M5272) 2309 2310 static void fec_enet_get_pauseparam(struct net_device *ndev, 2311 struct ethtool_pauseparam *pause) 2312 { 2313 struct fec_enet_private *fep = netdev_priv(ndev); 2314 2315 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0; 2316 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0; 2317 pause->rx_pause = pause->tx_pause; 2318 } 2319 2320 static int fec_enet_set_pauseparam(struct net_device *ndev, 2321 struct ethtool_pauseparam *pause) 2322 { 2323 struct fec_enet_private *fep = netdev_priv(ndev); 2324 2325 if (!ndev->phydev) 2326 return -ENODEV; 2327 2328 if (pause->tx_pause != pause->rx_pause) { 2329 netdev_info(ndev, 2330 "hardware only support enable/disable both tx and rx"); 2331 return -EINVAL; 2332 } 2333 2334 fep->pause_flag = 0; 2335 2336 /* tx pause must be same as rx pause */ 2337 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0; 2338 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0; 2339 2340 phy_set_sym_pause(ndev->phydev, pause->rx_pause, pause->tx_pause, 2341 pause->autoneg); 2342 2343 if (pause->autoneg) { 2344 if (netif_running(ndev)) 2345 fec_stop(ndev); 2346 phy_start_aneg(ndev->phydev); 2347 } 2348 if (netif_running(ndev)) { 2349 napi_disable(&fep->napi); 2350 netif_tx_lock_bh(ndev); 2351 fec_restart(ndev); 2352 netif_tx_wake_all_queues(ndev); 2353 netif_tx_unlock_bh(ndev); 2354 napi_enable(&fep->napi); 2355 } 2356 2357 return 0; 2358 } 2359 2360 static const struct fec_stat { 2361 char name[ETH_GSTRING_LEN]; 2362 u16 offset; 2363 } fec_stats[] = { 2364 /* RMON TX */ 2365 { "tx_dropped", RMON_T_DROP }, 2366 { "tx_packets", RMON_T_PACKETS }, 2367 { "tx_broadcast", RMON_T_BC_PKT }, 2368 { "tx_multicast", RMON_T_MC_PKT }, 2369 { "tx_crc_errors", RMON_T_CRC_ALIGN }, 2370 { "tx_undersize", RMON_T_UNDERSIZE }, 2371 { "tx_oversize", RMON_T_OVERSIZE }, 2372 { "tx_fragment", RMON_T_FRAG }, 2373 { "tx_jabber", RMON_T_JAB }, 2374 { "tx_collision", RMON_T_COL }, 2375 { "tx_64byte", RMON_T_P64 }, 2376 { "tx_65to127byte", RMON_T_P65TO127 }, 2377 { "tx_128to255byte", RMON_T_P128TO255 }, 2378 { "tx_256to511byte", RMON_T_P256TO511 }, 2379 { "tx_512to1023byte", RMON_T_P512TO1023 }, 2380 { "tx_1024to2047byte", RMON_T_P1024TO2047 }, 2381 { "tx_GTE2048byte", RMON_T_P_GTE2048 }, 2382 { "tx_octets", RMON_T_OCTETS }, 2383 2384 /* IEEE TX */ 2385 { "IEEE_tx_drop", IEEE_T_DROP }, 2386 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK }, 2387 { "IEEE_tx_1col", IEEE_T_1COL }, 2388 { "IEEE_tx_mcol", IEEE_T_MCOL }, 2389 { "IEEE_tx_def", IEEE_T_DEF }, 2390 { "IEEE_tx_lcol", IEEE_T_LCOL }, 2391 { "IEEE_tx_excol", IEEE_T_EXCOL }, 2392 { "IEEE_tx_macerr", IEEE_T_MACERR }, 2393 { "IEEE_tx_cserr", IEEE_T_CSERR }, 2394 { "IEEE_tx_sqe", IEEE_T_SQE }, 2395 { "IEEE_tx_fdxfc", IEEE_T_FDXFC }, 2396 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK }, 2397 2398 /* RMON RX */ 2399 { "rx_packets", RMON_R_PACKETS }, 2400 { "rx_broadcast", RMON_R_BC_PKT }, 2401 { "rx_multicast", RMON_R_MC_PKT }, 2402 { "rx_crc_errors", RMON_R_CRC_ALIGN }, 2403 { "rx_undersize", RMON_R_UNDERSIZE }, 2404 { "rx_oversize", RMON_R_OVERSIZE }, 2405 { "rx_fragment", RMON_R_FRAG }, 2406 { "rx_jabber", RMON_R_JAB }, 2407 { "rx_64byte", RMON_R_P64 }, 2408 { "rx_65to127byte", RMON_R_P65TO127 }, 2409 { "rx_128to255byte", RMON_R_P128TO255 }, 2410 { "rx_256to511byte", RMON_R_P256TO511 }, 2411 { "rx_512to1023byte", RMON_R_P512TO1023 }, 2412 { "rx_1024to2047byte", RMON_R_P1024TO2047 }, 2413 { "rx_GTE2048byte", RMON_R_P_GTE2048 }, 2414 { "rx_octets", RMON_R_OCTETS }, 2415 2416 /* IEEE RX */ 2417 { "IEEE_rx_drop", IEEE_R_DROP }, 2418 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK }, 2419 { "IEEE_rx_crc", IEEE_R_CRC }, 2420 { "IEEE_rx_align", IEEE_R_ALIGN }, 2421 { "IEEE_rx_macerr", IEEE_R_MACERR }, 2422 { "IEEE_rx_fdxfc", IEEE_R_FDXFC }, 2423 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK }, 2424 }; 2425 2426 #define FEC_STATS_SIZE (ARRAY_SIZE(fec_stats) * sizeof(u64)) 2427 2428 static void fec_enet_update_ethtool_stats(struct net_device *dev) 2429 { 2430 struct fec_enet_private *fep = netdev_priv(dev); 2431 int i; 2432 2433 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2434 fep->ethtool_stats[i] = readl(fep->hwp + fec_stats[i].offset); 2435 } 2436 2437 static void fec_enet_get_ethtool_stats(struct net_device *dev, 2438 struct ethtool_stats *stats, u64 *data) 2439 { 2440 struct fec_enet_private *fep = netdev_priv(dev); 2441 2442 if (netif_running(dev)) 2443 fec_enet_update_ethtool_stats(dev); 2444 2445 memcpy(data, fep->ethtool_stats, FEC_STATS_SIZE); 2446 } 2447 2448 static void fec_enet_get_strings(struct net_device *netdev, 2449 u32 stringset, u8 *data) 2450 { 2451 int i; 2452 switch (stringset) { 2453 case ETH_SS_STATS: 2454 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2455 memcpy(data + i * ETH_GSTRING_LEN, 2456 fec_stats[i].name, ETH_GSTRING_LEN); 2457 break; 2458 } 2459 } 2460 2461 static int fec_enet_get_sset_count(struct net_device *dev, int sset) 2462 { 2463 switch (sset) { 2464 case ETH_SS_STATS: 2465 return ARRAY_SIZE(fec_stats); 2466 default: 2467 return -EOPNOTSUPP; 2468 } 2469 } 2470 2471 static void fec_enet_clear_ethtool_stats(struct net_device *dev) 2472 { 2473 struct fec_enet_private *fep = netdev_priv(dev); 2474 int i; 2475 2476 /* Disable MIB statistics counters */ 2477 writel(FEC_MIB_CTRLSTAT_DISABLE, fep->hwp + FEC_MIB_CTRLSTAT); 2478 2479 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2480 writel(0, fep->hwp + fec_stats[i].offset); 2481 2482 /* Don't disable MIB statistics counters */ 2483 writel(0, fep->hwp + FEC_MIB_CTRLSTAT); 2484 } 2485 2486 #else /* !defined(CONFIG_M5272) */ 2487 #define FEC_STATS_SIZE 0 2488 static inline void fec_enet_update_ethtool_stats(struct net_device *dev) 2489 { 2490 } 2491 2492 static inline void fec_enet_clear_ethtool_stats(struct net_device *dev) 2493 { 2494 } 2495 #endif /* !defined(CONFIG_M5272) */ 2496 2497 /* ITR clock source is enet system clock (clk_ahb). 2498 * TCTT unit is cycle_ns * 64 cycle 2499 * So, the ICTT value = X us / (cycle_ns * 64) 2500 */ 2501 static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us) 2502 { 2503 struct fec_enet_private *fep = netdev_priv(ndev); 2504 2505 return us * (fep->itr_clk_rate / 64000) / 1000; 2506 } 2507 2508 /* Set threshold for interrupt coalescing */ 2509 static void fec_enet_itr_coal_set(struct net_device *ndev) 2510 { 2511 struct fec_enet_private *fep = netdev_priv(ndev); 2512 int rx_itr, tx_itr; 2513 2514 /* Must be greater than zero to avoid unpredictable behavior */ 2515 if (!fep->rx_time_itr || !fep->rx_pkts_itr || 2516 !fep->tx_time_itr || !fep->tx_pkts_itr) 2517 return; 2518 2519 /* Select enet system clock as Interrupt Coalescing 2520 * timer Clock Source 2521 */ 2522 rx_itr = FEC_ITR_CLK_SEL; 2523 tx_itr = FEC_ITR_CLK_SEL; 2524 2525 /* set ICFT and ICTT */ 2526 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr); 2527 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr)); 2528 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr); 2529 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr)); 2530 2531 rx_itr |= FEC_ITR_EN; 2532 tx_itr |= FEC_ITR_EN; 2533 2534 writel(tx_itr, fep->hwp + FEC_TXIC0); 2535 writel(rx_itr, fep->hwp + FEC_RXIC0); 2536 if (fep->quirks & FEC_QUIRK_HAS_AVB) { 2537 writel(tx_itr, fep->hwp + FEC_TXIC1); 2538 writel(rx_itr, fep->hwp + FEC_RXIC1); 2539 writel(tx_itr, fep->hwp + FEC_TXIC2); 2540 writel(rx_itr, fep->hwp + FEC_RXIC2); 2541 } 2542 } 2543 2544 static int 2545 fec_enet_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec) 2546 { 2547 struct fec_enet_private *fep = netdev_priv(ndev); 2548 2549 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) 2550 return -EOPNOTSUPP; 2551 2552 ec->rx_coalesce_usecs = fep->rx_time_itr; 2553 ec->rx_max_coalesced_frames = fep->rx_pkts_itr; 2554 2555 ec->tx_coalesce_usecs = fep->tx_time_itr; 2556 ec->tx_max_coalesced_frames = fep->tx_pkts_itr; 2557 2558 return 0; 2559 } 2560 2561 static int 2562 fec_enet_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec) 2563 { 2564 struct fec_enet_private *fep = netdev_priv(ndev); 2565 struct device *dev = &fep->pdev->dev; 2566 unsigned int cycle; 2567 2568 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) 2569 return -EOPNOTSUPP; 2570 2571 if (ec->rx_max_coalesced_frames > 255) { 2572 dev_err(dev, "Rx coalesced frames exceed hardware limitation\n"); 2573 return -EINVAL; 2574 } 2575 2576 if (ec->tx_max_coalesced_frames > 255) { 2577 dev_err(dev, "Tx coalesced frame exceed hardware limitation\n"); 2578 return -EINVAL; 2579 } 2580 2581 cycle = fec_enet_us_to_itr_clock(ndev, ec->rx_coalesce_usecs); 2582 if (cycle > 0xFFFF) { 2583 dev_err(dev, "Rx coalesced usec exceed hardware limitation\n"); 2584 return -EINVAL; 2585 } 2586 2587 cycle = fec_enet_us_to_itr_clock(ndev, ec->tx_coalesce_usecs); 2588 if (cycle > 0xFFFF) { 2589 dev_err(dev, "Tx coalesced usec exceed hardware limitation\n"); 2590 return -EINVAL; 2591 } 2592 2593 fep->rx_time_itr = ec->rx_coalesce_usecs; 2594 fep->rx_pkts_itr = ec->rx_max_coalesced_frames; 2595 2596 fep->tx_time_itr = ec->tx_coalesce_usecs; 2597 fep->tx_pkts_itr = ec->tx_max_coalesced_frames; 2598 2599 fec_enet_itr_coal_set(ndev); 2600 2601 return 0; 2602 } 2603 2604 static void fec_enet_itr_coal_init(struct net_device *ndev) 2605 { 2606 struct ethtool_coalesce ec; 2607 2608 ec.rx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT; 2609 ec.rx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT; 2610 2611 ec.tx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT; 2612 ec.tx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT; 2613 2614 fec_enet_set_coalesce(ndev, &ec); 2615 } 2616 2617 static int fec_enet_get_tunable(struct net_device *netdev, 2618 const struct ethtool_tunable *tuna, 2619 void *data) 2620 { 2621 struct fec_enet_private *fep = netdev_priv(netdev); 2622 int ret = 0; 2623 2624 switch (tuna->id) { 2625 case ETHTOOL_RX_COPYBREAK: 2626 *(u32 *)data = fep->rx_copybreak; 2627 break; 2628 default: 2629 ret = -EINVAL; 2630 break; 2631 } 2632 2633 return ret; 2634 } 2635 2636 static int fec_enet_set_tunable(struct net_device *netdev, 2637 const struct ethtool_tunable *tuna, 2638 const void *data) 2639 { 2640 struct fec_enet_private *fep = netdev_priv(netdev); 2641 int ret = 0; 2642 2643 switch (tuna->id) { 2644 case ETHTOOL_RX_COPYBREAK: 2645 fep->rx_copybreak = *(u32 *)data; 2646 break; 2647 default: 2648 ret = -EINVAL; 2649 break; 2650 } 2651 2652 return ret; 2653 } 2654 2655 static void 2656 fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2657 { 2658 struct fec_enet_private *fep = netdev_priv(ndev); 2659 2660 if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) { 2661 wol->supported = WAKE_MAGIC; 2662 wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0; 2663 } else { 2664 wol->supported = wol->wolopts = 0; 2665 } 2666 } 2667 2668 static int 2669 fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2670 { 2671 struct fec_enet_private *fep = netdev_priv(ndev); 2672 2673 if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET)) 2674 return -EINVAL; 2675 2676 if (wol->wolopts & ~WAKE_MAGIC) 2677 return -EINVAL; 2678 2679 device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC); 2680 if (device_may_wakeup(&ndev->dev)) { 2681 fep->wol_flag |= FEC_WOL_FLAG_ENABLE; 2682 if (fep->irq[0] > 0) 2683 enable_irq_wake(fep->irq[0]); 2684 } else { 2685 fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE); 2686 if (fep->irq[0] > 0) 2687 disable_irq_wake(fep->irq[0]); 2688 } 2689 2690 return 0; 2691 } 2692 2693 static const struct ethtool_ops fec_enet_ethtool_ops = { 2694 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 2695 ETHTOOL_COALESCE_MAX_FRAMES, 2696 .get_drvinfo = fec_enet_get_drvinfo, 2697 .get_regs_len = fec_enet_get_regs_len, 2698 .get_regs = fec_enet_get_regs, 2699 .nway_reset = phy_ethtool_nway_reset, 2700 .get_link = ethtool_op_get_link, 2701 .get_coalesce = fec_enet_get_coalesce, 2702 .set_coalesce = fec_enet_set_coalesce, 2703 #ifndef CONFIG_M5272 2704 .get_pauseparam = fec_enet_get_pauseparam, 2705 .set_pauseparam = fec_enet_set_pauseparam, 2706 .get_strings = fec_enet_get_strings, 2707 .get_ethtool_stats = fec_enet_get_ethtool_stats, 2708 .get_sset_count = fec_enet_get_sset_count, 2709 #endif 2710 .get_ts_info = fec_enet_get_ts_info, 2711 .get_tunable = fec_enet_get_tunable, 2712 .set_tunable = fec_enet_set_tunable, 2713 .get_wol = fec_enet_get_wol, 2714 .set_wol = fec_enet_set_wol, 2715 .get_link_ksettings = phy_ethtool_get_link_ksettings, 2716 .set_link_ksettings = phy_ethtool_set_link_ksettings, 2717 }; 2718 2719 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) 2720 { 2721 struct fec_enet_private *fep = netdev_priv(ndev); 2722 struct phy_device *phydev = ndev->phydev; 2723 2724 if (!netif_running(ndev)) 2725 return -EINVAL; 2726 2727 if (!phydev) 2728 return -ENODEV; 2729 2730 if (fep->bufdesc_ex) { 2731 bool use_fec_hwts = !phy_has_hwtstamp(phydev); 2732 2733 if (cmd == SIOCSHWTSTAMP) { 2734 if (use_fec_hwts) 2735 return fec_ptp_set(ndev, rq); 2736 fec_ptp_disable_hwts(ndev); 2737 } else if (cmd == SIOCGHWTSTAMP) { 2738 if (use_fec_hwts) 2739 return fec_ptp_get(ndev, rq); 2740 } 2741 } 2742 2743 return phy_mii_ioctl(phydev, rq, cmd); 2744 } 2745 2746 static void fec_enet_free_buffers(struct net_device *ndev) 2747 { 2748 struct fec_enet_private *fep = netdev_priv(ndev); 2749 unsigned int i; 2750 struct sk_buff *skb; 2751 struct bufdesc *bdp; 2752 struct fec_enet_priv_tx_q *txq; 2753 struct fec_enet_priv_rx_q *rxq; 2754 unsigned int q; 2755 2756 for (q = 0; q < fep->num_rx_queues; q++) { 2757 rxq = fep->rx_queue[q]; 2758 bdp = rxq->bd.base; 2759 for (i = 0; i < rxq->bd.ring_size; i++) { 2760 skb = rxq->rx_skbuff[i]; 2761 rxq->rx_skbuff[i] = NULL; 2762 if (skb) { 2763 dma_unmap_single(&fep->pdev->dev, 2764 fec32_to_cpu(bdp->cbd_bufaddr), 2765 FEC_ENET_RX_FRSIZE - fep->rx_align, 2766 DMA_FROM_DEVICE); 2767 dev_kfree_skb(skb); 2768 } 2769 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 2770 } 2771 } 2772 2773 for (q = 0; q < fep->num_tx_queues; q++) { 2774 txq = fep->tx_queue[q]; 2775 for (i = 0; i < txq->bd.ring_size; i++) { 2776 kfree(txq->tx_bounce[i]); 2777 txq->tx_bounce[i] = NULL; 2778 skb = txq->tx_skbuff[i]; 2779 txq->tx_skbuff[i] = NULL; 2780 dev_kfree_skb(skb); 2781 } 2782 } 2783 } 2784 2785 static void fec_enet_free_queue(struct net_device *ndev) 2786 { 2787 struct fec_enet_private *fep = netdev_priv(ndev); 2788 int i; 2789 struct fec_enet_priv_tx_q *txq; 2790 2791 for (i = 0; i < fep->num_tx_queues; i++) 2792 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) { 2793 txq = fep->tx_queue[i]; 2794 dma_free_coherent(&fep->pdev->dev, 2795 txq->bd.ring_size * TSO_HEADER_SIZE, 2796 txq->tso_hdrs, 2797 txq->tso_hdrs_dma); 2798 } 2799 2800 for (i = 0; i < fep->num_rx_queues; i++) 2801 kfree(fep->rx_queue[i]); 2802 for (i = 0; i < fep->num_tx_queues; i++) 2803 kfree(fep->tx_queue[i]); 2804 } 2805 2806 static int fec_enet_alloc_queue(struct net_device *ndev) 2807 { 2808 struct fec_enet_private *fep = netdev_priv(ndev); 2809 int i; 2810 int ret = 0; 2811 struct fec_enet_priv_tx_q *txq; 2812 2813 for (i = 0; i < fep->num_tx_queues; i++) { 2814 txq = kzalloc(sizeof(*txq), GFP_KERNEL); 2815 if (!txq) { 2816 ret = -ENOMEM; 2817 goto alloc_failed; 2818 } 2819 2820 fep->tx_queue[i] = txq; 2821 txq->bd.ring_size = TX_RING_SIZE; 2822 fep->total_tx_ring_size += fep->tx_queue[i]->bd.ring_size; 2823 2824 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS; 2825 txq->tx_wake_threshold = 2826 (txq->bd.ring_size - txq->tx_stop_threshold) / 2; 2827 2828 txq->tso_hdrs = dma_alloc_coherent(&fep->pdev->dev, 2829 txq->bd.ring_size * TSO_HEADER_SIZE, 2830 &txq->tso_hdrs_dma, 2831 GFP_KERNEL); 2832 if (!txq->tso_hdrs) { 2833 ret = -ENOMEM; 2834 goto alloc_failed; 2835 } 2836 } 2837 2838 for (i = 0; i < fep->num_rx_queues; i++) { 2839 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]), 2840 GFP_KERNEL); 2841 if (!fep->rx_queue[i]) { 2842 ret = -ENOMEM; 2843 goto alloc_failed; 2844 } 2845 2846 fep->rx_queue[i]->bd.ring_size = RX_RING_SIZE; 2847 fep->total_rx_ring_size += fep->rx_queue[i]->bd.ring_size; 2848 } 2849 return ret; 2850 2851 alloc_failed: 2852 fec_enet_free_queue(ndev); 2853 return ret; 2854 } 2855 2856 static int 2857 fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue) 2858 { 2859 struct fec_enet_private *fep = netdev_priv(ndev); 2860 unsigned int i; 2861 struct sk_buff *skb; 2862 struct bufdesc *bdp; 2863 struct fec_enet_priv_rx_q *rxq; 2864 2865 rxq = fep->rx_queue[queue]; 2866 bdp = rxq->bd.base; 2867 for (i = 0; i < rxq->bd.ring_size; i++) { 2868 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE); 2869 if (!skb) 2870 goto err_alloc; 2871 2872 if (fec_enet_new_rxbdp(ndev, bdp, skb)) { 2873 dev_kfree_skb(skb); 2874 goto err_alloc; 2875 } 2876 2877 rxq->rx_skbuff[i] = skb; 2878 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); 2879 2880 if (fep->bufdesc_ex) { 2881 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 2882 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); 2883 } 2884 2885 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 2886 } 2887 2888 /* Set the last buffer to wrap. */ 2889 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); 2890 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 2891 return 0; 2892 2893 err_alloc: 2894 fec_enet_free_buffers(ndev); 2895 return -ENOMEM; 2896 } 2897 2898 static int 2899 fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue) 2900 { 2901 struct fec_enet_private *fep = netdev_priv(ndev); 2902 unsigned int i; 2903 struct bufdesc *bdp; 2904 struct fec_enet_priv_tx_q *txq; 2905 2906 txq = fep->tx_queue[queue]; 2907 bdp = txq->bd.base; 2908 for (i = 0; i < txq->bd.ring_size; i++) { 2909 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); 2910 if (!txq->tx_bounce[i]) 2911 goto err_alloc; 2912 2913 bdp->cbd_sc = cpu_to_fec16(0); 2914 bdp->cbd_bufaddr = cpu_to_fec32(0); 2915 2916 if (fep->bufdesc_ex) { 2917 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 2918 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_TX_INT); 2919 } 2920 2921 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 2922 } 2923 2924 /* Set the last buffer to wrap. */ 2925 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); 2926 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 2927 2928 return 0; 2929 2930 err_alloc: 2931 fec_enet_free_buffers(ndev); 2932 return -ENOMEM; 2933 } 2934 2935 static int fec_enet_alloc_buffers(struct net_device *ndev) 2936 { 2937 struct fec_enet_private *fep = netdev_priv(ndev); 2938 unsigned int i; 2939 2940 for (i = 0; i < fep->num_rx_queues; i++) 2941 if (fec_enet_alloc_rxq_buffers(ndev, i)) 2942 return -ENOMEM; 2943 2944 for (i = 0; i < fep->num_tx_queues; i++) 2945 if (fec_enet_alloc_txq_buffers(ndev, i)) 2946 return -ENOMEM; 2947 return 0; 2948 } 2949 2950 static int 2951 fec_enet_open(struct net_device *ndev) 2952 { 2953 struct fec_enet_private *fep = netdev_priv(ndev); 2954 int ret; 2955 bool reset_again; 2956 2957 ret = pm_runtime_get_sync(&fep->pdev->dev); 2958 if (ret < 0) 2959 return ret; 2960 2961 pinctrl_pm_select_default_state(&fep->pdev->dev); 2962 ret = fec_enet_clk_enable(ndev, true); 2963 if (ret) 2964 goto clk_enable; 2965 2966 /* During the first fec_enet_open call the PHY isn't probed at this 2967 * point. Therefore the phy_reset_after_clk_enable() call within 2968 * fec_enet_clk_enable() fails. As we need this reset in order to be 2969 * sure the PHY is working correctly we check if we need to reset again 2970 * later when the PHY is probed 2971 */ 2972 if (ndev->phydev && ndev->phydev->drv) 2973 reset_again = false; 2974 else 2975 reset_again = true; 2976 2977 /* I should reset the ring buffers here, but I don't yet know 2978 * a simple way to do that. 2979 */ 2980 2981 ret = fec_enet_alloc_buffers(ndev); 2982 if (ret) 2983 goto err_enet_alloc; 2984 2985 /* Init MAC prior to mii bus probe */ 2986 fec_restart(ndev); 2987 2988 /* Probe and connect to PHY when open the interface */ 2989 ret = fec_enet_mii_probe(ndev); 2990 if (ret) 2991 goto err_enet_mii_probe; 2992 2993 /* Call phy_reset_after_clk_enable() again if it failed during 2994 * phy_reset_after_clk_enable() before because the PHY wasn't probed. 2995 */ 2996 if (reset_again) 2997 phy_reset_after_clk_enable(ndev->phydev); 2998 2999 if (fep->quirks & FEC_QUIRK_ERR006687) 3000 imx6q_cpuidle_fec_irqs_used(); 3001 3002 napi_enable(&fep->napi); 3003 phy_start(ndev->phydev); 3004 netif_tx_start_all_queues(ndev); 3005 3006 device_set_wakeup_enable(&ndev->dev, fep->wol_flag & 3007 FEC_WOL_FLAG_ENABLE); 3008 3009 return 0; 3010 3011 err_enet_mii_probe: 3012 fec_enet_free_buffers(ndev); 3013 err_enet_alloc: 3014 fec_enet_clk_enable(ndev, false); 3015 clk_enable: 3016 pm_runtime_mark_last_busy(&fep->pdev->dev); 3017 pm_runtime_put_autosuspend(&fep->pdev->dev); 3018 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3019 return ret; 3020 } 3021 3022 static int 3023 fec_enet_close(struct net_device *ndev) 3024 { 3025 struct fec_enet_private *fep = netdev_priv(ndev); 3026 3027 phy_stop(ndev->phydev); 3028 3029 if (netif_device_present(ndev)) { 3030 napi_disable(&fep->napi); 3031 netif_tx_disable(ndev); 3032 fec_stop(ndev); 3033 } 3034 3035 phy_disconnect(ndev->phydev); 3036 3037 if (fep->quirks & FEC_QUIRK_ERR006687) 3038 imx6q_cpuidle_fec_irqs_unused(); 3039 3040 fec_enet_update_ethtool_stats(ndev); 3041 3042 fec_enet_clk_enable(ndev, false); 3043 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3044 pm_runtime_mark_last_busy(&fep->pdev->dev); 3045 pm_runtime_put_autosuspend(&fep->pdev->dev); 3046 3047 fec_enet_free_buffers(ndev); 3048 3049 return 0; 3050 } 3051 3052 /* Set or clear the multicast filter for this adaptor. 3053 * Skeleton taken from sunlance driver. 3054 * The CPM Ethernet implementation allows Multicast as well as individual 3055 * MAC address filtering. Some of the drivers check to make sure it is 3056 * a group multicast address, and discard those that are not. I guess I 3057 * will do the same for now, but just remove the test if you want 3058 * individual filtering as well (do the upper net layers want or support 3059 * this kind of feature?). 3060 */ 3061 3062 #define FEC_HASH_BITS 6 /* #bits in hash */ 3063 3064 static void set_multicast_list(struct net_device *ndev) 3065 { 3066 struct fec_enet_private *fep = netdev_priv(ndev); 3067 struct netdev_hw_addr *ha; 3068 unsigned int crc, tmp; 3069 unsigned char hash; 3070 unsigned int hash_high = 0, hash_low = 0; 3071 3072 if (ndev->flags & IFF_PROMISC) { 3073 tmp = readl(fep->hwp + FEC_R_CNTRL); 3074 tmp |= 0x8; 3075 writel(tmp, fep->hwp + FEC_R_CNTRL); 3076 return; 3077 } 3078 3079 tmp = readl(fep->hwp + FEC_R_CNTRL); 3080 tmp &= ~0x8; 3081 writel(tmp, fep->hwp + FEC_R_CNTRL); 3082 3083 if (ndev->flags & IFF_ALLMULTI) { 3084 /* Catch all multicast addresses, so set the 3085 * filter to all 1's 3086 */ 3087 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 3088 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 3089 3090 return; 3091 } 3092 3093 /* Add the addresses in hash register */ 3094 netdev_for_each_mc_addr(ha, ndev) { 3095 /* calculate crc32 value of mac address */ 3096 crc = ether_crc_le(ndev->addr_len, ha->addr); 3097 3098 /* only upper 6 bits (FEC_HASH_BITS) are used 3099 * which point to specific bit in the hash registers 3100 */ 3101 hash = (crc >> (32 - FEC_HASH_BITS)) & 0x3f; 3102 3103 if (hash > 31) 3104 hash_high |= 1 << (hash - 32); 3105 else 3106 hash_low |= 1 << hash; 3107 } 3108 3109 writel(hash_high, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 3110 writel(hash_low, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 3111 } 3112 3113 /* Set a MAC change in hardware. */ 3114 static int 3115 fec_set_mac_address(struct net_device *ndev, void *p) 3116 { 3117 struct fec_enet_private *fep = netdev_priv(ndev); 3118 struct sockaddr *addr = p; 3119 3120 if (addr) { 3121 if (!is_valid_ether_addr(addr->sa_data)) 3122 return -EADDRNOTAVAIL; 3123 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len); 3124 } 3125 3126 /* Add netif status check here to avoid system hang in below case: 3127 * ifconfig ethx down; ifconfig ethx hw ether xx:xx:xx:xx:xx:xx; 3128 * After ethx down, fec all clocks are gated off and then register 3129 * access causes system hang. 3130 */ 3131 if (!netif_running(ndev)) 3132 return 0; 3133 3134 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) | 3135 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24), 3136 fep->hwp + FEC_ADDR_LOW); 3137 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24), 3138 fep->hwp + FEC_ADDR_HIGH); 3139 return 0; 3140 } 3141 3142 #ifdef CONFIG_NET_POLL_CONTROLLER 3143 /** 3144 * fec_poll_controller - FEC Poll controller function 3145 * @dev: The FEC network adapter 3146 * 3147 * Polled functionality used by netconsole and others in non interrupt mode 3148 * 3149 */ 3150 static void fec_poll_controller(struct net_device *dev) 3151 { 3152 int i; 3153 struct fec_enet_private *fep = netdev_priv(dev); 3154 3155 for (i = 0; i < FEC_IRQ_NUM; i++) { 3156 if (fep->irq[i] > 0) { 3157 disable_irq(fep->irq[i]); 3158 fec_enet_interrupt(fep->irq[i], dev); 3159 enable_irq(fep->irq[i]); 3160 } 3161 } 3162 } 3163 #endif 3164 3165 static inline void fec_enet_set_netdev_features(struct net_device *netdev, 3166 netdev_features_t features) 3167 { 3168 struct fec_enet_private *fep = netdev_priv(netdev); 3169 netdev_features_t changed = features ^ netdev->features; 3170 3171 netdev->features = features; 3172 3173 /* Receive checksum has been changed */ 3174 if (changed & NETIF_F_RXCSUM) { 3175 if (features & NETIF_F_RXCSUM) 3176 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 3177 else 3178 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED; 3179 } 3180 } 3181 3182 static int fec_set_features(struct net_device *netdev, 3183 netdev_features_t features) 3184 { 3185 struct fec_enet_private *fep = netdev_priv(netdev); 3186 netdev_features_t changed = features ^ netdev->features; 3187 3188 if (netif_running(netdev) && changed & NETIF_F_RXCSUM) { 3189 napi_disable(&fep->napi); 3190 netif_tx_lock_bh(netdev); 3191 fec_stop(netdev); 3192 fec_enet_set_netdev_features(netdev, features); 3193 fec_restart(netdev); 3194 netif_tx_wake_all_queues(netdev); 3195 netif_tx_unlock_bh(netdev); 3196 napi_enable(&fep->napi); 3197 } else { 3198 fec_enet_set_netdev_features(netdev, features); 3199 } 3200 3201 return 0; 3202 } 3203 3204 static const struct net_device_ops fec_netdev_ops = { 3205 .ndo_open = fec_enet_open, 3206 .ndo_stop = fec_enet_close, 3207 .ndo_start_xmit = fec_enet_start_xmit, 3208 .ndo_set_rx_mode = set_multicast_list, 3209 .ndo_validate_addr = eth_validate_addr, 3210 .ndo_tx_timeout = fec_timeout, 3211 .ndo_set_mac_address = fec_set_mac_address, 3212 .ndo_do_ioctl = fec_enet_ioctl, 3213 #ifdef CONFIG_NET_POLL_CONTROLLER 3214 .ndo_poll_controller = fec_poll_controller, 3215 #endif 3216 .ndo_set_features = fec_set_features, 3217 }; 3218 3219 static const unsigned short offset_des_active_rxq[] = { 3220 FEC_R_DES_ACTIVE_0, FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2 3221 }; 3222 3223 static const unsigned short offset_des_active_txq[] = { 3224 FEC_X_DES_ACTIVE_0, FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2 3225 }; 3226 3227 /* 3228 * XXX: We need to clean up on failure exits here. 3229 * 3230 */ 3231 static int fec_enet_init(struct net_device *ndev) 3232 { 3233 struct fec_enet_private *fep = netdev_priv(ndev); 3234 struct bufdesc *cbd_base; 3235 dma_addr_t bd_dma; 3236 int bd_size; 3237 unsigned int i; 3238 unsigned dsize = fep->bufdesc_ex ? sizeof(struct bufdesc_ex) : 3239 sizeof(struct bufdesc); 3240 unsigned dsize_log2 = __fls(dsize); 3241 int ret; 3242 3243 WARN_ON(dsize != (1 << dsize_log2)); 3244 #if defined(CONFIG_ARM) || defined(CONFIG_ARM64) 3245 fep->rx_align = 0xf; 3246 fep->tx_align = 0xf; 3247 #else 3248 fep->rx_align = 0x3; 3249 fep->tx_align = 0x3; 3250 #endif 3251 3252 /* Check mask of the streaming and coherent API */ 3253 ret = dma_set_mask_and_coherent(&fep->pdev->dev, DMA_BIT_MASK(32)); 3254 if (ret < 0) { 3255 dev_warn(&fep->pdev->dev, "No suitable DMA available\n"); 3256 return ret; 3257 } 3258 3259 fec_enet_alloc_queue(ndev); 3260 3261 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) * dsize; 3262 3263 /* Allocate memory for buffer descriptors. */ 3264 cbd_base = dmam_alloc_coherent(&fep->pdev->dev, bd_size, &bd_dma, 3265 GFP_KERNEL); 3266 if (!cbd_base) { 3267 return -ENOMEM; 3268 } 3269 3270 /* Get the Ethernet address */ 3271 fec_get_mac(ndev); 3272 /* make sure MAC we just acquired is programmed into the hw */ 3273 fec_set_mac_address(ndev, NULL); 3274 3275 /* Set receive and transmit descriptor base. */ 3276 for (i = 0; i < fep->num_rx_queues; i++) { 3277 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[i]; 3278 unsigned size = dsize * rxq->bd.ring_size; 3279 3280 rxq->bd.qid = i; 3281 rxq->bd.base = cbd_base; 3282 rxq->bd.cur = cbd_base; 3283 rxq->bd.dma = bd_dma; 3284 rxq->bd.dsize = dsize; 3285 rxq->bd.dsize_log2 = dsize_log2; 3286 rxq->bd.reg_desc_active = fep->hwp + offset_des_active_rxq[i]; 3287 bd_dma += size; 3288 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size); 3289 rxq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); 3290 } 3291 3292 for (i = 0; i < fep->num_tx_queues; i++) { 3293 struct fec_enet_priv_tx_q *txq = fep->tx_queue[i]; 3294 unsigned size = dsize * txq->bd.ring_size; 3295 3296 txq->bd.qid = i; 3297 txq->bd.base = cbd_base; 3298 txq->bd.cur = cbd_base; 3299 txq->bd.dma = bd_dma; 3300 txq->bd.dsize = dsize; 3301 txq->bd.dsize_log2 = dsize_log2; 3302 txq->bd.reg_desc_active = fep->hwp + offset_des_active_txq[i]; 3303 bd_dma += size; 3304 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size); 3305 txq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); 3306 } 3307 3308 3309 /* The FEC Ethernet specific entries in the device structure */ 3310 ndev->watchdog_timeo = TX_TIMEOUT; 3311 ndev->netdev_ops = &fec_netdev_ops; 3312 ndev->ethtool_ops = &fec_enet_ethtool_ops; 3313 3314 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK); 3315 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT); 3316 3317 if (fep->quirks & FEC_QUIRK_HAS_VLAN) 3318 /* enable hw VLAN support */ 3319 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; 3320 3321 if (fep->quirks & FEC_QUIRK_HAS_CSUM) { 3322 ndev->gso_max_segs = FEC_MAX_TSO_SEGS; 3323 3324 /* enable hw accelerator */ 3325 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM 3326 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO); 3327 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 3328 } 3329 3330 if (fep->quirks & FEC_QUIRK_HAS_AVB) { 3331 fep->tx_align = 0; 3332 fep->rx_align = 0x3f; 3333 } 3334 3335 ndev->hw_features = ndev->features; 3336 3337 fec_restart(ndev); 3338 3339 if (fep->quirks & FEC_QUIRK_MIB_CLEAR) 3340 fec_enet_clear_ethtool_stats(ndev); 3341 else 3342 fec_enet_update_ethtool_stats(ndev); 3343 3344 return 0; 3345 } 3346 3347 #ifdef CONFIG_OF 3348 static int fec_reset_phy(struct platform_device *pdev) 3349 { 3350 int err, phy_reset; 3351 bool active_high = false; 3352 int msec = 1, phy_post_delay = 0; 3353 struct device_node *np = pdev->dev.of_node; 3354 3355 if (!np) 3356 return 0; 3357 3358 err = of_property_read_u32(np, "phy-reset-duration", &msec); 3359 /* A sane reset duration should not be longer than 1s */ 3360 if (!err && msec > 1000) 3361 msec = 1; 3362 3363 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0); 3364 if (phy_reset == -EPROBE_DEFER) 3365 return phy_reset; 3366 else if (!gpio_is_valid(phy_reset)) 3367 return 0; 3368 3369 err = of_property_read_u32(np, "phy-reset-post-delay", &phy_post_delay); 3370 /* valid reset duration should be less than 1s */ 3371 if (!err && phy_post_delay > 1000) 3372 return -EINVAL; 3373 3374 active_high = of_property_read_bool(np, "phy-reset-active-high"); 3375 3376 err = devm_gpio_request_one(&pdev->dev, phy_reset, 3377 active_high ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW, 3378 "phy-reset"); 3379 if (err) { 3380 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err); 3381 return err; 3382 } 3383 3384 if (msec > 20) 3385 msleep(msec); 3386 else 3387 usleep_range(msec * 1000, msec * 1000 + 1000); 3388 3389 gpio_set_value_cansleep(phy_reset, !active_high); 3390 3391 if (!phy_post_delay) 3392 return 0; 3393 3394 if (phy_post_delay > 20) 3395 msleep(phy_post_delay); 3396 else 3397 usleep_range(phy_post_delay * 1000, 3398 phy_post_delay * 1000 + 1000); 3399 3400 return 0; 3401 } 3402 #else /* CONFIG_OF */ 3403 static int fec_reset_phy(struct platform_device *pdev) 3404 { 3405 /* 3406 * In case of platform probe, the reset has been done 3407 * by machine code. 3408 */ 3409 return 0; 3410 } 3411 #endif /* CONFIG_OF */ 3412 3413 static void 3414 fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx) 3415 { 3416 struct device_node *np = pdev->dev.of_node; 3417 3418 *num_tx = *num_rx = 1; 3419 3420 if (!np || !of_device_is_available(np)) 3421 return; 3422 3423 /* parse the num of tx and rx queues */ 3424 of_property_read_u32(np, "fsl,num-tx-queues", num_tx); 3425 3426 of_property_read_u32(np, "fsl,num-rx-queues", num_rx); 3427 3428 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) { 3429 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n", 3430 *num_tx); 3431 *num_tx = 1; 3432 return; 3433 } 3434 3435 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) { 3436 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n", 3437 *num_rx); 3438 *num_rx = 1; 3439 return; 3440 } 3441 3442 } 3443 3444 static int fec_enet_get_irq_cnt(struct platform_device *pdev) 3445 { 3446 int irq_cnt = platform_irq_count(pdev); 3447 3448 if (irq_cnt > FEC_IRQ_NUM) 3449 irq_cnt = FEC_IRQ_NUM; /* last for pps */ 3450 else if (irq_cnt == 2) 3451 irq_cnt = 1; /* last for pps */ 3452 else if (irq_cnt <= 0) 3453 irq_cnt = 1; /* At least 1 irq is needed */ 3454 return irq_cnt; 3455 } 3456 3457 static int fec_enet_init_stop_mode(struct fec_enet_private *fep, 3458 struct device_node *np) 3459 { 3460 struct device_node *gpr_np; 3461 u32 out_val[3]; 3462 int ret = 0; 3463 3464 gpr_np = of_parse_phandle(np, "fsl,stop-mode", 0); 3465 if (!gpr_np) 3466 return 0; 3467 3468 ret = of_property_read_u32_array(np, "fsl,stop-mode", out_val, 3469 ARRAY_SIZE(out_val)); 3470 if (ret) { 3471 dev_dbg(&fep->pdev->dev, "no stop mode property\n"); 3472 return ret; 3473 } 3474 3475 fep->stop_gpr.gpr = syscon_node_to_regmap(gpr_np); 3476 if (IS_ERR(fep->stop_gpr.gpr)) { 3477 dev_err(&fep->pdev->dev, "could not find gpr regmap\n"); 3478 ret = PTR_ERR(fep->stop_gpr.gpr); 3479 fep->stop_gpr.gpr = NULL; 3480 goto out; 3481 } 3482 3483 fep->stop_gpr.reg = out_val[1]; 3484 fep->stop_gpr.bit = out_val[2]; 3485 3486 out: 3487 of_node_put(gpr_np); 3488 3489 return ret; 3490 } 3491 3492 static int 3493 fec_probe(struct platform_device *pdev) 3494 { 3495 struct fec_enet_private *fep; 3496 struct fec_platform_data *pdata; 3497 phy_interface_t interface; 3498 struct net_device *ndev; 3499 int i, irq, ret = 0; 3500 const struct of_device_id *of_id; 3501 static int dev_id; 3502 struct device_node *np = pdev->dev.of_node, *phy_node; 3503 int num_tx_qs; 3504 int num_rx_qs; 3505 char irq_name[8]; 3506 int irq_cnt; 3507 struct fec_devinfo *dev_info; 3508 3509 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs); 3510 3511 /* Init network device */ 3512 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private) + 3513 FEC_STATS_SIZE, num_tx_qs, num_rx_qs); 3514 if (!ndev) 3515 return -ENOMEM; 3516 3517 SET_NETDEV_DEV(ndev, &pdev->dev); 3518 3519 /* setup board info structure */ 3520 fep = netdev_priv(ndev); 3521 3522 of_id = of_match_device(fec_dt_ids, &pdev->dev); 3523 if (of_id) 3524 pdev->id_entry = of_id->data; 3525 dev_info = (struct fec_devinfo *)pdev->id_entry->driver_data; 3526 if (dev_info) 3527 fep->quirks = dev_info->quirks; 3528 3529 fep->netdev = ndev; 3530 fep->num_rx_queues = num_rx_qs; 3531 fep->num_tx_queues = num_tx_qs; 3532 3533 #if !defined(CONFIG_M5272) 3534 /* default enable pause frame auto negotiation */ 3535 if (fep->quirks & FEC_QUIRK_HAS_GBIT) 3536 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG; 3537 #endif 3538 3539 /* Select default pin state */ 3540 pinctrl_pm_select_default_state(&pdev->dev); 3541 3542 fep->hwp = devm_platform_ioremap_resource(pdev, 0); 3543 if (IS_ERR(fep->hwp)) { 3544 ret = PTR_ERR(fep->hwp); 3545 goto failed_ioremap; 3546 } 3547 3548 fep->pdev = pdev; 3549 fep->dev_id = dev_id++; 3550 3551 platform_set_drvdata(pdev, ndev); 3552 3553 if ((of_machine_is_compatible("fsl,imx6q") || 3554 of_machine_is_compatible("fsl,imx6dl")) && 3555 !of_property_read_bool(np, "fsl,err006687-workaround-present")) 3556 fep->quirks |= FEC_QUIRK_ERR006687; 3557 3558 if (of_get_property(np, "fsl,magic-packet", NULL)) 3559 fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET; 3560 3561 ret = fec_enet_init_stop_mode(fep, np); 3562 if (ret) 3563 goto failed_stop_mode; 3564 3565 phy_node = of_parse_phandle(np, "phy-handle", 0); 3566 if (!phy_node && of_phy_is_fixed_link(np)) { 3567 ret = of_phy_register_fixed_link(np); 3568 if (ret < 0) { 3569 dev_err(&pdev->dev, 3570 "broken fixed-link specification\n"); 3571 goto failed_phy; 3572 } 3573 phy_node = of_node_get(np); 3574 } 3575 fep->phy_node = phy_node; 3576 3577 ret = of_get_phy_mode(pdev->dev.of_node, &interface); 3578 if (ret) { 3579 pdata = dev_get_platdata(&pdev->dev); 3580 if (pdata) 3581 fep->phy_interface = pdata->phy; 3582 else 3583 fep->phy_interface = PHY_INTERFACE_MODE_MII; 3584 } else { 3585 fep->phy_interface = interface; 3586 } 3587 3588 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 3589 if (IS_ERR(fep->clk_ipg)) { 3590 ret = PTR_ERR(fep->clk_ipg); 3591 goto failed_clk; 3592 } 3593 3594 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 3595 if (IS_ERR(fep->clk_ahb)) { 3596 ret = PTR_ERR(fep->clk_ahb); 3597 goto failed_clk; 3598 } 3599 3600 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb); 3601 3602 /* enet_out is optional, depends on board */ 3603 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out"); 3604 if (IS_ERR(fep->clk_enet_out)) 3605 fep->clk_enet_out = NULL; 3606 3607 fep->ptp_clk_on = false; 3608 mutex_init(&fep->ptp_clk_mutex); 3609 3610 /* clk_ref is optional, depends on board */ 3611 fep->clk_ref = devm_clk_get(&pdev->dev, "enet_clk_ref"); 3612 if (IS_ERR(fep->clk_ref)) 3613 fep->clk_ref = NULL; 3614 3615 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX; 3616 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp"); 3617 if (IS_ERR(fep->clk_ptp)) { 3618 fep->clk_ptp = NULL; 3619 fep->bufdesc_ex = false; 3620 } 3621 3622 ret = fec_enet_clk_enable(ndev, true); 3623 if (ret) 3624 goto failed_clk; 3625 3626 ret = clk_prepare_enable(fep->clk_ipg); 3627 if (ret) 3628 goto failed_clk_ipg; 3629 ret = clk_prepare_enable(fep->clk_ahb); 3630 if (ret) 3631 goto failed_clk_ahb; 3632 3633 fep->reg_phy = devm_regulator_get_optional(&pdev->dev, "phy"); 3634 if (!IS_ERR(fep->reg_phy)) { 3635 ret = regulator_enable(fep->reg_phy); 3636 if (ret) { 3637 dev_err(&pdev->dev, 3638 "Failed to enable phy regulator: %d\n", ret); 3639 goto failed_regulator; 3640 } 3641 } else { 3642 if (PTR_ERR(fep->reg_phy) == -EPROBE_DEFER) { 3643 ret = -EPROBE_DEFER; 3644 goto failed_regulator; 3645 } 3646 fep->reg_phy = NULL; 3647 } 3648 3649 pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT); 3650 pm_runtime_use_autosuspend(&pdev->dev); 3651 pm_runtime_get_noresume(&pdev->dev); 3652 pm_runtime_set_active(&pdev->dev); 3653 pm_runtime_enable(&pdev->dev); 3654 3655 ret = fec_reset_phy(pdev); 3656 if (ret) 3657 goto failed_reset; 3658 3659 irq_cnt = fec_enet_get_irq_cnt(pdev); 3660 if (fep->bufdesc_ex) 3661 fec_ptp_init(pdev, irq_cnt); 3662 3663 ret = fec_enet_init(ndev); 3664 if (ret) 3665 goto failed_init; 3666 3667 for (i = 0; i < irq_cnt; i++) { 3668 snprintf(irq_name, sizeof(irq_name), "int%d", i); 3669 irq = platform_get_irq_byname_optional(pdev, irq_name); 3670 if (irq < 0) 3671 irq = platform_get_irq(pdev, i); 3672 if (irq < 0) { 3673 ret = irq; 3674 goto failed_irq; 3675 } 3676 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt, 3677 0, pdev->name, ndev); 3678 if (ret) 3679 goto failed_irq; 3680 3681 fep->irq[i] = irq; 3682 } 3683 3684 ret = fec_enet_mii_init(pdev); 3685 if (ret) 3686 goto failed_mii_init; 3687 3688 /* Carrier starts down, phylib will bring it up */ 3689 netif_carrier_off(ndev); 3690 fec_enet_clk_enable(ndev, false); 3691 pinctrl_pm_select_sleep_state(&pdev->dev); 3692 3693 ret = register_netdev(ndev); 3694 if (ret) 3695 goto failed_register; 3696 3697 device_init_wakeup(&ndev->dev, fep->wol_flag & 3698 FEC_WOL_HAS_MAGIC_PACKET); 3699 3700 if (fep->bufdesc_ex && fep->ptp_clock) 3701 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id); 3702 3703 fep->rx_copybreak = COPYBREAK_DEFAULT; 3704 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work); 3705 3706 pm_runtime_mark_last_busy(&pdev->dev); 3707 pm_runtime_put_autosuspend(&pdev->dev); 3708 3709 return 0; 3710 3711 failed_register: 3712 fec_enet_mii_remove(fep); 3713 failed_mii_init: 3714 failed_irq: 3715 failed_init: 3716 fec_ptp_stop(pdev); 3717 if (fep->reg_phy) 3718 regulator_disable(fep->reg_phy); 3719 failed_reset: 3720 pm_runtime_put_noidle(&pdev->dev); 3721 pm_runtime_disable(&pdev->dev); 3722 failed_regulator: 3723 clk_disable_unprepare(fep->clk_ahb); 3724 failed_clk_ahb: 3725 clk_disable_unprepare(fep->clk_ipg); 3726 failed_clk_ipg: 3727 fec_enet_clk_enable(ndev, false); 3728 failed_clk: 3729 if (of_phy_is_fixed_link(np)) 3730 of_phy_deregister_fixed_link(np); 3731 of_node_put(phy_node); 3732 failed_stop_mode: 3733 failed_phy: 3734 dev_id--; 3735 failed_ioremap: 3736 free_netdev(ndev); 3737 3738 return ret; 3739 } 3740 3741 static int 3742 fec_drv_remove(struct platform_device *pdev) 3743 { 3744 struct net_device *ndev = platform_get_drvdata(pdev); 3745 struct fec_enet_private *fep = netdev_priv(ndev); 3746 struct device_node *np = pdev->dev.of_node; 3747 int ret; 3748 3749 ret = pm_runtime_get_sync(&pdev->dev); 3750 if (ret < 0) 3751 return ret; 3752 3753 cancel_work_sync(&fep->tx_timeout_work); 3754 fec_ptp_stop(pdev); 3755 unregister_netdev(ndev); 3756 fec_enet_mii_remove(fep); 3757 if (fep->reg_phy) 3758 regulator_disable(fep->reg_phy); 3759 3760 if (of_phy_is_fixed_link(np)) 3761 of_phy_deregister_fixed_link(np); 3762 of_node_put(fep->phy_node); 3763 free_netdev(ndev); 3764 3765 clk_disable_unprepare(fep->clk_ahb); 3766 clk_disable_unprepare(fep->clk_ipg); 3767 pm_runtime_put_noidle(&pdev->dev); 3768 pm_runtime_disable(&pdev->dev); 3769 3770 return 0; 3771 } 3772 3773 static int __maybe_unused fec_suspend(struct device *dev) 3774 { 3775 struct net_device *ndev = dev_get_drvdata(dev); 3776 struct fec_enet_private *fep = netdev_priv(ndev); 3777 3778 rtnl_lock(); 3779 if (netif_running(ndev)) { 3780 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) 3781 fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON; 3782 phy_stop(ndev->phydev); 3783 napi_disable(&fep->napi); 3784 netif_tx_lock_bh(ndev); 3785 netif_device_detach(ndev); 3786 netif_tx_unlock_bh(ndev); 3787 fec_stop(ndev); 3788 fec_enet_clk_enable(ndev, false); 3789 if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) 3790 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3791 } 3792 rtnl_unlock(); 3793 3794 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) 3795 regulator_disable(fep->reg_phy); 3796 3797 /* SOC supply clock to phy, when clock is disabled, phy link down 3798 * SOC control phy regulator, when regulator is disabled, phy link down 3799 */ 3800 if (fep->clk_enet_out || fep->reg_phy) 3801 fep->link = 0; 3802 3803 return 0; 3804 } 3805 3806 static int __maybe_unused fec_resume(struct device *dev) 3807 { 3808 struct net_device *ndev = dev_get_drvdata(dev); 3809 struct fec_enet_private *fep = netdev_priv(ndev); 3810 int ret; 3811 int val; 3812 3813 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) { 3814 ret = regulator_enable(fep->reg_phy); 3815 if (ret) 3816 return ret; 3817 } 3818 3819 rtnl_lock(); 3820 if (netif_running(ndev)) { 3821 ret = fec_enet_clk_enable(ndev, true); 3822 if (ret) { 3823 rtnl_unlock(); 3824 goto failed_clk; 3825 } 3826 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) { 3827 fec_enet_stop_mode(fep, false); 3828 3829 val = readl(fep->hwp + FEC_ECNTRL); 3830 val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP); 3831 writel(val, fep->hwp + FEC_ECNTRL); 3832 fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON; 3833 } else { 3834 pinctrl_pm_select_default_state(&fep->pdev->dev); 3835 } 3836 fec_restart(ndev); 3837 netif_tx_lock_bh(ndev); 3838 netif_device_attach(ndev); 3839 netif_tx_unlock_bh(ndev); 3840 napi_enable(&fep->napi); 3841 phy_start(ndev->phydev); 3842 } 3843 rtnl_unlock(); 3844 3845 return 0; 3846 3847 failed_clk: 3848 if (fep->reg_phy) 3849 regulator_disable(fep->reg_phy); 3850 return ret; 3851 } 3852 3853 static int __maybe_unused fec_runtime_suspend(struct device *dev) 3854 { 3855 struct net_device *ndev = dev_get_drvdata(dev); 3856 struct fec_enet_private *fep = netdev_priv(ndev); 3857 3858 clk_disable_unprepare(fep->clk_ahb); 3859 clk_disable_unprepare(fep->clk_ipg); 3860 3861 return 0; 3862 } 3863 3864 static int __maybe_unused fec_runtime_resume(struct device *dev) 3865 { 3866 struct net_device *ndev = dev_get_drvdata(dev); 3867 struct fec_enet_private *fep = netdev_priv(ndev); 3868 int ret; 3869 3870 ret = clk_prepare_enable(fep->clk_ahb); 3871 if (ret) 3872 return ret; 3873 ret = clk_prepare_enable(fep->clk_ipg); 3874 if (ret) 3875 goto failed_clk_ipg; 3876 3877 return 0; 3878 3879 failed_clk_ipg: 3880 clk_disable_unprepare(fep->clk_ahb); 3881 return ret; 3882 } 3883 3884 static const struct dev_pm_ops fec_pm_ops = { 3885 SET_SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume) 3886 SET_RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL) 3887 }; 3888 3889 static struct platform_driver fec_driver = { 3890 .driver = { 3891 .name = DRIVER_NAME, 3892 .pm = &fec_pm_ops, 3893 .of_match_table = fec_dt_ids, 3894 .suppress_bind_attrs = true, 3895 }, 3896 .id_table = fec_devtype, 3897 .probe = fec_probe, 3898 .remove = fec_drv_remove, 3899 }; 3900 3901 module_platform_driver(fec_driver); 3902 3903 MODULE_ALIAS("platform:"DRIVER_NAME); 3904 MODULE_LICENSE("GPL"); 3905