1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. 4 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) 5 * 6 * Right now, I am very wasteful with the buffers. I allocate memory 7 * pages and then divide them into 2K frame buffers. This way I know I 8 * have buffers large enough to hold one frame within one buffer descriptor. 9 * Once I get this working, I will use 64 or 128 byte CPM buffers, which 10 * will be much more memory efficient and will easily handle lots of 11 * small packets. 12 * 13 * Much better multiple PHY support by Magnus Damm. 14 * Copyright (c) 2000 Ericsson Radio Systems AB. 15 * 16 * Support for FEC controller of ColdFire processors. 17 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) 18 * 19 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) 20 * Copyright (c) 2004-2006 Macq Electronique SA. 21 * 22 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. 23 */ 24 25 #include <linux/module.h> 26 #include <linux/kernel.h> 27 #include <linux/string.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/ptrace.h> 30 #include <linux/errno.h> 31 #include <linux/ioport.h> 32 #include <linux/slab.h> 33 #include <linux/interrupt.h> 34 #include <linux/delay.h> 35 #include <linux/netdevice.h> 36 #include <linux/etherdevice.h> 37 #include <linux/skbuff.h> 38 #include <linux/in.h> 39 #include <linux/ip.h> 40 #include <net/ip.h> 41 #include <net/selftests.h> 42 #include <net/tso.h> 43 #include <linux/tcp.h> 44 #include <linux/udp.h> 45 #include <linux/icmp.h> 46 #include <linux/spinlock.h> 47 #include <linux/workqueue.h> 48 #include <linux/bitops.h> 49 #include <linux/io.h> 50 #include <linux/irq.h> 51 #include <linux/clk.h> 52 #include <linux/crc32.h> 53 #include <linux/platform_device.h> 54 #include <linux/mdio.h> 55 #include <linux/phy.h> 56 #include <linux/fec.h> 57 #include <linux/of.h> 58 #include <linux/of_device.h> 59 #include <linux/of_gpio.h> 60 #include <linux/of_mdio.h> 61 #include <linux/of_net.h> 62 #include <linux/regulator/consumer.h> 63 #include <linux/if_vlan.h> 64 #include <linux/pinctrl/consumer.h> 65 #include <linux/prefetch.h> 66 #include <linux/mfd/syscon.h> 67 #include <linux/regmap.h> 68 #include <soc/imx/cpuidle.h> 69 70 #include <asm/cacheflush.h> 71 72 #include "fec.h" 73 74 static void set_multicast_list(struct net_device *ndev); 75 static void fec_enet_itr_coal_init(struct net_device *ndev); 76 77 #define DRIVER_NAME "fec" 78 79 static const u16 fec_enet_vlan_pri_to_queue[8] = {0, 0, 1, 1, 1, 2, 2, 2}; 80 81 /* Pause frame feild and FIFO threshold */ 82 #define FEC_ENET_FCE (1 << 5) 83 #define FEC_ENET_RSEM_V 0x84 84 #define FEC_ENET_RSFL_V 16 85 #define FEC_ENET_RAEM_V 0x8 86 #define FEC_ENET_RAFL_V 0x8 87 #define FEC_ENET_OPD_V 0xFFF0 88 #define FEC_MDIO_PM_TIMEOUT 100 /* ms */ 89 90 struct fec_devinfo { 91 u32 quirks; 92 }; 93 94 static const struct fec_devinfo fec_imx25_info = { 95 .quirks = FEC_QUIRK_USE_GASKET | FEC_QUIRK_MIB_CLEAR | 96 FEC_QUIRK_HAS_FRREG, 97 }; 98 99 static const struct fec_devinfo fec_imx27_info = { 100 .quirks = FEC_QUIRK_MIB_CLEAR | FEC_QUIRK_HAS_FRREG, 101 }; 102 103 static const struct fec_devinfo fec_imx28_info = { 104 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME | 105 FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC | 106 FEC_QUIRK_HAS_FRREG | FEC_QUIRK_CLEAR_SETUP_MII | 107 FEC_QUIRK_NO_HARD_RESET, 108 }; 109 110 static const struct fec_devinfo fec_imx6q_info = { 111 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 112 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 113 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 | 114 FEC_QUIRK_HAS_RACC | FEC_QUIRK_CLEAR_SETUP_MII | 115 FEC_QUIRK_HAS_PMQOS, 116 }; 117 118 static const struct fec_devinfo fec_mvf600_info = { 119 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC, 120 }; 121 122 static const struct fec_devinfo fec_imx6x_info = { 123 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 124 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 125 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 126 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 127 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE | 128 FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES, 129 }; 130 131 static const struct fec_devinfo fec_imx6ul_info = { 132 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 133 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 134 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR007885 | 135 FEC_QUIRK_BUG_CAPTURE | FEC_QUIRK_HAS_RACC | 136 FEC_QUIRK_HAS_COALESCE | FEC_QUIRK_CLEAR_SETUP_MII, 137 }; 138 139 static const struct fec_devinfo fec_imx8mq_info = { 140 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 141 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 142 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 143 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 144 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE | 145 FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES | 146 FEC_QUIRK_HAS_EEE | FEC_QUIRK_WAKEUP_FROM_INT2, 147 }; 148 149 static const struct fec_devinfo fec_imx8qm_info = { 150 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 151 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 152 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 153 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 154 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE | 155 FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES | 156 FEC_QUIRK_DELAYED_CLKS_SUPPORT, 157 }; 158 159 static const struct fec_devinfo fec_s32v234_info = { 160 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 161 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 162 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 163 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE, 164 }; 165 166 static struct platform_device_id fec_devtype[] = { 167 { 168 /* keep it for coldfire */ 169 .name = DRIVER_NAME, 170 .driver_data = 0, 171 }, { 172 .name = "imx25-fec", 173 .driver_data = (kernel_ulong_t)&fec_imx25_info, 174 }, { 175 .name = "imx27-fec", 176 .driver_data = (kernel_ulong_t)&fec_imx27_info, 177 }, { 178 .name = "imx28-fec", 179 .driver_data = (kernel_ulong_t)&fec_imx28_info, 180 }, { 181 .name = "imx6q-fec", 182 .driver_data = (kernel_ulong_t)&fec_imx6q_info, 183 }, { 184 .name = "mvf600-fec", 185 .driver_data = (kernel_ulong_t)&fec_mvf600_info, 186 }, { 187 .name = "imx6sx-fec", 188 .driver_data = (kernel_ulong_t)&fec_imx6x_info, 189 }, { 190 .name = "imx6ul-fec", 191 .driver_data = (kernel_ulong_t)&fec_imx6ul_info, 192 }, { 193 .name = "imx8mq-fec", 194 .driver_data = (kernel_ulong_t)&fec_imx8mq_info, 195 }, { 196 .name = "imx8qm-fec", 197 .driver_data = (kernel_ulong_t)&fec_imx8qm_info, 198 }, { 199 .name = "s32v234-fec", 200 .driver_data = (kernel_ulong_t)&fec_s32v234_info, 201 }, { 202 /* sentinel */ 203 } 204 }; 205 MODULE_DEVICE_TABLE(platform, fec_devtype); 206 207 enum imx_fec_type { 208 IMX25_FEC = 1, /* runs on i.mx25/50/53 */ 209 IMX27_FEC, /* runs on i.mx27/35/51 */ 210 IMX28_FEC, 211 IMX6Q_FEC, 212 MVF600_FEC, 213 IMX6SX_FEC, 214 IMX6UL_FEC, 215 IMX8MQ_FEC, 216 IMX8QM_FEC, 217 S32V234_FEC, 218 }; 219 220 static const struct of_device_id fec_dt_ids[] = { 221 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], }, 222 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], }, 223 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], }, 224 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], }, 225 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], }, 226 { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], }, 227 { .compatible = "fsl,imx6ul-fec", .data = &fec_devtype[IMX6UL_FEC], }, 228 { .compatible = "fsl,imx8mq-fec", .data = &fec_devtype[IMX8MQ_FEC], }, 229 { .compatible = "fsl,imx8qm-fec", .data = &fec_devtype[IMX8QM_FEC], }, 230 { .compatible = "fsl,s32v234-fec", .data = &fec_devtype[S32V234_FEC], }, 231 { /* sentinel */ } 232 }; 233 MODULE_DEVICE_TABLE(of, fec_dt_ids); 234 235 static unsigned char macaddr[ETH_ALEN]; 236 module_param_array(macaddr, byte, NULL, 0); 237 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address"); 238 239 #if defined(CONFIG_M5272) 240 /* 241 * Some hardware gets it MAC address out of local flash memory. 242 * if this is non-zero then assume it is the address to get MAC from. 243 */ 244 #if defined(CONFIG_NETtel) 245 #define FEC_FLASHMAC 0xf0006006 246 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) 247 #define FEC_FLASHMAC 0xf0006000 248 #elif defined(CONFIG_CANCam) 249 #define FEC_FLASHMAC 0xf0020000 250 #elif defined (CONFIG_M5272C3) 251 #define FEC_FLASHMAC (0xffe04000 + 4) 252 #elif defined(CONFIG_MOD5272) 253 #define FEC_FLASHMAC 0xffc0406b 254 #else 255 #define FEC_FLASHMAC 0 256 #endif 257 #endif /* CONFIG_M5272 */ 258 259 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets. 260 * 261 * 2048 byte skbufs are allocated. However, alignment requirements 262 * varies between FEC variants. Worst case is 64, so round down by 64. 263 */ 264 #define PKT_MAXBUF_SIZE (round_down(2048 - 64, 64)) 265 #define PKT_MINBUF_SIZE 64 266 267 /* FEC receive acceleration */ 268 #define FEC_RACC_IPDIS (1 << 1) 269 #define FEC_RACC_PRODIS (1 << 2) 270 #define FEC_RACC_SHIFT16 BIT(7) 271 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS) 272 273 /* MIB Control Register */ 274 #define FEC_MIB_CTRLSTAT_DISABLE BIT(31) 275 276 /* 277 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame 278 * size bits. Other FEC hardware does not, so we need to take that into 279 * account when setting it. 280 */ 281 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 282 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \ 283 defined(CONFIG_ARM64) 284 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) 285 #else 286 #define OPT_FRAME_SIZE 0 287 #endif 288 289 /* FEC MII MMFR bits definition */ 290 #define FEC_MMFR_ST (1 << 30) 291 #define FEC_MMFR_ST_C45 (0) 292 #define FEC_MMFR_OP_READ (2 << 28) 293 #define FEC_MMFR_OP_READ_C45 (3 << 28) 294 #define FEC_MMFR_OP_WRITE (1 << 28) 295 #define FEC_MMFR_OP_ADDR_WRITE (0) 296 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23) 297 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18) 298 #define FEC_MMFR_TA (2 << 16) 299 #define FEC_MMFR_DATA(v) (v & 0xffff) 300 /* FEC ECR bits definition */ 301 #define FEC_ECR_RESET BIT(0) 302 #define FEC_ECR_ETHEREN BIT(1) 303 #define FEC_ECR_MAGICEN BIT(2) 304 #define FEC_ECR_SLEEP BIT(3) 305 #define FEC_ECR_EN1588 BIT(4) 306 307 #define FEC_MII_TIMEOUT 30000 /* us */ 308 309 /* Transmitter timeout */ 310 #define TX_TIMEOUT (2 * HZ) 311 312 #define FEC_PAUSE_FLAG_AUTONEG 0x1 313 #define FEC_PAUSE_FLAG_ENABLE 0x2 314 #define FEC_WOL_HAS_MAGIC_PACKET (0x1 << 0) 315 #define FEC_WOL_FLAG_ENABLE (0x1 << 1) 316 #define FEC_WOL_FLAG_SLEEP_ON (0x1 << 2) 317 318 #define COPYBREAK_DEFAULT 256 319 320 /* Max number of allowed TCP segments for software TSO */ 321 #define FEC_MAX_TSO_SEGS 100 322 #define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) 323 324 #define IS_TSO_HEADER(txq, addr) \ 325 ((addr >= txq->tso_hdrs_dma) && \ 326 (addr < txq->tso_hdrs_dma + txq->bd.ring_size * TSO_HEADER_SIZE)) 327 328 static int mii_cnt; 329 330 static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, 331 struct bufdesc_prop *bd) 332 { 333 return (bdp >= bd->last) ? bd->base 334 : (struct bufdesc *)(((void *)bdp) + bd->dsize); 335 } 336 337 static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, 338 struct bufdesc_prop *bd) 339 { 340 return (bdp <= bd->base) ? bd->last 341 : (struct bufdesc *)(((void *)bdp) - bd->dsize); 342 } 343 344 static int fec_enet_get_bd_index(struct bufdesc *bdp, 345 struct bufdesc_prop *bd) 346 { 347 return ((const char *)bdp - (const char *)bd->base) >> bd->dsize_log2; 348 } 349 350 static int fec_enet_get_free_txdesc_num(struct fec_enet_priv_tx_q *txq) 351 { 352 int entries; 353 354 entries = (((const char *)txq->dirty_tx - 355 (const char *)txq->bd.cur) >> txq->bd.dsize_log2) - 1; 356 357 return entries >= 0 ? entries : entries + txq->bd.ring_size; 358 } 359 360 static void swap_buffer(void *bufaddr, int len) 361 { 362 int i; 363 unsigned int *buf = bufaddr; 364 365 for (i = 0; i < len; i += 4, buf++) 366 swab32s(buf); 367 } 368 369 static void swap_buffer2(void *dst_buf, void *src_buf, int len) 370 { 371 int i; 372 unsigned int *src = src_buf; 373 unsigned int *dst = dst_buf; 374 375 for (i = 0; i < len; i += 4, src++, dst++) 376 *dst = swab32p(src); 377 } 378 379 static void fec_dump(struct net_device *ndev) 380 { 381 struct fec_enet_private *fep = netdev_priv(ndev); 382 struct bufdesc *bdp; 383 struct fec_enet_priv_tx_q *txq; 384 int index = 0; 385 386 netdev_info(ndev, "TX ring dump\n"); 387 pr_info("Nr SC addr len SKB\n"); 388 389 txq = fep->tx_queue[0]; 390 bdp = txq->bd.base; 391 392 do { 393 pr_info("%3u %c%c 0x%04x 0x%08x %4u %p\n", 394 index, 395 bdp == txq->bd.cur ? 'S' : ' ', 396 bdp == txq->dirty_tx ? 'H' : ' ', 397 fec16_to_cpu(bdp->cbd_sc), 398 fec32_to_cpu(bdp->cbd_bufaddr), 399 fec16_to_cpu(bdp->cbd_datlen), 400 txq->tx_skbuff[index]); 401 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 402 index++; 403 } while (bdp != txq->bd.base); 404 } 405 406 static inline bool is_ipv4_pkt(struct sk_buff *skb) 407 { 408 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4; 409 } 410 411 static int 412 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev) 413 { 414 /* Only run for packets requiring a checksum. */ 415 if (skb->ip_summed != CHECKSUM_PARTIAL) 416 return 0; 417 418 if (unlikely(skb_cow_head(skb, 0))) 419 return -1; 420 421 if (is_ipv4_pkt(skb)) 422 ip_hdr(skb)->check = 0; 423 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0; 424 425 return 0; 426 } 427 428 static struct bufdesc * 429 fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq, 430 struct sk_buff *skb, 431 struct net_device *ndev) 432 { 433 struct fec_enet_private *fep = netdev_priv(ndev); 434 struct bufdesc *bdp = txq->bd.cur; 435 struct bufdesc_ex *ebdp; 436 int nr_frags = skb_shinfo(skb)->nr_frags; 437 int frag, frag_len; 438 unsigned short status; 439 unsigned int estatus = 0; 440 skb_frag_t *this_frag; 441 unsigned int index; 442 void *bufaddr; 443 dma_addr_t addr; 444 int i; 445 446 for (frag = 0; frag < nr_frags; frag++) { 447 this_frag = &skb_shinfo(skb)->frags[frag]; 448 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 449 ebdp = (struct bufdesc_ex *)bdp; 450 451 status = fec16_to_cpu(bdp->cbd_sc); 452 status &= ~BD_ENET_TX_STATS; 453 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 454 frag_len = skb_frag_size(&skb_shinfo(skb)->frags[frag]); 455 456 /* Handle the last BD specially */ 457 if (frag == nr_frags - 1) { 458 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 459 if (fep->bufdesc_ex) { 460 estatus |= BD_ENET_TX_INT; 461 if (unlikely(skb_shinfo(skb)->tx_flags & 462 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 463 estatus |= BD_ENET_TX_TS; 464 } 465 } 466 467 if (fep->bufdesc_ex) { 468 if (fep->quirks & FEC_QUIRK_HAS_AVB) 469 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 470 if (skb->ip_summed == CHECKSUM_PARTIAL) 471 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 472 473 ebdp->cbd_bdu = 0; 474 ebdp->cbd_esc = cpu_to_fec32(estatus); 475 } 476 477 bufaddr = skb_frag_address(this_frag); 478 479 index = fec_enet_get_bd_index(bdp, &txq->bd); 480 if (((unsigned long) bufaddr) & fep->tx_align || 481 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 482 memcpy(txq->tx_bounce[index], bufaddr, frag_len); 483 bufaddr = txq->tx_bounce[index]; 484 485 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 486 swap_buffer(bufaddr, frag_len); 487 } 488 489 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len, 490 DMA_TO_DEVICE); 491 if (dma_mapping_error(&fep->pdev->dev, addr)) { 492 if (net_ratelimit()) 493 netdev_err(ndev, "Tx DMA memory map failed\n"); 494 goto dma_mapping_error; 495 } 496 497 bdp->cbd_bufaddr = cpu_to_fec32(addr); 498 bdp->cbd_datlen = cpu_to_fec16(frag_len); 499 /* Make sure the updates to rest of the descriptor are 500 * performed before transferring ownership. 501 */ 502 wmb(); 503 bdp->cbd_sc = cpu_to_fec16(status); 504 } 505 506 return bdp; 507 dma_mapping_error: 508 bdp = txq->bd.cur; 509 for (i = 0; i < frag; i++) { 510 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 511 dma_unmap_single(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr), 512 fec16_to_cpu(bdp->cbd_datlen), DMA_TO_DEVICE); 513 } 514 return ERR_PTR(-ENOMEM); 515 } 516 517 static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq, 518 struct sk_buff *skb, struct net_device *ndev) 519 { 520 struct fec_enet_private *fep = netdev_priv(ndev); 521 int nr_frags = skb_shinfo(skb)->nr_frags; 522 struct bufdesc *bdp, *last_bdp; 523 void *bufaddr; 524 dma_addr_t addr; 525 unsigned short status; 526 unsigned short buflen; 527 unsigned int estatus = 0; 528 unsigned int index; 529 int entries_free; 530 531 entries_free = fec_enet_get_free_txdesc_num(txq); 532 if (entries_free < MAX_SKB_FRAGS + 1) { 533 dev_kfree_skb_any(skb); 534 if (net_ratelimit()) 535 netdev_err(ndev, "NOT enough BD for SG!\n"); 536 return NETDEV_TX_OK; 537 } 538 539 /* Protocol checksum off-load for TCP and UDP. */ 540 if (fec_enet_clear_csum(skb, ndev)) { 541 dev_kfree_skb_any(skb); 542 return NETDEV_TX_OK; 543 } 544 545 /* Fill in a Tx ring entry */ 546 bdp = txq->bd.cur; 547 last_bdp = bdp; 548 status = fec16_to_cpu(bdp->cbd_sc); 549 status &= ~BD_ENET_TX_STATS; 550 551 /* Set buffer length and buffer pointer */ 552 bufaddr = skb->data; 553 buflen = skb_headlen(skb); 554 555 index = fec_enet_get_bd_index(bdp, &txq->bd); 556 if (((unsigned long) bufaddr) & fep->tx_align || 557 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 558 memcpy(txq->tx_bounce[index], skb->data, buflen); 559 bufaddr = txq->tx_bounce[index]; 560 561 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 562 swap_buffer(bufaddr, buflen); 563 } 564 565 /* Push the data cache so the CPM does not get stale memory data. */ 566 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE); 567 if (dma_mapping_error(&fep->pdev->dev, addr)) { 568 dev_kfree_skb_any(skb); 569 if (net_ratelimit()) 570 netdev_err(ndev, "Tx DMA memory map failed\n"); 571 return NETDEV_TX_OK; 572 } 573 574 if (nr_frags) { 575 last_bdp = fec_enet_txq_submit_frag_skb(txq, skb, ndev); 576 if (IS_ERR(last_bdp)) { 577 dma_unmap_single(&fep->pdev->dev, addr, 578 buflen, DMA_TO_DEVICE); 579 dev_kfree_skb_any(skb); 580 return NETDEV_TX_OK; 581 } 582 } else { 583 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 584 if (fep->bufdesc_ex) { 585 estatus = BD_ENET_TX_INT; 586 if (unlikely(skb_shinfo(skb)->tx_flags & 587 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 588 estatus |= BD_ENET_TX_TS; 589 } 590 } 591 bdp->cbd_bufaddr = cpu_to_fec32(addr); 592 bdp->cbd_datlen = cpu_to_fec16(buflen); 593 594 if (fep->bufdesc_ex) { 595 596 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 597 598 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 599 fep->hwts_tx_en)) 600 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 601 602 if (fep->quirks & FEC_QUIRK_HAS_AVB) 603 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 604 605 if (skb->ip_summed == CHECKSUM_PARTIAL) 606 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 607 608 ebdp->cbd_bdu = 0; 609 ebdp->cbd_esc = cpu_to_fec32(estatus); 610 } 611 612 index = fec_enet_get_bd_index(last_bdp, &txq->bd); 613 /* Save skb pointer */ 614 txq->tx_skbuff[index] = skb; 615 616 /* Make sure the updates to rest of the descriptor are performed before 617 * transferring ownership. 618 */ 619 wmb(); 620 621 /* Send it on its way. Tell FEC it's ready, interrupt when done, 622 * it's the last BD of the frame, and to put the CRC on the end. 623 */ 624 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC); 625 bdp->cbd_sc = cpu_to_fec16(status); 626 627 /* If this was the last BD in the ring, start at the beginning again. */ 628 bdp = fec_enet_get_nextdesc(last_bdp, &txq->bd); 629 630 skb_tx_timestamp(skb); 631 632 /* Make sure the update to bdp and tx_skbuff are performed before 633 * txq->bd.cur. 634 */ 635 wmb(); 636 txq->bd.cur = bdp; 637 638 /* Trigger transmission start */ 639 writel(0, txq->bd.reg_desc_active); 640 641 return 0; 642 } 643 644 static int 645 fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb, 646 struct net_device *ndev, 647 struct bufdesc *bdp, int index, char *data, 648 int size, bool last_tcp, bool is_last) 649 { 650 struct fec_enet_private *fep = netdev_priv(ndev); 651 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 652 unsigned short status; 653 unsigned int estatus = 0; 654 dma_addr_t addr; 655 656 status = fec16_to_cpu(bdp->cbd_sc); 657 status &= ~BD_ENET_TX_STATS; 658 659 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 660 661 if (((unsigned long) data) & fep->tx_align || 662 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 663 memcpy(txq->tx_bounce[index], data, size); 664 data = txq->tx_bounce[index]; 665 666 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 667 swap_buffer(data, size); 668 } 669 670 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE); 671 if (dma_mapping_error(&fep->pdev->dev, addr)) { 672 dev_kfree_skb_any(skb); 673 if (net_ratelimit()) 674 netdev_err(ndev, "Tx DMA memory map failed\n"); 675 return NETDEV_TX_BUSY; 676 } 677 678 bdp->cbd_datlen = cpu_to_fec16(size); 679 bdp->cbd_bufaddr = cpu_to_fec32(addr); 680 681 if (fep->bufdesc_ex) { 682 if (fep->quirks & FEC_QUIRK_HAS_AVB) 683 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 684 if (skb->ip_summed == CHECKSUM_PARTIAL) 685 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 686 ebdp->cbd_bdu = 0; 687 ebdp->cbd_esc = cpu_to_fec32(estatus); 688 } 689 690 /* Handle the last BD specially */ 691 if (last_tcp) 692 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC); 693 if (is_last) { 694 status |= BD_ENET_TX_INTR; 695 if (fep->bufdesc_ex) 696 ebdp->cbd_esc |= cpu_to_fec32(BD_ENET_TX_INT); 697 } 698 699 bdp->cbd_sc = cpu_to_fec16(status); 700 701 return 0; 702 } 703 704 static int 705 fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq, 706 struct sk_buff *skb, struct net_device *ndev, 707 struct bufdesc *bdp, int index) 708 { 709 struct fec_enet_private *fep = netdev_priv(ndev); 710 int hdr_len = skb_tcp_all_headers(skb); 711 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 712 void *bufaddr; 713 unsigned long dmabuf; 714 unsigned short status; 715 unsigned int estatus = 0; 716 717 status = fec16_to_cpu(bdp->cbd_sc); 718 status &= ~BD_ENET_TX_STATS; 719 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 720 721 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 722 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE; 723 if (((unsigned long)bufaddr) & fep->tx_align || 724 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 725 memcpy(txq->tx_bounce[index], skb->data, hdr_len); 726 bufaddr = txq->tx_bounce[index]; 727 728 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 729 swap_buffer(bufaddr, hdr_len); 730 731 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr, 732 hdr_len, DMA_TO_DEVICE); 733 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) { 734 dev_kfree_skb_any(skb); 735 if (net_ratelimit()) 736 netdev_err(ndev, "Tx DMA memory map failed\n"); 737 return NETDEV_TX_BUSY; 738 } 739 } 740 741 bdp->cbd_bufaddr = cpu_to_fec32(dmabuf); 742 bdp->cbd_datlen = cpu_to_fec16(hdr_len); 743 744 if (fep->bufdesc_ex) { 745 if (fep->quirks & FEC_QUIRK_HAS_AVB) 746 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 747 if (skb->ip_summed == CHECKSUM_PARTIAL) 748 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 749 ebdp->cbd_bdu = 0; 750 ebdp->cbd_esc = cpu_to_fec32(estatus); 751 } 752 753 bdp->cbd_sc = cpu_to_fec16(status); 754 755 return 0; 756 } 757 758 static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq, 759 struct sk_buff *skb, 760 struct net_device *ndev) 761 { 762 struct fec_enet_private *fep = netdev_priv(ndev); 763 int hdr_len, total_len, data_left; 764 struct bufdesc *bdp = txq->bd.cur; 765 struct tso_t tso; 766 unsigned int index = 0; 767 int ret; 768 769 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(txq)) { 770 dev_kfree_skb_any(skb); 771 if (net_ratelimit()) 772 netdev_err(ndev, "NOT enough BD for TSO!\n"); 773 return NETDEV_TX_OK; 774 } 775 776 /* Protocol checksum off-load for TCP and UDP. */ 777 if (fec_enet_clear_csum(skb, ndev)) { 778 dev_kfree_skb_any(skb); 779 return NETDEV_TX_OK; 780 } 781 782 /* Initialize the TSO handler, and prepare the first payload */ 783 hdr_len = tso_start(skb, &tso); 784 785 total_len = skb->len - hdr_len; 786 while (total_len > 0) { 787 char *hdr; 788 789 index = fec_enet_get_bd_index(bdp, &txq->bd); 790 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); 791 total_len -= data_left; 792 793 /* prepare packet headers: MAC + IP + TCP */ 794 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 795 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); 796 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index); 797 if (ret) 798 goto err_release; 799 800 while (data_left > 0) { 801 int size; 802 803 size = min_t(int, tso.size, data_left); 804 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 805 index = fec_enet_get_bd_index(bdp, &txq->bd); 806 ret = fec_enet_txq_put_data_tso(txq, skb, ndev, 807 bdp, index, 808 tso.data, size, 809 size == data_left, 810 total_len == 0); 811 if (ret) 812 goto err_release; 813 814 data_left -= size; 815 tso_build_data(skb, &tso, size); 816 } 817 818 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 819 } 820 821 /* Save skb pointer */ 822 txq->tx_skbuff[index] = skb; 823 824 skb_tx_timestamp(skb); 825 txq->bd.cur = bdp; 826 827 /* Trigger transmission start */ 828 if (!(fep->quirks & FEC_QUIRK_ERR007885) || 829 !readl(txq->bd.reg_desc_active) || 830 !readl(txq->bd.reg_desc_active) || 831 !readl(txq->bd.reg_desc_active) || 832 !readl(txq->bd.reg_desc_active)) 833 writel(0, txq->bd.reg_desc_active); 834 835 return 0; 836 837 err_release: 838 /* TODO: Release all used data descriptors for TSO */ 839 return ret; 840 } 841 842 static netdev_tx_t 843 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) 844 { 845 struct fec_enet_private *fep = netdev_priv(ndev); 846 int entries_free; 847 unsigned short queue; 848 struct fec_enet_priv_tx_q *txq; 849 struct netdev_queue *nq; 850 int ret; 851 852 queue = skb_get_queue_mapping(skb); 853 txq = fep->tx_queue[queue]; 854 nq = netdev_get_tx_queue(ndev, queue); 855 856 if (skb_is_gso(skb)) 857 ret = fec_enet_txq_submit_tso(txq, skb, ndev); 858 else 859 ret = fec_enet_txq_submit_skb(txq, skb, ndev); 860 if (ret) 861 return ret; 862 863 entries_free = fec_enet_get_free_txdesc_num(txq); 864 if (entries_free <= txq->tx_stop_threshold) 865 netif_tx_stop_queue(nq); 866 867 return NETDEV_TX_OK; 868 } 869 870 /* Init RX & TX buffer descriptors 871 */ 872 static void fec_enet_bd_init(struct net_device *dev) 873 { 874 struct fec_enet_private *fep = netdev_priv(dev); 875 struct fec_enet_priv_tx_q *txq; 876 struct fec_enet_priv_rx_q *rxq; 877 struct bufdesc *bdp; 878 unsigned int i; 879 unsigned int q; 880 881 for (q = 0; q < fep->num_rx_queues; q++) { 882 /* Initialize the receive buffer descriptors. */ 883 rxq = fep->rx_queue[q]; 884 bdp = rxq->bd.base; 885 886 for (i = 0; i < rxq->bd.ring_size; i++) { 887 888 /* Initialize the BD for every fragment in the page. */ 889 if (bdp->cbd_bufaddr) 890 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); 891 else 892 bdp->cbd_sc = cpu_to_fec16(0); 893 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 894 } 895 896 /* Set the last buffer to wrap */ 897 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); 898 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 899 900 rxq->bd.cur = rxq->bd.base; 901 } 902 903 for (q = 0; q < fep->num_tx_queues; q++) { 904 /* ...and the same for transmit */ 905 txq = fep->tx_queue[q]; 906 bdp = txq->bd.base; 907 txq->bd.cur = bdp; 908 909 for (i = 0; i < txq->bd.ring_size; i++) { 910 /* Initialize the BD for every fragment in the page. */ 911 bdp->cbd_sc = cpu_to_fec16(0); 912 if (bdp->cbd_bufaddr && 913 !IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr))) 914 dma_unmap_single(&fep->pdev->dev, 915 fec32_to_cpu(bdp->cbd_bufaddr), 916 fec16_to_cpu(bdp->cbd_datlen), 917 DMA_TO_DEVICE); 918 if (txq->tx_skbuff[i]) { 919 dev_kfree_skb_any(txq->tx_skbuff[i]); 920 txq->tx_skbuff[i] = NULL; 921 } 922 bdp->cbd_bufaddr = cpu_to_fec32(0); 923 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 924 } 925 926 /* Set the last buffer to wrap */ 927 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); 928 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 929 txq->dirty_tx = bdp; 930 } 931 } 932 933 static void fec_enet_active_rxring(struct net_device *ndev) 934 { 935 struct fec_enet_private *fep = netdev_priv(ndev); 936 int i; 937 938 for (i = 0; i < fep->num_rx_queues; i++) 939 writel(0, fep->rx_queue[i]->bd.reg_desc_active); 940 } 941 942 static void fec_enet_enable_ring(struct net_device *ndev) 943 { 944 struct fec_enet_private *fep = netdev_priv(ndev); 945 struct fec_enet_priv_tx_q *txq; 946 struct fec_enet_priv_rx_q *rxq; 947 int i; 948 949 for (i = 0; i < fep->num_rx_queues; i++) { 950 rxq = fep->rx_queue[i]; 951 writel(rxq->bd.dma, fep->hwp + FEC_R_DES_START(i)); 952 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i)); 953 954 /* enable DMA1/2 */ 955 if (i) 956 writel(RCMR_MATCHEN | RCMR_CMP(i), 957 fep->hwp + FEC_RCMR(i)); 958 } 959 960 for (i = 0; i < fep->num_tx_queues; i++) { 961 txq = fep->tx_queue[i]; 962 writel(txq->bd.dma, fep->hwp + FEC_X_DES_START(i)); 963 964 /* enable DMA1/2 */ 965 if (i) 966 writel(DMA_CLASS_EN | IDLE_SLOPE(i), 967 fep->hwp + FEC_DMA_CFG(i)); 968 } 969 } 970 971 static void fec_enet_reset_skb(struct net_device *ndev) 972 { 973 struct fec_enet_private *fep = netdev_priv(ndev); 974 struct fec_enet_priv_tx_q *txq; 975 int i, j; 976 977 for (i = 0; i < fep->num_tx_queues; i++) { 978 txq = fep->tx_queue[i]; 979 980 for (j = 0; j < txq->bd.ring_size; j++) { 981 if (txq->tx_skbuff[j]) { 982 dev_kfree_skb_any(txq->tx_skbuff[j]); 983 txq->tx_skbuff[j] = NULL; 984 } 985 } 986 } 987 } 988 989 /* 990 * This function is called to start or restart the FEC during a link 991 * change, transmit timeout, or to reconfigure the FEC. The network 992 * packet processing for this device must be stopped before this call. 993 */ 994 static void 995 fec_restart(struct net_device *ndev) 996 { 997 struct fec_enet_private *fep = netdev_priv(ndev); 998 u32 temp_mac[2]; 999 u32 rcntl = OPT_FRAME_SIZE | 0x04; 1000 u32 ecntl = 0x2; /* ETHEREN */ 1001 struct ptp_clock_request ptp_rq = { .type = PTP_CLK_REQ_PPS }; 1002 1003 fec_ptp_save_state(fep); 1004 1005 /* Whack a reset. We should wait for this. 1006 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC 1007 * instead of reset MAC itself. 1008 */ 1009 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES || 1010 ((fep->quirks & FEC_QUIRK_NO_HARD_RESET) && fep->link)) { 1011 writel(0, fep->hwp + FEC_ECNTRL); 1012 } else { 1013 writel(1, fep->hwp + FEC_ECNTRL); 1014 udelay(10); 1015 } 1016 1017 /* 1018 * enet-mac reset will reset mac address registers too, 1019 * so need to reconfigure it. 1020 */ 1021 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN); 1022 writel((__force u32)cpu_to_be32(temp_mac[0]), 1023 fep->hwp + FEC_ADDR_LOW); 1024 writel((__force u32)cpu_to_be32(temp_mac[1]), 1025 fep->hwp + FEC_ADDR_HIGH); 1026 1027 /* Clear any outstanding interrupt, except MDIO. */ 1028 writel((0xffffffff & ~FEC_ENET_MII), fep->hwp + FEC_IEVENT); 1029 1030 fec_enet_bd_init(ndev); 1031 1032 fec_enet_enable_ring(ndev); 1033 1034 /* Reset tx SKB buffers. */ 1035 fec_enet_reset_skb(ndev); 1036 1037 /* Enable MII mode */ 1038 if (fep->full_duplex == DUPLEX_FULL) { 1039 /* FD enable */ 1040 writel(0x04, fep->hwp + FEC_X_CNTRL); 1041 } else { 1042 /* No Rcv on Xmit */ 1043 rcntl |= 0x02; 1044 writel(0x0, fep->hwp + FEC_X_CNTRL); 1045 } 1046 1047 /* Set MII speed */ 1048 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1049 1050 #if !defined(CONFIG_M5272) 1051 if (fep->quirks & FEC_QUIRK_HAS_RACC) { 1052 u32 val = readl(fep->hwp + FEC_RACC); 1053 1054 /* align IP header */ 1055 val |= FEC_RACC_SHIFT16; 1056 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED) 1057 /* set RX checksum */ 1058 val |= FEC_RACC_OPTIONS; 1059 else 1060 val &= ~FEC_RACC_OPTIONS; 1061 writel(val, fep->hwp + FEC_RACC); 1062 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_FTRL); 1063 } 1064 #endif 1065 1066 /* 1067 * The phy interface and speed need to get configured 1068 * differently on enet-mac. 1069 */ 1070 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 1071 /* Enable flow control and length check */ 1072 rcntl |= 0x40000000 | 0x00000020; 1073 1074 /* RGMII, RMII or MII */ 1075 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII || 1076 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 1077 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID || 1078 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) 1079 rcntl |= (1 << 6); 1080 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 1081 rcntl |= (1 << 8); 1082 else 1083 rcntl &= ~(1 << 8); 1084 1085 /* 1G, 100M or 10M */ 1086 if (ndev->phydev) { 1087 if (ndev->phydev->speed == SPEED_1000) 1088 ecntl |= (1 << 5); 1089 else if (ndev->phydev->speed == SPEED_100) 1090 rcntl &= ~(1 << 9); 1091 else 1092 rcntl |= (1 << 9); 1093 } 1094 } else { 1095 #ifdef FEC_MIIGSK_ENR 1096 if (fep->quirks & FEC_QUIRK_USE_GASKET) { 1097 u32 cfgr; 1098 /* disable the gasket and wait */ 1099 writel(0, fep->hwp + FEC_MIIGSK_ENR); 1100 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4) 1101 udelay(1); 1102 1103 /* 1104 * configure the gasket: 1105 * RMII, 50 MHz, no loopback, no echo 1106 * MII, 25 MHz, no loopback, no echo 1107 */ 1108 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 1109 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII; 1110 if (ndev->phydev && ndev->phydev->speed == SPEED_10) 1111 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M; 1112 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR); 1113 1114 /* re-enable the gasket */ 1115 writel(2, fep->hwp + FEC_MIIGSK_ENR); 1116 } 1117 #endif 1118 } 1119 1120 #if !defined(CONFIG_M5272) 1121 /* enable pause frame*/ 1122 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) || 1123 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) && 1124 ndev->phydev && ndev->phydev->pause)) { 1125 rcntl |= FEC_ENET_FCE; 1126 1127 /* set FIFO threshold parameter to reduce overrun */ 1128 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM); 1129 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL); 1130 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM); 1131 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL); 1132 1133 /* OPD */ 1134 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD); 1135 } else { 1136 rcntl &= ~FEC_ENET_FCE; 1137 } 1138 #endif /* !defined(CONFIG_M5272) */ 1139 1140 writel(rcntl, fep->hwp + FEC_R_CNTRL); 1141 1142 /* Setup multicast filter. */ 1143 set_multicast_list(ndev); 1144 #ifndef CONFIG_M5272 1145 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); 1146 writel(0, fep->hwp + FEC_HASH_TABLE_LOW); 1147 #endif 1148 1149 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 1150 /* enable ENET endian swap */ 1151 ecntl |= (1 << 8); 1152 /* enable ENET store and forward mode */ 1153 writel(1 << 8, fep->hwp + FEC_X_WMRK); 1154 } 1155 1156 if (fep->bufdesc_ex) 1157 ecntl |= FEC_ECR_EN1588; 1158 1159 if (fep->quirks & FEC_QUIRK_DELAYED_CLKS_SUPPORT && 1160 fep->rgmii_txc_dly) 1161 ecntl |= FEC_ENET_TXC_DLY; 1162 if (fep->quirks & FEC_QUIRK_DELAYED_CLKS_SUPPORT && 1163 fep->rgmii_rxc_dly) 1164 ecntl |= FEC_ENET_RXC_DLY; 1165 1166 #ifndef CONFIG_M5272 1167 /* Enable the MIB statistic event counters */ 1168 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT); 1169 #endif 1170 1171 /* And last, enable the transmit and receive processing */ 1172 writel(ecntl, fep->hwp + FEC_ECNTRL); 1173 fec_enet_active_rxring(ndev); 1174 1175 if (fep->bufdesc_ex) 1176 fec_ptp_start_cyclecounter(ndev); 1177 1178 /* Restart PPS if needed */ 1179 if (fep->pps_enable) { 1180 /* Clear flag so fec_ptp_enable_pps() doesn't return immediately */ 1181 fep->pps_enable = 0; 1182 fec_ptp_restore_state(fep); 1183 fep->ptp_caps.enable(&fep->ptp_caps, &ptp_rq, 1); 1184 } 1185 1186 /* Enable interrupts we wish to service */ 1187 if (fep->link) 1188 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1189 else 1190 writel(0, fep->hwp + FEC_IMASK); 1191 1192 /* Init the interrupt coalescing */ 1193 fec_enet_itr_coal_init(ndev); 1194 1195 } 1196 1197 static int fec_enet_ipc_handle_init(struct fec_enet_private *fep) 1198 { 1199 if (!(of_machine_is_compatible("fsl,imx8qm") || 1200 of_machine_is_compatible("fsl,imx8qxp") || 1201 of_machine_is_compatible("fsl,imx8dxl"))) 1202 return 0; 1203 1204 return imx_scu_get_handle(&fep->ipc_handle); 1205 } 1206 1207 static void fec_enet_ipg_stop_set(struct fec_enet_private *fep, bool enabled) 1208 { 1209 struct device_node *np = fep->pdev->dev.of_node; 1210 u32 rsrc_id, val; 1211 int idx; 1212 1213 if (!np || !fep->ipc_handle) 1214 return; 1215 1216 idx = of_alias_get_id(np, "ethernet"); 1217 if (idx < 0) 1218 idx = 0; 1219 rsrc_id = idx ? IMX_SC_R_ENET_1 : IMX_SC_R_ENET_0; 1220 1221 val = enabled ? 1 : 0; 1222 imx_sc_misc_set_control(fep->ipc_handle, rsrc_id, IMX_SC_C_IPG_STOP, val); 1223 } 1224 1225 static void fec_enet_stop_mode(struct fec_enet_private *fep, bool enabled) 1226 { 1227 struct fec_platform_data *pdata = fep->pdev->dev.platform_data; 1228 struct fec_stop_mode_gpr *stop_gpr = &fep->stop_gpr; 1229 1230 if (stop_gpr->gpr) { 1231 if (enabled) 1232 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg, 1233 BIT(stop_gpr->bit), 1234 BIT(stop_gpr->bit)); 1235 else 1236 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg, 1237 BIT(stop_gpr->bit), 0); 1238 } else if (pdata && pdata->sleep_mode_enable) { 1239 pdata->sleep_mode_enable(enabled); 1240 } else { 1241 fec_enet_ipg_stop_set(fep, enabled); 1242 } 1243 } 1244 1245 static void fec_irqs_disable(struct net_device *ndev) 1246 { 1247 struct fec_enet_private *fep = netdev_priv(ndev); 1248 1249 writel(0, fep->hwp + FEC_IMASK); 1250 } 1251 1252 static void fec_irqs_disable_except_wakeup(struct net_device *ndev) 1253 { 1254 struct fec_enet_private *fep = netdev_priv(ndev); 1255 1256 writel(0, fep->hwp + FEC_IMASK); 1257 writel(FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK); 1258 } 1259 1260 static void 1261 fec_stop(struct net_device *ndev) 1262 { 1263 struct fec_enet_private *fep = netdev_priv(ndev); 1264 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8); 1265 u32 val; 1266 struct ptp_clock_request ptp_rq = { .type = PTP_CLK_REQ_PPS }; 1267 u32 ecntl = 0; 1268 1269 /* We cannot expect a graceful transmit stop without link !!! */ 1270 if (fep->link) { 1271 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ 1272 udelay(10); 1273 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) 1274 netdev_err(ndev, "Graceful transmit stop did not complete!\n"); 1275 } 1276 1277 fec_ptp_save_state(fep); 1278 1279 /* Whack a reset. We should wait for this. 1280 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC 1281 * instead of reset MAC itself. 1282 */ 1283 if (!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1284 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) { 1285 writel(0, fep->hwp + FEC_ECNTRL); 1286 } else { 1287 writel(1, fep->hwp + FEC_ECNTRL); 1288 udelay(10); 1289 } 1290 } else { 1291 val = readl(fep->hwp + FEC_ECNTRL); 1292 val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP); 1293 writel(val, fep->hwp + FEC_ECNTRL); 1294 } 1295 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1296 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1297 1298 if (fep->bufdesc_ex) 1299 ecntl |= FEC_ECR_EN1588; 1300 1301 /* We have to keep ENET enabled to have MII interrupt stay working */ 1302 if (fep->quirks & FEC_QUIRK_ENET_MAC && 1303 !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1304 ecntl |= FEC_ECR_ETHEREN; 1305 writel(rmii_mode, fep->hwp + FEC_R_CNTRL); 1306 } 1307 1308 writel(ecntl, fep->hwp + FEC_ECNTRL); 1309 1310 if (fep->bufdesc_ex) 1311 fec_ptp_start_cyclecounter(ndev); 1312 1313 /* Restart PPS if needed */ 1314 if (fep->pps_enable) { 1315 /* Clear flag so fec_ptp_enable_pps() doesn't return immediately */ 1316 fep->pps_enable = 0; 1317 fec_ptp_restore_state(fep); 1318 fep->ptp_caps.enable(&fep->ptp_caps, &ptp_rq, 1); 1319 } 1320 } 1321 1322 1323 static void 1324 fec_timeout(struct net_device *ndev, unsigned int txqueue) 1325 { 1326 struct fec_enet_private *fep = netdev_priv(ndev); 1327 1328 fec_dump(ndev); 1329 1330 ndev->stats.tx_errors++; 1331 1332 schedule_work(&fep->tx_timeout_work); 1333 } 1334 1335 static void fec_enet_timeout_work(struct work_struct *work) 1336 { 1337 struct fec_enet_private *fep = 1338 container_of(work, struct fec_enet_private, tx_timeout_work); 1339 struct net_device *ndev = fep->netdev; 1340 1341 rtnl_lock(); 1342 if (netif_device_present(ndev) || netif_running(ndev)) { 1343 napi_disable(&fep->napi); 1344 netif_tx_lock_bh(ndev); 1345 fec_restart(ndev); 1346 netif_tx_wake_all_queues(ndev); 1347 netif_tx_unlock_bh(ndev); 1348 napi_enable(&fep->napi); 1349 } 1350 rtnl_unlock(); 1351 } 1352 1353 static void 1354 fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts, 1355 struct skb_shared_hwtstamps *hwtstamps) 1356 { 1357 unsigned long flags; 1358 u64 ns; 1359 1360 spin_lock_irqsave(&fep->tmreg_lock, flags); 1361 ns = timecounter_cyc2time(&fep->tc, ts); 1362 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 1363 1364 memset(hwtstamps, 0, sizeof(*hwtstamps)); 1365 hwtstamps->hwtstamp = ns_to_ktime(ns); 1366 } 1367 1368 static void 1369 fec_enet_tx_queue(struct net_device *ndev, u16 queue_id) 1370 { 1371 struct fec_enet_private *fep; 1372 struct bufdesc *bdp; 1373 unsigned short status; 1374 struct sk_buff *skb; 1375 struct fec_enet_priv_tx_q *txq; 1376 struct netdev_queue *nq; 1377 int index = 0; 1378 int entries_free; 1379 1380 fep = netdev_priv(ndev); 1381 1382 txq = fep->tx_queue[queue_id]; 1383 /* get next bdp of dirty_tx */ 1384 nq = netdev_get_tx_queue(ndev, queue_id); 1385 bdp = txq->dirty_tx; 1386 1387 /* get next bdp of dirty_tx */ 1388 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1389 1390 while (bdp != READ_ONCE(txq->bd.cur)) { 1391 /* Order the load of bd.cur and cbd_sc */ 1392 rmb(); 1393 status = fec16_to_cpu(READ_ONCE(bdp->cbd_sc)); 1394 if (status & BD_ENET_TX_READY) 1395 break; 1396 1397 index = fec_enet_get_bd_index(bdp, &txq->bd); 1398 1399 skb = txq->tx_skbuff[index]; 1400 txq->tx_skbuff[index] = NULL; 1401 if (!IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr))) 1402 dma_unmap_single(&fep->pdev->dev, 1403 fec32_to_cpu(bdp->cbd_bufaddr), 1404 fec16_to_cpu(bdp->cbd_datlen), 1405 DMA_TO_DEVICE); 1406 bdp->cbd_bufaddr = cpu_to_fec32(0); 1407 if (!skb) 1408 goto skb_done; 1409 1410 /* Check for errors. */ 1411 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | 1412 BD_ENET_TX_RL | BD_ENET_TX_UN | 1413 BD_ENET_TX_CSL)) { 1414 ndev->stats.tx_errors++; 1415 if (status & BD_ENET_TX_HB) /* No heartbeat */ 1416 ndev->stats.tx_heartbeat_errors++; 1417 if (status & BD_ENET_TX_LC) /* Late collision */ 1418 ndev->stats.tx_window_errors++; 1419 if (status & BD_ENET_TX_RL) /* Retrans limit */ 1420 ndev->stats.tx_aborted_errors++; 1421 if (status & BD_ENET_TX_UN) /* Underrun */ 1422 ndev->stats.tx_fifo_errors++; 1423 if (status & BD_ENET_TX_CSL) /* Carrier lost */ 1424 ndev->stats.tx_carrier_errors++; 1425 } else { 1426 ndev->stats.tx_packets++; 1427 ndev->stats.tx_bytes += skb->len; 1428 } 1429 1430 /* NOTE: SKBTX_IN_PROGRESS being set does not imply it's we who 1431 * are to time stamp the packet, so we still need to check time 1432 * stamping enabled flag. 1433 */ 1434 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS && 1435 fep->hwts_tx_en) && 1436 fep->bufdesc_ex) { 1437 struct skb_shared_hwtstamps shhwtstamps; 1438 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1439 1440 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), &shhwtstamps); 1441 skb_tstamp_tx(skb, &shhwtstamps); 1442 } 1443 1444 /* Deferred means some collisions occurred during transmit, 1445 * but we eventually sent the packet OK. 1446 */ 1447 if (status & BD_ENET_TX_DEF) 1448 ndev->stats.collisions++; 1449 1450 /* Free the sk buffer associated with this last transmit */ 1451 dev_kfree_skb_any(skb); 1452 skb_done: 1453 /* Make sure the update to bdp and tx_skbuff are performed 1454 * before dirty_tx 1455 */ 1456 wmb(); 1457 txq->dirty_tx = bdp; 1458 1459 /* Update pointer to next buffer descriptor to be transmitted */ 1460 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1461 1462 /* Since we have freed up a buffer, the ring is no longer full 1463 */ 1464 if (netif_tx_queue_stopped(nq)) { 1465 entries_free = fec_enet_get_free_txdesc_num(txq); 1466 if (entries_free >= txq->tx_wake_threshold) 1467 netif_tx_wake_queue(nq); 1468 } 1469 } 1470 1471 /* ERR006358: Keep the transmitter going */ 1472 if (bdp != txq->bd.cur && 1473 readl(txq->bd.reg_desc_active) == 0) 1474 writel(0, txq->bd.reg_desc_active); 1475 } 1476 1477 static void fec_enet_tx(struct net_device *ndev) 1478 { 1479 struct fec_enet_private *fep = netdev_priv(ndev); 1480 int i; 1481 1482 /* Make sure that AVB queues are processed first. */ 1483 for (i = fep->num_tx_queues - 1; i >= 0; i--) 1484 fec_enet_tx_queue(ndev, i); 1485 } 1486 1487 static int 1488 fec_enet_new_rxbdp(struct net_device *ndev, struct bufdesc *bdp, struct sk_buff *skb) 1489 { 1490 struct fec_enet_private *fep = netdev_priv(ndev); 1491 int off; 1492 1493 off = ((unsigned long)skb->data) & fep->rx_align; 1494 if (off) 1495 skb_reserve(skb, fep->rx_align + 1 - off); 1496 1497 bdp->cbd_bufaddr = cpu_to_fec32(dma_map_single(&fep->pdev->dev, skb->data, FEC_ENET_RX_FRSIZE - fep->rx_align, DMA_FROM_DEVICE)); 1498 if (dma_mapping_error(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr))) { 1499 if (net_ratelimit()) 1500 netdev_err(ndev, "Rx DMA memory map failed\n"); 1501 return -ENOMEM; 1502 } 1503 1504 return 0; 1505 } 1506 1507 static bool fec_enet_copybreak(struct net_device *ndev, struct sk_buff **skb, 1508 struct bufdesc *bdp, u32 length, bool swap) 1509 { 1510 struct fec_enet_private *fep = netdev_priv(ndev); 1511 struct sk_buff *new_skb; 1512 1513 if (length > fep->rx_copybreak) 1514 return false; 1515 1516 new_skb = netdev_alloc_skb(ndev, length); 1517 if (!new_skb) 1518 return false; 1519 1520 dma_sync_single_for_cpu(&fep->pdev->dev, 1521 fec32_to_cpu(bdp->cbd_bufaddr), 1522 FEC_ENET_RX_FRSIZE - fep->rx_align, 1523 DMA_FROM_DEVICE); 1524 if (!swap) 1525 memcpy(new_skb->data, (*skb)->data, length); 1526 else 1527 swap_buffer2(new_skb->data, (*skb)->data, length); 1528 *skb = new_skb; 1529 1530 return true; 1531 } 1532 1533 /* During a receive, the bd_rx.cur points to the current incoming buffer. 1534 * When we update through the ring, if the next incoming buffer has 1535 * not been given to the system, we just set the empty indicator, 1536 * effectively tossing the packet. 1537 */ 1538 static int 1539 fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id) 1540 { 1541 struct fec_enet_private *fep = netdev_priv(ndev); 1542 struct fec_enet_priv_rx_q *rxq; 1543 struct bufdesc *bdp; 1544 unsigned short status; 1545 struct sk_buff *skb_new = NULL; 1546 struct sk_buff *skb; 1547 ushort pkt_len; 1548 __u8 *data; 1549 int pkt_received = 0; 1550 struct bufdesc_ex *ebdp = NULL; 1551 bool vlan_packet_rcvd = false; 1552 u16 vlan_tag; 1553 int index = 0; 1554 bool is_copybreak; 1555 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME; 1556 1557 #ifdef CONFIG_M532x 1558 flush_cache_all(); 1559 #endif 1560 rxq = fep->rx_queue[queue_id]; 1561 1562 /* First, grab all of the stats for the incoming packet. 1563 * These get messed up if we get called due to a busy condition. 1564 */ 1565 bdp = rxq->bd.cur; 1566 1567 while (!((status = fec16_to_cpu(bdp->cbd_sc)) & BD_ENET_RX_EMPTY)) { 1568 1569 if (pkt_received >= budget) 1570 break; 1571 pkt_received++; 1572 1573 writel(FEC_ENET_RXF_GET(queue_id), fep->hwp + FEC_IEVENT); 1574 1575 /* Check for errors. */ 1576 status ^= BD_ENET_RX_LAST; 1577 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | 1578 BD_ENET_RX_CR | BD_ENET_RX_OV | BD_ENET_RX_LAST | 1579 BD_ENET_RX_CL)) { 1580 ndev->stats.rx_errors++; 1581 if (status & BD_ENET_RX_OV) { 1582 /* FIFO overrun */ 1583 ndev->stats.rx_fifo_errors++; 1584 goto rx_processing_done; 1585 } 1586 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH 1587 | BD_ENET_RX_LAST)) { 1588 /* Frame too long or too short. */ 1589 ndev->stats.rx_length_errors++; 1590 if (status & BD_ENET_RX_LAST) 1591 netdev_err(ndev, "rcv is not +last\n"); 1592 } 1593 if (status & BD_ENET_RX_CR) /* CRC Error */ 1594 ndev->stats.rx_crc_errors++; 1595 /* Report late collisions as a frame error. */ 1596 if (status & (BD_ENET_RX_NO | BD_ENET_RX_CL)) 1597 ndev->stats.rx_frame_errors++; 1598 goto rx_processing_done; 1599 } 1600 1601 /* Process the incoming frame. */ 1602 ndev->stats.rx_packets++; 1603 pkt_len = fec16_to_cpu(bdp->cbd_datlen); 1604 ndev->stats.rx_bytes += pkt_len; 1605 1606 index = fec_enet_get_bd_index(bdp, &rxq->bd); 1607 skb = rxq->rx_skbuff[index]; 1608 1609 /* The packet length includes FCS, but we don't want to 1610 * include that when passing upstream as it messes up 1611 * bridging applications. 1612 */ 1613 is_copybreak = fec_enet_copybreak(ndev, &skb, bdp, pkt_len - 4, 1614 need_swap); 1615 if (!is_copybreak) { 1616 skb_new = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE); 1617 if (unlikely(!skb_new)) { 1618 ndev->stats.rx_dropped++; 1619 goto rx_processing_done; 1620 } 1621 dma_unmap_single(&fep->pdev->dev, 1622 fec32_to_cpu(bdp->cbd_bufaddr), 1623 FEC_ENET_RX_FRSIZE - fep->rx_align, 1624 DMA_FROM_DEVICE); 1625 } 1626 1627 prefetch(skb->data - NET_IP_ALIGN); 1628 skb_put(skb, pkt_len - 4); 1629 data = skb->data; 1630 1631 if (!is_copybreak && need_swap) 1632 swap_buffer(data, pkt_len); 1633 1634 #if !defined(CONFIG_M5272) 1635 if (fep->quirks & FEC_QUIRK_HAS_RACC) 1636 data = skb_pull_inline(skb, 2); 1637 #endif 1638 1639 /* Extract the enhanced buffer descriptor */ 1640 ebdp = NULL; 1641 if (fep->bufdesc_ex) 1642 ebdp = (struct bufdesc_ex *)bdp; 1643 1644 /* If this is a VLAN packet remove the VLAN Tag */ 1645 vlan_packet_rcvd = false; 1646 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) && 1647 fep->bufdesc_ex && 1648 (ebdp->cbd_esc & cpu_to_fec32(BD_ENET_RX_VLAN))) { 1649 /* Push and remove the vlan tag */ 1650 struct vlan_hdr *vlan_header = 1651 (struct vlan_hdr *) (data + ETH_HLEN); 1652 vlan_tag = ntohs(vlan_header->h_vlan_TCI); 1653 1654 vlan_packet_rcvd = true; 1655 1656 memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2); 1657 skb_pull(skb, VLAN_HLEN); 1658 } 1659 1660 skb->protocol = eth_type_trans(skb, ndev); 1661 1662 /* Get receive timestamp from the skb */ 1663 if (fep->hwts_rx_en && fep->bufdesc_ex) 1664 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), 1665 skb_hwtstamps(skb)); 1666 1667 if (fep->bufdesc_ex && 1668 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) { 1669 if (!(ebdp->cbd_esc & cpu_to_fec32(FLAG_RX_CSUM_ERROR))) { 1670 /* don't check it */ 1671 skb->ip_summed = CHECKSUM_UNNECESSARY; 1672 } else { 1673 skb_checksum_none_assert(skb); 1674 } 1675 } 1676 1677 /* Handle received VLAN packets */ 1678 if (vlan_packet_rcvd) 1679 __vlan_hwaccel_put_tag(skb, 1680 htons(ETH_P_8021Q), 1681 vlan_tag); 1682 1683 skb_record_rx_queue(skb, queue_id); 1684 napi_gro_receive(&fep->napi, skb); 1685 1686 if (is_copybreak) { 1687 dma_sync_single_for_device(&fep->pdev->dev, 1688 fec32_to_cpu(bdp->cbd_bufaddr), 1689 FEC_ENET_RX_FRSIZE - fep->rx_align, 1690 DMA_FROM_DEVICE); 1691 } else { 1692 rxq->rx_skbuff[index] = skb_new; 1693 fec_enet_new_rxbdp(ndev, bdp, skb_new); 1694 } 1695 1696 rx_processing_done: 1697 /* Clear the status flags for this buffer */ 1698 status &= ~BD_ENET_RX_STATS; 1699 1700 /* Mark the buffer empty */ 1701 status |= BD_ENET_RX_EMPTY; 1702 1703 if (fep->bufdesc_ex) { 1704 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1705 1706 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); 1707 ebdp->cbd_prot = 0; 1708 ebdp->cbd_bdu = 0; 1709 } 1710 /* Make sure the updates to rest of the descriptor are 1711 * performed before transferring ownership. 1712 */ 1713 wmb(); 1714 bdp->cbd_sc = cpu_to_fec16(status); 1715 1716 /* Update BD pointer to next entry */ 1717 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 1718 1719 /* Doing this here will keep the FEC running while we process 1720 * incoming frames. On a heavily loaded network, we should be 1721 * able to keep up at the expense of system resources. 1722 */ 1723 writel(0, rxq->bd.reg_desc_active); 1724 } 1725 rxq->bd.cur = bdp; 1726 return pkt_received; 1727 } 1728 1729 static int fec_enet_rx(struct net_device *ndev, int budget) 1730 { 1731 struct fec_enet_private *fep = netdev_priv(ndev); 1732 int i, done = 0; 1733 1734 /* Make sure that AVB queues are processed first. */ 1735 for (i = fep->num_rx_queues - 1; i >= 0; i--) 1736 done += fec_enet_rx_queue(ndev, budget - done, i); 1737 1738 return done; 1739 } 1740 1741 static bool fec_enet_collect_events(struct fec_enet_private *fep) 1742 { 1743 uint int_events; 1744 1745 int_events = readl(fep->hwp + FEC_IEVENT); 1746 1747 /* Don't clear MDIO events, we poll for those */ 1748 int_events &= ~FEC_ENET_MII; 1749 1750 writel(int_events, fep->hwp + FEC_IEVENT); 1751 1752 return int_events != 0; 1753 } 1754 1755 static irqreturn_t 1756 fec_enet_interrupt(int irq, void *dev_id) 1757 { 1758 struct net_device *ndev = dev_id; 1759 struct fec_enet_private *fep = netdev_priv(ndev); 1760 irqreturn_t ret = IRQ_NONE; 1761 1762 if (fec_enet_collect_events(fep) && fep->link) { 1763 ret = IRQ_HANDLED; 1764 1765 if (napi_schedule_prep(&fep->napi)) { 1766 /* Disable interrupts */ 1767 writel(0, fep->hwp + FEC_IMASK); 1768 __napi_schedule(&fep->napi); 1769 } 1770 } 1771 1772 return ret; 1773 } 1774 1775 static int fec_enet_rx_napi(struct napi_struct *napi, int budget) 1776 { 1777 struct net_device *ndev = napi->dev; 1778 struct fec_enet_private *fep = netdev_priv(ndev); 1779 int done = 0; 1780 1781 do { 1782 done += fec_enet_rx(ndev, budget - done); 1783 fec_enet_tx(ndev); 1784 } while ((done < budget) && fec_enet_collect_events(fep)); 1785 1786 if (done < budget) { 1787 napi_complete_done(napi, done); 1788 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1789 } 1790 1791 return done; 1792 } 1793 1794 /* ------------------------------------------------------------------------- */ 1795 static int fec_get_mac(struct net_device *ndev) 1796 { 1797 struct fec_enet_private *fep = netdev_priv(ndev); 1798 unsigned char *iap, tmpaddr[ETH_ALEN]; 1799 int ret; 1800 1801 /* 1802 * try to get mac address in following order: 1803 * 1804 * 1) module parameter via kernel command line in form 1805 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0 1806 */ 1807 iap = macaddr; 1808 1809 /* 1810 * 2) from device tree data 1811 */ 1812 if (!is_valid_ether_addr(iap)) { 1813 struct device_node *np = fep->pdev->dev.of_node; 1814 if (np) { 1815 ret = of_get_mac_address(np, tmpaddr); 1816 if (!ret) 1817 iap = tmpaddr; 1818 else if (ret == -EPROBE_DEFER) 1819 return ret; 1820 } 1821 } 1822 1823 /* 1824 * 3) from flash or fuse (via platform data) 1825 */ 1826 if (!is_valid_ether_addr(iap)) { 1827 #ifdef CONFIG_M5272 1828 if (FEC_FLASHMAC) 1829 iap = (unsigned char *)FEC_FLASHMAC; 1830 #else 1831 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev); 1832 1833 if (pdata) 1834 iap = (unsigned char *)&pdata->mac; 1835 #endif 1836 } 1837 1838 /* 1839 * 4) FEC mac registers set by bootloader 1840 */ 1841 if (!is_valid_ether_addr(iap)) { 1842 *((__be32 *) &tmpaddr[0]) = 1843 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW)); 1844 *((__be16 *) &tmpaddr[4]) = 1845 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16); 1846 iap = &tmpaddr[0]; 1847 } 1848 1849 /* 1850 * 5) random mac address 1851 */ 1852 if (!is_valid_ether_addr(iap)) { 1853 /* Report it and use a random ethernet address instead */ 1854 dev_err(&fep->pdev->dev, "Invalid MAC address: %pM\n", iap); 1855 eth_hw_addr_random(ndev); 1856 dev_info(&fep->pdev->dev, "Using random MAC address: %pM\n", 1857 ndev->dev_addr); 1858 return 0; 1859 } 1860 1861 /* Adjust MAC if using macaddr */ 1862 eth_hw_addr_gen(ndev, iap, iap == macaddr ? fep->dev_id : 0); 1863 1864 return 0; 1865 } 1866 1867 /* ------------------------------------------------------------------------- */ 1868 1869 /* 1870 * Phy section 1871 */ 1872 static void fec_enet_adjust_link(struct net_device *ndev) 1873 { 1874 struct fec_enet_private *fep = netdev_priv(ndev); 1875 struct phy_device *phy_dev = ndev->phydev; 1876 int status_change = 0; 1877 1878 /* 1879 * If the netdev is down, or is going down, we're not interested 1880 * in link state events, so just mark our idea of the link as down 1881 * and ignore the event. 1882 */ 1883 if (!netif_running(ndev) || !netif_device_present(ndev)) { 1884 fep->link = 0; 1885 } else if (phy_dev->link) { 1886 if (!fep->link) { 1887 fep->link = phy_dev->link; 1888 status_change = 1; 1889 } 1890 1891 if (fep->full_duplex != phy_dev->duplex) { 1892 fep->full_duplex = phy_dev->duplex; 1893 status_change = 1; 1894 } 1895 1896 if (phy_dev->speed != fep->speed) { 1897 fep->speed = phy_dev->speed; 1898 status_change = 1; 1899 } 1900 1901 /* if any of the above changed restart the FEC */ 1902 if (status_change) { 1903 napi_disable(&fep->napi); 1904 netif_tx_lock_bh(ndev); 1905 fec_restart(ndev); 1906 netif_tx_wake_all_queues(ndev); 1907 netif_tx_unlock_bh(ndev); 1908 napi_enable(&fep->napi); 1909 } 1910 } else { 1911 if (fep->link) { 1912 napi_disable(&fep->napi); 1913 netif_tx_lock_bh(ndev); 1914 fec_stop(ndev); 1915 netif_tx_unlock_bh(ndev); 1916 napi_enable(&fep->napi); 1917 fep->link = phy_dev->link; 1918 status_change = 1; 1919 } 1920 } 1921 1922 if (status_change) 1923 phy_print_status(phy_dev); 1924 } 1925 1926 static int fec_enet_mdio_wait(struct fec_enet_private *fep) 1927 { 1928 uint ievent; 1929 int ret; 1930 1931 ret = readl_poll_timeout_atomic(fep->hwp + FEC_IEVENT, ievent, 1932 ievent & FEC_ENET_MII, 2, 30000); 1933 1934 if (!ret) 1935 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); 1936 1937 return ret; 1938 } 1939 1940 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) 1941 { 1942 struct fec_enet_private *fep = bus->priv; 1943 struct device *dev = &fep->pdev->dev; 1944 int ret = 0, frame_start, frame_addr, frame_op; 1945 bool is_c45 = !!(regnum & MII_ADDR_C45); 1946 1947 ret = pm_runtime_resume_and_get(dev); 1948 if (ret < 0) 1949 return ret; 1950 1951 if (is_c45) { 1952 frame_start = FEC_MMFR_ST_C45; 1953 1954 /* write address */ 1955 frame_addr = (regnum >> 16); 1956 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE | 1957 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 1958 FEC_MMFR_TA | (regnum & 0xFFFF), 1959 fep->hwp + FEC_MII_DATA); 1960 1961 /* wait for end of transfer */ 1962 ret = fec_enet_mdio_wait(fep); 1963 if (ret) { 1964 netdev_err(fep->netdev, "MDIO address write timeout\n"); 1965 goto out; 1966 } 1967 1968 frame_op = FEC_MMFR_OP_READ_C45; 1969 1970 } else { 1971 /* C22 read */ 1972 frame_op = FEC_MMFR_OP_READ; 1973 frame_start = FEC_MMFR_ST; 1974 frame_addr = regnum; 1975 } 1976 1977 /* start a read op */ 1978 writel(frame_start | frame_op | 1979 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 1980 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); 1981 1982 /* wait for end of transfer */ 1983 ret = fec_enet_mdio_wait(fep); 1984 if (ret) { 1985 netdev_err(fep->netdev, "MDIO read timeout\n"); 1986 goto out; 1987 } 1988 1989 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); 1990 1991 out: 1992 pm_runtime_mark_last_busy(dev); 1993 pm_runtime_put_autosuspend(dev); 1994 1995 return ret; 1996 } 1997 1998 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, 1999 u16 value) 2000 { 2001 struct fec_enet_private *fep = bus->priv; 2002 struct device *dev = &fep->pdev->dev; 2003 int ret, frame_start, frame_addr; 2004 bool is_c45 = !!(regnum & MII_ADDR_C45); 2005 2006 ret = pm_runtime_resume_and_get(dev); 2007 if (ret < 0) 2008 return ret; 2009 2010 if (is_c45) { 2011 frame_start = FEC_MMFR_ST_C45; 2012 2013 /* write address */ 2014 frame_addr = (regnum >> 16); 2015 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE | 2016 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 2017 FEC_MMFR_TA | (regnum & 0xFFFF), 2018 fep->hwp + FEC_MII_DATA); 2019 2020 /* wait for end of transfer */ 2021 ret = fec_enet_mdio_wait(fep); 2022 if (ret) { 2023 netdev_err(fep->netdev, "MDIO address write timeout\n"); 2024 goto out; 2025 } 2026 } else { 2027 /* C22 write */ 2028 frame_start = FEC_MMFR_ST; 2029 frame_addr = regnum; 2030 } 2031 2032 /* start a write op */ 2033 writel(frame_start | FEC_MMFR_OP_WRITE | 2034 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 2035 FEC_MMFR_TA | FEC_MMFR_DATA(value), 2036 fep->hwp + FEC_MII_DATA); 2037 2038 /* wait for end of transfer */ 2039 ret = fec_enet_mdio_wait(fep); 2040 if (ret) 2041 netdev_err(fep->netdev, "MDIO write timeout\n"); 2042 2043 out: 2044 pm_runtime_mark_last_busy(dev); 2045 pm_runtime_put_autosuspend(dev); 2046 2047 return ret; 2048 } 2049 2050 static void fec_enet_phy_reset_after_clk_enable(struct net_device *ndev) 2051 { 2052 struct fec_enet_private *fep = netdev_priv(ndev); 2053 struct phy_device *phy_dev = ndev->phydev; 2054 2055 if (phy_dev) { 2056 phy_reset_after_clk_enable(phy_dev); 2057 } else if (fep->phy_node) { 2058 /* 2059 * If the PHY still is not bound to the MAC, but there is 2060 * OF PHY node and a matching PHY device instance already, 2061 * use the OF PHY node to obtain the PHY device instance, 2062 * and then use that PHY device instance when triggering 2063 * the PHY reset. 2064 */ 2065 phy_dev = of_phy_find_device(fep->phy_node); 2066 phy_reset_after_clk_enable(phy_dev); 2067 put_device(&phy_dev->mdio.dev); 2068 } 2069 } 2070 2071 static int fec_enet_clk_enable(struct net_device *ndev, bool enable) 2072 { 2073 struct fec_enet_private *fep = netdev_priv(ndev); 2074 unsigned long flags; 2075 int ret; 2076 2077 if (enable) { 2078 ret = clk_prepare_enable(fep->clk_enet_out); 2079 if (ret) 2080 return ret; 2081 2082 if (fep->clk_ptp) { 2083 spin_lock_irqsave(&fep->tmreg_lock, flags); 2084 ret = clk_prepare_enable(fep->clk_ptp); 2085 if (ret) { 2086 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 2087 goto failed_clk_ptp; 2088 } else { 2089 fep->ptp_clk_on = true; 2090 } 2091 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 2092 } 2093 2094 ret = clk_prepare_enable(fep->clk_ref); 2095 if (ret) 2096 goto failed_clk_ref; 2097 2098 ret = clk_prepare_enable(fep->clk_2x_txclk); 2099 if (ret) 2100 goto failed_clk_2x_txclk; 2101 2102 fec_enet_phy_reset_after_clk_enable(ndev); 2103 } else { 2104 clk_disable_unprepare(fep->clk_enet_out); 2105 if (fep->clk_ptp) { 2106 spin_lock_irqsave(&fep->tmreg_lock, flags); 2107 clk_disable_unprepare(fep->clk_ptp); 2108 fep->ptp_clk_on = false; 2109 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 2110 } 2111 clk_disable_unprepare(fep->clk_ref); 2112 clk_disable_unprepare(fep->clk_2x_txclk); 2113 } 2114 2115 return 0; 2116 2117 failed_clk_2x_txclk: 2118 if (fep->clk_ref) 2119 clk_disable_unprepare(fep->clk_ref); 2120 failed_clk_ref: 2121 if (fep->clk_ptp) { 2122 spin_lock_irqsave(&fep->tmreg_lock, flags); 2123 clk_disable_unprepare(fep->clk_ptp); 2124 fep->ptp_clk_on = false; 2125 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 2126 } 2127 failed_clk_ptp: 2128 clk_disable_unprepare(fep->clk_enet_out); 2129 2130 return ret; 2131 } 2132 2133 static int fec_enet_parse_rgmii_delay(struct fec_enet_private *fep, 2134 struct device_node *np) 2135 { 2136 u32 rgmii_tx_delay, rgmii_rx_delay; 2137 2138 /* For rgmii tx internal delay, valid values are 0ps and 2000ps */ 2139 if (!of_property_read_u32(np, "tx-internal-delay-ps", &rgmii_tx_delay)) { 2140 if (rgmii_tx_delay != 0 && rgmii_tx_delay != 2000) { 2141 dev_err(&fep->pdev->dev, "The only allowed RGMII TX delay values are: 0ps, 2000ps"); 2142 return -EINVAL; 2143 } else if (rgmii_tx_delay == 2000) { 2144 fep->rgmii_txc_dly = true; 2145 } 2146 } 2147 2148 /* For rgmii rx internal delay, valid values are 0ps and 2000ps */ 2149 if (!of_property_read_u32(np, "rx-internal-delay-ps", &rgmii_rx_delay)) { 2150 if (rgmii_rx_delay != 0 && rgmii_rx_delay != 2000) { 2151 dev_err(&fep->pdev->dev, "The only allowed RGMII RX delay values are: 0ps, 2000ps"); 2152 return -EINVAL; 2153 } else if (rgmii_rx_delay == 2000) { 2154 fep->rgmii_rxc_dly = true; 2155 } 2156 } 2157 2158 return 0; 2159 } 2160 2161 static int fec_enet_mii_probe(struct net_device *ndev) 2162 { 2163 struct fec_enet_private *fep = netdev_priv(ndev); 2164 struct phy_device *phy_dev = NULL; 2165 char mdio_bus_id[MII_BUS_ID_SIZE]; 2166 char phy_name[MII_BUS_ID_SIZE + 3]; 2167 int phy_id; 2168 int dev_id = fep->dev_id; 2169 2170 if (fep->phy_node) { 2171 phy_dev = of_phy_connect(ndev, fep->phy_node, 2172 &fec_enet_adjust_link, 0, 2173 fep->phy_interface); 2174 if (!phy_dev) { 2175 netdev_err(ndev, "Unable to connect to phy\n"); 2176 return -ENODEV; 2177 } 2178 } else { 2179 /* check for attached phy */ 2180 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) { 2181 if (!mdiobus_is_registered_device(fep->mii_bus, phy_id)) 2182 continue; 2183 if (dev_id--) 2184 continue; 2185 strscpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE); 2186 break; 2187 } 2188 2189 if (phy_id >= PHY_MAX_ADDR) { 2190 netdev_info(ndev, "no PHY, assuming direct connection to switch\n"); 2191 strscpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); 2192 phy_id = 0; 2193 } 2194 2195 snprintf(phy_name, sizeof(phy_name), 2196 PHY_ID_FMT, mdio_bus_id, phy_id); 2197 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, 2198 fep->phy_interface); 2199 } 2200 2201 if (IS_ERR(phy_dev)) { 2202 netdev_err(ndev, "could not attach to PHY\n"); 2203 return PTR_ERR(phy_dev); 2204 } 2205 2206 /* mask with MAC supported features */ 2207 if (fep->quirks & FEC_QUIRK_HAS_GBIT) { 2208 phy_set_max_speed(phy_dev, 1000); 2209 phy_remove_link_mode(phy_dev, 2210 ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 2211 #if !defined(CONFIG_M5272) 2212 phy_support_sym_pause(phy_dev); 2213 #endif 2214 } 2215 else 2216 phy_set_max_speed(phy_dev, 100); 2217 2218 fep->link = 0; 2219 fep->full_duplex = 0; 2220 2221 phy_dev->mac_managed_pm = 1; 2222 2223 phy_attached_info(phy_dev); 2224 2225 return 0; 2226 } 2227 2228 static int fec_enet_mii_init(struct platform_device *pdev) 2229 { 2230 static struct mii_bus *fec0_mii_bus; 2231 struct net_device *ndev = platform_get_drvdata(pdev); 2232 struct fec_enet_private *fep = netdev_priv(ndev); 2233 bool suppress_preamble = false; 2234 struct device_node *node; 2235 int err = -ENXIO; 2236 u32 mii_speed, holdtime; 2237 u32 bus_freq; 2238 2239 /* 2240 * The i.MX28 dual fec interfaces are not equal. 2241 * Here are the differences: 2242 * 2243 * - fec0 supports MII & RMII modes while fec1 only supports RMII 2244 * - fec0 acts as the 1588 time master while fec1 is slave 2245 * - external phys can only be configured by fec0 2246 * 2247 * That is to say fec1 can not work independently. It only works 2248 * when fec0 is working. The reason behind this design is that the 2249 * second interface is added primarily for Switch mode. 2250 * 2251 * Because of the last point above, both phys are attached on fec0 2252 * mdio interface in board design, and need to be configured by 2253 * fec0 mii_bus. 2254 */ 2255 if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) { 2256 /* fec1 uses fec0 mii_bus */ 2257 if (mii_cnt && fec0_mii_bus) { 2258 fep->mii_bus = fec0_mii_bus; 2259 mii_cnt++; 2260 return 0; 2261 } 2262 return -ENOENT; 2263 } 2264 2265 bus_freq = 2500000; /* 2.5MHz by default */ 2266 node = of_get_child_by_name(pdev->dev.of_node, "mdio"); 2267 if (node) { 2268 of_property_read_u32(node, "clock-frequency", &bus_freq); 2269 suppress_preamble = of_property_read_bool(node, 2270 "suppress-preamble"); 2271 } 2272 2273 /* 2274 * Set MII speed (= clk_get_rate() / 2 * phy_speed) 2275 * 2276 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while 2277 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28 2278 * Reference Manual has an error on this, and gets fixed on i.MX6Q 2279 * document. 2280 */ 2281 mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), bus_freq * 2); 2282 if (fep->quirks & FEC_QUIRK_ENET_MAC) 2283 mii_speed--; 2284 if (mii_speed > 63) { 2285 dev_err(&pdev->dev, 2286 "fec clock (%lu) too fast to get right mii speed\n", 2287 clk_get_rate(fep->clk_ipg)); 2288 err = -EINVAL; 2289 goto err_out; 2290 } 2291 2292 /* 2293 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka 2294 * MII_SPEED) register that defines the MDIO output hold time. Earlier 2295 * versions are RAZ there, so just ignore the difference and write the 2296 * register always. 2297 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns. 2298 * HOLDTIME + 1 is the number of clk cycles the fec is holding the 2299 * output. 2300 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive). 2301 * Given that ceil(clkrate / 5000000) <= 64, the calculation for 2302 * holdtime cannot result in a value greater than 3. 2303 */ 2304 holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1; 2305 2306 fep->phy_speed = mii_speed << 1 | holdtime << 8; 2307 2308 if (suppress_preamble) 2309 fep->phy_speed |= BIT(7); 2310 2311 if (fep->quirks & FEC_QUIRK_CLEAR_SETUP_MII) { 2312 /* Clear MMFR to avoid to generate MII event by writing MSCR. 2313 * MII event generation condition: 2314 * - writing MSCR: 2315 * - mmfr[31:0]_not_zero & mscr[7:0]_is_zero & 2316 * mscr_reg_data_in[7:0] != 0 2317 * - writing MMFR: 2318 * - mscr[7:0]_not_zero 2319 */ 2320 writel(0, fep->hwp + FEC_MII_DATA); 2321 } 2322 2323 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 2324 2325 /* Clear any pending transaction complete indication */ 2326 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); 2327 2328 fep->mii_bus = mdiobus_alloc(); 2329 if (fep->mii_bus == NULL) { 2330 err = -ENOMEM; 2331 goto err_out; 2332 } 2333 2334 fep->mii_bus->name = "fec_enet_mii_bus"; 2335 fep->mii_bus->read = fec_enet_mdio_read; 2336 fep->mii_bus->write = fec_enet_mdio_write; 2337 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 2338 pdev->name, fep->dev_id + 1); 2339 fep->mii_bus->priv = fep; 2340 fep->mii_bus->parent = &pdev->dev; 2341 2342 err = of_mdiobus_register(fep->mii_bus, node); 2343 if (err) 2344 goto err_out_free_mdiobus; 2345 of_node_put(node); 2346 2347 mii_cnt++; 2348 2349 /* save fec0 mii_bus */ 2350 if (fep->quirks & FEC_QUIRK_SINGLE_MDIO) 2351 fec0_mii_bus = fep->mii_bus; 2352 2353 return 0; 2354 2355 err_out_free_mdiobus: 2356 mdiobus_free(fep->mii_bus); 2357 err_out: 2358 of_node_put(node); 2359 return err; 2360 } 2361 2362 static void fec_enet_mii_remove(struct fec_enet_private *fep) 2363 { 2364 if (--mii_cnt == 0) { 2365 mdiobus_unregister(fep->mii_bus); 2366 mdiobus_free(fep->mii_bus); 2367 } 2368 } 2369 2370 static void fec_enet_get_drvinfo(struct net_device *ndev, 2371 struct ethtool_drvinfo *info) 2372 { 2373 struct fec_enet_private *fep = netdev_priv(ndev); 2374 2375 strscpy(info->driver, fep->pdev->dev.driver->name, 2376 sizeof(info->driver)); 2377 strscpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info)); 2378 } 2379 2380 static int fec_enet_get_regs_len(struct net_device *ndev) 2381 { 2382 struct fec_enet_private *fep = netdev_priv(ndev); 2383 struct resource *r; 2384 int s = 0; 2385 2386 r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0); 2387 if (r) 2388 s = resource_size(r); 2389 2390 return s; 2391 } 2392 2393 /* List of registers that can be safety be read to dump them with ethtool */ 2394 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 2395 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \ 2396 defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST) 2397 static __u32 fec_enet_register_version = 2; 2398 static u32 fec_enet_register_offset[] = { 2399 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0, 2400 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL, 2401 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1, 2402 FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH, 2403 FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, 2404 FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1, 2405 FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2, 2406 FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0, 2407 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM, 2408 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2, 2409 FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1, 2410 FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME, 2411 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT, 2412 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG, 2413 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255, 2414 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047, 2415 RMON_T_P_GTE2048, RMON_T_OCTETS, 2416 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF, 2417 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE, 2418 IEEE_T_FDXFC, IEEE_T_OCTETS_OK, 2419 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN, 2420 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB, 2421 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255, 2422 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047, 2423 RMON_R_P_GTE2048, RMON_R_OCTETS, 2424 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR, 2425 IEEE_R_FDXFC, IEEE_R_OCTETS_OK 2426 }; 2427 #else 2428 static __u32 fec_enet_register_version = 1; 2429 static u32 fec_enet_register_offset[] = { 2430 FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0, 2431 FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0, 2432 FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED, 2433 FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL, 2434 FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, 2435 FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0, 2436 FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0, 2437 FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0, 2438 FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2 2439 }; 2440 #endif 2441 2442 static void fec_enet_get_regs(struct net_device *ndev, 2443 struct ethtool_regs *regs, void *regbuf) 2444 { 2445 struct fec_enet_private *fep = netdev_priv(ndev); 2446 u32 __iomem *theregs = (u32 __iomem *)fep->hwp; 2447 struct device *dev = &fep->pdev->dev; 2448 u32 *buf = (u32 *)regbuf; 2449 u32 i, off; 2450 int ret; 2451 2452 ret = pm_runtime_resume_and_get(dev); 2453 if (ret < 0) 2454 return; 2455 2456 regs->version = fec_enet_register_version; 2457 2458 memset(buf, 0, regs->len); 2459 2460 for (i = 0; i < ARRAY_SIZE(fec_enet_register_offset); i++) { 2461 off = fec_enet_register_offset[i]; 2462 2463 if ((off == FEC_R_BOUND || off == FEC_R_FSTART) && 2464 !(fep->quirks & FEC_QUIRK_HAS_FRREG)) 2465 continue; 2466 2467 off >>= 2; 2468 buf[off] = readl(&theregs[off]); 2469 } 2470 2471 pm_runtime_mark_last_busy(dev); 2472 pm_runtime_put_autosuspend(dev); 2473 } 2474 2475 static int fec_enet_get_ts_info(struct net_device *ndev, 2476 struct ethtool_ts_info *info) 2477 { 2478 struct fec_enet_private *fep = netdev_priv(ndev); 2479 2480 if (fep->bufdesc_ex) { 2481 2482 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 2483 SOF_TIMESTAMPING_RX_SOFTWARE | 2484 SOF_TIMESTAMPING_SOFTWARE | 2485 SOF_TIMESTAMPING_TX_HARDWARE | 2486 SOF_TIMESTAMPING_RX_HARDWARE | 2487 SOF_TIMESTAMPING_RAW_HARDWARE; 2488 if (fep->ptp_clock) 2489 info->phc_index = ptp_clock_index(fep->ptp_clock); 2490 else 2491 info->phc_index = -1; 2492 2493 info->tx_types = (1 << HWTSTAMP_TX_OFF) | 2494 (1 << HWTSTAMP_TX_ON); 2495 2496 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 2497 (1 << HWTSTAMP_FILTER_ALL); 2498 return 0; 2499 } else { 2500 return ethtool_op_get_ts_info(ndev, info); 2501 } 2502 } 2503 2504 #if !defined(CONFIG_M5272) 2505 2506 static void fec_enet_get_pauseparam(struct net_device *ndev, 2507 struct ethtool_pauseparam *pause) 2508 { 2509 struct fec_enet_private *fep = netdev_priv(ndev); 2510 2511 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0; 2512 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0; 2513 pause->rx_pause = pause->tx_pause; 2514 } 2515 2516 static int fec_enet_set_pauseparam(struct net_device *ndev, 2517 struct ethtool_pauseparam *pause) 2518 { 2519 struct fec_enet_private *fep = netdev_priv(ndev); 2520 2521 if (!ndev->phydev) 2522 return -ENODEV; 2523 2524 if (pause->tx_pause != pause->rx_pause) { 2525 netdev_info(ndev, 2526 "hardware only support enable/disable both tx and rx"); 2527 return -EINVAL; 2528 } 2529 2530 fep->pause_flag = 0; 2531 2532 /* tx pause must be same as rx pause */ 2533 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0; 2534 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0; 2535 2536 phy_set_sym_pause(ndev->phydev, pause->rx_pause, pause->tx_pause, 2537 pause->autoneg); 2538 2539 if (pause->autoneg) { 2540 if (netif_running(ndev)) 2541 fec_stop(ndev); 2542 phy_start_aneg(ndev->phydev); 2543 } 2544 if (netif_running(ndev)) { 2545 napi_disable(&fep->napi); 2546 netif_tx_lock_bh(ndev); 2547 fec_restart(ndev); 2548 netif_tx_wake_all_queues(ndev); 2549 netif_tx_unlock_bh(ndev); 2550 napi_enable(&fep->napi); 2551 } 2552 2553 return 0; 2554 } 2555 2556 static const struct fec_stat { 2557 char name[ETH_GSTRING_LEN]; 2558 u16 offset; 2559 } fec_stats[] = { 2560 /* RMON TX */ 2561 { "tx_dropped", RMON_T_DROP }, 2562 { "tx_packets", RMON_T_PACKETS }, 2563 { "tx_broadcast", RMON_T_BC_PKT }, 2564 { "tx_multicast", RMON_T_MC_PKT }, 2565 { "tx_crc_errors", RMON_T_CRC_ALIGN }, 2566 { "tx_undersize", RMON_T_UNDERSIZE }, 2567 { "tx_oversize", RMON_T_OVERSIZE }, 2568 { "tx_fragment", RMON_T_FRAG }, 2569 { "tx_jabber", RMON_T_JAB }, 2570 { "tx_collision", RMON_T_COL }, 2571 { "tx_64byte", RMON_T_P64 }, 2572 { "tx_65to127byte", RMON_T_P65TO127 }, 2573 { "tx_128to255byte", RMON_T_P128TO255 }, 2574 { "tx_256to511byte", RMON_T_P256TO511 }, 2575 { "tx_512to1023byte", RMON_T_P512TO1023 }, 2576 { "tx_1024to2047byte", RMON_T_P1024TO2047 }, 2577 { "tx_GTE2048byte", RMON_T_P_GTE2048 }, 2578 { "tx_octets", RMON_T_OCTETS }, 2579 2580 /* IEEE TX */ 2581 { "IEEE_tx_drop", IEEE_T_DROP }, 2582 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK }, 2583 { "IEEE_tx_1col", IEEE_T_1COL }, 2584 { "IEEE_tx_mcol", IEEE_T_MCOL }, 2585 { "IEEE_tx_def", IEEE_T_DEF }, 2586 { "IEEE_tx_lcol", IEEE_T_LCOL }, 2587 { "IEEE_tx_excol", IEEE_T_EXCOL }, 2588 { "IEEE_tx_macerr", IEEE_T_MACERR }, 2589 { "IEEE_tx_cserr", IEEE_T_CSERR }, 2590 { "IEEE_tx_sqe", IEEE_T_SQE }, 2591 { "IEEE_tx_fdxfc", IEEE_T_FDXFC }, 2592 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK }, 2593 2594 /* RMON RX */ 2595 { "rx_packets", RMON_R_PACKETS }, 2596 { "rx_broadcast", RMON_R_BC_PKT }, 2597 { "rx_multicast", RMON_R_MC_PKT }, 2598 { "rx_crc_errors", RMON_R_CRC_ALIGN }, 2599 { "rx_undersize", RMON_R_UNDERSIZE }, 2600 { "rx_oversize", RMON_R_OVERSIZE }, 2601 { "rx_fragment", RMON_R_FRAG }, 2602 { "rx_jabber", RMON_R_JAB }, 2603 { "rx_64byte", RMON_R_P64 }, 2604 { "rx_65to127byte", RMON_R_P65TO127 }, 2605 { "rx_128to255byte", RMON_R_P128TO255 }, 2606 { "rx_256to511byte", RMON_R_P256TO511 }, 2607 { "rx_512to1023byte", RMON_R_P512TO1023 }, 2608 { "rx_1024to2047byte", RMON_R_P1024TO2047 }, 2609 { "rx_GTE2048byte", RMON_R_P_GTE2048 }, 2610 { "rx_octets", RMON_R_OCTETS }, 2611 2612 /* IEEE RX */ 2613 { "IEEE_rx_drop", IEEE_R_DROP }, 2614 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK }, 2615 { "IEEE_rx_crc", IEEE_R_CRC }, 2616 { "IEEE_rx_align", IEEE_R_ALIGN }, 2617 { "IEEE_rx_macerr", IEEE_R_MACERR }, 2618 { "IEEE_rx_fdxfc", IEEE_R_FDXFC }, 2619 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK }, 2620 }; 2621 2622 #define FEC_STATS_SIZE (ARRAY_SIZE(fec_stats) * sizeof(u64)) 2623 2624 static void fec_enet_update_ethtool_stats(struct net_device *dev) 2625 { 2626 struct fec_enet_private *fep = netdev_priv(dev); 2627 int i; 2628 2629 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2630 fep->ethtool_stats[i] = readl(fep->hwp + fec_stats[i].offset); 2631 } 2632 2633 static void fec_enet_get_ethtool_stats(struct net_device *dev, 2634 struct ethtool_stats *stats, u64 *data) 2635 { 2636 struct fec_enet_private *fep = netdev_priv(dev); 2637 2638 if (netif_running(dev)) 2639 fec_enet_update_ethtool_stats(dev); 2640 2641 memcpy(data, fep->ethtool_stats, FEC_STATS_SIZE); 2642 } 2643 2644 static void fec_enet_get_strings(struct net_device *netdev, 2645 u32 stringset, u8 *data) 2646 { 2647 int i; 2648 switch (stringset) { 2649 case ETH_SS_STATS: 2650 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2651 memcpy(data + i * ETH_GSTRING_LEN, 2652 fec_stats[i].name, ETH_GSTRING_LEN); 2653 break; 2654 case ETH_SS_TEST: 2655 net_selftest_get_strings(data); 2656 break; 2657 } 2658 } 2659 2660 static int fec_enet_get_sset_count(struct net_device *dev, int sset) 2661 { 2662 switch (sset) { 2663 case ETH_SS_STATS: 2664 return ARRAY_SIZE(fec_stats); 2665 case ETH_SS_TEST: 2666 return net_selftest_get_count(); 2667 default: 2668 return -EOPNOTSUPP; 2669 } 2670 } 2671 2672 static void fec_enet_clear_ethtool_stats(struct net_device *dev) 2673 { 2674 struct fec_enet_private *fep = netdev_priv(dev); 2675 int i; 2676 2677 /* Disable MIB statistics counters */ 2678 writel(FEC_MIB_CTRLSTAT_DISABLE, fep->hwp + FEC_MIB_CTRLSTAT); 2679 2680 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2681 writel(0, fep->hwp + fec_stats[i].offset); 2682 2683 /* Don't disable MIB statistics counters */ 2684 writel(0, fep->hwp + FEC_MIB_CTRLSTAT); 2685 } 2686 2687 #else /* !defined(CONFIG_M5272) */ 2688 #define FEC_STATS_SIZE 0 2689 static inline void fec_enet_update_ethtool_stats(struct net_device *dev) 2690 { 2691 } 2692 2693 static inline void fec_enet_clear_ethtool_stats(struct net_device *dev) 2694 { 2695 } 2696 #endif /* !defined(CONFIG_M5272) */ 2697 2698 /* ITR clock source is enet system clock (clk_ahb). 2699 * TCTT unit is cycle_ns * 64 cycle 2700 * So, the ICTT value = X us / (cycle_ns * 64) 2701 */ 2702 static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us) 2703 { 2704 struct fec_enet_private *fep = netdev_priv(ndev); 2705 2706 return us * (fep->itr_clk_rate / 64000) / 1000; 2707 } 2708 2709 /* Set threshold for interrupt coalescing */ 2710 static void fec_enet_itr_coal_set(struct net_device *ndev) 2711 { 2712 struct fec_enet_private *fep = netdev_priv(ndev); 2713 int rx_itr, tx_itr; 2714 2715 /* Must be greater than zero to avoid unpredictable behavior */ 2716 if (!fep->rx_time_itr || !fep->rx_pkts_itr || 2717 !fep->tx_time_itr || !fep->tx_pkts_itr) 2718 return; 2719 2720 /* Select enet system clock as Interrupt Coalescing 2721 * timer Clock Source 2722 */ 2723 rx_itr = FEC_ITR_CLK_SEL; 2724 tx_itr = FEC_ITR_CLK_SEL; 2725 2726 /* set ICFT and ICTT */ 2727 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr); 2728 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr)); 2729 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr); 2730 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr)); 2731 2732 rx_itr |= FEC_ITR_EN; 2733 tx_itr |= FEC_ITR_EN; 2734 2735 writel(tx_itr, fep->hwp + FEC_TXIC0); 2736 writel(rx_itr, fep->hwp + FEC_RXIC0); 2737 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) { 2738 writel(tx_itr, fep->hwp + FEC_TXIC1); 2739 writel(rx_itr, fep->hwp + FEC_RXIC1); 2740 writel(tx_itr, fep->hwp + FEC_TXIC2); 2741 writel(rx_itr, fep->hwp + FEC_RXIC2); 2742 } 2743 } 2744 2745 static int fec_enet_get_coalesce(struct net_device *ndev, 2746 struct ethtool_coalesce *ec, 2747 struct kernel_ethtool_coalesce *kernel_coal, 2748 struct netlink_ext_ack *extack) 2749 { 2750 struct fec_enet_private *fep = netdev_priv(ndev); 2751 2752 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) 2753 return -EOPNOTSUPP; 2754 2755 ec->rx_coalesce_usecs = fep->rx_time_itr; 2756 ec->rx_max_coalesced_frames = fep->rx_pkts_itr; 2757 2758 ec->tx_coalesce_usecs = fep->tx_time_itr; 2759 ec->tx_max_coalesced_frames = fep->tx_pkts_itr; 2760 2761 return 0; 2762 } 2763 2764 static int fec_enet_set_coalesce(struct net_device *ndev, 2765 struct ethtool_coalesce *ec, 2766 struct kernel_ethtool_coalesce *kernel_coal, 2767 struct netlink_ext_ack *extack) 2768 { 2769 struct fec_enet_private *fep = netdev_priv(ndev); 2770 struct device *dev = &fep->pdev->dev; 2771 unsigned int cycle; 2772 2773 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) 2774 return -EOPNOTSUPP; 2775 2776 if (ec->rx_max_coalesced_frames > 255) { 2777 dev_err(dev, "Rx coalesced frames exceed hardware limitation\n"); 2778 return -EINVAL; 2779 } 2780 2781 if (ec->tx_max_coalesced_frames > 255) { 2782 dev_err(dev, "Tx coalesced frame exceed hardware limitation\n"); 2783 return -EINVAL; 2784 } 2785 2786 cycle = fec_enet_us_to_itr_clock(ndev, ec->rx_coalesce_usecs); 2787 if (cycle > 0xFFFF) { 2788 dev_err(dev, "Rx coalesced usec exceed hardware limitation\n"); 2789 return -EINVAL; 2790 } 2791 2792 cycle = fec_enet_us_to_itr_clock(ndev, ec->tx_coalesce_usecs); 2793 if (cycle > 0xFFFF) { 2794 dev_err(dev, "Tx coalesced usec exceed hardware limitation\n"); 2795 return -EINVAL; 2796 } 2797 2798 fep->rx_time_itr = ec->rx_coalesce_usecs; 2799 fep->rx_pkts_itr = ec->rx_max_coalesced_frames; 2800 2801 fep->tx_time_itr = ec->tx_coalesce_usecs; 2802 fep->tx_pkts_itr = ec->tx_max_coalesced_frames; 2803 2804 fec_enet_itr_coal_set(ndev); 2805 2806 return 0; 2807 } 2808 2809 static void fec_enet_itr_coal_init(struct net_device *ndev) 2810 { 2811 struct ethtool_coalesce ec; 2812 2813 ec.rx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT; 2814 ec.rx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT; 2815 2816 ec.tx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT; 2817 ec.tx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT; 2818 2819 fec_enet_set_coalesce(ndev, &ec, NULL, NULL); 2820 } 2821 2822 static int fec_enet_get_tunable(struct net_device *netdev, 2823 const struct ethtool_tunable *tuna, 2824 void *data) 2825 { 2826 struct fec_enet_private *fep = netdev_priv(netdev); 2827 int ret = 0; 2828 2829 switch (tuna->id) { 2830 case ETHTOOL_RX_COPYBREAK: 2831 *(u32 *)data = fep->rx_copybreak; 2832 break; 2833 default: 2834 ret = -EINVAL; 2835 break; 2836 } 2837 2838 return ret; 2839 } 2840 2841 static int fec_enet_set_tunable(struct net_device *netdev, 2842 const struct ethtool_tunable *tuna, 2843 const void *data) 2844 { 2845 struct fec_enet_private *fep = netdev_priv(netdev); 2846 int ret = 0; 2847 2848 switch (tuna->id) { 2849 case ETHTOOL_RX_COPYBREAK: 2850 fep->rx_copybreak = *(u32 *)data; 2851 break; 2852 default: 2853 ret = -EINVAL; 2854 break; 2855 } 2856 2857 return ret; 2858 } 2859 2860 /* LPI Sleep Ts count base on tx clk (clk_ref). 2861 * The lpi sleep cnt value = X us / (cycle_ns). 2862 */ 2863 static int fec_enet_us_to_tx_cycle(struct net_device *ndev, int us) 2864 { 2865 struct fec_enet_private *fep = netdev_priv(ndev); 2866 2867 return us * (fep->clk_ref_rate / 1000) / 1000; 2868 } 2869 2870 static int fec_enet_eee_mode_set(struct net_device *ndev, bool enable) 2871 { 2872 struct fec_enet_private *fep = netdev_priv(ndev); 2873 struct ethtool_eee *p = &fep->eee; 2874 unsigned int sleep_cycle, wake_cycle; 2875 int ret = 0; 2876 2877 if (enable) { 2878 ret = phy_init_eee(ndev->phydev, false); 2879 if (ret) 2880 return ret; 2881 2882 sleep_cycle = fec_enet_us_to_tx_cycle(ndev, p->tx_lpi_timer); 2883 wake_cycle = sleep_cycle; 2884 } else { 2885 sleep_cycle = 0; 2886 wake_cycle = 0; 2887 } 2888 2889 p->tx_lpi_enabled = enable; 2890 p->eee_enabled = enable; 2891 p->eee_active = enable; 2892 2893 writel(sleep_cycle, fep->hwp + FEC_LPI_SLEEP); 2894 writel(wake_cycle, fep->hwp + FEC_LPI_WAKE); 2895 2896 return 0; 2897 } 2898 2899 static int 2900 fec_enet_get_eee(struct net_device *ndev, struct ethtool_eee *edata) 2901 { 2902 struct fec_enet_private *fep = netdev_priv(ndev); 2903 struct ethtool_eee *p = &fep->eee; 2904 2905 if (!(fep->quirks & FEC_QUIRK_HAS_EEE)) 2906 return -EOPNOTSUPP; 2907 2908 if (!netif_running(ndev)) 2909 return -ENETDOWN; 2910 2911 edata->eee_enabled = p->eee_enabled; 2912 edata->eee_active = p->eee_active; 2913 edata->tx_lpi_timer = p->tx_lpi_timer; 2914 edata->tx_lpi_enabled = p->tx_lpi_enabled; 2915 2916 return phy_ethtool_get_eee(ndev->phydev, edata); 2917 } 2918 2919 static int 2920 fec_enet_set_eee(struct net_device *ndev, struct ethtool_eee *edata) 2921 { 2922 struct fec_enet_private *fep = netdev_priv(ndev); 2923 struct ethtool_eee *p = &fep->eee; 2924 int ret = 0; 2925 2926 if (!(fep->quirks & FEC_QUIRK_HAS_EEE)) 2927 return -EOPNOTSUPP; 2928 2929 if (!netif_running(ndev)) 2930 return -ENETDOWN; 2931 2932 p->tx_lpi_timer = edata->tx_lpi_timer; 2933 2934 if (!edata->eee_enabled || !edata->tx_lpi_enabled || 2935 !edata->tx_lpi_timer) 2936 ret = fec_enet_eee_mode_set(ndev, false); 2937 else 2938 ret = fec_enet_eee_mode_set(ndev, true); 2939 2940 if (ret) 2941 return ret; 2942 2943 return phy_ethtool_set_eee(ndev->phydev, edata); 2944 } 2945 2946 static void 2947 fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2948 { 2949 struct fec_enet_private *fep = netdev_priv(ndev); 2950 2951 if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) { 2952 wol->supported = WAKE_MAGIC; 2953 wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0; 2954 } else { 2955 wol->supported = wol->wolopts = 0; 2956 } 2957 } 2958 2959 static int 2960 fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2961 { 2962 struct fec_enet_private *fep = netdev_priv(ndev); 2963 2964 if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET)) 2965 return -EINVAL; 2966 2967 if (wol->wolopts & ~WAKE_MAGIC) 2968 return -EINVAL; 2969 2970 device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC); 2971 if (device_may_wakeup(&ndev->dev)) 2972 fep->wol_flag |= FEC_WOL_FLAG_ENABLE; 2973 else 2974 fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE); 2975 2976 return 0; 2977 } 2978 2979 static const struct ethtool_ops fec_enet_ethtool_ops = { 2980 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 2981 ETHTOOL_COALESCE_MAX_FRAMES, 2982 .get_drvinfo = fec_enet_get_drvinfo, 2983 .get_regs_len = fec_enet_get_regs_len, 2984 .get_regs = fec_enet_get_regs, 2985 .nway_reset = phy_ethtool_nway_reset, 2986 .get_link = ethtool_op_get_link, 2987 .get_coalesce = fec_enet_get_coalesce, 2988 .set_coalesce = fec_enet_set_coalesce, 2989 #ifndef CONFIG_M5272 2990 .get_pauseparam = fec_enet_get_pauseparam, 2991 .set_pauseparam = fec_enet_set_pauseparam, 2992 .get_strings = fec_enet_get_strings, 2993 .get_ethtool_stats = fec_enet_get_ethtool_stats, 2994 .get_sset_count = fec_enet_get_sset_count, 2995 #endif 2996 .get_ts_info = fec_enet_get_ts_info, 2997 .get_tunable = fec_enet_get_tunable, 2998 .set_tunable = fec_enet_set_tunable, 2999 .get_wol = fec_enet_get_wol, 3000 .set_wol = fec_enet_set_wol, 3001 .get_eee = fec_enet_get_eee, 3002 .set_eee = fec_enet_set_eee, 3003 .get_link_ksettings = phy_ethtool_get_link_ksettings, 3004 .set_link_ksettings = phy_ethtool_set_link_ksettings, 3005 .self_test = net_selftest, 3006 }; 3007 3008 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) 3009 { 3010 struct fec_enet_private *fep = netdev_priv(ndev); 3011 struct phy_device *phydev = ndev->phydev; 3012 3013 if (!netif_running(ndev)) 3014 return -EINVAL; 3015 3016 if (!phydev) 3017 return -ENODEV; 3018 3019 if (fep->bufdesc_ex) { 3020 bool use_fec_hwts = !phy_has_hwtstamp(phydev); 3021 3022 if (cmd == SIOCSHWTSTAMP) { 3023 if (use_fec_hwts) 3024 return fec_ptp_set(ndev, rq); 3025 fec_ptp_disable_hwts(ndev); 3026 } else if (cmd == SIOCGHWTSTAMP) { 3027 if (use_fec_hwts) 3028 return fec_ptp_get(ndev, rq); 3029 } 3030 } 3031 3032 return phy_mii_ioctl(phydev, rq, cmd); 3033 } 3034 3035 static void fec_enet_free_buffers(struct net_device *ndev) 3036 { 3037 struct fec_enet_private *fep = netdev_priv(ndev); 3038 unsigned int i; 3039 struct sk_buff *skb; 3040 struct bufdesc *bdp; 3041 struct fec_enet_priv_tx_q *txq; 3042 struct fec_enet_priv_rx_q *rxq; 3043 unsigned int q; 3044 3045 for (q = 0; q < fep->num_rx_queues; q++) { 3046 rxq = fep->rx_queue[q]; 3047 bdp = rxq->bd.base; 3048 for (i = 0; i < rxq->bd.ring_size; i++) { 3049 skb = rxq->rx_skbuff[i]; 3050 rxq->rx_skbuff[i] = NULL; 3051 if (skb) { 3052 dma_unmap_single(&fep->pdev->dev, 3053 fec32_to_cpu(bdp->cbd_bufaddr), 3054 FEC_ENET_RX_FRSIZE - fep->rx_align, 3055 DMA_FROM_DEVICE); 3056 dev_kfree_skb(skb); 3057 } 3058 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 3059 } 3060 } 3061 3062 for (q = 0; q < fep->num_tx_queues; q++) { 3063 txq = fep->tx_queue[q]; 3064 for (i = 0; i < txq->bd.ring_size; i++) { 3065 kfree(txq->tx_bounce[i]); 3066 txq->tx_bounce[i] = NULL; 3067 skb = txq->tx_skbuff[i]; 3068 txq->tx_skbuff[i] = NULL; 3069 dev_kfree_skb(skb); 3070 } 3071 } 3072 } 3073 3074 static void fec_enet_free_queue(struct net_device *ndev) 3075 { 3076 struct fec_enet_private *fep = netdev_priv(ndev); 3077 int i; 3078 struct fec_enet_priv_tx_q *txq; 3079 3080 for (i = 0; i < fep->num_tx_queues; i++) 3081 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) { 3082 txq = fep->tx_queue[i]; 3083 dma_free_coherent(&fep->pdev->dev, 3084 txq->bd.ring_size * TSO_HEADER_SIZE, 3085 txq->tso_hdrs, 3086 txq->tso_hdrs_dma); 3087 } 3088 3089 for (i = 0; i < fep->num_rx_queues; i++) 3090 kfree(fep->rx_queue[i]); 3091 for (i = 0; i < fep->num_tx_queues; i++) 3092 kfree(fep->tx_queue[i]); 3093 } 3094 3095 static int fec_enet_alloc_queue(struct net_device *ndev) 3096 { 3097 struct fec_enet_private *fep = netdev_priv(ndev); 3098 int i; 3099 int ret = 0; 3100 struct fec_enet_priv_tx_q *txq; 3101 3102 for (i = 0; i < fep->num_tx_queues; i++) { 3103 txq = kzalloc(sizeof(*txq), GFP_KERNEL); 3104 if (!txq) { 3105 ret = -ENOMEM; 3106 goto alloc_failed; 3107 } 3108 3109 fep->tx_queue[i] = txq; 3110 txq->bd.ring_size = TX_RING_SIZE; 3111 fep->total_tx_ring_size += fep->tx_queue[i]->bd.ring_size; 3112 3113 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS; 3114 txq->tx_wake_threshold = 3115 (txq->bd.ring_size - txq->tx_stop_threshold) / 2; 3116 3117 txq->tso_hdrs = dma_alloc_coherent(&fep->pdev->dev, 3118 txq->bd.ring_size * TSO_HEADER_SIZE, 3119 &txq->tso_hdrs_dma, 3120 GFP_KERNEL); 3121 if (!txq->tso_hdrs) { 3122 ret = -ENOMEM; 3123 goto alloc_failed; 3124 } 3125 } 3126 3127 for (i = 0; i < fep->num_rx_queues; i++) { 3128 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]), 3129 GFP_KERNEL); 3130 if (!fep->rx_queue[i]) { 3131 ret = -ENOMEM; 3132 goto alloc_failed; 3133 } 3134 3135 fep->rx_queue[i]->bd.ring_size = RX_RING_SIZE; 3136 fep->total_rx_ring_size += fep->rx_queue[i]->bd.ring_size; 3137 } 3138 return ret; 3139 3140 alloc_failed: 3141 fec_enet_free_queue(ndev); 3142 return ret; 3143 } 3144 3145 static int 3146 fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue) 3147 { 3148 struct fec_enet_private *fep = netdev_priv(ndev); 3149 unsigned int i; 3150 struct sk_buff *skb; 3151 struct bufdesc *bdp; 3152 struct fec_enet_priv_rx_q *rxq; 3153 3154 rxq = fep->rx_queue[queue]; 3155 bdp = rxq->bd.base; 3156 for (i = 0; i < rxq->bd.ring_size; i++) { 3157 skb = __netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE, GFP_KERNEL); 3158 if (!skb) 3159 goto err_alloc; 3160 3161 if (fec_enet_new_rxbdp(ndev, bdp, skb)) { 3162 dev_kfree_skb(skb); 3163 goto err_alloc; 3164 } 3165 3166 rxq->rx_skbuff[i] = skb; 3167 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); 3168 3169 if (fep->bufdesc_ex) { 3170 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 3171 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); 3172 } 3173 3174 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 3175 } 3176 3177 /* Set the last buffer to wrap. */ 3178 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); 3179 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 3180 return 0; 3181 3182 err_alloc: 3183 fec_enet_free_buffers(ndev); 3184 return -ENOMEM; 3185 } 3186 3187 static int 3188 fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue) 3189 { 3190 struct fec_enet_private *fep = netdev_priv(ndev); 3191 unsigned int i; 3192 struct bufdesc *bdp; 3193 struct fec_enet_priv_tx_q *txq; 3194 3195 txq = fep->tx_queue[queue]; 3196 bdp = txq->bd.base; 3197 for (i = 0; i < txq->bd.ring_size; i++) { 3198 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); 3199 if (!txq->tx_bounce[i]) 3200 goto err_alloc; 3201 3202 bdp->cbd_sc = cpu_to_fec16(0); 3203 bdp->cbd_bufaddr = cpu_to_fec32(0); 3204 3205 if (fep->bufdesc_ex) { 3206 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 3207 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_TX_INT); 3208 } 3209 3210 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 3211 } 3212 3213 /* Set the last buffer to wrap. */ 3214 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); 3215 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 3216 3217 return 0; 3218 3219 err_alloc: 3220 fec_enet_free_buffers(ndev); 3221 return -ENOMEM; 3222 } 3223 3224 static int fec_enet_alloc_buffers(struct net_device *ndev) 3225 { 3226 struct fec_enet_private *fep = netdev_priv(ndev); 3227 unsigned int i; 3228 3229 for (i = 0; i < fep->num_rx_queues; i++) 3230 if (fec_enet_alloc_rxq_buffers(ndev, i)) 3231 return -ENOMEM; 3232 3233 for (i = 0; i < fep->num_tx_queues; i++) 3234 if (fec_enet_alloc_txq_buffers(ndev, i)) 3235 return -ENOMEM; 3236 return 0; 3237 } 3238 3239 static int 3240 fec_enet_open(struct net_device *ndev) 3241 { 3242 struct fec_enet_private *fep = netdev_priv(ndev); 3243 int ret; 3244 bool reset_again; 3245 3246 ret = pm_runtime_resume_and_get(&fep->pdev->dev); 3247 if (ret < 0) 3248 return ret; 3249 3250 pinctrl_pm_select_default_state(&fep->pdev->dev); 3251 ret = fec_enet_clk_enable(ndev, true); 3252 if (ret) 3253 goto clk_enable; 3254 3255 /* During the first fec_enet_open call the PHY isn't probed at this 3256 * point. Therefore the phy_reset_after_clk_enable() call within 3257 * fec_enet_clk_enable() fails. As we need this reset in order to be 3258 * sure the PHY is working correctly we check if we need to reset again 3259 * later when the PHY is probed 3260 */ 3261 if (ndev->phydev && ndev->phydev->drv) 3262 reset_again = false; 3263 else 3264 reset_again = true; 3265 3266 /* I should reset the ring buffers here, but I don't yet know 3267 * a simple way to do that. 3268 */ 3269 3270 ret = fec_enet_alloc_buffers(ndev); 3271 if (ret) 3272 goto err_enet_alloc; 3273 3274 /* Init MAC prior to mii bus probe */ 3275 fec_restart(ndev); 3276 3277 /* Call phy_reset_after_clk_enable() again if it failed during 3278 * phy_reset_after_clk_enable() before because the PHY wasn't probed. 3279 */ 3280 if (reset_again) 3281 fec_enet_phy_reset_after_clk_enable(ndev); 3282 3283 /* Probe and connect to PHY when open the interface */ 3284 ret = fec_enet_mii_probe(ndev); 3285 if (ret) 3286 goto err_enet_mii_probe; 3287 3288 if (fep->quirks & FEC_QUIRK_ERR006687) 3289 imx6q_cpuidle_fec_irqs_used(); 3290 3291 if (fep->quirks & FEC_QUIRK_HAS_PMQOS) 3292 cpu_latency_qos_add_request(&fep->pm_qos_req, 0); 3293 3294 napi_enable(&fep->napi); 3295 phy_start(ndev->phydev); 3296 netif_tx_start_all_queues(ndev); 3297 3298 device_set_wakeup_enable(&ndev->dev, fep->wol_flag & 3299 FEC_WOL_FLAG_ENABLE); 3300 3301 return 0; 3302 3303 err_enet_mii_probe: 3304 fec_enet_free_buffers(ndev); 3305 err_enet_alloc: 3306 fec_enet_clk_enable(ndev, false); 3307 clk_enable: 3308 pm_runtime_mark_last_busy(&fep->pdev->dev); 3309 pm_runtime_put_autosuspend(&fep->pdev->dev); 3310 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3311 return ret; 3312 } 3313 3314 static int 3315 fec_enet_close(struct net_device *ndev) 3316 { 3317 struct fec_enet_private *fep = netdev_priv(ndev); 3318 3319 phy_stop(ndev->phydev); 3320 3321 if (netif_device_present(ndev)) { 3322 napi_disable(&fep->napi); 3323 netif_tx_disable(ndev); 3324 fec_stop(ndev); 3325 } 3326 3327 phy_disconnect(ndev->phydev); 3328 3329 if (fep->quirks & FEC_QUIRK_ERR006687) 3330 imx6q_cpuidle_fec_irqs_unused(); 3331 3332 fec_enet_update_ethtool_stats(ndev); 3333 3334 fec_enet_clk_enable(ndev, false); 3335 if (fep->quirks & FEC_QUIRK_HAS_PMQOS) 3336 cpu_latency_qos_remove_request(&fep->pm_qos_req); 3337 3338 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3339 pm_runtime_mark_last_busy(&fep->pdev->dev); 3340 pm_runtime_put_autosuspend(&fep->pdev->dev); 3341 3342 fec_enet_free_buffers(ndev); 3343 3344 return 0; 3345 } 3346 3347 /* Set or clear the multicast filter for this adaptor. 3348 * Skeleton taken from sunlance driver. 3349 * The CPM Ethernet implementation allows Multicast as well as individual 3350 * MAC address filtering. Some of the drivers check to make sure it is 3351 * a group multicast address, and discard those that are not. I guess I 3352 * will do the same for now, but just remove the test if you want 3353 * individual filtering as well (do the upper net layers want or support 3354 * this kind of feature?). 3355 */ 3356 3357 #define FEC_HASH_BITS 6 /* #bits in hash */ 3358 3359 static void set_multicast_list(struct net_device *ndev) 3360 { 3361 struct fec_enet_private *fep = netdev_priv(ndev); 3362 struct netdev_hw_addr *ha; 3363 unsigned int crc, tmp; 3364 unsigned char hash; 3365 unsigned int hash_high = 0, hash_low = 0; 3366 3367 if (ndev->flags & IFF_PROMISC) { 3368 tmp = readl(fep->hwp + FEC_R_CNTRL); 3369 tmp |= 0x8; 3370 writel(tmp, fep->hwp + FEC_R_CNTRL); 3371 return; 3372 } 3373 3374 tmp = readl(fep->hwp + FEC_R_CNTRL); 3375 tmp &= ~0x8; 3376 writel(tmp, fep->hwp + FEC_R_CNTRL); 3377 3378 if (ndev->flags & IFF_ALLMULTI) { 3379 /* Catch all multicast addresses, so set the 3380 * filter to all 1's 3381 */ 3382 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 3383 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 3384 3385 return; 3386 } 3387 3388 /* Add the addresses in hash register */ 3389 netdev_for_each_mc_addr(ha, ndev) { 3390 /* calculate crc32 value of mac address */ 3391 crc = ether_crc_le(ndev->addr_len, ha->addr); 3392 3393 /* only upper 6 bits (FEC_HASH_BITS) are used 3394 * which point to specific bit in the hash registers 3395 */ 3396 hash = (crc >> (32 - FEC_HASH_BITS)) & 0x3f; 3397 3398 if (hash > 31) 3399 hash_high |= 1 << (hash - 32); 3400 else 3401 hash_low |= 1 << hash; 3402 } 3403 3404 writel(hash_high, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 3405 writel(hash_low, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 3406 } 3407 3408 /* Set a MAC change in hardware. */ 3409 static int 3410 fec_set_mac_address(struct net_device *ndev, void *p) 3411 { 3412 struct fec_enet_private *fep = netdev_priv(ndev); 3413 struct sockaddr *addr = p; 3414 3415 if (addr) { 3416 if (!is_valid_ether_addr(addr->sa_data)) 3417 return -EADDRNOTAVAIL; 3418 eth_hw_addr_set(ndev, addr->sa_data); 3419 } 3420 3421 /* Add netif status check here to avoid system hang in below case: 3422 * ifconfig ethx down; ifconfig ethx hw ether xx:xx:xx:xx:xx:xx; 3423 * After ethx down, fec all clocks are gated off and then register 3424 * access causes system hang. 3425 */ 3426 if (!netif_running(ndev)) 3427 return 0; 3428 3429 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) | 3430 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24), 3431 fep->hwp + FEC_ADDR_LOW); 3432 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24), 3433 fep->hwp + FEC_ADDR_HIGH); 3434 return 0; 3435 } 3436 3437 #ifdef CONFIG_NET_POLL_CONTROLLER 3438 /** 3439 * fec_poll_controller - FEC Poll controller function 3440 * @dev: The FEC network adapter 3441 * 3442 * Polled functionality used by netconsole and others in non interrupt mode 3443 * 3444 */ 3445 static void fec_poll_controller(struct net_device *dev) 3446 { 3447 int i; 3448 struct fec_enet_private *fep = netdev_priv(dev); 3449 3450 for (i = 0; i < FEC_IRQ_NUM; i++) { 3451 if (fep->irq[i] > 0) { 3452 disable_irq(fep->irq[i]); 3453 fec_enet_interrupt(fep->irq[i], dev); 3454 enable_irq(fep->irq[i]); 3455 } 3456 } 3457 } 3458 #endif 3459 3460 static inline void fec_enet_set_netdev_features(struct net_device *netdev, 3461 netdev_features_t features) 3462 { 3463 struct fec_enet_private *fep = netdev_priv(netdev); 3464 netdev_features_t changed = features ^ netdev->features; 3465 3466 netdev->features = features; 3467 3468 /* Receive checksum has been changed */ 3469 if (changed & NETIF_F_RXCSUM) { 3470 if (features & NETIF_F_RXCSUM) 3471 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 3472 else 3473 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED; 3474 } 3475 } 3476 3477 static int fec_set_features(struct net_device *netdev, 3478 netdev_features_t features) 3479 { 3480 struct fec_enet_private *fep = netdev_priv(netdev); 3481 netdev_features_t changed = features ^ netdev->features; 3482 3483 if (netif_running(netdev) && changed & NETIF_F_RXCSUM) { 3484 napi_disable(&fep->napi); 3485 netif_tx_lock_bh(netdev); 3486 fec_stop(netdev); 3487 fec_enet_set_netdev_features(netdev, features); 3488 fec_restart(netdev); 3489 netif_tx_wake_all_queues(netdev); 3490 netif_tx_unlock_bh(netdev); 3491 napi_enable(&fep->napi); 3492 } else { 3493 fec_enet_set_netdev_features(netdev, features); 3494 } 3495 3496 return 0; 3497 } 3498 3499 static u16 fec_enet_get_raw_vlan_tci(struct sk_buff *skb) 3500 { 3501 struct vlan_ethhdr *vhdr; 3502 unsigned short vlan_TCI = 0; 3503 3504 if (skb->protocol == htons(ETH_P_ALL)) { 3505 vhdr = (struct vlan_ethhdr *)(skb->data); 3506 vlan_TCI = ntohs(vhdr->h_vlan_TCI); 3507 } 3508 3509 return vlan_TCI; 3510 } 3511 3512 static u16 fec_enet_select_queue(struct net_device *ndev, struct sk_buff *skb, 3513 struct net_device *sb_dev) 3514 { 3515 struct fec_enet_private *fep = netdev_priv(ndev); 3516 u16 vlan_tag; 3517 3518 if (!(fep->quirks & FEC_QUIRK_HAS_AVB)) 3519 return netdev_pick_tx(ndev, skb, NULL); 3520 3521 vlan_tag = fec_enet_get_raw_vlan_tci(skb); 3522 if (!vlan_tag) 3523 return vlan_tag; 3524 3525 return fec_enet_vlan_pri_to_queue[vlan_tag >> 13]; 3526 } 3527 3528 static const struct net_device_ops fec_netdev_ops = { 3529 .ndo_open = fec_enet_open, 3530 .ndo_stop = fec_enet_close, 3531 .ndo_start_xmit = fec_enet_start_xmit, 3532 .ndo_select_queue = fec_enet_select_queue, 3533 .ndo_set_rx_mode = set_multicast_list, 3534 .ndo_validate_addr = eth_validate_addr, 3535 .ndo_tx_timeout = fec_timeout, 3536 .ndo_set_mac_address = fec_set_mac_address, 3537 .ndo_eth_ioctl = fec_enet_ioctl, 3538 #ifdef CONFIG_NET_POLL_CONTROLLER 3539 .ndo_poll_controller = fec_poll_controller, 3540 #endif 3541 .ndo_set_features = fec_set_features, 3542 }; 3543 3544 static const unsigned short offset_des_active_rxq[] = { 3545 FEC_R_DES_ACTIVE_0, FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2 3546 }; 3547 3548 static const unsigned short offset_des_active_txq[] = { 3549 FEC_X_DES_ACTIVE_0, FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2 3550 }; 3551 3552 /* 3553 * XXX: We need to clean up on failure exits here. 3554 * 3555 */ 3556 static int fec_enet_init(struct net_device *ndev) 3557 { 3558 struct fec_enet_private *fep = netdev_priv(ndev); 3559 struct bufdesc *cbd_base; 3560 dma_addr_t bd_dma; 3561 int bd_size; 3562 unsigned int i; 3563 unsigned dsize = fep->bufdesc_ex ? sizeof(struct bufdesc_ex) : 3564 sizeof(struct bufdesc); 3565 unsigned dsize_log2 = __fls(dsize); 3566 int ret; 3567 3568 WARN_ON(dsize != (1 << dsize_log2)); 3569 #if defined(CONFIG_ARM) || defined(CONFIG_ARM64) 3570 fep->rx_align = 0xf; 3571 fep->tx_align = 0xf; 3572 #else 3573 fep->rx_align = 0x3; 3574 fep->tx_align = 0x3; 3575 #endif 3576 3577 /* Check mask of the streaming and coherent API */ 3578 ret = dma_set_mask_and_coherent(&fep->pdev->dev, DMA_BIT_MASK(32)); 3579 if (ret < 0) { 3580 dev_warn(&fep->pdev->dev, "No suitable DMA available\n"); 3581 return ret; 3582 } 3583 3584 ret = fec_enet_alloc_queue(ndev); 3585 if (ret) 3586 return ret; 3587 3588 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) * dsize; 3589 3590 /* Allocate memory for buffer descriptors. */ 3591 cbd_base = dmam_alloc_coherent(&fep->pdev->dev, bd_size, &bd_dma, 3592 GFP_KERNEL); 3593 if (!cbd_base) { 3594 ret = -ENOMEM; 3595 goto free_queue_mem; 3596 } 3597 3598 /* Get the Ethernet address */ 3599 ret = fec_get_mac(ndev); 3600 if (ret) 3601 goto free_queue_mem; 3602 3603 /* make sure MAC we just acquired is programmed into the hw */ 3604 fec_set_mac_address(ndev, NULL); 3605 3606 /* Set receive and transmit descriptor base. */ 3607 for (i = 0; i < fep->num_rx_queues; i++) { 3608 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[i]; 3609 unsigned size = dsize * rxq->bd.ring_size; 3610 3611 rxq->bd.qid = i; 3612 rxq->bd.base = cbd_base; 3613 rxq->bd.cur = cbd_base; 3614 rxq->bd.dma = bd_dma; 3615 rxq->bd.dsize = dsize; 3616 rxq->bd.dsize_log2 = dsize_log2; 3617 rxq->bd.reg_desc_active = fep->hwp + offset_des_active_rxq[i]; 3618 bd_dma += size; 3619 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size); 3620 rxq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); 3621 } 3622 3623 for (i = 0; i < fep->num_tx_queues; i++) { 3624 struct fec_enet_priv_tx_q *txq = fep->tx_queue[i]; 3625 unsigned size = dsize * txq->bd.ring_size; 3626 3627 txq->bd.qid = i; 3628 txq->bd.base = cbd_base; 3629 txq->bd.cur = cbd_base; 3630 txq->bd.dma = bd_dma; 3631 txq->bd.dsize = dsize; 3632 txq->bd.dsize_log2 = dsize_log2; 3633 txq->bd.reg_desc_active = fep->hwp + offset_des_active_txq[i]; 3634 bd_dma += size; 3635 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size); 3636 txq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); 3637 } 3638 3639 3640 /* The FEC Ethernet specific entries in the device structure */ 3641 ndev->watchdog_timeo = TX_TIMEOUT; 3642 ndev->netdev_ops = &fec_netdev_ops; 3643 ndev->ethtool_ops = &fec_enet_ethtool_ops; 3644 3645 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK); 3646 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT); 3647 3648 if (fep->quirks & FEC_QUIRK_HAS_VLAN) 3649 /* enable hw VLAN support */ 3650 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; 3651 3652 if (fep->quirks & FEC_QUIRK_HAS_CSUM) { 3653 netif_set_tso_max_segs(ndev, FEC_MAX_TSO_SEGS); 3654 3655 /* enable hw accelerator */ 3656 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM 3657 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO); 3658 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 3659 } 3660 3661 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) { 3662 fep->tx_align = 0; 3663 fep->rx_align = 0x3f; 3664 } 3665 3666 ndev->hw_features = ndev->features; 3667 3668 fec_restart(ndev); 3669 3670 if (fep->quirks & FEC_QUIRK_MIB_CLEAR) 3671 fec_enet_clear_ethtool_stats(ndev); 3672 else 3673 fec_enet_update_ethtool_stats(ndev); 3674 3675 return 0; 3676 3677 free_queue_mem: 3678 fec_enet_free_queue(ndev); 3679 return ret; 3680 } 3681 3682 #ifdef CONFIG_OF 3683 static int fec_reset_phy(struct platform_device *pdev) 3684 { 3685 int err, phy_reset; 3686 bool active_high = false; 3687 int msec = 1, phy_post_delay = 0; 3688 struct device_node *np = pdev->dev.of_node; 3689 3690 if (!np) 3691 return 0; 3692 3693 err = of_property_read_u32(np, "phy-reset-duration", &msec); 3694 /* A sane reset duration should not be longer than 1s */ 3695 if (!err && msec > 1000) 3696 msec = 1; 3697 3698 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0); 3699 if (phy_reset == -EPROBE_DEFER) 3700 return phy_reset; 3701 else if (!gpio_is_valid(phy_reset)) 3702 return 0; 3703 3704 err = of_property_read_u32(np, "phy-reset-post-delay", &phy_post_delay); 3705 /* valid reset duration should be less than 1s */ 3706 if (!err && phy_post_delay > 1000) 3707 return -EINVAL; 3708 3709 active_high = of_property_read_bool(np, "phy-reset-active-high"); 3710 3711 err = devm_gpio_request_one(&pdev->dev, phy_reset, 3712 active_high ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW, 3713 "phy-reset"); 3714 if (err) { 3715 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err); 3716 return err; 3717 } 3718 3719 if (msec > 20) 3720 msleep(msec); 3721 else 3722 usleep_range(msec * 1000, msec * 1000 + 1000); 3723 3724 gpio_set_value_cansleep(phy_reset, !active_high); 3725 3726 if (!phy_post_delay) 3727 return 0; 3728 3729 if (phy_post_delay > 20) 3730 msleep(phy_post_delay); 3731 else 3732 usleep_range(phy_post_delay * 1000, 3733 phy_post_delay * 1000 + 1000); 3734 3735 return 0; 3736 } 3737 #else /* CONFIG_OF */ 3738 static int fec_reset_phy(struct platform_device *pdev) 3739 { 3740 /* 3741 * In case of platform probe, the reset has been done 3742 * by machine code. 3743 */ 3744 return 0; 3745 } 3746 #endif /* CONFIG_OF */ 3747 3748 static void 3749 fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx) 3750 { 3751 struct device_node *np = pdev->dev.of_node; 3752 3753 *num_tx = *num_rx = 1; 3754 3755 if (!np || !of_device_is_available(np)) 3756 return; 3757 3758 /* parse the num of tx and rx queues */ 3759 of_property_read_u32(np, "fsl,num-tx-queues", num_tx); 3760 3761 of_property_read_u32(np, "fsl,num-rx-queues", num_rx); 3762 3763 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) { 3764 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n", 3765 *num_tx); 3766 *num_tx = 1; 3767 return; 3768 } 3769 3770 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) { 3771 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n", 3772 *num_rx); 3773 *num_rx = 1; 3774 return; 3775 } 3776 3777 } 3778 3779 static int fec_enet_get_irq_cnt(struct platform_device *pdev) 3780 { 3781 int irq_cnt = platform_irq_count(pdev); 3782 3783 if (irq_cnt > FEC_IRQ_NUM) 3784 irq_cnt = FEC_IRQ_NUM; /* last for pps */ 3785 else if (irq_cnt == 2) 3786 irq_cnt = 1; /* last for pps */ 3787 else if (irq_cnt <= 0) 3788 irq_cnt = 1; /* At least 1 irq is needed */ 3789 return irq_cnt; 3790 } 3791 3792 static void fec_enet_get_wakeup_irq(struct platform_device *pdev) 3793 { 3794 struct net_device *ndev = platform_get_drvdata(pdev); 3795 struct fec_enet_private *fep = netdev_priv(ndev); 3796 3797 if (fep->quirks & FEC_QUIRK_WAKEUP_FROM_INT2) 3798 fep->wake_irq = fep->irq[2]; 3799 else 3800 fep->wake_irq = fep->irq[0]; 3801 } 3802 3803 static int fec_enet_init_stop_mode(struct fec_enet_private *fep, 3804 struct device_node *np) 3805 { 3806 struct device_node *gpr_np; 3807 u32 out_val[3]; 3808 int ret = 0; 3809 3810 gpr_np = of_parse_phandle(np, "fsl,stop-mode", 0); 3811 if (!gpr_np) 3812 return 0; 3813 3814 ret = of_property_read_u32_array(np, "fsl,stop-mode", out_val, 3815 ARRAY_SIZE(out_val)); 3816 if (ret) { 3817 dev_dbg(&fep->pdev->dev, "no stop mode property\n"); 3818 goto out; 3819 } 3820 3821 fep->stop_gpr.gpr = syscon_node_to_regmap(gpr_np); 3822 if (IS_ERR(fep->stop_gpr.gpr)) { 3823 dev_err(&fep->pdev->dev, "could not find gpr regmap\n"); 3824 ret = PTR_ERR(fep->stop_gpr.gpr); 3825 fep->stop_gpr.gpr = NULL; 3826 goto out; 3827 } 3828 3829 fep->stop_gpr.reg = out_val[1]; 3830 fep->stop_gpr.bit = out_val[2]; 3831 3832 out: 3833 of_node_put(gpr_np); 3834 3835 return ret; 3836 } 3837 3838 static int 3839 fec_probe(struct platform_device *pdev) 3840 { 3841 struct fec_enet_private *fep; 3842 struct fec_platform_data *pdata; 3843 phy_interface_t interface; 3844 struct net_device *ndev; 3845 int i, irq, ret = 0; 3846 const struct of_device_id *of_id; 3847 static int dev_id; 3848 struct device_node *np = pdev->dev.of_node, *phy_node; 3849 int num_tx_qs; 3850 int num_rx_qs; 3851 char irq_name[8]; 3852 int irq_cnt; 3853 struct fec_devinfo *dev_info; 3854 3855 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs); 3856 3857 /* Init network device */ 3858 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private) + 3859 FEC_STATS_SIZE, num_tx_qs, num_rx_qs); 3860 if (!ndev) 3861 return -ENOMEM; 3862 3863 SET_NETDEV_DEV(ndev, &pdev->dev); 3864 3865 /* setup board info structure */ 3866 fep = netdev_priv(ndev); 3867 3868 of_id = of_match_device(fec_dt_ids, &pdev->dev); 3869 if (of_id) 3870 pdev->id_entry = of_id->data; 3871 dev_info = (struct fec_devinfo *)pdev->id_entry->driver_data; 3872 if (dev_info) 3873 fep->quirks = dev_info->quirks; 3874 3875 fep->netdev = ndev; 3876 fep->num_rx_queues = num_rx_qs; 3877 fep->num_tx_queues = num_tx_qs; 3878 3879 #if !defined(CONFIG_M5272) 3880 /* default enable pause frame auto negotiation */ 3881 if (fep->quirks & FEC_QUIRK_HAS_GBIT) 3882 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG; 3883 #endif 3884 3885 /* Select default pin state */ 3886 pinctrl_pm_select_default_state(&pdev->dev); 3887 3888 fep->hwp = devm_platform_ioremap_resource(pdev, 0); 3889 if (IS_ERR(fep->hwp)) { 3890 ret = PTR_ERR(fep->hwp); 3891 goto failed_ioremap; 3892 } 3893 3894 fep->pdev = pdev; 3895 fep->dev_id = dev_id++; 3896 3897 platform_set_drvdata(pdev, ndev); 3898 3899 if ((of_machine_is_compatible("fsl,imx6q") || 3900 of_machine_is_compatible("fsl,imx6dl")) && 3901 !of_property_read_bool(np, "fsl,err006687-workaround-present")) 3902 fep->quirks |= FEC_QUIRK_ERR006687; 3903 3904 ret = fec_enet_ipc_handle_init(fep); 3905 if (ret) 3906 goto failed_ipc_init; 3907 3908 if (of_get_property(np, "fsl,magic-packet", NULL)) 3909 fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET; 3910 3911 ret = fec_enet_init_stop_mode(fep, np); 3912 if (ret) 3913 goto failed_stop_mode; 3914 3915 phy_node = of_parse_phandle(np, "phy-handle", 0); 3916 if (!phy_node && of_phy_is_fixed_link(np)) { 3917 ret = of_phy_register_fixed_link(np); 3918 if (ret < 0) { 3919 dev_err(&pdev->dev, 3920 "broken fixed-link specification\n"); 3921 goto failed_phy; 3922 } 3923 phy_node = of_node_get(np); 3924 } 3925 fep->phy_node = phy_node; 3926 3927 ret = of_get_phy_mode(pdev->dev.of_node, &interface); 3928 if (ret) { 3929 pdata = dev_get_platdata(&pdev->dev); 3930 if (pdata) 3931 fep->phy_interface = pdata->phy; 3932 else 3933 fep->phy_interface = PHY_INTERFACE_MODE_MII; 3934 } else { 3935 fep->phy_interface = interface; 3936 } 3937 3938 ret = fec_enet_parse_rgmii_delay(fep, np); 3939 if (ret) 3940 goto failed_rgmii_delay; 3941 3942 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 3943 if (IS_ERR(fep->clk_ipg)) { 3944 ret = PTR_ERR(fep->clk_ipg); 3945 goto failed_clk; 3946 } 3947 3948 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 3949 if (IS_ERR(fep->clk_ahb)) { 3950 ret = PTR_ERR(fep->clk_ahb); 3951 goto failed_clk; 3952 } 3953 3954 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb); 3955 3956 /* enet_out is optional, depends on board */ 3957 fep->clk_enet_out = devm_clk_get_optional(&pdev->dev, "enet_out"); 3958 if (IS_ERR(fep->clk_enet_out)) { 3959 ret = PTR_ERR(fep->clk_enet_out); 3960 goto failed_clk; 3961 } 3962 3963 fep->ptp_clk_on = false; 3964 spin_lock_init(&fep->tmreg_lock); 3965 3966 /* clk_ref is optional, depends on board */ 3967 fep->clk_ref = devm_clk_get_optional(&pdev->dev, "enet_clk_ref"); 3968 if (IS_ERR(fep->clk_ref)) { 3969 ret = PTR_ERR(fep->clk_ref); 3970 goto failed_clk; 3971 } 3972 fep->clk_ref_rate = clk_get_rate(fep->clk_ref); 3973 3974 /* clk_2x_txclk is optional, depends on board */ 3975 if (fep->rgmii_txc_dly || fep->rgmii_rxc_dly) { 3976 fep->clk_2x_txclk = devm_clk_get(&pdev->dev, "enet_2x_txclk"); 3977 if (IS_ERR(fep->clk_2x_txclk)) 3978 fep->clk_2x_txclk = NULL; 3979 } 3980 3981 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX; 3982 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp"); 3983 if (IS_ERR(fep->clk_ptp)) { 3984 fep->clk_ptp = NULL; 3985 fep->bufdesc_ex = false; 3986 } 3987 3988 ret = fec_enet_clk_enable(ndev, true); 3989 if (ret) 3990 goto failed_clk; 3991 3992 ret = clk_prepare_enable(fep->clk_ipg); 3993 if (ret) 3994 goto failed_clk_ipg; 3995 ret = clk_prepare_enable(fep->clk_ahb); 3996 if (ret) 3997 goto failed_clk_ahb; 3998 3999 fep->reg_phy = devm_regulator_get_optional(&pdev->dev, "phy"); 4000 if (!IS_ERR(fep->reg_phy)) { 4001 ret = regulator_enable(fep->reg_phy); 4002 if (ret) { 4003 dev_err(&pdev->dev, 4004 "Failed to enable phy regulator: %d\n", ret); 4005 goto failed_regulator; 4006 } 4007 } else { 4008 if (PTR_ERR(fep->reg_phy) == -EPROBE_DEFER) { 4009 ret = -EPROBE_DEFER; 4010 goto failed_regulator; 4011 } 4012 fep->reg_phy = NULL; 4013 } 4014 4015 pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT); 4016 pm_runtime_use_autosuspend(&pdev->dev); 4017 pm_runtime_get_noresume(&pdev->dev); 4018 pm_runtime_set_active(&pdev->dev); 4019 pm_runtime_enable(&pdev->dev); 4020 4021 ret = fec_reset_phy(pdev); 4022 if (ret) 4023 goto failed_reset; 4024 4025 irq_cnt = fec_enet_get_irq_cnt(pdev); 4026 if (fep->bufdesc_ex) 4027 fec_ptp_init(pdev, irq_cnt); 4028 4029 ret = fec_enet_init(ndev); 4030 if (ret) 4031 goto failed_init; 4032 4033 for (i = 0; i < irq_cnt; i++) { 4034 snprintf(irq_name, sizeof(irq_name), "int%d", i); 4035 irq = platform_get_irq_byname_optional(pdev, irq_name); 4036 if (irq < 0) 4037 irq = platform_get_irq(pdev, i); 4038 if (irq < 0) { 4039 ret = irq; 4040 goto failed_irq; 4041 } 4042 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt, 4043 0, pdev->name, ndev); 4044 if (ret) 4045 goto failed_irq; 4046 4047 fep->irq[i] = irq; 4048 } 4049 4050 /* Decide which interrupt line is wakeup capable */ 4051 fec_enet_get_wakeup_irq(pdev); 4052 4053 ret = fec_enet_mii_init(pdev); 4054 if (ret) 4055 goto failed_mii_init; 4056 4057 /* Carrier starts down, phylib will bring it up */ 4058 netif_carrier_off(ndev); 4059 fec_enet_clk_enable(ndev, false); 4060 pinctrl_pm_select_sleep_state(&pdev->dev); 4061 4062 ndev->max_mtu = PKT_MAXBUF_SIZE - ETH_HLEN - ETH_FCS_LEN; 4063 4064 ret = register_netdev(ndev); 4065 if (ret) 4066 goto failed_register; 4067 4068 device_init_wakeup(&ndev->dev, fep->wol_flag & 4069 FEC_WOL_HAS_MAGIC_PACKET); 4070 4071 if (fep->bufdesc_ex && fep->ptp_clock) 4072 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id); 4073 4074 fep->rx_copybreak = COPYBREAK_DEFAULT; 4075 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work); 4076 4077 pm_runtime_mark_last_busy(&pdev->dev); 4078 pm_runtime_put_autosuspend(&pdev->dev); 4079 4080 return 0; 4081 4082 failed_register: 4083 fec_enet_mii_remove(fep); 4084 failed_mii_init: 4085 failed_irq: 4086 failed_init: 4087 fec_ptp_stop(pdev); 4088 failed_reset: 4089 pm_runtime_put_noidle(&pdev->dev); 4090 pm_runtime_disable(&pdev->dev); 4091 if (fep->reg_phy) 4092 regulator_disable(fep->reg_phy); 4093 failed_regulator: 4094 clk_disable_unprepare(fep->clk_ahb); 4095 failed_clk_ahb: 4096 clk_disable_unprepare(fep->clk_ipg); 4097 failed_clk_ipg: 4098 fec_enet_clk_enable(ndev, false); 4099 failed_clk: 4100 failed_rgmii_delay: 4101 if (of_phy_is_fixed_link(np)) 4102 of_phy_deregister_fixed_link(np); 4103 of_node_put(phy_node); 4104 failed_stop_mode: 4105 failed_ipc_init: 4106 failed_phy: 4107 dev_id--; 4108 failed_ioremap: 4109 free_netdev(ndev); 4110 4111 return ret; 4112 } 4113 4114 static int 4115 fec_drv_remove(struct platform_device *pdev) 4116 { 4117 struct net_device *ndev = platform_get_drvdata(pdev); 4118 struct fec_enet_private *fep = netdev_priv(ndev); 4119 struct device_node *np = pdev->dev.of_node; 4120 int ret; 4121 4122 ret = pm_runtime_resume_and_get(&pdev->dev); 4123 if (ret < 0) 4124 return ret; 4125 4126 cancel_work_sync(&fep->tx_timeout_work); 4127 fec_ptp_stop(pdev); 4128 unregister_netdev(ndev); 4129 fec_enet_mii_remove(fep); 4130 if (fep->reg_phy) 4131 regulator_disable(fep->reg_phy); 4132 4133 if (of_phy_is_fixed_link(np)) 4134 of_phy_deregister_fixed_link(np); 4135 of_node_put(fep->phy_node); 4136 4137 clk_disable_unprepare(fep->clk_ahb); 4138 clk_disable_unprepare(fep->clk_ipg); 4139 pm_runtime_put_noidle(&pdev->dev); 4140 pm_runtime_disable(&pdev->dev); 4141 4142 free_netdev(ndev); 4143 return 0; 4144 } 4145 4146 static int __maybe_unused fec_suspend(struct device *dev) 4147 { 4148 struct net_device *ndev = dev_get_drvdata(dev); 4149 struct fec_enet_private *fep = netdev_priv(ndev); 4150 int ret; 4151 4152 rtnl_lock(); 4153 if (netif_running(ndev)) { 4154 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) 4155 fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON; 4156 phy_stop(ndev->phydev); 4157 napi_disable(&fep->napi); 4158 netif_tx_lock_bh(ndev); 4159 netif_device_detach(ndev); 4160 netif_tx_unlock_bh(ndev); 4161 fec_stop(ndev); 4162 if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) { 4163 fec_irqs_disable(ndev); 4164 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 4165 } else { 4166 fec_irqs_disable_except_wakeup(ndev); 4167 if (fep->wake_irq > 0) { 4168 disable_irq(fep->wake_irq); 4169 enable_irq_wake(fep->wake_irq); 4170 } 4171 fec_enet_stop_mode(fep, true); 4172 } 4173 /* It's safe to disable clocks since interrupts are masked */ 4174 fec_enet_clk_enable(ndev, false); 4175 4176 fep->rpm_active = !pm_runtime_status_suspended(dev); 4177 if (fep->rpm_active) { 4178 ret = pm_runtime_force_suspend(dev); 4179 if (ret < 0) { 4180 rtnl_unlock(); 4181 return ret; 4182 } 4183 } 4184 } 4185 rtnl_unlock(); 4186 4187 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) 4188 regulator_disable(fep->reg_phy); 4189 4190 /* SOC supply clock to phy, when clock is disabled, phy link down 4191 * SOC control phy regulator, when regulator is disabled, phy link down 4192 */ 4193 if (fep->clk_enet_out || fep->reg_phy) 4194 fep->link = 0; 4195 4196 return 0; 4197 } 4198 4199 static int __maybe_unused fec_resume(struct device *dev) 4200 { 4201 struct net_device *ndev = dev_get_drvdata(dev); 4202 struct fec_enet_private *fep = netdev_priv(ndev); 4203 int ret; 4204 int val; 4205 4206 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) { 4207 ret = regulator_enable(fep->reg_phy); 4208 if (ret) 4209 return ret; 4210 } 4211 4212 rtnl_lock(); 4213 if (netif_running(ndev)) { 4214 if (fep->rpm_active) 4215 pm_runtime_force_resume(dev); 4216 4217 ret = fec_enet_clk_enable(ndev, true); 4218 if (ret) { 4219 rtnl_unlock(); 4220 goto failed_clk; 4221 } 4222 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) { 4223 fec_enet_stop_mode(fep, false); 4224 if (fep->wake_irq) { 4225 disable_irq_wake(fep->wake_irq); 4226 enable_irq(fep->wake_irq); 4227 } 4228 4229 val = readl(fep->hwp + FEC_ECNTRL); 4230 val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP); 4231 writel(val, fep->hwp + FEC_ECNTRL); 4232 fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON; 4233 } else { 4234 pinctrl_pm_select_default_state(&fep->pdev->dev); 4235 } 4236 fec_restart(ndev); 4237 netif_tx_lock_bh(ndev); 4238 netif_device_attach(ndev); 4239 netif_tx_unlock_bh(ndev); 4240 napi_enable(&fep->napi); 4241 phy_init_hw(ndev->phydev); 4242 phy_start(ndev->phydev); 4243 } 4244 rtnl_unlock(); 4245 4246 return 0; 4247 4248 failed_clk: 4249 if (fep->reg_phy) 4250 regulator_disable(fep->reg_phy); 4251 return ret; 4252 } 4253 4254 static int __maybe_unused fec_runtime_suspend(struct device *dev) 4255 { 4256 struct net_device *ndev = dev_get_drvdata(dev); 4257 struct fec_enet_private *fep = netdev_priv(ndev); 4258 4259 clk_disable_unprepare(fep->clk_ahb); 4260 clk_disable_unprepare(fep->clk_ipg); 4261 4262 return 0; 4263 } 4264 4265 static int __maybe_unused fec_runtime_resume(struct device *dev) 4266 { 4267 struct net_device *ndev = dev_get_drvdata(dev); 4268 struct fec_enet_private *fep = netdev_priv(ndev); 4269 int ret; 4270 4271 ret = clk_prepare_enable(fep->clk_ahb); 4272 if (ret) 4273 return ret; 4274 ret = clk_prepare_enable(fep->clk_ipg); 4275 if (ret) 4276 goto failed_clk_ipg; 4277 4278 return 0; 4279 4280 failed_clk_ipg: 4281 clk_disable_unprepare(fep->clk_ahb); 4282 return ret; 4283 } 4284 4285 static const struct dev_pm_ops fec_pm_ops = { 4286 SET_SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume) 4287 SET_RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL) 4288 }; 4289 4290 static struct platform_driver fec_driver = { 4291 .driver = { 4292 .name = DRIVER_NAME, 4293 .pm = &fec_pm_ops, 4294 .of_match_table = fec_dt_ids, 4295 .suppress_bind_attrs = true, 4296 }, 4297 .id_table = fec_devtype, 4298 .probe = fec_probe, 4299 .remove = fec_drv_remove, 4300 }; 4301 4302 module_platform_driver(fec_driver); 4303 4304 MODULE_LICENSE("GPL"); 4305