1 /* 2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. 3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) 4 * 5 * Right now, I am very wasteful with the buffers. I allocate memory 6 * pages and then divide them into 2K frame buffers. This way I know I 7 * have buffers large enough to hold one frame within one buffer descriptor. 8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which 9 * will be much more memory efficient and will easily handle lots of 10 * small packets. 11 * 12 * Much better multiple PHY support by Magnus Damm. 13 * Copyright (c) 2000 Ericsson Radio Systems AB. 14 * 15 * Support for FEC controller of ColdFire processors. 16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) 17 * 18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) 19 * Copyright (c) 2004-2006 Macq Electronique SA. 20 * 21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. 22 */ 23 24 #include <linux/module.h> 25 #include <linux/kernel.h> 26 #include <linux/string.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/ptrace.h> 29 #include <linux/errno.h> 30 #include <linux/ioport.h> 31 #include <linux/slab.h> 32 #include <linux/interrupt.h> 33 #include <linux/delay.h> 34 #include <linux/netdevice.h> 35 #include <linux/etherdevice.h> 36 #include <linux/skbuff.h> 37 #include <linux/in.h> 38 #include <linux/ip.h> 39 #include <net/ip.h> 40 #include <net/tso.h> 41 #include <linux/tcp.h> 42 #include <linux/udp.h> 43 #include <linux/icmp.h> 44 #include <linux/spinlock.h> 45 #include <linux/workqueue.h> 46 #include <linux/bitops.h> 47 #include <linux/io.h> 48 #include <linux/irq.h> 49 #include <linux/clk.h> 50 #include <linux/platform_device.h> 51 #include <linux/mdio.h> 52 #include <linux/phy.h> 53 #include <linux/fec.h> 54 #include <linux/of.h> 55 #include <linux/of_device.h> 56 #include <linux/of_gpio.h> 57 #include <linux/of_mdio.h> 58 #include <linux/of_net.h> 59 #include <linux/regulator/consumer.h> 60 #include <linux/if_vlan.h> 61 #include <linux/pinctrl/consumer.h> 62 #include <linux/prefetch.h> 63 #include <soc/imx/cpuidle.h> 64 65 #include <asm/cacheflush.h> 66 67 #include "fec.h" 68 69 static void set_multicast_list(struct net_device *ndev); 70 static void fec_enet_itr_coal_init(struct net_device *ndev); 71 72 #define DRIVER_NAME "fec" 73 74 #define FEC_ENET_GET_QUQUE(_x) ((_x == 0) ? 1 : ((_x == 1) ? 2 : 0)) 75 76 /* Pause frame feild and FIFO threshold */ 77 #define FEC_ENET_FCE (1 << 5) 78 #define FEC_ENET_RSEM_V 0x84 79 #define FEC_ENET_RSFL_V 16 80 #define FEC_ENET_RAEM_V 0x8 81 #define FEC_ENET_RAFL_V 0x8 82 #define FEC_ENET_OPD_V 0xFFF0 83 #define FEC_MDIO_PM_TIMEOUT 100 /* ms */ 84 85 static struct platform_device_id fec_devtype[] = { 86 { 87 /* keep it for coldfire */ 88 .name = DRIVER_NAME, 89 .driver_data = 0, 90 }, { 91 .name = "imx25-fec", 92 .driver_data = FEC_QUIRK_USE_GASKET | FEC_QUIRK_HAS_RACC, 93 }, { 94 .name = "imx27-fec", 95 .driver_data = FEC_QUIRK_HAS_RACC, 96 }, { 97 .name = "imx28-fec", 98 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME | 99 FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC, 100 }, { 101 .name = "imx6q-fec", 102 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 103 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 104 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 | 105 FEC_QUIRK_HAS_RACC, 106 }, { 107 .name = "mvf600-fec", 108 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC, 109 }, { 110 .name = "imx6sx-fec", 111 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 112 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 113 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 114 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 115 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE, 116 }, { 117 .name = "imx6ul-fec", 118 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 119 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 120 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_BUG_CAPTURE | 121 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE, 122 }, { 123 /* sentinel */ 124 } 125 }; 126 MODULE_DEVICE_TABLE(platform, fec_devtype); 127 128 enum imx_fec_type { 129 IMX25_FEC = 1, /* runs on i.mx25/50/53 */ 130 IMX27_FEC, /* runs on i.mx27/35/51 */ 131 IMX28_FEC, 132 IMX6Q_FEC, 133 MVF600_FEC, 134 IMX6SX_FEC, 135 IMX6UL_FEC, 136 }; 137 138 static const struct of_device_id fec_dt_ids[] = { 139 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], }, 140 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], }, 141 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], }, 142 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], }, 143 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], }, 144 { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], }, 145 { .compatible = "fsl,imx6ul-fec", .data = &fec_devtype[IMX6UL_FEC], }, 146 { /* sentinel */ } 147 }; 148 MODULE_DEVICE_TABLE(of, fec_dt_ids); 149 150 static unsigned char macaddr[ETH_ALEN]; 151 module_param_array(macaddr, byte, NULL, 0); 152 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address"); 153 154 #if defined(CONFIG_M5272) 155 /* 156 * Some hardware gets it MAC address out of local flash memory. 157 * if this is non-zero then assume it is the address to get MAC from. 158 */ 159 #if defined(CONFIG_NETtel) 160 #define FEC_FLASHMAC 0xf0006006 161 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) 162 #define FEC_FLASHMAC 0xf0006000 163 #elif defined(CONFIG_CANCam) 164 #define FEC_FLASHMAC 0xf0020000 165 #elif defined (CONFIG_M5272C3) 166 #define FEC_FLASHMAC (0xffe04000 + 4) 167 #elif defined(CONFIG_MOD5272) 168 #define FEC_FLASHMAC 0xffc0406b 169 #else 170 #define FEC_FLASHMAC 0 171 #endif 172 #endif /* CONFIG_M5272 */ 173 174 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets. 175 */ 176 #define PKT_MAXBUF_SIZE 1522 177 #define PKT_MINBUF_SIZE 64 178 #define PKT_MAXBLR_SIZE 1536 179 180 /* FEC receive acceleration */ 181 #define FEC_RACC_IPDIS (1 << 1) 182 #define FEC_RACC_PRODIS (1 << 2) 183 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS) 184 185 /* 186 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame 187 * size bits. Other FEC hardware does not, so we need to take that into 188 * account when setting it. 189 */ 190 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 191 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) 192 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) 193 #else 194 #define OPT_FRAME_SIZE 0 195 #endif 196 197 /* FEC MII MMFR bits definition */ 198 #define FEC_MMFR_ST (1 << 30) 199 #define FEC_MMFR_OP_READ (2 << 28) 200 #define FEC_MMFR_OP_WRITE (1 << 28) 201 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23) 202 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18) 203 #define FEC_MMFR_TA (2 << 16) 204 #define FEC_MMFR_DATA(v) (v & 0xffff) 205 /* FEC ECR bits definition */ 206 #define FEC_ECR_MAGICEN (1 << 2) 207 #define FEC_ECR_SLEEP (1 << 3) 208 209 #define FEC_MII_TIMEOUT 30000 /* us */ 210 211 /* Transmitter timeout */ 212 #define TX_TIMEOUT (2 * HZ) 213 214 #define FEC_PAUSE_FLAG_AUTONEG 0x1 215 #define FEC_PAUSE_FLAG_ENABLE 0x2 216 #define FEC_WOL_HAS_MAGIC_PACKET (0x1 << 0) 217 #define FEC_WOL_FLAG_ENABLE (0x1 << 1) 218 #define FEC_WOL_FLAG_SLEEP_ON (0x1 << 2) 219 220 #define COPYBREAK_DEFAULT 256 221 222 #define TSO_HEADER_SIZE 128 223 /* Max number of allowed TCP segments for software TSO */ 224 #define FEC_MAX_TSO_SEGS 100 225 #define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) 226 227 #define IS_TSO_HEADER(txq, addr) \ 228 ((addr >= txq->tso_hdrs_dma) && \ 229 (addr < txq->tso_hdrs_dma + txq->bd.ring_size * TSO_HEADER_SIZE)) 230 231 static int mii_cnt; 232 233 static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, 234 struct bufdesc_prop *bd) 235 { 236 return (bdp >= bd->last) ? bd->base 237 : (struct bufdesc *)(((unsigned)bdp) + bd->dsize); 238 } 239 240 static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, 241 struct bufdesc_prop *bd) 242 { 243 return (bdp <= bd->base) ? bd->last 244 : (struct bufdesc *)(((unsigned)bdp) - bd->dsize); 245 } 246 247 static int fec_enet_get_bd_index(struct bufdesc *bdp, 248 struct bufdesc_prop *bd) 249 { 250 return ((const char *)bdp - (const char *)bd->base) >> bd->dsize_log2; 251 } 252 253 static int fec_enet_get_free_txdesc_num(struct fec_enet_priv_tx_q *txq) 254 { 255 int entries; 256 257 entries = (((const char *)txq->dirty_tx - 258 (const char *)txq->bd.cur) >> txq->bd.dsize_log2) - 1; 259 260 return entries >= 0 ? entries : entries + txq->bd.ring_size; 261 } 262 263 static void swap_buffer(void *bufaddr, int len) 264 { 265 int i; 266 unsigned int *buf = bufaddr; 267 268 for (i = 0; i < len; i += 4, buf++) 269 swab32s(buf); 270 } 271 272 static void swap_buffer2(void *dst_buf, void *src_buf, int len) 273 { 274 int i; 275 unsigned int *src = src_buf; 276 unsigned int *dst = dst_buf; 277 278 for (i = 0; i < len; i += 4, src++, dst++) 279 *dst = swab32p(src); 280 } 281 282 static void fec_dump(struct net_device *ndev) 283 { 284 struct fec_enet_private *fep = netdev_priv(ndev); 285 struct bufdesc *bdp; 286 struct fec_enet_priv_tx_q *txq; 287 int index = 0; 288 289 netdev_info(ndev, "TX ring dump\n"); 290 pr_info("Nr SC addr len SKB\n"); 291 292 txq = fep->tx_queue[0]; 293 bdp = txq->bd.base; 294 295 do { 296 pr_info("%3u %c%c 0x%04x 0x%08x %4u %p\n", 297 index, 298 bdp == txq->bd.cur ? 'S' : ' ', 299 bdp == txq->dirty_tx ? 'H' : ' ', 300 fec16_to_cpu(bdp->cbd_sc), 301 fec32_to_cpu(bdp->cbd_bufaddr), 302 fec16_to_cpu(bdp->cbd_datlen), 303 txq->tx_skbuff[index]); 304 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 305 index++; 306 } while (bdp != txq->bd.base); 307 } 308 309 static inline bool is_ipv4_pkt(struct sk_buff *skb) 310 { 311 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4; 312 } 313 314 static int 315 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev) 316 { 317 /* Only run for packets requiring a checksum. */ 318 if (skb->ip_summed != CHECKSUM_PARTIAL) 319 return 0; 320 321 if (unlikely(skb_cow_head(skb, 0))) 322 return -1; 323 324 if (is_ipv4_pkt(skb)) 325 ip_hdr(skb)->check = 0; 326 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0; 327 328 return 0; 329 } 330 331 static struct bufdesc * 332 fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq, 333 struct sk_buff *skb, 334 struct net_device *ndev) 335 { 336 struct fec_enet_private *fep = netdev_priv(ndev); 337 struct bufdesc *bdp = txq->bd.cur; 338 struct bufdesc_ex *ebdp; 339 int nr_frags = skb_shinfo(skb)->nr_frags; 340 int frag, frag_len; 341 unsigned short status; 342 unsigned int estatus = 0; 343 skb_frag_t *this_frag; 344 unsigned int index; 345 void *bufaddr; 346 dma_addr_t addr; 347 int i; 348 349 for (frag = 0; frag < nr_frags; frag++) { 350 this_frag = &skb_shinfo(skb)->frags[frag]; 351 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 352 ebdp = (struct bufdesc_ex *)bdp; 353 354 status = fec16_to_cpu(bdp->cbd_sc); 355 status &= ~BD_ENET_TX_STATS; 356 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 357 frag_len = skb_shinfo(skb)->frags[frag].size; 358 359 /* Handle the last BD specially */ 360 if (frag == nr_frags - 1) { 361 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 362 if (fep->bufdesc_ex) { 363 estatus |= BD_ENET_TX_INT; 364 if (unlikely(skb_shinfo(skb)->tx_flags & 365 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 366 estatus |= BD_ENET_TX_TS; 367 } 368 } 369 370 if (fep->bufdesc_ex) { 371 if (fep->quirks & FEC_QUIRK_HAS_AVB) 372 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 373 if (skb->ip_summed == CHECKSUM_PARTIAL) 374 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 375 ebdp->cbd_bdu = 0; 376 ebdp->cbd_esc = cpu_to_fec32(estatus); 377 } 378 379 bufaddr = page_address(this_frag->page.p) + this_frag->page_offset; 380 381 index = fec_enet_get_bd_index(bdp, &txq->bd); 382 if (((unsigned long) bufaddr) & fep->tx_align || 383 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 384 memcpy(txq->tx_bounce[index], bufaddr, frag_len); 385 bufaddr = txq->tx_bounce[index]; 386 387 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 388 swap_buffer(bufaddr, frag_len); 389 } 390 391 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len, 392 DMA_TO_DEVICE); 393 if (dma_mapping_error(&fep->pdev->dev, addr)) { 394 if (net_ratelimit()) 395 netdev_err(ndev, "Tx DMA memory map failed\n"); 396 goto dma_mapping_error; 397 } 398 399 bdp->cbd_bufaddr = cpu_to_fec32(addr); 400 bdp->cbd_datlen = cpu_to_fec16(frag_len); 401 /* Make sure the updates to rest of the descriptor are 402 * performed before transferring ownership. 403 */ 404 wmb(); 405 bdp->cbd_sc = cpu_to_fec16(status); 406 } 407 408 return bdp; 409 dma_mapping_error: 410 bdp = txq->bd.cur; 411 for (i = 0; i < frag; i++) { 412 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 413 dma_unmap_single(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr), 414 fec16_to_cpu(bdp->cbd_datlen), DMA_TO_DEVICE); 415 } 416 return ERR_PTR(-ENOMEM); 417 } 418 419 static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq, 420 struct sk_buff *skb, struct net_device *ndev) 421 { 422 struct fec_enet_private *fep = netdev_priv(ndev); 423 int nr_frags = skb_shinfo(skb)->nr_frags; 424 struct bufdesc *bdp, *last_bdp; 425 void *bufaddr; 426 dma_addr_t addr; 427 unsigned short status; 428 unsigned short buflen; 429 unsigned int estatus = 0; 430 unsigned int index; 431 int entries_free; 432 433 entries_free = fec_enet_get_free_txdesc_num(txq); 434 if (entries_free < MAX_SKB_FRAGS + 1) { 435 dev_kfree_skb_any(skb); 436 if (net_ratelimit()) 437 netdev_err(ndev, "NOT enough BD for SG!\n"); 438 return NETDEV_TX_OK; 439 } 440 441 /* Protocol checksum off-load for TCP and UDP. */ 442 if (fec_enet_clear_csum(skb, ndev)) { 443 dev_kfree_skb_any(skb); 444 return NETDEV_TX_OK; 445 } 446 447 /* Fill in a Tx ring entry */ 448 bdp = txq->bd.cur; 449 last_bdp = bdp; 450 status = fec16_to_cpu(bdp->cbd_sc); 451 status &= ~BD_ENET_TX_STATS; 452 453 /* Set buffer length and buffer pointer */ 454 bufaddr = skb->data; 455 buflen = skb_headlen(skb); 456 457 index = fec_enet_get_bd_index(bdp, &txq->bd); 458 if (((unsigned long) bufaddr) & fep->tx_align || 459 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 460 memcpy(txq->tx_bounce[index], skb->data, buflen); 461 bufaddr = txq->tx_bounce[index]; 462 463 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 464 swap_buffer(bufaddr, buflen); 465 } 466 467 /* Push the data cache so the CPM does not get stale memory data. */ 468 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE); 469 if (dma_mapping_error(&fep->pdev->dev, addr)) { 470 dev_kfree_skb_any(skb); 471 if (net_ratelimit()) 472 netdev_err(ndev, "Tx DMA memory map failed\n"); 473 return NETDEV_TX_OK; 474 } 475 476 if (nr_frags) { 477 last_bdp = fec_enet_txq_submit_frag_skb(txq, skb, ndev); 478 if (IS_ERR(last_bdp)) { 479 dma_unmap_single(&fep->pdev->dev, addr, 480 buflen, DMA_TO_DEVICE); 481 dev_kfree_skb_any(skb); 482 return NETDEV_TX_OK; 483 } 484 } else { 485 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 486 if (fep->bufdesc_ex) { 487 estatus = BD_ENET_TX_INT; 488 if (unlikely(skb_shinfo(skb)->tx_flags & 489 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 490 estatus |= BD_ENET_TX_TS; 491 } 492 } 493 bdp->cbd_bufaddr = cpu_to_fec32(addr); 494 bdp->cbd_datlen = cpu_to_fec16(buflen); 495 496 if (fep->bufdesc_ex) { 497 498 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 499 500 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 501 fep->hwts_tx_en)) 502 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 503 504 if (fep->quirks & FEC_QUIRK_HAS_AVB) 505 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 506 507 if (skb->ip_summed == CHECKSUM_PARTIAL) 508 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 509 510 ebdp->cbd_bdu = 0; 511 ebdp->cbd_esc = cpu_to_fec32(estatus); 512 } 513 514 index = fec_enet_get_bd_index(last_bdp, &txq->bd); 515 /* Save skb pointer */ 516 txq->tx_skbuff[index] = skb; 517 518 /* Make sure the updates to rest of the descriptor are performed before 519 * transferring ownership. 520 */ 521 wmb(); 522 523 /* Send it on its way. Tell FEC it's ready, interrupt when done, 524 * it's the last BD of the frame, and to put the CRC on the end. 525 */ 526 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC); 527 bdp->cbd_sc = cpu_to_fec16(status); 528 529 /* If this was the last BD in the ring, start at the beginning again. */ 530 bdp = fec_enet_get_nextdesc(last_bdp, &txq->bd); 531 532 skb_tx_timestamp(skb); 533 534 /* Make sure the update to bdp and tx_skbuff are performed before 535 * txq->bd.cur. 536 */ 537 wmb(); 538 txq->bd.cur = bdp; 539 540 /* Trigger transmission start */ 541 writel(0, txq->bd.reg_desc_active); 542 543 return 0; 544 } 545 546 static int 547 fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb, 548 struct net_device *ndev, 549 struct bufdesc *bdp, int index, char *data, 550 int size, bool last_tcp, bool is_last) 551 { 552 struct fec_enet_private *fep = netdev_priv(ndev); 553 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 554 unsigned short status; 555 unsigned int estatus = 0; 556 dma_addr_t addr; 557 558 status = fec16_to_cpu(bdp->cbd_sc); 559 status &= ~BD_ENET_TX_STATS; 560 561 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 562 563 if (((unsigned long) data) & fep->tx_align || 564 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 565 memcpy(txq->tx_bounce[index], data, size); 566 data = txq->tx_bounce[index]; 567 568 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 569 swap_buffer(data, size); 570 } 571 572 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE); 573 if (dma_mapping_error(&fep->pdev->dev, addr)) { 574 dev_kfree_skb_any(skb); 575 if (net_ratelimit()) 576 netdev_err(ndev, "Tx DMA memory map failed\n"); 577 return NETDEV_TX_BUSY; 578 } 579 580 bdp->cbd_datlen = cpu_to_fec16(size); 581 bdp->cbd_bufaddr = cpu_to_fec32(addr); 582 583 if (fep->bufdesc_ex) { 584 if (fep->quirks & FEC_QUIRK_HAS_AVB) 585 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 586 if (skb->ip_summed == CHECKSUM_PARTIAL) 587 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 588 ebdp->cbd_bdu = 0; 589 ebdp->cbd_esc = cpu_to_fec32(estatus); 590 } 591 592 /* Handle the last BD specially */ 593 if (last_tcp) 594 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC); 595 if (is_last) { 596 status |= BD_ENET_TX_INTR; 597 if (fep->bufdesc_ex) 598 ebdp->cbd_esc |= cpu_to_fec32(BD_ENET_TX_INT); 599 } 600 601 bdp->cbd_sc = cpu_to_fec16(status); 602 603 return 0; 604 } 605 606 static int 607 fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq, 608 struct sk_buff *skb, struct net_device *ndev, 609 struct bufdesc *bdp, int index) 610 { 611 struct fec_enet_private *fep = netdev_priv(ndev); 612 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 613 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 614 void *bufaddr; 615 unsigned long dmabuf; 616 unsigned short status; 617 unsigned int estatus = 0; 618 619 status = fec16_to_cpu(bdp->cbd_sc); 620 status &= ~BD_ENET_TX_STATS; 621 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 622 623 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 624 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE; 625 if (((unsigned long)bufaddr) & fep->tx_align || 626 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 627 memcpy(txq->tx_bounce[index], skb->data, hdr_len); 628 bufaddr = txq->tx_bounce[index]; 629 630 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 631 swap_buffer(bufaddr, hdr_len); 632 633 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr, 634 hdr_len, DMA_TO_DEVICE); 635 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) { 636 dev_kfree_skb_any(skb); 637 if (net_ratelimit()) 638 netdev_err(ndev, "Tx DMA memory map failed\n"); 639 return NETDEV_TX_BUSY; 640 } 641 } 642 643 bdp->cbd_bufaddr = cpu_to_fec32(dmabuf); 644 bdp->cbd_datlen = cpu_to_fec16(hdr_len); 645 646 if (fep->bufdesc_ex) { 647 if (fep->quirks & FEC_QUIRK_HAS_AVB) 648 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 649 if (skb->ip_summed == CHECKSUM_PARTIAL) 650 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 651 ebdp->cbd_bdu = 0; 652 ebdp->cbd_esc = cpu_to_fec32(estatus); 653 } 654 655 bdp->cbd_sc = cpu_to_fec16(status); 656 657 return 0; 658 } 659 660 static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq, 661 struct sk_buff *skb, 662 struct net_device *ndev) 663 { 664 struct fec_enet_private *fep = netdev_priv(ndev); 665 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 666 int total_len, data_left; 667 struct bufdesc *bdp = txq->bd.cur; 668 struct tso_t tso; 669 unsigned int index = 0; 670 int ret; 671 672 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(txq)) { 673 dev_kfree_skb_any(skb); 674 if (net_ratelimit()) 675 netdev_err(ndev, "NOT enough BD for TSO!\n"); 676 return NETDEV_TX_OK; 677 } 678 679 /* Protocol checksum off-load for TCP and UDP. */ 680 if (fec_enet_clear_csum(skb, ndev)) { 681 dev_kfree_skb_any(skb); 682 return NETDEV_TX_OK; 683 } 684 685 /* Initialize the TSO handler, and prepare the first payload */ 686 tso_start(skb, &tso); 687 688 total_len = skb->len - hdr_len; 689 while (total_len > 0) { 690 char *hdr; 691 692 index = fec_enet_get_bd_index(bdp, &txq->bd); 693 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); 694 total_len -= data_left; 695 696 /* prepare packet headers: MAC + IP + TCP */ 697 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 698 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); 699 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index); 700 if (ret) 701 goto err_release; 702 703 while (data_left > 0) { 704 int size; 705 706 size = min_t(int, tso.size, data_left); 707 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 708 index = fec_enet_get_bd_index(bdp, &txq->bd); 709 ret = fec_enet_txq_put_data_tso(txq, skb, ndev, 710 bdp, index, 711 tso.data, size, 712 size == data_left, 713 total_len == 0); 714 if (ret) 715 goto err_release; 716 717 data_left -= size; 718 tso_build_data(skb, &tso, size); 719 } 720 721 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 722 } 723 724 /* Save skb pointer */ 725 txq->tx_skbuff[index] = skb; 726 727 skb_tx_timestamp(skb); 728 txq->bd.cur = bdp; 729 730 /* Trigger transmission start */ 731 if (!(fep->quirks & FEC_QUIRK_ERR007885) || 732 !readl(txq->bd.reg_desc_active) || 733 !readl(txq->bd.reg_desc_active) || 734 !readl(txq->bd.reg_desc_active) || 735 !readl(txq->bd.reg_desc_active)) 736 writel(0, txq->bd.reg_desc_active); 737 738 return 0; 739 740 err_release: 741 /* TODO: Release all used data descriptors for TSO */ 742 return ret; 743 } 744 745 static netdev_tx_t 746 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) 747 { 748 struct fec_enet_private *fep = netdev_priv(ndev); 749 int entries_free; 750 unsigned short queue; 751 struct fec_enet_priv_tx_q *txq; 752 struct netdev_queue *nq; 753 int ret; 754 755 queue = skb_get_queue_mapping(skb); 756 txq = fep->tx_queue[queue]; 757 nq = netdev_get_tx_queue(ndev, queue); 758 759 if (skb_is_gso(skb)) 760 ret = fec_enet_txq_submit_tso(txq, skb, ndev); 761 else 762 ret = fec_enet_txq_submit_skb(txq, skb, ndev); 763 if (ret) 764 return ret; 765 766 entries_free = fec_enet_get_free_txdesc_num(txq); 767 if (entries_free <= txq->tx_stop_threshold) 768 netif_tx_stop_queue(nq); 769 770 return NETDEV_TX_OK; 771 } 772 773 /* Init RX & TX buffer descriptors 774 */ 775 static void fec_enet_bd_init(struct net_device *dev) 776 { 777 struct fec_enet_private *fep = netdev_priv(dev); 778 struct fec_enet_priv_tx_q *txq; 779 struct fec_enet_priv_rx_q *rxq; 780 struct bufdesc *bdp; 781 unsigned int i; 782 unsigned int q; 783 784 for (q = 0; q < fep->num_rx_queues; q++) { 785 /* Initialize the receive buffer descriptors. */ 786 rxq = fep->rx_queue[q]; 787 bdp = rxq->bd.base; 788 789 for (i = 0; i < rxq->bd.ring_size; i++) { 790 791 /* Initialize the BD for every fragment in the page. */ 792 if (bdp->cbd_bufaddr) 793 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); 794 else 795 bdp->cbd_sc = cpu_to_fec16(0); 796 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 797 } 798 799 /* Set the last buffer to wrap */ 800 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); 801 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 802 803 rxq->bd.cur = rxq->bd.base; 804 } 805 806 for (q = 0; q < fep->num_tx_queues; q++) { 807 /* ...and the same for transmit */ 808 txq = fep->tx_queue[q]; 809 bdp = txq->bd.base; 810 txq->bd.cur = bdp; 811 812 for (i = 0; i < txq->bd.ring_size; i++) { 813 /* Initialize the BD for every fragment in the page. */ 814 bdp->cbd_sc = cpu_to_fec16(0); 815 if (txq->tx_skbuff[i]) { 816 dev_kfree_skb_any(txq->tx_skbuff[i]); 817 txq->tx_skbuff[i] = NULL; 818 } 819 bdp->cbd_bufaddr = cpu_to_fec32(0); 820 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 821 } 822 823 /* Set the last buffer to wrap */ 824 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); 825 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 826 txq->dirty_tx = bdp; 827 } 828 } 829 830 static void fec_enet_active_rxring(struct net_device *ndev) 831 { 832 struct fec_enet_private *fep = netdev_priv(ndev); 833 int i; 834 835 for (i = 0; i < fep->num_rx_queues; i++) 836 writel(0, fep->rx_queue[i]->bd.reg_desc_active); 837 } 838 839 static void fec_enet_enable_ring(struct net_device *ndev) 840 { 841 struct fec_enet_private *fep = netdev_priv(ndev); 842 struct fec_enet_priv_tx_q *txq; 843 struct fec_enet_priv_rx_q *rxq; 844 int i; 845 846 for (i = 0; i < fep->num_rx_queues; i++) { 847 rxq = fep->rx_queue[i]; 848 writel(rxq->bd.dma, fep->hwp + FEC_R_DES_START(i)); 849 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i)); 850 851 /* enable DMA1/2 */ 852 if (i) 853 writel(RCMR_MATCHEN | RCMR_CMP(i), 854 fep->hwp + FEC_RCMR(i)); 855 } 856 857 for (i = 0; i < fep->num_tx_queues; i++) { 858 txq = fep->tx_queue[i]; 859 writel(txq->bd.dma, fep->hwp + FEC_X_DES_START(i)); 860 861 /* enable DMA1/2 */ 862 if (i) 863 writel(DMA_CLASS_EN | IDLE_SLOPE(i), 864 fep->hwp + FEC_DMA_CFG(i)); 865 } 866 } 867 868 static void fec_enet_reset_skb(struct net_device *ndev) 869 { 870 struct fec_enet_private *fep = netdev_priv(ndev); 871 struct fec_enet_priv_tx_q *txq; 872 int i, j; 873 874 for (i = 0; i < fep->num_tx_queues; i++) { 875 txq = fep->tx_queue[i]; 876 877 for (j = 0; j < txq->bd.ring_size; j++) { 878 if (txq->tx_skbuff[j]) { 879 dev_kfree_skb_any(txq->tx_skbuff[j]); 880 txq->tx_skbuff[j] = NULL; 881 } 882 } 883 } 884 } 885 886 /* 887 * This function is called to start or restart the FEC during a link 888 * change, transmit timeout, or to reconfigure the FEC. The network 889 * packet processing for this device must be stopped before this call. 890 */ 891 static void 892 fec_restart(struct net_device *ndev) 893 { 894 struct fec_enet_private *fep = netdev_priv(ndev); 895 u32 val; 896 u32 temp_mac[2]; 897 u32 rcntl = OPT_FRAME_SIZE | 0x04; 898 u32 ecntl = 0x2; /* ETHEREN */ 899 900 /* Whack a reset. We should wait for this. 901 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC 902 * instead of reset MAC itself. 903 */ 904 if (fep->quirks & FEC_QUIRK_HAS_AVB) { 905 writel(0, fep->hwp + FEC_ECNTRL); 906 } else { 907 writel(1, fep->hwp + FEC_ECNTRL); 908 udelay(10); 909 } 910 911 /* 912 * enet-mac reset will reset mac address registers too, 913 * so need to reconfigure it. 914 */ 915 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 916 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN); 917 writel((__force u32)cpu_to_be32(temp_mac[0]), 918 fep->hwp + FEC_ADDR_LOW); 919 writel((__force u32)cpu_to_be32(temp_mac[1]), 920 fep->hwp + FEC_ADDR_HIGH); 921 } 922 923 /* Clear any outstanding interrupt. */ 924 writel(0xffffffff, fep->hwp + FEC_IEVENT); 925 926 fec_enet_bd_init(ndev); 927 928 fec_enet_enable_ring(ndev); 929 930 /* Reset tx SKB buffers. */ 931 fec_enet_reset_skb(ndev); 932 933 /* Enable MII mode */ 934 if (fep->full_duplex == DUPLEX_FULL) { 935 /* FD enable */ 936 writel(0x04, fep->hwp + FEC_X_CNTRL); 937 } else { 938 /* No Rcv on Xmit */ 939 rcntl |= 0x02; 940 writel(0x0, fep->hwp + FEC_X_CNTRL); 941 } 942 943 /* Set MII speed */ 944 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 945 946 #if !defined(CONFIG_M5272) 947 if (fep->quirks & FEC_QUIRK_HAS_RACC) { 948 /* set RX checksum */ 949 val = readl(fep->hwp + FEC_RACC); 950 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED) 951 val |= FEC_RACC_OPTIONS; 952 else 953 val &= ~FEC_RACC_OPTIONS; 954 writel(val, fep->hwp + FEC_RACC); 955 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_FTRL); 956 } 957 #endif 958 959 /* 960 * The phy interface and speed need to get configured 961 * differently on enet-mac. 962 */ 963 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 964 /* Enable flow control and length check */ 965 rcntl |= 0x40000000 | 0x00000020; 966 967 /* RGMII, RMII or MII */ 968 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII || 969 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 970 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID || 971 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) 972 rcntl |= (1 << 6); 973 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 974 rcntl |= (1 << 8); 975 else 976 rcntl &= ~(1 << 8); 977 978 /* 1G, 100M or 10M */ 979 if (ndev->phydev) { 980 if (ndev->phydev->speed == SPEED_1000) 981 ecntl |= (1 << 5); 982 else if (ndev->phydev->speed == SPEED_100) 983 rcntl &= ~(1 << 9); 984 else 985 rcntl |= (1 << 9); 986 } 987 } else { 988 #ifdef FEC_MIIGSK_ENR 989 if (fep->quirks & FEC_QUIRK_USE_GASKET) { 990 u32 cfgr; 991 /* disable the gasket and wait */ 992 writel(0, fep->hwp + FEC_MIIGSK_ENR); 993 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4) 994 udelay(1); 995 996 /* 997 * configure the gasket: 998 * RMII, 50 MHz, no loopback, no echo 999 * MII, 25 MHz, no loopback, no echo 1000 */ 1001 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 1002 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII; 1003 if (ndev->phydev && ndev->phydev->speed == SPEED_10) 1004 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M; 1005 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR); 1006 1007 /* re-enable the gasket */ 1008 writel(2, fep->hwp + FEC_MIIGSK_ENR); 1009 } 1010 #endif 1011 } 1012 1013 #if !defined(CONFIG_M5272) 1014 /* enable pause frame*/ 1015 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) || 1016 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) && 1017 ndev->phydev && ndev->phydev->pause)) { 1018 rcntl |= FEC_ENET_FCE; 1019 1020 /* set FIFO threshold parameter to reduce overrun */ 1021 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM); 1022 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL); 1023 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM); 1024 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL); 1025 1026 /* OPD */ 1027 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD); 1028 } else { 1029 rcntl &= ~FEC_ENET_FCE; 1030 } 1031 #endif /* !defined(CONFIG_M5272) */ 1032 1033 writel(rcntl, fep->hwp + FEC_R_CNTRL); 1034 1035 /* Setup multicast filter. */ 1036 set_multicast_list(ndev); 1037 #ifndef CONFIG_M5272 1038 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); 1039 writel(0, fep->hwp + FEC_HASH_TABLE_LOW); 1040 #endif 1041 1042 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 1043 /* enable ENET endian swap */ 1044 ecntl |= (1 << 8); 1045 /* enable ENET store and forward mode */ 1046 writel(1 << 8, fep->hwp + FEC_X_WMRK); 1047 } 1048 1049 if (fep->bufdesc_ex) 1050 ecntl |= (1 << 4); 1051 1052 #ifndef CONFIG_M5272 1053 /* Enable the MIB statistic event counters */ 1054 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT); 1055 #endif 1056 1057 /* And last, enable the transmit and receive processing */ 1058 writel(ecntl, fep->hwp + FEC_ECNTRL); 1059 fec_enet_active_rxring(ndev); 1060 1061 if (fep->bufdesc_ex) 1062 fec_ptp_start_cyclecounter(ndev); 1063 1064 /* Enable interrupts we wish to service */ 1065 if (fep->link) 1066 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1067 else 1068 writel(FEC_ENET_MII, fep->hwp + FEC_IMASK); 1069 1070 /* Init the interrupt coalescing */ 1071 fec_enet_itr_coal_init(ndev); 1072 1073 } 1074 1075 static void 1076 fec_stop(struct net_device *ndev) 1077 { 1078 struct fec_enet_private *fep = netdev_priv(ndev); 1079 struct fec_platform_data *pdata = fep->pdev->dev.platform_data; 1080 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8); 1081 u32 val; 1082 1083 /* We cannot expect a graceful transmit stop without link !!! */ 1084 if (fep->link) { 1085 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ 1086 udelay(10); 1087 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) 1088 netdev_err(ndev, "Graceful transmit stop did not complete!\n"); 1089 } 1090 1091 /* Whack a reset. We should wait for this. 1092 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC 1093 * instead of reset MAC itself. 1094 */ 1095 if (!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1096 if (fep->quirks & FEC_QUIRK_HAS_AVB) { 1097 writel(0, fep->hwp + FEC_ECNTRL); 1098 } else { 1099 writel(1, fep->hwp + FEC_ECNTRL); 1100 udelay(10); 1101 } 1102 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1103 } else { 1104 writel(FEC_DEFAULT_IMASK | FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK); 1105 val = readl(fep->hwp + FEC_ECNTRL); 1106 val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP); 1107 writel(val, fep->hwp + FEC_ECNTRL); 1108 1109 if (pdata && pdata->sleep_mode_enable) 1110 pdata->sleep_mode_enable(true); 1111 } 1112 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1113 1114 /* We have to keep ENET enabled to have MII interrupt stay working */ 1115 if (fep->quirks & FEC_QUIRK_ENET_MAC && 1116 !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1117 writel(2, fep->hwp + FEC_ECNTRL); 1118 writel(rmii_mode, fep->hwp + FEC_R_CNTRL); 1119 } 1120 } 1121 1122 1123 static void 1124 fec_timeout(struct net_device *ndev) 1125 { 1126 struct fec_enet_private *fep = netdev_priv(ndev); 1127 1128 fec_dump(ndev); 1129 1130 ndev->stats.tx_errors++; 1131 1132 schedule_work(&fep->tx_timeout_work); 1133 } 1134 1135 static void fec_enet_timeout_work(struct work_struct *work) 1136 { 1137 struct fec_enet_private *fep = 1138 container_of(work, struct fec_enet_private, tx_timeout_work); 1139 struct net_device *ndev = fep->netdev; 1140 1141 rtnl_lock(); 1142 if (netif_device_present(ndev) || netif_running(ndev)) { 1143 napi_disable(&fep->napi); 1144 netif_tx_lock_bh(ndev); 1145 fec_restart(ndev); 1146 netif_wake_queue(ndev); 1147 netif_tx_unlock_bh(ndev); 1148 napi_enable(&fep->napi); 1149 } 1150 rtnl_unlock(); 1151 } 1152 1153 static void 1154 fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts, 1155 struct skb_shared_hwtstamps *hwtstamps) 1156 { 1157 unsigned long flags; 1158 u64 ns; 1159 1160 spin_lock_irqsave(&fep->tmreg_lock, flags); 1161 ns = timecounter_cyc2time(&fep->tc, ts); 1162 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 1163 1164 memset(hwtstamps, 0, sizeof(*hwtstamps)); 1165 hwtstamps->hwtstamp = ns_to_ktime(ns); 1166 } 1167 1168 static void 1169 fec_enet_tx_queue(struct net_device *ndev, u16 queue_id) 1170 { 1171 struct fec_enet_private *fep; 1172 struct bufdesc *bdp; 1173 unsigned short status; 1174 struct sk_buff *skb; 1175 struct fec_enet_priv_tx_q *txq; 1176 struct netdev_queue *nq; 1177 int index = 0; 1178 int entries_free; 1179 1180 fep = netdev_priv(ndev); 1181 1182 queue_id = FEC_ENET_GET_QUQUE(queue_id); 1183 1184 txq = fep->tx_queue[queue_id]; 1185 /* get next bdp of dirty_tx */ 1186 nq = netdev_get_tx_queue(ndev, queue_id); 1187 bdp = txq->dirty_tx; 1188 1189 /* get next bdp of dirty_tx */ 1190 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1191 1192 while (bdp != READ_ONCE(txq->bd.cur)) { 1193 /* Order the load of bd.cur and cbd_sc */ 1194 rmb(); 1195 status = fec16_to_cpu(READ_ONCE(bdp->cbd_sc)); 1196 if (status & BD_ENET_TX_READY) 1197 break; 1198 1199 index = fec_enet_get_bd_index(bdp, &txq->bd); 1200 1201 skb = txq->tx_skbuff[index]; 1202 txq->tx_skbuff[index] = NULL; 1203 if (!IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr))) 1204 dma_unmap_single(&fep->pdev->dev, 1205 fec32_to_cpu(bdp->cbd_bufaddr), 1206 fec16_to_cpu(bdp->cbd_datlen), 1207 DMA_TO_DEVICE); 1208 bdp->cbd_bufaddr = cpu_to_fec32(0); 1209 if (!skb) 1210 goto skb_done; 1211 1212 /* Check for errors. */ 1213 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | 1214 BD_ENET_TX_RL | BD_ENET_TX_UN | 1215 BD_ENET_TX_CSL)) { 1216 ndev->stats.tx_errors++; 1217 if (status & BD_ENET_TX_HB) /* No heartbeat */ 1218 ndev->stats.tx_heartbeat_errors++; 1219 if (status & BD_ENET_TX_LC) /* Late collision */ 1220 ndev->stats.tx_window_errors++; 1221 if (status & BD_ENET_TX_RL) /* Retrans limit */ 1222 ndev->stats.tx_aborted_errors++; 1223 if (status & BD_ENET_TX_UN) /* Underrun */ 1224 ndev->stats.tx_fifo_errors++; 1225 if (status & BD_ENET_TX_CSL) /* Carrier lost */ 1226 ndev->stats.tx_carrier_errors++; 1227 } else { 1228 ndev->stats.tx_packets++; 1229 ndev->stats.tx_bytes += skb->len; 1230 } 1231 1232 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) && 1233 fep->bufdesc_ex) { 1234 struct skb_shared_hwtstamps shhwtstamps; 1235 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1236 1237 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), &shhwtstamps); 1238 skb_tstamp_tx(skb, &shhwtstamps); 1239 } 1240 1241 /* Deferred means some collisions occurred during transmit, 1242 * but we eventually sent the packet OK. 1243 */ 1244 if (status & BD_ENET_TX_DEF) 1245 ndev->stats.collisions++; 1246 1247 /* Free the sk buffer associated with this last transmit */ 1248 dev_kfree_skb_any(skb); 1249 skb_done: 1250 /* Make sure the update to bdp and tx_skbuff are performed 1251 * before dirty_tx 1252 */ 1253 wmb(); 1254 txq->dirty_tx = bdp; 1255 1256 /* Update pointer to next buffer descriptor to be transmitted */ 1257 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1258 1259 /* Since we have freed up a buffer, the ring is no longer full 1260 */ 1261 if (netif_queue_stopped(ndev)) { 1262 entries_free = fec_enet_get_free_txdesc_num(txq); 1263 if (entries_free >= txq->tx_wake_threshold) 1264 netif_tx_wake_queue(nq); 1265 } 1266 } 1267 1268 /* ERR006538: Keep the transmitter going */ 1269 if (bdp != txq->bd.cur && 1270 readl(txq->bd.reg_desc_active) == 0) 1271 writel(0, txq->bd.reg_desc_active); 1272 } 1273 1274 static void 1275 fec_enet_tx(struct net_device *ndev) 1276 { 1277 struct fec_enet_private *fep = netdev_priv(ndev); 1278 u16 queue_id; 1279 /* First process class A queue, then Class B and Best Effort queue */ 1280 for_each_set_bit(queue_id, &fep->work_tx, FEC_ENET_MAX_TX_QS) { 1281 clear_bit(queue_id, &fep->work_tx); 1282 fec_enet_tx_queue(ndev, queue_id); 1283 } 1284 return; 1285 } 1286 1287 static int 1288 fec_enet_new_rxbdp(struct net_device *ndev, struct bufdesc *bdp, struct sk_buff *skb) 1289 { 1290 struct fec_enet_private *fep = netdev_priv(ndev); 1291 int off; 1292 1293 off = ((unsigned long)skb->data) & fep->rx_align; 1294 if (off) 1295 skb_reserve(skb, fep->rx_align + 1 - off); 1296 1297 bdp->cbd_bufaddr = cpu_to_fec32(dma_map_single(&fep->pdev->dev, skb->data, FEC_ENET_RX_FRSIZE - fep->rx_align, DMA_FROM_DEVICE)); 1298 if (dma_mapping_error(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr))) { 1299 if (net_ratelimit()) 1300 netdev_err(ndev, "Rx DMA memory map failed\n"); 1301 return -ENOMEM; 1302 } 1303 1304 return 0; 1305 } 1306 1307 static bool fec_enet_copybreak(struct net_device *ndev, struct sk_buff **skb, 1308 struct bufdesc *bdp, u32 length, bool swap) 1309 { 1310 struct fec_enet_private *fep = netdev_priv(ndev); 1311 struct sk_buff *new_skb; 1312 1313 if (length > fep->rx_copybreak) 1314 return false; 1315 1316 new_skb = netdev_alloc_skb(ndev, length); 1317 if (!new_skb) 1318 return false; 1319 1320 dma_sync_single_for_cpu(&fep->pdev->dev, 1321 fec32_to_cpu(bdp->cbd_bufaddr), 1322 FEC_ENET_RX_FRSIZE - fep->rx_align, 1323 DMA_FROM_DEVICE); 1324 if (!swap) 1325 memcpy(new_skb->data, (*skb)->data, length); 1326 else 1327 swap_buffer2(new_skb->data, (*skb)->data, length); 1328 *skb = new_skb; 1329 1330 return true; 1331 } 1332 1333 /* During a receive, the bd_rx.cur points to the current incoming buffer. 1334 * When we update through the ring, if the next incoming buffer has 1335 * not been given to the system, we just set the empty indicator, 1336 * effectively tossing the packet. 1337 */ 1338 static int 1339 fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id) 1340 { 1341 struct fec_enet_private *fep = netdev_priv(ndev); 1342 struct fec_enet_priv_rx_q *rxq; 1343 struct bufdesc *bdp; 1344 unsigned short status; 1345 struct sk_buff *skb_new = NULL; 1346 struct sk_buff *skb; 1347 ushort pkt_len; 1348 __u8 *data; 1349 int pkt_received = 0; 1350 struct bufdesc_ex *ebdp = NULL; 1351 bool vlan_packet_rcvd = false; 1352 u16 vlan_tag; 1353 int index = 0; 1354 bool is_copybreak; 1355 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME; 1356 1357 #ifdef CONFIG_M532x 1358 flush_cache_all(); 1359 #endif 1360 queue_id = FEC_ENET_GET_QUQUE(queue_id); 1361 rxq = fep->rx_queue[queue_id]; 1362 1363 /* First, grab all of the stats for the incoming packet. 1364 * These get messed up if we get called due to a busy condition. 1365 */ 1366 bdp = rxq->bd.cur; 1367 1368 while (!((status = fec16_to_cpu(bdp->cbd_sc)) & BD_ENET_RX_EMPTY)) { 1369 1370 if (pkt_received >= budget) 1371 break; 1372 pkt_received++; 1373 1374 writel(FEC_ENET_RXF, fep->hwp + FEC_IEVENT); 1375 1376 /* Check for errors. */ 1377 status ^= BD_ENET_RX_LAST; 1378 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | 1379 BD_ENET_RX_CR | BD_ENET_RX_OV | BD_ENET_RX_LAST | 1380 BD_ENET_RX_CL)) { 1381 ndev->stats.rx_errors++; 1382 if (status & BD_ENET_RX_OV) { 1383 /* FIFO overrun */ 1384 ndev->stats.rx_fifo_errors++; 1385 goto rx_processing_done; 1386 } 1387 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH 1388 | BD_ENET_RX_LAST)) { 1389 /* Frame too long or too short. */ 1390 ndev->stats.rx_length_errors++; 1391 if (status & BD_ENET_RX_LAST) 1392 netdev_err(ndev, "rcv is not +last\n"); 1393 } 1394 if (status & BD_ENET_RX_CR) /* CRC Error */ 1395 ndev->stats.rx_crc_errors++; 1396 /* Report late collisions as a frame error. */ 1397 if (status & (BD_ENET_RX_NO | BD_ENET_RX_CL)) 1398 ndev->stats.rx_frame_errors++; 1399 goto rx_processing_done; 1400 } 1401 1402 /* Process the incoming frame. */ 1403 ndev->stats.rx_packets++; 1404 pkt_len = fec16_to_cpu(bdp->cbd_datlen); 1405 ndev->stats.rx_bytes += pkt_len; 1406 1407 index = fec_enet_get_bd_index(bdp, &rxq->bd); 1408 skb = rxq->rx_skbuff[index]; 1409 1410 /* The packet length includes FCS, but we don't want to 1411 * include that when passing upstream as it messes up 1412 * bridging applications. 1413 */ 1414 is_copybreak = fec_enet_copybreak(ndev, &skb, bdp, pkt_len - 4, 1415 need_swap); 1416 if (!is_copybreak) { 1417 skb_new = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE); 1418 if (unlikely(!skb_new)) { 1419 ndev->stats.rx_dropped++; 1420 goto rx_processing_done; 1421 } 1422 dma_unmap_single(&fep->pdev->dev, 1423 fec32_to_cpu(bdp->cbd_bufaddr), 1424 FEC_ENET_RX_FRSIZE - fep->rx_align, 1425 DMA_FROM_DEVICE); 1426 } 1427 1428 prefetch(skb->data - NET_IP_ALIGN); 1429 skb_put(skb, pkt_len - 4); 1430 data = skb->data; 1431 if (!is_copybreak && need_swap) 1432 swap_buffer(data, pkt_len); 1433 1434 /* Extract the enhanced buffer descriptor */ 1435 ebdp = NULL; 1436 if (fep->bufdesc_ex) 1437 ebdp = (struct bufdesc_ex *)bdp; 1438 1439 /* If this is a VLAN packet remove the VLAN Tag */ 1440 vlan_packet_rcvd = false; 1441 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) && 1442 fep->bufdesc_ex && 1443 (ebdp->cbd_esc & cpu_to_fec32(BD_ENET_RX_VLAN))) { 1444 /* Push and remove the vlan tag */ 1445 struct vlan_hdr *vlan_header = 1446 (struct vlan_hdr *) (data + ETH_HLEN); 1447 vlan_tag = ntohs(vlan_header->h_vlan_TCI); 1448 1449 vlan_packet_rcvd = true; 1450 1451 memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2); 1452 skb_pull(skb, VLAN_HLEN); 1453 } 1454 1455 skb->protocol = eth_type_trans(skb, ndev); 1456 1457 /* Get receive timestamp from the skb */ 1458 if (fep->hwts_rx_en && fep->bufdesc_ex) 1459 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), 1460 skb_hwtstamps(skb)); 1461 1462 if (fep->bufdesc_ex && 1463 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) { 1464 if (!(ebdp->cbd_esc & cpu_to_fec32(FLAG_RX_CSUM_ERROR))) { 1465 /* don't check it */ 1466 skb->ip_summed = CHECKSUM_UNNECESSARY; 1467 } else { 1468 skb_checksum_none_assert(skb); 1469 } 1470 } 1471 1472 /* Handle received VLAN packets */ 1473 if (vlan_packet_rcvd) 1474 __vlan_hwaccel_put_tag(skb, 1475 htons(ETH_P_8021Q), 1476 vlan_tag); 1477 1478 napi_gro_receive(&fep->napi, skb); 1479 1480 if (is_copybreak) { 1481 dma_sync_single_for_device(&fep->pdev->dev, 1482 fec32_to_cpu(bdp->cbd_bufaddr), 1483 FEC_ENET_RX_FRSIZE - fep->rx_align, 1484 DMA_FROM_DEVICE); 1485 } else { 1486 rxq->rx_skbuff[index] = skb_new; 1487 fec_enet_new_rxbdp(ndev, bdp, skb_new); 1488 } 1489 1490 rx_processing_done: 1491 /* Clear the status flags for this buffer */ 1492 status &= ~BD_ENET_RX_STATS; 1493 1494 /* Mark the buffer empty */ 1495 status |= BD_ENET_RX_EMPTY; 1496 1497 if (fep->bufdesc_ex) { 1498 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1499 1500 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); 1501 ebdp->cbd_prot = 0; 1502 ebdp->cbd_bdu = 0; 1503 } 1504 /* Make sure the updates to rest of the descriptor are 1505 * performed before transferring ownership. 1506 */ 1507 wmb(); 1508 bdp->cbd_sc = cpu_to_fec16(status); 1509 1510 /* Update BD pointer to next entry */ 1511 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 1512 1513 /* Doing this here will keep the FEC running while we process 1514 * incoming frames. On a heavily loaded network, we should be 1515 * able to keep up at the expense of system resources. 1516 */ 1517 writel(0, rxq->bd.reg_desc_active); 1518 } 1519 rxq->bd.cur = bdp; 1520 return pkt_received; 1521 } 1522 1523 static int 1524 fec_enet_rx(struct net_device *ndev, int budget) 1525 { 1526 int pkt_received = 0; 1527 u16 queue_id; 1528 struct fec_enet_private *fep = netdev_priv(ndev); 1529 1530 for_each_set_bit(queue_id, &fep->work_rx, FEC_ENET_MAX_RX_QS) { 1531 int ret; 1532 1533 ret = fec_enet_rx_queue(ndev, 1534 budget - pkt_received, queue_id); 1535 1536 if (ret < budget - pkt_received) 1537 clear_bit(queue_id, &fep->work_rx); 1538 1539 pkt_received += ret; 1540 } 1541 return pkt_received; 1542 } 1543 1544 static bool 1545 fec_enet_collect_events(struct fec_enet_private *fep, uint int_events) 1546 { 1547 if (int_events == 0) 1548 return false; 1549 1550 if (int_events & FEC_ENET_RXF) 1551 fep->work_rx |= (1 << 2); 1552 if (int_events & FEC_ENET_RXF_1) 1553 fep->work_rx |= (1 << 0); 1554 if (int_events & FEC_ENET_RXF_2) 1555 fep->work_rx |= (1 << 1); 1556 1557 if (int_events & FEC_ENET_TXF) 1558 fep->work_tx |= (1 << 2); 1559 if (int_events & FEC_ENET_TXF_1) 1560 fep->work_tx |= (1 << 0); 1561 if (int_events & FEC_ENET_TXF_2) 1562 fep->work_tx |= (1 << 1); 1563 1564 return true; 1565 } 1566 1567 static irqreturn_t 1568 fec_enet_interrupt(int irq, void *dev_id) 1569 { 1570 struct net_device *ndev = dev_id; 1571 struct fec_enet_private *fep = netdev_priv(ndev); 1572 uint int_events; 1573 irqreturn_t ret = IRQ_NONE; 1574 1575 int_events = readl(fep->hwp + FEC_IEVENT); 1576 writel(int_events, fep->hwp + FEC_IEVENT); 1577 fec_enet_collect_events(fep, int_events); 1578 1579 if ((fep->work_tx || fep->work_rx) && fep->link) { 1580 ret = IRQ_HANDLED; 1581 1582 if (napi_schedule_prep(&fep->napi)) { 1583 /* Disable the NAPI interrupts */ 1584 writel(FEC_NAPI_IMASK, fep->hwp + FEC_IMASK); 1585 __napi_schedule(&fep->napi); 1586 } 1587 } 1588 1589 if (int_events & FEC_ENET_MII) { 1590 ret = IRQ_HANDLED; 1591 complete(&fep->mdio_done); 1592 } 1593 1594 if (fep->ptp_clock) 1595 fec_ptp_check_pps_event(fep); 1596 1597 return ret; 1598 } 1599 1600 static int fec_enet_rx_napi(struct napi_struct *napi, int budget) 1601 { 1602 struct net_device *ndev = napi->dev; 1603 struct fec_enet_private *fep = netdev_priv(ndev); 1604 int pkts; 1605 1606 pkts = fec_enet_rx(ndev, budget); 1607 1608 fec_enet_tx(ndev); 1609 1610 if (pkts < budget) { 1611 napi_complete(napi); 1612 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1613 } 1614 return pkts; 1615 } 1616 1617 /* ------------------------------------------------------------------------- */ 1618 static void fec_get_mac(struct net_device *ndev) 1619 { 1620 struct fec_enet_private *fep = netdev_priv(ndev); 1621 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev); 1622 unsigned char *iap, tmpaddr[ETH_ALEN]; 1623 1624 /* 1625 * try to get mac address in following order: 1626 * 1627 * 1) module parameter via kernel command line in form 1628 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0 1629 */ 1630 iap = macaddr; 1631 1632 /* 1633 * 2) from device tree data 1634 */ 1635 if (!is_valid_ether_addr(iap)) { 1636 struct device_node *np = fep->pdev->dev.of_node; 1637 if (np) { 1638 const char *mac = of_get_mac_address(np); 1639 if (mac) 1640 iap = (unsigned char *) mac; 1641 } 1642 } 1643 1644 /* 1645 * 3) from flash or fuse (via platform data) 1646 */ 1647 if (!is_valid_ether_addr(iap)) { 1648 #ifdef CONFIG_M5272 1649 if (FEC_FLASHMAC) 1650 iap = (unsigned char *)FEC_FLASHMAC; 1651 #else 1652 if (pdata) 1653 iap = (unsigned char *)&pdata->mac; 1654 #endif 1655 } 1656 1657 /* 1658 * 4) FEC mac registers set by bootloader 1659 */ 1660 if (!is_valid_ether_addr(iap)) { 1661 *((__be32 *) &tmpaddr[0]) = 1662 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW)); 1663 *((__be16 *) &tmpaddr[4]) = 1664 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16); 1665 iap = &tmpaddr[0]; 1666 } 1667 1668 /* 1669 * 5) random mac address 1670 */ 1671 if (!is_valid_ether_addr(iap)) { 1672 /* Report it and use a random ethernet address instead */ 1673 netdev_err(ndev, "Invalid MAC address: %pM\n", iap); 1674 eth_hw_addr_random(ndev); 1675 netdev_info(ndev, "Using random MAC address: %pM\n", 1676 ndev->dev_addr); 1677 return; 1678 } 1679 1680 memcpy(ndev->dev_addr, iap, ETH_ALEN); 1681 1682 /* Adjust MAC if using macaddr */ 1683 if (iap == macaddr) 1684 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id; 1685 } 1686 1687 /* ------------------------------------------------------------------------- */ 1688 1689 /* 1690 * Phy section 1691 */ 1692 static void fec_enet_adjust_link(struct net_device *ndev) 1693 { 1694 struct fec_enet_private *fep = netdev_priv(ndev); 1695 struct phy_device *phy_dev = ndev->phydev; 1696 int status_change = 0; 1697 1698 /* Prevent a state halted on mii error */ 1699 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) { 1700 phy_dev->state = PHY_RESUMING; 1701 return; 1702 } 1703 1704 /* 1705 * If the netdev is down, or is going down, we're not interested 1706 * in link state events, so just mark our idea of the link as down 1707 * and ignore the event. 1708 */ 1709 if (!netif_running(ndev) || !netif_device_present(ndev)) { 1710 fep->link = 0; 1711 } else if (phy_dev->link) { 1712 if (!fep->link) { 1713 fep->link = phy_dev->link; 1714 status_change = 1; 1715 } 1716 1717 if (fep->full_duplex != phy_dev->duplex) { 1718 fep->full_duplex = phy_dev->duplex; 1719 status_change = 1; 1720 } 1721 1722 if (phy_dev->speed != fep->speed) { 1723 fep->speed = phy_dev->speed; 1724 status_change = 1; 1725 } 1726 1727 /* if any of the above changed restart the FEC */ 1728 if (status_change) { 1729 napi_disable(&fep->napi); 1730 netif_tx_lock_bh(ndev); 1731 fec_restart(ndev); 1732 netif_wake_queue(ndev); 1733 netif_tx_unlock_bh(ndev); 1734 napi_enable(&fep->napi); 1735 } 1736 } else { 1737 if (fep->link) { 1738 napi_disable(&fep->napi); 1739 netif_tx_lock_bh(ndev); 1740 fec_stop(ndev); 1741 netif_tx_unlock_bh(ndev); 1742 napi_enable(&fep->napi); 1743 fep->link = phy_dev->link; 1744 status_change = 1; 1745 } 1746 } 1747 1748 if (status_change) 1749 phy_print_status(phy_dev); 1750 } 1751 1752 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) 1753 { 1754 struct fec_enet_private *fep = bus->priv; 1755 struct device *dev = &fep->pdev->dev; 1756 unsigned long time_left; 1757 int ret = 0; 1758 1759 ret = pm_runtime_get_sync(dev); 1760 if (ret < 0) 1761 return ret; 1762 1763 fep->mii_timeout = 0; 1764 reinit_completion(&fep->mdio_done); 1765 1766 /* start a read op */ 1767 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ | 1768 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | 1769 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); 1770 1771 /* wait for end of transfer */ 1772 time_left = wait_for_completion_timeout(&fep->mdio_done, 1773 usecs_to_jiffies(FEC_MII_TIMEOUT)); 1774 if (time_left == 0) { 1775 fep->mii_timeout = 1; 1776 netdev_err(fep->netdev, "MDIO read timeout\n"); 1777 ret = -ETIMEDOUT; 1778 goto out; 1779 } 1780 1781 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); 1782 1783 out: 1784 pm_runtime_mark_last_busy(dev); 1785 pm_runtime_put_autosuspend(dev); 1786 1787 return ret; 1788 } 1789 1790 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, 1791 u16 value) 1792 { 1793 struct fec_enet_private *fep = bus->priv; 1794 struct device *dev = &fep->pdev->dev; 1795 unsigned long time_left; 1796 int ret; 1797 1798 ret = pm_runtime_get_sync(dev); 1799 if (ret < 0) 1800 return ret; 1801 else 1802 ret = 0; 1803 1804 fep->mii_timeout = 0; 1805 reinit_completion(&fep->mdio_done); 1806 1807 /* start a write op */ 1808 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE | 1809 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | 1810 FEC_MMFR_TA | FEC_MMFR_DATA(value), 1811 fep->hwp + FEC_MII_DATA); 1812 1813 /* wait for end of transfer */ 1814 time_left = wait_for_completion_timeout(&fep->mdio_done, 1815 usecs_to_jiffies(FEC_MII_TIMEOUT)); 1816 if (time_left == 0) { 1817 fep->mii_timeout = 1; 1818 netdev_err(fep->netdev, "MDIO write timeout\n"); 1819 ret = -ETIMEDOUT; 1820 } 1821 1822 pm_runtime_mark_last_busy(dev); 1823 pm_runtime_put_autosuspend(dev); 1824 1825 return ret; 1826 } 1827 1828 static int fec_enet_clk_enable(struct net_device *ndev, bool enable) 1829 { 1830 struct fec_enet_private *fep = netdev_priv(ndev); 1831 int ret; 1832 1833 if (enable) { 1834 ret = clk_prepare_enable(fep->clk_ahb); 1835 if (ret) 1836 return ret; 1837 if (fep->clk_enet_out) { 1838 ret = clk_prepare_enable(fep->clk_enet_out); 1839 if (ret) 1840 goto failed_clk_enet_out; 1841 } 1842 if (fep->clk_ptp) { 1843 mutex_lock(&fep->ptp_clk_mutex); 1844 ret = clk_prepare_enable(fep->clk_ptp); 1845 if (ret) { 1846 mutex_unlock(&fep->ptp_clk_mutex); 1847 goto failed_clk_ptp; 1848 } else { 1849 fep->ptp_clk_on = true; 1850 } 1851 mutex_unlock(&fep->ptp_clk_mutex); 1852 } 1853 if (fep->clk_ref) { 1854 ret = clk_prepare_enable(fep->clk_ref); 1855 if (ret) 1856 goto failed_clk_ref; 1857 } 1858 } else { 1859 clk_disable_unprepare(fep->clk_ahb); 1860 if (fep->clk_enet_out) 1861 clk_disable_unprepare(fep->clk_enet_out); 1862 if (fep->clk_ptp) { 1863 mutex_lock(&fep->ptp_clk_mutex); 1864 clk_disable_unprepare(fep->clk_ptp); 1865 fep->ptp_clk_on = false; 1866 mutex_unlock(&fep->ptp_clk_mutex); 1867 } 1868 if (fep->clk_ref) 1869 clk_disable_unprepare(fep->clk_ref); 1870 } 1871 1872 return 0; 1873 1874 failed_clk_ref: 1875 if (fep->clk_ref) 1876 clk_disable_unprepare(fep->clk_ref); 1877 failed_clk_ptp: 1878 if (fep->clk_enet_out) 1879 clk_disable_unprepare(fep->clk_enet_out); 1880 failed_clk_enet_out: 1881 clk_disable_unprepare(fep->clk_ahb); 1882 1883 return ret; 1884 } 1885 1886 static int fec_enet_mii_probe(struct net_device *ndev) 1887 { 1888 struct fec_enet_private *fep = netdev_priv(ndev); 1889 struct phy_device *phy_dev = NULL; 1890 char mdio_bus_id[MII_BUS_ID_SIZE]; 1891 char phy_name[MII_BUS_ID_SIZE + 3]; 1892 int phy_id; 1893 int dev_id = fep->dev_id; 1894 1895 if (fep->phy_node) { 1896 phy_dev = of_phy_connect(ndev, fep->phy_node, 1897 &fec_enet_adjust_link, 0, 1898 fep->phy_interface); 1899 if (!phy_dev) 1900 return -ENODEV; 1901 } else { 1902 /* check for attached phy */ 1903 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) { 1904 if (!mdiobus_is_registered_device(fep->mii_bus, phy_id)) 1905 continue; 1906 if (dev_id--) 1907 continue; 1908 strlcpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE); 1909 break; 1910 } 1911 1912 if (phy_id >= PHY_MAX_ADDR) { 1913 netdev_info(ndev, "no PHY, assuming direct connection to switch\n"); 1914 strlcpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); 1915 phy_id = 0; 1916 } 1917 1918 snprintf(phy_name, sizeof(phy_name), 1919 PHY_ID_FMT, mdio_bus_id, phy_id); 1920 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, 1921 fep->phy_interface); 1922 } 1923 1924 if (IS_ERR(phy_dev)) { 1925 netdev_err(ndev, "could not attach to PHY\n"); 1926 return PTR_ERR(phy_dev); 1927 } 1928 1929 /* mask with MAC supported features */ 1930 if (fep->quirks & FEC_QUIRK_HAS_GBIT) { 1931 phy_dev->supported &= PHY_GBIT_FEATURES; 1932 phy_dev->supported &= ~SUPPORTED_1000baseT_Half; 1933 #if !defined(CONFIG_M5272) 1934 phy_dev->supported |= SUPPORTED_Pause; 1935 #endif 1936 } 1937 else 1938 phy_dev->supported &= PHY_BASIC_FEATURES; 1939 1940 phy_dev->advertising = phy_dev->supported; 1941 1942 fep->link = 0; 1943 fep->full_duplex = 0; 1944 1945 phy_attached_info(phy_dev); 1946 1947 return 0; 1948 } 1949 1950 static int fec_enet_mii_init(struct platform_device *pdev) 1951 { 1952 static struct mii_bus *fec0_mii_bus; 1953 struct net_device *ndev = platform_get_drvdata(pdev); 1954 struct fec_enet_private *fep = netdev_priv(ndev); 1955 struct device_node *node; 1956 int err = -ENXIO; 1957 u32 mii_speed, holdtime; 1958 1959 /* 1960 * The i.MX28 dual fec interfaces are not equal. 1961 * Here are the differences: 1962 * 1963 * - fec0 supports MII & RMII modes while fec1 only supports RMII 1964 * - fec0 acts as the 1588 time master while fec1 is slave 1965 * - external phys can only be configured by fec0 1966 * 1967 * That is to say fec1 can not work independently. It only works 1968 * when fec0 is working. The reason behind this design is that the 1969 * second interface is added primarily for Switch mode. 1970 * 1971 * Because of the last point above, both phys are attached on fec0 1972 * mdio interface in board design, and need to be configured by 1973 * fec0 mii_bus. 1974 */ 1975 if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) { 1976 /* fec1 uses fec0 mii_bus */ 1977 if (mii_cnt && fec0_mii_bus) { 1978 fep->mii_bus = fec0_mii_bus; 1979 mii_cnt++; 1980 return 0; 1981 } 1982 return -ENOENT; 1983 } 1984 1985 fep->mii_timeout = 0; 1986 1987 /* 1988 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed) 1989 * 1990 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while 1991 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28 1992 * Reference Manual has an error on this, and gets fixed on i.MX6Q 1993 * document. 1994 */ 1995 mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 5000000); 1996 if (fep->quirks & FEC_QUIRK_ENET_MAC) 1997 mii_speed--; 1998 if (mii_speed > 63) { 1999 dev_err(&pdev->dev, 2000 "fec clock (%lu) to fast to get right mii speed\n", 2001 clk_get_rate(fep->clk_ipg)); 2002 err = -EINVAL; 2003 goto err_out; 2004 } 2005 2006 /* 2007 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka 2008 * MII_SPEED) register that defines the MDIO output hold time. Earlier 2009 * versions are RAZ there, so just ignore the difference and write the 2010 * register always. 2011 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns. 2012 * HOLDTIME + 1 is the number of clk cycles the fec is holding the 2013 * output. 2014 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive). 2015 * Given that ceil(clkrate / 5000000) <= 64, the calculation for 2016 * holdtime cannot result in a value greater than 3. 2017 */ 2018 holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1; 2019 2020 fep->phy_speed = mii_speed << 1 | holdtime << 8; 2021 2022 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 2023 2024 fep->mii_bus = mdiobus_alloc(); 2025 if (fep->mii_bus == NULL) { 2026 err = -ENOMEM; 2027 goto err_out; 2028 } 2029 2030 fep->mii_bus->name = "fec_enet_mii_bus"; 2031 fep->mii_bus->read = fec_enet_mdio_read; 2032 fep->mii_bus->write = fec_enet_mdio_write; 2033 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 2034 pdev->name, fep->dev_id + 1); 2035 fep->mii_bus->priv = fep; 2036 fep->mii_bus->parent = &pdev->dev; 2037 2038 node = of_get_child_by_name(pdev->dev.of_node, "mdio"); 2039 if (node) { 2040 err = of_mdiobus_register(fep->mii_bus, node); 2041 of_node_put(node); 2042 } else { 2043 err = mdiobus_register(fep->mii_bus); 2044 } 2045 2046 if (err) 2047 goto err_out_free_mdiobus; 2048 2049 mii_cnt++; 2050 2051 /* save fec0 mii_bus */ 2052 if (fep->quirks & FEC_QUIRK_SINGLE_MDIO) 2053 fec0_mii_bus = fep->mii_bus; 2054 2055 return 0; 2056 2057 err_out_free_mdiobus: 2058 mdiobus_free(fep->mii_bus); 2059 err_out: 2060 return err; 2061 } 2062 2063 static void fec_enet_mii_remove(struct fec_enet_private *fep) 2064 { 2065 if (--mii_cnt == 0) { 2066 mdiobus_unregister(fep->mii_bus); 2067 mdiobus_free(fep->mii_bus); 2068 } 2069 } 2070 2071 static void fec_enet_get_drvinfo(struct net_device *ndev, 2072 struct ethtool_drvinfo *info) 2073 { 2074 struct fec_enet_private *fep = netdev_priv(ndev); 2075 2076 strlcpy(info->driver, fep->pdev->dev.driver->name, 2077 sizeof(info->driver)); 2078 strlcpy(info->version, "Revision: 1.0", sizeof(info->version)); 2079 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info)); 2080 } 2081 2082 static int fec_enet_get_regs_len(struct net_device *ndev) 2083 { 2084 struct fec_enet_private *fep = netdev_priv(ndev); 2085 struct resource *r; 2086 int s = 0; 2087 2088 r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0); 2089 if (r) 2090 s = resource_size(r); 2091 2092 return s; 2093 } 2094 2095 /* List of registers that can be safety be read to dump them with ethtool */ 2096 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 2097 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) 2098 static u32 fec_enet_register_offset[] = { 2099 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0, 2100 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL, 2101 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1, 2102 FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH, 2103 FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, 2104 FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1, 2105 FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2, 2106 FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0, 2107 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM, 2108 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2, 2109 FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1, 2110 FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME, 2111 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT, 2112 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG, 2113 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255, 2114 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047, 2115 RMON_T_P_GTE2048, RMON_T_OCTETS, 2116 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF, 2117 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE, 2118 IEEE_T_FDXFC, IEEE_T_OCTETS_OK, 2119 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN, 2120 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB, 2121 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255, 2122 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047, 2123 RMON_R_P_GTE2048, RMON_R_OCTETS, 2124 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR, 2125 IEEE_R_FDXFC, IEEE_R_OCTETS_OK 2126 }; 2127 #else 2128 static u32 fec_enet_register_offset[] = { 2129 FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0, 2130 FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0, 2131 FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED, 2132 FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL, 2133 FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, 2134 FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0, 2135 FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0, 2136 FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0, 2137 FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2 2138 }; 2139 #endif 2140 2141 static void fec_enet_get_regs(struct net_device *ndev, 2142 struct ethtool_regs *regs, void *regbuf) 2143 { 2144 struct fec_enet_private *fep = netdev_priv(ndev); 2145 u32 __iomem *theregs = (u32 __iomem *)fep->hwp; 2146 u32 *buf = (u32 *)regbuf; 2147 u32 i, off; 2148 2149 memset(buf, 0, regs->len); 2150 2151 for (i = 0; i < ARRAY_SIZE(fec_enet_register_offset); i++) { 2152 off = fec_enet_register_offset[i] / 4; 2153 buf[off] = readl(&theregs[off]); 2154 } 2155 } 2156 2157 static int fec_enet_get_ts_info(struct net_device *ndev, 2158 struct ethtool_ts_info *info) 2159 { 2160 struct fec_enet_private *fep = netdev_priv(ndev); 2161 2162 if (fep->bufdesc_ex) { 2163 2164 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 2165 SOF_TIMESTAMPING_RX_SOFTWARE | 2166 SOF_TIMESTAMPING_SOFTWARE | 2167 SOF_TIMESTAMPING_TX_HARDWARE | 2168 SOF_TIMESTAMPING_RX_HARDWARE | 2169 SOF_TIMESTAMPING_RAW_HARDWARE; 2170 if (fep->ptp_clock) 2171 info->phc_index = ptp_clock_index(fep->ptp_clock); 2172 else 2173 info->phc_index = -1; 2174 2175 info->tx_types = (1 << HWTSTAMP_TX_OFF) | 2176 (1 << HWTSTAMP_TX_ON); 2177 2178 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 2179 (1 << HWTSTAMP_FILTER_ALL); 2180 return 0; 2181 } else { 2182 return ethtool_op_get_ts_info(ndev, info); 2183 } 2184 } 2185 2186 #if !defined(CONFIG_M5272) 2187 2188 static void fec_enet_get_pauseparam(struct net_device *ndev, 2189 struct ethtool_pauseparam *pause) 2190 { 2191 struct fec_enet_private *fep = netdev_priv(ndev); 2192 2193 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0; 2194 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0; 2195 pause->rx_pause = pause->tx_pause; 2196 } 2197 2198 static int fec_enet_set_pauseparam(struct net_device *ndev, 2199 struct ethtool_pauseparam *pause) 2200 { 2201 struct fec_enet_private *fep = netdev_priv(ndev); 2202 2203 if (!ndev->phydev) 2204 return -ENODEV; 2205 2206 if (pause->tx_pause != pause->rx_pause) { 2207 netdev_info(ndev, 2208 "hardware only support enable/disable both tx and rx"); 2209 return -EINVAL; 2210 } 2211 2212 fep->pause_flag = 0; 2213 2214 /* tx pause must be same as rx pause */ 2215 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0; 2216 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0; 2217 2218 if (pause->rx_pause || pause->autoneg) { 2219 ndev->phydev->supported |= ADVERTISED_Pause; 2220 ndev->phydev->advertising |= ADVERTISED_Pause; 2221 } else { 2222 ndev->phydev->supported &= ~ADVERTISED_Pause; 2223 ndev->phydev->advertising &= ~ADVERTISED_Pause; 2224 } 2225 2226 if (pause->autoneg) { 2227 if (netif_running(ndev)) 2228 fec_stop(ndev); 2229 phy_start_aneg(ndev->phydev); 2230 } 2231 if (netif_running(ndev)) { 2232 napi_disable(&fep->napi); 2233 netif_tx_lock_bh(ndev); 2234 fec_restart(ndev); 2235 netif_wake_queue(ndev); 2236 netif_tx_unlock_bh(ndev); 2237 napi_enable(&fep->napi); 2238 } 2239 2240 return 0; 2241 } 2242 2243 static const struct fec_stat { 2244 char name[ETH_GSTRING_LEN]; 2245 u16 offset; 2246 } fec_stats[] = { 2247 /* RMON TX */ 2248 { "tx_dropped", RMON_T_DROP }, 2249 { "tx_packets", RMON_T_PACKETS }, 2250 { "tx_broadcast", RMON_T_BC_PKT }, 2251 { "tx_multicast", RMON_T_MC_PKT }, 2252 { "tx_crc_errors", RMON_T_CRC_ALIGN }, 2253 { "tx_undersize", RMON_T_UNDERSIZE }, 2254 { "tx_oversize", RMON_T_OVERSIZE }, 2255 { "tx_fragment", RMON_T_FRAG }, 2256 { "tx_jabber", RMON_T_JAB }, 2257 { "tx_collision", RMON_T_COL }, 2258 { "tx_64byte", RMON_T_P64 }, 2259 { "tx_65to127byte", RMON_T_P65TO127 }, 2260 { "tx_128to255byte", RMON_T_P128TO255 }, 2261 { "tx_256to511byte", RMON_T_P256TO511 }, 2262 { "tx_512to1023byte", RMON_T_P512TO1023 }, 2263 { "tx_1024to2047byte", RMON_T_P1024TO2047 }, 2264 { "tx_GTE2048byte", RMON_T_P_GTE2048 }, 2265 { "tx_octets", RMON_T_OCTETS }, 2266 2267 /* IEEE TX */ 2268 { "IEEE_tx_drop", IEEE_T_DROP }, 2269 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK }, 2270 { "IEEE_tx_1col", IEEE_T_1COL }, 2271 { "IEEE_tx_mcol", IEEE_T_MCOL }, 2272 { "IEEE_tx_def", IEEE_T_DEF }, 2273 { "IEEE_tx_lcol", IEEE_T_LCOL }, 2274 { "IEEE_tx_excol", IEEE_T_EXCOL }, 2275 { "IEEE_tx_macerr", IEEE_T_MACERR }, 2276 { "IEEE_tx_cserr", IEEE_T_CSERR }, 2277 { "IEEE_tx_sqe", IEEE_T_SQE }, 2278 { "IEEE_tx_fdxfc", IEEE_T_FDXFC }, 2279 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK }, 2280 2281 /* RMON RX */ 2282 { "rx_packets", RMON_R_PACKETS }, 2283 { "rx_broadcast", RMON_R_BC_PKT }, 2284 { "rx_multicast", RMON_R_MC_PKT }, 2285 { "rx_crc_errors", RMON_R_CRC_ALIGN }, 2286 { "rx_undersize", RMON_R_UNDERSIZE }, 2287 { "rx_oversize", RMON_R_OVERSIZE }, 2288 { "rx_fragment", RMON_R_FRAG }, 2289 { "rx_jabber", RMON_R_JAB }, 2290 { "rx_64byte", RMON_R_P64 }, 2291 { "rx_65to127byte", RMON_R_P65TO127 }, 2292 { "rx_128to255byte", RMON_R_P128TO255 }, 2293 { "rx_256to511byte", RMON_R_P256TO511 }, 2294 { "rx_512to1023byte", RMON_R_P512TO1023 }, 2295 { "rx_1024to2047byte", RMON_R_P1024TO2047 }, 2296 { "rx_GTE2048byte", RMON_R_P_GTE2048 }, 2297 { "rx_octets", RMON_R_OCTETS }, 2298 2299 /* IEEE RX */ 2300 { "IEEE_rx_drop", IEEE_R_DROP }, 2301 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK }, 2302 { "IEEE_rx_crc", IEEE_R_CRC }, 2303 { "IEEE_rx_align", IEEE_R_ALIGN }, 2304 { "IEEE_rx_macerr", IEEE_R_MACERR }, 2305 { "IEEE_rx_fdxfc", IEEE_R_FDXFC }, 2306 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK }, 2307 }; 2308 2309 static void fec_enet_get_ethtool_stats(struct net_device *dev, 2310 struct ethtool_stats *stats, u64 *data) 2311 { 2312 struct fec_enet_private *fep = netdev_priv(dev); 2313 int i; 2314 2315 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2316 data[i] = readl(fep->hwp + fec_stats[i].offset); 2317 } 2318 2319 static void fec_enet_get_strings(struct net_device *netdev, 2320 u32 stringset, u8 *data) 2321 { 2322 int i; 2323 switch (stringset) { 2324 case ETH_SS_STATS: 2325 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2326 memcpy(data + i * ETH_GSTRING_LEN, 2327 fec_stats[i].name, ETH_GSTRING_LEN); 2328 break; 2329 } 2330 } 2331 2332 static int fec_enet_get_sset_count(struct net_device *dev, int sset) 2333 { 2334 switch (sset) { 2335 case ETH_SS_STATS: 2336 return ARRAY_SIZE(fec_stats); 2337 default: 2338 return -EOPNOTSUPP; 2339 } 2340 } 2341 #endif /* !defined(CONFIG_M5272) */ 2342 2343 static int fec_enet_nway_reset(struct net_device *dev) 2344 { 2345 struct phy_device *phydev = dev->phydev; 2346 2347 if (!phydev) 2348 return -ENODEV; 2349 2350 return genphy_restart_aneg(phydev); 2351 } 2352 2353 /* ITR clock source is enet system clock (clk_ahb). 2354 * TCTT unit is cycle_ns * 64 cycle 2355 * So, the ICTT value = X us / (cycle_ns * 64) 2356 */ 2357 static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us) 2358 { 2359 struct fec_enet_private *fep = netdev_priv(ndev); 2360 2361 return us * (fep->itr_clk_rate / 64000) / 1000; 2362 } 2363 2364 /* Set threshold for interrupt coalescing */ 2365 static void fec_enet_itr_coal_set(struct net_device *ndev) 2366 { 2367 struct fec_enet_private *fep = netdev_priv(ndev); 2368 int rx_itr, tx_itr; 2369 2370 /* Must be greater than zero to avoid unpredictable behavior */ 2371 if (!fep->rx_time_itr || !fep->rx_pkts_itr || 2372 !fep->tx_time_itr || !fep->tx_pkts_itr) 2373 return; 2374 2375 /* Select enet system clock as Interrupt Coalescing 2376 * timer Clock Source 2377 */ 2378 rx_itr = FEC_ITR_CLK_SEL; 2379 tx_itr = FEC_ITR_CLK_SEL; 2380 2381 /* set ICFT and ICTT */ 2382 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr); 2383 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr)); 2384 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr); 2385 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr)); 2386 2387 rx_itr |= FEC_ITR_EN; 2388 tx_itr |= FEC_ITR_EN; 2389 2390 writel(tx_itr, fep->hwp + FEC_TXIC0); 2391 writel(rx_itr, fep->hwp + FEC_RXIC0); 2392 if (fep->quirks & FEC_QUIRK_HAS_AVB) { 2393 writel(tx_itr, fep->hwp + FEC_TXIC1); 2394 writel(rx_itr, fep->hwp + FEC_RXIC1); 2395 writel(tx_itr, fep->hwp + FEC_TXIC2); 2396 writel(rx_itr, fep->hwp + FEC_RXIC2); 2397 } 2398 } 2399 2400 static int 2401 fec_enet_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec) 2402 { 2403 struct fec_enet_private *fep = netdev_priv(ndev); 2404 2405 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) 2406 return -EOPNOTSUPP; 2407 2408 ec->rx_coalesce_usecs = fep->rx_time_itr; 2409 ec->rx_max_coalesced_frames = fep->rx_pkts_itr; 2410 2411 ec->tx_coalesce_usecs = fep->tx_time_itr; 2412 ec->tx_max_coalesced_frames = fep->tx_pkts_itr; 2413 2414 return 0; 2415 } 2416 2417 static int 2418 fec_enet_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec) 2419 { 2420 struct fec_enet_private *fep = netdev_priv(ndev); 2421 unsigned int cycle; 2422 2423 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) 2424 return -EOPNOTSUPP; 2425 2426 if (ec->rx_max_coalesced_frames > 255) { 2427 pr_err("Rx coalesced frames exceed hardware limitation\n"); 2428 return -EINVAL; 2429 } 2430 2431 if (ec->tx_max_coalesced_frames > 255) { 2432 pr_err("Tx coalesced frame exceed hardware limitation\n"); 2433 return -EINVAL; 2434 } 2435 2436 cycle = fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr); 2437 if (cycle > 0xFFFF) { 2438 pr_err("Rx coalesced usec exceed hardware limitation\n"); 2439 return -EINVAL; 2440 } 2441 2442 cycle = fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr); 2443 if (cycle > 0xFFFF) { 2444 pr_err("Rx coalesced usec exceed hardware limitation\n"); 2445 return -EINVAL; 2446 } 2447 2448 fep->rx_time_itr = ec->rx_coalesce_usecs; 2449 fep->rx_pkts_itr = ec->rx_max_coalesced_frames; 2450 2451 fep->tx_time_itr = ec->tx_coalesce_usecs; 2452 fep->tx_pkts_itr = ec->tx_max_coalesced_frames; 2453 2454 fec_enet_itr_coal_set(ndev); 2455 2456 return 0; 2457 } 2458 2459 static void fec_enet_itr_coal_init(struct net_device *ndev) 2460 { 2461 struct ethtool_coalesce ec; 2462 2463 ec.rx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT; 2464 ec.rx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT; 2465 2466 ec.tx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT; 2467 ec.tx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT; 2468 2469 fec_enet_set_coalesce(ndev, &ec); 2470 } 2471 2472 static int fec_enet_get_tunable(struct net_device *netdev, 2473 const struct ethtool_tunable *tuna, 2474 void *data) 2475 { 2476 struct fec_enet_private *fep = netdev_priv(netdev); 2477 int ret = 0; 2478 2479 switch (tuna->id) { 2480 case ETHTOOL_RX_COPYBREAK: 2481 *(u32 *)data = fep->rx_copybreak; 2482 break; 2483 default: 2484 ret = -EINVAL; 2485 break; 2486 } 2487 2488 return ret; 2489 } 2490 2491 static int fec_enet_set_tunable(struct net_device *netdev, 2492 const struct ethtool_tunable *tuna, 2493 const void *data) 2494 { 2495 struct fec_enet_private *fep = netdev_priv(netdev); 2496 int ret = 0; 2497 2498 switch (tuna->id) { 2499 case ETHTOOL_RX_COPYBREAK: 2500 fep->rx_copybreak = *(u32 *)data; 2501 break; 2502 default: 2503 ret = -EINVAL; 2504 break; 2505 } 2506 2507 return ret; 2508 } 2509 2510 static void 2511 fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2512 { 2513 struct fec_enet_private *fep = netdev_priv(ndev); 2514 2515 if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) { 2516 wol->supported = WAKE_MAGIC; 2517 wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0; 2518 } else { 2519 wol->supported = wol->wolopts = 0; 2520 } 2521 } 2522 2523 static int 2524 fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2525 { 2526 struct fec_enet_private *fep = netdev_priv(ndev); 2527 2528 if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET)) 2529 return -EINVAL; 2530 2531 if (wol->wolopts & ~WAKE_MAGIC) 2532 return -EINVAL; 2533 2534 device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC); 2535 if (device_may_wakeup(&ndev->dev)) { 2536 fep->wol_flag |= FEC_WOL_FLAG_ENABLE; 2537 if (fep->irq[0] > 0) 2538 enable_irq_wake(fep->irq[0]); 2539 } else { 2540 fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE); 2541 if (fep->irq[0] > 0) 2542 disable_irq_wake(fep->irq[0]); 2543 } 2544 2545 return 0; 2546 } 2547 2548 static const struct ethtool_ops fec_enet_ethtool_ops = { 2549 .get_drvinfo = fec_enet_get_drvinfo, 2550 .get_regs_len = fec_enet_get_regs_len, 2551 .get_regs = fec_enet_get_regs, 2552 .nway_reset = fec_enet_nway_reset, 2553 .get_link = ethtool_op_get_link, 2554 .get_coalesce = fec_enet_get_coalesce, 2555 .set_coalesce = fec_enet_set_coalesce, 2556 #ifndef CONFIG_M5272 2557 .get_pauseparam = fec_enet_get_pauseparam, 2558 .set_pauseparam = fec_enet_set_pauseparam, 2559 .get_strings = fec_enet_get_strings, 2560 .get_ethtool_stats = fec_enet_get_ethtool_stats, 2561 .get_sset_count = fec_enet_get_sset_count, 2562 #endif 2563 .get_ts_info = fec_enet_get_ts_info, 2564 .get_tunable = fec_enet_get_tunable, 2565 .set_tunable = fec_enet_set_tunable, 2566 .get_wol = fec_enet_get_wol, 2567 .set_wol = fec_enet_set_wol, 2568 .get_link_ksettings = phy_ethtool_get_link_ksettings, 2569 .set_link_ksettings = phy_ethtool_set_link_ksettings, 2570 }; 2571 2572 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) 2573 { 2574 struct fec_enet_private *fep = netdev_priv(ndev); 2575 struct phy_device *phydev = ndev->phydev; 2576 2577 if (!netif_running(ndev)) 2578 return -EINVAL; 2579 2580 if (!phydev) 2581 return -ENODEV; 2582 2583 if (fep->bufdesc_ex) { 2584 if (cmd == SIOCSHWTSTAMP) 2585 return fec_ptp_set(ndev, rq); 2586 if (cmd == SIOCGHWTSTAMP) 2587 return fec_ptp_get(ndev, rq); 2588 } 2589 2590 return phy_mii_ioctl(phydev, rq, cmd); 2591 } 2592 2593 static void fec_enet_free_buffers(struct net_device *ndev) 2594 { 2595 struct fec_enet_private *fep = netdev_priv(ndev); 2596 unsigned int i; 2597 struct sk_buff *skb; 2598 struct bufdesc *bdp; 2599 struct fec_enet_priv_tx_q *txq; 2600 struct fec_enet_priv_rx_q *rxq; 2601 unsigned int q; 2602 2603 for (q = 0; q < fep->num_rx_queues; q++) { 2604 rxq = fep->rx_queue[q]; 2605 bdp = rxq->bd.base; 2606 for (i = 0; i < rxq->bd.ring_size; i++) { 2607 skb = rxq->rx_skbuff[i]; 2608 rxq->rx_skbuff[i] = NULL; 2609 if (skb) { 2610 dma_unmap_single(&fep->pdev->dev, 2611 fec32_to_cpu(bdp->cbd_bufaddr), 2612 FEC_ENET_RX_FRSIZE - fep->rx_align, 2613 DMA_FROM_DEVICE); 2614 dev_kfree_skb(skb); 2615 } 2616 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 2617 } 2618 } 2619 2620 for (q = 0; q < fep->num_tx_queues; q++) { 2621 txq = fep->tx_queue[q]; 2622 bdp = txq->bd.base; 2623 for (i = 0; i < txq->bd.ring_size; i++) { 2624 kfree(txq->tx_bounce[i]); 2625 txq->tx_bounce[i] = NULL; 2626 skb = txq->tx_skbuff[i]; 2627 txq->tx_skbuff[i] = NULL; 2628 dev_kfree_skb(skb); 2629 } 2630 } 2631 } 2632 2633 static void fec_enet_free_queue(struct net_device *ndev) 2634 { 2635 struct fec_enet_private *fep = netdev_priv(ndev); 2636 int i; 2637 struct fec_enet_priv_tx_q *txq; 2638 2639 for (i = 0; i < fep->num_tx_queues; i++) 2640 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) { 2641 txq = fep->tx_queue[i]; 2642 dma_free_coherent(NULL, 2643 txq->bd.ring_size * TSO_HEADER_SIZE, 2644 txq->tso_hdrs, 2645 txq->tso_hdrs_dma); 2646 } 2647 2648 for (i = 0; i < fep->num_rx_queues; i++) 2649 kfree(fep->rx_queue[i]); 2650 for (i = 0; i < fep->num_tx_queues; i++) 2651 kfree(fep->tx_queue[i]); 2652 } 2653 2654 static int fec_enet_alloc_queue(struct net_device *ndev) 2655 { 2656 struct fec_enet_private *fep = netdev_priv(ndev); 2657 int i; 2658 int ret = 0; 2659 struct fec_enet_priv_tx_q *txq; 2660 2661 for (i = 0; i < fep->num_tx_queues; i++) { 2662 txq = kzalloc(sizeof(*txq), GFP_KERNEL); 2663 if (!txq) { 2664 ret = -ENOMEM; 2665 goto alloc_failed; 2666 } 2667 2668 fep->tx_queue[i] = txq; 2669 txq->bd.ring_size = TX_RING_SIZE; 2670 fep->total_tx_ring_size += fep->tx_queue[i]->bd.ring_size; 2671 2672 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS; 2673 txq->tx_wake_threshold = 2674 (txq->bd.ring_size - txq->tx_stop_threshold) / 2; 2675 2676 txq->tso_hdrs = dma_alloc_coherent(NULL, 2677 txq->bd.ring_size * TSO_HEADER_SIZE, 2678 &txq->tso_hdrs_dma, 2679 GFP_KERNEL); 2680 if (!txq->tso_hdrs) { 2681 ret = -ENOMEM; 2682 goto alloc_failed; 2683 } 2684 } 2685 2686 for (i = 0; i < fep->num_rx_queues; i++) { 2687 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]), 2688 GFP_KERNEL); 2689 if (!fep->rx_queue[i]) { 2690 ret = -ENOMEM; 2691 goto alloc_failed; 2692 } 2693 2694 fep->rx_queue[i]->bd.ring_size = RX_RING_SIZE; 2695 fep->total_rx_ring_size += fep->rx_queue[i]->bd.ring_size; 2696 } 2697 return ret; 2698 2699 alloc_failed: 2700 fec_enet_free_queue(ndev); 2701 return ret; 2702 } 2703 2704 static int 2705 fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue) 2706 { 2707 struct fec_enet_private *fep = netdev_priv(ndev); 2708 unsigned int i; 2709 struct sk_buff *skb; 2710 struct bufdesc *bdp; 2711 struct fec_enet_priv_rx_q *rxq; 2712 2713 rxq = fep->rx_queue[queue]; 2714 bdp = rxq->bd.base; 2715 for (i = 0; i < rxq->bd.ring_size; i++) { 2716 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE); 2717 if (!skb) 2718 goto err_alloc; 2719 2720 if (fec_enet_new_rxbdp(ndev, bdp, skb)) { 2721 dev_kfree_skb(skb); 2722 goto err_alloc; 2723 } 2724 2725 rxq->rx_skbuff[i] = skb; 2726 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); 2727 2728 if (fep->bufdesc_ex) { 2729 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 2730 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); 2731 } 2732 2733 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 2734 } 2735 2736 /* Set the last buffer to wrap. */ 2737 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); 2738 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 2739 return 0; 2740 2741 err_alloc: 2742 fec_enet_free_buffers(ndev); 2743 return -ENOMEM; 2744 } 2745 2746 static int 2747 fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue) 2748 { 2749 struct fec_enet_private *fep = netdev_priv(ndev); 2750 unsigned int i; 2751 struct bufdesc *bdp; 2752 struct fec_enet_priv_tx_q *txq; 2753 2754 txq = fep->tx_queue[queue]; 2755 bdp = txq->bd.base; 2756 for (i = 0; i < txq->bd.ring_size; i++) { 2757 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); 2758 if (!txq->tx_bounce[i]) 2759 goto err_alloc; 2760 2761 bdp->cbd_sc = cpu_to_fec16(0); 2762 bdp->cbd_bufaddr = cpu_to_fec32(0); 2763 2764 if (fep->bufdesc_ex) { 2765 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 2766 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_TX_INT); 2767 } 2768 2769 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 2770 } 2771 2772 /* Set the last buffer to wrap. */ 2773 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); 2774 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 2775 2776 return 0; 2777 2778 err_alloc: 2779 fec_enet_free_buffers(ndev); 2780 return -ENOMEM; 2781 } 2782 2783 static int fec_enet_alloc_buffers(struct net_device *ndev) 2784 { 2785 struct fec_enet_private *fep = netdev_priv(ndev); 2786 unsigned int i; 2787 2788 for (i = 0; i < fep->num_rx_queues; i++) 2789 if (fec_enet_alloc_rxq_buffers(ndev, i)) 2790 return -ENOMEM; 2791 2792 for (i = 0; i < fep->num_tx_queues; i++) 2793 if (fec_enet_alloc_txq_buffers(ndev, i)) 2794 return -ENOMEM; 2795 return 0; 2796 } 2797 2798 static int 2799 fec_enet_open(struct net_device *ndev) 2800 { 2801 struct fec_enet_private *fep = netdev_priv(ndev); 2802 int ret; 2803 2804 ret = pm_runtime_get_sync(&fep->pdev->dev); 2805 if (ret < 0) 2806 return ret; 2807 2808 pinctrl_pm_select_default_state(&fep->pdev->dev); 2809 ret = fec_enet_clk_enable(ndev, true); 2810 if (ret) 2811 goto clk_enable; 2812 2813 /* I should reset the ring buffers here, but I don't yet know 2814 * a simple way to do that. 2815 */ 2816 2817 ret = fec_enet_alloc_buffers(ndev); 2818 if (ret) 2819 goto err_enet_alloc; 2820 2821 /* Init MAC prior to mii bus probe */ 2822 fec_restart(ndev); 2823 2824 /* Probe and connect to PHY when open the interface */ 2825 ret = fec_enet_mii_probe(ndev); 2826 if (ret) 2827 goto err_enet_mii_probe; 2828 2829 if (fep->quirks & FEC_QUIRK_ERR006687) 2830 imx6q_cpuidle_fec_irqs_used(); 2831 2832 napi_enable(&fep->napi); 2833 phy_start(ndev->phydev); 2834 netif_tx_start_all_queues(ndev); 2835 2836 device_set_wakeup_enable(&ndev->dev, fep->wol_flag & 2837 FEC_WOL_FLAG_ENABLE); 2838 2839 return 0; 2840 2841 err_enet_mii_probe: 2842 fec_enet_free_buffers(ndev); 2843 err_enet_alloc: 2844 fec_enet_clk_enable(ndev, false); 2845 clk_enable: 2846 pm_runtime_mark_last_busy(&fep->pdev->dev); 2847 pm_runtime_put_autosuspend(&fep->pdev->dev); 2848 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 2849 return ret; 2850 } 2851 2852 static int 2853 fec_enet_close(struct net_device *ndev) 2854 { 2855 struct fec_enet_private *fep = netdev_priv(ndev); 2856 2857 phy_stop(ndev->phydev); 2858 2859 if (netif_device_present(ndev)) { 2860 napi_disable(&fep->napi); 2861 netif_tx_disable(ndev); 2862 fec_stop(ndev); 2863 } 2864 2865 phy_disconnect(ndev->phydev); 2866 2867 if (fep->quirks & FEC_QUIRK_ERR006687) 2868 imx6q_cpuidle_fec_irqs_unused(); 2869 2870 fec_enet_clk_enable(ndev, false); 2871 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 2872 pm_runtime_mark_last_busy(&fep->pdev->dev); 2873 pm_runtime_put_autosuspend(&fep->pdev->dev); 2874 2875 fec_enet_free_buffers(ndev); 2876 2877 return 0; 2878 } 2879 2880 /* Set or clear the multicast filter for this adaptor. 2881 * Skeleton taken from sunlance driver. 2882 * The CPM Ethernet implementation allows Multicast as well as individual 2883 * MAC address filtering. Some of the drivers check to make sure it is 2884 * a group multicast address, and discard those that are not. I guess I 2885 * will do the same for now, but just remove the test if you want 2886 * individual filtering as well (do the upper net layers want or support 2887 * this kind of feature?). 2888 */ 2889 2890 #define HASH_BITS 6 /* #bits in hash */ 2891 #define CRC32_POLY 0xEDB88320 2892 2893 static void set_multicast_list(struct net_device *ndev) 2894 { 2895 struct fec_enet_private *fep = netdev_priv(ndev); 2896 struct netdev_hw_addr *ha; 2897 unsigned int i, bit, data, crc, tmp; 2898 unsigned char hash; 2899 2900 if (ndev->flags & IFF_PROMISC) { 2901 tmp = readl(fep->hwp + FEC_R_CNTRL); 2902 tmp |= 0x8; 2903 writel(tmp, fep->hwp + FEC_R_CNTRL); 2904 return; 2905 } 2906 2907 tmp = readl(fep->hwp + FEC_R_CNTRL); 2908 tmp &= ~0x8; 2909 writel(tmp, fep->hwp + FEC_R_CNTRL); 2910 2911 if (ndev->flags & IFF_ALLMULTI) { 2912 /* Catch all multicast addresses, so set the 2913 * filter to all 1's 2914 */ 2915 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 2916 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 2917 2918 return; 2919 } 2920 2921 /* Clear filter and add the addresses in hash register 2922 */ 2923 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 2924 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 2925 2926 netdev_for_each_mc_addr(ha, ndev) { 2927 /* calculate crc32 value of mac address */ 2928 crc = 0xffffffff; 2929 2930 for (i = 0; i < ndev->addr_len; i++) { 2931 data = ha->addr[i]; 2932 for (bit = 0; bit < 8; bit++, data >>= 1) { 2933 crc = (crc >> 1) ^ 2934 (((crc ^ data) & 1) ? CRC32_POLY : 0); 2935 } 2936 } 2937 2938 /* only upper 6 bits (HASH_BITS) are used 2939 * which point to specific bit in he hash registers 2940 */ 2941 hash = (crc >> (32 - HASH_BITS)) & 0x3f; 2942 2943 if (hash > 31) { 2944 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 2945 tmp |= 1 << (hash - 32); 2946 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 2947 } else { 2948 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW); 2949 tmp |= 1 << hash; 2950 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 2951 } 2952 } 2953 } 2954 2955 /* Set a MAC change in hardware. */ 2956 static int 2957 fec_set_mac_address(struct net_device *ndev, void *p) 2958 { 2959 struct fec_enet_private *fep = netdev_priv(ndev); 2960 struct sockaddr *addr = p; 2961 2962 if (addr) { 2963 if (!is_valid_ether_addr(addr->sa_data)) 2964 return -EADDRNOTAVAIL; 2965 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len); 2966 } 2967 2968 /* Add netif status check here to avoid system hang in below case: 2969 * ifconfig ethx down; ifconfig ethx hw ether xx:xx:xx:xx:xx:xx; 2970 * After ethx down, fec all clocks are gated off and then register 2971 * access causes system hang. 2972 */ 2973 if (!netif_running(ndev)) 2974 return 0; 2975 2976 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) | 2977 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24), 2978 fep->hwp + FEC_ADDR_LOW); 2979 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24), 2980 fep->hwp + FEC_ADDR_HIGH); 2981 return 0; 2982 } 2983 2984 #ifdef CONFIG_NET_POLL_CONTROLLER 2985 /** 2986 * fec_poll_controller - FEC Poll controller function 2987 * @dev: The FEC network adapter 2988 * 2989 * Polled functionality used by netconsole and others in non interrupt mode 2990 * 2991 */ 2992 static void fec_poll_controller(struct net_device *dev) 2993 { 2994 int i; 2995 struct fec_enet_private *fep = netdev_priv(dev); 2996 2997 for (i = 0; i < FEC_IRQ_NUM; i++) { 2998 if (fep->irq[i] > 0) { 2999 disable_irq(fep->irq[i]); 3000 fec_enet_interrupt(fep->irq[i], dev); 3001 enable_irq(fep->irq[i]); 3002 } 3003 } 3004 } 3005 #endif 3006 3007 static inline void fec_enet_set_netdev_features(struct net_device *netdev, 3008 netdev_features_t features) 3009 { 3010 struct fec_enet_private *fep = netdev_priv(netdev); 3011 netdev_features_t changed = features ^ netdev->features; 3012 3013 netdev->features = features; 3014 3015 /* Receive checksum has been changed */ 3016 if (changed & NETIF_F_RXCSUM) { 3017 if (features & NETIF_F_RXCSUM) 3018 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 3019 else 3020 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED; 3021 } 3022 } 3023 3024 static int fec_set_features(struct net_device *netdev, 3025 netdev_features_t features) 3026 { 3027 struct fec_enet_private *fep = netdev_priv(netdev); 3028 netdev_features_t changed = features ^ netdev->features; 3029 3030 if (netif_running(netdev) && changed & NETIF_F_RXCSUM) { 3031 napi_disable(&fep->napi); 3032 netif_tx_lock_bh(netdev); 3033 fec_stop(netdev); 3034 fec_enet_set_netdev_features(netdev, features); 3035 fec_restart(netdev); 3036 netif_tx_wake_all_queues(netdev); 3037 netif_tx_unlock_bh(netdev); 3038 napi_enable(&fep->napi); 3039 } else { 3040 fec_enet_set_netdev_features(netdev, features); 3041 } 3042 3043 return 0; 3044 } 3045 3046 static const struct net_device_ops fec_netdev_ops = { 3047 .ndo_open = fec_enet_open, 3048 .ndo_stop = fec_enet_close, 3049 .ndo_start_xmit = fec_enet_start_xmit, 3050 .ndo_set_rx_mode = set_multicast_list, 3051 .ndo_change_mtu = eth_change_mtu, 3052 .ndo_validate_addr = eth_validate_addr, 3053 .ndo_tx_timeout = fec_timeout, 3054 .ndo_set_mac_address = fec_set_mac_address, 3055 .ndo_do_ioctl = fec_enet_ioctl, 3056 #ifdef CONFIG_NET_POLL_CONTROLLER 3057 .ndo_poll_controller = fec_poll_controller, 3058 #endif 3059 .ndo_set_features = fec_set_features, 3060 }; 3061 3062 static const unsigned short offset_des_active_rxq[] = { 3063 FEC_R_DES_ACTIVE_0, FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2 3064 }; 3065 3066 static const unsigned short offset_des_active_txq[] = { 3067 FEC_X_DES_ACTIVE_0, FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2 3068 }; 3069 3070 /* 3071 * XXX: We need to clean up on failure exits here. 3072 * 3073 */ 3074 static int fec_enet_init(struct net_device *ndev) 3075 { 3076 struct fec_enet_private *fep = netdev_priv(ndev); 3077 struct bufdesc *cbd_base; 3078 dma_addr_t bd_dma; 3079 int bd_size; 3080 unsigned int i; 3081 unsigned dsize = fep->bufdesc_ex ? sizeof(struct bufdesc_ex) : 3082 sizeof(struct bufdesc); 3083 unsigned dsize_log2 = __fls(dsize); 3084 3085 WARN_ON(dsize != (1 << dsize_log2)); 3086 #if defined(CONFIG_ARM) 3087 fep->rx_align = 0xf; 3088 fep->tx_align = 0xf; 3089 #else 3090 fep->rx_align = 0x3; 3091 fep->tx_align = 0x3; 3092 #endif 3093 3094 fec_enet_alloc_queue(ndev); 3095 3096 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) * dsize; 3097 3098 /* Allocate memory for buffer descriptors. */ 3099 cbd_base = dmam_alloc_coherent(&fep->pdev->dev, bd_size, &bd_dma, 3100 GFP_KERNEL); 3101 if (!cbd_base) { 3102 return -ENOMEM; 3103 } 3104 3105 memset(cbd_base, 0, bd_size); 3106 3107 /* Get the Ethernet address */ 3108 fec_get_mac(ndev); 3109 /* make sure MAC we just acquired is programmed into the hw */ 3110 fec_set_mac_address(ndev, NULL); 3111 3112 /* Set receive and transmit descriptor base. */ 3113 for (i = 0; i < fep->num_rx_queues; i++) { 3114 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[i]; 3115 unsigned size = dsize * rxq->bd.ring_size; 3116 3117 rxq->bd.qid = i; 3118 rxq->bd.base = cbd_base; 3119 rxq->bd.cur = cbd_base; 3120 rxq->bd.dma = bd_dma; 3121 rxq->bd.dsize = dsize; 3122 rxq->bd.dsize_log2 = dsize_log2; 3123 rxq->bd.reg_desc_active = fep->hwp + offset_des_active_rxq[i]; 3124 bd_dma += size; 3125 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size); 3126 rxq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); 3127 } 3128 3129 for (i = 0; i < fep->num_tx_queues; i++) { 3130 struct fec_enet_priv_tx_q *txq = fep->tx_queue[i]; 3131 unsigned size = dsize * txq->bd.ring_size; 3132 3133 txq->bd.qid = i; 3134 txq->bd.base = cbd_base; 3135 txq->bd.cur = cbd_base; 3136 txq->bd.dma = bd_dma; 3137 txq->bd.dsize = dsize; 3138 txq->bd.dsize_log2 = dsize_log2; 3139 txq->bd.reg_desc_active = fep->hwp + offset_des_active_txq[i]; 3140 bd_dma += size; 3141 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size); 3142 txq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); 3143 } 3144 3145 3146 /* The FEC Ethernet specific entries in the device structure */ 3147 ndev->watchdog_timeo = TX_TIMEOUT; 3148 ndev->netdev_ops = &fec_netdev_ops; 3149 ndev->ethtool_ops = &fec_enet_ethtool_ops; 3150 3151 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK); 3152 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT); 3153 3154 if (fep->quirks & FEC_QUIRK_HAS_VLAN) 3155 /* enable hw VLAN support */ 3156 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; 3157 3158 if (fep->quirks & FEC_QUIRK_HAS_CSUM) { 3159 ndev->gso_max_segs = FEC_MAX_TSO_SEGS; 3160 3161 /* enable hw accelerator */ 3162 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM 3163 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO); 3164 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 3165 } 3166 3167 if (fep->quirks & FEC_QUIRK_HAS_AVB) { 3168 fep->tx_align = 0; 3169 fep->rx_align = 0x3f; 3170 } 3171 3172 ndev->hw_features = ndev->features; 3173 3174 fec_restart(ndev); 3175 3176 return 0; 3177 } 3178 3179 #ifdef CONFIG_OF 3180 static void fec_reset_phy(struct platform_device *pdev) 3181 { 3182 int err, phy_reset; 3183 bool active_high = false; 3184 int msec = 1; 3185 struct device_node *np = pdev->dev.of_node; 3186 3187 if (!np) 3188 return; 3189 3190 of_property_read_u32(np, "phy-reset-duration", &msec); 3191 /* A sane reset duration should not be longer than 1s */ 3192 if (msec > 1000) 3193 msec = 1; 3194 3195 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0); 3196 if (!gpio_is_valid(phy_reset)) 3197 return; 3198 3199 active_high = of_property_read_bool(np, "phy-reset-active-high"); 3200 3201 err = devm_gpio_request_one(&pdev->dev, phy_reset, 3202 active_high ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW, 3203 "phy-reset"); 3204 if (err) { 3205 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err); 3206 return; 3207 } 3208 3209 if (msec > 20) 3210 msleep(msec); 3211 else 3212 usleep_range(msec * 1000, msec * 1000 + 1000); 3213 3214 gpio_set_value_cansleep(phy_reset, !active_high); 3215 } 3216 #else /* CONFIG_OF */ 3217 static void fec_reset_phy(struct platform_device *pdev) 3218 { 3219 /* 3220 * In case of platform probe, the reset has been done 3221 * by machine code. 3222 */ 3223 } 3224 #endif /* CONFIG_OF */ 3225 3226 static void 3227 fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx) 3228 { 3229 struct device_node *np = pdev->dev.of_node; 3230 3231 *num_tx = *num_rx = 1; 3232 3233 if (!np || !of_device_is_available(np)) 3234 return; 3235 3236 /* parse the num of tx and rx queues */ 3237 of_property_read_u32(np, "fsl,num-tx-queues", num_tx); 3238 3239 of_property_read_u32(np, "fsl,num-rx-queues", num_rx); 3240 3241 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) { 3242 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n", 3243 *num_tx); 3244 *num_tx = 1; 3245 return; 3246 } 3247 3248 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) { 3249 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n", 3250 *num_rx); 3251 *num_rx = 1; 3252 return; 3253 } 3254 3255 } 3256 3257 static int 3258 fec_probe(struct platform_device *pdev) 3259 { 3260 struct fec_enet_private *fep; 3261 struct fec_platform_data *pdata; 3262 struct net_device *ndev; 3263 int i, irq, ret = 0; 3264 struct resource *r; 3265 const struct of_device_id *of_id; 3266 static int dev_id; 3267 struct device_node *np = pdev->dev.of_node, *phy_node; 3268 int num_tx_qs; 3269 int num_rx_qs; 3270 3271 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs); 3272 3273 /* Init network device */ 3274 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private), 3275 num_tx_qs, num_rx_qs); 3276 if (!ndev) 3277 return -ENOMEM; 3278 3279 SET_NETDEV_DEV(ndev, &pdev->dev); 3280 3281 /* setup board info structure */ 3282 fep = netdev_priv(ndev); 3283 3284 of_id = of_match_device(fec_dt_ids, &pdev->dev); 3285 if (of_id) 3286 pdev->id_entry = of_id->data; 3287 fep->quirks = pdev->id_entry->driver_data; 3288 3289 fep->netdev = ndev; 3290 fep->num_rx_queues = num_rx_qs; 3291 fep->num_tx_queues = num_tx_qs; 3292 3293 #if !defined(CONFIG_M5272) 3294 /* default enable pause frame auto negotiation */ 3295 if (fep->quirks & FEC_QUIRK_HAS_GBIT) 3296 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG; 3297 #endif 3298 3299 /* Select default pin state */ 3300 pinctrl_pm_select_default_state(&pdev->dev); 3301 3302 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3303 fep->hwp = devm_ioremap_resource(&pdev->dev, r); 3304 if (IS_ERR(fep->hwp)) { 3305 ret = PTR_ERR(fep->hwp); 3306 goto failed_ioremap; 3307 } 3308 3309 fep->pdev = pdev; 3310 fep->dev_id = dev_id++; 3311 3312 platform_set_drvdata(pdev, ndev); 3313 3314 if ((of_machine_is_compatible("fsl,imx6q") || 3315 of_machine_is_compatible("fsl,imx6dl")) && 3316 !of_property_read_bool(np, "fsl,err006687-workaround-present")) 3317 fep->quirks |= FEC_QUIRK_ERR006687; 3318 3319 if (of_get_property(np, "fsl,magic-packet", NULL)) 3320 fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET; 3321 3322 phy_node = of_parse_phandle(np, "phy-handle", 0); 3323 if (!phy_node && of_phy_is_fixed_link(np)) { 3324 ret = of_phy_register_fixed_link(np); 3325 if (ret < 0) { 3326 dev_err(&pdev->dev, 3327 "broken fixed-link specification\n"); 3328 goto failed_phy; 3329 } 3330 phy_node = of_node_get(np); 3331 } 3332 fep->phy_node = phy_node; 3333 3334 ret = of_get_phy_mode(pdev->dev.of_node); 3335 if (ret < 0) { 3336 pdata = dev_get_platdata(&pdev->dev); 3337 if (pdata) 3338 fep->phy_interface = pdata->phy; 3339 else 3340 fep->phy_interface = PHY_INTERFACE_MODE_MII; 3341 } else { 3342 fep->phy_interface = ret; 3343 } 3344 3345 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 3346 if (IS_ERR(fep->clk_ipg)) { 3347 ret = PTR_ERR(fep->clk_ipg); 3348 goto failed_clk; 3349 } 3350 3351 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 3352 if (IS_ERR(fep->clk_ahb)) { 3353 ret = PTR_ERR(fep->clk_ahb); 3354 goto failed_clk; 3355 } 3356 3357 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb); 3358 3359 /* enet_out is optional, depends on board */ 3360 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out"); 3361 if (IS_ERR(fep->clk_enet_out)) 3362 fep->clk_enet_out = NULL; 3363 3364 fep->ptp_clk_on = false; 3365 mutex_init(&fep->ptp_clk_mutex); 3366 3367 /* clk_ref is optional, depends on board */ 3368 fep->clk_ref = devm_clk_get(&pdev->dev, "enet_clk_ref"); 3369 if (IS_ERR(fep->clk_ref)) 3370 fep->clk_ref = NULL; 3371 3372 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX; 3373 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp"); 3374 if (IS_ERR(fep->clk_ptp)) { 3375 fep->clk_ptp = NULL; 3376 fep->bufdesc_ex = false; 3377 } 3378 3379 ret = fec_enet_clk_enable(ndev, true); 3380 if (ret) 3381 goto failed_clk; 3382 3383 ret = clk_prepare_enable(fep->clk_ipg); 3384 if (ret) 3385 goto failed_clk_ipg; 3386 3387 fep->reg_phy = devm_regulator_get(&pdev->dev, "phy"); 3388 if (!IS_ERR(fep->reg_phy)) { 3389 ret = regulator_enable(fep->reg_phy); 3390 if (ret) { 3391 dev_err(&pdev->dev, 3392 "Failed to enable phy regulator: %d\n", ret); 3393 goto failed_regulator; 3394 } 3395 } else { 3396 fep->reg_phy = NULL; 3397 } 3398 3399 pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT); 3400 pm_runtime_use_autosuspend(&pdev->dev); 3401 pm_runtime_get_noresume(&pdev->dev); 3402 pm_runtime_set_active(&pdev->dev); 3403 pm_runtime_enable(&pdev->dev); 3404 3405 fec_reset_phy(pdev); 3406 3407 if (fep->bufdesc_ex) 3408 fec_ptp_init(pdev); 3409 3410 ret = fec_enet_init(ndev); 3411 if (ret) 3412 goto failed_init; 3413 3414 for (i = 0; i < FEC_IRQ_NUM; i++) { 3415 irq = platform_get_irq(pdev, i); 3416 if (irq < 0) { 3417 if (i) 3418 break; 3419 ret = irq; 3420 goto failed_irq; 3421 } 3422 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt, 3423 0, pdev->name, ndev); 3424 if (ret) 3425 goto failed_irq; 3426 3427 fep->irq[i] = irq; 3428 } 3429 3430 init_completion(&fep->mdio_done); 3431 ret = fec_enet_mii_init(pdev); 3432 if (ret) 3433 goto failed_mii_init; 3434 3435 /* Carrier starts down, phylib will bring it up */ 3436 netif_carrier_off(ndev); 3437 fec_enet_clk_enable(ndev, false); 3438 pinctrl_pm_select_sleep_state(&pdev->dev); 3439 3440 ret = register_netdev(ndev); 3441 if (ret) 3442 goto failed_register; 3443 3444 device_init_wakeup(&ndev->dev, fep->wol_flag & 3445 FEC_WOL_HAS_MAGIC_PACKET); 3446 3447 if (fep->bufdesc_ex && fep->ptp_clock) 3448 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id); 3449 3450 fep->rx_copybreak = COPYBREAK_DEFAULT; 3451 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work); 3452 3453 pm_runtime_mark_last_busy(&pdev->dev); 3454 pm_runtime_put_autosuspend(&pdev->dev); 3455 3456 return 0; 3457 3458 failed_register: 3459 fec_enet_mii_remove(fep); 3460 failed_mii_init: 3461 failed_irq: 3462 failed_init: 3463 fec_ptp_stop(pdev); 3464 if (fep->reg_phy) 3465 regulator_disable(fep->reg_phy); 3466 failed_regulator: 3467 clk_disable_unprepare(fep->clk_ipg); 3468 failed_clk_ipg: 3469 fec_enet_clk_enable(ndev, false); 3470 failed_clk: 3471 failed_phy: 3472 of_node_put(phy_node); 3473 failed_ioremap: 3474 free_netdev(ndev); 3475 3476 return ret; 3477 } 3478 3479 static int 3480 fec_drv_remove(struct platform_device *pdev) 3481 { 3482 struct net_device *ndev = platform_get_drvdata(pdev); 3483 struct fec_enet_private *fep = netdev_priv(ndev); 3484 3485 cancel_work_sync(&fep->tx_timeout_work); 3486 fec_ptp_stop(pdev); 3487 unregister_netdev(ndev); 3488 fec_enet_mii_remove(fep); 3489 if (fep->reg_phy) 3490 regulator_disable(fep->reg_phy); 3491 of_node_put(fep->phy_node); 3492 free_netdev(ndev); 3493 3494 return 0; 3495 } 3496 3497 static int __maybe_unused fec_suspend(struct device *dev) 3498 { 3499 struct net_device *ndev = dev_get_drvdata(dev); 3500 struct fec_enet_private *fep = netdev_priv(ndev); 3501 3502 rtnl_lock(); 3503 if (netif_running(ndev)) { 3504 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) 3505 fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON; 3506 phy_stop(ndev->phydev); 3507 napi_disable(&fep->napi); 3508 netif_tx_lock_bh(ndev); 3509 netif_device_detach(ndev); 3510 netif_tx_unlock_bh(ndev); 3511 fec_stop(ndev); 3512 fec_enet_clk_enable(ndev, false); 3513 if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) 3514 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3515 } 3516 rtnl_unlock(); 3517 3518 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) 3519 regulator_disable(fep->reg_phy); 3520 3521 /* SOC supply clock to phy, when clock is disabled, phy link down 3522 * SOC control phy regulator, when regulator is disabled, phy link down 3523 */ 3524 if (fep->clk_enet_out || fep->reg_phy) 3525 fep->link = 0; 3526 3527 return 0; 3528 } 3529 3530 static int __maybe_unused fec_resume(struct device *dev) 3531 { 3532 struct net_device *ndev = dev_get_drvdata(dev); 3533 struct fec_enet_private *fep = netdev_priv(ndev); 3534 struct fec_platform_data *pdata = fep->pdev->dev.platform_data; 3535 int ret; 3536 int val; 3537 3538 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) { 3539 ret = regulator_enable(fep->reg_phy); 3540 if (ret) 3541 return ret; 3542 } 3543 3544 rtnl_lock(); 3545 if (netif_running(ndev)) { 3546 ret = fec_enet_clk_enable(ndev, true); 3547 if (ret) { 3548 rtnl_unlock(); 3549 goto failed_clk; 3550 } 3551 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) { 3552 if (pdata && pdata->sleep_mode_enable) 3553 pdata->sleep_mode_enable(false); 3554 val = readl(fep->hwp + FEC_ECNTRL); 3555 val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP); 3556 writel(val, fep->hwp + FEC_ECNTRL); 3557 fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON; 3558 } else { 3559 pinctrl_pm_select_default_state(&fep->pdev->dev); 3560 } 3561 fec_restart(ndev); 3562 netif_tx_lock_bh(ndev); 3563 netif_device_attach(ndev); 3564 netif_tx_unlock_bh(ndev); 3565 napi_enable(&fep->napi); 3566 phy_start(ndev->phydev); 3567 } 3568 rtnl_unlock(); 3569 3570 return 0; 3571 3572 failed_clk: 3573 if (fep->reg_phy) 3574 regulator_disable(fep->reg_phy); 3575 return ret; 3576 } 3577 3578 static int __maybe_unused fec_runtime_suspend(struct device *dev) 3579 { 3580 struct net_device *ndev = dev_get_drvdata(dev); 3581 struct fec_enet_private *fep = netdev_priv(ndev); 3582 3583 clk_disable_unprepare(fep->clk_ipg); 3584 3585 return 0; 3586 } 3587 3588 static int __maybe_unused fec_runtime_resume(struct device *dev) 3589 { 3590 struct net_device *ndev = dev_get_drvdata(dev); 3591 struct fec_enet_private *fep = netdev_priv(ndev); 3592 3593 return clk_prepare_enable(fep->clk_ipg); 3594 } 3595 3596 static const struct dev_pm_ops fec_pm_ops = { 3597 SET_SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume) 3598 SET_RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL) 3599 }; 3600 3601 static struct platform_driver fec_driver = { 3602 .driver = { 3603 .name = DRIVER_NAME, 3604 .pm = &fec_pm_ops, 3605 .of_match_table = fec_dt_ids, 3606 }, 3607 .id_table = fec_devtype, 3608 .probe = fec_probe, 3609 .remove = fec_drv_remove, 3610 }; 3611 3612 module_platform_driver(fec_driver); 3613 3614 MODULE_ALIAS("platform:"DRIVER_NAME); 3615 MODULE_LICENSE("GPL"); 3616