1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. 4 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) 5 * 6 * Right now, I am very wasteful with the buffers. I allocate memory 7 * pages and then divide them into 2K frame buffers. This way I know I 8 * have buffers large enough to hold one frame within one buffer descriptor. 9 * Once I get this working, I will use 64 or 128 byte CPM buffers, which 10 * will be much more memory efficient and will easily handle lots of 11 * small packets. 12 * 13 * Much better multiple PHY support by Magnus Damm. 14 * Copyright (c) 2000 Ericsson Radio Systems AB. 15 * 16 * Support for FEC controller of ColdFire processors. 17 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) 18 * 19 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) 20 * Copyright (c) 2004-2006 Macq Electronique SA. 21 * 22 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. 23 */ 24 25 #include <linux/module.h> 26 #include <linux/kernel.h> 27 #include <linux/string.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/ptrace.h> 30 #include <linux/errno.h> 31 #include <linux/ioport.h> 32 #include <linux/slab.h> 33 #include <linux/interrupt.h> 34 #include <linux/delay.h> 35 #include <linux/netdevice.h> 36 #include <linux/etherdevice.h> 37 #include <linux/skbuff.h> 38 #include <linux/in.h> 39 #include <linux/ip.h> 40 #include <net/ip.h> 41 #include <net/selftests.h> 42 #include <net/tso.h> 43 #include <linux/tcp.h> 44 #include <linux/udp.h> 45 #include <linux/icmp.h> 46 #include <linux/spinlock.h> 47 #include <linux/workqueue.h> 48 #include <linux/bitops.h> 49 #include <linux/io.h> 50 #include <linux/irq.h> 51 #include <linux/clk.h> 52 #include <linux/crc32.h> 53 #include <linux/platform_device.h> 54 #include <linux/mdio.h> 55 #include <linux/phy.h> 56 #include <linux/fec.h> 57 #include <linux/of.h> 58 #include <linux/of_device.h> 59 #include <linux/of_gpio.h> 60 #include <linux/of_mdio.h> 61 #include <linux/of_net.h> 62 #include <linux/regulator/consumer.h> 63 #include <linux/if_vlan.h> 64 #include <linux/pinctrl/consumer.h> 65 #include <linux/prefetch.h> 66 #include <linux/mfd/syscon.h> 67 #include <linux/regmap.h> 68 #include <soc/imx/cpuidle.h> 69 70 #include <asm/cacheflush.h> 71 72 #include "fec.h" 73 74 static void set_multicast_list(struct net_device *ndev); 75 static void fec_enet_itr_coal_init(struct net_device *ndev); 76 77 #define DRIVER_NAME "fec" 78 79 static const u16 fec_enet_vlan_pri_to_queue[8] = {0, 0, 1, 1, 1, 2, 2, 2}; 80 81 /* Pause frame feild and FIFO threshold */ 82 #define FEC_ENET_FCE (1 << 5) 83 #define FEC_ENET_RSEM_V 0x84 84 #define FEC_ENET_RSFL_V 16 85 #define FEC_ENET_RAEM_V 0x8 86 #define FEC_ENET_RAFL_V 0x8 87 #define FEC_ENET_OPD_V 0xFFF0 88 #define FEC_MDIO_PM_TIMEOUT 100 /* ms */ 89 90 struct fec_devinfo { 91 u32 quirks; 92 }; 93 94 static const struct fec_devinfo fec_imx25_info = { 95 .quirks = FEC_QUIRK_USE_GASKET | FEC_QUIRK_MIB_CLEAR | 96 FEC_QUIRK_HAS_FRREG, 97 }; 98 99 static const struct fec_devinfo fec_imx27_info = { 100 .quirks = FEC_QUIRK_MIB_CLEAR | FEC_QUIRK_HAS_FRREG, 101 }; 102 103 static const struct fec_devinfo fec_imx28_info = { 104 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME | 105 FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC | 106 FEC_QUIRK_HAS_FRREG | FEC_QUIRK_CLEAR_SETUP_MII | 107 FEC_QUIRK_NO_HARD_RESET, 108 }; 109 110 static const struct fec_devinfo fec_imx6q_info = { 111 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 112 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 113 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 | 114 FEC_QUIRK_HAS_RACC | FEC_QUIRK_CLEAR_SETUP_MII, 115 }; 116 117 static const struct fec_devinfo fec_mvf600_info = { 118 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC, 119 }; 120 121 static const struct fec_devinfo fec_imx6x_info = { 122 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 123 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 124 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 125 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 126 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE | 127 FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES, 128 }; 129 130 static const struct fec_devinfo fec_imx6ul_info = { 131 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 132 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 133 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR007885 | 134 FEC_QUIRK_BUG_CAPTURE | FEC_QUIRK_HAS_RACC | 135 FEC_QUIRK_HAS_COALESCE | FEC_QUIRK_CLEAR_SETUP_MII, 136 }; 137 138 static const struct fec_devinfo fec_imx8mq_info = { 139 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 140 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 141 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 142 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 143 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE | 144 FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES | 145 FEC_QUIRK_HAS_EEE | FEC_QUIRK_WAKEUP_FROM_INT2, 146 }; 147 148 static const struct fec_devinfo fec_imx8qm_info = { 149 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 150 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 151 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 152 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 153 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE | 154 FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES | 155 FEC_QUIRK_DELAYED_CLKS_SUPPORT, 156 }; 157 158 static struct platform_device_id fec_devtype[] = { 159 { 160 /* keep it for coldfire */ 161 .name = DRIVER_NAME, 162 .driver_data = 0, 163 }, { 164 .name = "imx25-fec", 165 .driver_data = (kernel_ulong_t)&fec_imx25_info, 166 }, { 167 .name = "imx27-fec", 168 .driver_data = (kernel_ulong_t)&fec_imx27_info, 169 }, { 170 .name = "imx28-fec", 171 .driver_data = (kernel_ulong_t)&fec_imx28_info, 172 }, { 173 .name = "imx6q-fec", 174 .driver_data = (kernel_ulong_t)&fec_imx6q_info, 175 }, { 176 .name = "mvf600-fec", 177 .driver_data = (kernel_ulong_t)&fec_mvf600_info, 178 }, { 179 .name = "imx6sx-fec", 180 .driver_data = (kernel_ulong_t)&fec_imx6x_info, 181 }, { 182 .name = "imx6ul-fec", 183 .driver_data = (kernel_ulong_t)&fec_imx6ul_info, 184 }, { 185 .name = "imx8mq-fec", 186 .driver_data = (kernel_ulong_t)&fec_imx8mq_info, 187 }, { 188 .name = "imx8qm-fec", 189 .driver_data = (kernel_ulong_t)&fec_imx8qm_info, 190 }, { 191 /* sentinel */ 192 } 193 }; 194 MODULE_DEVICE_TABLE(platform, fec_devtype); 195 196 enum imx_fec_type { 197 IMX25_FEC = 1, /* runs on i.mx25/50/53 */ 198 IMX27_FEC, /* runs on i.mx27/35/51 */ 199 IMX28_FEC, 200 IMX6Q_FEC, 201 MVF600_FEC, 202 IMX6SX_FEC, 203 IMX6UL_FEC, 204 IMX8MQ_FEC, 205 IMX8QM_FEC, 206 }; 207 208 static const struct of_device_id fec_dt_ids[] = { 209 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], }, 210 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], }, 211 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], }, 212 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], }, 213 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], }, 214 { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], }, 215 { .compatible = "fsl,imx6ul-fec", .data = &fec_devtype[IMX6UL_FEC], }, 216 { .compatible = "fsl,imx8mq-fec", .data = &fec_devtype[IMX8MQ_FEC], }, 217 { .compatible = "fsl,imx8qm-fec", .data = &fec_devtype[IMX8QM_FEC], }, 218 { /* sentinel */ } 219 }; 220 MODULE_DEVICE_TABLE(of, fec_dt_ids); 221 222 static unsigned char macaddr[ETH_ALEN]; 223 module_param_array(macaddr, byte, NULL, 0); 224 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address"); 225 226 #if defined(CONFIG_M5272) 227 /* 228 * Some hardware gets it MAC address out of local flash memory. 229 * if this is non-zero then assume it is the address to get MAC from. 230 */ 231 #if defined(CONFIG_NETtel) 232 #define FEC_FLASHMAC 0xf0006006 233 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) 234 #define FEC_FLASHMAC 0xf0006000 235 #elif defined(CONFIG_CANCam) 236 #define FEC_FLASHMAC 0xf0020000 237 #elif defined (CONFIG_M5272C3) 238 #define FEC_FLASHMAC (0xffe04000 + 4) 239 #elif defined(CONFIG_MOD5272) 240 #define FEC_FLASHMAC 0xffc0406b 241 #else 242 #define FEC_FLASHMAC 0 243 #endif 244 #endif /* CONFIG_M5272 */ 245 246 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets. 247 * 248 * 2048 byte skbufs are allocated. However, alignment requirements 249 * varies between FEC variants. Worst case is 64, so round down by 64. 250 */ 251 #define PKT_MAXBUF_SIZE (round_down(2048 - 64, 64)) 252 #define PKT_MINBUF_SIZE 64 253 254 /* FEC receive acceleration */ 255 #define FEC_RACC_IPDIS (1 << 1) 256 #define FEC_RACC_PRODIS (1 << 2) 257 #define FEC_RACC_SHIFT16 BIT(7) 258 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS) 259 260 /* MIB Control Register */ 261 #define FEC_MIB_CTRLSTAT_DISABLE BIT(31) 262 263 /* 264 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame 265 * size bits. Other FEC hardware does not, so we need to take that into 266 * account when setting it. 267 */ 268 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 269 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \ 270 defined(CONFIG_ARM64) 271 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) 272 #else 273 #define OPT_FRAME_SIZE 0 274 #endif 275 276 /* FEC MII MMFR bits definition */ 277 #define FEC_MMFR_ST (1 << 30) 278 #define FEC_MMFR_ST_C45 (0) 279 #define FEC_MMFR_OP_READ (2 << 28) 280 #define FEC_MMFR_OP_READ_C45 (3 << 28) 281 #define FEC_MMFR_OP_WRITE (1 << 28) 282 #define FEC_MMFR_OP_ADDR_WRITE (0) 283 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23) 284 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18) 285 #define FEC_MMFR_TA (2 << 16) 286 #define FEC_MMFR_DATA(v) (v & 0xffff) 287 /* FEC ECR bits definition */ 288 #define FEC_ECR_MAGICEN (1 << 2) 289 #define FEC_ECR_SLEEP (1 << 3) 290 291 #define FEC_MII_TIMEOUT 30000 /* us */ 292 293 /* Transmitter timeout */ 294 #define TX_TIMEOUT (2 * HZ) 295 296 #define FEC_PAUSE_FLAG_AUTONEG 0x1 297 #define FEC_PAUSE_FLAG_ENABLE 0x2 298 #define FEC_WOL_HAS_MAGIC_PACKET (0x1 << 0) 299 #define FEC_WOL_FLAG_ENABLE (0x1 << 1) 300 #define FEC_WOL_FLAG_SLEEP_ON (0x1 << 2) 301 302 #define COPYBREAK_DEFAULT 256 303 304 /* Max number of allowed TCP segments for software TSO */ 305 #define FEC_MAX_TSO_SEGS 100 306 #define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) 307 308 #define IS_TSO_HEADER(txq, addr) \ 309 ((addr >= txq->tso_hdrs_dma) && \ 310 (addr < txq->tso_hdrs_dma + txq->bd.ring_size * TSO_HEADER_SIZE)) 311 312 static int mii_cnt; 313 314 static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, 315 struct bufdesc_prop *bd) 316 { 317 return (bdp >= bd->last) ? bd->base 318 : (struct bufdesc *)(((void *)bdp) + bd->dsize); 319 } 320 321 static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, 322 struct bufdesc_prop *bd) 323 { 324 return (bdp <= bd->base) ? bd->last 325 : (struct bufdesc *)(((void *)bdp) - bd->dsize); 326 } 327 328 static int fec_enet_get_bd_index(struct bufdesc *bdp, 329 struct bufdesc_prop *bd) 330 { 331 return ((const char *)bdp - (const char *)bd->base) >> bd->dsize_log2; 332 } 333 334 static int fec_enet_get_free_txdesc_num(struct fec_enet_priv_tx_q *txq) 335 { 336 int entries; 337 338 entries = (((const char *)txq->dirty_tx - 339 (const char *)txq->bd.cur) >> txq->bd.dsize_log2) - 1; 340 341 return entries >= 0 ? entries : entries + txq->bd.ring_size; 342 } 343 344 static void swap_buffer(void *bufaddr, int len) 345 { 346 int i; 347 unsigned int *buf = bufaddr; 348 349 for (i = 0; i < len; i += 4, buf++) 350 swab32s(buf); 351 } 352 353 static void swap_buffer2(void *dst_buf, void *src_buf, int len) 354 { 355 int i; 356 unsigned int *src = src_buf; 357 unsigned int *dst = dst_buf; 358 359 for (i = 0; i < len; i += 4, src++, dst++) 360 *dst = swab32p(src); 361 } 362 363 static void fec_dump(struct net_device *ndev) 364 { 365 struct fec_enet_private *fep = netdev_priv(ndev); 366 struct bufdesc *bdp; 367 struct fec_enet_priv_tx_q *txq; 368 int index = 0; 369 370 netdev_info(ndev, "TX ring dump\n"); 371 pr_info("Nr SC addr len SKB\n"); 372 373 txq = fep->tx_queue[0]; 374 bdp = txq->bd.base; 375 376 do { 377 pr_info("%3u %c%c 0x%04x 0x%08x %4u %p\n", 378 index, 379 bdp == txq->bd.cur ? 'S' : ' ', 380 bdp == txq->dirty_tx ? 'H' : ' ', 381 fec16_to_cpu(bdp->cbd_sc), 382 fec32_to_cpu(bdp->cbd_bufaddr), 383 fec16_to_cpu(bdp->cbd_datlen), 384 txq->tx_skbuff[index]); 385 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 386 index++; 387 } while (bdp != txq->bd.base); 388 } 389 390 static inline bool is_ipv4_pkt(struct sk_buff *skb) 391 { 392 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4; 393 } 394 395 static int 396 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev) 397 { 398 /* Only run for packets requiring a checksum. */ 399 if (skb->ip_summed != CHECKSUM_PARTIAL) 400 return 0; 401 402 if (unlikely(skb_cow_head(skb, 0))) 403 return -1; 404 405 if (is_ipv4_pkt(skb)) 406 ip_hdr(skb)->check = 0; 407 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0; 408 409 return 0; 410 } 411 412 static struct bufdesc * 413 fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq, 414 struct sk_buff *skb, 415 struct net_device *ndev) 416 { 417 struct fec_enet_private *fep = netdev_priv(ndev); 418 struct bufdesc *bdp = txq->bd.cur; 419 struct bufdesc_ex *ebdp; 420 int nr_frags = skb_shinfo(skb)->nr_frags; 421 int frag, frag_len; 422 unsigned short status; 423 unsigned int estatus = 0; 424 skb_frag_t *this_frag; 425 unsigned int index; 426 void *bufaddr; 427 dma_addr_t addr; 428 int i; 429 430 for (frag = 0; frag < nr_frags; frag++) { 431 this_frag = &skb_shinfo(skb)->frags[frag]; 432 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 433 ebdp = (struct bufdesc_ex *)bdp; 434 435 status = fec16_to_cpu(bdp->cbd_sc); 436 status &= ~BD_ENET_TX_STATS; 437 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 438 frag_len = skb_frag_size(&skb_shinfo(skb)->frags[frag]); 439 440 /* Handle the last BD specially */ 441 if (frag == nr_frags - 1) { 442 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 443 if (fep->bufdesc_ex) { 444 estatus |= BD_ENET_TX_INT; 445 if (unlikely(skb_shinfo(skb)->tx_flags & 446 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 447 estatus |= BD_ENET_TX_TS; 448 } 449 } 450 451 if (fep->bufdesc_ex) { 452 if (fep->quirks & FEC_QUIRK_HAS_AVB) 453 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 454 if (skb->ip_summed == CHECKSUM_PARTIAL) 455 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 456 457 ebdp->cbd_bdu = 0; 458 ebdp->cbd_esc = cpu_to_fec32(estatus); 459 } 460 461 bufaddr = skb_frag_address(this_frag); 462 463 index = fec_enet_get_bd_index(bdp, &txq->bd); 464 if (((unsigned long) bufaddr) & fep->tx_align || 465 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 466 memcpy(txq->tx_bounce[index], bufaddr, frag_len); 467 bufaddr = txq->tx_bounce[index]; 468 469 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 470 swap_buffer(bufaddr, frag_len); 471 } 472 473 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len, 474 DMA_TO_DEVICE); 475 if (dma_mapping_error(&fep->pdev->dev, addr)) { 476 if (net_ratelimit()) 477 netdev_err(ndev, "Tx DMA memory map failed\n"); 478 goto dma_mapping_error; 479 } 480 481 bdp->cbd_bufaddr = cpu_to_fec32(addr); 482 bdp->cbd_datlen = cpu_to_fec16(frag_len); 483 /* Make sure the updates to rest of the descriptor are 484 * performed before transferring ownership. 485 */ 486 wmb(); 487 bdp->cbd_sc = cpu_to_fec16(status); 488 } 489 490 return bdp; 491 dma_mapping_error: 492 bdp = txq->bd.cur; 493 for (i = 0; i < frag; i++) { 494 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 495 dma_unmap_single(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr), 496 fec16_to_cpu(bdp->cbd_datlen), DMA_TO_DEVICE); 497 } 498 return ERR_PTR(-ENOMEM); 499 } 500 501 static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq, 502 struct sk_buff *skb, struct net_device *ndev) 503 { 504 struct fec_enet_private *fep = netdev_priv(ndev); 505 int nr_frags = skb_shinfo(skb)->nr_frags; 506 struct bufdesc *bdp, *last_bdp; 507 void *bufaddr; 508 dma_addr_t addr; 509 unsigned short status; 510 unsigned short buflen; 511 unsigned int estatus = 0; 512 unsigned int index; 513 int entries_free; 514 515 entries_free = fec_enet_get_free_txdesc_num(txq); 516 if (entries_free < MAX_SKB_FRAGS + 1) { 517 dev_kfree_skb_any(skb); 518 if (net_ratelimit()) 519 netdev_err(ndev, "NOT enough BD for SG!\n"); 520 return NETDEV_TX_OK; 521 } 522 523 /* Protocol checksum off-load for TCP and UDP. */ 524 if (fec_enet_clear_csum(skb, ndev)) { 525 dev_kfree_skb_any(skb); 526 return NETDEV_TX_OK; 527 } 528 529 /* Fill in a Tx ring entry */ 530 bdp = txq->bd.cur; 531 last_bdp = bdp; 532 status = fec16_to_cpu(bdp->cbd_sc); 533 status &= ~BD_ENET_TX_STATS; 534 535 /* Set buffer length and buffer pointer */ 536 bufaddr = skb->data; 537 buflen = skb_headlen(skb); 538 539 index = fec_enet_get_bd_index(bdp, &txq->bd); 540 if (((unsigned long) bufaddr) & fep->tx_align || 541 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 542 memcpy(txq->tx_bounce[index], skb->data, buflen); 543 bufaddr = txq->tx_bounce[index]; 544 545 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 546 swap_buffer(bufaddr, buflen); 547 } 548 549 /* Push the data cache so the CPM does not get stale memory data. */ 550 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE); 551 if (dma_mapping_error(&fep->pdev->dev, addr)) { 552 dev_kfree_skb_any(skb); 553 if (net_ratelimit()) 554 netdev_err(ndev, "Tx DMA memory map failed\n"); 555 return NETDEV_TX_OK; 556 } 557 558 if (nr_frags) { 559 last_bdp = fec_enet_txq_submit_frag_skb(txq, skb, ndev); 560 if (IS_ERR(last_bdp)) { 561 dma_unmap_single(&fep->pdev->dev, addr, 562 buflen, DMA_TO_DEVICE); 563 dev_kfree_skb_any(skb); 564 return NETDEV_TX_OK; 565 } 566 } else { 567 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 568 if (fep->bufdesc_ex) { 569 estatus = BD_ENET_TX_INT; 570 if (unlikely(skb_shinfo(skb)->tx_flags & 571 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 572 estatus |= BD_ENET_TX_TS; 573 } 574 } 575 bdp->cbd_bufaddr = cpu_to_fec32(addr); 576 bdp->cbd_datlen = cpu_to_fec16(buflen); 577 578 if (fep->bufdesc_ex) { 579 580 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 581 582 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 583 fep->hwts_tx_en)) 584 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 585 586 if (fep->quirks & FEC_QUIRK_HAS_AVB) 587 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 588 589 if (skb->ip_summed == CHECKSUM_PARTIAL) 590 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 591 592 ebdp->cbd_bdu = 0; 593 ebdp->cbd_esc = cpu_to_fec32(estatus); 594 } 595 596 index = fec_enet_get_bd_index(last_bdp, &txq->bd); 597 /* Save skb pointer */ 598 txq->tx_skbuff[index] = skb; 599 600 /* Make sure the updates to rest of the descriptor are performed before 601 * transferring ownership. 602 */ 603 wmb(); 604 605 /* Send it on its way. Tell FEC it's ready, interrupt when done, 606 * it's the last BD of the frame, and to put the CRC on the end. 607 */ 608 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC); 609 bdp->cbd_sc = cpu_to_fec16(status); 610 611 /* If this was the last BD in the ring, start at the beginning again. */ 612 bdp = fec_enet_get_nextdesc(last_bdp, &txq->bd); 613 614 skb_tx_timestamp(skb); 615 616 /* Make sure the update to bdp and tx_skbuff are performed before 617 * txq->bd.cur. 618 */ 619 wmb(); 620 txq->bd.cur = bdp; 621 622 /* Trigger transmission start */ 623 writel(0, txq->bd.reg_desc_active); 624 625 return 0; 626 } 627 628 static int 629 fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb, 630 struct net_device *ndev, 631 struct bufdesc *bdp, int index, char *data, 632 int size, bool last_tcp, bool is_last) 633 { 634 struct fec_enet_private *fep = netdev_priv(ndev); 635 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 636 unsigned short status; 637 unsigned int estatus = 0; 638 dma_addr_t addr; 639 640 status = fec16_to_cpu(bdp->cbd_sc); 641 status &= ~BD_ENET_TX_STATS; 642 643 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 644 645 if (((unsigned long) data) & fep->tx_align || 646 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 647 memcpy(txq->tx_bounce[index], data, size); 648 data = txq->tx_bounce[index]; 649 650 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 651 swap_buffer(data, size); 652 } 653 654 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE); 655 if (dma_mapping_error(&fep->pdev->dev, addr)) { 656 dev_kfree_skb_any(skb); 657 if (net_ratelimit()) 658 netdev_err(ndev, "Tx DMA memory map failed\n"); 659 return NETDEV_TX_BUSY; 660 } 661 662 bdp->cbd_datlen = cpu_to_fec16(size); 663 bdp->cbd_bufaddr = cpu_to_fec32(addr); 664 665 if (fep->bufdesc_ex) { 666 if (fep->quirks & FEC_QUIRK_HAS_AVB) 667 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 668 if (skb->ip_summed == CHECKSUM_PARTIAL) 669 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 670 ebdp->cbd_bdu = 0; 671 ebdp->cbd_esc = cpu_to_fec32(estatus); 672 } 673 674 /* Handle the last BD specially */ 675 if (last_tcp) 676 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC); 677 if (is_last) { 678 status |= BD_ENET_TX_INTR; 679 if (fep->bufdesc_ex) 680 ebdp->cbd_esc |= cpu_to_fec32(BD_ENET_TX_INT); 681 } 682 683 bdp->cbd_sc = cpu_to_fec16(status); 684 685 return 0; 686 } 687 688 static int 689 fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq, 690 struct sk_buff *skb, struct net_device *ndev, 691 struct bufdesc *bdp, int index) 692 { 693 struct fec_enet_private *fep = netdev_priv(ndev); 694 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 695 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 696 void *bufaddr; 697 unsigned long dmabuf; 698 unsigned short status; 699 unsigned int estatus = 0; 700 701 status = fec16_to_cpu(bdp->cbd_sc); 702 status &= ~BD_ENET_TX_STATS; 703 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 704 705 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 706 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE; 707 if (((unsigned long)bufaddr) & fep->tx_align || 708 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 709 memcpy(txq->tx_bounce[index], skb->data, hdr_len); 710 bufaddr = txq->tx_bounce[index]; 711 712 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 713 swap_buffer(bufaddr, hdr_len); 714 715 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr, 716 hdr_len, DMA_TO_DEVICE); 717 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) { 718 dev_kfree_skb_any(skb); 719 if (net_ratelimit()) 720 netdev_err(ndev, "Tx DMA memory map failed\n"); 721 return NETDEV_TX_BUSY; 722 } 723 } 724 725 bdp->cbd_bufaddr = cpu_to_fec32(dmabuf); 726 bdp->cbd_datlen = cpu_to_fec16(hdr_len); 727 728 if (fep->bufdesc_ex) { 729 if (fep->quirks & FEC_QUIRK_HAS_AVB) 730 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 731 if (skb->ip_summed == CHECKSUM_PARTIAL) 732 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 733 ebdp->cbd_bdu = 0; 734 ebdp->cbd_esc = cpu_to_fec32(estatus); 735 } 736 737 bdp->cbd_sc = cpu_to_fec16(status); 738 739 return 0; 740 } 741 742 static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq, 743 struct sk_buff *skb, 744 struct net_device *ndev) 745 { 746 struct fec_enet_private *fep = netdev_priv(ndev); 747 int hdr_len, total_len, data_left; 748 struct bufdesc *bdp = txq->bd.cur; 749 struct tso_t tso; 750 unsigned int index = 0; 751 int ret; 752 753 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(txq)) { 754 dev_kfree_skb_any(skb); 755 if (net_ratelimit()) 756 netdev_err(ndev, "NOT enough BD for TSO!\n"); 757 return NETDEV_TX_OK; 758 } 759 760 /* Protocol checksum off-load for TCP and UDP. */ 761 if (fec_enet_clear_csum(skb, ndev)) { 762 dev_kfree_skb_any(skb); 763 return NETDEV_TX_OK; 764 } 765 766 /* Initialize the TSO handler, and prepare the first payload */ 767 hdr_len = tso_start(skb, &tso); 768 769 total_len = skb->len - hdr_len; 770 while (total_len > 0) { 771 char *hdr; 772 773 index = fec_enet_get_bd_index(bdp, &txq->bd); 774 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); 775 total_len -= data_left; 776 777 /* prepare packet headers: MAC + IP + TCP */ 778 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 779 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); 780 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index); 781 if (ret) 782 goto err_release; 783 784 while (data_left > 0) { 785 int size; 786 787 size = min_t(int, tso.size, data_left); 788 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 789 index = fec_enet_get_bd_index(bdp, &txq->bd); 790 ret = fec_enet_txq_put_data_tso(txq, skb, ndev, 791 bdp, index, 792 tso.data, size, 793 size == data_left, 794 total_len == 0); 795 if (ret) 796 goto err_release; 797 798 data_left -= size; 799 tso_build_data(skb, &tso, size); 800 } 801 802 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 803 } 804 805 /* Save skb pointer */ 806 txq->tx_skbuff[index] = skb; 807 808 skb_tx_timestamp(skb); 809 txq->bd.cur = bdp; 810 811 /* Trigger transmission start */ 812 if (!(fep->quirks & FEC_QUIRK_ERR007885) || 813 !readl(txq->bd.reg_desc_active) || 814 !readl(txq->bd.reg_desc_active) || 815 !readl(txq->bd.reg_desc_active) || 816 !readl(txq->bd.reg_desc_active)) 817 writel(0, txq->bd.reg_desc_active); 818 819 return 0; 820 821 err_release: 822 /* TODO: Release all used data descriptors for TSO */ 823 return ret; 824 } 825 826 static netdev_tx_t 827 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) 828 { 829 struct fec_enet_private *fep = netdev_priv(ndev); 830 int entries_free; 831 unsigned short queue; 832 struct fec_enet_priv_tx_q *txq; 833 struct netdev_queue *nq; 834 int ret; 835 836 queue = skb_get_queue_mapping(skb); 837 txq = fep->tx_queue[queue]; 838 nq = netdev_get_tx_queue(ndev, queue); 839 840 if (skb_is_gso(skb)) 841 ret = fec_enet_txq_submit_tso(txq, skb, ndev); 842 else 843 ret = fec_enet_txq_submit_skb(txq, skb, ndev); 844 if (ret) 845 return ret; 846 847 entries_free = fec_enet_get_free_txdesc_num(txq); 848 if (entries_free <= txq->tx_stop_threshold) 849 netif_tx_stop_queue(nq); 850 851 return NETDEV_TX_OK; 852 } 853 854 /* Init RX & TX buffer descriptors 855 */ 856 static void fec_enet_bd_init(struct net_device *dev) 857 { 858 struct fec_enet_private *fep = netdev_priv(dev); 859 struct fec_enet_priv_tx_q *txq; 860 struct fec_enet_priv_rx_q *rxq; 861 struct bufdesc *bdp; 862 unsigned int i; 863 unsigned int q; 864 865 for (q = 0; q < fep->num_rx_queues; q++) { 866 /* Initialize the receive buffer descriptors. */ 867 rxq = fep->rx_queue[q]; 868 bdp = rxq->bd.base; 869 870 for (i = 0; i < rxq->bd.ring_size; i++) { 871 872 /* Initialize the BD for every fragment in the page. */ 873 if (bdp->cbd_bufaddr) 874 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); 875 else 876 bdp->cbd_sc = cpu_to_fec16(0); 877 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 878 } 879 880 /* Set the last buffer to wrap */ 881 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); 882 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 883 884 rxq->bd.cur = rxq->bd.base; 885 } 886 887 for (q = 0; q < fep->num_tx_queues; q++) { 888 /* ...and the same for transmit */ 889 txq = fep->tx_queue[q]; 890 bdp = txq->bd.base; 891 txq->bd.cur = bdp; 892 893 for (i = 0; i < txq->bd.ring_size; i++) { 894 /* Initialize the BD for every fragment in the page. */ 895 bdp->cbd_sc = cpu_to_fec16(0); 896 if (bdp->cbd_bufaddr && 897 !IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr))) 898 dma_unmap_single(&fep->pdev->dev, 899 fec32_to_cpu(bdp->cbd_bufaddr), 900 fec16_to_cpu(bdp->cbd_datlen), 901 DMA_TO_DEVICE); 902 if (txq->tx_skbuff[i]) { 903 dev_kfree_skb_any(txq->tx_skbuff[i]); 904 txq->tx_skbuff[i] = NULL; 905 } 906 bdp->cbd_bufaddr = cpu_to_fec32(0); 907 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 908 } 909 910 /* Set the last buffer to wrap */ 911 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); 912 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 913 txq->dirty_tx = bdp; 914 } 915 } 916 917 static void fec_enet_active_rxring(struct net_device *ndev) 918 { 919 struct fec_enet_private *fep = netdev_priv(ndev); 920 int i; 921 922 for (i = 0; i < fep->num_rx_queues; i++) 923 writel(0, fep->rx_queue[i]->bd.reg_desc_active); 924 } 925 926 static void fec_enet_enable_ring(struct net_device *ndev) 927 { 928 struct fec_enet_private *fep = netdev_priv(ndev); 929 struct fec_enet_priv_tx_q *txq; 930 struct fec_enet_priv_rx_q *rxq; 931 int i; 932 933 for (i = 0; i < fep->num_rx_queues; i++) { 934 rxq = fep->rx_queue[i]; 935 writel(rxq->bd.dma, fep->hwp + FEC_R_DES_START(i)); 936 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i)); 937 938 /* enable DMA1/2 */ 939 if (i) 940 writel(RCMR_MATCHEN | RCMR_CMP(i), 941 fep->hwp + FEC_RCMR(i)); 942 } 943 944 for (i = 0; i < fep->num_tx_queues; i++) { 945 txq = fep->tx_queue[i]; 946 writel(txq->bd.dma, fep->hwp + FEC_X_DES_START(i)); 947 948 /* enable DMA1/2 */ 949 if (i) 950 writel(DMA_CLASS_EN | IDLE_SLOPE(i), 951 fep->hwp + FEC_DMA_CFG(i)); 952 } 953 } 954 955 static void fec_enet_reset_skb(struct net_device *ndev) 956 { 957 struct fec_enet_private *fep = netdev_priv(ndev); 958 struct fec_enet_priv_tx_q *txq; 959 int i, j; 960 961 for (i = 0; i < fep->num_tx_queues; i++) { 962 txq = fep->tx_queue[i]; 963 964 for (j = 0; j < txq->bd.ring_size; j++) { 965 if (txq->tx_skbuff[j]) { 966 dev_kfree_skb_any(txq->tx_skbuff[j]); 967 txq->tx_skbuff[j] = NULL; 968 } 969 } 970 } 971 } 972 973 /* 974 * This function is called to start or restart the FEC during a link 975 * change, transmit timeout, or to reconfigure the FEC. The network 976 * packet processing for this device must be stopped before this call. 977 */ 978 static void 979 fec_restart(struct net_device *ndev) 980 { 981 struct fec_enet_private *fep = netdev_priv(ndev); 982 u32 temp_mac[2]; 983 u32 rcntl = OPT_FRAME_SIZE | 0x04; 984 u32 ecntl = 0x2; /* ETHEREN */ 985 986 /* Whack a reset. We should wait for this. 987 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC 988 * instead of reset MAC itself. 989 */ 990 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES || 991 ((fep->quirks & FEC_QUIRK_NO_HARD_RESET) && fep->link)) { 992 writel(0, fep->hwp + FEC_ECNTRL); 993 } else { 994 writel(1, fep->hwp + FEC_ECNTRL); 995 udelay(10); 996 } 997 998 /* 999 * enet-mac reset will reset mac address registers too, 1000 * so need to reconfigure it. 1001 */ 1002 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN); 1003 writel((__force u32)cpu_to_be32(temp_mac[0]), 1004 fep->hwp + FEC_ADDR_LOW); 1005 writel((__force u32)cpu_to_be32(temp_mac[1]), 1006 fep->hwp + FEC_ADDR_HIGH); 1007 1008 /* Clear any outstanding interrupt, except MDIO. */ 1009 writel((0xffffffff & ~FEC_ENET_MII), fep->hwp + FEC_IEVENT); 1010 1011 fec_enet_bd_init(ndev); 1012 1013 fec_enet_enable_ring(ndev); 1014 1015 /* Reset tx SKB buffers. */ 1016 fec_enet_reset_skb(ndev); 1017 1018 /* Enable MII mode */ 1019 if (fep->full_duplex == DUPLEX_FULL) { 1020 /* FD enable */ 1021 writel(0x04, fep->hwp + FEC_X_CNTRL); 1022 } else { 1023 /* No Rcv on Xmit */ 1024 rcntl |= 0x02; 1025 writel(0x0, fep->hwp + FEC_X_CNTRL); 1026 } 1027 1028 /* Set MII speed */ 1029 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1030 1031 #if !defined(CONFIG_M5272) 1032 if (fep->quirks & FEC_QUIRK_HAS_RACC) { 1033 u32 val = readl(fep->hwp + FEC_RACC); 1034 1035 /* align IP header */ 1036 val |= FEC_RACC_SHIFT16; 1037 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED) 1038 /* set RX checksum */ 1039 val |= FEC_RACC_OPTIONS; 1040 else 1041 val &= ~FEC_RACC_OPTIONS; 1042 writel(val, fep->hwp + FEC_RACC); 1043 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_FTRL); 1044 } 1045 #endif 1046 1047 /* 1048 * The phy interface and speed need to get configured 1049 * differently on enet-mac. 1050 */ 1051 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 1052 /* Enable flow control and length check */ 1053 rcntl |= 0x40000000 | 0x00000020; 1054 1055 /* RGMII, RMII or MII */ 1056 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII || 1057 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 1058 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID || 1059 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) 1060 rcntl |= (1 << 6); 1061 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 1062 rcntl |= (1 << 8); 1063 else 1064 rcntl &= ~(1 << 8); 1065 1066 /* 1G, 100M or 10M */ 1067 if (ndev->phydev) { 1068 if (ndev->phydev->speed == SPEED_1000) 1069 ecntl |= (1 << 5); 1070 else if (ndev->phydev->speed == SPEED_100) 1071 rcntl &= ~(1 << 9); 1072 else 1073 rcntl |= (1 << 9); 1074 } 1075 } else { 1076 #ifdef FEC_MIIGSK_ENR 1077 if (fep->quirks & FEC_QUIRK_USE_GASKET) { 1078 u32 cfgr; 1079 /* disable the gasket and wait */ 1080 writel(0, fep->hwp + FEC_MIIGSK_ENR); 1081 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4) 1082 udelay(1); 1083 1084 /* 1085 * configure the gasket: 1086 * RMII, 50 MHz, no loopback, no echo 1087 * MII, 25 MHz, no loopback, no echo 1088 */ 1089 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 1090 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII; 1091 if (ndev->phydev && ndev->phydev->speed == SPEED_10) 1092 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M; 1093 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR); 1094 1095 /* re-enable the gasket */ 1096 writel(2, fep->hwp + FEC_MIIGSK_ENR); 1097 } 1098 #endif 1099 } 1100 1101 #if !defined(CONFIG_M5272) 1102 /* enable pause frame*/ 1103 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) || 1104 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) && 1105 ndev->phydev && ndev->phydev->pause)) { 1106 rcntl |= FEC_ENET_FCE; 1107 1108 /* set FIFO threshold parameter to reduce overrun */ 1109 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM); 1110 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL); 1111 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM); 1112 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL); 1113 1114 /* OPD */ 1115 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD); 1116 } else { 1117 rcntl &= ~FEC_ENET_FCE; 1118 } 1119 #endif /* !defined(CONFIG_M5272) */ 1120 1121 writel(rcntl, fep->hwp + FEC_R_CNTRL); 1122 1123 /* Setup multicast filter. */ 1124 set_multicast_list(ndev); 1125 #ifndef CONFIG_M5272 1126 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); 1127 writel(0, fep->hwp + FEC_HASH_TABLE_LOW); 1128 #endif 1129 1130 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 1131 /* enable ENET endian swap */ 1132 ecntl |= (1 << 8); 1133 /* enable ENET store and forward mode */ 1134 writel(1 << 8, fep->hwp + FEC_X_WMRK); 1135 } 1136 1137 if (fep->bufdesc_ex) 1138 ecntl |= (1 << 4); 1139 1140 if (fep->quirks & FEC_QUIRK_DELAYED_CLKS_SUPPORT && 1141 fep->rgmii_txc_dly) 1142 ecntl |= FEC_ENET_TXC_DLY; 1143 if (fep->quirks & FEC_QUIRK_DELAYED_CLKS_SUPPORT && 1144 fep->rgmii_rxc_dly) 1145 ecntl |= FEC_ENET_RXC_DLY; 1146 1147 #ifndef CONFIG_M5272 1148 /* Enable the MIB statistic event counters */ 1149 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT); 1150 #endif 1151 1152 /* And last, enable the transmit and receive processing */ 1153 writel(ecntl, fep->hwp + FEC_ECNTRL); 1154 fec_enet_active_rxring(ndev); 1155 1156 if (fep->bufdesc_ex) 1157 fec_ptp_start_cyclecounter(ndev); 1158 1159 /* Enable interrupts we wish to service */ 1160 if (fep->link) 1161 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1162 else 1163 writel(0, fep->hwp + FEC_IMASK); 1164 1165 /* Init the interrupt coalescing */ 1166 fec_enet_itr_coal_init(ndev); 1167 1168 } 1169 1170 static void fec_enet_stop_mode(struct fec_enet_private *fep, bool enabled) 1171 { 1172 struct fec_platform_data *pdata = fep->pdev->dev.platform_data; 1173 struct fec_stop_mode_gpr *stop_gpr = &fep->stop_gpr; 1174 1175 if (stop_gpr->gpr) { 1176 if (enabled) 1177 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg, 1178 BIT(stop_gpr->bit), 1179 BIT(stop_gpr->bit)); 1180 else 1181 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg, 1182 BIT(stop_gpr->bit), 0); 1183 } else if (pdata && pdata->sleep_mode_enable) { 1184 pdata->sleep_mode_enable(enabled); 1185 } 1186 } 1187 1188 static void 1189 fec_stop(struct net_device *ndev) 1190 { 1191 struct fec_enet_private *fep = netdev_priv(ndev); 1192 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8); 1193 u32 val; 1194 1195 /* We cannot expect a graceful transmit stop without link !!! */ 1196 if (fep->link) { 1197 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ 1198 udelay(10); 1199 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) 1200 netdev_err(ndev, "Graceful transmit stop did not complete!\n"); 1201 } 1202 1203 /* Whack a reset. We should wait for this. 1204 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC 1205 * instead of reset MAC itself. 1206 */ 1207 if (!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1208 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) { 1209 writel(0, fep->hwp + FEC_ECNTRL); 1210 } else { 1211 writel(1, fep->hwp + FEC_ECNTRL); 1212 udelay(10); 1213 } 1214 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1215 } else { 1216 writel(FEC_DEFAULT_IMASK | FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK); 1217 val = readl(fep->hwp + FEC_ECNTRL); 1218 val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP); 1219 writel(val, fep->hwp + FEC_ECNTRL); 1220 fec_enet_stop_mode(fep, true); 1221 } 1222 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1223 1224 /* We have to keep ENET enabled to have MII interrupt stay working */ 1225 if (fep->quirks & FEC_QUIRK_ENET_MAC && 1226 !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1227 writel(2, fep->hwp + FEC_ECNTRL); 1228 writel(rmii_mode, fep->hwp + FEC_R_CNTRL); 1229 } 1230 } 1231 1232 1233 static void 1234 fec_timeout(struct net_device *ndev, unsigned int txqueue) 1235 { 1236 struct fec_enet_private *fep = netdev_priv(ndev); 1237 1238 fec_dump(ndev); 1239 1240 ndev->stats.tx_errors++; 1241 1242 schedule_work(&fep->tx_timeout_work); 1243 } 1244 1245 static void fec_enet_timeout_work(struct work_struct *work) 1246 { 1247 struct fec_enet_private *fep = 1248 container_of(work, struct fec_enet_private, tx_timeout_work); 1249 struct net_device *ndev = fep->netdev; 1250 1251 rtnl_lock(); 1252 if (netif_device_present(ndev) || netif_running(ndev)) { 1253 napi_disable(&fep->napi); 1254 netif_tx_lock_bh(ndev); 1255 fec_restart(ndev); 1256 netif_tx_wake_all_queues(ndev); 1257 netif_tx_unlock_bh(ndev); 1258 napi_enable(&fep->napi); 1259 } 1260 rtnl_unlock(); 1261 } 1262 1263 static void 1264 fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts, 1265 struct skb_shared_hwtstamps *hwtstamps) 1266 { 1267 unsigned long flags; 1268 u64 ns; 1269 1270 spin_lock_irqsave(&fep->tmreg_lock, flags); 1271 ns = timecounter_cyc2time(&fep->tc, ts); 1272 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 1273 1274 memset(hwtstamps, 0, sizeof(*hwtstamps)); 1275 hwtstamps->hwtstamp = ns_to_ktime(ns); 1276 } 1277 1278 static void 1279 fec_enet_tx_queue(struct net_device *ndev, u16 queue_id) 1280 { 1281 struct fec_enet_private *fep; 1282 struct bufdesc *bdp; 1283 unsigned short status; 1284 struct sk_buff *skb; 1285 struct fec_enet_priv_tx_q *txq; 1286 struct netdev_queue *nq; 1287 int index = 0; 1288 int entries_free; 1289 1290 fep = netdev_priv(ndev); 1291 1292 txq = fep->tx_queue[queue_id]; 1293 /* get next bdp of dirty_tx */ 1294 nq = netdev_get_tx_queue(ndev, queue_id); 1295 bdp = txq->dirty_tx; 1296 1297 /* get next bdp of dirty_tx */ 1298 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1299 1300 while (bdp != READ_ONCE(txq->bd.cur)) { 1301 /* Order the load of bd.cur and cbd_sc */ 1302 rmb(); 1303 status = fec16_to_cpu(READ_ONCE(bdp->cbd_sc)); 1304 if (status & BD_ENET_TX_READY) 1305 break; 1306 1307 index = fec_enet_get_bd_index(bdp, &txq->bd); 1308 1309 skb = txq->tx_skbuff[index]; 1310 txq->tx_skbuff[index] = NULL; 1311 if (!IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr))) 1312 dma_unmap_single(&fep->pdev->dev, 1313 fec32_to_cpu(bdp->cbd_bufaddr), 1314 fec16_to_cpu(bdp->cbd_datlen), 1315 DMA_TO_DEVICE); 1316 bdp->cbd_bufaddr = cpu_to_fec32(0); 1317 if (!skb) 1318 goto skb_done; 1319 1320 /* Check for errors. */ 1321 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | 1322 BD_ENET_TX_RL | BD_ENET_TX_UN | 1323 BD_ENET_TX_CSL)) { 1324 ndev->stats.tx_errors++; 1325 if (status & BD_ENET_TX_HB) /* No heartbeat */ 1326 ndev->stats.tx_heartbeat_errors++; 1327 if (status & BD_ENET_TX_LC) /* Late collision */ 1328 ndev->stats.tx_window_errors++; 1329 if (status & BD_ENET_TX_RL) /* Retrans limit */ 1330 ndev->stats.tx_aborted_errors++; 1331 if (status & BD_ENET_TX_UN) /* Underrun */ 1332 ndev->stats.tx_fifo_errors++; 1333 if (status & BD_ENET_TX_CSL) /* Carrier lost */ 1334 ndev->stats.tx_carrier_errors++; 1335 } else { 1336 ndev->stats.tx_packets++; 1337 ndev->stats.tx_bytes += skb->len; 1338 } 1339 1340 /* NOTE: SKBTX_IN_PROGRESS being set does not imply it's we who 1341 * are to time stamp the packet, so we still need to check time 1342 * stamping enabled flag. 1343 */ 1344 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS && 1345 fep->hwts_tx_en) && 1346 fep->bufdesc_ex) { 1347 struct skb_shared_hwtstamps shhwtstamps; 1348 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1349 1350 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), &shhwtstamps); 1351 skb_tstamp_tx(skb, &shhwtstamps); 1352 } 1353 1354 /* Deferred means some collisions occurred during transmit, 1355 * but we eventually sent the packet OK. 1356 */ 1357 if (status & BD_ENET_TX_DEF) 1358 ndev->stats.collisions++; 1359 1360 /* Free the sk buffer associated with this last transmit */ 1361 dev_kfree_skb_any(skb); 1362 skb_done: 1363 /* Make sure the update to bdp and tx_skbuff are performed 1364 * before dirty_tx 1365 */ 1366 wmb(); 1367 txq->dirty_tx = bdp; 1368 1369 /* Update pointer to next buffer descriptor to be transmitted */ 1370 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1371 1372 /* Since we have freed up a buffer, the ring is no longer full 1373 */ 1374 if (netif_tx_queue_stopped(nq)) { 1375 entries_free = fec_enet_get_free_txdesc_num(txq); 1376 if (entries_free >= txq->tx_wake_threshold) 1377 netif_tx_wake_queue(nq); 1378 } 1379 } 1380 1381 /* ERR006358: Keep the transmitter going */ 1382 if (bdp != txq->bd.cur && 1383 readl(txq->bd.reg_desc_active) == 0) 1384 writel(0, txq->bd.reg_desc_active); 1385 } 1386 1387 static void fec_enet_tx(struct net_device *ndev) 1388 { 1389 struct fec_enet_private *fep = netdev_priv(ndev); 1390 int i; 1391 1392 /* Make sure that AVB queues are processed first. */ 1393 for (i = fep->num_tx_queues - 1; i >= 0; i--) 1394 fec_enet_tx_queue(ndev, i); 1395 } 1396 1397 static int 1398 fec_enet_new_rxbdp(struct net_device *ndev, struct bufdesc *bdp, struct sk_buff *skb) 1399 { 1400 struct fec_enet_private *fep = netdev_priv(ndev); 1401 int off; 1402 1403 off = ((unsigned long)skb->data) & fep->rx_align; 1404 if (off) 1405 skb_reserve(skb, fep->rx_align + 1 - off); 1406 1407 bdp->cbd_bufaddr = cpu_to_fec32(dma_map_single(&fep->pdev->dev, skb->data, FEC_ENET_RX_FRSIZE - fep->rx_align, DMA_FROM_DEVICE)); 1408 if (dma_mapping_error(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr))) { 1409 if (net_ratelimit()) 1410 netdev_err(ndev, "Rx DMA memory map failed\n"); 1411 return -ENOMEM; 1412 } 1413 1414 return 0; 1415 } 1416 1417 static bool fec_enet_copybreak(struct net_device *ndev, struct sk_buff **skb, 1418 struct bufdesc *bdp, u32 length, bool swap) 1419 { 1420 struct fec_enet_private *fep = netdev_priv(ndev); 1421 struct sk_buff *new_skb; 1422 1423 if (length > fep->rx_copybreak) 1424 return false; 1425 1426 new_skb = netdev_alloc_skb(ndev, length); 1427 if (!new_skb) 1428 return false; 1429 1430 dma_sync_single_for_cpu(&fep->pdev->dev, 1431 fec32_to_cpu(bdp->cbd_bufaddr), 1432 FEC_ENET_RX_FRSIZE - fep->rx_align, 1433 DMA_FROM_DEVICE); 1434 if (!swap) 1435 memcpy(new_skb->data, (*skb)->data, length); 1436 else 1437 swap_buffer2(new_skb->data, (*skb)->data, length); 1438 *skb = new_skb; 1439 1440 return true; 1441 } 1442 1443 /* During a receive, the bd_rx.cur points to the current incoming buffer. 1444 * When we update through the ring, if the next incoming buffer has 1445 * not been given to the system, we just set the empty indicator, 1446 * effectively tossing the packet. 1447 */ 1448 static int 1449 fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id) 1450 { 1451 struct fec_enet_private *fep = netdev_priv(ndev); 1452 struct fec_enet_priv_rx_q *rxq; 1453 struct bufdesc *bdp; 1454 unsigned short status; 1455 struct sk_buff *skb_new = NULL; 1456 struct sk_buff *skb; 1457 ushort pkt_len; 1458 __u8 *data; 1459 int pkt_received = 0; 1460 struct bufdesc_ex *ebdp = NULL; 1461 bool vlan_packet_rcvd = false; 1462 u16 vlan_tag; 1463 int index = 0; 1464 bool is_copybreak; 1465 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME; 1466 1467 #ifdef CONFIG_M532x 1468 flush_cache_all(); 1469 #endif 1470 rxq = fep->rx_queue[queue_id]; 1471 1472 /* First, grab all of the stats for the incoming packet. 1473 * These get messed up if we get called due to a busy condition. 1474 */ 1475 bdp = rxq->bd.cur; 1476 1477 while (!((status = fec16_to_cpu(bdp->cbd_sc)) & BD_ENET_RX_EMPTY)) { 1478 1479 if (pkt_received >= budget) 1480 break; 1481 pkt_received++; 1482 1483 writel(FEC_ENET_RXF, fep->hwp + FEC_IEVENT); 1484 1485 /* Check for errors. */ 1486 status ^= BD_ENET_RX_LAST; 1487 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | 1488 BD_ENET_RX_CR | BD_ENET_RX_OV | BD_ENET_RX_LAST | 1489 BD_ENET_RX_CL)) { 1490 ndev->stats.rx_errors++; 1491 if (status & BD_ENET_RX_OV) { 1492 /* FIFO overrun */ 1493 ndev->stats.rx_fifo_errors++; 1494 goto rx_processing_done; 1495 } 1496 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH 1497 | BD_ENET_RX_LAST)) { 1498 /* Frame too long or too short. */ 1499 ndev->stats.rx_length_errors++; 1500 if (status & BD_ENET_RX_LAST) 1501 netdev_err(ndev, "rcv is not +last\n"); 1502 } 1503 if (status & BD_ENET_RX_CR) /* CRC Error */ 1504 ndev->stats.rx_crc_errors++; 1505 /* Report late collisions as a frame error. */ 1506 if (status & (BD_ENET_RX_NO | BD_ENET_RX_CL)) 1507 ndev->stats.rx_frame_errors++; 1508 goto rx_processing_done; 1509 } 1510 1511 /* Process the incoming frame. */ 1512 ndev->stats.rx_packets++; 1513 pkt_len = fec16_to_cpu(bdp->cbd_datlen); 1514 ndev->stats.rx_bytes += pkt_len; 1515 1516 index = fec_enet_get_bd_index(bdp, &rxq->bd); 1517 skb = rxq->rx_skbuff[index]; 1518 1519 /* The packet length includes FCS, but we don't want to 1520 * include that when passing upstream as it messes up 1521 * bridging applications. 1522 */ 1523 is_copybreak = fec_enet_copybreak(ndev, &skb, bdp, pkt_len - 4, 1524 need_swap); 1525 if (!is_copybreak) { 1526 skb_new = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE); 1527 if (unlikely(!skb_new)) { 1528 ndev->stats.rx_dropped++; 1529 goto rx_processing_done; 1530 } 1531 dma_unmap_single(&fep->pdev->dev, 1532 fec32_to_cpu(bdp->cbd_bufaddr), 1533 FEC_ENET_RX_FRSIZE - fep->rx_align, 1534 DMA_FROM_DEVICE); 1535 } 1536 1537 prefetch(skb->data - NET_IP_ALIGN); 1538 skb_put(skb, pkt_len - 4); 1539 data = skb->data; 1540 1541 if (!is_copybreak && need_swap) 1542 swap_buffer(data, pkt_len); 1543 1544 #if !defined(CONFIG_M5272) 1545 if (fep->quirks & FEC_QUIRK_HAS_RACC) 1546 data = skb_pull_inline(skb, 2); 1547 #endif 1548 1549 /* Extract the enhanced buffer descriptor */ 1550 ebdp = NULL; 1551 if (fep->bufdesc_ex) 1552 ebdp = (struct bufdesc_ex *)bdp; 1553 1554 /* If this is a VLAN packet remove the VLAN Tag */ 1555 vlan_packet_rcvd = false; 1556 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) && 1557 fep->bufdesc_ex && 1558 (ebdp->cbd_esc & cpu_to_fec32(BD_ENET_RX_VLAN))) { 1559 /* Push and remove the vlan tag */ 1560 struct vlan_hdr *vlan_header = 1561 (struct vlan_hdr *) (data + ETH_HLEN); 1562 vlan_tag = ntohs(vlan_header->h_vlan_TCI); 1563 1564 vlan_packet_rcvd = true; 1565 1566 memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2); 1567 skb_pull(skb, VLAN_HLEN); 1568 } 1569 1570 skb->protocol = eth_type_trans(skb, ndev); 1571 1572 /* Get receive timestamp from the skb */ 1573 if (fep->hwts_rx_en && fep->bufdesc_ex) 1574 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), 1575 skb_hwtstamps(skb)); 1576 1577 if (fep->bufdesc_ex && 1578 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) { 1579 if (!(ebdp->cbd_esc & cpu_to_fec32(FLAG_RX_CSUM_ERROR))) { 1580 /* don't check it */ 1581 skb->ip_summed = CHECKSUM_UNNECESSARY; 1582 } else { 1583 skb_checksum_none_assert(skb); 1584 } 1585 } 1586 1587 /* Handle received VLAN packets */ 1588 if (vlan_packet_rcvd) 1589 __vlan_hwaccel_put_tag(skb, 1590 htons(ETH_P_8021Q), 1591 vlan_tag); 1592 1593 skb_record_rx_queue(skb, queue_id); 1594 napi_gro_receive(&fep->napi, skb); 1595 1596 if (is_copybreak) { 1597 dma_sync_single_for_device(&fep->pdev->dev, 1598 fec32_to_cpu(bdp->cbd_bufaddr), 1599 FEC_ENET_RX_FRSIZE - fep->rx_align, 1600 DMA_FROM_DEVICE); 1601 } else { 1602 rxq->rx_skbuff[index] = skb_new; 1603 fec_enet_new_rxbdp(ndev, bdp, skb_new); 1604 } 1605 1606 rx_processing_done: 1607 /* Clear the status flags for this buffer */ 1608 status &= ~BD_ENET_RX_STATS; 1609 1610 /* Mark the buffer empty */ 1611 status |= BD_ENET_RX_EMPTY; 1612 1613 if (fep->bufdesc_ex) { 1614 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1615 1616 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); 1617 ebdp->cbd_prot = 0; 1618 ebdp->cbd_bdu = 0; 1619 } 1620 /* Make sure the updates to rest of the descriptor are 1621 * performed before transferring ownership. 1622 */ 1623 wmb(); 1624 bdp->cbd_sc = cpu_to_fec16(status); 1625 1626 /* Update BD pointer to next entry */ 1627 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 1628 1629 /* Doing this here will keep the FEC running while we process 1630 * incoming frames. On a heavily loaded network, we should be 1631 * able to keep up at the expense of system resources. 1632 */ 1633 writel(0, rxq->bd.reg_desc_active); 1634 } 1635 rxq->bd.cur = bdp; 1636 return pkt_received; 1637 } 1638 1639 static int fec_enet_rx(struct net_device *ndev, int budget) 1640 { 1641 struct fec_enet_private *fep = netdev_priv(ndev); 1642 int i, done = 0; 1643 1644 /* Make sure that AVB queues are processed first. */ 1645 for (i = fep->num_rx_queues - 1; i >= 0; i--) 1646 done += fec_enet_rx_queue(ndev, budget - done, i); 1647 1648 return done; 1649 } 1650 1651 static bool fec_enet_collect_events(struct fec_enet_private *fep) 1652 { 1653 uint int_events; 1654 1655 int_events = readl(fep->hwp + FEC_IEVENT); 1656 1657 /* Don't clear MDIO events, we poll for those */ 1658 int_events &= ~FEC_ENET_MII; 1659 1660 writel(int_events, fep->hwp + FEC_IEVENT); 1661 1662 return int_events != 0; 1663 } 1664 1665 static irqreturn_t 1666 fec_enet_interrupt(int irq, void *dev_id) 1667 { 1668 struct net_device *ndev = dev_id; 1669 struct fec_enet_private *fep = netdev_priv(ndev); 1670 irqreturn_t ret = IRQ_NONE; 1671 1672 if (fec_enet_collect_events(fep) && fep->link) { 1673 ret = IRQ_HANDLED; 1674 1675 if (napi_schedule_prep(&fep->napi)) { 1676 /* Disable interrupts */ 1677 writel(0, fep->hwp + FEC_IMASK); 1678 __napi_schedule(&fep->napi); 1679 } 1680 } 1681 1682 return ret; 1683 } 1684 1685 static int fec_enet_rx_napi(struct napi_struct *napi, int budget) 1686 { 1687 struct net_device *ndev = napi->dev; 1688 struct fec_enet_private *fep = netdev_priv(ndev); 1689 int done = 0; 1690 1691 do { 1692 done += fec_enet_rx(ndev, budget - done); 1693 fec_enet_tx(ndev); 1694 } while ((done < budget) && fec_enet_collect_events(fep)); 1695 1696 if (done < budget) { 1697 napi_complete_done(napi, done); 1698 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1699 } 1700 1701 return done; 1702 } 1703 1704 /* ------------------------------------------------------------------------- */ 1705 static int fec_get_mac(struct net_device *ndev) 1706 { 1707 struct fec_enet_private *fep = netdev_priv(ndev); 1708 unsigned char *iap, tmpaddr[ETH_ALEN]; 1709 int ret; 1710 1711 /* 1712 * try to get mac address in following order: 1713 * 1714 * 1) module parameter via kernel command line in form 1715 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0 1716 */ 1717 iap = macaddr; 1718 1719 /* 1720 * 2) from device tree data 1721 */ 1722 if (!is_valid_ether_addr(iap)) { 1723 struct device_node *np = fep->pdev->dev.of_node; 1724 if (np) { 1725 ret = of_get_mac_address(np, tmpaddr); 1726 if (!ret) 1727 iap = tmpaddr; 1728 else if (ret == -EPROBE_DEFER) 1729 return ret; 1730 } 1731 } 1732 1733 /* 1734 * 3) from flash or fuse (via platform data) 1735 */ 1736 if (!is_valid_ether_addr(iap)) { 1737 #ifdef CONFIG_M5272 1738 if (FEC_FLASHMAC) 1739 iap = (unsigned char *)FEC_FLASHMAC; 1740 #else 1741 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev); 1742 1743 if (pdata) 1744 iap = (unsigned char *)&pdata->mac; 1745 #endif 1746 } 1747 1748 /* 1749 * 4) FEC mac registers set by bootloader 1750 */ 1751 if (!is_valid_ether_addr(iap)) { 1752 *((__be32 *) &tmpaddr[0]) = 1753 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW)); 1754 *((__be16 *) &tmpaddr[4]) = 1755 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16); 1756 iap = &tmpaddr[0]; 1757 } 1758 1759 /* 1760 * 5) random mac address 1761 */ 1762 if (!is_valid_ether_addr(iap)) { 1763 /* Report it and use a random ethernet address instead */ 1764 dev_err(&fep->pdev->dev, "Invalid MAC address: %pM\n", iap); 1765 eth_hw_addr_random(ndev); 1766 dev_info(&fep->pdev->dev, "Using random MAC address: %pM\n", 1767 ndev->dev_addr); 1768 return 0; 1769 } 1770 1771 memcpy(ndev->dev_addr, iap, ETH_ALEN); 1772 1773 /* Adjust MAC if using macaddr */ 1774 if (iap == macaddr) 1775 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id; 1776 1777 return 0; 1778 } 1779 1780 /* ------------------------------------------------------------------------- */ 1781 1782 /* 1783 * Phy section 1784 */ 1785 static void fec_enet_adjust_link(struct net_device *ndev) 1786 { 1787 struct fec_enet_private *fep = netdev_priv(ndev); 1788 struct phy_device *phy_dev = ndev->phydev; 1789 int status_change = 0; 1790 1791 /* 1792 * If the netdev is down, or is going down, we're not interested 1793 * in link state events, so just mark our idea of the link as down 1794 * and ignore the event. 1795 */ 1796 if (!netif_running(ndev) || !netif_device_present(ndev)) { 1797 fep->link = 0; 1798 } else if (phy_dev->link) { 1799 if (!fep->link) { 1800 fep->link = phy_dev->link; 1801 status_change = 1; 1802 } 1803 1804 if (fep->full_duplex != phy_dev->duplex) { 1805 fep->full_duplex = phy_dev->duplex; 1806 status_change = 1; 1807 } 1808 1809 if (phy_dev->speed != fep->speed) { 1810 fep->speed = phy_dev->speed; 1811 status_change = 1; 1812 } 1813 1814 /* if any of the above changed restart the FEC */ 1815 if (status_change) { 1816 napi_disable(&fep->napi); 1817 netif_tx_lock_bh(ndev); 1818 fec_restart(ndev); 1819 netif_tx_wake_all_queues(ndev); 1820 netif_tx_unlock_bh(ndev); 1821 napi_enable(&fep->napi); 1822 } 1823 } else { 1824 if (fep->link) { 1825 napi_disable(&fep->napi); 1826 netif_tx_lock_bh(ndev); 1827 fec_stop(ndev); 1828 netif_tx_unlock_bh(ndev); 1829 napi_enable(&fep->napi); 1830 fep->link = phy_dev->link; 1831 status_change = 1; 1832 } 1833 } 1834 1835 if (status_change) 1836 phy_print_status(phy_dev); 1837 } 1838 1839 static int fec_enet_mdio_wait(struct fec_enet_private *fep) 1840 { 1841 uint ievent; 1842 int ret; 1843 1844 ret = readl_poll_timeout_atomic(fep->hwp + FEC_IEVENT, ievent, 1845 ievent & FEC_ENET_MII, 2, 30000); 1846 1847 if (!ret) 1848 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); 1849 1850 return ret; 1851 } 1852 1853 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) 1854 { 1855 struct fec_enet_private *fep = bus->priv; 1856 struct device *dev = &fep->pdev->dev; 1857 int ret = 0, frame_start, frame_addr, frame_op; 1858 bool is_c45 = !!(regnum & MII_ADDR_C45); 1859 1860 ret = pm_runtime_resume_and_get(dev); 1861 if (ret < 0) 1862 return ret; 1863 1864 if (is_c45) { 1865 frame_start = FEC_MMFR_ST_C45; 1866 1867 /* write address */ 1868 frame_addr = (regnum >> 16); 1869 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE | 1870 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 1871 FEC_MMFR_TA | (regnum & 0xFFFF), 1872 fep->hwp + FEC_MII_DATA); 1873 1874 /* wait for end of transfer */ 1875 ret = fec_enet_mdio_wait(fep); 1876 if (ret) { 1877 netdev_err(fep->netdev, "MDIO address write timeout\n"); 1878 goto out; 1879 } 1880 1881 frame_op = FEC_MMFR_OP_READ_C45; 1882 1883 } else { 1884 /* C22 read */ 1885 frame_op = FEC_MMFR_OP_READ; 1886 frame_start = FEC_MMFR_ST; 1887 frame_addr = regnum; 1888 } 1889 1890 /* start a read op */ 1891 writel(frame_start | frame_op | 1892 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 1893 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); 1894 1895 /* wait for end of transfer */ 1896 ret = fec_enet_mdio_wait(fep); 1897 if (ret) { 1898 netdev_err(fep->netdev, "MDIO read timeout\n"); 1899 goto out; 1900 } 1901 1902 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); 1903 1904 out: 1905 pm_runtime_mark_last_busy(dev); 1906 pm_runtime_put_autosuspend(dev); 1907 1908 return ret; 1909 } 1910 1911 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, 1912 u16 value) 1913 { 1914 struct fec_enet_private *fep = bus->priv; 1915 struct device *dev = &fep->pdev->dev; 1916 int ret, frame_start, frame_addr; 1917 bool is_c45 = !!(regnum & MII_ADDR_C45); 1918 1919 ret = pm_runtime_resume_and_get(dev); 1920 if (ret < 0) 1921 return ret; 1922 1923 if (is_c45) { 1924 frame_start = FEC_MMFR_ST_C45; 1925 1926 /* write address */ 1927 frame_addr = (regnum >> 16); 1928 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE | 1929 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 1930 FEC_MMFR_TA | (regnum & 0xFFFF), 1931 fep->hwp + FEC_MII_DATA); 1932 1933 /* wait for end of transfer */ 1934 ret = fec_enet_mdio_wait(fep); 1935 if (ret) { 1936 netdev_err(fep->netdev, "MDIO address write timeout\n"); 1937 goto out; 1938 } 1939 } else { 1940 /* C22 write */ 1941 frame_start = FEC_MMFR_ST; 1942 frame_addr = regnum; 1943 } 1944 1945 /* start a write op */ 1946 writel(frame_start | FEC_MMFR_OP_WRITE | 1947 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 1948 FEC_MMFR_TA | FEC_MMFR_DATA(value), 1949 fep->hwp + FEC_MII_DATA); 1950 1951 /* wait for end of transfer */ 1952 ret = fec_enet_mdio_wait(fep); 1953 if (ret) 1954 netdev_err(fep->netdev, "MDIO write timeout\n"); 1955 1956 out: 1957 pm_runtime_mark_last_busy(dev); 1958 pm_runtime_put_autosuspend(dev); 1959 1960 return ret; 1961 } 1962 1963 static void fec_enet_phy_reset_after_clk_enable(struct net_device *ndev) 1964 { 1965 struct fec_enet_private *fep = netdev_priv(ndev); 1966 struct phy_device *phy_dev = ndev->phydev; 1967 1968 if (phy_dev) { 1969 phy_reset_after_clk_enable(phy_dev); 1970 } else if (fep->phy_node) { 1971 /* 1972 * If the PHY still is not bound to the MAC, but there is 1973 * OF PHY node and a matching PHY device instance already, 1974 * use the OF PHY node to obtain the PHY device instance, 1975 * and then use that PHY device instance when triggering 1976 * the PHY reset. 1977 */ 1978 phy_dev = of_phy_find_device(fep->phy_node); 1979 phy_reset_after_clk_enable(phy_dev); 1980 put_device(&phy_dev->mdio.dev); 1981 } 1982 } 1983 1984 static int fec_enet_clk_enable(struct net_device *ndev, bool enable) 1985 { 1986 struct fec_enet_private *fep = netdev_priv(ndev); 1987 int ret; 1988 1989 if (enable) { 1990 ret = clk_prepare_enable(fep->clk_enet_out); 1991 if (ret) 1992 return ret; 1993 1994 if (fep->clk_ptp) { 1995 mutex_lock(&fep->ptp_clk_mutex); 1996 ret = clk_prepare_enable(fep->clk_ptp); 1997 if (ret) { 1998 mutex_unlock(&fep->ptp_clk_mutex); 1999 goto failed_clk_ptp; 2000 } else { 2001 fep->ptp_clk_on = true; 2002 } 2003 mutex_unlock(&fep->ptp_clk_mutex); 2004 } 2005 2006 ret = clk_prepare_enable(fep->clk_ref); 2007 if (ret) 2008 goto failed_clk_ref; 2009 2010 ret = clk_prepare_enable(fep->clk_2x_txclk); 2011 if (ret) 2012 goto failed_clk_2x_txclk; 2013 2014 fec_enet_phy_reset_after_clk_enable(ndev); 2015 } else { 2016 clk_disable_unprepare(fep->clk_enet_out); 2017 if (fep->clk_ptp) { 2018 mutex_lock(&fep->ptp_clk_mutex); 2019 clk_disable_unprepare(fep->clk_ptp); 2020 fep->ptp_clk_on = false; 2021 mutex_unlock(&fep->ptp_clk_mutex); 2022 } 2023 clk_disable_unprepare(fep->clk_ref); 2024 clk_disable_unprepare(fep->clk_2x_txclk); 2025 } 2026 2027 return 0; 2028 2029 failed_clk_2x_txclk: 2030 if (fep->clk_ref) 2031 clk_disable_unprepare(fep->clk_ref); 2032 failed_clk_ref: 2033 if (fep->clk_ptp) { 2034 mutex_lock(&fep->ptp_clk_mutex); 2035 clk_disable_unprepare(fep->clk_ptp); 2036 fep->ptp_clk_on = false; 2037 mutex_unlock(&fep->ptp_clk_mutex); 2038 } 2039 failed_clk_ptp: 2040 clk_disable_unprepare(fep->clk_enet_out); 2041 2042 return ret; 2043 } 2044 2045 static int fec_enet_parse_rgmii_delay(struct fec_enet_private *fep, 2046 struct device_node *np) 2047 { 2048 u32 rgmii_tx_delay, rgmii_rx_delay; 2049 2050 /* For rgmii tx internal delay, valid values are 0ps and 2000ps */ 2051 if (!of_property_read_u32(np, "tx-internal-delay-ps", &rgmii_tx_delay)) { 2052 if (rgmii_tx_delay != 0 && rgmii_tx_delay != 2000) { 2053 dev_err(&fep->pdev->dev, "The only allowed RGMII TX delay values are: 0ps, 2000ps"); 2054 return -EINVAL; 2055 } else if (rgmii_tx_delay == 2000) { 2056 fep->rgmii_txc_dly = true; 2057 } 2058 } 2059 2060 /* For rgmii rx internal delay, valid values are 0ps and 2000ps */ 2061 if (!of_property_read_u32(np, "rx-internal-delay-ps", &rgmii_rx_delay)) { 2062 if (rgmii_rx_delay != 0 && rgmii_rx_delay != 2000) { 2063 dev_err(&fep->pdev->dev, "The only allowed RGMII RX delay values are: 0ps, 2000ps"); 2064 return -EINVAL; 2065 } else if (rgmii_rx_delay == 2000) { 2066 fep->rgmii_rxc_dly = true; 2067 } 2068 } 2069 2070 return 0; 2071 } 2072 2073 static int fec_enet_mii_probe(struct net_device *ndev) 2074 { 2075 struct fec_enet_private *fep = netdev_priv(ndev); 2076 struct phy_device *phy_dev = NULL; 2077 char mdio_bus_id[MII_BUS_ID_SIZE]; 2078 char phy_name[MII_BUS_ID_SIZE + 3]; 2079 int phy_id; 2080 int dev_id = fep->dev_id; 2081 2082 if (fep->phy_node) { 2083 phy_dev = of_phy_connect(ndev, fep->phy_node, 2084 &fec_enet_adjust_link, 0, 2085 fep->phy_interface); 2086 if (!phy_dev) { 2087 netdev_err(ndev, "Unable to connect to phy\n"); 2088 return -ENODEV; 2089 } 2090 } else { 2091 /* check for attached phy */ 2092 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) { 2093 if (!mdiobus_is_registered_device(fep->mii_bus, phy_id)) 2094 continue; 2095 if (dev_id--) 2096 continue; 2097 strlcpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE); 2098 break; 2099 } 2100 2101 if (phy_id >= PHY_MAX_ADDR) { 2102 netdev_info(ndev, "no PHY, assuming direct connection to switch\n"); 2103 strlcpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); 2104 phy_id = 0; 2105 } 2106 2107 snprintf(phy_name, sizeof(phy_name), 2108 PHY_ID_FMT, mdio_bus_id, phy_id); 2109 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, 2110 fep->phy_interface); 2111 } 2112 2113 if (IS_ERR(phy_dev)) { 2114 netdev_err(ndev, "could not attach to PHY\n"); 2115 return PTR_ERR(phy_dev); 2116 } 2117 2118 /* mask with MAC supported features */ 2119 if (fep->quirks & FEC_QUIRK_HAS_GBIT) { 2120 phy_set_max_speed(phy_dev, 1000); 2121 phy_remove_link_mode(phy_dev, 2122 ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 2123 #if !defined(CONFIG_M5272) 2124 phy_support_sym_pause(phy_dev); 2125 #endif 2126 } 2127 else 2128 phy_set_max_speed(phy_dev, 100); 2129 2130 fep->link = 0; 2131 fep->full_duplex = 0; 2132 2133 phy_dev->mac_managed_pm = 1; 2134 2135 phy_attached_info(phy_dev); 2136 2137 return 0; 2138 } 2139 2140 static int fec_enet_mii_init(struct platform_device *pdev) 2141 { 2142 static struct mii_bus *fec0_mii_bus; 2143 struct net_device *ndev = platform_get_drvdata(pdev); 2144 struct fec_enet_private *fep = netdev_priv(ndev); 2145 bool suppress_preamble = false; 2146 struct device_node *node; 2147 int err = -ENXIO; 2148 u32 mii_speed, holdtime; 2149 u32 bus_freq; 2150 2151 /* 2152 * The i.MX28 dual fec interfaces are not equal. 2153 * Here are the differences: 2154 * 2155 * - fec0 supports MII & RMII modes while fec1 only supports RMII 2156 * - fec0 acts as the 1588 time master while fec1 is slave 2157 * - external phys can only be configured by fec0 2158 * 2159 * That is to say fec1 can not work independently. It only works 2160 * when fec0 is working. The reason behind this design is that the 2161 * second interface is added primarily for Switch mode. 2162 * 2163 * Because of the last point above, both phys are attached on fec0 2164 * mdio interface in board design, and need to be configured by 2165 * fec0 mii_bus. 2166 */ 2167 if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) { 2168 /* fec1 uses fec0 mii_bus */ 2169 if (mii_cnt && fec0_mii_bus) { 2170 fep->mii_bus = fec0_mii_bus; 2171 mii_cnt++; 2172 return 0; 2173 } 2174 return -ENOENT; 2175 } 2176 2177 bus_freq = 2500000; /* 2.5MHz by default */ 2178 node = of_get_child_by_name(pdev->dev.of_node, "mdio"); 2179 if (node) { 2180 of_property_read_u32(node, "clock-frequency", &bus_freq); 2181 suppress_preamble = of_property_read_bool(node, 2182 "suppress-preamble"); 2183 } 2184 2185 /* 2186 * Set MII speed (= clk_get_rate() / 2 * phy_speed) 2187 * 2188 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while 2189 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28 2190 * Reference Manual has an error on this, and gets fixed on i.MX6Q 2191 * document. 2192 */ 2193 mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), bus_freq * 2); 2194 if (fep->quirks & FEC_QUIRK_ENET_MAC) 2195 mii_speed--; 2196 if (mii_speed > 63) { 2197 dev_err(&pdev->dev, 2198 "fec clock (%lu) too fast to get right mii speed\n", 2199 clk_get_rate(fep->clk_ipg)); 2200 err = -EINVAL; 2201 goto err_out; 2202 } 2203 2204 /* 2205 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka 2206 * MII_SPEED) register that defines the MDIO output hold time. Earlier 2207 * versions are RAZ there, so just ignore the difference and write the 2208 * register always. 2209 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns. 2210 * HOLDTIME + 1 is the number of clk cycles the fec is holding the 2211 * output. 2212 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive). 2213 * Given that ceil(clkrate / 5000000) <= 64, the calculation for 2214 * holdtime cannot result in a value greater than 3. 2215 */ 2216 holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1; 2217 2218 fep->phy_speed = mii_speed << 1 | holdtime << 8; 2219 2220 if (suppress_preamble) 2221 fep->phy_speed |= BIT(7); 2222 2223 if (fep->quirks & FEC_QUIRK_CLEAR_SETUP_MII) { 2224 /* Clear MMFR to avoid to generate MII event by writing MSCR. 2225 * MII event generation condition: 2226 * - writing MSCR: 2227 * - mmfr[31:0]_not_zero & mscr[7:0]_is_zero & 2228 * mscr_reg_data_in[7:0] != 0 2229 * - writing MMFR: 2230 * - mscr[7:0]_not_zero 2231 */ 2232 writel(0, fep->hwp + FEC_MII_DATA); 2233 } 2234 2235 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 2236 2237 /* Clear any pending transaction complete indication */ 2238 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); 2239 2240 fep->mii_bus = mdiobus_alloc(); 2241 if (fep->mii_bus == NULL) { 2242 err = -ENOMEM; 2243 goto err_out; 2244 } 2245 2246 fep->mii_bus->name = "fec_enet_mii_bus"; 2247 fep->mii_bus->read = fec_enet_mdio_read; 2248 fep->mii_bus->write = fec_enet_mdio_write; 2249 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 2250 pdev->name, fep->dev_id + 1); 2251 fep->mii_bus->priv = fep; 2252 fep->mii_bus->parent = &pdev->dev; 2253 2254 err = of_mdiobus_register(fep->mii_bus, node); 2255 if (err) 2256 goto err_out_free_mdiobus; 2257 of_node_put(node); 2258 2259 mii_cnt++; 2260 2261 /* save fec0 mii_bus */ 2262 if (fep->quirks & FEC_QUIRK_SINGLE_MDIO) 2263 fec0_mii_bus = fep->mii_bus; 2264 2265 return 0; 2266 2267 err_out_free_mdiobus: 2268 mdiobus_free(fep->mii_bus); 2269 err_out: 2270 of_node_put(node); 2271 return err; 2272 } 2273 2274 static void fec_enet_mii_remove(struct fec_enet_private *fep) 2275 { 2276 if (--mii_cnt == 0) { 2277 mdiobus_unregister(fep->mii_bus); 2278 mdiobus_free(fep->mii_bus); 2279 } 2280 } 2281 2282 static void fec_enet_get_drvinfo(struct net_device *ndev, 2283 struct ethtool_drvinfo *info) 2284 { 2285 struct fec_enet_private *fep = netdev_priv(ndev); 2286 2287 strlcpy(info->driver, fep->pdev->dev.driver->name, 2288 sizeof(info->driver)); 2289 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info)); 2290 } 2291 2292 static int fec_enet_get_regs_len(struct net_device *ndev) 2293 { 2294 struct fec_enet_private *fep = netdev_priv(ndev); 2295 struct resource *r; 2296 int s = 0; 2297 2298 r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0); 2299 if (r) 2300 s = resource_size(r); 2301 2302 return s; 2303 } 2304 2305 /* List of registers that can be safety be read to dump them with ethtool */ 2306 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 2307 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \ 2308 defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST) 2309 static __u32 fec_enet_register_version = 2; 2310 static u32 fec_enet_register_offset[] = { 2311 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0, 2312 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL, 2313 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1, 2314 FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH, 2315 FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, 2316 FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1, 2317 FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2, 2318 FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0, 2319 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM, 2320 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2, 2321 FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1, 2322 FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME, 2323 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT, 2324 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG, 2325 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255, 2326 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047, 2327 RMON_T_P_GTE2048, RMON_T_OCTETS, 2328 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF, 2329 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE, 2330 IEEE_T_FDXFC, IEEE_T_OCTETS_OK, 2331 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN, 2332 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB, 2333 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255, 2334 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047, 2335 RMON_R_P_GTE2048, RMON_R_OCTETS, 2336 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR, 2337 IEEE_R_FDXFC, IEEE_R_OCTETS_OK 2338 }; 2339 #else 2340 static __u32 fec_enet_register_version = 1; 2341 static u32 fec_enet_register_offset[] = { 2342 FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0, 2343 FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0, 2344 FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED, 2345 FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL, 2346 FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, 2347 FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0, 2348 FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0, 2349 FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0, 2350 FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2 2351 }; 2352 #endif 2353 2354 static void fec_enet_get_regs(struct net_device *ndev, 2355 struct ethtool_regs *regs, void *regbuf) 2356 { 2357 struct fec_enet_private *fep = netdev_priv(ndev); 2358 u32 __iomem *theregs = (u32 __iomem *)fep->hwp; 2359 struct device *dev = &fep->pdev->dev; 2360 u32 *buf = (u32 *)regbuf; 2361 u32 i, off; 2362 int ret; 2363 2364 ret = pm_runtime_resume_and_get(dev); 2365 if (ret < 0) 2366 return; 2367 2368 regs->version = fec_enet_register_version; 2369 2370 memset(buf, 0, regs->len); 2371 2372 for (i = 0; i < ARRAY_SIZE(fec_enet_register_offset); i++) { 2373 off = fec_enet_register_offset[i]; 2374 2375 if ((off == FEC_R_BOUND || off == FEC_R_FSTART) && 2376 !(fep->quirks & FEC_QUIRK_HAS_FRREG)) 2377 continue; 2378 2379 off >>= 2; 2380 buf[off] = readl(&theregs[off]); 2381 } 2382 2383 pm_runtime_mark_last_busy(dev); 2384 pm_runtime_put_autosuspend(dev); 2385 } 2386 2387 static int fec_enet_get_ts_info(struct net_device *ndev, 2388 struct ethtool_ts_info *info) 2389 { 2390 struct fec_enet_private *fep = netdev_priv(ndev); 2391 2392 if (fep->bufdesc_ex) { 2393 2394 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 2395 SOF_TIMESTAMPING_RX_SOFTWARE | 2396 SOF_TIMESTAMPING_SOFTWARE | 2397 SOF_TIMESTAMPING_TX_HARDWARE | 2398 SOF_TIMESTAMPING_RX_HARDWARE | 2399 SOF_TIMESTAMPING_RAW_HARDWARE; 2400 if (fep->ptp_clock) 2401 info->phc_index = ptp_clock_index(fep->ptp_clock); 2402 else 2403 info->phc_index = -1; 2404 2405 info->tx_types = (1 << HWTSTAMP_TX_OFF) | 2406 (1 << HWTSTAMP_TX_ON); 2407 2408 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 2409 (1 << HWTSTAMP_FILTER_ALL); 2410 return 0; 2411 } else { 2412 return ethtool_op_get_ts_info(ndev, info); 2413 } 2414 } 2415 2416 #if !defined(CONFIG_M5272) 2417 2418 static void fec_enet_get_pauseparam(struct net_device *ndev, 2419 struct ethtool_pauseparam *pause) 2420 { 2421 struct fec_enet_private *fep = netdev_priv(ndev); 2422 2423 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0; 2424 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0; 2425 pause->rx_pause = pause->tx_pause; 2426 } 2427 2428 static int fec_enet_set_pauseparam(struct net_device *ndev, 2429 struct ethtool_pauseparam *pause) 2430 { 2431 struct fec_enet_private *fep = netdev_priv(ndev); 2432 2433 if (!ndev->phydev) 2434 return -ENODEV; 2435 2436 if (pause->tx_pause != pause->rx_pause) { 2437 netdev_info(ndev, 2438 "hardware only support enable/disable both tx and rx"); 2439 return -EINVAL; 2440 } 2441 2442 fep->pause_flag = 0; 2443 2444 /* tx pause must be same as rx pause */ 2445 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0; 2446 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0; 2447 2448 phy_set_sym_pause(ndev->phydev, pause->rx_pause, pause->tx_pause, 2449 pause->autoneg); 2450 2451 if (pause->autoneg) { 2452 if (netif_running(ndev)) 2453 fec_stop(ndev); 2454 phy_start_aneg(ndev->phydev); 2455 } 2456 if (netif_running(ndev)) { 2457 napi_disable(&fep->napi); 2458 netif_tx_lock_bh(ndev); 2459 fec_restart(ndev); 2460 netif_tx_wake_all_queues(ndev); 2461 netif_tx_unlock_bh(ndev); 2462 napi_enable(&fep->napi); 2463 } 2464 2465 return 0; 2466 } 2467 2468 static const struct fec_stat { 2469 char name[ETH_GSTRING_LEN]; 2470 u16 offset; 2471 } fec_stats[] = { 2472 /* RMON TX */ 2473 { "tx_dropped", RMON_T_DROP }, 2474 { "tx_packets", RMON_T_PACKETS }, 2475 { "tx_broadcast", RMON_T_BC_PKT }, 2476 { "tx_multicast", RMON_T_MC_PKT }, 2477 { "tx_crc_errors", RMON_T_CRC_ALIGN }, 2478 { "tx_undersize", RMON_T_UNDERSIZE }, 2479 { "tx_oversize", RMON_T_OVERSIZE }, 2480 { "tx_fragment", RMON_T_FRAG }, 2481 { "tx_jabber", RMON_T_JAB }, 2482 { "tx_collision", RMON_T_COL }, 2483 { "tx_64byte", RMON_T_P64 }, 2484 { "tx_65to127byte", RMON_T_P65TO127 }, 2485 { "tx_128to255byte", RMON_T_P128TO255 }, 2486 { "tx_256to511byte", RMON_T_P256TO511 }, 2487 { "tx_512to1023byte", RMON_T_P512TO1023 }, 2488 { "tx_1024to2047byte", RMON_T_P1024TO2047 }, 2489 { "tx_GTE2048byte", RMON_T_P_GTE2048 }, 2490 { "tx_octets", RMON_T_OCTETS }, 2491 2492 /* IEEE TX */ 2493 { "IEEE_tx_drop", IEEE_T_DROP }, 2494 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK }, 2495 { "IEEE_tx_1col", IEEE_T_1COL }, 2496 { "IEEE_tx_mcol", IEEE_T_MCOL }, 2497 { "IEEE_tx_def", IEEE_T_DEF }, 2498 { "IEEE_tx_lcol", IEEE_T_LCOL }, 2499 { "IEEE_tx_excol", IEEE_T_EXCOL }, 2500 { "IEEE_tx_macerr", IEEE_T_MACERR }, 2501 { "IEEE_tx_cserr", IEEE_T_CSERR }, 2502 { "IEEE_tx_sqe", IEEE_T_SQE }, 2503 { "IEEE_tx_fdxfc", IEEE_T_FDXFC }, 2504 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK }, 2505 2506 /* RMON RX */ 2507 { "rx_packets", RMON_R_PACKETS }, 2508 { "rx_broadcast", RMON_R_BC_PKT }, 2509 { "rx_multicast", RMON_R_MC_PKT }, 2510 { "rx_crc_errors", RMON_R_CRC_ALIGN }, 2511 { "rx_undersize", RMON_R_UNDERSIZE }, 2512 { "rx_oversize", RMON_R_OVERSIZE }, 2513 { "rx_fragment", RMON_R_FRAG }, 2514 { "rx_jabber", RMON_R_JAB }, 2515 { "rx_64byte", RMON_R_P64 }, 2516 { "rx_65to127byte", RMON_R_P65TO127 }, 2517 { "rx_128to255byte", RMON_R_P128TO255 }, 2518 { "rx_256to511byte", RMON_R_P256TO511 }, 2519 { "rx_512to1023byte", RMON_R_P512TO1023 }, 2520 { "rx_1024to2047byte", RMON_R_P1024TO2047 }, 2521 { "rx_GTE2048byte", RMON_R_P_GTE2048 }, 2522 { "rx_octets", RMON_R_OCTETS }, 2523 2524 /* IEEE RX */ 2525 { "IEEE_rx_drop", IEEE_R_DROP }, 2526 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK }, 2527 { "IEEE_rx_crc", IEEE_R_CRC }, 2528 { "IEEE_rx_align", IEEE_R_ALIGN }, 2529 { "IEEE_rx_macerr", IEEE_R_MACERR }, 2530 { "IEEE_rx_fdxfc", IEEE_R_FDXFC }, 2531 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK }, 2532 }; 2533 2534 #define FEC_STATS_SIZE (ARRAY_SIZE(fec_stats) * sizeof(u64)) 2535 2536 static void fec_enet_update_ethtool_stats(struct net_device *dev) 2537 { 2538 struct fec_enet_private *fep = netdev_priv(dev); 2539 int i; 2540 2541 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2542 fep->ethtool_stats[i] = readl(fep->hwp + fec_stats[i].offset); 2543 } 2544 2545 static void fec_enet_get_ethtool_stats(struct net_device *dev, 2546 struct ethtool_stats *stats, u64 *data) 2547 { 2548 struct fec_enet_private *fep = netdev_priv(dev); 2549 2550 if (netif_running(dev)) 2551 fec_enet_update_ethtool_stats(dev); 2552 2553 memcpy(data, fep->ethtool_stats, FEC_STATS_SIZE); 2554 } 2555 2556 static void fec_enet_get_strings(struct net_device *netdev, 2557 u32 stringset, u8 *data) 2558 { 2559 int i; 2560 switch (stringset) { 2561 case ETH_SS_STATS: 2562 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2563 memcpy(data + i * ETH_GSTRING_LEN, 2564 fec_stats[i].name, ETH_GSTRING_LEN); 2565 break; 2566 case ETH_SS_TEST: 2567 net_selftest_get_strings(data); 2568 break; 2569 } 2570 } 2571 2572 static int fec_enet_get_sset_count(struct net_device *dev, int sset) 2573 { 2574 switch (sset) { 2575 case ETH_SS_STATS: 2576 return ARRAY_SIZE(fec_stats); 2577 case ETH_SS_TEST: 2578 return net_selftest_get_count(); 2579 default: 2580 return -EOPNOTSUPP; 2581 } 2582 } 2583 2584 static void fec_enet_clear_ethtool_stats(struct net_device *dev) 2585 { 2586 struct fec_enet_private *fep = netdev_priv(dev); 2587 int i; 2588 2589 /* Disable MIB statistics counters */ 2590 writel(FEC_MIB_CTRLSTAT_DISABLE, fep->hwp + FEC_MIB_CTRLSTAT); 2591 2592 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2593 writel(0, fep->hwp + fec_stats[i].offset); 2594 2595 /* Don't disable MIB statistics counters */ 2596 writel(0, fep->hwp + FEC_MIB_CTRLSTAT); 2597 } 2598 2599 #else /* !defined(CONFIG_M5272) */ 2600 #define FEC_STATS_SIZE 0 2601 static inline void fec_enet_update_ethtool_stats(struct net_device *dev) 2602 { 2603 } 2604 2605 static inline void fec_enet_clear_ethtool_stats(struct net_device *dev) 2606 { 2607 } 2608 #endif /* !defined(CONFIG_M5272) */ 2609 2610 /* ITR clock source is enet system clock (clk_ahb). 2611 * TCTT unit is cycle_ns * 64 cycle 2612 * So, the ICTT value = X us / (cycle_ns * 64) 2613 */ 2614 static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us) 2615 { 2616 struct fec_enet_private *fep = netdev_priv(ndev); 2617 2618 return us * (fep->itr_clk_rate / 64000) / 1000; 2619 } 2620 2621 /* Set threshold for interrupt coalescing */ 2622 static void fec_enet_itr_coal_set(struct net_device *ndev) 2623 { 2624 struct fec_enet_private *fep = netdev_priv(ndev); 2625 int rx_itr, tx_itr; 2626 2627 /* Must be greater than zero to avoid unpredictable behavior */ 2628 if (!fep->rx_time_itr || !fep->rx_pkts_itr || 2629 !fep->tx_time_itr || !fep->tx_pkts_itr) 2630 return; 2631 2632 /* Select enet system clock as Interrupt Coalescing 2633 * timer Clock Source 2634 */ 2635 rx_itr = FEC_ITR_CLK_SEL; 2636 tx_itr = FEC_ITR_CLK_SEL; 2637 2638 /* set ICFT and ICTT */ 2639 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr); 2640 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr)); 2641 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr); 2642 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr)); 2643 2644 rx_itr |= FEC_ITR_EN; 2645 tx_itr |= FEC_ITR_EN; 2646 2647 writel(tx_itr, fep->hwp + FEC_TXIC0); 2648 writel(rx_itr, fep->hwp + FEC_RXIC0); 2649 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) { 2650 writel(tx_itr, fep->hwp + FEC_TXIC1); 2651 writel(rx_itr, fep->hwp + FEC_RXIC1); 2652 writel(tx_itr, fep->hwp + FEC_TXIC2); 2653 writel(rx_itr, fep->hwp + FEC_RXIC2); 2654 } 2655 } 2656 2657 static int fec_enet_get_coalesce(struct net_device *ndev, 2658 struct ethtool_coalesce *ec, 2659 struct kernel_ethtool_coalesce *kernel_coal, 2660 struct netlink_ext_ack *extack) 2661 { 2662 struct fec_enet_private *fep = netdev_priv(ndev); 2663 2664 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) 2665 return -EOPNOTSUPP; 2666 2667 ec->rx_coalesce_usecs = fep->rx_time_itr; 2668 ec->rx_max_coalesced_frames = fep->rx_pkts_itr; 2669 2670 ec->tx_coalesce_usecs = fep->tx_time_itr; 2671 ec->tx_max_coalesced_frames = fep->tx_pkts_itr; 2672 2673 return 0; 2674 } 2675 2676 static int fec_enet_set_coalesce(struct net_device *ndev, 2677 struct ethtool_coalesce *ec, 2678 struct kernel_ethtool_coalesce *kernel_coal, 2679 struct netlink_ext_ack *extack) 2680 { 2681 struct fec_enet_private *fep = netdev_priv(ndev); 2682 struct device *dev = &fep->pdev->dev; 2683 unsigned int cycle; 2684 2685 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) 2686 return -EOPNOTSUPP; 2687 2688 if (ec->rx_max_coalesced_frames > 255) { 2689 dev_err(dev, "Rx coalesced frames exceed hardware limitation\n"); 2690 return -EINVAL; 2691 } 2692 2693 if (ec->tx_max_coalesced_frames > 255) { 2694 dev_err(dev, "Tx coalesced frame exceed hardware limitation\n"); 2695 return -EINVAL; 2696 } 2697 2698 cycle = fec_enet_us_to_itr_clock(ndev, ec->rx_coalesce_usecs); 2699 if (cycle > 0xFFFF) { 2700 dev_err(dev, "Rx coalesced usec exceed hardware limitation\n"); 2701 return -EINVAL; 2702 } 2703 2704 cycle = fec_enet_us_to_itr_clock(ndev, ec->tx_coalesce_usecs); 2705 if (cycle > 0xFFFF) { 2706 dev_err(dev, "Tx coalesced usec exceed hardware limitation\n"); 2707 return -EINVAL; 2708 } 2709 2710 fep->rx_time_itr = ec->rx_coalesce_usecs; 2711 fep->rx_pkts_itr = ec->rx_max_coalesced_frames; 2712 2713 fep->tx_time_itr = ec->tx_coalesce_usecs; 2714 fep->tx_pkts_itr = ec->tx_max_coalesced_frames; 2715 2716 fec_enet_itr_coal_set(ndev); 2717 2718 return 0; 2719 } 2720 2721 static void fec_enet_itr_coal_init(struct net_device *ndev) 2722 { 2723 struct ethtool_coalesce ec; 2724 2725 ec.rx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT; 2726 ec.rx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT; 2727 2728 ec.tx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT; 2729 ec.tx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT; 2730 2731 fec_enet_set_coalesce(ndev, &ec, NULL, NULL); 2732 } 2733 2734 static int fec_enet_get_tunable(struct net_device *netdev, 2735 const struct ethtool_tunable *tuna, 2736 void *data) 2737 { 2738 struct fec_enet_private *fep = netdev_priv(netdev); 2739 int ret = 0; 2740 2741 switch (tuna->id) { 2742 case ETHTOOL_RX_COPYBREAK: 2743 *(u32 *)data = fep->rx_copybreak; 2744 break; 2745 default: 2746 ret = -EINVAL; 2747 break; 2748 } 2749 2750 return ret; 2751 } 2752 2753 static int fec_enet_set_tunable(struct net_device *netdev, 2754 const struct ethtool_tunable *tuna, 2755 const void *data) 2756 { 2757 struct fec_enet_private *fep = netdev_priv(netdev); 2758 int ret = 0; 2759 2760 switch (tuna->id) { 2761 case ETHTOOL_RX_COPYBREAK: 2762 fep->rx_copybreak = *(u32 *)data; 2763 break; 2764 default: 2765 ret = -EINVAL; 2766 break; 2767 } 2768 2769 return ret; 2770 } 2771 2772 /* LPI Sleep Ts count base on tx clk (clk_ref). 2773 * The lpi sleep cnt value = X us / (cycle_ns). 2774 */ 2775 static int fec_enet_us_to_tx_cycle(struct net_device *ndev, int us) 2776 { 2777 struct fec_enet_private *fep = netdev_priv(ndev); 2778 2779 return us * (fep->clk_ref_rate / 1000) / 1000; 2780 } 2781 2782 static int fec_enet_eee_mode_set(struct net_device *ndev, bool enable) 2783 { 2784 struct fec_enet_private *fep = netdev_priv(ndev); 2785 struct ethtool_eee *p = &fep->eee; 2786 unsigned int sleep_cycle, wake_cycle; 2787 int ret = 0; 2788 2789 if (enable) { 2790 ret = phy_init_eee(ndev->phydev, 0); 2791 if (ret) 2792 return ret; 2793 2794 sleep_cycle = fec_enet_us_to_tx_cycle(ndev, p->tx_lpi_timer); 2795 wake_cycle = sleep_cycle; 2796 } else { 2797 sleep_cycle = 0; 2798 wake_cycle = 0; 2799 } 2800 2801 p->tx_lpi_enabled = enable; 2802 p->eee_enabled = enable; 2803 p->eee_active = enable; 2804 2805 writel(sleep_cycle, fep->hwp + FEC_LPI_SLEEP); 2806 writel(wake_cycle, fep->hwp + FEC_LPI_WAKE); 2807 2808 return 0; 2809 } 2810 2811 static int 2812 fec_enet_get_eee(struct net_device *ndev, struct ethtool_eee *edata) 2813 { 2814 struct fec_enet_private *fep = netdev_priv(ndev); 2815 struct ethtool_eee *p = &fep->eee; 2816 2817 if (!(fep->quirks & FEC_QUIRK_HAS_EEE)) 2818 return -EOPNOTSUPP; 2819 2820 if (!netif_running(ndev)) 2821 return -ENETDOWN; 2822 2823 edata->eee_enabled = p->eee_enabled; 2824 edata->eee_active = p->eee_active; 2825 edata->tx_lpi_timer = p->tx_lpi_timer; 2826 edata->tx_lpi_enabled = p->tx_lpi_enabled; 2827 2828 return phy_ethtool_get_eee(ndev->phydev, edata); 2829 } 2830 2831 static int 2832 fec_enet_set_eee(struct net_device *ndev, struct ethtool_eee *edata) 2833 { 2834 struct fec_enet_private *fep = netdev_priv(ndev); 2835 struct ethtool_eee *p = &fep->eee; 2836 int ret = 0; 2837 2838 if (!(fep->quirks & FEC_QUIRK_HAS_EEE)) 2839 return -EOPNOTSUPP; 2840 2841 if (!netif_running(ndev)) 2842 return -ENETDOWN; 2843 2844 p->tx_lpi_timer = edata->tx_lpi_timer; 2845 2846 if (!edata->eee_enabled || !edata->tx_lpi_enabled || 2847 !edata->tx_lpi_timer) 2848 ret = fec_enet_eee_mode_set(ndev, false); 2849 else 2850 ret = fec_enet_eee_mode_set(ndev, true); 2851 2852 if (ret) 2853 return ret; 2854 2855 return phy_ethtool_set_eee(ndev->phydev, edata); 2856 } 2857 2858 static void 2859 fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2860 { 2861 struct fec_enet_private *fep = netdev_priv(ndev); 2862 2863 if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) { 2864 wol->supported = WAKE_MAGIC; 2865 wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0; 2866 } else { 2867 wol->supported = wol->wolopts = 0; 2868 } 2869 } 2870 2871 static int 2872 fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2873 { 2874 struct fec_enet_private *fep = netdev_priv(ndev); 2875 2876 if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET)) 2877 return -EINVAL; 2878 2879 if (wol->wolopts & ~WAKE_MAGIC) 2880 return -EINVAL; 2881 2882 device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC); 2883 if (device_may_wakeup(&ndev->dev)) { 2884 fep->wol_flag |= FEC_WOL_FLAG_ENABLE; 2885 if (fep->wake_irq > 0) 2886 enable_irq_wake(fep->wake_irq); 2887 } else { 2888 fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE); 2889 if (fep->wake_irq > 0) 2890 disable_irq_wake(fep->wake_irq); 2891 } 2892 2893 return 0; 2894 } 2895 2896 static const struct ethtool_ops fec_enet_ethtool_ops = { 2897 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 2898 ETHTOOL_COALESCE_MAX_FRAMES, 2899 .get_drvinfo = fec_enet_get_drvinfo, 2900 .get_regs_len = fec_enet_get_regs_len, 2901 .get_regs = fec_enet_get_regs, 2902 .nway_reset = phy_ethtool_nway_reset, 2903 .get_link = ethtool_op_get_link, 2904 .get_coalesce = fec_enet_get_coalesce, 2905 .set_coalesce = fec_enet_set_coalesce, 2906 #ifndef CONFIG_M5272 2907 .get_pauseparam = fec_enet_get_pauseparam, 2908 .set_pauseparam = fec_enet_set_pauseparam, 2909 .get_strings = fec_enet_get_strings, 2910 .get_ethtool_stats = fec_enet_get_ethtool_stats, 2911 .get_sset_count = fec_enet_get_sset_count, 2912 #endif 2913 .get_ts_info = fec_enet_get_ts_info, 2914 .get_tunable = fec_enet_get_tunable, 2915 .set_tunable = fec_enet_set_tunable, 2916 .get_wol = fec_enet_get_wol, 2917 .set_wol = fec_enet_set_wol, 2918 .get_eee = fec_enet_get_eee, 2919 .set_eee = fec_enet_set_eee, 2920 .get_link_ksettings = phy_ethtool_get_link_ksettings, 2921 .set_link_ksettings = phy_ethtool_set_link_ksettings, 2922 .self_test = net_selftest, 2923 }; 2924 2925 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) 2926 { 2927 struct fec_enet_private *fep = netdev_priv(ndev); 2928 struct phy_device *phydev = ndev->phydev; 2929 2930 if (!netif_running(ndev)) 2931 return -EINVAL; 2932 2933 if (!phydev) 2934 return -ENODEV; 2935 2936 if (fep->bufdesc_ex) { 2937 bool use_fec_hwts = !phy_has_hwtstamp(phydev); 2938 2939 if (cmd == SIOCSHWTSTAMP) { 2940 if (use_fec_hwts) 2941 return fec_ptp_set(ndev, rq); 2942 fec_ptp_disable_hwts(ndev); 2943 } else if (cmd == SIOCGHWTSTAMP) { 2944 if (use_fec_hwts) 2945 return fec_ptp_get(ndev, rq); 2946 } 2947 } 2948 2949 return phy_mii_ioctl(phydev, rq, cmd); 2950 } 2951 2952 static void fec_enet_free_buffers(struct net_device *ndev) 2953 { 2954 struct fec_enet_private *fep = netdev_priv(ndev); 2955 unsigned int i; 2956 struct sk_buff *skb; 2957 struct bufdesc *bdp; 2958 struct fec_enet_priv_tx_q *txq; 2959 struct fec_enet_priv_rx_q *rxq; 2960 unsigned int q; 2961 2962 for (q = 0; q < fep->num_rx_queues; q++) { 2963 rxq = fep->rx_queue[q]; 2964 bdp = rxq->bd.base; 2965 for (i = 0; i < rxq->bd.ring_size; i++) { 2966 skb = rxq->rx_skbuff[i]; 2967 rxq->rx_skbuff[i] = NULL; 2968 if (skb) { 2969 dma_unmap_single(&fep->pdev->dev, 2970 fec32_to_cpu(bdp->cbd_bufaddr), 2971 FEC_ENET_RX_FRSIZE - fep->rx_align, 2972 DMA_FROM_DEVICE); 2973 dev_kfree_skb(skb); 2974 } 2975 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 2976 } 2977 } 2978 2979 for (q = 0; q < fep->num_tx_queues; q++) { 2980 txq = fep->tx_queue[q]; 2981 for (i = 0; i < txq->bd.ring_size; i++) { 2982 kfree(txq->tx_bounce[i]); 2983 txq->tx_bounce[i] = NULL; 2984 skb = txq->tx_skbuff[i]; 2985 txq->tx_skbuff[i] = NULL; 2986 dev_kfree_skb(skb); 2987 } 2988 } 2989 } 2990 2991 static void fec_enet_free_queue(struct net_device *ndev) 2992 { 2993 struct fec_enet_private *fep = netdev_priv(ndev); 2994 int i; 2995 struct fec_enet_priv_tx_q *txq; 2996 2997 for (i = 0; i < fep->num_tx_queues; i++) 2998 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) { 2999 txq = fep->tx_queue[i]; 3000 dma_free_coherent(&fep->pdev->dev, 3001 txq->bd.ring_size * TSO_HEADER_SIZE, 3002 txq->tso_hdrs, 3003 txq->tso_hdrs_dma); 3004 } 3005 3006 for (i = 0; i < fep->num_rx_queues; i++) 3007 kfree(fep->rx_queue[i]); 3008 for (i = 0; i < fep->num_tx_queues; i++) 3009 kfree(fep->tx_queue[i]); 3010 } 3011 3012 static int fec_enet_alloc_queue(struct net_device *ndev) 3013 { 3014 struct fec_enet_private *fep = netdev_priv(ndev); 3015 int i; 3016 int ret = 0; 3017 struct fec_enet_priv_tx_q *txq; 3018 3019 for (i = 0; i < fep->num_tx_queues; i++) { 3020 txq = kzalloc(sizeof(*txq), GFP_KERNEL); 3021 if (!txq) { 3022 ret = -ENOMEM; 3023 goto alloc_failed; 3024 } 3025 3026 fep->tx_queue[i] = txq; 3027 txq->bd.ring_size = TX_RING_SIZE; 3028 fep->total_tx_ring_size += fep->tx_queue[i]->bd.ring_size; 3029 3030 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS; 3031 txq->tx_wake_threshold = 3032 (txq->bd.ring_size - txq->tx_stop_threshold) / 2; 3033 3034 txq->tso_hdrs = dma_alloc_coherent(&fep->pdev->dev, 3035 txq->bd.ring_size * TSO_HEADER_SIZE, 3036 &txq->tso_hdrs_dma, 3037 GFP_KERNEL); 3038 if (!txq->tso_hdrs) { 3039 ret = -ENOMEM; 3040 goto alloc_failed; 3041 } 3042 } 3043 3044 for (i = 0; i < fep->num_rx_queues; i++) { 3045 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]), 3046 GFP_KERNEL); 3047 if (!fep->rx_queue[i]) { 3048 ret = -ENOMEM; 3049 goto alloc_failed; 3050 } 3051 3052 fep->rx_queue[i]->bd.ring_size = RX_RING_SIZE; 3053 fep->total_rx_ring_size += fep->rx_queue[i]->bd.ring_size; 3054 } 3055 return ret; 3056 3057 alloc_failed: 3058 fec_enet_free_queue(ndev); 3059 return ret; 3060 } 3061 3062 static int 3063 fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue) 3064 { 3065 struct fec_enet_private *fep = netdev_priv(ndev); 3066 unsigned int i; 3067 struct sk_buff *skb; 3068 struct bufdesc *bdp; 3069 struct fec_enet_priv_rx_q *rxq; 3070 3071 rxq = fep->rx_queue[queue]; 3072 bdp = rxq->bd.base; 3073 for (i = 0; i < rxq->bd.ring_size; i++) { 3074 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE); 3075 if (!skb) 3076 goto err_alloc; 3077 3078 if (fec_enet_new_rxbdp(ndev, bdp, skb)) { 3079 dev_kfree_skb(skb); 3080 goto err_alloc; 3081 } 3082 3083 rxq->rx_skbuff[i] = skb; 3084 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); 3085 3086 if (fep->bufdesc_ex) { 3087 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 3088 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); 3089 } 3090 3091 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 3092 } 3093 3094 /* Set the last buffer to wrap. */ 3095 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); 3096 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 3097 return 0; 3098 3099 err_alloc: 3100 fec_enet_free_buffers(ndev); 3101 return -ENOMEM; 3102 } 3103 3104 static int 3105 fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue) 3106 { 3107 struct fec_enet_private *fep = netdev_priv(ndev); 3108 unsigned int i; 3109 struct bufdesc *bdp; 3110 struct fec_enet_priv_tx_q *txq; 3111 3112 txq = fep->tx_queue[queue]; 3113 bdp = txq->bd.base; 3114 for (i = 0; i < txq->bd.ring_size; i++) { 3115 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); 3116 if (!txq->tx_bounce[i]) 3117 goto err_alloc; 3118 3119 bdp->cbd_sc = cpu_to_fec16(0); 3120 bdp->cbd_bufaddr = cpu_to_fec32(0); 3121 3122 if (fep->bufdesc_ex) { 3123 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 3124 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_TX_INT); 3125 } 3126 3127 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 3128 } 3129 3130 /* Set the last buffer to wrap. */ 3131 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); 3132 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 3133 3134 return 0; 3135 3136 err_alloc: 3137 fec_enet_free_buffers(ndev); 3138 return -ENOMEM; 3139 } 3140 3141 static int fec_enet_alloc_buffers(struct net_device *ndev) 3142 { 3143 struct fec_enet_private *fep = netdev_priv(ndev); 3144 unsigned int i; 3145 3146 for (i = 0; i < fep->num_rx_queues; i++) 3147 if (fec_enet_alloc_rxq_buffers(ndev, i)) 3148 return -ENOMEM; 3149 3150 for (i = 0; i < fep->num_tx_queues; i++) 3151 if (fec_enet_alloc_txq_buffers(ndev, i)) 3152 return -ENOMEM; 3153 return 0; 3154 } 3155 3156 static int 3157 fec_enet_open(struct net_device *ndev) 3158 { 3159 struct fec_enet_private *fep = netdev_priv(ndev); 3160 int ret; 3161 bool reset_again; 3162 3163 ret = pm_runtime_resume_and_get(&fep->pdev->dev); 3164 if (ret < 0) 3165 return ret; 3166 3167 pinctrl_pm_select_default_state(&fep->pdev->dev); 3168 ret = fec_enet_clk_enable(ndev, true); 3169 if (ret) 3170 goto clk_enable; 3171 3172 /* During the first fec_enet_open call the PHY isn't probed at this 3173 * point. Therefore the phy_reset_after_clk_enable() call within 3174 * fec_enet_clk_enable() fails. As we need this reset in order to be 3175 * sure the PHY is working correctly we check if we need to reset again 3176 * later when the PHY is probed 3177 */ 3178 if (ndev->phydev && ndev->phydev->drv) 3179 reset_again = false; 3180 else 3181 reset_again = true; 3182 3183 /* I should reset the ring buffers here, but I don't yet know 3184 * a simple way to do that. 3185 */ 3186 3187 ret = fec_enet_alloc_buffers(ndev); 3188 if (ret) 3189 goto err_enet_alloc; 3190 3191 /* Init MAC prior to mii bus probe */ 3192 fec_restart(ndev); 3193 3194 /* Call phy_reset_after_clk_enable() again if it failed during 3195 * phy_reset_after_clk_enable() before because the PHY wasn't probed. 3196 */ 3197 if (reset_again) 3198 fec_enet_phy_reset_after_clk_enable(ndev); 3199 3200 /* Probe and connect to PHY when open the interface */ 3201 ret = fec_enet_mii_probe(ndev); 3202 if (ret) 3203 goto err_enet_mii_probe; 3204 3205 if (fep->quirks & FEC_QUIRK_ERR006687) 3206 imx6q_cpuidle_fec_irqs_used(); 3207 3208 napi_enable(&fep->napi); 3209 phy_start(ndev->phydev); 3210 netif_tx_start_all_queues(ndev); 3211 3212 device_set_wakeup_enable(&ndev->dev, fep->wol_flag & 3213 FEC_WOL_FLAG_ENABLE); 3214 3215 return 0; 3216 3217 err_enet_mii_probe: 3218 fec_enet_free_buffers(ndev); 3219 err_enet_alloc: 3220 fec_enet_clk_enable(ndev, false); 3221 clk_enable: 3222 pm_runtime_mark_last_busy(&fep->pdev->dev); 3223 pm_runtime_put_autosuspend(&fep->pdev->dev); 3224 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3225 return ret; 3226 } 3227 3228 static int 3229 fec_enet_close(struct net_device *ndev) 3230 { 3231 struct fec_enet_private *fep = netdev_priv(ndev); 3232 3233 phy_stop(ndev->phydev); 3234 3235 if (netif_device_present(ndev)) { 3236 napi_disable(&fep->napi); 3237 netif_tx_disable(ndev); 3238 fec_stop(ndev); 3239 } 3240 3241 phy_disconnect(ndev->phydev); 3242 3243 if (fep->quirks & FEC_QUIRK_ERR006687) 3244 imx6q_cpuidle_fec_irqs_unused(); 3245 3246 fec_enet_update_ethtool_stats(ndev); 3247 3248 fec_enet_clk_enable(ndev, false); 3249 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3250 pm_runtime_mark_last_busy(&fep->pdev->dev); 3251 pm_runtime_put_autosuspend(&fep->pdev->dev); 3252 3253 fec_enet_free_buffers(ndev); 3254 3255 return 0; 3256 } 3257 3258 /* Set or clear the multicast filter for this adaptor. 3259 * Skeleton taken from sunlance driver. 3260 * The CPM Ethernet implementation allows Multicast as well as individual 3261 * MAC address filtering. Some of the drivers check to make sure it is 3262 * a group multicast address, and discard those that are not. I guess I 3263 * will do the same for now, but just remove the test if you want 3264 * individual filtering as well (do the upper net layers want or support 3265 * this kind of feature?). 3266 */ 3267 3268 #define FEC_HASH_BITS 6 /* #bits in hash */ 3269 3270 static void set_multicast_list(struct net_device *ndev) 3271 { 3272 struct fec_enet_private *fep = netdev_priv(ndev); 3273 struct netdev_hw_addr *ha; 3274 unsigned int crc, tmp; 3275 unsigned char hash; 3276 unsigned int hash_high = 0, hash_low = 0; 3277 3278 if (ndev->flags & IFF_PROMISC) { 3279 tmp = readl(fep->hwp + FEC_R_CNTRL); 3280 tmp |= 0x8; 3281 writel(tmp, fep->hwp + FEC_R_CNTRL); 3282 return; 3283 } 3284 3285 tmp = readl(fep->hwp + FEC_R_CNTRL); 3286 tmp &= ~0x8; 3287 writel(tmp, fep->hwp + FEC_R_CNTRL); 3288 3289 if (ndev->flags & IFF_ALLMULTI) { 3290 /* Catch all multicast addresses, so set the 3291 * filter to all 1's 3292 */ 3293 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 3294 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 3295 3296 return; 3297 } 3298 3299 /* Add the addresses in hash register */ 3300 netdev_for_each_mc_addr(ha, ndev) { 3301 /* calculate crc32 value of mac address */ 3302 crc = ether_crc_le(ndev->addr_len, ha->addr); 3303 3304 /* only upper 6 bits (FEC_HASH_BITS) are used 3305 * which point to specific bit in the hash registers 3306 */ 3307 hash = (crc >> (32 - FEC_HASH_BITS)) & 0x3f; 3308 3309 if (hash > 31) 3310 hash_high |= 1 << (hash - 32); 3311 else 3312 hash_low |= 1 << hash; 3313 } 3314 3315 writel(hash_high, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 3316 writel(hash_low, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 3317 } 3318 3319 /* Set a MAC change in hardware. */ 3320 static int 3321 fec_set_mac_address(struct net_device *ndev, void *p) 3322 { 3323 struct fec_enet_private *fep = netdev_priv(ndev); 3324 struct sockaddr *addr = p; 3325 3326 if (addr) { 3327 if (!is_valid_ether_addr(addr->sa_data)) 3328 return -EADDRNOTAVAIL; 3329 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len); 3330 } 3331 3332 /* Add netif status check here to avoid system hang in below case: 3333 * ifconfig ethx down; ifconfig ethx hw ether xx:xx:xx:xx:xx:xx; 3334 * After ethx down, fec all clocks are gated off and then register 3335 * access causes system hang. 3336 */ 3337 if (!netif_running(ndev)) 3338 return 0; 3339 3340 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) | 3341 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24), 3342 fep->hwp + FEC_ADDR_LOW); 3343 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24), 3344 fep->hwp + FEC_ADDR_HIGH); 3345 return 0; 3346 } 3347 3348 #ifdef CONFIG_NET_POLL_CONTROLLER 3349 /** 3350 * fec_poll_controller - FEC Poll controller function 3351 * @dev: The FEC network adapter 3352 * 3353 * Polled functionality used by netconsole and others in non interrupt mode 3354 * 3355 */ 3356 static void fec_poll_controller(struct net_device *dev) 3357 { 3358 int i; 3359 struct fec_enet_private *fep = netdev_priv(dev); 3360 3361 for (i = 0; i < FEC_IRQ_NUM; i++) { 3362 if (fep->irq[i] > 0) { 3363 disable_irq(fep->irq[i]); 3364 fec_enet_interrupt(fep->irq[i], dev); 3365 enable_irq(fep->irq[i]); 3366 } 3367 } 3368 } 3369 #endif 3370 3371 static inline void fec_enet_set_netdev_features(struct net_device *netdev, 3372 netdev_features_t features) 3373 { 3374 struct fec_enet_private *fep = netdev_priv(netdev); 3375 netdev_features_t changed = features ^ netdev->features; 3376 3377 netdev->features = features; 3378 3379 /* Receive checksum has been changed */ 3380 if (changed & NETIF_F_RXCSUM) { 3381 if (features & NETIF_F_RXCSUM) 3382 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 3383 else 3384 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED; 3385 } 3386 } 3387 3388 static int fec_set_features(struct net_device *netdev, 3389 netdev_features_t features) 3390 { 3391 struct fec_enet_private *fep = netdev_priv(netdev); 3392 netdev_features_t changed = features ^ netdev->features; 3393 3394 if (netif_running(netdev) && changed & NETIF_F_RXCSUM) { 3395 napi_disable(&fep->napi); 3396 netif_tx_lock_bh(netdev); 3397 fec_stop(netdev); 3398 fec_enet_set_netdev_features(netdev, features); 3399 fec_restart(netdev); 3400 netif_tx_wake_all_queues(netdev); 3401 netif_tx_unlock_bh(netdev); 3402 napi_enable(&fep->napi); 3403 } else { 3404 fec_enet_set_netdev_features(netdev, features); 3405 } 3406 3407 return 0; 3408 } 3409 3410 static u16 fec_enet_get_raw_vlan_tci(struct sk_buff *skb) 3411 { 3412 struct vlan_ethhdr *vhdr; 3413 unsigned short vlan_TCI = 0; 3414 3415 if (skb->protocol == htons(ETH_P_ALL)) { 3416 vhdr = (struct vlan_ethhdr *)(skb->data); 3417 vlan_TCI = ntohs(vhdr->h_vlan_TCI); 3418 } 3419 3420 return vlan_TCI; 3421 } 3422 3423 static u16 fec_enet_select_queue(struct net_device *ndev, struct sk_buff *skb, 3424 struct net_device *sb_dev) 3425 { 3426 struct fec_enet_private *fep = netdev_priv(ndev); 3427 u16 vlan_tag; 3428 3429 if (!(fep->quirks & FEC_QUIRK_HAS_AVB)) 3430 return netdev_pick_tx(ndev, skb, NULL); 3431 3432 vlan_tag = fec_enet_get_raw_vlan_tci(skb); 3433 if (!vlan_tag) 3434 return vlan_tag; 3435 3436 return fec_enet_vlan_pri_to_queue[vlan_tag >> 13]; 3437 } 3438 3439 static const struct net_device_ops fec_netdev_ops = { 3440 .ndo_open = fec_enet_open, 3441 .ndo_stop = fec_enet_close, 3442 .ndo_start_xmit = fec_enet_start_xmit, 3443 .ndo_select_queue = fec_enet_select_queue, 3444 .ndo_set_rx_mode = set_multicast_list, 3445 .ndo_validate_addr = eth_validate_addr, 3446 .ndo_tx_timeout = fec_timeout, 3447 .ndo_set_mac_address = fec_set_mac_address, 3448 .ndo_eth_ioctl = fec_enet_ioctl, 3449 #ifdef CONFIG_NET_POLL_CONTROLLER 3450 .ndo_poll_controller = fec_poll_controller, 3451 #endif 3452 .ndo_set_features = fec_set_features, 3453 }; 3454 3455 static const unsigned short offset_des_active_rxq[] = { 3456 FEC_R_DES_ACTIVE_0, FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2 3457 }; 3458 3459 static const unsigned short offset_des_active_txq[] = { 3460 FEC_X_DES_ACTIVE_0, FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2 3461 }; 3462 3463 /* 3464 * XXX: We need to clean up on failure exits here. 3465 * 3466 */ 3467 static int fec_enet_init(struct net_device *ndev) 3468 { 3469 struct fec_enet_private *fep = netdev_priv(ndev); 3470 struct bufdesc *cbd_base; 3471 dma_addr_t bd_dma; 3472 int bd_size; 3473 unsigned int i; 3474 unsigned dsize = fep->bufdesc_ex ? sizeof(struct bufdesc_ex) : 3475 sizeof(struct bufdesc); 3476 unsigned dsize_log2 = __fls(dsize); 3477 int ret; 3478 3479 WARN_ON(dsize != (1 << dsize_log2)); 3480 #if defined(CONFIG_ARM) || defined(CONFIG_ARM64) 3481 fep->rx_align = 0xf; 3482 fep->tx_align = 0xf; 3483 #else 3484 fep->rx_align = 0x3; 3485 fep->tx_align = 0x3; 3486 #endif 3487 3488 /* Check mask of the streaming and coherent API */ 3489 ret = dma_set_mask_and_coherent(&fep->pdev->dev, DMA_BIT_MASK(32)); 3490 if (ret < 0) { 3491 dev_warn(&fep->pdev->dev, "No suitable DMA available\n"); 3492 return ret; 3493 } 3494 3495 ret = fec_enet_alloc_queue(ndev); 3496 if (ret) 3497 return ret; 3498 3499 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) * dsize; 3500 3501 /* Allocate memory for buffer descriptors. */ 3502 cbd_base = dmam_alloc_coherent(&fep->pdev->dev, bd_size, &bd_dma, 3503 GFP_KERNEL); 3504 if (!cbd_base) { 3505 ret = -ENOMEM; 3506 goto free_queue_mem; 3507 } 3508 3509 /* Get the Ethernet address */ 3510 ret = fec_get_mac(ndev); 3511 if (ret) 3512 goto free_queue_mem; 3513 3514 /* make sure MAC we just acquired is programmed into the hw */ 3515 fec_set_mac_address(ndev, NULL); 3516 3517 /* Set receive and transmit descriptor base. */ 3518 for (i = 0; i < fep->num_rx_queues; i++) { 3519 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[i]; 3520 unsigned size = dsize * rxq->bd.ring_size; 3521 3522 rxq->bd.qid = i; 3523 rxq->bd.base = cbd_base; 3524 rxq->bd.cur = cbd_base; 3525 rxq->bd.dma = bd_dma; 3526 rxq->bd.dsize = dsize; 3527 rxq->bd.dsize_log2 = dsize_log2; 3528 rxq->bd.reg_desc_active = fep->hwp + offset_des_active_rxq[i]; 3529 bd_dma += size; 3530 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size); 3531 rxq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); 3532 } 3533 3534 for (i = 0; i < fep->num_tx_queues; i++) { 3535 struct fec_enet_priv_tx_q *txq = fep->tx_queue[i]; 3536 unsigned size = dsize * txq->bd.ring_size; 3537 3538 txq->bd.qid = i; 3539 txq->bd.base = cbd_base; 3540 txq->bd.cur = cbd_base; 3541 txq->bd.dma = bd_dma; 3542 txq->bd.dsize = dsize; 3543 txq->bd.dsize_log2 = dsize_log2; 3544 txq->bd.reg_desc_active = fep->hwp + offset_des_active_txq[i]; 3545 bd_dma += size; 3546 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size); 3547 txq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); 3548 } 3549 3550 3551 /* The FEC Ethernet specific entries in the device structure */ 3552 ndev->watchdog_timeo = TX_TIMEOUT; 3553 ndev->netdev_ops = &fec_netdev_ops; 3554 ndev->ethtool_ops = &fec_enet_ethtool_ops; 3555 3556 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK); 3557 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT); 3558 3559 if (fep->quirks & FEC_QUIRK_HAS_VLAN) 3560 /* enable hw VLAN support */ 3561 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; 3562 3563 if (fep->quirks & FEC_QUIRK_HAS_CSUM) { 3564 ndev->gso_max_segs = FEC_MAX_TSO_SEGS; 3565 3566 /* enable hw accelerator */ 3567 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM 3568 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO); 3569 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 3570 } 3571 3572 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) { 3573 fep->tx_align = 0; 3574 fep->rx_align = 0x3f; 3575 } 3576 3577 ndev->hw_features = ndev->features; 3578 3579 fec_restart(ndev); 3580 3581 if (fep->quirks & FEC_QUIRK_MIB_CLEAR) 3582 fec_enet_clear_ethtool_stats(ndev); 3583 else 3584 fec_enet_update_ethtool_stats(ndev); 3585 3586 return 0; 3587 3588 free_queue_mem: 3589 fec_enet_free_queue(ndev); 3590 return ret; 3591 } 3592 3593 #ifdef CONFIG_OF 3594 static int fec_reset_phy(struct platform_device *pdev) 3595 { 3596 int err, phy_reset; 3597 bool active_high = false; 3598 int msec = 1, phy_post_delay = 0; 3599 struct device_node *np = pdev->dev.of_node; 3600 3601 if (!np) 3602 return 0; 3603 3604 err = of_property_read_u32(np, "phy-reset-duration", &msec); 3605 /* A sane reset duration should not be longer than 1s */ 3606 if (!err && msec > 1000) 3607 msec = 1; 3608 3609 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0); 3610 if (phy_reset == -EPROBE_DEFER) 3611 return phy_reset; 3612 else if (!gpio_is_valid(phy_reset)) 3613 return 0; 3614 3615 err = of_property_read_u32(np, "phy-reset-post-delay", &phy_post_delay); 3616 /* valid reset duration should be less than 1s */ 3617 if (!err && phy_post_delay > 1000) 3618 return -EINVAL; 3619 3620 active_high = of_property_read_bool(np, "phy-reset-active-high"); 3621 3622 err = devm_gpio_request_one(&pdev->dev, phy_reset, 3623 active_high ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW, 3624 "phy-reset"); 3625 if (err) { 3626 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err); 3627 return err; 3628 } 3629 3630 if (msec > 20) 3631 msleep(msec); 3632 else 3633 usleep_range(msec * 1000, msec * 1000 + 1000); 3634 3635 gpio_set_value_cansleep(phy_reset, !active_high); 3636 3637 if (!phy_post_delay) 3638 return 0; 3639 3640 if (phy_post_delay > 20) 3641 msleep(phy_post_delay); 3642 else 3643 usleep_range(phy_post_delay * 1000, 3644 phy_post_delay * 1000 + 1000); 3645 3646 return 0; 3647 } 3648 #else /* CONFIG_OF */ 3649 static int fec_reset_phy(struct platform_device *pdev) 3650 { 3651 /* 3652 * In case of platform probe, the reset has been done 3653 * by machine code. 3654 */ 3655 return 0; 3656 } 3657 #endif /* CONFIG_OF */ 3658 3659 static void 3660 fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx) 3661 { 3662 struct device_node *np = pdev->dev.of_node; 3663 3664 *num_tx = *num_rx = 1; 3665 3666 if (!np || !of_device_is_available(np)) 3667 return; 3668 3669 /* parse the num of tx and rx queues */ 3670 of_property_read_u32(np, "fsl,num-tx-queues", num_tx); 3671 3672 of_property_read_u32(np, "fsl,num-rx-queues", num_rx); 3673 3674 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) { 3675 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n", 3676 *num_tx); 3677 *num_tx = 1; 3678 return; 3679 } 3680 3681 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) { 3682 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n", 3683 *num_rx); 3684 *num_rx = 1; 3685 return; 3686 } 3687 3688 } 3689 3690 static int fec_enet_get_irq_cnt(struct platform_device *pdev) 3691 { 3692 int irq_cnt = platform_irq_count(pdev); 3693 3694 if (irq_cnt > FEC_IRQ_NUM) 3695 irq_cnt = FEC_IRQ_NUM; /* last for pps */ 3696 else if (irq_cnt == 2) 3697 irq_cnt = 1; /* last for pps */ 3698 else if (irq_cnt <= 0) 3699 irq_cnt = 1; /* At least 1 irq is needed */ 3700 return irq_cnt; 3701 } 3702 3703 static void fec_enet_get_wakeup_irq(struct platform_device *pdev) 3704 { 3705 struct net_device *ndev = platform_get_drvdata(pdev); 3706 struct fec_enet_private *fep = netdev_priv(ndev); 3707 3708 if (fep->quirks & FEC_QUIRK_WAKEUP_FROM_INT2) 3709 fep->wake_irq = fep->irq[2]; 3710 else 3711 fep->wake_irq = fep->irq[0]; 3712 } 3713 3714 static int fec_enet_init_stop_mode(struct fec_enet_private *fep, 3715 struct device_node *np) 3716 { 3717 struct device_node *gpr_np; 3718 u32 out_val[3]; 3719 int ret = 0; 3720 3721 gpr_np = of_parse_phandle(np, "fsl,stop-mode", 0); 3722 if (!gpr_np) 3723 return 0; 3724 3725 ret = of_property_read_u32_array(np, "fsl,stop-mode", out_val, 3726 ARRAY_SIZE(out_val)); 3727 if (ret) { 3728 dev_dbg(&fep->pdev->dev, "no stop mode property\n"); 3729 return ret; 3730 } 3731 3732 fep->stop_gpr.gpr = syscon_node_to_regmap(gpr_np); 3733 if (IS_ERR(fep->stop_gpr.gpr)) { 3734 dev_err(&fep->pdev->dev, "could not find gpr regmap\n"); 3735 ret = PTR_ERR(fep->stop_gpr.gpr); 3736 fep->stop_gpr.gpr = NULL; 3737 goto out; 3738 } 3739 3740 fep->stop_gpr.reg = out_val[1]; 3741 fep->stop_gpr.bit = out_val[2]; 3742 3743 out: 3744 of_node_put(gpr_np); 3745 3746 return ret; 3747 } 3748 3749 static int 3750 fec_probe(struct platform_device *pdev) 3751 { 3752 struct fec_enet_private *fep; 3753 struct fec_platform_data *pdata; 3754 phy_interface_t interface; 3755 struct net_device *ndev; 3756 int i, irq, ret = 0; 3757 const struct of_device_id *of_id; 3758 static int dev_id; 3759 struct device_node *np = pdev->dev.of_node, *phy_node; 3760 int num_tx_qs; 3761 int num_rx_qs; 3762 char irq_name[8]; 3763 int irq_cnt; 3764 struct fec_devinfo *dev_info; 3765 3766 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs); 3767 3768 /* Init network device */ 3769 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private) + 3770 FEC_STATS_SIZE, num_tx_qs, num_rx_qs); 3771 if (!ndev) 3772 return -ENOMEM; 3773 3774 SET_NETDEV_DEV(ndev, &pdev->dev); 3775 3776 /* setup board info structure */ 3777 fep = netdev_priv(ndev); 3778 3779 of_id = of_match_device(fec_dt_ids, &pdev->dev); 3780 if (of_id) 3781 pdev->id_entry = of_id->data; 3782 dev_info = (struct fec_devinfo *)pdev->id_entry->driver_data; 3783 if (dev_info) 3784 fep->quirks = dev_info->quirks; 3785 3786 fep->netdev = ndev; 3787 fep->num_rx_queues = num_rx_qs; 3788 fep->num_tx_queues = num_tx_qs; 3789 3790 #if !defined(CONFIG_M5272) 3791 /* default enable pause frame auto negotiation */ 3792 if (fep->quirks & FEC_QUIRK_HAS_GBIT) 3793 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG; 3794 #endif 3795 3796 /* Select default pin state */ 3797 pinctrl_pm_select_default_state(&pdev->dev); 3798 3799 fep->hwp = devm_platform_ioremap_resource(pdev, 0); 3800 if (IS_ERR(fep->hwp)) { 3801 ret = PTR_ERR(fep->hwp); 3802 goto failed_ioremap; 3803 } 3804 3805 fep->pdev = pdev; 3806 fep->dev_id = dev_id++; 3807 3808 platform_set_drvdata(pdev, ndev); 3809 3810 if ((of_machine_is_compatible("fsl,imx6q") || 3811 of_machine_is_compatible("fsl,imx6dl")) && 3812 !of_property_read_bool(np, "fsl,err006687-workaround-present")) 3813 fep->quirks |= FEC_QUIRK_ERR006687; 3814 3815 if (of_get_property(np, "fsl,magic-packet", NULL)) 3816 fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET; 3817 3818 ret = fec_enet_init_stop_mode(fep, np); 3819 if (ret) 3820 goto failed_stop_mode; 3821 3822 phy_node = of_parse_phandle(np, "phy-handle", 0); 3823 if (!phy_node && of_phy_is_fixed_link(np)) { 3824 ret = of_phy_register_fixed_link(np); 3825 if (ret < 0) { 3826 dev_err(&pdev->dev, 3827 "broken fixed-link specification\n"); 3828 goto failed_phy; 3829 } 3830 phy_node = of_node_get(np); 3831 } 3832 fep->phy_node = phy_node; 3833 3834 ret = of_get_phy_mode(pdev->dev.of_node, &interface); 3835 if (ret) { 3836 pdata = dev_get_platdata(&pdev->dev); 3837 if (pdata) 3838 fep->phy_interface = pdata->phy; 3839 else 3840 fep->phy_interface = PHY_INTERFACE_MODE_MII; 3841 } else { 3842 fep->phy_interface = interface; 3843 } 3844 3845 ret = fec_enet_parse_rgmii_delay(fep, np); 3846 if (ret) 3847 goto failed_rgmii_delay; 3848 3849 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 3850 if (IS_ERR(fep->clk_ipg)) { 3851 ret = PTR_ERR(fep->clk_ipg); 3852 goto failed_clk; 3853 } 3854 3855 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 3856 if (IS_ERR(fep->clk_ahb)) { 3857 ret = PTR_ERR(fep->clk_ahb); 3858 goto failed_clk; 3859 } 3860 3861 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb); 3862 3863 /* enet_out is optional, depends on board */ 3864 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out"); 3865 if (IS_ERR(fep->clk_enet_out)) 3866 fep->clk_enet_out = NULL; 3867 3868 fep->ptp_clk_on = false; 3869 mutex_init(&fep->ptp_clk_mutex); 3870 3871 /* clk_ref is optional, depends on board */ 3872 fep->clk_ref = devm_clk_get(&pdev->dev, "enet_clk_ref"); 3873 if (IS_ERR(fep->clk_ref)) 3874 fep->clk_ref = NULL; 3875 fep->clk_ref_rate = clk_get_rate(fep->clk_ref); 3876 3877 /* clk_2x_txclk is optional, depends on board */ 3878 if (fep->rgmii_txc_dly || fep->rgmii_rxc_dly) { 3879 fep->clk_2x_txclk = devm_clk_get(&pdev->dev, "enet_2x_txclk"); 3880 if (IS_ERR(fep->clk_2x_txclk)) 3881 fep->clk_2x_txclk = NULL; 3882 } 3883 3884 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX; 3885 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp"); 3886 if (IS_ERR(fep->clk_ptp)) { 3887 fep->clk_ptp = NULL; 3888 fep->bufdesc_ex = false; 3889 } 3890 3891 ret = fec_enet_clk_enable(ndev, true); 3892 if (ret) 3893 goto failed_clk; 3894 3895 ret = clk_prepare_enable(fep->clk_ipg); 3896 if (ret) 3897 goto failed_clk_ipg; 3898 ret = clk_prepare_enable(fep->clk_ahb); 3899 if (ret) 3900 goto failed_clk_ahb; 3901 3902 fep->reg_phy = devm_regulator_get_optional(&pdev->dev, "phy"); 3903 if (!IS_ERR(fep->reg_phy)) { 3904 ret = regulator_enable(fep->reg_phy); 3905 if (ret) { 3906 dev_err(&pdev->dev, 3907 "Failed to enable phy regulator: %d\n", ret); 3908 goto failed_regulator; 3909 } 3910 } else { 3911 if (PTR_ERR(fep->reg_phy) == -EPROBE_DEFER) { 3912 ret = -EPROBE_DEFER; 3913 goto failed_regulator; 3914 } 3915 fep->reg_phy = NULL; 3916 } 3917 3918 pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT); 3919 pm_runtime_use_autosuspend(&pdev->dev); 3920 pm_runtime_get_noresume(&pdev->dev); 3921 pm_runtime_set_active(&pdev->dev); 3922 pm_runtime_enable(&pdev->dev); 3923 3924 ret = fec_reset_phy(pdev); 3925 if (ret) 3926 goto failed_reset; 3927 3928 irq_cnt = fec_enet_get_irq_cnt(pdev); 3929 if (fep->bufdesc_ex) 3930 fec_ptp_init(pdev, irq_cnt); 3931 3932 ret = fec_enet_init(ndev); 3933 if (ret) 3934 goto failed_init; 3935 3936 for (i = 0; i < irq_cnt; i++) { 3937 snprintf(irq_name, sizeof(irq_name), "int%d", i); 3938 irq = platform_get_irq_byname_optional(pdev, irq_name); 3939 if (irq < 0) 3940 irq = platform_get_irq(pdev, i); 3941 if (irq < 0) { 3942 ret = irq; 3943 goto failed_irq; 3944 } 3945 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt, 3946 0, pdev->name, ndev); 3947 if (ret) 3948 goto failed_irq; 3949 3950 fep->irq[i] = irq; 3951 } 3952 3953 /* Decide which interrupt line is wakeup capable */ 3954 fec_enet_get_wakeup_irq(pdev); 3955 3956 ret = fec_enet_mii_init(pdev); 3957 if (ret) 3958 goto failed_mii_init; 3959 3960 /* Carrier starts down, phylib will bring it up */ 3961 netif_carrier_off(ndev); 3962 fec_enet_clk_enable(ndev, false); 3963 pinctrl_pm_select_sleep_state(&pdev->dev); 3964 3965 ndev->max_mtu = PKT_MAXBUF_SIZE - ETH_HLEN - ETH_FCS_LEN; 3966 3967 ret = register_netdev(ndev); 3968 if (ret) 3969 goto failed_register; 3970 3971 device_init_wakeup(&ndev->dev, fep->wol_flag & 3972 FEC_WOL_HAS_MAGIC_PACKET); 3973 3974 if (fep->bufdesc_ex && fep->ptp_clock) 3975 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id); 3976 3977 fep->rx_copybreak = COPYBREAK_DEFAULT; 3978 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work); 3979 3980 pm_runtime_mark_last_busy(&pdev->dev); 3981 pm_runtime_put_autosuspend(&pdev->dev); 3982 3983 return 0; 3984 3985 failed_register: 3986 fec_enet_mii_remove(fep); 3987 failed_mii_init: 3988 failed_irq: 3989 failed_init: 3990 fec_ptp_stop(pdev); 3991 failed_reset: 3992 pm_runtime_put_noidle(&pdev->dev); 3993 pm_runtime_disable(&pdev->dev); 3994 if (fep->reg_phy) 3995 regulator_disable(fep->reg_phy); 3996 failed_regulator: 3997 clk_disable_unprepare(fep->clk_ahb); 3998 failed_clk_ahb: 3999 clk_disable_unprepare(fep->clk_ipg); 4000 failed_clk_ipg: 4001 fec_enet_clk_enable(ndev, false); 4002 failed_clk: 4003 failed_rgmii_delay: 4004 if (of_phy_is_fixed_link(np)) 4005 of_phy_deregister_fixed_link(np); 4006 of_node_put(phy_node); 4007 failed_stop_mode: 4008 failed_phy: 4009 dev_id--; 4010 failed_ioremap: 4011 free_netdev(ndev); 4012 4013 return ret; 4014 } 4015 4016 static int 4017 fec_drv_remove(struct platform_device *pdev) 4018 { 4019 struct net_device *ndev = platform_get_drvdata(pdev); 4020 struct fec_enet_private *fep = netdev_priv(ndev); 4021 struct device_node *np = pdev->dev.of_node; 4022 int ret; 4023 4024 ret = pm_runtime_resume_and_get(&pdev->dev); 4025 if (ret < 0) 4026 return ret; 4027 4028 cancel_work_sync(&fep->tx_timeout_work); 4029 fec_ptp_stop(pdev); 4030 unregister_netdev(ndev); 4031 fec_enet_mii_remove(fep); 4032 if (fep->reg_phy) 4033 regulator_disable(fep->reg_phy); 4034 4035 if (of_phy_is_fixed_link(np)) 4036 of_phy_deregister_fixed_link(np); 4037 of_node_put(fep->phy_node); 4038 4039 clk_disable_unprepare(fep->clk_ahb); 4040 clk_disable_unprepare(fep->clk_ipg); 4041 pm_runtime_put_noidle(&pdev->dev); 4042 pm_runtime_disable(&pdev->dev); 4043 4044 free_netdev(ndev); 4045 return 0; 4046 } 4047 4048 static int __maybe_unused fec_suspend(struct device *dev) 4049 { 4050 struct net_device *ndev = dev_get_drvdata(dev); 4051 struct fec_enet_private *fep = netdev_priv(ndev); 4052 4053 rtnl_lock(); 4054 if (netif_running(ndev)) { 4055 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) 4056 fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON; 4057 phy_stop(ndev->phydev); 4058 napi_disable(&fep->napi); 4059 netif_tx_lock_bh(ndev); 4060 netif_device_detach(ndev); 4061 netif_tx_unlock_bh(ndev); 4062 fec_stop(ndev); 4063 fec_enet_clk_enable(ndev, false); 4064 if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) 4065 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 4066 } 4067 rtnl_unlock(); 4068 4069 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) 4070 regulator_disable(fep->reg_phy); 4071 4072 /* SOC supply clock to phy, when clock is disabled, phy link down 4073 * SOC control phy regulator, when regulator is disabled, phy link down 4074 */ 4075 if (fep->clk_enet_out || fep->reg_phy) 4076 fep->link = 0; 4077 4078 return 0; 4079 } 4080 4081 static int __maybe_unused fec_resume(struct device *dev) 4082 { 4083 struct net_device *ndev = dev_get_drvdata(dev); 4084 struct fec_enet_private *fep = netdev_priv(ndev); 4085 int ret; 4086 int val; 4087 4088 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) { 4089 ret = regulator_enable(fep->reg_phy); 4090 if (ret) 4091 return ret; 4092 } 4093 4094 rtnl_lock(); 4095 if (netif_running(ndev)) { 4096 ret = fec_enet_clk_enable(ndev, true); 4097 if (ret) { 4098 rtnl_unlock(); 4099 goto failed_clk; 4100 } 4101 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) { 4102 fec_enet_stop_mode(fep, false); 4103 4104 val = readl(fep->hwp + FEC_ECNTRL); 4105 val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP); 4106 writel(val, fep->hwp + FEC_ECNTRL); 4107 fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON; 4108 } else { 4109 pinctrl_pm_select_default_state(&fep->pdev->dev); 4110 } 4111 fec_restart(ndev); 4112 netif_tx_lock_bh(ndev); 4113 netif_device_attach(ndev); 4114 netif_tx_unlock_bh(ndev); 4115 napi_enable(&fep->napi); 4116 phy_init_hw(ndev->phydev); 4117 phy_start(ndev->phydev); 4118 } 4119 rtnl_unlock(); 4120 4121 return 0; 4122 4123 failed_clk: 4124 if (fep->reg_phy) 4125 regulator_disable(fep->reg_phy); 4126 return ret; 4127 } 4128 4129 static int __maybe_unused fec_runtime_suspend(struct device *dev) 4130 { 4131 struct net_device *ndev = dev_get_drvdata(dev); 4132 struct fec_enet_private *fep = netdev_priv(ndev); 4133 4134 clk_disable_unprepare(fep->clk_ahb); 4135 clk_disable_unprepare(fep->clk_ipg); 4136 4137 return 0; 4138 } 4139 4140 static int __maybe_unused fec_runtime_resume(struct device *dev) 4141 { 4142 struct net_device *ndev = dev_get_drvdata(dev); 4143 struct fec_enet_private *fep = netdev_priv(ndev); 4144 int ret; 4145 4146 ret = clk_prepare_enable(fep->clk_ahb); 4147 if (ret) 4148 return ret; 4149 ret = clk_prepare_enable(fep->clk_ipg); 4150 if (ret) 4151 goto failed_clk_ipg; 4152 4153 return 0; 4154 4155 failed_clk_ipg: 4156 clk_disable_unprepare(fep->clk_ahb); 4157 return ret; 4158 } 4159 4160 static const struct dev_pm_ops fec_pm_ops = { 4161 SET_SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume) 4162 SET_RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL) 4163 }; 4164 4165 static struct platform_driver fec_driver = { 4166 .driver = { 4167 .name = DRIVER_NAME, 4168 .pm = &fec_pm_ops, 4169 .of_match_table = fec_dt_ids, 4170 .suppress_bind_attrs = true, 4171 }, 4172 .id_table = fec_devtype, 4173 .probe = fec_probe, 4174 .remove = fec_drv_remove, 4175 }; 4176 4177 module_platform_driver(fec_driver); 4178 4179 MODULE_LICENSE("GPL"); 4180