1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. 4 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) 5 * 6 * Right now, I am very wasteful with the buffers. I allocate memory 7 * pages and then divide them into 2K frame buffers. This way I know I 8 * have buffers large enough to hold one frame within one buffer descriptor. 9 * Once I get this working, I will use 64 or 128 byte CPM buffers, which 10 * will be much more memory efficient and will easily handle lots of 11 * small packets. 12 * 13 * Much better multiple PHY support by Magnus Damm. 14 * Copyright (c) 2000 Ericsson Radio Systems AB. 15 * 16 * Support for FEC controller of ColdFire processors. 17 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) 18 * 19 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) 20 * Copyright (c) 2004-2006 Macq Electronique SA. 21 * 22 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. 23 */ 24 25 #include <linux/module.h> 26 #include <linux/kernel.h> 27 #include <linux/string.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/ptrace.h> 30 #include <linux/errno.h> 31 #include <linux/ioport.h> 32 #include <linux/slab.h> 33 #include <linux/interrupt.h> 34 #include <linux/delay.h> 35 #include <linux/netdevice.h> 36 #include <linux/etherdevice.h> 37 #include <linux/skbuff.h> 38 #include <linux/in.h> 39 #include <linux/ip.h> 40 #include <net/ip.h> 41 #include <net/tso.h> 42 #include <linux/tcp.h> 43 #include <linux/udp.h> 44 #include <linux/icmp.h> 45 #include <linux/spinlock.h> 46 #include <linux/workqueue.h> 47 #include <linux/bitops.h> 48 #include <linux/io.h> 49 #include <linux/irq.h> 50 #include <linux/clk.h> 51 #include <linux/crc32.h> 52 #include <linux/platform_device.h> 53 #include <linux/mdio.h> 54 #include <linux/phy.h> 55 #include <linux/fec.h> 56 #include <linux/of.h> 57 #include <linux/of_device.h> 58 #include <linux/of_gpio.h> 59 #include <linux/of_mdio.h> 60 #include <linux/of_net.h> 61 #include <linux/regulator/consumer.h> 62 #include <linux/if_vlan.h> 63 #include <linux/pinctrl/consumer.h> 64 #include <linux/prefetch.h> 65 #include <linux/mfd/syscon.h> 66 #include <linux/regmap.h> 67 #include <soc/imx/cpuidle.h> 68 69 #include <asm/cacheflush.h> 70 71 #include "fec.h" 72 73 static void set_multicast_list(struct net_device *ndev); 74 static void fec_enet_itr_coal_init(struct net_device *ndev); 75 76 #define DRIVER_NAME "fec" 77 78 #define FEC_ENET_GET_QUQUE(_x) ((_x == 0) ? 1 : ((_x == 1) ? 2 : 0)) 79 80 /* Pause frame feild and FIFO threshold */ 81 #define FEC_ENET_FCE (1 << 5) 82 #define FEC_ENET_RSEM_V 0x84 83 #define FEC_ENET_RSFL_V 16 84 #define FEC_ENET_RAEM_V 0x8 85 #define FEC_ENET_RAFL_V 0x8 86 #define FEC_ENET_OPD_V 0xFFF0 87 #define FEC_MDIO_PM_TIMEOUT 100 /* ms */ 88 89 struct fec_devinfo { 90 u32 quirks; 91 }; 92 93 static const struct fec_devinfo fec_imx25_info = { 94 .quirks = FEC_QUIRK_USE_GASKET | FEC_QUIRK_MIB_CLEAR | 95 FEC_QUIRK_HAS_FRREG, 96 }; 97 98 static const struct fec_devinfo fec_imx27_info = { 99 .quirks = FEC_QUIRK_MIB_CLEAR | FEC_QUIRK_HAS_FRREG, 100 }; 101 102 static const struct fec_devinfo fec_imx28_info = { 103 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME | 104 FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC | 105 FEC_QUIRK_HAS_FRREG, 106 }; 107 108 static const struct fec_devinfo fec_imx6q_info = { 109 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 110 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 111 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 | 112 FEC_QUIRK_HAS_RACC, 113 }; 114 115 static const struct fec_devinfo fec_mvf600_info = { 116 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC, 117 }; 118 119 static const struct fec_devinfo fec_imx6x_info = { 120 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 121 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 122 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 123 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 124 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE, 125 }; 126 127 static const struct fec_devinfo fec_imx6ul_info = { 128 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 129 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 130 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR007885 | 131 FEC_QUIRK_BUG_CAPTURE | FEC_QUIRK_HAS_RACC | 132 FEC_QUIRK_HAS_COALESCE, 133 }; 134 135 static struct platform_device_id fec_devtype[] = { 136 { 137 /* keep it for coldfire */ 138 .name = DRIVER_NAME, 139 .driver_data = 0, 140 }, { 141 .name = "imx25-fec", 142 .driver_data = (kernel_ulong_t)&fec_imx25_info, 143 }, { 144 .name = "imx27-fec", 145 .driver_data = (kernel_ulong_t)&fec_imx27_info, 146 }, { 147 .name = "imx28-fec", 148 .driver_data = (kernel_ulong_t)&fec_imx28_info, 149 }, { 150 .name = "imx6q-fec", 151 .driver_data = (kernel_ulong_t)&fec_imx6q_info, 152 }, { 153 .name = "mvf600-fec", 154 .driver_data = (kernel_ulong_t)&fec_mvf600_info, 155 }, { 156 .name = "imx6sx-fec", 157 .driver_data = (kernel_ulong_t)&fec_imx6x_info, 158 }, { 159 .name = "imx6ul-fec", 160 .driver_data = (kernel_ulong_t)&fec_imx6ul_info, 161 }, { 162 /* sentinel */ 163 } 164 }; 165 MODULE_DEVICE_TABLE(platform, fec_devtype); 166 167 enum imx_fec_type { 168 IMX25_FEC = 1, /* runs on i.mx25/50/53 */ 169 IMX27_FEC, /* runs on i.mx27/35/51 */ 170 IMX28_FEC, 171 IMX6Q_FEC, 172 MVF600_FEC, 173 IMX6SX_FEC, 174 IMX6UL_FEC, 175 }; 176 177 static const struct of_device_id fec_dt_ids[] = { 178 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], }, 179 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], }, 180 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], }, 181 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], }, 182 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], }, 183 { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], }, 184 { .compatible = "fsl,imx6ul-fec", .data = &fec_devtype[IMX6UL_FEC], }, 185 { /* sentinel */ } 186 }; 187 MODULE_DEVICE_TABLE(of, fec_dt_ids); 188 189 static unsigned char macaddr[ETH_ALEN]; 190 module_param_array(macaddr, byte, NULL, 0); 191 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address"); 192 193 #if defined(CONFIG_M5272) 194 /* 195 * Some hardware gets it MAC address out of local flash memory. 196 * if this is non-zero then assume it is the address to get MAC from. 197 */ 198 #if defined(CONFIG_NETtel) 199 #define FEC_FLASHMAC 0xf0006006 200 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) 201 #define FEC_FLASHMAC 0xf0006000 202 #elif defined(CONFIG_CANCam) 203 #define FEC_FLASHMAC 0xf0020000 204 #elif defined (CONFIG_M5272C3) 205 #define FEC_FLASHMAC (0xffe04000 + 4) 206 #elif defined(CONFIG_MOD5272) 207 #define FEC_FLASHMAC 0xffc0406b 208 #else 209 #define FEC_FLASHMAC 0 210 #endif 211 #endif /* CONFIG_M5272 */ 212 213 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets. 214 * 215 * 2048 byte skbufs are allocated. However, alignment requirements 216 * varies between FEC variants. Worst case is 64, so round down by 64. 217 */ 218 #define PKT_MAXBUF_SIZE (round_down(2048 - 64, 64)) 219 #define PKT_MINBUF_SIZE 64 220 221 /* FEC receive acceleration */ 222 #define FEC_RACC_IPDIS (1 << 1) 223 #define FEC_RACC_PRODIS (1 << 2) 224 #define FEC_RACC_SHIFT16 BIT(7) 225 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS) 226 227 /* MIB Control Register */ 228 #define FEC_MIB_CTRLSTAT_DISABLE BIT(31) 229 230 /* 231 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame 232 * size bits. Other FEC hardware does not, so we need to take that into 233 * account when setting it. 234 */ 235 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 236 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \ 237 defined(CONFIG_ARM64) 238 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) 239 #else 240 #define OPT_FRAME_SIZE 0 241 #endif 242 243 /* FEC MII MMFR bits definition */ 244 #define FEC_MMFR_ST (1 << 30) 245 #define FEC_MMFR_ST_C45 (0) 246 #define FEC_MMFR_OP_READ (2 << 28) 247 #define FEC_MMFR_OP_READ_C45 (3 << 28) 248 #define FEC_MMFR_OP_WRITE (1 << 28) 249 #define FEC_MMFR_OP_ADDR_WRITE (0) 250 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23) 251 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18) 252 #define FEC_MMFR_TA (2 << 16) 253 #define FEC_MMFR_DATA(v) (v & 0xffff) 254 /* FEC ECR bits definition */ 255 #define FEC_ECR_MAGICEN (1 << 2) 256 #define FEC_ECR_SLEEP (1 << 3) 257 258 #define FEC_MII_TIMEOUT 30000 /* us */ 259 260 /* Transmitter timeout */ 261 #define TX_TIMEOUT (2 * HZ) 262 263 #define FEC_PAUSE_FLAG_AUTONEG 0x1 264 #define FEC_PAUSE_FLAG_ENABLE 0x2 265 #define FEC_WOL_HAS_MAGIC_PACKET (0x1 << 0) 266 #define FEC_WOL_FLAG_ENABLE (0x1 << 1) 267 #define FEC_WOL_FLAG_SLEEP_ON (0x1 << 2) 268 269 #define COPYBREAK_DEFAULT 256 270 271 /* Max number of allowed TCP segments for software TSO */ 272 #define FEC_MAX_TSO_SEGS 100 273 #define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) 274 275 #define IS_TSO_HEADER(txq, addr) \ 276 ((addr >= txq->tso_hdrs_dma) && \ 277 (addr < txq->tso_hdrs_dma + txq->bd.ring_size * TSO_HEADER_SIZE)) 278 279 static int mii_cnt; 280 281 static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, 282 struct bufdesc_prop *bd) 283 { 284 return (bdp >= bd->last) ? bd->base 285 : (struct bufdesc *)(((void *)bdp) + bd->dsize); 286 } 287 288 static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, 289 struct bufdesc_prop *bd) 290 { 291 return (bdp <= bd->base) ? bd->last 292 : (struct bufdesc *)(((void *)bdp) - bd->dsize); 293 } 294 295 static int fec_enet_get_bd_index(struct bufdesc *bdp, 296 struct bufdesc_prop *bd) 297 { 298 return ((const char *)bdp - (const char *)bd->base) >> bd->dsize_log2; 299 } 300 301 static int fec_enet_get_free_txdesc_num(struct fec_enet_priv_tx_q *txq) 302 { 303 int entries; 304 305 entries = (((const char *)txq->dirty_tx - 306 (const char *)txq->bd.cur) >> txq->bd.dsize_log2) - 1; 307 308 return entries >= 0 ? entries : entries + txq->bd.ring_size; 309 } 310 311 static void swap_buffer(void *bufaddr, int len) 312 { 313 int i; 314 unsigned int *buf = bufaddr; 315 316 for (i = 0; i < len; i += 4, buf++) 317 swab32s(buf); 318 } 319 320 static void swap_buffer2(void *dst_buf, void *src_buf, int len) 321 { 322 int i; 323 unsigned int *src = src_buf; 324 unsigned int *dst = dst_buf; 325 326 for (i = 0; i < len; i += 4, src++, dst++) 327 *dst = swab32p(src); 328 } 329 330 static void fec_dump(struct net_device *ndev) 331 { 332 struct fec_enet_private *fep = netdev_priv(ndev); 333 struct bufdesc *bdp; 334 struct fec_enet_priv_tx_q *txq; 335 int index = 0; 336 337 netdev_info(ndev, "TX ring dump\n"); 338 pr_info("Nr SC addr len SKB\n"); 339 340 txq = fep->tx_queue[0]; 341 bdp = txq->bd.base; 342 343 do { 344 pr_info("%3u %c%c 0x%04x 0x%08x %4u %p\n", 345 index, 346 bdp == txq->bd.cur ? 'S' : ' ', 347 bdp == txq->dirty_tx ? 'H' : ' ', 348 fec16_to_cpu(bdp->cbd_sc), 349 fec32_to_cpu(bdp->cbd_bufaddr), 350 fec16_to_cpu(bdp->cbd_datlen), 351 txq->tx_skbuff[index]); 352 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 353 index++; 354 } while (bdp != txq->bd.base); 355 } 356 357 static inline bool is_ipv4_pkt(struct sk_buff *skb) 358 { 359 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4; 360 } 361 362 static int 363 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev) 364 { 365 /* Only run for packets requiring a checksum. */ 366 if (skb->ip_summed != CHECKSUM_PARTIAL) 367 return 0; 368 369 if (unlikely(skb_cow_head(skb, 0))) 370 return -1; 371 372 if (is_ipv4_pkt(skb)) 373 ip_hdr(skb)->check = 0; 374 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0; 375 376 return 0; 377 } 378 379 static struct bufdesc * 380 fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq, 381 struct sk_buff *skb, 382 struct net_device *ndev) 383 { 384 struct fec_enet_private *fep = netdev_priv(ndev); 385 struct bufdesc *bdp = txq->bd.cur; 386 struct bufdesc_ex *ebdp; 387 int nr_frags = skb_shinfo(skb)->nr_frags; 388 int frag, frag_len; 389 unsigned short status; 390 unsigned int estatus = 0; 391 skb_frag_t *this_frag; 392 unsigned int index; 393 void *bufaddr; 394 dma_addr_t addr; 395 int i; 396 397 for (frag = 0; frag < nr_frags; frag++) { 398 this_frag = &skb_shinfo(skb)->frags[frag]; 399 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 400 ebdp = (struct bufdesc_ex *)bdp; 401 402 status = fec16_to_cpu(bdp->cbd_sc); 403 status &= ~BD_ENET_TX_STATS; 404 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 405 frag_len = skb_frag_size(&skb_shinfo(skb)->frags[frag]); 406 407 /* Handle the last BD specially */ 408 if (frag == nr_frags - 1) { 409 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 410 if (fep->bufdesc_ex) { 411 estatus |= BD_ENET_TX_INT; 412 if (unlikely(skb_shinfo(skb)->tx_flags & 413 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 414 estatus |= BD_ENET_TX_TS; 415 } 416 } 417 418 if (fep->bufdesc_ex) { 419 if (fep->quirks & FEC_QUIRK_HAS_AVB) 420 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 421 if (skb->ip_summed == CHECKSUM_PARTIAL) 422 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 423 ebdp->cbd_bdu = 0; 424 ebdp->cbd_esc = cpu_to_fec32(estatus); 425 } 426 427 bufaddr = skb_frag_address(this_frag); 428 429 index = fec_enet_get_bd_index(bdp, &txq->bd); 430 if (((unsigned long) bufaddr) & fep->tx_align || 431 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 432 memcpy(txq->tx_bounce[index], bufaddr, frag_len); 433 bufaddr = txq->tx_bounce[index]; 434 435 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 436 swap_buffer(bufaddr, frag_len); 437 } 438 439 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len, 440 DMA_TO_DEVICE); 441 if (dma_mapping_error(&fep->pdev->dev, addr)) { 442 if (net_ratelimit()) 443 netdev_err(ndev, "Tx DMA memory map failed\n"); 444 goto dma_mapping_error; 445 } 446 447 bdp->cbd_bufaddr = cpu_to_fec32(addr); 448 bdp->cbd_datlen = cpu_to_fec16(frag_len); 449 /* Make sure the updates to rest of the descriptor are 450 * performed before transferring ownership. 451 */ 452 wmb(); 453 bdp->cbd_sc = cpu_to_fec16(status); 454 } 455 456 return bdp; 457 dma_mapping_error: 458 bdp = txq->bd.cur; 459 for (i = 0; i < frag; i++) { 460 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 461 dma_unmap_single(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr), 462 fec16_to_cpu(bdp->cbd_datlen), DMA_TO_DEVICE); 463 } 464 return ERR_PTR(-ENOMEM); 465 } 466 467 static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq, 468 struct sk_buff *skb, struct net_device *ndev) 469 { 470 struct fec_enet_private *fep = netdev_priv(ndev); 471 int nr_frags = skb_shinfo(skb)->nr_frags; 472 struct bufdesc *bdp, *last_bdp; 473 void *bufaddr; 474 dma_addr_t addr; 475 unsigned short status; 476 unsigned short buflen; 477 unsigned int estatus = 0; 478 unsigned int index; 479 int entries_free; 480 481 entries_free = fec_enet_get_free_txdesc_num(txq); 482 if (entries_free < MAX_SKB_FRAGS + 1) { 483 dev_kfree_skb_any(skb); 484 if (net_ratelimit()) 485 netdev_err(ndev, "NOT enough BD for SG!\n"); 486 return NETDEV_TX_OK; 487 } 488 489 /* Protocol checksum off-load for TCP and UDP. */ 490 if (fec_enet_clear_csum(skb, ndev)) { 491 dev_kfree_skb_any(skb); 492 return NETDEV_TX_OK; 493 } 494 495 /* Fill in a Tx ring entry */ 496 bdp = txq->bd.cur; 497 last_bdp = bdp; 498 status = fec16_to_cpu(bdp->cbd_sc); 499 status &= ~BD_ENET_TX_STATS; 500 501 /* Set buffer length and buffer pointer */ 502 bufaddr = skb->data; 503 buflen = skb_headlen(skb); 504 505 index = fec_enet_get_bd_index(bdp, &txq->bd); 506 if (((unsigned long) bufaddr) & fep->tx_align || 507 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 508 memcpy(txq->tx_bounce[index], skb->data, buflen); 509 bufaddr = txq->tx_bounce[index]; 510 511 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 512 swap_buffer(bufaddr, buflen); 513 } 514 515 /* Push the data cache so the CPM does not get stale memory data. */ 516 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE); 517 if (dma_mapping_error(&fep->pdev->dev, addr)) { 518 dev_kfree_skb_any(skb); 519 if (net_ratelimit()) 520 netdev_err(ndev, "Tx DMA memory map failed\n"); 521 return NETDEV_TX_OK; 522 } 523 524 if (nr_frags) { 525 last_bdp = fec_enet_txq_submit_frag_skb(txq, skb, ndev); 526 if (IS_ERR(last_bdp)) { 527 dma_unmap_single(&fep->pdev->dev, addr, 528 buflen, DMA_TO_DEVICE); 529 dev_kfree_skb_any(skb); 530 return NETDEV_TX_OK; 531 } 532 } else { 533 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 534 if (fep->bufdesc_ex) { 535 estatus = BD_ENET_TX_INT; 536 if (unlikely(skb_shinfo(skb)->tx_flags & 537 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 538 estatus |= BD_ENET_TX_TS; 539 } 540 } 541 bdp->cbd_bufaddr = cpu_to_fec32(addr); 542 bdp->cbd_datlen = cpu_to_fec16(buflen); 543 544 if (fep->bufdesc_ex) { 545 546 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 547 548 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 549 fep->hwts_tx_en)) 550 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 551 552 if (fep->quirks & FEC_QUIRK_HAS_AVB) 553 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 554 555 if (skb->ip_summed == CHECKSUM_PARTIAL) 556 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 557 558 ebdp->cbd_bdu = 0; 559 ebdp->cbd_esc = cpu_to_fec32(estatus); 560 } 561 562 index = fec_enet_get_bd_index(last_bdp, &txq->bd); 563 /* Save skb pointer */ 564 txq->tx_skbuff[index] = skb; 565 566 /* Make sure the updates to rest of the descriptor are performed before 567 * transferring ownership. 568 */ 569 wmb(); 570 571 /* Send it on its way. Tell FEC it's ready, interrupt when done, 572 * it's the last BD of the frame, and to put the CRC on the end. 573 */ 574 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC); 575 bdp->cbd_sc = cpu_to_fec16(status); 576 577 /* If this was the last BD in the ring, start at the beginning again. */ 578 bdp = fec_enet_get_nextdesc(last_bdp, &txq->bd); 579 580 skb_tx_timestamp(skb); 581 582 /* Make sure the update to bdp and tx_skbuff are performed before 583 * txq->bd.cur. 584 */ 585 wmb(); 586 txq->bd.cur = bdp; 587 588 /* Trigger transmission start */ 589 writel(0, txq->bd.reg_desc_active); 590 591 return 0; 592 } 593 594 static int 595 fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb, 596 struct net_device *ndev, 597 struct bufdesc *bdp, int index, char *data, 598 int size, bool last_tcp, bool is_last) 599 { 600 struct fec_enet_private *fep = netdev_priv(ndev); 601 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 602 unsigned short status; 603 unsigned int estatus = 0; 604 dma_addr_t addr; 605 606 status = fec16_to_cpu(bdp->cbd_sc); 607 status &= ~BD_ENET_TX_STATS; 608 609 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 610 611 if (((unsigned long) data) & fep->tx_align || 612 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 613 memcpy(txq->tx_bounce[index], data, size); 614 data = txq->tx_bounce[index]; 615 616 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 617 swap_buffer(data, size); 618 } 619 620 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE); 621 if (dma_mapping_error(&fep->pdev->dev, addr)) { 622 dev_kfree_skb_any(skb); 623 if (net_ratelimit()) 624 netdev_err(ndev, "Tx DMA memory map failed\n"); 625 return NETDEV_TX_BUSY; 626 } 627 628 bdp->cbd_datlen = cpu_to_fec16(size); 629 bdp->cbd_bufaddr = cpu_to_fec32(addr); 630 631 if (fep->bufdesc_ex) { 632 if (fep->quirks & FEC_QUIRK_HAS_AVB) 633 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 634 if (skb->ip_summed == CHECKSUM_PARTIAL) 635 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 636 ebdp->cbd_bdu = 0; 637 ebdp->cbd_esc = cpu_to_fec32(estatus); 638 } 639 640 /* Handle the last BD specially */ 641 if (last_tcp) 642 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC); 643 if (is_last) { 644 status |= BD_ENET_TX_INTR; 645 if (fep->bufdesc_ex) 646 ebdp->cbd_esc |= cpu_to_fec32(BD_ENET_TX_INT); 647 } 648 649 bdp->cbd_sc = cpu_to_fec16(status); 650 651 return 0; 652 } 653 654 static int 655 fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq, 656 struct sk_buff *skb, struct net_device *ndev, 657 struct bufdesc *bdp, int index) 658 { 659 struct fec_enet_private *fep = netdev_priv(ndev); 660 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 661 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 662 void *bufaddr; 663 unsigned long dmabuf; 664 unsigned short status; 665 unsigned int estatus = 0; 666 667 status = fec16_to_cpu(bdp->cbd_sc); 668 status &= ~BD_ENET_TX_STATS; 669 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 670 671 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 672 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE; 673 if (((unsigned long)bufaddr) & fep->tx_align || 674 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 675 memcpy(txq->tx_bounce[index], skb->data, hdr_len); 676 bufaddr = txq->tx_bounce[index]; 677 678 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 679 swap_buffer(bufaddr, hdr_len); 680 681 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr, 682 hdr_len, DMA_TO_DEVICE); 683 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) { 684 dev_kfree_skb_any(skb); 685 if (net_ratelimit()) 686 netdev_err(ndev, "Tx DMA memory map failed\n"); 687 return NETDEV_TX_BUSY; 688 } 689 } 690 691 bdp->cbd_bufaddr = cpu_to_fec32(dmabuf); 692 bdp->cbd_datlen = cpu_to_fec16(hdr_len); 693 694 if (fep->bufdesc_ex) { 695 if (fep->quirks & FEC_QUIRK_HAS_AVB) 696 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 697 if (skb->ip_summed == CHECKSUM_PARTIAL) 698 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 699 ebdp->cbd_bdu = 0; 700 ebdp->cbd_esc = cpu_to_fec32(estatus); 701 } 702 703 bdp->cbd_sc = cpu_to_fec16(status); 704 705 return 0; 706 } 707 708 static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq, 709 struct sk_buff *skb, 710 struct net_device *ndev) 711 { 712 struct fec_enet_private *fep = netdev_priv(ndev); 713 int hdr_len, total_len, data_left; 714 struct bufdesc *bdp = txq->bd.cur; 715 struct tso_t tso; 716 unsigned int index = 0; 717 int ret; 718 719 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(txq)) { 720 dev_kfree_skb_any(skb); 721 if (net_ratelimit()) 722 netdev_err(ndev, "NOT enough BD for TSO!\n"); 723 return NETDEV_TX_OK; 724 } 725 726 /* Protocol checksum off-load for TCP and UDP. */ 727 if (fec_enet_clear_csum(skb, ndev)) { 728 dev_kfree_skb_any(skb); 729 return NETDEV_TX_OK; 730 } 731 732 /* Initialize the TSO handler, and prepare the first payload */ 733 hdr_len = tso_start(skb, &tso); 734 735 total_len = skb->len - hdr_len; 736 while (total_len > 0) { 737 char *hdr; 738 739 index = fec_enet_get_bd_index(bdp, &txq->bd); 740 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); 741 total_len -= data_left; 742 743 /* prepare packet headers: MAC + IP + TCP */ 744 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 745 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); 746 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index); 747 if (ret) 748 goto err_release; 749 750 while (data_left > 0) { 751 int size; 752 753 size = min_t(int, tso.size, data_left); 754 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 755 index = fec_enet_get_bd_index(bdp, &txq->bd); 756 ret = fec_enet_txq_put_data_tso(txq, skb, ndev, 757 bdp, index, 758 tso.data, size, 759 size == data_left, 760 total_len == 0); 761 if (ret) 762 goto err_release; 763 764 data_left -= size; 765 tso_build_data(skb, &tso, size); 766 } 767 768 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 769 } 770 771 /* Save skb pointer */ 772 txq->tx_skbuff[index] = skb; 773 774 skb_tx_timestamp(skb); 775 txq->bd.cur = bdp; 776 777 /* Trigger transmission start */ 778 if (!(fep->quirks & FEC_QUIRK_ERR007885) || 779 !readl(txq->bd.reg_desc_active) || 780 !readl(txq->bd.reg_desc_active) || 781 !readl(txq->bd.reg_desc_active) || 782 !readl(txq->bd.reg_desc_active)) 783 writel(0, txq->bd.reg_desc_active); 784 785 return 0; 786 787 err_release: 788 /* TODO: Release all used data descriptors for TSO */ 789 return ret; 790 } 791 792 static netdev_tx_t 793 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) 794 { 795 struct fec_enet_private *fep = netdev_priv(ndev); 796 int entries_free; 797 unsigned short queue; 798 struct fec_enet_priv_tx_q *txq; 799 struct netdev_queue *nq; 800 int ret; 801 802 queue = skb_get_queue_mapping(skb); 803 txq = fep->tx_queue[queue]; 804 nq = netdev_get_tx_queue(ndev, queue); 805 806 if (skb_is_gso(skb)) 807 ret = fec_enet_txq_submit_tso(txq, skb, ndev); 808 else 809 ret = fec_enet_txq_submit_skb(txq, skb, ndev); 810 if (ret) 811 return ret; 812 813 entries_free = fec_enet_get_free_txdesc_num(txq); 814 if (entries_free <= txq->tx_stop_threshold) 815 netif_tx_stop_queue(nq); 816 817 return NETDEV_TX_OK; 818 } 819 820 /* Init RX & TX buffer descriptors 821 */ 822 static void fec_enet_bd_init(struct net_device *dev) 823 { 824 struct fec_enet_private *fep = netdev_priv(dev); 825 struct fec_enet_priv_tx_q *txq; 826 struct fec_enet_priv_rx_q *rxq; 827 struct bufdesc *bdp; 828 unsigned int i; 829 unsigned int q; 830 831 for (q = 0; q < fep->num_rx_queues; q++) { 832 /* Initialize the receive buffer descriptors. */ 833 rxq = fep->rx_queue[q]; 834 bdp = rxq->bd.base; 835 836 for (i = 0; i < rxq->bd.ring_size; i++) { 837 838 /* Initialize the BD for every fragment in the page. */ 839 if (bdp->cbd_bufaddr) 840 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); 841 else 842 bdp->cbd_sc = cpu_to_fec16(0); 843 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 844 } 845 846 /* Set the last buffer to wrap */ 847 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); 848 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 849 850 rxq->bd.cur = rxq->bd.base; 851 } 852 853 for (q = 0; q < fep->num_tx_queues; q++) { 854 /* ...and the same for transmit */ 855 txq = fep->tx_queue[q]; 856 bdp = txq->bd.base; 857 txq->bd.cur = bdp; 858 859 for (i = 0; i < txq->bd.ring_size; i++) { 860 /* Initialize the BD for every fragment in the page. */ 861 bdp->cbd_sc = cpu_to_fec16(0); 862 if (bdp->cbd_bufaddr && 863 !IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr))) 864 dma_unmap_single(&fep->pdev->dev, 865 fec32_to_cpu(bdp->cbd_bufaddr), 866 fec16_to_cpu(bdp->cbd_datlen), 867 DMA_TO_DEVICE); 868 if (txq->tx_skbuff[i]) { 869 dev_kfree_skb_any(txq->tx_skbuff[i]); 870 txq->tx_skbuff[i] = NULL; 871 } 872 bdp->cbd_bufaddr = cpu_to_fec32(0); 873 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 874 } 875 876 /* Set the last buffer to wrap */ 877 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); 878 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 879 txq->dirty_tx = bdp; 880 } 881 } 882 883 static void fec_enet_active_rxring(struct net_device *ndev) 884 { 885 struct fec_enet_private *fep = netdev_priv(ndev); 886 int i; 887 888 for (i = 0; i < fep->num_rx_queues; i++) 889 writel(0, fep->rx_queue[i]->bd.reg_desc_active); 890 } 891 892 static void fec_enet_enable_ring(struct net_device *ndev) 893 { 894 struct fec_enet_private *fep = netdev_priv(ndev); 895 struct fec_enet_priv_tx_q *txq; 896 struct fec_enet_priv_rx_q *rxq; 897 int i; 898 899 for (i = 0; i < fep->num_rx_queues; i++) { 900 rxq = fep->rx_queue[i]; 901 writel(rxq->bd.dma, fep->hwp + FEC_R_DES_START(i)); 902 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i)); 903 904 /* enable DMA1/2 */ 905 if (i) 906 writel(RCMR_MATCHEN | RCMR_CMP(i), 907 fep->hwp + FEC_RCMR(i)); 908 } 909 910 for (i = 0; i < fep->num_tx_queues; i++) { 911 txq = fep->tx_queue[i]; 912 writel(txq->bd.dma, fep->hwp + FEC_X_DES_START(i)); 913 914 /* enable DMA1/2 */ 915 if (i) 916 writel(DMA_CLASS_EN | IDLE_SLOPE(i), 917 fep->hwp + FEC_DMA_CFG(i)); 918 } 919 } 920 921 static void fec_enet_reset_skb(struct net_device *ndev) 922 { 923 struct fec_enet_private *fep = netdev_priv(ndev); 924 struct fec_enet_priv_tx_q *txq; 925 int i, j; 926 927 for (i = 0; i < fep->num_tx_queues; i++) { 928 txq = fep->tx_queue[i]; 929 930 for (j = 0; j < txq->bd.ring_size; j++) { 931 if (txq->tx_skbuff[j]) { 932 dev_kfree_skb_any(txq->tx_skbuff[j]); 933 txq->tx_skbuff[j] = NULL; 934 } 935 } 936 } 937 } 938 939 /* 940 * This function is called to start or restart the FEC during a link 941 * change, transmit timeout, or to reconfigure the FEC. The network 942 * packet processing for this device must be stopped before this call. 943 */ 944 static void 945 fec_restart(struct net_device *ndev) 946 { 947 struct fec_enet_private *fep = netdev_priv(ndev); 948 u32 val; 949 u32 temp_mac[2]; 950 u32 rcntl = OPT_FRAME_SIZE | 0x04; 951 u32 ecntl = 0x2; /* ETHEREN */ 952 953 /* Whack a reset. We should wait for this. 954 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC 955 * instead of reset MAC itself. 956 */ 957 if (fep->quirks & FEC_QUIRK_HAS_AVB) { 958 writel(0, fep->hwp + FEC_ECNTRL); 959 } else { 960 writel(1, fep->hwp + FEC_ECNTRL); 961 udelay(10); 962 } 963 964 /* 965 * enet-mac reset will reset mac address registers too, 966 * so need to reconfigure it. 967 */ 968 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN); 969 writel((__force u32)cpu_to_be32(temp_mac[0]), 970 fep->hwp + FEC_ADDR_LOW); 971 writel((__force u32)cpu_to_be32(temp_mac[1]), 972 fep->hwp + FEC_ADDR_HIGH); 973 974 /* Clear any outstanding interrupt, except MDIO. */ 975 writel((0xffffffff & ~FEC_ENET_MII), fep->hwp + FEC_IEVENT); 976 977 fec_enet_bd_init(ndev); 978 979 fec_enet_enable_ring(ndev); 980 981 /* Reset tx SKB buffers. */ 982 fec_enet_reset_skb(ndev); 983 984 /* Enable MII mode */ 985 if (fep->full_duplex == DUPLEX_FULL) { 986 /* FD enable */ 987 writel(0x04, fep->hwp + FEC_X_CNTRL); 988 } else { 989 /* No Rcv on Xmit */ 990 rcntl |= 0x02; 991 writel(0x0, fep->hwp + FEC_X_CNTRL); 992 } 993 994 /* Set MII speed */ 995 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 996 997 #if !defined(CONFIG_M5272) 998 if (fep->quirks & FEC_QUIRK_HAS_RACC) { 999 val = readl(fep->hwp + FEC_RACC); 1000 /* align IP header */ 1001 val |= FEC_RACC_SHIFT16; 1002 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED) 1003 /* set RX checksum */ 1004 val |= FEC_RACC_OPTIONS; 1005 else 1006 val &= ~FEC_RACC_OPTIONS; 1007 writel(val, fep->hwp + FEC_RACC); 1008 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_FTRL); 1009 } 1010 #endif 1011 1012 /* 1013 * The phy interface and speed need to get configured 1014 * differently on enet-mac. 1015 */ 1016 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 1017 /* Enable flow control and length check */ 1018 rcntl |= 0x40000000 | 0x00000020; 1019 1020 /* RGMII, RMII or MII */ 1021 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII || 1022 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 1023 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID || 1024 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) 1025 rcntl |= (1 << 6); 1026 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 1027 rcntl |= (1 << 8); 1028 else 1029 rcntl &= ~(1 << 8); 1030 1031 /* 1G, 100M or 10M */ 1032 if (ndev->phydev) { 1033 if (ndev->phydev->speed == SPEED_1000) 1034 ecntl |= (1 << 5); 1035 else if (ndev->phydev->speed == SPEED_100) 1036 rcntl &= ~(1 << 9); 1037 else 1038 rcntl |= (1 << 9); 1039 } 1040 } else { 1041 #ifdef FEC_MIIGSK_ENR 1042 if (fep->quirks & FEC_QUIRK_USE_GASKET) { 1043 u32 cfgr; 1044 /* disable the gasket and wait */ 1045 writel(0, fep->hwp + FEC_MIIGSK_ENR); 1046 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4) 1047 udelay(1); 1048 1049 /* 1050 * configure the gasket: 1051 * RMII, 50 MHz, no loopback, no echo 1052 * MII, 25 MHz, no loopback, no echo 1053 */ 1054 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 1055 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII; 1056 if (ndev->phydev && ndev->phydev->speed == SPEED_10) 1057 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M; 1058 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR); 1059 1060 /* re-enable the gasket */ 1061 writel(2, fep->hwp + FEC_MIIGSK_ENR); 1062 } 1063 #endif 1064 } 1065 1066 #if !defined(CONFIG_M5272) 1067 /* enable pause frame*/ 1068 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) || 1069 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) && 1070 ndev->phydev && ndev->phydev->pause)) { 1071 rcntl |= FEC_ENET_FCE; 1072 1073 /* set FIFO threshold parameter to reduce overrun */ 1074 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM); 1075 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL); 1076 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM); 1077 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL); 1078 1079 /* OPD */ 1080 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD); 1081 } else { 1082 rcntl &= ~FEC_ENET_FCE; 1083 } 1084 #endif /* !defined(CONFIG_M5272) */ 1085 1086 writel(rcntl, fep->hwp + FEC_R_CNTRL); 1087 1088 /* Setup multicast filter. */ 1089 set_multicast_list(ndev); 1090 #ifndef CONFIG_M5272 1091 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); 1092 writel(0, fep->hwp + FEC_HASH_TABLE_LOW); 1093 #endif 1094 1095 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 1096 /* enable ENET endian swap */ 1097 ecntl |= (1 << 8); 1098 /* enable ENET store and forward mode */ 1099 writel(1 << 8, fep->hwp + FEC_X_WMRK); 1100 } 1101 1102 if (fep->bufdesc_ex) 1103 ecntl |= (1 << 4); 1104 1105 #ifndef CONFIG_M5272 1106 /* Enable the MIB statistic event counters */ 1107 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT); 1108 #endif 1109 1110 /* And last, enable the transmit and receive processing */ 1111 writel(ecntl, fep->hwp + FEC_ECNTRL); 1112 fec_enet_active_rxring(ndev); 1113 1114 if (fep->bufdesc_ex) 1115 fec_ptp_start_cyclecounter(ndev); 1116 1117 /* Enable interrupts we wish to service */ 1118 if (fep->link) 1119 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1120 else 1121 writel(0, fep->hwp + FEC_IMASK); 1122 1123 /* Init the interrupt coalescing */ 1124 fec_enet_itr_coal_init(ndev); 1125 1126 } 1127 1128 static void fec_enet_stop_mode(struct fec_enet_private *fep, bool enabled) 1129 { 1130 struct fec_platform_data *pdata = fep->pdev->dev.platform_data; 1131 struct fec_stop_mode_gpr *stop_gpr = &fep->stop_gpr; 1132 1133 if (stop_gpr->gpr) { 1134 if (enabled) 1135 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg, 1136 BIT(stop_gpr->bit), 1137 BIT(stop_gpr->bit)); 1138 else 1139 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg, 1140 BIT(stop_gpr->bit), 0); 1141 } else if (pdata && pdata->sleep_mode_enable) { 1142 pdata->sleep_mode_enable(enabled); 1143 } 1144 } 1145 1146 static void 1147 fec_stop(struct net_device *ndev) 1148 { 1149 struct fec_enet_private *fep = netdev_priv(ndev); 1150 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8); 1151 u32 val; 1152 1153 /* We cannot expect a graceful transmit stop without link !!! */ 1154 if (fep->link) { 1155 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ 1156 udelay(10); 1157 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) 1158 netdev_err(ndev, "Graceful transmit stop did not complete!\n"); 1159 } 1160 1161 /* Whack a reset. We should wait for this. 1162 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC 1163 * instead of reset MAC itself. 1164 */ 1165 if (!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1166 if (fep->quirks & FEC_QUIRK_HAS_AVB) { 1167 writel(0, fep->hwp + FEC_ECNTRL); 1168 } else { 1169 writel(1, fep->hwp + FEC_ECNTRL); 1170 udelay(10); 1171 } 1172 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1173 } else { 1174 writel(FEC_DEFAULT_IMASK | FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK); 1175 val = readl(fep->hwp + FEC_ECNTRL); 1176 val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP); 1177 writel(val, fep->hwp + FEC_ECNTRL); 1178 fec_enet_stop_mode(fep, true); 1179 } 1180 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1181 1182 /* We have to keep ENET enabled to have MII interrupt stay working */ 1183 if (fep->quirks & FEC_QUIRK_ENET_MAC && 1184 !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1185 writel(2, fep->hwp + FEC_ECNTRL); 1186 writel(rmii_mode, fep->hwp + FEC_R_CNTRL); 1187 } 1188 } 1189 1190 1191 static void 1192 fec_timeout(struct net_device *ndev, unsigned int txqueue) 1193 { 1194 struct fec_enet_private *fep = netdev_priv(ndev); 1195 1196 fec_dump(ndev); 1197 1198 ndev->stats.tx_errors++; 1199 1200 schedule_work(&fep->tx_timeout_work); 1201 } 1202 1203 static void fec_enet_timeout_work(struct work_struct *work) 1204 { 1205 struct fec_enet_private *fep = 1206 container_of(work, struct fec_enet_private, tx_timeout_work); 1207 struct net_device *ndev = fep->netdev; 1208 1209 rtnl_lock(); 1210 if (netif_device_present(ndev) || netif_running(ndev)) { 1211 napi_disable(&fep->napi); 1212 netif_tx_lock_bh(ndev); 1213 fec_restart(ndev); 1214 netif_tx_wake_all_queues(ndev); 1215 netif_tx_unlock_bh(ndev); 1216 napi_enable(&fep->napi); 1217 } 1218 rtnl_unlock(); 1219 } 1220 1221 static void 1222 fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts, 1223 struct skb_shared_hwtstamps *hwtstamps) 1224 { 1225 unsigned long flags; 1226 u64 ns; 1227 1228 spin_lock_irqsave(&fep->tmreg_lock, flags); 1229 ns = timecounter_cyc2time(&fep->tc, ts); 1230 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 1231 1232 memset(hwtstamps, 0, sizeof(*hwtstamps)); 1233 hwtstamps->hwtstamp = ns_to_ktime(ns); 1234 } 1235 1236 static void 1237 fec_enet_tx_queue(struct net_device *ndev, u16 queue_id) 1238 { 1239 struct fec_enet_private *fep; 1240 struct bufdesc *bdp; 1241 unsigned short status; 1242 struct sk_buff *skb; 1243 struct fec_enet_priv_tx_q *txq; 1244 struct netdev_queue *nq; 1245 int index = 0; 1246 int entries_free; 1247 1248 fep = netdev_priv(ndev); 1249 1250 queue_id = FEC_ENET_GET_QUQUE(queue_id); 1251 1252 txq = fep->tx_queue[queue_id]; 1253 /* get next bdp of dirty_tx */ 1254 nq = netdev_get_tx_queue(ndev, queue_id); 1255 bdp = txq->dirty_tx; 1256 1257 /* get next bdp of dirty_tx */ 1258 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1259 1260 while (bdp != READ_ONCE(txq->bd.cur)) { 1261 /* Order the load of bd.cur and cbd_sc */ 1262 rmb(); 1263 status = fec16_to_cpu(READ_ONCE(bdp->cbd_sc)); 1264 if (status & BD_ENET_TX_READY) 1265 break; 1266 1267 index = fec_enet_get_bd_index(bdp, &txq->bd); 1268 1269 skb = txq->tx_skbuff[index]; 1270 txq->tx_skbuff[index] = NULL; 1271 if (!IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr))) 1272 dma_unmap_single(&fep->pdev->dev, 1273 fec32_to_cpu(bdp->cbd_bufaddr), 1274 fec16_to_cpu(bdp->cbd_datlen), 1275 DMA_TO_DEVICE); 1276 bdp->cbd_bufaddr = cpu_to_fec32(0); 1277 if (!skb) 1278 goto skb_done; 1279 1280 /* Check for errors. */ 1281 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | 1282 BD_ENET_TX_RL | BD_ENET_TX_UN | 1283 BD_ENET_TX_CSL)) { 1284 ndev->stats.tx_errors++; 1285 if (status & BD_ENET_TX_HB) /* No heartbeat */ 1286 ndev->stats.tx_heartbeat_errors++; 1287 if (status & BD_ENET_TX_LC) /* Late collision */ 1288 ndev->stats.tx_window_errors++; 1289 if (status & BD_ENET_TX_RL) /* Retrans limit */ 1290 ndev->stats.tx_aborted_errors++; 1291 if (status & BD_ENET_TX_UN) /* Underrun */ 1292 ndev->stats.tx_fifo_errors++; 1293 if (status & BD_ENET_TX_CSL) /* Carrier lost */ 1294 ndev->stats.tx_carrier_errors++; 1295 } else { 1296 ndev->stats.tx_packets++; 1297 ndev->stats.tx_bytes += skb->len; 1298 } 1299 1300 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) && 1301 fep->bufdesc_ex) { 1302 struct skb_shared_hwtstamps shhwtstamps; 1303 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1304 1305 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), &shhwtstamps); 1306 skb_tstamp_tx(skb, &shhwtstamps); 1307 } 1308 1309 /* Deferred means some collisions occurred during transmit, 1310 * but we eventually sent the packet OK. 1311 */ 1312 if (status & BD_ENET_TX_DEF) 1313 ndev->stats.collisions++; 1314 1315 /* Free the sk buffer associated with this last transmit */ 1316 dev_kfree_skb_any(skb); 1317 skb_done: 1318 /* Make sure the update to bdp and tx_skbuff are performed 1319 * before dirty_tx 1320 */ 1321 wmb(); 1322 txq->dirty_tx = bdp; 1323 1324 /* Update pointer to next buffer descriptor to be transmitted */ 1325 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1326 1327 /* Since we have freed up a buffer, the ring is no longer full 1328 */ 1329 if (netif_tx_queue_stopped(nq)) { 1330 entries_free = fec_enet_get_free_txdesc_num(txq); 1331 if (entries_free >= txq->tx_wake_threshold) 1332 netif_tx_wake_queue(nq); 1333 } 1334 } 1335 1336 /* ERR006358: Keep the transmitter going */ 1337 if (bdp != txq->bd.cur && 1338 readl(txq->bd.reg_desc_active) == 0) 1339 writel(0, txq->bd.reg_desc_active); 1340 } 1341 1342 static void 1343 fec_enet_tx(struct net_device *ndev) 1344 { 1345 struct fec_enet_private *fep = netdev_priv(ndev); 1346 u16 queue_id; 1347 /* First process class A queue, then Class B and Best Effort queue */ 1348 for_each_set_bit(queue_id, &fep->work_tx, FEC_ENET_MAX_TX_QS) { 1349 clear_bit(queue_id, &fep->work_tx); 1350 fec_enet_tx_queue(ndev, queue_id); 1351 } 1352 return; 1353 } 1354 1355 static int 1356 fec_enet_new_rxbdp(struct net_device *ndev, struct bufdesc *bdp, struct sk_buff *skb) 1357 { 1358 struct fec_enet_private *fep = netdev_priv(ndev); 1359 int off; 1360 1361 off = ((unsigned long)skb->data) & fep->rx_align; 1362 if (off) 1363 skb_reserve(skb, fep->rx_align + 1 - off); 1364 1365 bdp->cbd_bufaddr = cpu_to_fec32(dma_map_single(&fep->pdev->dev, skb->data, FEC_ENET_RX_FRSIZE - fep->rx_align, DMA_FROM_DEVICE)); 1366 if (dma_mapping_error(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr))) { 1367 if (net_ratelimit()) 1368 netdev_err(ndev, "Rx DMA memory map failed\n"); 1369 return -ENOMEM; 1370 } 1371 1372 return 0; 1373 } 1374 1375 static bool fec_enet_copybreak(struct net_device *ndev, struct sk_buff **skb, 1376 struct bufdesc *bdp, u32 length, bool swap) 1377 { 1378 struct fec_enet_private *fep = netdev_priv(ndev); 1379 struct sk_buff *new_skb; 1380 1381 if (length > fep->rx_copybreak) 1382 return false; 1383 1384 new_skb = netdev_alloc_skb(ndev, length); 1385 if (!new_skb) 1386 return false; 1387 1388 dma_sync_single_for_cpu(&fep->pdev->dev, 1389 fec32_to_cpu(bdp->cbd_bufaddr), 1390 FEC_ENET_RX_FRSIZE - fep->rx_align, 1391 DMA_FROM_DEVICE); 1392 if (!swap) 1393 memcpy(new_skb->data, (*skb)->data, length); 1394 else 1395 swap_buffer2(new_skb->data, (*skb)->data, length); 1396 *skb = new_skb; 1397 1398 return true; 1399 } 1400 1401 /* During a receive, the bd_rx.cur points to the current incoming buffer. 1402 * When we update through the ring, if the next incoming buffer has 1403 * not been given to the system, we just set the empty indicator, 1404 * effectively tossing the packet. 1405 */ 1406 static int 1407 fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id) 1408 { 1409 struct fec_enet_private *fep = netdev_priv(ndev); 1410 struct fec_enet_priv_rx_q *rxq; 1411 struct bufdesc *bdp; 1412 unsigned short status; 1413 struct sk_buff *skb_new = NULL; 1414 struct sk_buff *skb; 1415 ushort pkt_len; 1416 __u8 *data; 1417 int pkt_received = 0; 1418 struct bufdesc_ex *ebdp = NULL; 1419 bool vlan_packet_rcvd = false; 1420 u16 vlan_tag; 1421 int index = 0; 1422 bool is_copybreak; 1423 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME; 1424 1425 #ifdef CONFIG_M532x 1426 flush_cache_all(); 1427 #endif 1428 queue_id = FEC_ENET_GET_QUQUE(queue_id); 1429 rxq = fep->rx_queue[queue_id]; 1430 1431 /* First, grab all of the stats for the incoming packet. 1432 * These get messed up if we get called due to a busy condition. 1433 */ 1434 bdp = rxq->bd.cur; 1435 1436 while (!((status = fec16_to_cpu(bdp->cbd_sc)) & BD_ENET_RX_EMPTY)) { 1437 1438 if (pkt_received >= budget) 1439 break; 1440 pkt_received++; 1441 1442 writel(FEC_ENET_RXF, fep->hwp + FEC_IEVENT); 1443 1444 /* Check for errors. */ 1445 status ^= BD_ENET_RX_LAST; 1446 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | 1447 BD_ENET_RX_CR | BD_ENET_RX_OV | BD_ENET_RX_LAST | 1448 BD_ENET_RX_CL)) { 1449 ndev->stats.rx_errors++; 1450 if (status & BD_ENET_RX_OV) { 1451 /* FIFO overrun */ 1452 ndev->stats.rx_fifo_errors++; 1453 goto rx_processing_done; 1454 } 1455 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH 1456 | BD_ENET_RX_LAST)) { 1457 /* Frame too long or too short. */ 1458 ndev->stats.rx_length_errors++; 1459 if (status & BD_ENET_RX_LAST) 1460 netdev_err(ndev, "rcv is not +last\n"); 1461 } 1462 if (status & BD_ENET_RX_CR) /* CRC Error */ 1463 ndev->stats.rx_crc_errors++; 1464 /* Report late collisions as a frame error. */ 1465 if (status & (BD_ENET_RX_NO | BD_ENET_RX_CL)) 1466 ndev->stats.rx_frame_errors++; 1467 goto rx_processing_done; 1468 } 1469 1470 /* Process the incoming frame. */ 1471 ndev->stats.rx_packets++; 1472 pkt_len = fec16_to_cpu(bdp->cbd_datlen); 1473 ndev->stats.rx_bytes += pkt_len; 1474 1475 index = fec_enet_get_bd_index(bdp, &rxq->bd); 1476 skb = rxq->rx_skbuff[index]; 1477 1478 /* The packet length includes FCS, but we don't want to 1479 * include that when passing upstream as it messes up 1480 * bridging applications. 1481 */ 1482 is_copybreak = fec_enet_copybreak(ndev, &skb, bdp, pkt_len - 4, 1483 need_swap); 1484 if (!is_copybreak) { 1485 skb_new = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE); 1486 if (unlikely(!skb_new)) { 1487 ndev->stats.rx_dropped++; 1488 goto rx_processing_done; 1489 } 1490 dma_unmap_single(&fep->pdev->dev, 1491 fec32_to_cpu(bdp->cbd_bufaddr), 1492 FEC_ENET_RX_FRSIZE - fep->rx_align, 1493 DMA_FROM_DEVICE); 1494 } 1495 1496 prefetch(skb->data - NET_IP_ALIGN); 1497 skb_put(skb, pkt_len - 4); 1498 data = skb->data; 1499 1500 if (!is_copybreak && need_swap) 1501 swap_buffer(data, pkt_len); 1502 1503 #if !defined(CONFIG_M5272) 1504 if (fep->quirks & FEC_QUIRK_HAS_RACC) 1505 data = skb_pull_inline(skb, 2); 1506 #endif 1507 1508 /* Extract the enhanced buffer descriptor */ 1509 ebdp = NULL; 1510 if (fep->bufdesc_ex) 1511 ebdp = (struct bufdesc_ex *)bdp; 1512 1513 /* If this is a VLAN packet remove the VLAN Tag */ 1514 vlan_packet_rcvd = false; 1515 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) && 1516 fep->bufdesc_ex && 1517 (ebdp->cbd_esc & cpu_to_fec32(BD_ENET_RX_VLAN))) { 1518 /* Push and remove the vlan tag */ 1519 struct vlan_hdr *vlan_header = 1520 (struct vlan_hdr *) (data + ETH_HLEN); 1521 vlan_tag = ntohs(vlan_header->h_vlan_TCI); 1522 1523 vlan_packet_rcvd = true; 1524 1525 memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2); 1526 skb_pull(skb, VLAN_HLEN); 1527 } 1528 1529 skb->protocol = eth_type_trans(skb, ndev); 1530 1531 /* Get receive timestamp from the skb */ 1532 if (fep->hwts_rx_en && fep->bufdesc_ex) 1533 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), 1534 skb_hwtstamps(skb)); 1535 1536 if (fep->bufdesc_ex && 1537 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) { 1538 if (!(ebdp->cbd_esc & cpu_to_fec32(FLAG_RX_CSUM_ERROR))) { 1539 /* don't check it */ 1540 skb->ip_summed = CHECKSUM_UNNECESSARY; 1541 } else { 1542 skb_checksum_none_assert(skb); 1543 } 1544 } 1545 1546 /* Handle received VLAN packets */ 1547 if (vlan_packet_rcvd) 1548 __vlan_hwaccel_put_tag(skb, 1549 htons(ETH_P_8021Q), 1550 vlan_tag); 1551 1552 napi_gro_receive(&fep->napi, skb); 1553 1554 if (is_copybreak) { 1555 dma_sync_single_for_device(&fep->pdev->dev, 1556 fec32_to_cpu(bdp->cbd_bufaddr), 1557 FEC_ENET_RX_FRSIZE - fep->rx_align, 1558 DMA_FROM_DEVICE); 1559 } else { 1560 rxq->rx_skbuff[index] = skb_new; 1561 fec_enet_new_rxbdp(ndev, bdp, skb_new); 1562 } 1563 1564 rx_processing_done: 1565 /* Clear the status flags for this buffer */ 1566 status &= ~BD_ENET_RX_STATS; 1567 1568 /* Mark the buffer empty */ 1569 status |= BD_ENET_RX_EMPTY; 1570 1571 if (fep->bufdesc_ex) { 1572 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1573 1574 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); 1575 ebdp->cbd_prot = 0; 1576 ebdp->cbd_bdu = 0; 1577 } 1578 /* Make sure the updates to rest of the descriptor are 1579 * performed before transferring ownership. 1580 */ 1581 wmb(); 1582 bdp->cbd_sc = cpu_to_fec16(status); 1583 1584 /* Update BD pointer to next entry */ 1585 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 1586 1587 /* Doing this here will keep the FEC running while we process 1588 * incoming frames. On a heavily loaded network, we should be 1589 * able to keep up at the expense of system resources. 1590 */ 1591 writel(0, rxq->bd.reg_desc_active); 1592 } 1593 rxq->bd.cur = bdp; 1594 return pkt_received; 1595 } 1596 1597 static int 1598 fec_enet_rx(struct net_device *ndev, int budget) 1599 { 1600 int pkt_received = 0; 1601 u16 queue_id; 1602 struct fec_enet_private *fep = netdev_priv(ndev); 1603 1604 for_each_set_bit(queue_id, &fep->work_rx, FEC_ENET_MAX_RX_QS) { 1605 int ret; 1606 1607 ret = fec_enet_rx_queue(ndev, 1608 budget - pkt_received, queue_id); 1609 1610 if (ret < budget - pkt_received) 1611 clear_bit(queue_id, &fep->work_rx); 1612 1613 pkt_received += ret; 1614 } 1615 return pkt_received; 1616 } 1617 1618 static bool 1619 fec_enet_collect_events(struct fec_enet_private *fep, uint int_events) 1620 { 1621 if (int_events == 0) 1622 return false; 1623 1624 if (int_events & FEC_ENET_RXF_0) 1625 fep->work_rx |= (1 << 2); 1626 if (int_events & FEC_ENET_RXF_1) 1627 fep->work_rx |= (1 << 0); 1628 if (int_events & FEC_ENET_RXF_2) 1629 fep->work_rx |= (1 << 1); 1630 1631 if (int_events & FEC_ENET_TXF_0) 1632 fep->work_tx |= (1 << 2); 1633 if (int_events & FEC_ENET_TXF_1) 1634 fep->work_tx |= (1 << 0); 1635 if (int_events & FEC_ENET_TXF_2) 1636 fep->work_tx |= (1 << 1); 1637 1638 return true; 1639 } 1640 1641 static irqreturn_t 1642 fec_enet_interrupt(int irq, void *dev_id) 1643 { 1644 struct net_device *ndev = dev_id; 1645 struct fec_enet_private *fep = netdev_priv(ndev); 1646 uint int_events; 1647 irqreturn_t ret = IRQ_NONE; 1648 1649 int_events = readl(fep->hwp + FEC_IEVENT); 1650 1651 /* Don't clear MDIO events, we poll for those */ 1652 int_events &= ~FEC_ENET_MII; 1653 1654 writel(int_events, fep->hwp + FEC_IEVENT); 1655 fec_enet_collect_events(fep, int_events); 1656 1657 if ((fep->work_tx || fep->work_rx) && fep->link) { 1658 ret = IRQ_HANDLED; 1659 1660 if (napi_schedule_prep(&fep->napi)) { 1661 /* Disable interrupts */ 1662 writel(0, fep->hwp + FEC_IMASK); 1663 __napi_schedule(&fep->napi); 1664 } 1665 } 1666 1667 return ret; 1668 } 1669 1670 static int fec_enet_rx_napi(struct napi_struct *napi, int budget) 1671 { 1672 struct net_device *ndev = napi->dev; 1673 struct fec_enet_private *fep = netdev_priv(ndev); 1674 int pkts; 1675 1676 pkts = fec_enet_rx(ndev, budget); 1677 1678 fec_enet_tx(ndev); 1679 1680 if (pkts < budget) { 1681 napi_complete_done(napi, pkts); 1682 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1683 } 1684 return pkts; 1685 } 1686 1687 /* ------------------------------------------------------------------------- */ 1688 static void fec_get_mac(struct net_device *ndev) 1689 { 1690 struct fec_enet_private *fep = netdev_priv(ndev); 1691 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev); 1692 unsigned char *iap, tmpaddr[ETH_ALEN]; 1693 1694 /* 1695 * try to get mac address in following order: 1696 * 1697 * 1) module parameter via kernel command line in form 1698 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0 1699 */ 1700 iap = macaddr; 1701 1702 /* 1703 * 2) from device tree data 1704 */ 1705 if (!is_valid_ether_addr(iap)) { 1706 struct device_node *np = fep->pdev->dev.of_node; 1707 if (np) { 1708 const char *mac = of_get_mac_address(np); 1709 if (!IS_ERR(mac)) 1710 iap = (unsigned char *) mac; 1711 } 1712 } 1713 1714 /* 1715 * 3) from flash or fuse (via platform data) 1716 */ 1717 if (!is_valid_ether_addr(iap)) { 1718 #ifdef CONFIG_M5272 1719 if (FEC_FLASHMAC) 1720 iap = (unsigned char *)FEC_FLASHMAC; 1721 #else 1722 if (pdata) 1723 iap = (unsigned char *)&pdata->mac; 1724 #endif 1725 } 1726 1727 /* 1728 * 4) FEC mac registers set by bootloader 1729 */ 1730 if (!is_valid_ether_addr(iap)) { 1731 *((__be32 *) &tmpaddr[0]) = 1732 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW)); 1733 *((__be16 *) &tmpaddr[4]) = 1734 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16); 1735 iap = &tmpaddr[0]; 1736 } 1737 1738 /* 1739 * 5) random mac address 1740 */ 1741 if (!is_valid_ether_addr(iap)) { 1742 /* Report it and use a random ethernet address instead */ 1743 dev_err(&fep->pdev->dev, "Invalid MAC address: %pM\n", iap); 1744 eth_hw_addr_random(ndev); 1745 dev_info(&fep->pdev->dev, "Using random MAC address: %pM\n", 1746 ndev->dev_addr); 1747 return; 1748 } 1749 1750 memcpy(ndev->dev_addr, iap, ETH_ALEN); 1751 1752 /* Adjust MAC if using macaddr */ 1753 if (iap == macaddr) 1754 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id; 1755 } 1756 1757 /* ------------------------------------------------------------------------- */ 1758 1759 /* 1760 * Phy section 1761 */ 1762 static void fec_enet_adjust_link(struct net_device *ndev) 1763 { 1764 struct fec_enet_private *fep = netdev_priv(ndev); 1765 struct phy_device *phy_dev = ndev->phydev; 1766 int status_change = 0; 1767 1768 /* 1769 * If the netdev is down, or is going down, we're not interested 1770 * in link state events, so just mark our idea of the link as down 1771 * and ignore the event. 1772 */ 1773 if (!netif_running(ndev) || !netif_device_present(ndev)) { 1774 fep->link = 0; 1775 } else if (phy_dev->link) { 1776 if (!fep->link) { 1777 fep->link = phy_dev->link; 1778 status_change = 1; 1779 } 1780 1781 if (fep->full_duplex != phy_dev->duplex) { 1782 fep->full_duplex = phy_dev->duplex; 1783 status_change = 1; 1784 } 1785 1786 if (phy_dev->speed != fep->speed) { 1787 fep->speed = phy_dev->speed; 1788 status_change = 1; 1789 } 1790 1791 /* if any of the above changed restart the FEC */ 1792 if (status_change) { 1793 napi_disable(&fep->napi); 1794 netif_tx_lock_bh(ndev); 1795 fec_restart(ndev); 1796 netif_tx_wake_all_queues(ndev); 1797 netif_tx_unlock_bh(ndev); 1798 napi_enable(&fep->napi); 1799 } 1800 } else { 1801 if (fep->link) { 1802 napi_disable(&fep->napi); 1803 netif_tx_lock_bh(ndev); 1804 fec_stop(ndev); 1805 netif_tx_unlock_bh(ndev); 1806 napi_enable(&fep->napi); 1807 fep->link = phy_dev->link; 1808 status_change = 1; 1809 } 1810 } 1811 1812 if (status_change) 1813 phy_print_status(phy_dev); 1814 } 1815 1816 static int fec_enet_mdio_wait(struct fec_enet_private *fep) 1817 { 1818 uint ievent; 1819 int ret; 1820 1821 ret = readl_poll_timeout_atomic(fep->hwp + FEC_IEVENT, ievent, 1822 ievent & FEC_ENET_MII, 2, 30000); 1823 1824 if (!ret) 1825 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); 1826 1827 return ret; 1828 } 1829 1830 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) 1831 { 1832 struct fec_enet_private *fep = bus->priv; 1833 struct device *dev = &fep->pdev->dev; 1834 int ret = 0, frame_start, frame_addr, frame_op; 1835 bool is_c45 = !!(regnum & MII_ADDR_C45); 1836 1837 ret = pm_runtime_get_sync(dev); 1838 if (ret < 0) 1839 return ret; 1840 1841 if (is_c45) { 1842 frame_start = FEC_MMFR_ST_C45; 1843 1844 /* write address */ 1845 frame_addr = (regnum >> 16); 1846 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE | 1847 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 1848 FEC_MMFR_TA | (regnum & 0xFFFF), 1849 fep->hwp + FEC_MII_DATA); 1850 1851 /* wait for end of transfer */ 1852 ret = fec_enet_mdio_wait(fep); 1853 if (ret) { 1854 netdev_err(fep->netdev, "MDIO address write timeout\n"); 1855 goto out; 1856 } 1857 1858 frame_op = FEC_MMFR_OP_READ_C45; 1859 1860 } else { 1861 /* C22 read */ 1862 frame_op = FEC_MMFR_OP_READ; 1863 frame_start = FEC_MMFR_ST; 1864 frame_addr = regnum; 1865 } 1866 1867 /* start a read op */ 1868 writel(frame_start | frame_op | 1869 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 1870 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); 1871 1872 /* wait for end of transfer */ 1873 ret = fec_enet_mdio_wait(fep); 1874 if (ret) { 1875 netdev_err(fep->netdev, "MDIO read timeout\n"); 1876 goto out; 1877 } 1878 1879 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); 1880 1881 out: 1882 pm_runtime_mark_last_busy(dev); 1883 pm_runtime_put_autosuspend(dev); 1884 1885 return ret; 1886 } 1887 1888 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, 1889 u16 value) 1890 { 1891 struct fec_enet_private *fep = bus->priv; 1892 struct device *dev = &fep->pdev->dev; 1893 int ret, frame_start, frame_addr; 1894 bool is_c45 = !!(regnum & MII_ADDR_C45); 1895 1896 ret = pm_runtime_get_sync(dev); 1897 if (ret < 0) 1898 return ret; 1899 else 1900 ret = 0; 1901 1902 if (is_c45) { 1903 frame_start = FEC_MMFR_ST_C45; 1904 1905 /* write address */ 1906 frame_addr = (regnum >> 16); 1907 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE | 1908 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 1909 FEC_MMFR_TA | (regnum & 0xFFFF), 1910 fep->hwp + FEC_MII_DATA); 1911 1912 /* wait for end of transfer */ 1913 ret = fec_enet_mdio_wait(fep); 1914 if (ret) { 1915 netdev_err(fep->netdev, "MDIO address write timeout\n"); 1916 goto out; 1917 } 1918 } else { 1919 /* C22 write */ 1920 frame_start = FEC_MMFR_ST; 1921 frame_addr = regnum; 1922 } 1923 1924 /* start a write op */ 1925 writel(frame_start | FEC_MMFR_OP_WRITE | 1926 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 1927 FEC_MMFR_TA | FEC_MMFR_DATA(value), 1928 fep->hwp + FEC_MII_DATA); 1929 1930 /* wait for end of transfer */ 1931 ret = fec_enet_mdio_wait(fep); 1932 if (ret) 1933 netdev_err(fep->netdev, "MDIO write timeout\n"); 1934 1935 out: 1936 pm_runtime_mark_last_busy(dev); 1937 pm_runtime_put_autosuspend(dev); 1938 1939 return ret; 1940 } 1941 1942 static int fec_enet_clk_enable(struct net_device *ndev, bool enable) 1943 { 1944 struct fec_enet_private *fep = netdev_priv(ndev); 1945 int ret; 1946 1947 if (enable) { 1948 ret = clk_prepare_enable(fep->clk_enet_out); 1949 if (ret) 1950 return ret; 1951 1952 if (fep->clk_ptp) { 1953 mutex_lock(&fep->ptp_clk_mutex); 1954 ret = clk_prepare_enable(fep->clk_ptp); 1955 if (ret) { 1956 mutex_unlock(&fep->ptp_clk_mutex); 1957 goto failed_clk_ptp; 1958 } else { 1959 fep->ptp_clk_on = true; 1960 } 1961 mutex_unlock(&fep->ptp_clk_mutex); 1962 } 1963 1964 ret = clk_prepare_enable(fep->clk_ref); 1965 if (ret) 1966 goto failed_clk_ref; 1967 1968 phy_reset_after_clk_enable(ndev->phydev); 1969 } else { 1970 clk_disable_unprepare(fep->clk_enet_out); 1971 if (fep->clk_ptp) { 1972 mutex_lock(&fep->ptp_clk_mutex); 1973 clk_disable_unprepare(fep->clk_ptp); 1974 fep->ptp_clk_on = false; 1975 mutex_unlock(&fep->ptp_clk_mutex); 1976 } 1977 clk_disable_unprepare(fep->clk_ref); 1978 } 1979 1980 return 0; 1981 1982 failed_clk_ref: 1983 if (fep->clk_ptp) { 1984 mutex_lock(&fep->ptp_clk_mutex); 1985 clk_disable_unprepare(fep->clk_ptp); 1986 fep->ptp_clk_on = false; 1987 mutex_unlock(&fep->ptp_clk_mutex); 1988 } 1989 failed_clk_ptp: 1990 if (fep->clk_enet_out) 1991 clk_disable_unprepare(fep->clk_enet_out); 1992 1993 return ret; 1994 } 1995 1996 static int fec_enet_mii_probe(struct net_device *ndev) 1997 { 1998 struct fec_enet_private *fep = netdev_priv(ndev); 1999 struct phy_device *phy_dev = NULL; 2000 char mdio_bus_id[MII_BUS_ID_SIZE]; 2001 char phy_name[MII_BUS_ID_SIZE + 3]; 2002 int phy_id; 2003 int dev_id = fep->dev_id; 2004 2005 if (fep->phy_node) { 2006 phy_dev = of_phy_connect(ndev, fep->phy_node, 2007 &fec_enet_adjust_link, 0, 2008 fep->phy_interface); 2009 if (!phy_dev) { 2010 netdev_err(ndev, "Unable to connect to phy\n"); 2011 return -ENODEV; 2012 } 2013 } else { 2014 /* check for attached phy */ 2015 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) { 2016 if (!mdiobus_is_registered_device(fep->mii_bus, phy_id)) 2017 continue; 2018 if (dev_id--) 2019 continue; 2020 strlcpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE); 2021 break; 2022 } 2023 2024 if (phy_id >= PHY_MAX_ADDR) { 2025 netdev_info(ndev, "no PHY, assuming direct connection to switch\n"); 2026 strlcpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); 2027 phy_id = 0; 2028 } 2029 2030 snprintf(phy_name, sizeof(phy_name), 2031 PHY_ID_FMT, mdio_bus_id, phy_id); 2032 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, 2033 fep->phy_interface); 2034 } 2035 2036 if (IS_ERR(phy_dev)) { 2037 netdev_err(ndev, "could not attach to PHY\n"); 2038 return PTR_ERR(phy_dev); 2039 } 2040 2041 /* mask with MAC supported features */ 2042 if (fep->quirks & FEC_QUIRK_HAS_GBIT) { 2043 phy_set_max_speed(phy_dev, 1000); 2044 phy_remove_link_mode(phy_dev, 2045 ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 2046 #if !defined(CONFIG_M5272) 2047 phy_support_sym_pause(phy_dev); 2048 #endif 2049 } 2050 else 2051 phy_set_max_speed(phy_dev, 100); 2052 2053 fep->link = 0; 2054 fep->full_duplex = 0; 2055 2056 phy_attached_info(phy_dev); 2057 2058 return 0; 2059 } 2060 2061 static int fec_enet_mii_init(struct platform_device *pdev) 2062 { 2063 static struct mii_bus *fec0_mii_bus; 2064 struct net_device *ndev = platform_get_drvdata(pdev); 2065 struct fec_enet_private *fep = netdev_priv(ndev); 2066 bool suppress_preamble = false; 2067 struct device_node *node; 2068 int err = -ENXIO; 2069 u32 mii_speed, holdtime; 2070 u32 bus_freq; 2071 2072 /* 2073 * The i.MX28 dual fec interfaces are not equal. 2074 * Here are the differences: 2075 * 2076 * - fec0 supports MII & RMII modes while fec1 only supports RMII 2077 * - fec0 acts as the 1588 time master while fec1 is slave 2078 * - external phys can only be configured by fec0 2079 * 2080 * That is to say fec1 can not work independently. It only works 2081 * when fec0 is working. The reason behind this design is that the 2082 * second interface is added primarily for Switch mode. 2083 * 2084 * Because of the last point above, both phys are attached on fec0 2085 * mdio interface in board design, and need to be configured by 2086 * fec0 mii_bus. 2087 */ 2088 if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) { 2089 /* fec1 uses fec0 mii_bus */ 2090 if (mii_cnt && fec0_mii_bus) { 2091 fep->mii_bus = fec0_mii_bus; 2092 mii_cnt++; 2093 return 0; 2094 } 2095 return -ENOENT; 2096 } 2097 2098 bus_freq = 2500000; /* 2.5MHz by default */ 2099 node = of_get_child_by_name(pdev->dev.of_node, "mdio"); 2100 if (node) { 2101 of_property_read_u32(node, "clock-frequency", &bus_freq); 2102 suppress_preamble = of_property_read_bool(node, 2103 "suppress-preamble"); 2104 } 2105 2106 /* 2107 * Set MII speed (= clk_get_rate() / 2 * phy_speed) 2108 * 2109 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while 2110 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28 2111 * Reference Manual has an error on this, and gets fixed on i.MX6Q 2112 * document. 2113 */ 2114 mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), bus_freq * 2); 2115 if (fep->quirks & FEC_QUIRK_ENET_MAC) 2116 mii_speed--; 2117 if (mii_speed > 63) { 2118 dev_err(&pdev->dev, 2119 "fec clock (%lu) too fast to get right mii speed\n", 2120 clk_get_rate(fep->clk_ipg)); 2121 err = -EINVAL; 2122 goto err_out; 2123 } 2124 2125 /* 2126 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka 2127 * MII_SPEED) register that defines the MDIO output hold time. Earlier 2128 * versions are RAZ there, so just ignore the difference and write the 2129 * register always. 2130 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns. 2131 * HOLDTIME + 1 is the number of clk cycles the fec is holding the 2132 * output. 2133 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive). 2134 * Given that ceil(clkrate / 5000000) <= 64, the calculation for 2135 * holdtime cannot result in a value greater than 3. 2136 */ 2137 holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1; 2138 2139 fep->phy_speed = mii_speed << 1 | holdtime << 8; 2140 2141 if (suppress_preamble) 2142 fep->phy_speed |= BIT(7); 2143 2144 /* Clear MMFR to avoid to generate MII event by writing MSCR. 2145 * MII event generation condition: 2146 * - writing MSCR: 2147 * - mmfr[31:0]_not_zero & mscr[7:0]_is_zero & 2148 * mscr_reg_data_in[7:0] != 0 2149 * - writing MMFR: 2150 * - mscr[7:0]_not_zero 2151 */ 2152 writel(0, fep->hwp + FEC_MII_DATA); 2153 2154 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 2155 2156 /* Clear any pending transaction complete indication */ 2157 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); 2158 2159 fep->mii_bus = mdiobus_alloc(); 2160 if (fep->mii_bus == NULL) { 2161 err = -ENOMEM; 2162 goto err_out; 2163 } 2164 2165 fep->mii_bus->name = "fec_enet_mii_bus"; 2166 fep->mii_bus->read = fec_enet_mdio_read; 2167 fep->mii_bus->write = fec_enet_mdio_write; 2168 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 2169 pdev->name, fep->dev_id + 1); 2170 fep->mii_bus->priv = fep; 2171 fep->mii_bus->parent = &pdev->dev; 2172 2173 err = of_mdiobus_register(fep->mii_bus, node); 2174 of_node_put(node); 2175 if (err) 2176 goto err_out_free_mdiobus; 2177 2178 mii_cnt++; 2179 2180 /* save fec0 mii_bus */ 2181 if (fep->quirks & FEC_QUIRK_SINGLE_MDIO) 2182 fec0_mii_bus = fep->mii_bus; 2183 2184 return 0; 2185 2186 err_out_free_mdiobus: 2187 mdiobus_free(fep->mii_bus); 2188 err_out: 2189 return err; 2190 } 2191 2192 static void fec_enet_mii_remove(struct fec_enet_private *fep) 2193 { 2194 if (--mii_cnt == 0) { 2195 mdiobus_unregister(fep->mii_bus); 2196 mdiobus_free(fep->mii_bus); 2197 } 2198 } 2199 2200 static void fec_enet_get_drvinfo(struct net_device *ndev, 2201 struct ethtool_drvinfo *info) 2202 { 2203 struct fec_enet_private *fep = netdev_priv(ndev); 2204 2205 strlcpy(info->driver, fep->pdev->dev.driver->name, 2206 sizeof(info->driver)); 2207 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info)); 2208 } 2209 2210 static int fec_enet_get_regs_len(struct net_device *ndev) 2211 { 2212 struct fec_enet_private *fep = netdev_priv(ndev); 2213 struct resource *r; 2214 int s = 0; 2215 2216 r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0); 2217 if (r) 2218 s = resource_size(r); 2219 2220 return s; 2221 } 2222 2223 /* List of registers that can be safety be read to dump them with ethtool */ 2224 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 2225 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \ 2226 defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST) 2227 static __u32 fec_enet_register_version = 2; 2228 static u32 fec_enet_register_offset[] = { 2229 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0, 2230 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL, 2231 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1, 2232 FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH, 2233 FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, 2234 FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1, 2235 FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2, 2236 FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0, 2237 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM, 2238 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2, 2239 FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1, 2240 FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME, 2241 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT, 2242 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG, 2243 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255, 2244 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047, 2245 RMON_T_P_GTE2048, RMON_T_OCTETS, 2246 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF, 2247 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE, 2248 IEEE_T_FDXFC, IEEE_T_OCTETS_OK, 2249 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN, 2250 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB, 2251 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255, 2252 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047, 2253 RMON_R_P_GTE2048, RMON_R_OCTETS, 2254 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR, 2255 IEEE_R_FDXFC, IEEE_R_OCTETS_OK 2256 }; 2257 #else 2258 static __u32 fec_enet_register_version = 1; 2259 static u32 fec_enet_register_offset[] = { 2260 FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0, 2261 FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0, 2262 FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED, 2263 FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL, 2264 FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, 2265 FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0, 2266 FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0, 2267 FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0, 2268 FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2 2269 }; 2270 #endif 2271 2272 static void fec_enet_get_regs(struct net_device *ndev, 2273 struct ethtool_regs *regs, void *regbuf) 2274 { 2275 struct fec_enet_private *fep = netdev_priv(ndev); 2276 u32 __iomem *theregs = (u32 __iomem *)fep->hwp; 2277 struct device *dev = &fep->pdev->dev; 2278 u32 *buf = (u32 *)regbuf; 2279 u32 i, off; 2280 int ret; 2281 2282 ret = pm_runtime_get_sync(dev); 2283 if (ret < 0) 2284 return; 2285 2286 regs->version = fec_enet_register_version; 2287 2288 memset(buf, 0, regs->len); 2289 2290 for (i = 0; i < ARRAY_SIZE(fec_enet_register_offset); i++) { 2291 off = fec_enet_register_offset[i]; 2292 2293 if ((off == FEC_R_BOUND || off == FEC_R_FSTART) && 2294 !(fep->quirks & FEC_QUIRK_HAS_FRREG)) 2295 continue; 2296 2297 off >>= 2; 2298 buf[off] = readl(&theregs[off]); 2299 } 2300 2301 pm_runtime_mark_last_busy(dev); 2302 pm_runtime_put_autosuspend(dev); 2303 } 2304 2305 static int fec_enet_get_ts_info(struct net_device *ndev, 2306 struct ethtool_ts_info *info) 2307 { 2308 struct fec_enet_private *fep = netdev_priv(ndev); 2309 2310 if (fep->bufdesc_ex) { 2311 2312 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 2313 SOF_TIMESTAMPING_RX_SOFTWARE | 2314 SOF_TIMESTAMPING_SOFTWARE | 2315 SOF_TIMESTAMPING_TX_HARDWARE | 2316 SOF_TIMESTAMPING_RX_HARDWARE | 2317 SOF_TIMESTAMPING_RAW_HARDWARE; 2318 if (fep->ptp_clock) 2319 info->phc_index = ptp_clock_index(fep->ptp_clock); 2320 else 2321 info->phc_index = -1; 2322 2323 info->tx_types = (1 << HWTSTAMP_TX_OFF) | 2324 (1 << HWTSTAMP_TX_ON); 2325 2326 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 2327 (1 << HWTSTAMP_FILTER_ALL); 2328 return 0; 2329 } else { 2330 return ethtool_op_get_ts_info(ndev, info); 2331 } 2332 } 2333 2334 #if !defined(CONFIG_M5272) 2335 2336 static void fec_enet_get_pauseparam(struct net_device *ndev, 2337 struct ethtool_pauseparam *pause) 2338 { 2339 struct fec_enet_private *fep = netdev_priv(ndev); 2340 2341 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0; 2342 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0; 2343 pause->rx_pause = pause->tx_pause; 2344 } 2345 2346 static int fec_enet_set_pauseparam(struct net_device *ndev, 2347 struct ethtool_pauseparam *pause) 2348 { 2349 struct fec_enet_private *fep = netdev_priv(ndev); 2350 2351 if (!ndev->phydev) 2352 return -ENODEV; 2353 2354 if (pause->tx_pause != pause->rx_pause) { 2355 netdev_info(ndev, 2356 "hardware only support enable/disable both tx and rx"); 2357 return -EINVAL; 2358 } 2359 2360 fep->pause_flag = 0; 2361 2362 /* tx pause must be same as rx pause */ 2363 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0; 2364 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0; 2365 2366 phy_set_sym_pause(ndev->phydev, pause->rx_pause, pause->tx_pause, 2367 pause->autoneg); 2368 2369 if (pause->autoneg) { 2370 if (netif_running(ndev)) 2371 fec_stop(ndev); 2372 phy_start_aneg(ndev->phydev); 2373 } 2374 if (netif_running(ndev)) { 2375 napi_disable(&fep->napi); 2376 netif_tx_lock_bh(ndev); 2377 fec_restart(ndev); 2378 netif_tx_wake_all_queues(ndev); 2379 netif_tx_unlock_bh(ndev); 2380 napi_enable(&fep->napi); 2381 } 2382 2383 return 0; 2384 } 2385 2386 static const struct fec_stat { 2387 char name[ETH_GSTRING_LEN]; 2388 u16 offset; 2389 } fec_stats[] = { 2390 /* RMON TX */ 2391 { "tx_dropped", RMON_T_DROP }, 2392 { "tx_packets", RMON_T_PACKETS }, 2393 { "tx_broadcast", RMON_T_BC_PKT }, 2394 { "tx_multicast", RMON_T_MC_PKT }, 2395 { "tx_crc_errors", RMON_T_CRC_ALIGN }, 2396 { "tx_undersize", RMON_T_UNDERSIZE }, 2397 { "tx_oversize", RMON_T_OVERSIZE }, 2398 { "tx_fragment", RMON_T_FRAG }, 2399 { "tx_jabber", RMON_T_JAB }, 2400 { "tx_collision", RMON_T_COL }, 2401 { "tx_64byte", RMON_T_P64 }, 2402 { "tx_65to127byte", RMON_T_P65TO127 }, 2403 { "tx_128to255byte", RMON_T_P128TO255 }, 2404 { "tx_256to511byte", RMON_T_P256TO511 }, 2405 { "tx_512to1023byte", RMON_T_P512TO1023 }, 2406 { "tx_1024to2047byte", RMON_T_P1024TO2047 }, 2407 { "tx_GTE2048byte", RMON_T_P_GTE2048 }, 2408 { "tx_octets", RMON_T_OCTETS }, 2409 2410 /* IEEE TX */ 2411 { "IEEE_tx_drop", IEEE_T_DROP }, 2412 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK }, 2413 { "IEEE_tx_1col", IEEE_T_1COL }, 2414 { "IEEE_tx_mcol", IEEE_T_MCOL }, 2415 { "IEEE_tx_def", IEEE_T_DEF }, 2416 { "IEEE_tx_lcol", IEEE_T_LCOL }, 2417 { "IEEE_tx_excol", IEEE_T_EXCOL }, 2418 { "IEEE_tx_macerr", IEEE_T_MACERR }, 2419 { "IEEE_tx_cserr", IEEE_T_CSERR }, 2420 { "IEEE_tx_sqe", IEEE_T_SQE }, 2421 { "IEEE_tx_fdxfc", IEEE_T_FDXFC }, 2422 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK }, 2423 2424 /* RMON RX */ 2425 { "rx_packets", RMON_R_PACKETS }, 2426 { "rx_broadcast", RMON_R_BC_PKT }, 2427 { "rx_multicast", RMON_R_MC_PKT }, 2428 { "rx_crc_errors", RMON_R_CRC_ALIGN }, 2429 { "rx_undersize", RMON_R_UNDERSIZE }, 2430 { "rx_oversize", RMON_R_OVERSIZE }, 2431 { "rx_fragment", RMON_R_FRAG }, 2432 { "rx_jabber", RMON_R_JAB }, 2433 { "rx_64byte", RMON_R_P64 }, 2434 { "rx_65to127byte", RMON_R_P65TO127 }, 2435 { "rx_128to255byte", RMON_R_P128TO255 }, 2436 { "rx_256to511byte", RMON_R_P256TO511 }, 2437 { "rx_512to1023byte", RMON_R_P512TO1023 }, 2438 { "rx_1024to2047byte", RMON_R_P1024TO2047 }, 2439 { "rx_GTE2048byte", RMON_R_P_GTE2048 }, 2440 { "rx_octets", RMON_R_OCTETS }, 2441 2442 /* IEEE RX */ 2443 { "IEEE_rx_drop", IEEE_R_DROP }, 2444 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK }, 2445 { "IEEE_rx_crc", IEEE_R_CRC }, 2446 { "IEEE_rx_align", IEEE_R_ALIGN }, 2447 { "IEEE_rx_macerr", IEEE_R_MACERR }, 2448 { "IEEE_rx_fdxfc", IEEE_R_FDXFC }, 2449 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK }, 2450 }; 2451 2452 #define FEC_STATS_SIZE (ARRAY_SIZE(fec_stats) * sizeof(u64)) 2453 2454 static void fec_enet_update_ethtool_stats(struct net_device *dev) 2455 { 2456 struct fec_enet_private *fep = netdev_priv(dev); 2457 int i; 2458 2459 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2460 fep->ethtool_stats[i] = readl(fep->hwp + fec_stats[i].offset); 2461 } 2462 2463 static void fec_enet_get_ethtool_stats(struct net_device *dev, 2464 struct ethtool_stats *stats, u64 *data) 2465 { 2466 struct fec_enet_private *fep = netdev_priv(dev); 2467 2468 if (netif_running(dev)) 2469 fec_enet_update_ethtool_stats(dev); 2470 2471 memcpy(data, fep->ethtool_stats, FEC_STATS_SIZE); 2472 } 2473 2474 static void fec_enet_get_strings(struct net_device *netdev, 2475 u32 stringset, u8 *data) 2476 { 2477 int i; 2478 switch (stringset) { 2479 case ETH_SS_STATS: 2480 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2481 memcpy(data + i * ETH_GSTRING_LEN, 2482 fec_stats[i].name, ETH_GSTRING_LEN); 2483 break; 2484 } 2485 } 2486 2487 static int fec_enet_get_sset_count(struct net_device *dev, int sset) 2488 { 2489 switch (sset) { 2490 case ETH_SS_STATS: 2491 return ARRAY_SIZE(fec_stats); 2492 default: 2493 return -EOPNOTSUPP; 2494 } 2495 } 2496 2497 static void fec_enet_clear_ethtool_stats(struct net_device *dev) 2498 { 2499 struct fec_enet_private *fep = netdev_priv(dev); 2500 int i; 2501 2502 /* Disable MIB statistics counters */ 2503 writel(FEC_MIB_CTRLSTAT_DISABLE, fep->hwp + FEC_MIB_CTRLSTAT); 2504 2505 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2506 writel(0, fep->hwp + fec_stats[i].offset); 2507 2508 /* Don't disable MIB statistics counters */ 2509 writel(0, fep->hwp + FEC_MIB_CTRLSTAT); 2510 } 2511 2512 #else /* !defined(CONFIG_M5272) */ 2513 #define FEC_STATS_SIZE 0 2514 static inline void fec_enet_update_ethtool_stats(struct net_device *dev) 2515 { 2516 } 2517 2518 static inline void fec_enet_clear_ethtool_stats(struct net_device *dev) 2519 { 2520 } 2521 #endif /* !defined(CONFIG_M5272) */ 2522 2523 /* ITR clock source is enet system clock (clk_ahb). 2524 * TCTT unit is cycle_ns * 64 cycle 2525 * So, the ICTT value = X us / (cycle_ns * 64) 2526 */ 2527 static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us) 2528 { 2529 struct fec_enet_private *fep = netdev_priv(ndev); 2530 2531 return us * (fep->itr_clk_rate / 64000) / 1000; 2532 } 2533 2534 /* Set threshold for interrupt coalescing */ 2535 static void fec_enet_itr_coal_set(struct net_device *ndev) 2536 { 2537 struct fec_enet_private *fep = netdev_priv(ndev); 2538 int rx_itr, tx_itr; 2539 2540 /* Must be greater than zero to avoid unpredictable behavior */ 2541 if (!fep->rx_time_itr || !fep->rx_pkts_itr || 2542 !fep->tx_time_itr || !fep->tx_pkts_itr) 2543 return; 2544 2545 /* Select enet system clock as Interrupt Coalescing 2546 * timer Clock Source 2547 */ 2548 rx_itr = FEC_ITR_CLK_SEL; 2549 tx_itr = FEC_ITR_CLK_SEL; 2550 2551 /* set ICFT and ICTT */ 2552 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr); 2553 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr)); 2554 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr); 2555 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr)); 2556 2557 rx_itr |= FEC_ITR_EN; 2558 tx_itr |= FEC_ITR_EN; 2559 2560 writel(tx_itr, fep->hwp + FEC_TXIC0); 2561 writel(rx_itr, fep->hwp + FEC_RXIC0); 2562 if (fep->quirks & FEC_QUIRK_HAS_AVB) { 2563 writel(tx_itr, fep->hwp + FEC_TXIC1); 2564 writel(rx_itr, fep->hwp + FEC_RXIC1); 2565 writel(tx_itr, fep->hwp + FEC_TXIC2); 2566 writel(rx_itr, fep->hwp + FEC_RXIC2); 2567 } 2568 } 2569 2570 static int 2571 fec_enet_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec) 2572 { 2573 struct fec_enet_private *fep = netdev_priv(ndev); 2574 2575 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) 2576 return -EOPNOTSUPP; 2577 2578 ec->rx_coalesce_usecs = fep->rx_time_itr; 2579 ec->rx_max_coalesced_frames = fep->rx_pkts_itr; 2580 2581 ec->tx_coalesce_usecs = fep->tx_time_itr; 2582 ec->tx_max_coalesced_frames = fep->tx_pkts_itr; 2583 2584 return 0; 2585 } 2586 2587 static int 2588 fec_enet_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec) 2589 { 2590 struct fec_enet_private *fep = netdev_priv(ndev); 2591 struct device *dev = &fep->pdev->dev; 2592 unsigned int cycle; 2593 2594 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) 2595 return -EOPNOTSUPP; 2596 2597 if (ec->rx_max_coalesced_frames > 255) { 2598 dev_err(dev, "Rx coalesced frames exceed hardware limitation\n"); 2599 return -EINVAL; 2600 } 2601 2602 if (ec->tx_max_coalesced_frames > 255) { 2603 dev_err(dev, "Tx coalesced frame exceed hardware limitation\n"); 2604 return -EINVAL; 2605 } 2606 2607 cycle = fec_enet_us_to_itr_clock(ndev, ec->rx_coalesce_usecs); 2608 if (cycle > 0xFFFF) { 2609 dev_err(dev, "Rx coalesced usec exceed hardware limitation\n"); 2610 return -EINVAL; 2611 } 2612 2613 cycle = fec_enet_us_to_itr_clock(ndev, ec->tx_coalesce_usecs); 2614 if (cycle > 0xFFFF) { 2615 dev_err(dev, "Tx coalesced usec exceed hardware limitation\n"); 2616 return -EINVAL; 2617 } 2618 2619 fep->rx_time_itr = ec->rx_coalesce_usecs; 2620 fep->rx_pkts_itr = ec->rx_max_coalesced_frames; 2621 2622 fep->tx_time_itr = ec->tx_coalesce_usecs; 2623 fep->tx_pkts_itr = ec->tx_max_coalesced_frames; 2624 2625 fec_enet_itr_coal_set(ndev); 2626 2627 return 0; 2628 } 2629 2630 static void fec_enet_itr_coal_init(struct net_device *ndev) 2631 { 2632 struct ethtool_coalesce ec; 2633 2634 ec.rx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT; 2635 ec.rx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT; 2636 2637 ec.tx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT; 2638 ec.tx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT; 2639 2640 fec_enet_set_coalesce(ndev, &ec); 2641 } 2642 2643 static int fec_enet_get_tunable(struct net_device *netdev, 2644 const struct ethtool_tunable *tuna, 2645 void *data) 2646 { 2647 struct fec_enet_private *fep = netdev_priv(netdev); 2648 int ret = 0; 2649 2650 switch (tuna->id) { 2651 case ETHTOOL_RX_COPYBREAK: 2652 *(u32 *)data = fep->rx_copybreak; 2653 break; 2654 default: 2655 ret = -EINVAL; 2656 break; 2657 } 2658 2659 return ret; 2660 } 2661 2662 static int fec_enet_set_tunable(struct net_device *netdev, 2663 const struct ethtool_tunable *tuna, 2664 const void *data) 2665 { 2666 struct fec_enet_private *fep = netdev_priv(netdev); 2667 int ret = 0; 2668 2669 switch (tuna->id) { 2670 case ETHTOOL_RX_COPYBREAK: 2671 fep->rx_copybreak = *(u32 *)data; 2672 break; 2673 default: 2674 ret = -EINVAL; 2675 break; 2676 } 2677 2678 return ret; 2679 } 2680 2681 static void 2682 fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2683 { 2684 struct fec_enet_private *fep = netdev_priv(ndev); 2685 2686 if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) { 2687 wol->supported = WAKE_MAGIC; 2688 wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0; 2689 } else { 2690 wol->supported = wol->wolopts = 0; 2691 } 2692 } 2693 2694 static int 2695 fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2696 { 2697 struct fec_enet_private *fep = netdev_priv(ndev); 2698 2699 if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET)) 2700 return -EINVAL; 2701 2702 if (wol->wolopts & ~WAKE_MAGIC) 2703 return -EINVAL; 2704 2705 device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC); 2706 if (device_may_wakeup(&ndev->dev)) { 2707 fep->wol_flag |= FEC_WOL_FLAG_ENABLE; 2708 if (fep->irq[0] > 0) 2709 enable_irq_wake(fep->irq[0]); 2710 } else { 2711 fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE); 2712 if (fep->irq[0] > 0) 2713 disable_irq_wake(fep->irq[0]); 2714 } 2715 2716 return 0; 2717 } 2718 2719 static const struct ethtool_ops fec_enet_ethtool_ops = { 2720 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 2721 ETHTOOL_COALESCE_MAX_FRAMES, 2722 .get_drvinfo = fec_enet_get_drvinfo, 2723 .get_regs_len = fec_enet_get_regs_len, 2724 .get_regs = fec_enet_get_regs, 2725 .nway_reset = phy_ethtool_nway_reset, 2726 .get_link = ethtool_op_get_link, 2727 .get_coalesce = fec_enet_get_coalesce, 2728 .set_coalesce = fec_enet_set_coalesce, 2729 #ifndef CONFIG_M5272 2730 .get_pauseparam = fec_enet_get_pauseparam, 2731 .set_pauseparam = fec_enet_set_pauseparam, 2732 .get_strings = fec_enet_get_strings, 2733 .get_ethtool_stats = fec_enet_get_ethtool_stats, 2734 .get_sset_count = fec_enet_get_sset_count, 2735 #endif 2736 .get_ts_info = fec_enet_get_ts_info, 2737 .get_tunable = fec_enet_get_tunable, 2738 .set_tunable = fec_enet_set_tunable, 2739 .get_wol = fec_enet_get_wol, 2740 .set_wol = fec_enet_set_wol, 2741 .get_link_ksettings = phy_ethtool_get_link_ksettings, 2742 .set_link_ksettings = phy_ethtool_set_link_ksettings, 2743 }; 2744 2745 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) 2746 { 2747 struct fec_enet_private *fep = netdev_priv(ndev); 2748 struct phy_device *phydev = ndev->phydev; 2749 2750 if (!netif_running(ndev)) 2751 return -EINVAL; 2752 2753 if (!phydev) 2754 return -ENODEV; 2755 2756 if (fep->bufdesc_ex) { 2757 if (cmd == SIOCSHWTSTAMP) 2758 return fec_ptp_set(ndev, rq); 2759 if (cmd == SIOCGHWTSTAMP) 2760 return fec_ptp_get(ndev, rq); 2761 } 2762 2763 return phy_mii_ioctl(phydev, rq, cmd); 2764 } 2765 2766 static void fec_enet_free_buffers(struct net_device *ndev) 2767 { 2768 struct fec_enet_private *fep = netdev_priv(ndev); 2769 unsigned int i; 2770 struct sk_buff *skb; 2771 struct bufdesc *bdp; 2772 struct fec_enet_priv_tx_q *txq; 2773 struct fec_enet_priv_rx_q *rxq; 2774 unsigned int q; 2775 2776 for (q = 0; q < fep->num_rx_queues; q++) { 2777 rxq = fep->rx_queue[q]; 2778 bdp = rxq->bd.base; 2779 for (i = 0; i < rxq->bd.ring_size; i++) { 2780 skb = rxq->rx_skbuff[i]; 2781 rxq->rx_skbuff[i] = NULL; 2782 if (skb) { 2783 dma_unmap_single(&fep->pdev->dev, 2784 fec32_to_cpu(bdp->cbd_bufaddr), 2785 FEC_ENET_RX_FRSIZE - fep->rx_align, 2786 DMA_FROM_DEVICE); 2787 dev_kfree_skb(skb); 2788 } 2789 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 2790 } 2791 } 2792 2793 for (q = 0; q < fep->num_tx_queues; q++) { 2794 txq = fep->tx_queue[q]; 2795 for (i = 0; i < txq->bd.ring_size; i++) { 2796 kfree(txq->tx_bounce[i]); 2797 txq->tx_bounce[i] = NULL; 2798 skb = txq->tx_skbuff[i]; 2799 txq->tx_skbuff[i] = NULL; 2800 dev_kfree_skb(skb); 2801 } 2802 } 2803 } 2804 2805 static void fec_enet_free_queue(struct net_device *ndev) 2806 { 2807 struct fec_enet_private *fep = netdev_priv(ndev); 2808 int i; 2809 struct fec_enet_priv_tx_q *txq; 2810 2811 for (i = 0; i < fep->num_tx_queues; i++) 2812 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) { 2813 txq = fep->tx_queue[i]; 2814 dma_free_coherent(&fep->pdev->dev, 2815 txq->bd.ring_size * TSO_HEADER_SIZE, 2816 txq->tso_hdrs, 2817 txq->tso_hdrs_dma); 2818 } 2819 2820 for (i = 0; i < fep->num_rx_queues; i++) 2821 kfree(fep->rx_queue[i]); 2822 for (i = 0; i < fep->num_tx_queues; i++) 2823 kfree(fep->tx_queue[i]); 2824 } 2825 2826 static int fec_enet_alloc_queue(struct net_device *ndev) 2827 { 2828 struct fec_enet_private *fep = netdev_priv(ndev); 2829 int i; 2830 int ret = 0; 2831 struct fec_enet_priv_tx_q *txq; 2832 2833 for (i = 0; i < fep->num_tx_queues; i++) { 2834 txq = kzalloc(sizeof(*txq), GFP_KERNEL); 2835 if (!txq) { 2836 ret = -ENOMEM; 2837 goto alloc_failed; 2838 } 2839 2840 fep->tx_queue[i] = txq; 2841 txq->bd.ring_size = TX_RING_SIZE; 2842 fep->total_tx_ring_size += fep->tx_queue[i]->bd.ring_size; 2843 2844 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS; 2845 txq->tx_wake_threshold = 2846 (txq->bd.ring_size - txq->tx_stop_threshold) / 2; 2847 2848 txq->tso_hdrs = dma_alloc_coherent(&fep->pdev->dev, 2849 txq->bd.ring_size * TSO_HEADER_SIZE, 2850 &txq->tso_hdrs_dma, 2851 GFP_KERNEL); 2852 if (!txq->tso_hdrs) { 2853 ret = -ENOMEM; 2854 goto alloc_failed; 2855 } 2856 } 2857 2858 for (i = 0; i < fep->num_rx_queues; i++) { 2859 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]), 2860 GFP_KERNEL); 2861 if (!fep->rx_queue[i]) { 2862 ret = -ENOMEM; 2863 goto alloc_failed; 2864 } 2865 2866 fep->rx_queue[i]->bd.ring_size = RX_RING_SIZE; 2867 fep->total_rx_ring_size += fep->rx_queue[i]->bd.ring_size; 2868 } 2869 return ret; 2870 2871 alloc_failed: 2872 fec_enet_free_queue(ndev); 2873 return ret; 2874 } 2875 2876 static int 2877 fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue) 2878 { 2879 struct fec_enet_private *fep = netdev_priv(ndev); 2880 unsigned int i; 2881 struct sk_buff *skb; 2882 struct bufdesc *bdp; 2883 struct fec_enet_priv_rx_q *rxq; 2884 2885 rxq = fep->rx_queue[queue]; 2886 bdp = rxq->bd.base; 2887 for (i = 0; i < rxq->bd.ring_size; i++) { 2888 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE); 2889 if (!skb) 2890 goto err_alloc; 2891 2892 if (fec_enet_new_rxbdp(ndev, bdp, skb)) { 2893 dev_kfree_skb(skb); 2894 goto err_alloc; 2895 } 2896 2897 rxq->rx_skbuff[i] = skb; 2898 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); 2899 2900 if (fep->bufdesc_ex) { 2901 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 2902 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); 2903 } 2904 2905 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 2906 } 2907 2908 /* Set the last buffer to wrap. */ 2909 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); 2910 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 2911 return 0; 2912 2913 err_alloc: 2914 fec_enet_free_buffers(ndev); 2915 return -ENOMEM; 2916 } 2917 2918 static int 2919 fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue) 2920 { 2921 struct fec_enet_private *fep = netdev_priv(ndev); 2922 unsigned int i; 2923 struct bufdesc *bdp; 2924 struct fec_enet_priv_tx_q *txq; 2925 2926 txq = fep->tx_queue[queue]; 2927 bdp = txq->bd.base; 2928 for (i = 0; i < txq->bd.ring_size; i++) { 2929 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); 2930 if (!txq->tx_bounce[i]) 2931 goto err_alloc; 2932 2933 bdp->cbd_sc = cpu_to_fec16(0); 2934 bdp->cbd_bufaddr = cpu_to_fec32(0); 2935 2936 if (fep->bufdesc_ex) { 2937 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 2938 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_TX_INT); 2939 } 2940 2941 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 2942 } 2943 2944 /* Set the last buffer to wrap. */ 2945 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); 2946 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 2947 2948 return 0; 2949 2950 err_alloc: 2951 fec_enet_free_buffers(ndev); 2952 return -ENOMEM; 2953 } 2954 2955 static int fec_enet_alloc_buffers(struct net_device *ndev) 2956 { 2957 struct fec_enet_private *fep = netdev_priv(ndev); 2958 unsigned int i; 2959 2960 for (i = 0; i < fep->num_rx_queues; i++) 2961 if (fec_enet_alloc_rxq_buffers(ndev, i)) 2962 return -ENOMEM; 2963 2964 for (i = 0; i < fep->num_tx_queues; i++) 2965 if (fec_enet_alloc_txq_buffers(ndev, i)) 2966 return -ENOMEM; 2967 return 0; 2968 } 2969 2970 static int 2971 fec_enet_open(struct net_device *ndev) 2972 { 2973 struct fec_enet_private *fep = netdev_priv(ndev); 2974 int ret; 2975 bool reset_again; 2976 2977 ret = pm_runtime_get_sync(&fep->pdev->dev); 2978 if (ret < 0) 2979 return ret; 2980 2981 pinctrl_pm_select_default_state(&fep->pdev->dev); 2982 ret = fec_enet_clk_enable(ndev, true); 2983 if (ret) 2984 goto clk_enable; 2985 2986 /* During the first fec_enet_open call the PHY isn't probed at this 2987 * point. Therefore the phy_reset_after_clk_enable() call within 2988 * fec_enet_clk_enable() fails. As we need this reset in order to be 2989 * sure the PHY is working correctly we check if we need to reset again 2990 * later when the PHY is probed 2991 */ 2992 if (ndev->phydev && ndev->phydev->drv) 2993 reset_again = false; 2994 else 2995 reset_again = true; 2996 2997 /* I should reset the ring buffers here, but I don't yet know 2998 * a simple way to do that. 2999 */ 3000 3001 ret = fec_enet_alloc_buffers(ndev); 3002 if (ret) 3003 goto err_enet_alloc; 3004 3005 /* Init MAC prior to mii bus probe */ 3006 fec_restart(ndev); 3007 3008 /* Probe and connect to PHY when open the interface */ 3009 ret = fec_enet_mii_probe(ndev); 3010 if (ret) 3011 goto err_enet_mii_probe; 3012 3013 /* Call phy_reset_after_clk_enable() again if it failed during 3014 * phy_reset_after_clk_enable() before because the PHY wasn't probed. 3015 */ 3016 if (reset_again) 3017 phy_reset_after_clk_enable(ndev->phydev); 3018 3019 if (fep->quirks & FEC_QUIRK_ERR006687) 3020 imx6q_cpuidle_fec_irqs_used(); 3021 3022 napi_enable(&fep->napi); 3023 phy_start(ndev->phydev); 3024 netif_tx_start_all_queues(ndev); 3025 3026 device_set_wakeup_enable(&ndev->dev, fep->wol_flag & 3027 FEC_WOL_FLAG_ENABLE); 3028 3029 return 0; 3030 3031 err_enet_mii_probe: 3032 fec_enet_free_buffers(ndev); 3033 err_enet_alloc: 3034 fec_enet_clk_enable(ndev, false); 3035 clk_enable: 3036 pm_runtime_mark_last_busy(&fep->pdev->dev); 3037 pm_runtime_put_autosuspend(&fep->pdev->dev); 3038 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3039 return ret; 3040 } 3041 3042 static int 3043 fec_enet_close(struct net_device *ndev) 3044 { 3045 struct fec_enet_private *fep = netdev_priv(ndev); 3046 3047 phy_stop(ndev->phydev); 3048 3049 if (netif_device_present(ndev)) { 3050 napi_disable(&fep->napi); 3051 netif_tx_disable(ndev); 3052 fec_stop(ndev); 3053 } 3054 3055 phy_disconnect(ndev->phydev); 3056 3057 if (fep->quirks & FEC_QUIRK_ERR006687) 3058 imx6q_cpuidle_fec_irqs_unused(); 3059 3060 fec_enet_update_ethtool_stats(ndev); 3061 3062 fec_enet_clk_enable(ndev, false); 3063 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3064 pm_runtime_mark_last_busy(&fep->pdev->dev); 3065 pm_runtime_put_autosuspend(&fep->pdev->dev); 3066 3067 fec_enet_free_buffers(ndev); 3068 3069 return 0; 3070 } 3071 3072 /* Set or clear the multicast filter for this adaptor. 3073 * Skeleton taken from sunlance driver. 3074 * The CPM Ethernet implementation allows Multicast as well as individual 3075 * MAC address filtering. Some of the drivers check to make sure it is 3076 * a group multicast address, and discard those that are not. I guess I 3077 * will do the same for now, but just remove the test if you want 3078 * individual filtering as well (do the upper net layers want or support 3079 * this kind of feature?). 3080 */ 3081 3082 #define FEC_HASH_BITS 6 /* #bits in hash */ 3083 3084 static void set_multicast_list(struct net_device *ndev) 3085 { 3086 struct fec_enet_private *fep = netdev_priv(ndev); 3087 struct netdev_hw_addr *ha; 3088 unsigned int crc, tmp; 3089 unsigned char hash; 3090 unsigned int hash_high = 0, hash_low = 0; 3091 3092 if (ndev->flags & IFF_PROMISC) { 3093 tmp = readl(fep->hwp + FEC_R_CNTRL); 3094 tmp |= 0x8; 3095 writel(tmp, fep->hwp + FEC_R_CNTRL); 3096 return; 3097 } 3098 3099 tmp = readl(fep->hwp + FEC_R_CNTRL); 3100 tmp &= ~0x8; 3101 writel(tmp, fep->hwp + FEC_R_CNTRL); 3102 3103 if (ndev->flags & IFF_ALLMULTI) { 3104 /* Catch all multicast addresses, so set the 3105 * filter to all 1's 3106 */ 3107 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 3108 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 3109 3110 return; 3111 } 3112 3113 /* Add the addresses in hash register */ 3114 netdev_for_each_mc_addr(ha, ndev) { 3115 /* calculate crc32 value of mac address */ 3116 crc = ether_crc_le(ndev->addr_len, ha->addr); 3117 3118 /* only upper 6 bits (FEC_HASH_BITS) are used 3119 * which point to specific bit in the hash registers 3120 */ 3121 hash = (crc >> (32 - FEC_HASH_BITS)) & 0x3f; 3122 3123 if (hash > 31) 3124 hash_high |= 1 << (hash - 32); 3125 else 3126 hash_low |= 1 << hash; 3127 } 3128 3129 writel(hash_high, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 3130 writel(hash_low, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 3131 } 3132 3133 /* Set a MAC change in hardware. */ 3134 static int 3135 fec_set_mac_address(struct net_device *ndev, void *p) 3136 { 3137 struct fec_enet_private *fep = netdev_priv(ndev); 3138 struct sockaddr *addr = p; 3139 3140 if (addr) { 3141 if (!is_valid_ether_addr(addr->sa_data)) 3142 return -EADDRNOTAVAIL; 3143 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len); 3144 } 3145 3146 /* Add netif status check here to avoid system hang in below case: 3147 * ifconfig ethx down; ifconfig ethx hw ether xx:xx:xx:xx:xx:xx; 3148 * After ethx down, fec all clocks are gated off and then register 3149 * access causes system hang. 3150 */ 3151 if (!netif_running(ndev)) 3152 return 0; 3153 3154 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) | 3155 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24), 3156 fep->hwp + FEC_ADDR_LOW); 3157 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24), 3158 fep->hwp + FEC_ADDR_HIGH); 3159 return 0; 3160 } 3161 3162 #ifdef CONFIG_NET_POLL_CONTROLLER 3163 /** 3164 * fec_poll_controller - FEC Poll controller function 3165 * @dev: The FEC network adapter 3166 * 3167 * Polled functionality used by netconsole and others in non interrupt mode 3168 * 3169 */ 3170 static void fec_poll_controller(struct net_device *dev) 3171 { 3172 int i; 3173 struct fec_enet_private *fep = netdev_priv(dev); 3174 3175 for (i = 0; i < FEC_IRQ_NUM; i++) { 3176 if (fep->irq[i] > 0) { 3177 disable_irq(fep->irq[i]); 3178 fec_enet_interrupt(fep->irq[i], dev); 3179 enable_irq(fep->irq[i]); 3180 } 3181 } 3182 } 3183 #endif 3184 3185 static inline void fec_enet_set_netdev_features(struct net_device *netdev, 3186 netdev_features_t features) 3187 { 3188 struct fec_enet_private *fep = netdev_priv(netdev); 3189 netdev_features_t changed = features ^ netdev->features; 3190 3191 netdev->features = features; 3192 3193 /* Receive checksum has been changed */ 3194 if (changed & NETIF_F_RXCSUM) { 3195 if (features & NETIF_F_RXCSUM) 3196 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 3197 else 3198 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED; 3199 } 3200 } 3201 3202 static int fec_set_features(struct net_device *netdev, 3203 netdev_features_t features) 3204 { 3205 struct fec_enet_private *fep = netdev_priv(netdev); 3206 netdev_features_t changed = features ^ netdev->features; 3207 3208 if (netif_running(netdev) && changed & NETIF_F_RXCSUM) { 3209 napi_disable(&fep->napi); 3210 netif_tx_lock_bh(netdev); 3211 fec_stop(netdev); 3212 fec_enet_set_netdev_features(netdev, features); 3213 fec_restart(netdev); 3214 netif_tx_wake_all_queues(netdev); 3215 netif_tx_unlock_bh(netdev); 3216 napi_enable(&fep->napi); 3217 } else { 3218 fec_enet_set_netdev_features(netdev, features); 3219 } 3220 3221 return 0; 3222 } 3223 3224 static const struct net_device_ops fec_netdev_ops = { 3225 .ndo_open = fec_enet_open, 3226 .ndo_stop = fec_enet_close, 3227 .ndo_start_xmit = fec_enet_start_xmit, 3228 .ndo_set_rx_mode = set_multicast_list, 3229 .ndo_validate_addr = eth_validate_addr, 3230 .ndo_tx_timeout = fec_timeout, 3231 .ndo_set_mac_address = fec_set_mac_address, 3232 .ndo_do_ioctl = fec_enet_ioctl, 3233 #ifdef CONFIG_NET_POLL_CONTROLLER 3234 .ndo_poll_controller = fec_poll_controller, 3235 #endif 3236 .ndo_set_features = fec_set_features, 3237 }; 3238 3239 static const unsigned short offset_des_active_rxq[] = { 3240 FEC_R_DES_ACTIVE_0, FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2 3241 }; 3242 3243 static const unsigned short offset_des_active_txq[] = { 3244 FEC_X_DES_ACTIVE_0, FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2 3245 }; 3246 3247 /* 3248 * XXX: We need to clean up on failure exits here. 3249 * 3250 */ 3251 static int fec_enet_init(struct net_device *ndev) 3252 { 3253 struct fec_enet_private *fep = netdev_priv(ndev); 3254 struct bufdesc *cbd_base; 3255 dma_addr_t bd_dma; 3256 int bd_size; 3257 unsigned int i; 3258 unsigned dsize = fep->bufdesc_ex ? sizeof(struct bufdesc_ex) : 3259 sizeof(struct bufdesc); 3260 unsigned dsize_log2 = __fls(dsize); 3261 int ret; 3262 3263 WARN_ON(dsize != (1 << dsize_log2)); 3264 #if defined(CONFIG_ARM) || defined(CONFIG_ARM64) 3265 fep->rx_align = 0xf; 3266 fep->tx_align = 0xf; 3267 #else 3268 fep->rx_align = 0x3; 3269 fep->tx_align = 0x3; 3270 #endif 3271 3272 /* Check mask of the streaming and coherent API */ 3273 ret = dma_set_mask_and_coherent(&fep->pdev->dev, DMA_BIT_MASK(32)); 3274 if (ret < 0) { 3275 dev_warn(&fep->pdev->dev, "No suitable DMA available\n"); 3276 return ret; 3277 } 3278 3279 fec_enet_alloc_queue(ndev); 3280 3281 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) * dsize; 3282 3283 /* Allocate memory for buffer descriptors. */ 3284 cbd_base = dmam_alloc_coherent(&fep->pdev->dev, bd_size, &bd_dma, 3285 GFP_KERNEL); 3286 if (!cbd_base) { 3287 return -ENOMEM; 3288 } 3289 3290 /* Get the Ethernet address */ 3291 fec_get_mac(ndev); 3292 /* make sure MAC we just acquired is programmed into the hw */ 3293 fec_set_mac_address(ndev, NULL); 3294 3295 /* Set receive and transmit descriptor base. */ 3296 for (i = 0; i < fep->num_rx_queues; i++) { 3297 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[i]; 3298 unsigned size = dsize * rxq->bd.ring_size; 3299 3300 rxq->bd.qid = i; 3301 rxq->bd.base = cbd_base; 3302 rxq->bd.cur = cbd_base; 3303 rxq->bd.dma = bd_dma; 3304 rxq->bd.dsize = dsize; 3305 rxq->bd.dsize_log2 = dsize_log2; 3306 rxq->bd.reg_desc_active = fep->hwp + offset_des_active_rxq[i]; 3307 bd_dma += size; 3308 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size); 3309 rxq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); 3310 } 3311 3312 for (i = 0; i < fep->num_tx_queues; i++) { 3313 struct fec_enet_priv_tx_q *txq = fep->tx_queue[i]; 3314 unsigned size = dsize * txq->bd.ring_size; 3315 3316 txq->bd.qid = i; 3317 txq->bd.base = cbd_base; 3318 txq->bd.cur = cbd_base; 3319 txq->bd.dma = bd_dma; 3320 txq->bd.dsize = dsize; 3321 txq->bd.dsize_log2 = dsize_log2; 3322 txq->bd.reg_desc_active = fep->hwp + offset_des_active_txq[i]; 3323 bd_dma += size; 3324 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size); 3325 txq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); 3326 } 3327 3328 3329 /* The FEC Ethernet specific entries in the device structure */ 3330 ndev->watchdog_timeo = TX_TIMEOUT; 3331 ndev->netdev_ops = &fec_netdev_ops; 3332 ndev->ethtool_ops = &fec_enet_ethtool_ops; 3333 3334 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK); 3335 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT); 3336 3337 if (fep->quirks & FEC_QUIRK_HAS_VLAN) 3338 /* enable hw VLAN support */ 3339 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; 3340 3341 if (fep->quirks & FEC_QUIRK_HAS_CSUM) { 3342 ndev->gso_max_segs = FEC_MAX_TSO_SEGS; 3343 3344 /* enable hw accelerator */ 3345 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM 3346 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO); 3347 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 3348 } 3349 3350 if (fep->quirks & FEC_QUIRK_HAS_AVB) { 3351 fep->tx_align = 0; 3352 fep->rx_align = 0x3f; 3353 } 3354 3355 ndev->hw_features = ndev->features; 3356 3357 fec_restart(ndev); 3358 3359 if (fep->quirks & FEC_QUIRK_MIB_CLEAR) 3360 fec_enet_clear_ethtool_stats(ndev); 3361 else 3362 fec_enet_update_ethtool_stats(ndev); 3363 3364 return 0; 3365 } 3366 3367 #ifdef CONFIG_OF 3368 static int fec_reset_phy(struct platform_device *pdev) 3369 { 3370 int err, phy_reset; 3371 bool active_high = false; 3372 int msec = 1, phy_post_delay = 0; 3373 struct device_node *np = pdev->dev.of_node; 3374 3375 if (!np) 3376 return 0; 3377 3378 err = of_property_read_u32(np, "phy-reset-duration", &msec); 3379 /* A sane reset duration should not be longer than 1s */ 3380 if (!err && msec > 1000) 3381 msec = 1; 3382 3383 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0); 3384 if (phy_reset == -EPROBE_DEFER) 3385 return phy_reset; 3386 else if (!gpio_is_valid(phy_reset)) 3387 return 0; 3388 3389 err = of_property_read_u32(np, "phy-reset-post-delay", &phy_post_delay); 3390 /* valid reset duration should be less than 1s */ 3391 if (!err && phy_post_delay > 1000) 3392 return -EINVAL; 3393 3394 active_high = of_property_read_bool(np, "phy-reset-active-high"); 3395 3396 err = devm_gpio_request_one(&pdev->dev, phy_reset, 3397 active_high ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW, 3398 "phy-reset"); 3399 if (err) { 3400 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err); 3401 return err; 3402 } 3403 3404 if (msec > 20) 3405 msleep(msec); 3406 else 3407 usleep_range(msec * 1000, msec * 1000 + 1000); 3408 3409 gpio_set_value_cansleep(phy_reset, !active_high); 3410 3411 if (!phy_post_delay) 3412 return 0; 3413 3414 if (phy_post_delay > 20) 3415 msleep(phy_post_delay); 3416 else 3417 usleep_range(phy_post_delay * 1000, 3418 phy_post_delay * 1000 + 1000); 3419 3420 return 0; 3421 } 3422 #else /* CONFIG_OF */ 3423 static int fec_reset_phy(struct platform_device *pdev) 3424 { 3425 /* 3426 * In case of platform probe, the reset has been done 3427 * by machine code. 3428 */ 3429 return 0; 3430 } 3431 #endif /* CONFIG_OF */ 3432 3433 static void 3434 fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx) 3435 { 3436 struct device_node *np = pdev->dev.of_node; 3437 3438 *num_tx = *num_rx = 1; 3439 3440 if (!np || !of_device_is_available(np)) 3441 return; 3442 3443 /* parse the num of tx and rx queues */ 3444 of_property_read_u32(np, "fsl,num-tx-queues", num_tx); 3445 3446 of_property_read_u32(np, "fsl,num-rx-queues", num_rx); 3447 3448 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) { 3449 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n", 3450 *num_tx); 3451 *num_tx = 1; 3452 return; 3453 } 3454 3455 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) { 3456 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n", 3457 *num_rx); 3458 *num_rx = 1; 3459 return; 3460 } 3461 3462 } 3463 3464 static int fec_enet_get_irq_cnt(struct platform_device *pdev) 3465 { 3466 int irq_cnt = platform_irq_count(pdev); 3467 3468 if (irq_cnt > FEC_IRQ_NUM) 3469 irq_cnt = FEC_IRQ_NUM; /* last for pps */ 3470 else if (irq_cnt == 2) 3471 irq_cnt = 1; /* last for pps */ 3472 else if (irq_cnt <= 0) 3473 irq_cnt = 1; /* At least 1 irq is needed */ 3474 return irq_cnt; 3475 } 3476 3477 static int fec_enet_init_stop_mode(struct fec_enet_private *fep, 3478 struct device_node *np) 3479 { 3480 struct device_node *gpr_np; 3481 u32 out_val[3]; 3482 int ret = 0; 3483 3484 gpr_np = of_parse_phandle(np, "fsl,stop-mode", 0); 3485 if (!gpr_np) 3486 return 0; 3487 3488 ret = of_property_read_u32_array(np, "fsl,stop-mode", out_val, 3489 ARRAY_SIZE(out_val)); 3490 if (ret) { 3491 dev_dbg(&fep->pdev->dev, "no stop mode property\n"); 3492 return ret; 3493 } 3494 3495 fep->stop_gpr.gpr = syscon_node_to_regmap(gpr_np); 3496 if (IS_ERR(fep->stop_gpr.gpr)) { 3497 dev_err(&fep->pdev->dev, "could not find gpr regmap\n"); 3498 ret = PTR_ERR(fep->stop_gpr.gpr); 3499 fep->stop_gpr.gpr = NULL; 3500 goto out; 3501 } 3502 3503 fep->stop_gpr.reg = out_val[1]; 3504 fep->stop_gpr.bit = out_val[2]; 3505 3506 out: 3507 of_node_put(gpr_np); 3508 3509 return ret; 3510 } 3511 3512 static int 3513 fec_probe(struct platform_device *pdev) 3514 { 3515 struct fec_enet_private *fep; 3516 struct fec_platform_data *pdata; 3517 phy_interface_t interface; 3518 struct net_device *ndev; 3519 int i, irq, ret = 0; 3520 const struct of_device_id *of_id; 3521 static int dev_id; 3522 struct device_node *np = pdev->dev.of_node, *phy_node; 3523 int num_tx_qs; 3524 int num_rx_qs; 3525 char irq_name[8]; 3526 int irq_cnt; 3527 struct fec_devinfo *dev_info; 3528 3529 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs); 3530 3531 /* Init network device */ 3532 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private) + 3533 FEC_STATS_SIZE, num_tx_qs, num_rx_qs); 3534 if (!ndev) 3535 return -ENOMEM; 3536 3537 SET_NETDEV_DEV(ndev, &pdev->dev); 3538 3539 /* setup board info structure */ 3540 fep = netdev_priv(ndev); 3541 3542 of_id = of_match_device(fec_dt_ids, &pdev->dev); 3543 if (of_id) 3544 pdev->id_entry = of_id->data; 3545 dev_info = (struct fec_devinfo *)pdev->id_entry->driver_data; 3546 if (dev_info) 3547 fep->quirks = dev_info->quirks; 3548 3549 fep->netdev = ndev; 3550 fep->num_rx_queues = num_rx_qs; 3551 fep->num_tx_queues = num_tx_qs; 3552 3553 #if !defined(CONFIG_M5272) 3554 /* default enable pause frame auto negotiation */ 3555 if (fep->quirks & FEC_QUIRK_HAS_GBIT) 3556 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG; 3557 #endif 3558 3559 /* Select default pin state */ 3560 pinctrl_pm_select_default_state(&pdev->dev); 3561 3562 fep->hwp = devm_platform_ioremap_resource(pdev, 0); 3563 if (IS_ERR(fep->hwp)) { 3564 ret = PTR_ERR(fep->hwp); 3565 goto failed_ioremap; 3566 } 3567 3568 fep->pdev = pdev; 3569 fep->dev_id = dev_id++; 3570 3571 platform_set_drvdata(pdev, ndev); 3572 3573 if ((of_machine_is_compatible("fsl,imx6q") || 3574 of_machine_is_compatible("fsl,imx6dl")) && 3575 !of_property_read_bool(np, "fsl,err006687-workaround-present")) 3576 fep->quirks |= FEC_QUIRK_ERR006687; 3577 3578 if (of_get_property(np, "fsl,magic-packet", NULL)) 3579 fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET; 3580 3581 ret = fec_enet_init_stop_mode(fep, np); 3582 if (ret) 3583 goto failed_stop_mode; 3584 3585 phy_node = of_parse_phandle(np, "phy-handle", 0); 3586 if (!phy_node && of_phy_is_fixed_link(np)) { 3587 ret = of_phy_register_fixed_link(np); 3588 if (ret < 0) { 3589 dev_err(&pdev->dev, 3590 "broken fixed-link specification\n"); 3591 goto failed_phy; 3592 } 3593 phy_node = of_node_get(np); 3594 } 3595 fep->phy_node = phy_node; 3596 3597 ret = of_get_phy_mode(pdev->dev.of_node, &interface); 3598 if (ret) { 3599 pdata = dev_get_platdata(&pdev->dev); 3600 if (pdata) 3601 fep->phy_interface = pdata->phy; 3602 else 3603 fep->phy_interface = PHY_INTERFACE_MODE_MII; 3604 } else { 3605 fep->phy_interface = interface; 3606 } 3607 3608 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 3609 if (IS_ERR(fep->clk_ipg)) { 3610 ret = PTR_ERR(fep->clk_ipg); 3611 goto failed_clk; 3612 } 3613 3614 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 3615 if (IS_ERR(fep->clk_ahb)) { 3616 ret = PTR_ERR(fep->clk_ahb); 3617 goto failed_clk; 3618 } 3619 3620 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb); 3621 3622 /* enet_out is optional, depends on board */ 3623 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out"); 3624 if (IS_ERR(fep->clk_enet_out)) 3625 fep->clk_enet_out = NULL; 3626 3627 fep->ptp_clk_on = false; 3628 mutex_init(&fep->ptp_clk_mutex); 3629 3630 /* clk_ref is optional, depends on board */ 3631 fep->clk_ref = devm_clk_get(&pdev->dev, "enet_clk_ref"); 3632 if (IS_ERR(fep->clk_ref)) 3633 fep->clk_ref = NULL; 3634 3635 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX; 3636 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp"); 3637 if (IS_ERR(fep->clk_ptp)) { 3638 fep->clk_ptp = NULL; 3639 fep->bufdesc_ex = false; 3640 } 3641 3642 ret = fec_enet_clk_enable(ndev, true); 3643 if (ret) 3644 goto failed_clk; 3645 3646 ret = clk_prepare_enable(fep->clk_ipg); 3647 if (ret) 3648 goto failed_clk_ipg; 3649 ret = clk_prepare_enable(fep->clk_ahb); 3650 if (ret) 3651 goto failed_clk_ahb; 3652 3653 fep->reg_phy = devm_regulator_get_optional(&pdev->dev, "phy"); 3654 if (!IS_ERR(fep->reg_phy)) { 3655 ret = regulator_enable(fep->reg_phy); 3656 if (ret) { 3657 dev_err(&pdev->dev, 3658 "Failed to enable phy regulator: %d\n", ret); 3659 goto failed_regulator; 3660 } 3661 } else { 3662 if (PTR_ERR(fep->reg_phy) == -EPROBE_DEFER) { 3663 ret = -EPROBE_DEFER; 3664 goto failed_regulator; 3665 } 3666 fep->reg_phy = NULL; 3667 } 3668 3669 pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT); 3670 pm_runtime_use_autosuspend(&pdev->dev); 3671 pm_runtime_get_noresume(&pdev->dev); 3672 pm_runtime_set_active(&pdev->dev); 3673 pm_runtime_enable(&pdev->dev); 3674 3675 ret = fec_reset_phy(pdev); 3676 if (ret) 3677 goto failed_reset; 3678 3679 irq_cnt = fec_enet_get_irq_cnt(pdev); 3680 if (fep->bufdesc_ex) 3681 fec_ptp_init(pdev, irq_cnt); 3682 3683 ret = fec_enet_init(ndev); 3684 if (ret) 3685 goto failed_init; 3686 3687 for (i = 0; i < irq_cnt; i++) { 3688 snprintf(irq_name, sizeof(irq_name), "int%d", i); 3689 irq = platform_get_irq_byname_optional(pdev, irq_name); 3690 if (irq < 0) 3691 irq = platform_get_irq(pdev, i); 3692 if (irq < 0) { 3693 ret = irq; 3694 goto failed_irq; 3695 } 3696 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt, 3697 0, pdev->name, ndev); 3698 if (ret) 3699 goto failed_irq; 3700 3701 fep->irq[i] = irq; 3702 } 3703 3704 ret = fec_enet_mii_init(pdev); 3705 if (ret) 3706 goto failed_mii_init; 3707 3708 /* Carrier starts down, phylib will bring it up */ 3709 netif_carrier_off(ndev); 3710 fec_enet_clk_enable(ndev, false); 3711 pinctrl_pm_select_sleep_state(&pdev->dev); 3712 3713 ret = register_netdev(ndev); 3714 if (ret) 3715 goto failed_register; 3716 3717 device_init_wakeup(&ndev->dev, fep->wol_flag & 3718 FEC_WOL_HAS_MAGIC_PACKET); 3719 3720 if (fep->bufdesc_ex && fep->ptp_clock) 3721 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id); 3722 3723 fep->rx_copybreak = COPYBREAK_DEFAULT; 3724 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work); 3725 3726 pm_runtime_mark_last_busy(&pdev->dev); 3727 pm_runtime_put_autosuspend(&pdev->dev); 3728 3729 return 0; 3730 3731 failed_register: 3732 fec_enet_mii_remove(fep); 3733 failed_mii_init: 3734 failed_irq: 3735 failed_init: 3736 fec_ptp_stop(pdev); 3737 if (fep->reg_phy) 3738 regulator_disable(fep->reg_phy); 3739 failed_reset: 3740 pm_runtime_put_noidle(&pdev->dev); 3741 pm_runtime_disable(&pdev->dev); 3742 failed_regulator: 3743 clk_disable_unprepare(fep->clk_ahb); 3744 failed_clk_ahb: 3745 clk_disable_unprepare(fep->clk_ipg); 3746 failed_clk_ipg: 3747 fec_enet_clk_enable(ndev, false); 3748 failed_clk: 3749 if (of_phy_is_fixed_link(np)) 3750 of_phy_deregister_fixed_link(np); 3751 of_node_put(phy_node); 3752 failed_stop_mode: 3753 failed_phy: 3754 dev_id--; 3755 failed_ioremap: 3756 free_netdev(ndev); 3757 3758 return ret; 3759 } 3760 3761 static int 3762 fec_drv_remove(struct platform_device *pdev) 3763 { 3764 struct net_device *ndev = platform_get_drvdata(pdev); 3765 struct fec_enet_private *fep = netdev_priv(ndev); 3766 struct device_node *np = pdev->dev.of_node; 3767 int ret; 3768 3769 ret = pm_runtime_get_sync(&pdev->dev); 3770 if (ret < 0) 3771 return ret; 3772 3773 cancel_work_sync(&fep->tx_timeout_work); 3774 fec_ptp_stop(pdev); 3775 unregister_netdev(ndev); 3776 fec_enet_mii_remove(fep); 3777 if (fep->reg_phy) 3778 regulator_disable(fep->reg_phy); 3779 3780 if (of_phy_is_fixed_link(np)) 3781 of_phy_deregister_fixed_link(np); 3782 of_node_put(fep->phy_node); 3783 free_netdev(ndev); 3784 3785 clk_disable_unprepare(fep->clk_ahb); 3786 clk_disable_unprepare(fep->clk_ipg); 3787 pm_runtime_put_noidle(&pdev->dev); 3788 pm_runtime_disable(&pdev->dev); 3789 3790 return 0; 3791 } 3792 3793 static int __maybe_unused fec_suspend(struct device *dev) 3794 { 3795 struct net_device *ndev = dev_get_drvdata(dev); 3796 struct fec_enet_private *fep = netdev_priv(ndev); 3797 3798 rtnl_lock(); 3799 if (netif_running(ndev)) { 3800 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) 3801 fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON; 3802 phy_stop(ndev->phydev); 3803 napi_disable(&fep->napi); 3804 netif_tx_lock_bh(ndev); 3805 netif_device_detach(ndev); 3806 netif_tx_unlock_bh(ndev); 3807 fec_stop(ndev); 3808 fec_enet_clk_enable(ndev, false); 3809 if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) 3810 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3811 } 3812 rtnl_unlock(); 3813 3814 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) 3815 regulator_disable(fep->reg_phy); 3816 3817 /* SOC supply clock to phy, when clock is disabled, phy link down 3818 * SOC control phy regulator, when regulator is disabled, phy link down 3819 */ 3820 if (fep->clk_enet_out || fep->reg_phy) 3821 fep->link = 0; 3822 3823 return 0; 3824 } 3825 3826 static int __maybe_unused fec_resume(struct device *dev) 3827 { 3828 struct net_device *ndev = dev_get_drvdata(dev); 3829 struct fec_enet_private *fep = netdev_priv(ndev); 3830 int ret; 3831 int val; 3832 3833 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) { 3834 ret = regulator_enable(fep->reg_phy); 3835 if (ret) 3836 return ret; 3837 } 3838 3839 rtnl_lock(); 3840 if (netif_running(ndev)) { 3841 ret = fec_enet_clk_enable(ndev, true); 3842 if (ret) { 3843 rtnl_unlock(); 3844 goto failed_clk; 3845 } 3846 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) { 3847 fec_enet_stop_mode(fep, false); 3848 3849 val = readl(fep->hwp + FEC_ECNTRL); 3850 val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP); 3851 writel(val, fep->hwp + FEC_ECNTRL); 3852 fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON; 3853 } else { 3854 pinctrl_pm_select_default_state(&fep->pdev->dev); 3855 } 3856 fec_restart(ndev); 3857 netif_tx_lock_bh(ndev); 3858 netif_device_attach(ndev); 3859 netif_tx_unlock_bh(ndev); 3860 napi_enable(&fep->napi); 3861 phy_start(ndev->phydev); 3862 } 3863 rtnl_unlock(); 3864 3865 return 0; 3866 3867 failed_clk: 3868 if (fep->reg_phy) 3869 regulator_disable(fep->reg_phy); 3870 return ret; 3871 } 3872 3873 static int __maybe_unused fec_runtime_suspend(struct device *dev) 3874 { 3875 struct net_device *ndev = dev_get_drvdata(dev); 3876 struct fec_enet_private *fep = netdev_priv(ndev); 3877 3878 clk_disable_unprepare(fep->clk_ahb); 3879 clk_disable_unprepare(fep->clk_ipg); 3880 3881 return 0; 3882 } 3883 3884 static int __maybe_unused fec_runtime_resume(struct device *dev) 3885 { 3886 struct net_device *ndev = dev_get_drvdata(dev); 3887 struct fec_enet_private *fep = netdev_priv(ndev); 3888 int ret; 3889 3890 ret = clk_prepare_enable(fep->clk_ahb); 3891 if (ret) 3892 return ret; 3893 ret = clk_prepare_enable(fep->clk_ipg); 3894 if (ret) 3895 goto failed_clk_ipg; 3896 3897 return 0; 3898 3899 failed_clk_ipg: 3900 clk_disable_unprepare(fep->clk_ahb); 3901 return ret; 3902 } 3903 3904 static const struct dev_pm_ops fec_pm_ops = { 3905 SET_SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume) 3906 SET_RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL) 3907 }; 3908 3909 static struct platform_driver fec_driver = { 3910 .driver = { 3911 .name = DRIVER_NAME, 3912 .pm = &fec_pm_ops, 3913 .of_match_table = fec_dt_ids, 3914 .suppress_bind_attrs = true, 3915 }, 3916 .id_table = fec_devtype, 3917 .probe = fec_probe, 3918 .remove = fec_drv_remove, 3919 }; 3920 3921 module_platform_driver(fec_driver); 3922 3923 MODULE_ALIAS("platform:"DRIVER_NAME); 3924 MODULE_LICENSE("GPL"); 3925