1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
4  * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5  *
6  * Right now, I am very wasteful with the buffers.  I allocate memory
7  * pages and then divide them into 2K frame buffers.  This way I know I
8  * have buffers large enough to hold one frame within one buffer descriptor.
9  * Once I get this working, I will use 64 or 128 byte CPM buffers, which
10  * will be much more memory efficient and will easily handle lots of
11  * small packets.
12  *
13  * Much better multiple PHY support by Magnus Damm.
14  * Copyright (c) 2000 Ericsson Radio Systems AB.
15  *
16  * Support for FEC controller of ColdFire processors.
17  * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
18  *
19  * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
20  * Copyright (c) 2004-2006 Macq Electronique SA.
21  *
22  * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
23  */
24 
25 #include <linux/module.h>
26 #include <linux/kernel.h>
27 #include <linux/string.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/ptrace.h>
30 #include <linux/errno.h>
31 #include <linux/ioport.h>
32 #include <linux/slab.h>
33 #include <linux/interrupt.h>
34 #include <linux/delay.h>
35 #include <linux/netdevice.h>
36 #include <linux/etherdevice.h>
37 #include <linux/skbuff.h>
38 #include <linux/in.h>
39 #include <linux/ip.h>
40 #include <net/ip.h>
41 #include <net/selftests.h>
42 #include <net/tso.h>
43 #include <linux/tcp.h>
44 #include <linux/udp.h>
45 #include <linux/icmp.h>
46 #include <linux/spinlock.h>
47 #include <linux/workqueue.h>
48 #include <linux/bitops.h>
49 #include <linux/io.h>
50 #include <linux/irq.h>
51 #include <linux/clk.h>
52 #include <linux/crc32.h>
53 #include <linux/platform_device.h>
54 #include <linux/mdio.h>
55 #include <linux/phy.h>
56 #include <linux/fec.h>
57 #include <linux/of.h>
58 #include <linux/of_device.h>
59 #include <linux/of_gpio.h>
60 #include <linux/of_mdio.h>
61 #include <linux/of_net.h>
62 #include <linux/regulator/consumer.h>
63 #include <linux/if_vlan.h>
64 #include <linux/pinctrl/consumer.h>
65 #include <linux/prefetch.h>
66 #include <linux/mfd/syscon.h>
67 #include <linux/regmap.h>
68 #include <soc/imx/cpuidle.h>
69 #include <linux/filter.h>
70 #include <linux/bpf.h>
71 
72 #include <asm/cacheflush.h>
73 
74 #include "fec.h"
75 
76 static void set_multicast_list(struct net_device *ndev);
77 static void fec_enet_itr_coal_set(struct net_device *ndev);
78 
79 #define DRIVER_NAME	"fec"
80 
81 static const u16 fec_enet_vlan_pri_to_queue[8] = {0, 0, 1, 1, 1, 2, 2, 2};
82 
83 /* Pause frame feild and FIFO threshold */
84 #define FEC_ENET_FCE	(1 << 5)
85 #define FEC_ENET_RSEM_V	0x84
86 #define FEC_ENET_RSFL_V	16
87 #define FEC_ENET_RAEM_V	0x8
88 #define FEC_ENET_RAFL_V	0x8
89 #define FEC_ENET_OPD_V	0xFFF0
90 #define FEC_MDIO_PM_TIMEOUT  100 /* ms */
91 
92 #define FEC_ENET_XDP_PASS          0
93 #define FEC_ENET_XDP_CONSUMED      BIT(0)
94 #define FEC_ENET_XDP_TX            BIT(1)
95 #define FEC_ENET_XDP_REDIR         BIT(2)
96 
97 struct fec_devinfo {
98 	u32 quirks;
99 };
100 
101 static const struct fec_devinfo fec_imx25_info = {
102 	.quirks = FEC_QUIRK_USE_GASKET | FEC_QUIRK_MIB_CLEAR |
103 		  FEC_QUIRK_HAS_FRREG,
104 };
105 
106 static const struct fec_devinfo fec_imx27_info = {
107 	.quirks = FEC_QUIRK_MIB_CLEAR | FEC_QUIRK_HAS_FRREG,
108 };
109 
110 static const struct fec_devinfo fec_imx28_info = {
111 	.quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME |
112 		  FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC |
113 		  FEC_QUIRK_HAS_FRREG | FEC_QUIRK_CLEAR_SETUP_MII |
114 		  FEC_QUIRK_NO_HARD_RESET,
115 };
116 
117 static const struct fec_devinfo fec_imx6q_info = {
118 	.quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
119 		  FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
120 		  FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 |
121 		  FEC_QUIRK_HAS_RACC | FEC_QUIRK_CLEAR_SETUP_MII |
122 		  FEC_QUIRK_HAS_PMQOS,
123 };
124 
125 static const struct fec_devinfo fec_mvf600_info = {
126 	.quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC,
127 };
128 
129 static const struct fec_devinfo fec_imx6x_info = {
130 	.quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
131 		  FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
132 		  FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
133 		  FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE |
134 		  FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE |
135 		  FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES,
136 };
137 
138 static const struct fec_devinfo fec_imx6ul_info = {
139 	.quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
140 		  FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
141 		  FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR007885 |
142 		  FEC_QUIRK_BUG_CAPTURE | FEC_QUIRK_HAS_RACC |
143 		  FEC_QUIRK_HAS_COALESCE | FEC_QUIRK_CLEAR_SETUP_MII,
144 };
145 
146 static const struct fec_devinfo fec_imx8mq_info = {
147 	.quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
148 		  FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
149 		  FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
150 		  FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE |
151 		  FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE |
152 		  FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES |
153 		  FEC_QUIRK_HAS_EEE | FEC_QUIRK_WAKEUP_FROM_INT2,
154 };
155 
156 static const struct fec_devinfo fec_imx8qm_info = {
157 	.quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
158 		  FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
159 		  FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
160 		  FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE |
161 		  FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE |
162 		  FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES |
163 		  FEC_QUIRK_DELAYED_CLKS_SUPPORT,
164 };
165 
166 static const struct fec_devinfo fec_s32v234_info = {
167 	.quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
168 		  FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
169 		  FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
170 		  FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE,
171 };
172 
173 static struct platform_device_id fec_devtype[] = {
174 	{
175 		/* keep it for coldfire */
176 		.name = DRIVER_NAME,
177 		.driver_data = 0,
178 	}, {
179 		.name = "imx25-fec",
180 		.driver_data = (kernel_ulong_t)&fec_imx25_info,
181 	}, {
182 		.name = "imx27-fec",
183 		.driver_data = (kernel_ulong_t)&fec_imx27_info,
184 	}, {
185 		.name = "imx28-fec",
186 		.driver_data = (kernel_ulong_t)&fec_imx28_info,
187 	}, {
188 		.name = "imx6q-fec",
189 		.driver_data = (kernel_ulong_t)&fec_imx6q_info,
190 	}, {
191 		.name = "mvf600-fec",
192 		.driver_data = (kernel_ulong_t)&fec_mvf600_info,
193 	}, {
194 		.name = "imx6sx-fec",
195 		.driver_data = (kernel_ulong_t)&fec_imx6x_info,
196 	}, {
197 		.name = "imx6ul-fec",
198 		.driver_data = (kernel_ulong_t)&fec_imx6ul_info,
199 	}, {
200 		.name = "imx8mq-fec",
201 		.driver_data = (kernel_ulong_t)&fec_imx8mq_info,
202 	}, {
203 		.name = "imx8qm-fec",
204 		.driver_data = (kernel_ulong_t)&fec_imx8qm_info,
205 	}, {
206 		.name = "s32v234-fec",
207 		.driver_data = (kernel_ulong_t)&fec_s32v234_info,
208 	}, {
209 		/* sentinel */
210 	}
211 };
212 MODULE_DEVICE_TABLE(platform, fec_devtype);
213 
214 enum imx_fec_type {
215 	IMX25_FEC = 1,	/* runs on i.mx25/50/53 */
216 	IMX27_FEC,	/* runs on i.mx27/35/51 */
217 	IMX28_FEC,
218 	IMX6Q_FEC,
219 	MVF600_FEC,
220 	IMX6SX_FEC,
221 	IMX6UL_FEC,
222 	IMX8MQ_FEC,
223 	IMX8QM_FEC,
224 	S32V234_FEC,
225 };
226 
227 static const struct of_device_id fec_dt_ids[] = {
228 	{ .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
229 	{ .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
230 	{ .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
231 	{ .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
232 	{ .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], },
233 	{ .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], },
234 	{ .compatible = "fsl,imx6ul-fec", .data = &fec_devtype[IMX6UL_FEC], },
235 	{ .compatible = "fsl,imx8mq-fec", .data = &fec_devtype[IMX8MQ_FEC], },
236 	{ .compatible = "fsl,imx8qm-fec", .data = &fec_devtype[IMX8QM_FEC], },
237 	{ .compatible = "fsl,s32v234-fec", .data = &fec_devtype[S32V234_FEC], },
238 	{ /* sentinel */ }
239 };
240 MODULE_DEVICE_TABLE(of, fec_dt_ids);
241 
242 static unsigned char macaddr[ETH_ALEN];
243 module_param_array(macaddr, byte, NULL, 0);
244 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
245 
246 #if defined(CONFIG_M5272)
247 /*
248  * Some hardware gets it MAC address out of local flash memory.
249  * if this is non-zero then assume it is the address to get MAC from.
250  */
251 #if defined(CONFIG_NETtel)
252 #define	FEC_FLASHMAC	0xf0006006
253 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
254 #define	FEC_FLASHMAC	0xf0006000
255 #elif defined(CONFIG_CANCam)
256 #define	FEC_FLASHMAC	0xf0020000
257 #elif defined (CONFIG_M5272C3)
258 #define	FEC_FLASHMAC	(0xffe04000 + 4)
259 #elif defined(CONFIG_MOD5272)
260 #define FEC_FLASHMAC	0xffc0406b
261 #else
262 #define	FEC_FLASHMAC	0
263 #endif
264 #endif /* CONFIG_M5272 */
265 
266 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets.
267  *
268  * 2048 byte skbufs are allocated. However, alignment requirements
269  * varies between FEC variants. Worst case is 64, so round down by 64.
270  */
271 #define PKT_MAXBUF_SIZE		(round_down(2048 - 64, 64))
272 #define PKT_MINBUF_SIZE		64
273 
274 /* FEC receive acceleration */
275 #define FEC_RACC_IPDIS		(1 << 1)
276 #define FEC_RACC_PRODIS		(1 << 2)
277 #define FEC_RACC_SHIFT16	BIT(7)
278 #define FEC_RACC_OPTIONS	(FEC_RACC_IPDIS | FEC_RACC_PRODIS)
279 
280 /* MIB Control Register */
281 #define FEC_MIB_CTRLSTAT_DISABLE	BIT(31)
282 
283 /*
284  * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
285  * size bits. Other FEC hardware does not, so we need to take that into
286  * account when setting it.
287  */
288 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
289     defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \
290     defined(CONFIG_ARM64)
291 #define	OPT_FRAME_SIZE	(PKT_MAXBUF_SIZE << 16)
292 #else
293 #define	OPT_FRAME_SIZE	0
294 #endif
295 
296 /* FEC MII MMFR bits definition */
297 #define FEC_MMFR_ST		(1 << 30)
298 #define FEC_MMFR_ST_C45		(0)
299 #define FEC_MMFR_OP_READ	(2 << 28)
300 #define FEC_MMFR_OP_READ_C45	(3 << 28)
301 #define FEC_MMFR_OP_WRITE	(1 << 28)
302 #define FEC_MMFR_OP_ADDR_WRITE	(0)
303 #define FEC_MMFR_PA(v)		((v & 0x1f) << 23)
304 #define FEC_MMFR_RA(v)		((v & 0x1f) << 18)
305 #define FEC_MMFR_TA		(2 << 16)
306 #define FEC_MMFR_DATA(v)	(v & 0xffff)
307 /* FEC ECR bits definition */
308 #define FEC_ECR_MAGICEN		(1 << 2)
309 #define FEC_ECR_SLEEP		(1 << 3)
310 
311 #define FEC_MII_TIMEOUT		30000 /* us */
312 
313 /* Transmitter timeout */
314 #define TX_TIMEOUT (2 * HZ)
315 
316 #define FEC_PAUSE_FLAG_AUTONEG	0x1
317 #define FEC_PAUSE_FLAG_ENABLE	0x2
318 #define FEC_WOL_HAS_MAGIC_PACKET	(0x1 << 0)
319 #define FEC_WOL_FLAG_ENABLE		(0x1 << 1)
320 #define FEC_WOL_FLAG_SLEEP_ON		(0x1 << 2)
321 
322 #define COPYBREAK_DEFAULT	256
323 
324 /* Max number of allowed TCP segments for software TSO */
325 #define FEC_MAX_TSO_SEGS	100
326 #define FEC_MAX_SKB_DESCS	(FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
327 
328 #define IS_TSO_HEADER(txq, addr) \
329 	((addr >= txq->tso_hdrs_dma) && \
330 	(addr < txq->tso_hdrs_dma + txq->bd.ring_size * TSO_HEADER_SIZE))
331 
332 static int mii_cnt;
333 
334 static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp,
335 					     struct bufdesc_prop *bd)
336 {
337 	return (bdp >= bd->last) ? bd->base
338 			: (struct bufdesc *)(((void *)bdp) + bd->dsize);
339 }
340 
341 static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp,
342 					     struct bufdesc_prop *bd)
343 {
344 	return (bdp <= bd->base) ? bd->last
345 			: (struct bufdesc *)(((void *)bdp) - bd->dsize);
346 }
347 
348 static int fec_enet_get_bd_index(struct bufdesc *bdp,
349 				 struct bufdesc_prop *bd)
350 {
351 	return ((const char *)bdp - (const char *)bd->base) >> bd->dsize_log2;
352 }
353 
354 static int fec_enet_get_free_txdesc_num(struct fec_enet_priv_tx_q *txq)
355 {
356 	int entries;
357 
358 	entries = (((const char *)txq->dirty_tx -
359 			(const char *)txq->bd.cur) >> txq->bd.dsize_log2) - 1;
360 
361 	return entries >= 0 ? entries : entries + txq->bd.ring_size;
362 }
363 
364 static void swap_buffer(void *bufaddr, int len)
365 {
366 	int i;
367 	unsigned int *buf = bufaddr;
368 
369 	for (i = 0; i < len; i += 4, buf++)
370 		swab32s(buf);
371 }
372 
373 static void fec_dump(struct net_device *ndev)
374 {
375 	struct fec_enet_private *fep = netdev_priv(ndev);
376 	struct bufdesc *bdp;
377 	struct fec_enet_priv_tx_q *txq;
378 	int index = 0;
379 
380 	netdev_info(ndev, "TX ring dump\n");
381 	pr_info("Nr     SC     addr       len  SKB\n");
382 
383 	txq = fep->tx_queue[0];
384 	bdp = txq->bd.base;
385 
386 	do {
387 		pr_info("%3u %c%c 0x%04x 0x%08x %4u %p\n",
388 			index,
389 			bdp == txq->bd.cur ? 'S' : ' ',
390 			bdp == txq->dirty_tx ? 'H' : ' ',
391 			fec16_to_cpu(bdp->cbd_sc),
392 			fec32_to_cpu(bdp->cbd_bufaddr),
393 			fec16_to_cpu(bdp->cbd_datlen),
394 			txq->tx_skbuff[index]);
395 		bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
396 		index++;
397 	} while (bdp != txq->bd.base);
398 }
399 
400 static inline bool is_ipv4_pkt(struct sk_buff *skb)
401 {
402 	return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4;
403 }
404 
405 static int
406 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev)
407 {
408 	/* Only run for packets requiring a checksum. */
409 	if (skb->ip_summed != CHECKSUM_PARTIAL)
410 		return 0;
411 
412 	if (unlikely(skb_cow_head(skb, 0)))
413 		return -1;
414 
415 	if (is_ipv4_pkt(skb))
416 		ip_hdr(skb)->check = 0;
417 	*(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0;
418 
419 	return 0;
420 }
421 
422 static int
423 fec_enet_create_page_pool(struct fec_enet_private *fep,
424 			  struct fec_enet_priv_rx_q *rxq, int size)
425 {
426 	struct bpf_prog *xdp_prog = READ_ONCE(fep->xdp_prog);
427 	struct page_pool_params pp_params = {
428 		.order = 0,
429 		.flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV,
430 		.pool_size = size,
431 		.nid = dev_to_node(&fep->pdev->dev),
432 		.dev = &fep->pdev->dev,
433 		.dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE,
434 		.offset = FEC_ENET_XDP_HEADROOM,
435 		.max_len = FEC_ENET_RX_FRSIZE,
436 	};
437 	int err;
438 
439 	rxq->page_pool = page_pool_create(&pp_params);
440 	if (IS_ERR(rxq->page_pool)) {
441 		err = PTR_ERR(rxq->page_pool);
442 		rxq->page_pool = NULL;
443 		return err;
444 	}
445 
446 	err = xdp_rxq_info_reg(&rxq->xdp_rxq, fep->netdev, rxq->id, 0);
447 	if (err < 0)
448 		goto err_free_pp;
449 
450 	err = xdp_rxq_info_reg_mem_model(&rxq->xdp_rxq, MEM_TYPE_PAGE_POOL,
451 					 rxq->page_pool);
452 	if (err)
453 		goto err_unregister_rxq;
454 
455 	return 0;
456 
457 err_unregister_rxq:
458 	xdp_rxq_info_unreg(&rxq->xdp_rxq);
459 err_free_pp:
460 	page_pool_destroy(rxq->page_pool);
461 	rxq->page_pool = NULL;
462 	return err;
463 }
464 
465 static struct bufdesc *
466 fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq,
467 			     struct sk_buff *skb,
468 			     struct net_device *ndev)
469 {
470 	struct fec_enet_private *fep = netdev_priv(ndev);
471 	struct bufdesc *bdp = txq->bd.cur;
472 	struct bufdesc_ex *ebdp;
473 	int nr_frags = skb_shinfo(skb)->nr_frags;
474 	int frag, frag_len;
475 	unsigned short status;
476 	unsigned int estatus = 0;
477 	skb_frag_t *this_frag;
478 	unsigned int index;
479 	void *bufaddr;
480 	dma_addr_t addr;
481 	int i;
482 
483 	for (frag = 0; frag < nr_frags; frag++) {
484 		this_frag = &skb_shinfo(skb)->frags[frag];
485 		bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
486 		ebdp = (struct bufdesc_ex *)bdp;
487 
488 		status = fec16_to_cpu(bdp->cbd_sc);
489 		status &= ~BD_ENET_TX_STATS;
490 		status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
491 		frag_len = skb_frag_size(&skb_shinfo(skb)->frags[frag]);
492 
493 		/* Handle the last BD specially */
494 		if (frag == nr_frags - 1) {
495 			status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
496 			if (fep->bufdesc_ex) {
497 				estatus |= BD_ENET_TX_INT;
498 				if (unlikely(skb_shinfo(skb)->tx_flags &
499 					SKBTX_HW_TSTAMP && fep->hwts_tx_en))
500 					estatus |= BD_ENET_TX_TS;
501 			}
502 		}
503 
504 		if (fep->bufdesc_ex) {
505 			if (fep->quirks & FEC_QUIRK_HAS_AVB)
506 				estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
507 			if (skb->ip_summed == CHECKSUM_PARTIAL)
508 				estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
509 
510 			ebdp->cbd_bdu = 0;
511 			ebdp->cbd_esc = cpu_to_fec32(estatus);
512 		}
513 
514 		bufaddr = skb_frag_address(this_frag);
515 
516 		index = fec_enet_get_bd_index(bdp, &txq->bd);
517 		if (((unsigned long) bufaddr) & fep->tx_align ||
518 			fep->quirks & FEC_QUIRK_SWAP_FRAME) {
519 			memcpy(txq->tx_bounce[index], bufaddr, frag_len);
520 			bufaddr = txq->tx_bounce[index];
521 
522 			if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
523 				swap_buffer(bufaddr, frag_len);
524 		}
525 
526 		addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len,
527 				      DMA_TO_DEVICE);
528 		if (dma_mapping_error(&fep->pdev->dev, addr)) {
529 			if (net_ratelimit())
530 				netdev_err(ndev, "Tx DMA memory map failed\n");
531 			goto dma_mapping_error;
532 		}
533 
534 		bdp->cbd_bufaddr = cpu_to_fec32(addr);
535 		bdp->cbd_datlen = cpu_to_fec16(frag_len);
536 		/* Make sure the updates to rest of the descriptor are
537 		 * performed before transferring ownership.
538 		 */
539 		wmb();
540 		bdp->cbd_sc = cpu_to_fec16(status);
541 	}
542 
543 	return bdp;
544 dma_mapping_error:
545 	bdp = txq->bd.cur;
546 	for (i = 0; i < frag; i++) {
547 		bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
548 		dma_unmap_single(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr),
549 				 fec16_to_cpu(bdp->cbd_datlen), DMA_TO_DEVICE);
550 	}
551 	return ERR_PTR(-ENOMEM);
552 }
553 
554 static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq,
555 				   struct sk_buff *skb, struct net_device *ndev)
556 {
557 	struct fec_enet_private *fep = netdev_priv(ndev);
558 	int nr_frags = skb_shinfo(skb)->nr_frags;
559 	struct bufdesc *bdp, *last_bdp;
560 	void *bufaddr;
561 	dma_addr_t addr;
562 	unsigned short status;
563 	unsigned short buflen;
564 	unsigned int estatus = 0;
565 	unsigned int index;
566 	int entries_free;
567 
568 	entries_free = fec_enet_get_free_txdesc_num(txq);
569 	if (entries_free < MAX_SKB_FRAGS + 1) {
570 		dev_kfree_skb_any(skb);
571 		if (net_ratelimit())
572 			netdev_err(ndev, "NOT enough BD for SG!\n");
573 		return NETDEV_TX_OK;
574 	}
575 
576 	/* Protocol checksum off-load for TCP and UDP. */
577 	if (fec_enet_clear_csum(skb, ndev)) {
578 		dev_kfree_skb_any(skb);
579 		return NETDEV_TX_OK;
580 	}
581 
582 	/* Fill in a Tx ring entry */
583 	bdp = txq->bd.cur;
584 	last_bdp = bdp;
585 	status = fec16_to_cpu(bdp->cbd_sc);
586 	status &= ~BD_ENET_TX_STATS;
587 
588 	/* Set buffer length and buffer pointer */
589 	bufaddr = skb->data;
590 	buflen = skb_headlen(skb);
591 
592 	index = fec_enet_get_bd_index(bdp, &txq->bd);
593 	if (((unsigned long) bufaddr) & fep->tx_align ||
594 		fep->quirks & FEC_QUIRK_SWAP_FRAME) {
595 		memcpy(txq->tx_bounce[index], skb->data, buflen);
596 		bufaddr = txq->tx_bounce[index];
597 
598 		if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
599 			swap_buffer(bufaddr, buflen);
600 	}
601 
602 	/* Push the data cache so the CPM does not get stale memory data. */
603 	addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE);
604 	if (dma_mapping_error(&fep->pdev->dev, addr)) {
605 		dev_kfree_skb_any(skb);
606 		if (net_ratelimit())
607 			netdev_err(ndev, "Tx DMA memory map failed\n");
608 		return NETDEV_TX_OK;
609 	}
610 
611 	if (nr_frags) {
612 		last_bdp = fec_enet_txq_submit_frag_skb(txq, skb, ndev);
613 		if (IS_ERR(last_bdp)) {
614 			dma_unmap_single(&fep->pdev->dev, addr,
615 					 buflen, DMA_TO_DEVICE);
616 			dev_kfree_skb_any(skb);
617 			return NETDEV_TX_OK;
618 		}
619 	} else {
620 		status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
621 		if (fep->bufdesc_ex) {
622 			estatus = BD_ENET_TX_INT;
623 			if (unlikely(skb_shinfo(skb)->tx_flags &
624 				SKBTX_HW_TSTAMP && fep->hwts_tx_en))
625 				estatus |= BD_ENET_TX_TS;
626 		}
627 	}
628 	bdp->cbd_bufaddr = cpu_to_fec32(addr);
629 	bdp->cbd_datlen = cpu_to_fec16(buflen);
630 
631 	if (fep->bufdesc_ex) {
632 
633 		struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
634 
635 		if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
636 			fep->hwts_tx_en))
637 			skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
638 
639 		if (fep->quirks & FEC_QUIRK_HAS_AVB)
640 			estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
641 
642 		if (skb->ip_summed == CHECKSUM_PARTIAL)
643 			estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
644 
645 		ebdp->cbd_bdu = 0;
646 		ebdp->cbd_esc = cpu_to_fec32(estatus);
647 	}
648 
649 	index = fec_enet_get_bd_index(last_bdp, &txq->bd);
650 	/* Save skb pointer */
651 	txq->tx_skbuff[index] = skb;
652 
653 	/* Make sure the updates to rest of the descriptor are performed before
654 	 * transferring ownership.
655 	 */
656 	wmb();
657 
658 	/* Send it on its way.  Tell FEC it's ready, interrupt when done,
659 	 * it's the last BD of the frame, and to put the CRC on the end.
660 	 */
661 	status |= (BD_ENET_TX_READY | BD_ENET_TX_TC);
662 	bdp->cbd_sc = cpu_to_fec16(status);
663 
664 	/* If this was the last BD in the ring, start at the beginning again. */
665 	bdp = fec_enet_get_nextdesc(last_bdp, &txq->bd);
666 
667 	skb_tx_timestamp(skb);
668 
669 	/* Make sure the update to bdp and tx_skbuff are performed before
670 	 * txq->bd.cur.
671 	 */
672 	wmb();
673 	txq->bd.cur = bdp;
674 
675 	/* Trigger transmission start */
676 	writel(0, txq->bd.reg_desc_active);
677 
678 	return 0;
679 }
680 
681 static int
682 fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb,
683 			  struct net_device *ndev,
684 			  struct bufdesc *bdp, int index, char *data,
685 			  int size, bool last_tcp, bool is_last)
686 {
687 	struct fec_enet_private *fep = netdev_priv(ndev);
688 	struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
689 	unsigned short status;
690 	unsigned int estatus = 0;
691 	dma_addr_t addr;
692 
693 	status = fec16_to_cpu(bdp->cbd_sc);
694 	status &= ~BD_ENET_TX_STATS;
695 
696 	status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
697 
698 	if (((unsigned long) data) & fep->tx_align ||
699 		fep->quirks & FEC_QUIRK_SWAP_FRAME) {
700 		memcpy(txq->tx_bounce[index], data, size);
701 		data = txq->tx_bounce[index];
702 
703 		if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
704 			swap_buffer(data, size);
705 	}
706 
707 	addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE);
708 	if (dma_mapping_error(&fep->pdev->dev, addr)) {
709 		dev_kfree_skb_any(skb);
710 		if (net_ratelimit())
711 			netdev_err(ndev, "Tx DMA memory map failed\n");
712 		return NETDEV_TX_OK;
713 	}
714 
715 	bdp->cbd_datlen = cpu_to_fec16(size);
716 	bdp->cbd_bufaddr = cpu_to_fec32(addr);
717 
718 	if (fep->bufdesc_ex) {
719 		if (fep->quirks & FEC_QUIRK_HAS_AVB)
720 			estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
721 		if (skb->ip_summed == CHECKSUM_PARTIAL)
722 			estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
723 		ebdp->cbd_bdu = 0;
724 		ebdp->cbd_esc = cpu_to_fec32(estatus);
725 	}
726 
727 	/* Handle the last BD specially */
728 	if (last_tcp)
729 		status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC);
730 	if (is_last) {
731 		status |= BD_ENET_TX_INTR;
732 		if (fep->bufdesc_ex)
733 			ebdp->cbd_esc |= cpu_to_fec32(BD_ENET_TX_INT);
734 	}
735 
736 	bdp->cbd_sc = cpu_to_fec16(status);
737 
738 	return 0;
739 }
740 
741 static int
742 fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq,
743 			 struct sk_buff *skb, struct net_device *ndev,
744 			 struct bufdesc *bdp, int index)
745 {
746 	struct fec_enet_private *fep = netdev_priv(ndev);
747 	int hdr_len = skb_tcp_all_headers(skb);
748 	struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
749 	void *bufaddr;
750 	unsigned long dmabuf;
751 	unsigned short status;
752 	unsigned int estatus = 0;
753 
754 	status = fec16_to_cpu(bdp->cbd_sc);
755 	status &= ~BD_ENET_TX_STATS;
756 	status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
757 
758 	bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
759 	dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE;
760 	if (((unsigned long)bufaddr) & fep->tx_align ||
761 		fep->quirks & FEC_QUIRK_SWAP_FRAME) {
762 		memcpy(txq->tx_bounce[index], skb->data, hdr_len);
763 		bufaddr = txq->tx_bounce[index];
764 
765 		if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
766 			swap_buffer(bufaddr, hdr_len);
767 
768 		dmabuf = dma_map_single(&fep->pdev->dev, bufaddr,
769 					hdr_len, DMA_TO_DEVICE);
770 		if (dma_mapping_error(&fep->pdev->dev, dmabuf)) {
771 			dev_kfree_skb_any(skb);
772 			if (net_ratelimit())
773 				netdev_err(ndev, "Tx DMA memory map failed\n");
774 			return NETDEV_TX_OK;
775 		}
776 	}
777 
778 	bdp->cbd_bufaddr = cpu_to_fec32(dmabuf);
779 	bdp->cbd_datlen = cpu_to_fec16(hdr_len);
780 
781 	if (fep->bufdesc_ex) {
782 		if (fep->quirks & FEC_QUIRK_HAS_AVB)
783 			estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
784 		if (skb->ip_summed == CHECKSUM_PARTIAL)
785 			estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
786 		ebdp->cbd_bdu = 0;
787 		ebdp->cbd_esc = cpu_to_fec32(estatus);
788 	}
789 
790 	bdp->cbd_sc = cpu_to_fec16(status);
791 
792 	return 0;
793 }
794 
795 static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq,
796 				   struct sk_buff *skb,
797 				   struct net_device *ndev)
798 {
799 	struct fec_enet_private *fep = netdev_priv(ndev);
800 	int hdr_len, total_len, data_left;
801 	struct bufdesc *bdp = txq->bd.cur;
802 	struct tso_t tso;
803 	unsigned int index = 0;
804 	int ret;
805 
806 	if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(txq)) {
807 		dev_kfree_skb_any(skb);
808 		if (net_ratelimit())
809 			netdev_err(ndev, "NOT enough BD for TSO!\n");
810 		return NETDEV_TX_OK;
811 	}
812 
813 	/* Protocol checksum off-load for TCP and UDP. */
814 	if (fec_enet_clear_csum(skb, ndev)) {
815 		dev_kfree_skb_any(skb);
816 		return NETDEV_TX_OK;
817 	}
818 
819 	/* Initialize the TSO handler, and prepare the first payload */
820 	hdr_len = tso_start(skb, &tso);
821 
822 	total_len = skb->len - hdr_len;
823 	while (total_len > 0) {
824 		char *hdr;
825 
826 		index = fec_enet_get_bd_index(bdp, &txq->bd);
827 		data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
828 		total_len -= data_left;
829 
830 		/* prepare packet headers: MAC + IP + TCP */
831 		hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
832 		tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
833 		ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index);
834 		if (ret)
835 			goto err_release;
836 
837 		while (data_left > 0) {
838 			int size;
839 
840 			size = min_t(int, tso.size, data_left);
841 			bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
842 			index = fec_enet_get_bd_index(bdp, &txq->bd);
843 			ret = fec_enet_txq_put_data_tso(txq, skb, ndev,
844 							bdp, index,
845 							tso.data, size,
846 							size == data_left,
847 							total_len == 0);
848 			if (ret)
849 				goto err_release;
850 
851 			data_left -= size;
852 			tso_build_data(skb, &tso, size);
853 		}
854 
855 		bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
856 	}
857 
858 	/* Save skb pointer */
859 	txq->tx_skbuff[index] = skb;
860 
861 	skb_tx_timestamp(skb);
862 	txq->bd.cur = bdp;
863 
864 	/* Trigger transmission start */
865 	if (!(fep->quirks & FEC_QUIRK_ERR007885) ||
866 	    !readl(txq->bd.reg_desc_active) ||
867 	    !readl(txq->bd.reg_desc_active) ||
868 	    !readl(txq->bd.reg_desc_active) ||
869 	    !readl(txq->bd.reg_desc_active))
870 		writel(0, txq->bd.reg_desc_active);
871 
872 	return 0;
873 
874 err_release:
875 	/* TODO: Release all used data descriptors for TSO */
876 	return ret;
877 }
878 
879 static netdev_tx_t
880 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
881 {
882 	struct fec_enet_private *fep = netdev_priv(ndev);
883 	int entries_free;
884 	unsigned short queue;
885 	struct fec_enet_priv_tx_q *txq;
886 	struct netdev_queue *nq;
887 	int ret;
888 
889 	queue = skb_get_queue_mapping(skb);
890 	txq = fep->tx_queue[queue];
891 	nq = netdev_get_tx_queue(ndev, queue);
892 
893 	if (skb_is_gso(skb))
894 		ret = fec_enet_txq_submit_tso(txq, skb, ndev);
895 	else
896 		ret = fec_enet_txq_submit_skb(txq, skb, ndev);
897 	if (ret)
898 		return ret;
899 
900 	entries_free = fec_enet_get_free_txdesc_num(txq);
901 	if (entries_free <= txq->tx_stop_threshold)
902 		netif_tx_stop_queue(nq);
903 
904 	return NETDEV_TX_OK;
905 }
906 
907 /* Init RX & TX buffer descriptors
908  */
909 static void fec_enet_bd_init(struct net_device *dev)
910 {
911 	struct fec_enet_private *fep = netdev_priv(dev);
912 	struct fec_enet_priv_tx_q *txq;
913 	struct fec_enet_priv_rx_q *rxq;
914 	struct bufdesc *bdp;
915 	unsigned int i;
916 	unsigned int q;
917 
918 	for (q = 0; q < fep->num_rx_queues; q++) {
919 		/* Initialize the receive buffer descriptors. */
920 		rxq = fep->rx_queue[q];
921 		bdp = rxq->bd.base;
922 
923 		for (i = 0; i < rxq->bd.ring_size; i++) {
924 
925 			/* Initialize the BD for every fragment in the page. */
926 			if (bdp->cbd_bufaddr)
927 				bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY);
928 			else
929 				bdp->cbd_sc = cpu_to_fec16(0);
930 			bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
931 		}
932 
933 		/* Set the last buffer to wrap */
934 		bdp = fec_enet_get_prevdesc(bdp, &rxq->bd);
935 		bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
936 
937 		rxq->bd.cur = rxq->bd.base;
938 	}
939 
940 	for (q = 0; q < fep->num_tx_queues; q++) {
941 		/* ...and the same for transmit */
942 		txq = fep->tx_queue[q];
943 		bdp = txq->bd.base;
944 		txq->bd.cur = bdp;
945 
946 		for (i = 0; i < txq->bd.ring_size; i++) {
947 			/* Initialize the BD for every fragment in the page. */
948 			bdp->cbd_sc = cpu_to_fec16(0);
949 			if (bdp->cbd_bufaddr &&
950 			    !IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr)))
951 				dma_unmap_single(&fep->pdev->dev,
952 						 fec32_to_cpu(bdp->cbd_bufaddr),
953 						 fec16_to_cpu(bdp->cbd_datlen),
954 						 DMA_TO_DEVICE);
955 			if (txq->tx_skbuff[i]) {
956 				dev_kfree_skb_any(txq->tx_skbuff[i]);
957 				txq->tx_skbuff[i] = NULL;
958 			}
959 			bdp->cbd_bufaddr = cpu_to_fec32(0);
960 			bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
961 		}
962 
963 		/* Set the last buffer to wrap */
964 		bdp = fec_enet_get_prevdesc(bdp, &txq->bd);
965 		bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
966 		txq->dirty_tx = bdp;
967 	}
968 }
969 
970 static void fec_enet_active_rxring(struct net_device *ndev)
971 {
972 	struct fec_enet_private *fep = netdev_priv(ndev);
973 	int i;
974 
975 	for (i = 0; i < fep->num_rx_queues; i++)
976 		writel(0, fep->rx_queue[i]->bd.reg_desc_active);
977 }
978 
979 static void fec_enet_enable_ring(struct net_device *ndev)
980 {
981 	struct fec_enet_private *fep = netdev_priv(ndev);
982 	struct fec_enet_priv_tx_q *txq;
983 	struct fec_enet_priv_rx_q *rxq;
984 	int i;
985 
986 	for (i = 0; i < fep->num_rx_queues; i++) {
987 		rxq = fep->rx_queue[i];
988 		writel(rxq->bd.dma, fep->hwp + FEC_R_DES_START(i));
989 		writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i));
990 
991 		/* enable DMA1/2 */
992 		if (i)
993 			writel(RCMR_MATCHEN | RCMR_CMP(i),
994 			       fep->hwp + FEC_RCMR(i));
995 	}
996 
997 	for (i = 0; i < fep->num_tx_queues; i++) {
998 		txq = fep->tx_queue[i];
999 		writel(txq->bd.dma, fep->hwp + FEC_X_DES_START(i));
1000 
1001 		/* enable DMA1/2 */
1002 		if (i)
1003 			writel(DMA_CLASS_EN | IDLE_SLOPE(i),
1004 			       fep->hwp + FEC_DMA_CFG(i));
1005 	}
1006 }
1007 
1008 static void fec_enet_reset_skb(struct net_device *ndev)
1009 {
1010 	struct fec_enet_private *fep = netdev_priv(ndev);
1011 	struct fec_enet_priv_tx_q *txq;
1012 	int i, j;
1013 
1014 	for (i = 0; i < fep->num_tx_queues; i++) {
1015 		txq = fep->tx_queue[i];
1016 
1017 		for (j = 0; j < txq->bd.ring_size; j++) {
1018 			if (txq->tx_skbuff[j]) {
1019 				dev_kfree_skb_any(txq->tx_skbuff[j]);
1020 				txq->tx_skbuff[j] = NULL;
1021 			}
1022 		}
1023 	}
1024 }
1025 
1026 /*
1027  * This function is called to start or restart the FEC during a link
1028  * change, transmit timeout, or to reconfigure the FEC.  The network
1029  * packet processing for this device must be stopped before this call.
1030  */
1031 static void
1032 fec_restart(struct net_device *ndev)
1033 {
1034 	struct fec_enet_private *fep = netdev_priv(ndev);
1035 	u32 temp_mac[2];
1036 	u32 rcntl = OPT_FRAME_SIZE | 0x04;
1037 	u32 ecntl = 0x2; /* ETHEREN */
1038 
1039 	/* Whack a reset.  We should wait for this.
1040 	 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
1041 	 * instead of reset MAC itself.
1042 	 */
1043 	if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES ||
1044 	    ((fep->quirks & FEC_QUIRK_NO_HARD_RESET) && fep->link)) {
1045 		writel(0, fep->hwp + FEC_ECNTRL);
1046 	} else {
1047 		writel(1, fep->hwp + FEC_ECNTRL);
1048 		udelay(10);
1049 	}
1050 
1051 	/*
1052 	 * enet-mac reset will reset mac address registers too,
1053 	 * so need to reconfigure it.
1054 	 */
1055 	memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
1056 	writel((__force u32)cpu_to_be32(temp_mac[0]),
1057 	       fep->hwp + FEC_ADDR_LOW);
1058 	writel((__force u32)cpu_to_be32(temp_mac[1]),
1059 	       fep->hwp + FEC_ADDR_HIGH);
1060 
1061 	/* Clear any outstanding interrupt, except MDIO. */
1062 	writel((0xffffffff & ~FEC_ENET_MII), fep->hwp + FEC_IEVENT);
1063 
1064 	fec_enet_bd_init(ndev);
1065 
1066 	fec_enet_enable_ring(ndev);
1067 
1068 	/* Reset tx SKB buffers. */
1069 	fec_enet_reset_skb(ndev);
1070 
1071 	/* Enable MII mode */
1072 	if (fep->full_duplex == DUPLEX_FULL) {
1073 		/* FD enable */
1074 		writel(0x04, fep->hwp + FEC_X_CNTRL);
1075 	} else {
1076 		/* No Rcv on Xmit */
1077 		rcntl |= 0x02;
1078 		writel(0x0, fep->hwp + FEC_X_CNTRL);
1079 	}
1080 
1081 	/* Set MII speed */
1082 	writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1083 
1084 #if !defined(CONFIG_M5272)
1085 	if (fep->quirks & FEC_QUIRK_HAS_RACC) {
1086 		u32 val = readl(fep->hwp + FEC_RACC);
1087 
1088 		/* align IP header */
1089 		val |= FEC_RACC_SHIFT16;
1090 		if (fep->csum_flags & FLAG_RX_CSUM_ENABLED)
1091 			/* set RX checksum */
1092 			val |= FEC_RACC_OPTIONS;
1093 		else
1094 			val &= ~FEC_RACC_OPTIONS;
1095 		writel(val, fep->hwp + FEC_RACC);
1096 		writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_FTRL);
1097 	}
1098 #endif
1099 
1100 	/*
1101 	 * The phy interface and speed need to get configured
1102 	 * differently on enet-mac.
1103 	 */
1104 	if (fep->quirks & FEC_QUIRK_ENET_MAC) {
1105 		/* Enable flow control and length check */
1106 		rcntl |= 0x40000000 | 0x00000020;
1107 
1108 		/* RGMII, RMII or MII */
1109 		if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII ||
1110 		    fep->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
1111 		    fep->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID ||
1112 		    fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID)
1113 			rcntl |= (1 << 6);
1114 		else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
1115 			rcntl |= (1 << 8);
1116 		else
1117 			rcntl &= ~(1 << 8);
1118 
1119 		/* 1G, 100M or 10M */
1120 		if (ndev->phydev) {
1121 			if (ndev->phydev->speed == SPEED_1000)
1122 				ecntl |= (1 << 5);
1123 			else if (ndev->phydev->speed == SPEED_100)
1124 				rcntl &= ~(1 << 9);
1125 			else
1126 				rcntl |= (1 << 9);
1127 		}
1128 	} else {
1129 #ifdef FEC_MIIGSK_ENR
1130 		if (fep->quirks & FEC_QUIRK_USE_GASKET) {
1131 			u32 cfgr;
1132 			/* disable the gasket and wait */
1133 			writel(0, fep->hwp + FEC_MIIGSK_ENR);
1134 			while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
1135 				udelay(1);
1136 
1137 			/*
1138 			 * configure the gasket:
1139 			 *   RMII, 50 MHz, no loopback, no echo
1140 			 *   MII, 25 MHz, no loopback, no echo
1141 			 */
1142 			cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
1143 				? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
1144 			if (ndev->phydev && ndev->phydev->speed == SPEED_10)
1145 				cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
1146 			writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
1147 
1148 			/* re-enable the gasket */
1149 			writel(2, fep->hwp + FEC_MIIGSK_ENR);
1150 		}
1151 #endif
1152 	}
1153 
1154 #if !defined(CONFIG_M5272)
1155 	/* enable pause frame*/
1156 	if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
1157 	    ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
1158 	     ndev->phydev && ndev->phydev->pause)) {
1159 		rcntl |= FEC_ENET_FCE;
1160 
1161 		/* set FIFO threshold parameter to reduce overrun */
1162 		writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
1163 		writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
1164 		writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
1165 		writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
1166 
1167 		/* OPD */
1168 		writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
1169 	} else {
1170 		rcntl &= ~FEC_ENET_FCE;
1171 	}
1172 #endif /* !defined(CONFIG_M5272) */
1173 
1174 	writel(rcntl, fep->hwp + FEC_R_CNTRL);
1175 
1176 	/* Setup multicast filter. */
1177 	set_multicast_list(ndev);
1178 #ifndef CONFIG_M5272
1179 	writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
1180 	writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
1181 #endif
1182 
1183 	if (fep->quirks & FEC_QUIRK_ENET_MAC) {
1184 		/* enable ENET endian swap */
1185 		ecntl |= (1 << 8);
1186 		/* enable ENET store and forward mode */
1187 		writel(1 << 8, fep->hwp + FEC_X_WMRK);
1188 	}
1189 
1190 	if (fep->bufdesc_ex)
1191 		ecntl |= (1 << 4);
1192 
1193 	if (fep->quirks & FEC_QUIRK_DELAYED_CLKS_SUPPORT &&
1194 	    fep->rgmii_txc_dly)
1195 		ecntl |= FEC_ENET_TXC_DLY;
1196 	if (fep->quirks & FEC_QUIRK_DELAYED_CLKS_SUPPORT &&
1197 	    fep->rgmii_rxc_dly)
1198 		ecntl |= FEC_ENET_RXC_DLY;
1199 
1200 #ifndef CONFIG_M5272
1201 	/* Enable the MIB statistic event counters */
1202 	writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT);
1203 #endif
1204 
1205 	/* And last, enable the transmit and receive processing */
1206 	writel(ecntl, fep->hwp + FEC_ECNTRL);
1207 	fec_enet_active_rxring(ndev);
1208 
1209 	if (fep->bufdesc_ex)
1210 		fec_ptp_start_cyclecounter(ndev);
1211 
1212 	/* Enable interrupts we wish to service */
1213 	if (fep->link)
1214 		writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1215 	else
1216 		writel(0, fep->hwp + FEC_IMASK);
1217 
1218 	/* Init the interrupt coalescing */
1219 	if (fep->quirks & FEC_QUIRK_HAS_COALESCE)
1220 		fec_enet_itr_coal_set(ndev);
1221 }
1222 
1223 static int fec_enet_ipc_handle_init(struct fec_enet_private *fep)
1224 {
1225 	if (!(of_machine_is_compatible("fsl,imx8qm") ||
1226 	      of_machine_is_compatible("fsl,imx8qxp") ||
1227 	      of_machine_is_compatible("fsl,imx8dxl")))
1228 		return 0;
1229 
1230 	return imx_scu_get_handle(&fep->ipc_handle);
1231 }
1232 
1233 static void fec_enet_ipg_stop_set(struct fec_enet_private *fep, bool enabled)
1234 {
1235 	struct device_node *np = fep->pdev->dev.of_node;
1236 	u32 rsrc_id, val;
1237 	int idx;
1238 
1239 	if (!np || !fep->ipc_handle)
1240 		return;
1241 
1242 	idx = of_alias_get_id(np, "ethernet");
1243 	if (idx < 0)
1244 		idx = 0;
1245 	rsrc_id = idx ? IMX_SC_R_ENET_1 : IMX_SC_R_ENET_0;
1246 
1247 	val = enabled ? 1 : 0;
1248 	imx_sc_misc_set_control(fep->ipc_handle, rsrc_id, IMX_SC_C_IPG_STOP, val);
1249 }
1250 
1251 static void fec_enet_stop_mode(struct fec_enet_private *fep, bool enabled)
1252 {
1253 	struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
1254 	struct fec_stop_mode_gpr *stop_gpr = &fep->stop_gpr;
1255 
1256 	if (stop_gpr->gpr) {
1257 		if (enabled)
1258 			regmap_update_bits(stop_gpr->gpr, stop_gpr->reg,
1259 					   BIT(stop_gpr->bit),
1260 					   BIT(stop_gpr->bit));
1261 		else
1262 			regmap_update_bits(stop_gpr->gpr, stop_gpr->reg,
1263 					   BIT(stop_gpr->bit), 0);
1264 	} else if (pdata && pdata->sleep_mode_enable) {
1265 		pdata->sleep_mode_enable(enabled);
1266 	} else {
1267 		fec_enet_ipg_stop_set(fep, enabled);
1268 	}
1269 }
1270 
1271 static void fec_irqs_disable(struct net_device *ndev)
1272 {
1273 	struct fec_enet_private *fep = netdev_priv(ndev);
1274 
1275 	writel(0, fep->hwp + FEC_IMASK);
1276 }
1277 
1278 static void fec_irqs_disable_except_wakeup(struct net_device *ndev)
1279 {
1280 	struct fec_enet_private *fep = netdev_priv(ndev);
1281 
1282 	writel(0, fep->hwp + FEC_IMASK);
1283 	writel(FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK);
1284 }
1285 
1286 static void
1287 fec_stop(struct net_device *ndev)
1288 {
1289 	struct fec_enet_private *fep = netdev_priv(ndev);
1290 	u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
1291 	u32 val;
1292 
1293 	/* We cannot expect a graceful transmit stop without link !!! */
1294 	if (fep->link) {
1295 		writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
1296 		udelay(10);
1297 		if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
1298 			netdev_err(ndev, "Graceful transmit stop did not complete!\n");
1299 	}
1300 
1301 	/* Whack a reset.  We should wait for this.
1302 	 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
1303 	 * instead of reset MAC itself.
1304 	 */
1305 	if (!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
1306 		if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) {
1307 			writel(0, fep->hwp + FEC_ECNTRL);
1308 		} else {
1309 			writel(1, fep->hwp + FEC_ECNTRL);
1310 			udelay(10);
1311 		}
1312 	} else {
1313 		val = readl(fep->hwp + FEC_ECNTRL);
1314 		val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
1315 		writel(val, fep->hwp + FEC_ECNTRL);
1316 	}
1317 	writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1318 	writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1319 
1320 	/* We have to keep ENET enabled to have MII interrupt stay working */
1321 	if (fep->quirks & FEC_QUIRK_ENET_MAC &&
1322 		!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
1323 		writel(2, fep->hwp + FEC_ECNTRL);
1324 		writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
1325 	}
1326 }
1327 
1328 
1329 static void
1330 fec_timeout(struct net_device *ndev, unsigned int txqueue)
1331 {
1332 	struct fec_enet_private *fep = netdev_priv(ndev);
1333 
1334 	fec_dump(ndev);
1335 
1336 	ndev->stats.tx_errors++;
1337 
1338 	schedule_work(&fep->tx_timeout_work);
1339 }
1340 
1341 static void fec_enet_timeout_work(struct work_struct *work)
1342 {
1343 	struct fec_enet_private *fep =
1344 		container_of(work, struct fec_enet_private, tx_timeout_work);
1345 	struct net_device *ndev = fep->netdev;
1346 
1347 	rtnl_lock();
1348 	if (netif_device_present(ndev) || netif_running(ndev)) {
1349 		napi_disable(&fep->napi);
1350 		netif_tx_lock_bh(ndev);
1351 		fec_restart(ndev);
1352 		netif_tx_wake_all_queues(ndev);
1353 		netif_tx_unlock_bh(ndev);
1354 		napi_enable(&fep->napi);
1355 	}
1356 	rtnl_unlock();
1357 }
1358 
1359 static void
1360 fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts,
1361 	struct skb_shared_hwtstamps *hwtstamps)
1362 {
1363 	unsigned long flags;
1364 	u64 ns;
1365 
1366 	spin_lock_irqsave(&fep->tmreg_lock, flags);
1367 	ns = timecounter_cyc2time(&fep->tc, ts);
1368 	spin_unlock_irqrestore(&fep->tmreg_lock, flags);
1369 
1370 	memset(hwtstamps, 0, sizeof(*hwtstamps));
1371 	hwtstamps->hwtstamp = ns_to_ktime(ns);
1372 }
1373 
1374 static void
1375 fec_enet_tx_queue(struct net_device *ndev, u16 queue_id)
1376 {
1377 	struct	fec_enet_private *fep;
1378 	struct bufdesc *bdp;
1379 	unsigned short status;
1380 	struct	sk_buff	*skb;
1381 	struct fec_enet_priv_tx_q *txq;
1382 	struct netdev_queue *nq;
1383 	int	index = 0;
1384 	int	entries_free;
1385 
1386 	fep = netdev_priv(ndev);
1387 
1388 	txq = fep->tx_queue[queue_id];
1389 	/* get next bdp of dirty_tx */
1390 	nq = netdev_get_tx_queue(ndev, queue_id);
1391 	bdp = txq->dirty_tx;
1392 
1393 	/* get next bdp of dirty_tx */
1394 	bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
1395 
1396 	while (bdp != READ_ONCE(txq->bd.cur)) {
1397 		/* Order the load of bd.cur and cbd_sc */
1398 		rmb();
1399 		status = fec16_to_cpu(READ_ONCE(bdp->cbd_sc));
1400 		if (status & BD_ENET_TX_READY)
1401 			break;
1402 
1403 		index = fec_enet_get_bd_index(bdp, &txq->bd);
1404 
1405 		skb = txq->tx_skbuff[index];
1406 		txq->tx_skbuff[index] = NULL;
1407 		if (!IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr)))
1408 			dma_unmap_single(&fep->pdev->dev,
1409 					 fec32_to_cpu(bdp->cbd_bufaddr),
1410 					 fec16_to_cpu(bdp->cbd_datlen),
1411 					 DMA_TO_DEVICE);
1412 		bdp->cbd_bufaddr = cpu_to_fec32(0);
1413 		if (!skb)
1414 			goto skb_done;
1415 
1416 		/* Check for errors. */
1417 		if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
1418 				   BD_ENET_TX_RL | BD_ENET_TX_UN |
1419 				   BD_ENET_TX_CSL)) {
1420 			ndev->stats.tx_errors++;
1421 			if (status & BD_ENET_TX_HB)  /* No heartbeat */
1422 				ndev->stats.tx_heartbeat_errors++;
1423 			if (status & BD_ENET_TX_LC)  /* Late collision */
1424 				ndev->stats.tx_window_errors++;
1425 			if (status & BD_ENET_TX_RL)  /* Retrans limit */
1426 				ndev->stats.tx_aborted_errors++;
1427 			if (status & BD_ENET_TX_UN)  /* Underrun */
1428 				ndev->stats.tx_fifo_errors++;
1429 			if (status & BD_ENET_TX_CSL) /* Carrier lost */
1430 				ndev->stats.tx_carrier_errors++;
1431 		} else {
1432 			ndev->stats.tx_packets++;
1433 			ndev->stats.tx_bytes += skb->len;
1434 		}
1435 
1436 		/* NOTE: SKBTX_IN_PROGRESS being set does not imply it's we who
1437 		 * are to time stamp the packet, so we still need to check time
1438 		 * stamping enabled flag.
1439 		 */
1440 		if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS &&
1441 			     fep->hwts_tx_en) &&
1442 		    fep->bufdesc_ex) {
1443 			struct skb_shared_hwtstamps shhwtstamps;
1444 			struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1445 
1446 			fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), &shhwtstamps);
1447 			skb_tstamp_tx(skb, &shhwtstamps);
1448 		}
1449 
1450 		/* Deferred means some collisions occurred during transmit,
1451 		 * but we eventually sent the packet OK.
1452 		 */
1453 		if (status & BD_ENET_TX_DEF)
1454 			ndev->stats.collisions++;
1455 
1456 		/* Free the sk buffer associated with this last transmit */
1457 		dev_kfree_skb_any(skb);
1458 skb_done:
1459 		/* Make sure the update to bdp and tx_skbuff are performed
1460 		 * before dirty_tx
1461 		 */
1462 		wmb();
1463 		txq->dirty_tx = bdp;
1464 
1465 		/* Update pointer to next buffer descriptor to be transmitted */
1466 		bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
1467 
1468 		/* Since we have freed up a buffer, the ring is no longer full
1469 		 */
1470 		if (netif_tx_queue_stopped(nq)) {
1471 			entries_free = fec_enet_get_free_txdesc_num(txq);
1472 			if (entries_free >= txq->tx_wake_threshold)
1473 				netif_tx_wake_queue(nq);
1474 		}
1475 	}
1476 
1477 	/* ERR006358: Keep the transmitter going */
1478 	if (bdp != txq->bd.cur &&
1479 	    readl(txq->bd.reg_desc_active) == 0)
1480 		writel(0, txq->bd.reg_desc_active);
1481 }
1482 
1483 static void fec_enet_tx(struct net_device *ndev)
1484 {
1485 	struct fec_enet_private *fep = netdev_priv(ndev);
1486 	int i;
1487 
1488 	/* Make sure that AVB queues are processed first. */
1489 	for (i = fep->num_tx_queues - 1; i >= 0; i--)
1490 		fec_enet_tx_queue(ndev, i);
1491 }
1492 
1493 static void fec_enet_update_cbd(struct fec_enet_priv_rx_q *rxq,
1494 				struct bufdesc *bdp, int index)
1495 {
1496 	struct page *new_page;
1497 	dma_addr_t phys_addr;
1498 
1499 	new_page = page_pool_dev_alloc_pages(rxq->page_pool);
1500 	WARN_ON(!new_page);
1501 	rxq->rx_skb_info[index].page = new_page;
1502 
1503 	rxq->rx_skb_info[index].offset = FEC_ENET_XDP_HEADROOM;
1504 	phys_addr = page_pool_get_dma_addr(new_page) + FEC_ENET_XDP_HEADROOM;
1505 	bdp->cbd_bufaddr = cpu_to_fec32(phys_addr);
1506 }
1507 
1508 static u32
1509 fec_enet_run_xdp(struct fec_enet_private *fep, struct bpf_prog *prog,
1510 		 struct xdp_buff *xdp, struct fec_enet_priv_rx_q *rxq, int index)
1511 {
1512 	unsigned int sync, len = xdp->data_end - xdp->data;
1513 	u32 ret = FEC_ENET_XDP_PASS;
1514 	struct page *page;
1515 	int err;
1516 	u32 act;
1517 
1518 	act = bpf_prog_run_xdp(prog, xdp);
1519 
1520 	/* Due xdp_adjust_tail: DMA sync for_device cover max len CPU touch */
1521 	sync = xdp->data_end - xdp->data_hard_start - FEC_ENET_XDP_HEADROOM;
1522 	sync = max(sync, len);
1523 
1524 	switch (act) {
1525 	case XDP_PASS:
1526 		rxq->stats[RX_XDP_PASS]++;
1527 		ret = FEC_ENET_XDP_PASS;
1528 		break;
1529 
1530 	case XDP_REDIRECT:
1531 		rxq->stats[RX_XDP_REDIRECT]++;
1532 		err = xdp_do_redirect(fep->netdev, xdp, prog);
1533 		if (!err) {
1534 			ret = FEC_ENET_XDP_REDIR;
1535 		} else {
1536 			ret = FEC_ENET_XDP_CONSUMED;
1537 			page = virt_to_head_page(xdp->data);
1538 			page_pool_put_page(rxq->page_pool, page, sync, true);
1539 		}
1540 		break;
1541 
1542 	default:
1543 		bpf_warn_invalid_xdp_action(fep->netdev, prog, act);
1544 		fallthrough;
1545 
1546 	case XDP_TX:
1547 		bpf_warn_invalid_xdp_action(fep->netdev, prog, act);
1548 		fallthrough;
1549 
1550 	case XDP_ABORTED:
1551 		fallthrough;    /* handle aborts by dropping packet */
1552 
1553 	case XDP_DROP:
1554 		rxq->stats[RX_XDP_DROP]++;
1555 		ret = FEC_ENET_XDP_CONSUMED;
1556 		page = virt_to_head_page(xdp->data);
1557 		page_pool_put_page(rxq->page_pool, page, sync, true);
1558 		break;
1559 	}
1560 
1561 	return ret;
1562 }
1563 
1564 /* During a receive, the bd_rx.cur points to the current incoming buffer.
1565  * When we update through the ring, if the next incoming buffer has
1566  * not been given to the system, we just set the empty indicator,
1567  * effectively tossing the packet.
1568  */
1569 static int
1570 fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id)
1571 {
1572 	struct fec_enet_private *fep = netdev_priv(ndev);
1573 	struct fec_enet_priv_rx_q *rxq;
1574 	struct bufdesc *bdp;
1575 	unsigned short status;
1576 	struct  sk_buff *skb;
1577 	ushort	pkt_len;
1578 	__u8 *data;
1579 	int	pkt_received = 0;
1580 	struct	bufdesc_ex *ebdp = NULL;
1581 	bool	vlan_packet_rcvd = false;
1582 	u16	vlan_tag;
1583 	int	index = 0;
1584 	bool	need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME;
1585 	struct bpf_prog *xdp_prog = READ_ONCE(fep->xdp_prog);
1586 	u32 ret, xdp_result = FEC_ENET_XDP_PASS;
1587 	u32 data_start = FEC_ENET_XDP_HEADROOM;
1588 	struct xdp_buff xdp;
1589 	struct page *page;
1590 	u32 sub_len = 4;
1591 
1592 #if !defined(CONFIG_M5272)
1593 	/*If it has the FEC_QUIRK_HAS_RACC quirk property, the bit of
1594 	 * FEC_RACC_SHIFT16 is set by default in the probe function.
1595 	 */
1596 	if (fep->quirks & FEC_QUIRK_HAS_RACC) {
1597 		data_start += 2;
1598 		sub_len += 2;
1599 	}
1600 #endif
1601 
1602 #ifdef CONFIG_M532x
1603 	flush_cache_all();
1604 #endif
1605 	rxq = fep->rx_queue[queue_id];
1606 
1607 	/* First, grab all of the stats for the incoming packet.
1608 	 * These get messed up if we get called due to a busy condition.
1609 	 */
1610 	bdp = rxq->bd.cur;
1611 	xdp_init_buff(&xdp, PAGE_SIZE, &rxq->xdp_rxq);
1612 
1613 	while (!((status = fec16_to_cpu(bdp->cbd_sc)) & BD_ENET_RX_EMPTY)) {
1614 
1615 		if (pkt_received >= budget)
1616 			break;
1617 		pkt_received++;
1618 
1619 		writel(FEC_ENET_RXF_GET(queue_id), fep->hwp + FEC_IEVENT);
1620 
1621 		/* Check for errors. */
1622 		status ^= BD_ENET_RX_LAST;
1623 		if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
1624 			   BD_ENET_RX_CR | BD_ENET_RX_OV | BD_ENET_RX_LAST |
1625 			   BD_ENET_RX_CL)) {
1626 			ndev->stats.rx_errors++;
1627 			if (status & BD_ENET_RX_OV) {
1628 				/* FIFO overrun */
1629 				ndev->stats.rx_fifo_errors++;
1630 				goto rx_processing_done;
1631 			}
1632 			if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH
1633 						| BD_ENET_RX_LAST)) {
1634 				/* Frame too long or too short. */
1635 				ndev->stats.rx_length_errors++;
1636 				if (status & BD_ENET_RX_LAST)
1637 					netdev_err(ndev, "rcv is not +last\n");
1638 			}
1639 			if (status & BD_ENET_RX_CR)	/* CRC Error */
1640 				ndev->stats.rx_crc_errors++;
1641 			/* Report late collisions as a frame error. */
1642 			if (status & (BD_ENET_RX_NO | BD_ENET_RX_CL))
1643 				ndev->stats.rx_frame_errors++;
1644 			goto rx_processing_done;
1645 		}
1646 
1647 		/* Process the incoming frame. */
1648 		ndev->stats.rx_packets++;
1649 		pkt_len = fec16_to_cpu(bdp->cbd_datlen);
1650 		ndev->stats.rx_bytes += pkt_len;
1651 
1652 		index = fec_enet_get_bd_index(bdp, &rxq->bd);
1653 		page = rxq->rx_skb_info[index].page;
1654 		dma_sync_single_for_cpu(&fep->pdev->dev,
1655 					fec32_to_cpu(bdp->cbd_bufaddr),
1656 					pkt_len,
1657 					DMA_FROM_DEVICE);
1658 		prefetch(page_address(page));
1659 		fec_enet_update_cbd(rxq, bdp, index);
1660 
1661 		if (xdp_prog) {
1662 			xdp_buff_clear_frags_flag(&xdp);
1663 			/* subtract 16bit shift and FCS */
1664 			xdp_prepare_buff(&xdp, page_address(page),
1665 					 data_start, pkt_len - sub_len, false);
1666 			ret = fec_enet_run_xdp(fep, xdp_prog, &xdp, rxq, index);
1667 			xdp_result |= ret;
1668 			if (ret != FEC_ENET_XDP_PASS)
1669 				goto rx_processing_done;
1670 		}
1671 
1672 		/* The packet length includes FCS, but we don't want to
1673 		 * include that when passing upstream as it messes up
1674 		 * bridging applications.
1675 		 */
1676 		skb = build_skb(page_address(page), PAGE_SIZE);
1677 		if (unlikely(!skb)) {
1678 			page_pool_recycle_direct(rxq->page_pool, page);
1679 			ndev->stats.rx_dropped++;
1680 
1681 			netdev_err_once(ndev, "build_skb failed!\n");
1682 			goto rx_processing_done;
1683 		}
1684 
1685 		skb_reserve(skb, data_start);
1686 		skb_put(skb, pkt_len - sub_len);
1687 		skb_mark_for_recycle(skb);
1688 
1689 		if (unlikely(need_swap)) {
1690 			data = page_address(page) + FEC_ENET_XDP_HEADROOM;
1691 			swap_buffer(data, pkt_len);
1692 		}
1693 		data = skb->data;
1694 
1695 		/* Extract the enhanced buffer descriptor */
1696 		ebdp = NULL;
1697 		if (fep->bufdesc_ex)
1698 			ebdp = (struct bufdesc_ex *)bdp;
1699 
1700 		/* If this is a VLAN packet remove the VLAN Tag */
1701 		vlan_packet_rcvd = false;
1702 		if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1703 		    fep->bufdesc_ex &&
1704 		    (ebdp->cbd_esc & cpu_to_fec32(BD_ENET_RX_VLAN))) {
1705 			/* Push and remove the vlan tag */
1706 			struct vlan_hdr *vlan_header =
1707 					(struct vlan_hdr *) (data + ETH_HLEN);
1708 			vlan_tag = ntohs(vlan_header->h_vlan_TCI);
1709 
1710 			vlan_packet_rcvd = true;
1711 
1712 			memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2);
1713 			skb_pull(skb, VLAN_HLEN);
1714 		}
1715 
1716 		skb->protocol = eth_type_trans(skb, ndev);
1717 
1718 		/* Get receive timestamp from the skb */
1719 		if (fep->hwts_rx_en && fep->bufdesc_ex)
1720 			fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts),
1721 					  skb_hwtstamps(skb));
1722 
1723 		if (fep->bufdesc_ex &&
1724 		    (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) {
1725 			if (!(ebdp->cbd_esc & cpu_to_fec32(FLAG_RX_CSUM_ERROR))) {
1726 				/* don't check it */
1727 				skb->ip_summed = CHECKSUM_UNNECESSARY;
1728 			} else {
1729 				skb_checksum_none_assert(skb);
1730 			}
1731 		}
1732 
1733 		/* Handle received VLAN packets */
1734 		if (vlan_packet_rcvd)
1735 			__vlan_hwaccel_put_tag(skb,
1736 					       htons(ETH_P_8021Q),
1737 					       vlan_tag);
1738 
1739 		skb_record_rx_queue(skb, queue_id);
1740 		napi_gro_receive(&fep->napi, skb);
1741 
1742 rx_processing_done:
1743 		/* Clear the status flags for this buffer */
1744 		status &= ~BD_ENET_RX_STATS;
1745 
1746 		/* Mark the buffer empty */
1747 		status |= BD_ENET_RX_EMPTY;
1748 
1749 		if (fep->bufdesc_ex) {
1750 			struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1751 
1752 			ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT);
1753 			ebdp->cbd_prot = 0;
1754 			ebdp->cbd_bdu = 0;
1755 		}
1756 		/* Make sure the updates to rest of the descriptor are
1757 		 * performed before transferring ownership.
1758 		 */
1759 		wmb();
1760 		bdp->cbd_sc = cpu_to_fec16(status);
1761 
1762 		/* Update BD pointer to next entry */
1763 		bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
1764 
1765 		/* Doing this here will keep the FEC running while we process
1766 		 * incoming frames.  On a heavily loaded network, we should be
1767 		 * able to keep up at the expense of system resources.
1768 		 */
1769 		writel(0, rxq->bd.reg_desc_active);
1770 	}
1771 	rxq->bd.cur = bdp;
1772 
1773 	if (xdp_result & FEC_ENET_XDP_REDIR)
1774 		xdp_do_flush_map();
1775 
1776 	return pkt_received;
1777 }
1778 
1779 static int fec_enet_rx(struct net_device *ndev, int budget)
1780 {
1781 	struct fec_enet_private *fep = netdev_priv(ndev);
1782 	int i, done = 0;
1783 
1784 	/* Make sure that AVB queues are processed first. */
1785 	for (i = fep->num_rx_queues - 1; i >= 0; i--)
1786 		done += fec_enet_rx_queue(ndev, budget - done, i);
1787 
1788 	return done;
1789 }
1790 
1791 static bool fec_enet_collect_events(struct fec_enet_private *fep)
1792 {
1793 	uint int_events;
1794 
1795 	int_events = readl(fep->hwp + FEC_IEVENT);
1796 
1797 	/* Don't clear MDIO events, we poll for those */
1798 	int_events &= ~FEC_ENET_MII;
1799 
1800 	writel(int_events, fep->hwp + FEC_IEVENT);
1801 
1802 	return int_events != 0;
1803 }
1804 
1805 static irqreturn_t
1806 fec_enet_interrupt(int irq, void *dev_id)
1807 {
1808 	struct net_device *ndev = dev_id;
1809 	struct fec_enet_private *fep = netdev_priv(ndev);
1810 	irqreturn_t ret = IRQ_NONE;
1811 
1812 	if (fec_enet_collect_events(fep) && fep->link) {
1813 		ret = IRQ_HANDLED;
1814 
1815 		if (napi_schedule_prep(&fep->napi)) {
1816 			/* Disable interrupts */
1817 			writel(0, fep->hwp + FEC_IMASK);
1818 			__napi_schedule(&fep->napi);
1819 		}
1820 	}
1821 
1822 	return ret;
1823 }
1824 
1825 static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
1826 {
1827 	struct net_device *ndev = napi->dev;
1828 	struct fec_enet_private *fep = netdev_priv(ndev);
1829 	int done = 0;
1830 
1831 	do {
1832 		done += fec_enet_rx(ndev, budget - done);
1833 		fec_enet_tx(ndev);
1834 	} while ((done < budget) && fec_enet_collect_events(fep));
1835 
1836 	if (done < budget) {
1837 		napi_complete_done(napi, done);
1838 		writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1839 	}
1840 
1841 	return done;
1842 }
1843 
1844 /* ------------------------------------------------------------------------- */
1845 static int fec_get_mac(struct net_device *ndev)
1846 {
1847 	struct fec_enet_private *fep = netdev_priv(ndev);
1848 	unsigned char *iap, tmpaddr[ETH_ALEN];
1849 	int ret;
1850 
1851 	/*
1852 	 * try to get mac address in following order:
1853 	 *
1854 	 * 1) module parameter via kernel command line in form
1855 	 *    fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
1856 	 */
1857 	iap = macaddr;
1858 
1859 	/*
1860 	 * 2) from device tree data
1861 	 */
1862 	if (!is_valid_ether_addr(iap)) {
1863 		struct device_node *np = fep->pdev->dev.of_node;
1864 		if (np) {
1865 			ret = of_get_mac_address(np, tmpaddr);
1866 			if (!ret)
1867 				iap = tmpaddr;
1868 			else if (ret == -EPROBE_DEFER)
1869 				return ret;
1870 		}
1871 	}
1872 
1873 	/*
1874 	 * 3) from flash or fuse (via platform data)
1875 	 */
1876 	if (!is_valid_ether_addr(iap)) {
1877 #ifdef CONFIG_M5272
1878 		if (FEC_FLASHMAC)
1879 			iap = (unsigned char *)FEC_FLASHMAC;
1880 #else
1881 		struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev);
1882 
1883 		if (pdata)
1884 			iap = (unsigned char *)&pdata->mac;
1885 #endif
1886 	}
1887 
1888 	/*
1889 	 * 4) FEC mac registers set by bootloader
1890 	 */
1891 	if (!is_valid_ether_addr(iap)) {
1892 		*((__be32 *) &tmpaddr[0]) =
1893 			cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW));
1894 		*((__be16 *) &tmpaddr[4]) =
1895 			cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
1896 		iap = &tmpaddr[0];
1897 	}
1898 
1899 	/*
1900 	 * 5) random mac address
1901 	 */
1902 	if (!is_valid_ether_addr(iap)) {
1903 		/* Report it and use a random ethernet address instead */
1904 		dev_err(&fep->pdev->dev, "Invalid MAC address: %pM\n", iap);
1905 		eth_hw_addr_random(ndev);
1906 		dev_info(&fep->pdev->dev, "Using random MAC address: %pM\n",
1907 			 ndev->dev_addr);
1908 		return 0;
1909 	}
1910 
1911 	/* Adjust MAC if using macaddr */
1912 	eth_hw_addr_gen(ndev, iap, iap == macaddr ? fep->dev_id : 0);
1913 
1914 	return 0;
1915 }
1916 
1917 /* ------------------------------------------------------------------------- */
1918 
1919 /*
1920  * Phy section
1921  */
1922 static void fec_enet_adjust_link(struct net_device *ndev)
1923 {
1924 	struct fec_enet_private *fep = netdev_priv(ndev);
1925 	struct phy_device *phy_dev = ndev->phydev;
1926 	int status_change = 0;
1927 
1928 	/*
1929 	 * If the netdev is down, or is going down, we're not interested
1930 	 * in link state events, so just mark our idea of the link as down
1931 	 * and ignore the event.
1932 	 */
1933 	if (!netif_running(ndev) || !netif_device_present(ndev)) {
1934 		fep->link = 0;
1935 	} else if (phy_dev->link) {
1936 		if (!fep->link) {
1937 			fep->link = phy_dev->link;
1938 			status_change = 1;
1939 		}
1940 
1941 		if (fep->full_duplex != phy_dev->duplex) {
1942 			fep->full_duplex = phy_dev->duplex;
1943 			status_change = 1;
1944 		}
1945 
1946 		if (phy_dev->speed != fep->speed) {
1947 			fep->speed = phy_dev->speed;
1948 			status_change = 1;
1949 		}
1950 
1951 		/* if any of the above changed restart the FEC */
1952 		if (status_change) {
1953 			napi_disable(&fep->napi);
1954 			netif_tx_lock_bh(ndev);
1955 			fec_restart(ndev);
1956 			netif_tx_wake_all_queues(ndev);
1957 			netif_tx_unlock_bh(ndev);
1958 			napi_enable(&fep->napi);
1959 		}
1960 	} else {
1961 		if (fep->link) {
1962 			napi_disable(&fep->napi);
1963 			netif_tx_lock_bh(ndev);
1964 			fec_stop(ndev);
1965 			netif_tx_unlock_bh(ndev);
1966 			napi_enable(&fep->napi);
1967 			fep->link = phy_dev->link;
1968 			status_change = 1;
1969 		}
1970 	}
1971 
1972 	if (status_change)
1973 		phy_print_status(phy_dev);
1974 }
1975 
1976 static int fec_enet_mdio_wait(struct fec_enet_private *fep)
1977 {
1978 	uint ievent;
1979 	int ret;
1980 
1981 	ret = readl_poll_timeout_atomic(fep->hwp + FEC_IEVENT, ievent,
1982 					ievent & FEC_ENET_MII, 2, 30000);
1983 
1984 	if (!ret)
1985 		writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT);
1986 
1987 	return ret;
1988 }
1989 
1990 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1991 {
1992 	struct fec_enet_private *fep = bus->priv;
1993 	struct device *dev = &fep->pdev->dev;
1994 	int ret = 0, frame_start, frame_addr, frame_op;
1995 	bool is_c45 = !!(regnum & MII_ADDR_C45);
1996 
1997 	ret = pm_runtime_resume_and_get(dev);
1998 	if (ret < 0)
1999 		return ret;
2000 
2001 	if (is_c45) {
2002 		frame_start = FEC_MMFR_ST_C45;
2003 
2004 		/* write address */
2005 		frame_addr = (regnum >> 16);
2006 		writel(frame_start | FEC_MMFR_OP_ADDR_WRITE |
2007 		       FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) |
2008 		       FEC_MMFR_TA | (regnum & 0xFFFF),
2009 		       fep->hwp + FEC_MII_DATA);
2010 
2011 		/* wait for end of transfer */
2012 		ret = fec_enet_mdio_wait(fep);
2013 		if (ret) {
2014 			netdev_err(fep->netdev, "MDIO address write timeout\n");
2015 			goto out;
2016 		}
2017 
2018 		frame_op = FEC_MMFR_OP_READ_C45;
2019 
2020 	} else {
2021 		/* C22 read */
2022 		frame_op = FEC_MMFR_OP_READ;
2023 		frame_start = FEC_MMFR_ST;
2024 		frame_addr = regnum;
2025 	}
2026 
2027 	/* start a read op */
2028 	writel(frame_start | frame_op |
2029 		FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) |
2030 		FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
2031 
2032 	/* wait for end of transfer */
2033 	ret = fec_enet_mdio_wait(fep);
2034 	if (ret) {
2035 		netdev_err(fep->netdev, "MDIO read timeout\n");
2036 		goto out;
2037 	}
2038 
2039 	ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
2040 
2041 out:
2042 	pm_runtime_mark_last_busy(dev);
2043 	pm_runtime_put_autosuspend(dev);
2044 
2045 	return ret;
2046 }
2047 
2048 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
2049 			   u16 value)
2050 {
2051 	struct fec_enet_private *fep = bus->priv;
2052 	struct device *dev = &fep->pdev->dev;
2053 	int ret, frame_start, frame_addr;
2054 	bool is_c45 = !!(regnum & MII_ADDR_C45);
2055 
2056 	ret = pm_runtime_resume_and_get(dev);
2057 	if (ret < 0)
2058 		return ret;
2059 
2060 	if (is_c45) {
2061 		frame_start = FEC_MMFR_ST_C45;
2062 
2063 		/* write address */
2064 		frame_addr = (regnum >> 16);
2065 		writel(frame_start | FEC_MMFR_OP_ADDR_WRITE |
2066 		       FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) |
2067 		       FEC_MMFR_TA | (regnum & 0xFFFF),
2068 		       fep->hwp + FEC_MII_DATA);
2069 
2070 		/* wait for end of transfer */
2071 		ret = fec_enet_mdio_wait(fep);
2072 		if (ret) {
2073 			netdev_err(fep->netdev, "MDIO address write timeout\n");
2074 			goto out;
2075 		}
2076 	} else {
2077 		/* C22 write */
2078 		frame_start = FEC_MMFR_ST;
2079 		frame_addr = regnum;
2080 	}
2081 
2082 	/* start a write op */
2083 	writel(frame_start | FEC_MMFR_OP_WRITE |
2084 		FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) |
2085 		FEC_MMFR_TA | FEC_MMFR_DATA(value),
2086 		fep->hwp + FEC_MII_DATA);
2087 
2088 	/* wait for end of transfer */
2089 	ret = fec_enet_mdio_wait(fep);
2090 	if (ret)
2091 		netdev_err(fep->netdev, "MDIO write timeout\n");
2092 
2093 out:
2094 	pm_runtime_mark_last_busy(dev);
2095 	pm_runtime_put_autosuspend(dev);
2096 
2097 	return ret;
2098 }
2099 
2100 static void fec_enet_phy_reset_after_clk_enable(struct net_device *ndev)
2101 {
2102 	struct fec_enet_private *fep = netdev_priv(ndev);
2103 	struct phy_device *phy_dev = ndev->phydev;
2104 
2105 	if (phy_dev) {
2106 		phy_reset_after_clk_enable(phy_dev);
2107 	} else if (fep->phy_node) {
2108 		/*
2109 		 * If the PHY still is not bound to the MAC, but there is
2110 		 * OF PHY node and a matching PHY device instance already,
2111 		 * use the OF PHY node to obtain the PHY device instance,
2112 		 * and then use that PHY device instance when triggering
2113 		 * the PHY reset.
2114 		 */
2115 		phy_dev = of_phy_find_device(fep->phy_node);
2116 		phy_reset_after_clk_enable(phy_dev);
2117 		put_device(&phy_dev->mdio.dev);
2118 	}
2119 }
2120 
2121 static int fec_enet_clk_enable(struct net_device *ndev, bool enable)
2122 {
2123 	struct fec_enet_private *fep = netdev_priv(ndev);
2124 	int ret;
2125 
2126 	if (enable) {
2127 		ret = clk_prepare_enable(fep->clk_enet_out);
2128 		if (ret)
2129 			return ret;
2130 
2131 		if (fep->clk_ptp) {
2132 			mutex_lock(&fep->ptp_clk_mutex);
2133 			ret = clk_prepare_enable(fep->clk_ptp);
2134 			if (ret) {
2135 				mutex_unlock(&fep->ptp_clk_mutex);
2136 				goto failed_clk_ptp;
2137 			} else {
2138 				fep->ptp_clk_on = true;
2139 			}
2140 			mutex_unlock(&fep->ptp_clk_mutex);
2141 		}
2142 
2143 		ret = clk_prepare_enable(fep->clk_ref);
2144 		if (ret)
2145 			goto failed_clk_ref;
2146 
2147 		ret = clk_prepare_enable(fep->clk_2x_txclk);
2148 		if (ret)
2149 			goto failed_clk_2x_txclk;
2150 
2151 		fec_enet_phy_reset_after_clk_enable(ndev);
2152 	} else {
2153 		clk_disable_unprepare(fep->clk_enet_out);
2154 		if (fep->clk_ptp) {
2155 			mutex_lock(&fep->ptp_clk_mutex);
2156 			clk_disable_unprepare(fep->clk_ptp);
2157 			fep->ptp_clk_on = false;
2158 			mutex_unlock(&fep->ptp_clk_mutex);
2159 		}
2160 		clk_disable_unprepare(fep->clk_ref);
2161 		clk_disable_unprepare(fep->clk_2x_txclk);
2162 	}
2163 
2164 	return 0;
2165 
2166 failed_clk_2x_txclk:
2167 	if (fep->clk_ref)
2168 		clk_disable_unprepare(fep->clk_ref);
2169 failed_clk_ref:
2170 	if (fep->clk_ptp) {
2171 		mutex_lock(&fep->ptp_clk_mutex);
2172 		clk_disable_unprepare(fep->clk_ptp);
2173 		fep->ptp_clk_on = false;
2174 		mutex_unlock(&fep->ptp_clk_mutex);
2175 	}
2176 failed_clk_ptp:
2177 	clk_disable_unprepare(fep->clk_enet_out);
2178 
2179 	return ret;
2180 }
2181 
2182 static int fec_enet_parse_rgmii_delay(struct fec_enet_private *fep,
2183 				      struct device_node *np)
2184 {
2185 	u32 rgmii_tx_delay, rgmii_rx_delay;
2186 
2187 	/* For rgmii tx internal delay, valid values are 0ps and 2000ps */
2188 	if (!of_property_read_u32(np, "tx-internal-delay-ps", &rgmii_tx_delay)) {
2189 		if (rgmii_tx_delay != 0 && rgmii_tx_delay != 2000) {
2190 			dev_err(&fep->pdev->dev, "The only allowed RGMII TX delay values are: 0ps, 2000ps");
2191 			return -EINVAL;
2192 		} else if (rgmii_tx_delay == 2000) {
2193 			fep->rgmii_txc_dly = true;
2194 		}
2195 	}
2196 
2197 	/* For rgmii rx internal delay, valid values are 0ps and 2000ps */
2198 	if (!of_property_read_u32(np, "rx-internal-delay-ps", &rgmii_rx_delay)) {
2199 		if (rgmii_rx_delay != 0 && rgmii_rx_delay != 2000) {
2200 			dev_err(&fep->pdev->dev, "The only allowed RGMII RX delay values are: 0ps, 2000ps");
2201 			return -EINVAL;
2202 		} else if (rgmii_rx_delay == 2000) {
2203 			fep->rgmii_rxc_dly = true;
2204 		}
2205 	}
2206 
2207 	return 0;
2208 }
2209 
2210 static int fec_enet_mii_probe(struct net_device *ndev)
2211 {
2212 	struct fec_enet_private *fep = netdev_priv(ndev);
2213 	struct phy_device *phy_dev = NULL;
2214 	char mdio_bus_id[MII_BUS_ID_SIZE];
2215 	char phy_name[MII_BUS_ID_SIZE + 3];
2216 	int phy_id;
2217 	int dev_id = fep->dev_id;
2218 
2219 	if (fep->phy_node) {
2220 		phy_dev = of_phy_connect(ndev, fep->phy_node,
2221 					 &fec_enet_adjust_link, 0,
2222 					 fep->phy_interface);
2223 		if (!phy_dev) {
2224 			netdev_err(ndev, "Unable to connect to phy\n");
2225 			return -ENODEV;
2226 		}
2227 	} else {
2228 		/* check for attached phy */
2229 		for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
2230 			if (!mdiobus_is_registered_device(fep->mii_bus, phy_id))
2231 				continue;
2232 			if (dev_id--)
2233 				continue;
2234 			strscpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
2235 			break;
2236 		}
2237 
2238 		if (phy_id >= PHY_MAX_ADDR) {
2239 			netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
2240 			strscpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
2241 			phy_id = 0;
2242 		}
2243 
2244 		snprintf(phy_name, sizeof(phy_name),
2245 			 PHY_ID_FMT, mdio_bus_id, phy_id);
2246 		phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
2247 				      fep->phy_interface);
2248 	}
2249 
2250 	if (IS_ERR(phy_dev)) {
2251 		netdev_err(ndev, "could not attach to PHY\n");
2252 		return PTR_ERR(phy_dev);
2253 	}
2254 
2255 	/* mask with MAC supported features */
2256 	if (fep->quirks & FEC_QUIRK_HAS_GBIT) {
2257 		phy_set_max_speed(phy_dev, 1000);
2258 		phy_remove_link_mode(phy_dev,
2259 				     ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
2260 #if !defined(CONFIG_M5272)
2261 		phy_support_sym_pause(phy_dev);
2262 #endif
2263 	}
2264 	else
2265 		phy_set_max_speed(phy_dev, 100);
2266 
2267 	fep->link = 0;
2268 	fep->full_duplex = 0;
2269 
2270 	phy_dev->mac_managed_pm = true;
2271 
2272 	phy_attached_info(phy_dev);
2273 
2274 	return 0;
2275 }
2276 
2277 static int fec_enet_mii_init(struct platform_device *pdev)
2278 {
2279 	static struct mii_bus *fec0_mii_bus;
2280 	struct net_device *ndev = platform_get_drvdata(pdev);
2281 	struct fec_enet_private *fep = netdev_priv(ndev);
2282 	bool suppress_preamble = false;
2283 	struct device_node *node;
2284 	int err = -ENXIO;
2285 	u32 mii_speed, holdtime;
2286 	u32 bus_freq;
2287 
2288 	/*
2289 	 * The i.MX28 dual fec interfaces are not equal.
2290 	 * Here are the differences:
2291 	 *
2292 	 *  - fec0 supports MII & RMII modes while fec1 only supports RMII
2293 	 *  - fec0 acts as the 1588 time master while fec1 is slave
2294 	 *  - external phys can only be configured by fec0
2295 	 *
2296 	 * That is to say fec1 can not work independently. It only works
2297 	 * when fec0 is working. The reason behind this design is that the
2298 	 * second interface is added primarily for Switch mode.
2299 	 *
2300 	 * Because of the last point above, both phys are attached on fec0
2301 	 * mdio interface in board design, and need to be configured by
2302 	 * fec0 mii_bus.
2303 	 */
2304 	if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) {
2305 		/* fec1 uses fec0 mii_bus */
2306 		if (mii_cnt && fec0_mii_bus) {
2307 			fep->mii_bus = fec0_mii_bus;
2308 			mii_cnt++;
2309 			return 0;
2310 		}
2311 		return -ENOENT;
2312 	}
2313 
2314 	bus_freq = 2500000; /* 2.5MHz by default */
2315 	node = of_get_child_by_name(pdev->dev.of_node, "mdio");
2316 	if (node) {
2317 		of_property_read_u32(node, "clock-frequency", &bus_freq);
2318 		suppress_preamble = of_property_read_bool(node,
2319 							  "suppress-preamble");
2320 	}
2321 
2322 	/*
2323 	 * Set MII speed (= clk_get_rate() / 2 * phy_speed)
2324 	 *
2325 	 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
2326 	 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'.  The i.MX28
2327 	 * Reference Manual has an error on this, and gets fixed on i.MX6Q
2328 	 * document.
2329 	 */
2330 	mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), bus_freq * 2);
2331 	if (fep->quirks & FEC_QUIRK_ENET_MAC)
2332 		mii_speed--;
2333 	if (mii_speed > 63) {
2334 		dev_err(&pdev->dev,
2335 			"fec clock (%lu) too fast to get right mii speed\n",
2336 			clk_get_rate(fep->clk_ipg));
2337 		err = -EINVAL;
2338 		goto err_out;
2339 	}
2340 
2341 	/*
2342 	 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka
2343 	 * MII_SPEED) register that defines the MDIO output hold time. Earlier
2344 	 * versions are RAZ there, so just ignore the difference and write the
2345 	 * register always.
2346 	 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns.
2347 	 * HOLDTIME + 1 is the number of clk cycles the fec is holding the
2348 	 * output.
2349 	 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive).
2350 	 * Given that ceil(clkrate / 5000000) <= 64, the calculation for
2351 	 * holdtime cannot result in a value greater than 3.
2352 	 */
2353 	holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1;
2354 
2355 	fep->phy_speed = mii_speed << 1 | holdtime << 8;
2356 
2357 	if (suppress_preamble)
2358 		fep->phy_speed |= BIT(7);
2359 
2360 	if (fep->quirks & FEC_QUIRK_CLEAR_SETUP_MII) {
2361 		/* Clear MMFR to avoid to generate MII event by writing MSCR.
2362 		 * MII event generation condition:
2363 		 * - writing MSCR:
2364 		 *	- mmfr[31:0]_not_zero & mscr[7:0]_is_zero &
2365 		 *	  mscr_reg_data_in[7:0] != 0
2366 		 * - writing MMFR:
2367 		 *	- mscr[7:0]_not_zero
2368 		 */
2369 		writel(0, fep->hwp + FEC_MII_DATA);
2370 	}
2371 
2372 	writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
2373 
2374 	/* Clear any pending transaction complete indication */
2375 	writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT);
2376 
2377 	fep->mii_bus = mdiobus_alloc();
2378 	if (fep->mii_bus == NULL) {
2379 		err = -ENOMEM;
2380 		goto err_out;
2381 	}
2382 
2383 	fep->mii_bus->name = "fec_enet_mii_bus";
2384 	fep->mii_bus->read = fec_enet_mdio_read;
2385 	fep->mii_bus->write = fec_enet_mdio_write;
2386 	snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2387 		pdev->name, fep->dev_id + 1);
2388 	fep->mii_bus->priv = fep;
2389 	fep->mii_bus->parent = &pdev->dev;
2390 
2391 	err = of_mdiobus_register(fep->mii_bus, node);
2392 	if (err)
2393 		goto err_out_free_mdiobus;
2394 	of_node_put(node);
2395 
2396 	mii_cnt++;
2397 
2398 	/* save fec0 mii_bus */
2399 	if (fep->quirks & FEC_QUIRK_SINGLE_MDIO)
2400 		fec0_mii_bus = fep->mii_bus;
2401 
2402 	return 0;
2403 
2404 err_out_free_mdiobus:
2405 	mdiobus_free(fep->mii_bus);
2406 err_out:
2407 	of_node_put(node);
2408 	return err;
2409 }
2410 
2411 static void fec_enet_mii_remove(struct fec_enet_private *fep)
2412 {
2413 	if (--mii_cnt == 0) {
2414 		mdiobus_unregister(fep->mii_bus);
2415 		mdiobus_free(fep->mii_bus);
2416 	}
2417 }
2418 
2419 static void fec_enet_get_drvinfo(struct net_device *ndev,
2420 				 struct ethtool_drvinfo *info)
2421 {
2422 	struct fec_enet_private *fep = netdev_priv(ndev);
2423 
2424 	strscpy(info->driver, fep->pdev->dev.driver->name,
2425 		sizeof(info->driver));
2426 	strscpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
2427 }
2428 
2429 static int fec_enet_get_regs_len(struct net_device *ndev)
2430 {
2431 	struct fec_enet_private *fep = netdev_priv(ndev);
2432 	struct resource *r;
2433 	int s = 0;
2434 
2435 	r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0);
2436 	if (r)
2437 		s = resource_size(r);
2438 
2439 	return s;
2440 }
2441 
2442 /* List of registers that can be safety be read to dump them with ethtool */
2443 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
2444 	defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \
2445 	defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST)
2446 static __u32 fec_enet_register_version = 2;
2447 static u32 fec_enet_register_offset[] = {
2448 	FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0,
2449 	FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL,
2450 	FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1,
2451 	FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH,
2452 	FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW,
2453 	FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1,
2454 	FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2,
2455 	FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0,
2456 	FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM,
2457 	FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2,
2458 	FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1,
2459 	FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME,
2460 	RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT,
2461 	RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG,
2462 	RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255,
2463 	RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047,
2464 	RMON_T_P_GTE2048, RMON_T_OCTETS,
2465 	IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF,
2466 	IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE,
2467 	IEEE_T_FDXFC, IEEE_T_OCTETS_OK,
2468 	RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN,
2469 	RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB,
2470 	RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255,
2471 	RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047,
2472 	RMON_R_P_GTE2048, RMON_R_OCTETS,
2473 	IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR,
2474 	IEEE_R_FDXFC, IEEE_R_OCTETS_OK
2475 };
2476 /* for i.MX6ul */
2477 static u32 fec_enet_register_offset_6ul[] = {
2478 	FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0,
2479 	FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL,
2480 	FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_RXIC0,
2481 	FEC_HASH_TABLE_HIGH, FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH,
2482 	FEC_GRP_HASH_TABLE_LOW, FEC_X_WMRK, FEC_R_DES_START_0,
2483 	FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM,
2484 	FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC,
2485 	RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT,
2486 	RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG,
2487 	RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255,
2488 	RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047,
2489 	RMON_T_P_GTE2048, RMON_T_OCTETS,
2490 	IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF,
2491 	IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE,
2492 	IEEE_T_FDXFC, IEEE_T_OCTETS_OK,
2493 	RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN,
2494 	RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB,
2495 	RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255,
2496 	RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047,
2497 	RMON_R_P_GTE2048, RMON_R_OCTETS,
2498 	IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR,
2499 	IEEE_R_FDXFC, IEEE_R_OCTETS_OK
2500 };
2501 #else
2502 static __u32 fec_enet_register_version = 1;
2503 static u32 fec_enet_register_offset[] = {
2504 	FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0,
2505 	FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0,
2506 	FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED,
2507 	FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL,
2508 	FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH,
2509 	FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0,
2510 	FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0,
2511 	FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0,
2512 	FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2
2513 };
2514 #endif
2515 
2516 static void fec_enet_get_regs(struct net_device *ndev,
2517 			      struct ethtool_regs *regs, void *regbuf)
2518 {
2519 	struct fec_enet_private *fep = netdev_priv(ndev);
2520 	u32 __iomem *theregs = (u32 __iomem *)fep->hwp;
2521 	struct device *dev = &fep->pdev->dev;
2522 	u32 *buf = (u32 *)regbuf;
2523 	u32 i, off;
2524 	int ret;
2525 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
2526 	defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \
2527 	defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST)
2528 	u32 *reg_list;
2529 	u32 reg_cnt;
2530 
2531 	if (!of_machine_is_compatible("fsl,imx6ul")) {
2532 		reg_list = fec_enet_register_offset;
2533 		reg_cnt = ARRAY_SIZE(fec_enet_register_offset);
2534 	} else {
2535 		reg_list = fec_enet_register_offset_6ul;
2536 		reg_cnt = ARRAY_SIZE(fec_enet_register_offset_6ul);
2537 	}
2538 #else
2539 	/* coldfire */
2540 	static u32 *reg_list = fec_enet_register_offset;
2541 	static const u32 reg_cnt = ARRAY_SIZE(fec_enet_register_offset);
2542 #endif
2543 	ret = pm_runtime_resume_and_get(dev);
2544 	if (ret < 0)
2545 		return;
2546 
2547 	regs->version = fec_enet_register_version;
2548 
2549 	memset(buf, 0, regs->len);
2550 
2551 	for (i = 0; i < reg_cnt; i++) {
2552 		off = reg_list[i];
2553 
2554 		if ((off == FEC_R_BOUND || off == FEC_R_FSTART) &&
2555 		    !(fep->quirks & FEC_QUIRK_HAS_FRREG))
2556 			continue;
2557 
2558 		off >>= 2;
2559 		buf[off] = readl(&theregs[off]);
2560 	}
2561 
2562 	pm_runtime_mark_last_busy(dev);
2563 	pm_runtime_put_autosuspend(dev);
2564 }
2565 
2566 static int fec_enet_get_ts_info(struct net_device *ndev,
2567 				struct ethtool_ts_info *info)
2568 {
2569 	struct fec_enet_private *fep = netdev_priv(ndev);
2570 
2571 	if (fep->bufdesc_ex) {
2572 
2573 		info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
2574 					SOF_TIMESTAMPING_RX_SOFTWARE |
2575 					SOF_TIMESTAMPING_SOFTWARE |
2576 					SOF_TIMESTAMPING_TX_HARDWARE |
2577 					SOF_TIMESTAMPING_RX_HARDWARE |
2578 					SOF_TIMESTAMPING_RAW_HARDWARE;
2579 		if (fep->ptp_clock)
2580 			info->phc_index = ptp_clock_index(fep->ptp_clock);
2581 		else
2582 			info->phc_index = -1;
2583 
2584 		info->tx_types = (1 << HWTSTAMP_TX_OFF) |
2585 				 (1 << HWTSTAMP_TX_ON);
2586 
2587 		info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
2588 				   (1 << HWTSTAMP_FILTER_ALL);
2589 		return 0;
2590 	} else {
2591 		return ethtool_op_get_ts_info(ndev, info);
2592 	}
2593 }
2594 
2595 #if !defined(CONFIG_M5272)
2596 
2597 static void fec_enet_get_pauseparam(struct net_device *ndev,
2598 				    struct ethtool_pauseparam *pause)
2599 {
2600 	struct fec_enet_private *fep = netdev_priv(ndev);
2601 
2602 	pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
2603 	pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
2604 	pause->rx_pause = pause->tx_pause;
2605 }
2606 
2607 static int fec_enet_set_pauseparam(struct net_device *ndev,
2608 				   struct ethtool_pauseparam *pause)
2609 {
2610 	struct fec_enet_private *fep = netdev_priv(ndev);
2611 
2612 	if (!ndev->phydev)
2613 		return -ENODEV;
2614 
2615 	if (pause->tx_pause != pause->rx_pause) {
2616 		netdev_info(ndev,
2617 			"hardware only support enable/disable both tx and rx");
2618 		return -EINVAL;
2619 	}
2620 
2621 	fep->pause_flag = 0;
2622 
2623 	/* tx pause must be same as rx pause */
2624 	fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
2625 	fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
2626 
2627 	phy_set_sym_pause(ndev->phydev, pause->rx_pause, pause->tx_pause,
2628 			  pause->autoneg);
2629 
2630 	if (pause->autoneg) {
2631 		if (netif_running(ndev))
2632 			fec_stop(ndev);
2633 		phy_start_aneg(ndev->phydev);
2634 	}
2635 	if (netif_running(ndev)) {
2636 		napi_disable(&fep->napi);
2637 		netif_tx_lock_bh(ndev);
2638 		fec_restart(ndev);
2639 		netif_tx_wake_all_queues(ndev);
2640 		netif_tx_unlock_bh(ndev);
2641 		napi_enable(&fep->napi);
2642 	}
2643 
2644 	return 0;
2645 }
2646 
2647 static const struct fec_stat {
2648 	char name[ETH_GSTRING_LEN];
2649 	u16 offset;
2650 } fec_stats[] = {
2651 	/* RMON TX */
2652 	{ "tx_dropped", RMON_T_DROP },
2653 	{ "tx_packets", RMON_T_PACKETS },
2654 	{ "tx_broadcast", RMON_T_BC_PKT },
2655 	{ "tx_multicast", RMON_T_MC_PKT },
2656 	{ "tx_crc_errors", RMON_T_CRC_ALIGN },
2657 	{ "tx_undersize", RMON_T_UNDERSIZE },
2658 	{ "tx_oversize", RMON_T_OVERSIZE },
2659 	{ "tx_fragment", RMON_T_FRAG },
2660 	{ "tx_jabber", RMON_T_JAB },
2661 	{ "tx_collision", RMON_T_COL },
2662 	{ "tx_64byte", RMON_T_P64 },
2663 	{ "tx_65to127byte", RMON_T_P65TO127 },
2664 	{ "tx_128to255byte", RMON_T_P128TO255 },
2665 	{ "tx_256to511byte", RMON_T_P256TO511 },
2666 	{ "tx_512to1023byte", RMON_T_P512TO1023 },
2667 	{ "tx_1024to2047byte", RMON_T_P1024TO2047 },
2668 	{ "tx_GTE2048byte", RMON_T_P_GTE2048 },
2669 	{ "tx_octets", RMON_T_OCTETS },
2670 
2671 	/* IEEE TX */
2672 	{ "IEEE_tx_drop", IEEE_T_DROP },
2673 	{ "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
2674 	{ "IEEE_tx_1col", IEEE_T_1COL },
2675 	{ "IEEE_tx_mcol", IEEE_T_MCOL },
2676 	{ "IEEE_tx_def", IEEE_T_DEF },
2677 	{ "IEEE_tx_lcol", IEEE_T_LCOL },
2678 	{ "IEEE_tx_excol", IEEE_T_EXCOL },
2679 	{ "IEEE_tx_macerr", IEEE_T_MACERR },
2680 	{ "IEEE_tx_cserr", IEEE_T_CSERR },
2681 	{ "IEEE_tx_sqe", IEEE_T_SQE },
2682 	{ "IEEE_tx_fdxfc", IEEE_T_FDXFC },
2683 	{ "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
2684 
2685 	/* RMON RX */
2686 	{ "rx_packets", RMON_R_PACKETS },
2687 	{ "rx_broadcast", RMON_R_BC_PKT },
2688 	{ "rx_multicast", RMON_R_MC_PKT },
2689 	{ "rx_crc_errors", RMON_R_CRC_ALIGN },
2690 	{ "rx_undersize", RMON_R_UNDERSIZE },
2691 	{ "rx_oversize", RMON_R_OVERSIZE },
2692 	{ "rx_fragment", RMON_R_FRAG },
2693 	{ "rx_jabber", RMON_R_JAB },
2694 	{ "rx_64byte", RMON_R_P64 },
2695 	{ "rx_65to127byte", RMON_R_P65TO127 },
2696 	{ "rx_128to255byte", RMON_R_P128TO255 },
2697 	{ "rx_256to511byte", RMON_R_P256TO511 },
2698 	{ "rx_512to1023byte", RMON_R_P512TO1023 },
2699 	{ "rx_1024to2047byte", RMON_R_P1024TO2047 },
2700 	{ "rx_GTE2048byte", RMON_R_P_GTE2048 },
2701 	{ "rx_octets", RMON_R_OCTETS },
2702 
2703 	/* IEEE RX */
2704 	{ "IEEE_rx_drop", IEEE_R_DROP },
2705 	{ "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
2706 	{ "IEEE_rx_crc", IEEE_R_CRC },
2707 	{ "IEEE_rx_align", IEEE_R_ALIGN },
2708 	{ "IEEE_rx_macerr", IEEE_R_MACERR },
2709 	{ "IEEE_rx_fdxfc", IEEE_R_FDXFC },
2710 	{ "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
2711 };
2712 
2713 #define FEC_STATS_SIZE		(ARRAY_SIZE(fec_stats) * sizeof(u64))
2714 
2715 static const char *fec_xdp_stat_strs[XDP_STATS_TOTAL] = {
2716 	"rx_xdp_redirect",           /* RX_XDP_REDIRECT = 0, */
2717 	"rx_xdp_pass",               /* RX_XDP_PASS, */
2718 	"rx_xdp_drop",               /* RX_XDP_DROP, */
2719 	"rx_xdp_tx",                 /* RX_XDP_TX, */
2720 	"rx_xdp_tx_errors",          /* RX_XDP_TX_ERRORS, */
2721 	"tx_xdp_xmit",               /* TX_XDP_XMIT, */
2722 	"tx_xdp_xmit_errors",        /* TX_XDP_XMIT_ERRORS, */
2723 };
2724 
2725 static void fec_enet_update_ethtool_stats(struct net_device *dev)
2726 {
2727 	struct fec_enet_private *fep = netdev_priv(dev);
2728 	int i;
2729 
2730 	for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2731 		fep->ethtool_stats[i] = readl(fep->hwp + fec_stats[i].offset);
2732 }
2733 
2734 static void fec_enet_get_xdp_stats(struct fec_enet_private *fep, u64 *data)
2735 {
2736 	u64 xdp_stats[XDP_STATS_TOTAL] = { 0 };
2737 	struct fec_enet_priv_rx_q *rxq;
2738 	int i, j;
2739 
2740 	for (i = fep->num_rx_queues - 1; i >= 0; i--) {
2741 		rxq = fep->rx_queue[i];
2742 
2743 		for (j = 0; j < XDP_STATS_TOTAL; j++)
2744 			xdp_stats[j] += rxq->stats[j];
2745 	}
2746 
2747 	memcpy(data, xdp_stats, sizeof(xdp_stats));
2748 }
2749 
2750 static void fec_enet_page_pool_stats(struct fec_enet_private *fep, u64 *data)
2751 {
2752 	struct page_pool_stats stats = {};
2753 	struct fec_enet_priv_rx_q *rxq;
2754 	int i;
2755 
2756 	for (i = fep->num_rx_queues - 1; i >= 0; i--) {
2757 		rxq = fep->rx_queue[i];
2758 
2759 		if (!rxq->page_pool)
2760 			continue;
2761 
2762 		page_pool_get_stats(rxq->page_pool, &stats);
2763 	}
2764 
2765 	page_pool_ethtool_stats_get(data, &stats);
2766 }
2767 
2768 static void fec_enet_get_ethtool_stats(struct net_device *dev,
2769 				       struct ethtool_stats *stats, u64 *data)
2770 {
2771 	struct fec_enet_private *fep = netdev_priv(dev);
2772 
2773 	if (netif_running(dev))
2774 		fec_enet_update_ethtool_stats(dev);
2775 
2776 	memcpy(data, fep->ethtool_stats, FEC_STATS_SIZE);
2777 	data += FEC_STATS_SIZE / sizeof(u64);
2778 
2779 	fec_enet_get_xdp_stats(fep, data);
2780 	data += XDP_STATS_TOTAL;
2781 
2782 	fec_enet_page_pool_stats(fep, data);
2783 }
2784 
2785 static void fec_enet_get_strings(struct net_device *netdev,
2786 	u32 stringset, u8 *data)
2787 {
2788 	int i;
2789 	switch (stringset) {
2790 	case ETH_SS_STATS:
2791 		for (i = 0; i < ARRAY_SIZE(fec_stats); i++) {
2792 			memcpy(data, fec_stats[i].name, ETH_GSTRING_LEN);
2793 			data += ETH_GSTRING_LEN;
2794 		}
2795 		for (i = 0; i < ARRAY_SIZE(fec_xdp_stat_strs); i++) {
2796 			strncpy(data, fec_xdp_stat_strs[i], ETH_GSTRING_LEN);
2797 			data += ETH_GSTRING_LEN;
2798 		}
2799 		page_pool_ethtool_stats_get_strings(data);
2800 
2801 		break;
2802 	case ETH_SS_TEST:
2803 		net_selftest_get_strings(data);
2804 		break;
2805 	}
2806 }
2807 
2808 static int fec_enet_get_sset_count(struct net_device *dev, int sset)
2809 {
2810 	int count;
2811 
2812 	switch (sset) {
2813 	case ETH_SS_STATS:
2814 		count = ARRAY_SIZE(fec_stats) + XDP_STATS_TOTAL;
2815 		count += page_pool_ethtool_stats_get_count();
2816 		return count;
2817 
2818 	case ETH_SS_TEST:
2819 		return net_selftest_get_count();
2820 	default:
2821 		return -EOPNOTSUPP;
2822 	}
2823 }
2824 
2825 static void fec_enet_clear_ethtool_stats(struct net_device *dev)
2826 {
2827 	struct fec_enet_private *fep = netdev_priv(dev);
2828 	struct fec_enet_priv_rx_q *rxq;
2829 	int i, j;
2830 
2831 	/* Disable MIB statistics counters */
2832 	writel(FEC_MIB_CTRLSTAT_DISABLE, fep->hwp + FEC_MIB_CTRLSTAT);
2833 
2834 	for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2835 		writel(0, fep->hwp + fec_stats[i].offset);
2836 
2837 	for (i = fep->num_rx_queues - 1; i >= 0; i--) {
2838 		rxq = fep->rx_queue[i];
2839 		for (j = 0; j < XDP_STATS_TOTAL; j++)
2840 			rxq->stats[j] = 0;
2841 	}
2842 
2843 	/* Don't disable MIB statistics counters */
2844 	writel(0, fep->hwp + FEC_MIB_CTRLSTAT);
2845 }
2846 
2847 #else	/* !defined(CONFIG_M5272) */
2848 #define FEC_STATS_SIZE	0
2849 static inline void fec_enet_update_ethtool_stats(struct net_device *dev)
2850 {
2851 }
2852 
2853 static inline void fec_enet_clear_ethtool_stats(struct net_device *dev)
2854 {
2855 }
2856 #endif /* !defined(CONFIG_M5272) */
2857 
2858 /* ITR clock source is enet system clock (clk_ahb).
2859  * TCTT unit is cycle_ns * 64 cycle
2860  * So, the ICTT value = X us / (cycle_ns * 64)
2861  */
2862 static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us)
2863 {
2864 	struct fec_enet_private *fep = netdev_priv(ndev);
2865 
2866 	return us * (fep->itr_clk_rate / 64000) / 1000;
2867 }
2868 
2869 /* Set threshold for interrupt coalescing */
2870 static void fec_enet_itr_coal_set(struct net_device *ndev)
2871 {
2872 	struct fec_enet_private *fep = netdev_priv(ndev);
2873 	int rx_itr, tx_itr;
2874 
2875 	/* Must be greater than zero to avoid unpredictable behavior */
2876 	if (!fep->rx_time_itr || !fep->rx_pkts_itr ||
2877 	    !fep->tx_time_itr || !fep->tx_pkts_itr)
2878 		return;
2879 
2880 	/* Select enet system clock as Interrupt Coalescing
2881 	 * timer Clock Source
2882 	 */
2883 	rx_itr = FEC_ITR_CLK_SEL;
2884 	tx_itr = FEC_ITR_CLK_SEL;
2885 
2886 	/* set ICFT and ICTT */
2887 	rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr);
2888 	rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr));
2889 	tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr);
2890 	tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr));
2891 
2892 	rx_itr |= FEC_ITR_EN;
2893 	tx_itr |= FEC_ITR_EN;
2894 
2895 	writel(tx_itr, fep->hwp + FEC_TXIC0);
2896 	writel(rx_itr, fep->hwp + FEC_RXIC0);
2897 	if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) {
2898 		writel(tx_itr, fep->hwp + FEC_TXIC1);
2899 		writel(rx_itr, fep->hwp + FEC_RXIC1);
2900 		writel(tx_itr, fep->hwp + FEC_TXIC2);
2901 		writel(rx_itr, fep->hwp + FEC_RXIC2);
2902 	}
2903 }
2904 
2905 static int fec_enet_get_coalesce(struct net_device *ndev,
2906 				 struct ethtool_coalesce *ec,
2907 				 struct kernel_ethtool_coalesce *kernel_coal,
2908 				 struct netlink_ext_ack *extack)
2909 {
2910 	struct fec_enet_private *fep = netdev_priv(ndev);
2911 
2912 	if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE))
2913 		return -EOPNOTSUPP;
2914 
2915 	ec->rx_coalesce_usecs = fep->rx_time_itr;
2916 	ec->rx_max_coalesced_frames = fep->rx_pkts_itr;
2917 
2918 	ec->tx_coalesce_usecs = fep->tx_time_itr;
2919 	ec->tx_max_coalesced_frames = fep->tx_pkts_itr;
2920 
2921 	return 0;
2922 }
2923 
2924 static int fec_enet_set_coalesce(struct net_device *ndev,
2925 				 struct ethtool_coalesce *ec,
2926 				 struct kernel_ethtool_coalesce *kernel_coal,
2927 				 struct netlink_ext_ack *extack)
2928 {
2929 	struct fec_enet_private *fep = netdev_priv(ndev);
2930 	struct device *dev = &fep->pdev->dev;
2931 	unsigned int cycle;
2932 
2933 	if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE))
2934 		return -EOPNOTSUPP;
2935 
2936 	if (ec->rx_max_coalesced_frames > 255) {
2937 		dev_err(dev, "Rx coalesced frames exceed hardware limitation\n");
2938 		return -EINVAL;
2939 	}
2940 
2941 	if (ec->tx_max_coalesced_frames > 255) {
2942 		dev_err(dev, "Tx coalesced frame exceed hardware limitation\n");
2943 		return -EINVAL;
2944 	}
2945 
2946 	cycle = fec_enet_us_to_itr_clock(ndev, ec->rx_coalesce_usecs);
2947 	if (cycle > 0xFFFF) {
2948 		dev_err(dev, "Rx coalesced usec exceed hardware limitation\n");
2949 		return -EINVAL;
2950 	}
2951 
2952 	cycle = fec_enet_us_to_itr_clock(ndev, ec->tx_coalesce_usecs);
2953 	if (cycle > 0xFFFF) {
2954 		dev_err(dev, "Tx coalesced usec exceed hardware limitation\n");
2955 		return -EINVAL;
2956 	}
2957 
2958 	fep->rx_time_itr = ec->rx_coalesce_usecs;
2959 	fep->rx_pkts_itr = ec->rx_max_coalesced_frames;
2960 
2961 	fep->tx_time_itr = ec->tx_coalesce_usecs;
2962 	fep->tx_pkts_itr = ec->tx_max_coalesced_frames;
2963 
2964 	fec_enet_itr_coal_set(ndev);
2965 
2966 	return 0;
2967 }
2968 
2969 static int fec_enet_get_tunable(struct net_device *netdev,
2970 				const struct ethtool_tunable *tuna,
2971 				void *data)
2972 {
2973 	struct fec_enet_private *fep = netdev_priv(netdev);
2974 	int ret = 0;
2975 
2976 	switch (tuna->id) {
2977 	case ETHTOOL_RX_COPYBREAK:
2978 		*(u32 *)data = fep->rx_copybreak;
2979 		break;
2980 	default:
2981 		ret = -EINVAL;
2982 		break;
2983 	}
2984 
2985 	return ret;
2986 }
2987 
2988 static int fec_enet_set_tunable(struct net_device *netdev,
2989 				const struct ethtool_tunable *tuna,
2990 				const void *data)
2991 {
2992 	struct fec_enet_private *fep = netdev_priv(netdev);
2993 	int ret = 0;
2994 
2995 	switch (tuna->id) {
2996 	case ETHTOOL_RX_COPYBREAK:
2997 		fep->rx_copybreak = *(u32 *)data;
2998 		break;
2999 	default:
3000 		ret = -EINVAL;
3001 		break;
3002 	}
3003 
3004 	return ret;
3005 }
3006 
3007 /* LPI Sleep Ts count base on tx clk (clk_ref).
3008  * The lpi sleep cnt value = X us / (cycle_ns).
3009  */
3010 static int fec_enet_us_to_tx_cycle(struct net_device *ndev, int us)
3011 {
3012 	struct fec_enet_private *fep = netdev_priv(ndev);
3013 
3014 	return us * (fep->clk_ref_rate / 1000) / 1000;
3015 }
3016 
3017 static int fec_enet_eee_mode_set(struct net_device *ndev, bool enable)
3018 {
3019 	struct fec_enet_private *fep = netdev_priv(ndev);
3020 	struct ethtool_eee *p = &fep->eee;
3021 	unsigned int sleep_cycle, wake_cycle;
3022 	int ret = 0;
3023 
3024 	if (enable) {
3025 		ret = phy_init_eee(ndev->phydev, false);
3026 		if (ret)
3027 			return ret;
3028 
3029 		sleep_cycle = fec_enet_us_to_tx_cycle(ndev, p->tx_lpi_timer);
3030 		wake_cycle = sleep_cycle;
3031 	} else {
3032 		sleep_cycle = 0;
3033 		wake_cycle = 0;
3034 	}
3035 
3036 	p->tx_lpi_enabled = enable;
3037 	p->eee_enabled = enable;
3038 	p->eee_active = enable;
3039 
3040 	writel(sleep_cycle, fep->hwp + FEC_LPI_SLEEP);
3041 	writel(wake_cycle, fep->hwp + FEC_LPI_WAKE);
3042 
3043 	return 0;
3044 }
3045 
3046 static int
3047 fec_enet_get_eee(struct net_device *ndev, struct ethtool_eee *edata)
3048 {
3049 	struct fec_enet_private *fep = netdev_priv(ndev);
3050 	struct ethtool_eee *p = &fep->eee;
3051 
3052 	if (!(fep->quirks & FEC_QUIRK_HAS_EEE))
3053 		return -EOPNOTSUPP;
3054 
3055 	if (!netif_running(ndev))
3056 		return -ENETDOWN;
3057 
3058 	edata->eee_enabled = p->eee_enabled;
3059 	edata->eee_active = p->eee_active;
3060 	edata->tx_lpi_timer = p->tx_lpi_timer;
3061 	edata->tx_lpi_enabled = p->tx_lpi_enabled;
3062 
3063 	return phy_ethtool_get_eee(ndev->phydev, edata);
3064 }
3065 
3066 static int
3067 fec_enet_set_eee(struct net_device *ndev, struct ethtool_eee *edata)
3068 {
3069 	struct fec_enet_private *fep = netdev_priv(ndev);
3070 	struct ethtool_eee *p = &fep->eee;
3071 	int ret = 0;
3072 
3073 	if (!(fep->quirks & FEC_QUIRK_HAS_EEE))
3074 		return -EOPNOTSUPP;
3075 
3076 	if (!netif_running(ndev))
3077 		return -ENETDOWN;
3078 
3079 	p->tx_lpi_timer = edata->tx_lpi_timer;
3080 
3081 	if (!edata->eee_enabled || !edata->tx_lpi_enabled ||
3082 	    !edata->tx_lpi_timer)
3083 		ret = fec_enet_eee_mode_set(ndev, false);
3084 	else
3085 		ret = fec_enet_eee_mode_set(ndev, true);
3086 
3087 	if (ret)
3088 		return ret;
3089 
3090 	return phy_ethtool_set_eee(ndev->phydev, edata);
3091 }
3092 
3093 static void
3094 fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
3095 {
3096 	struct fec_enet_private *fep = netdev_priv(ndev);
3097 
3098 	if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) {
3099 		wol->supported = WAKE_MAGIC;
3100 		wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0;
3101 	} else {
3102 		wol->supported = wol->wolopts = 0;
3103 	}
3104 }
3105 
3106 static int
3107 fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
3108 {
3109 	struct fec_enet_private *fep = netdev_priv(ndev);
3110 
3111 	if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET))
3112 		return -EINVAL;
3113 
3114 	if (wol->wolopts & ~WAKE_MAGIC)
3115 		return -EINVAL;
3116 
3117 	device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC);
3118 	if (device_may_wakeup(&ndev->dev))
3119 		fep->wol_flag |= FEC_WOL_FLAG_ENABLE;
3120 	else
3121 		fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE);
3122 
3123 	return 0;
3124 }
3125 
3126 static const struct ethtool_ops fec_enet_ethtool_ops = {
3127 	.supported_coalesce_params = ETHTOOL_COALESCE_USECS |
3128 				     ETHTOOL_COALESCE_MAX_FRAMES,
3129 	.get_drvinfo		= fec_enet_get_drvinfo,
3130 	.get_regs_len		= fec_enet_get_regs_len,
3131 	.get_regs		= fec_enet_get_regs,
3132 	.nway_reset		= phy_ethtool_nway_reset,
3133 	.get_link		= ethtool_op_get_link,
3134 	.get_coalesce		= fec_enet_get_coalesce,
3135 	.set_coalesce		= fec_enet_set_coalesce,
3136 #ifndef CONFIG_M5272
3137 	.get_pauseparam		= fec_enet_get_pauseparam,
3138 	.set_pauseparam		= fec_enet_set_pauseparam,
3139 	.get_strings		= fec_enet_get_strings,
3140 	.get_ethtool_stats	= fec_enet_get_ethtool_stats,
3141 	.get_sset_count		= fec_enet_get_sset_count,
3142 #endif
3143 	.get_ts_info		= fec_enet_get_ts_info,
3144 	.get_tunable		= fec_enet_get_tunable,
3145 	.set_tunable		= fec_enet_set_tunable,
3146 	.get_wol		= fec_enet_get_wol,
3147 	.set_wol		= fec_enet_set_wol,
3148 	.get_eee		= fec_enet_get_eee,
3149 	.set_eee		= fec_enet_set_eee,
3150 	.get_link_ksettings	= phy_ethtool_get_link_ksettings,
3151 	.set_link_ksettings	= phy_ethtool_set_link_ksettings,
3152 	.self_test		= net_selftest,
3153 };
3154 
3155 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
3156 {
3157 	struct fec_enet_private *fep = netdev_priv(ndev);
3158 	struct phy_device *phydev = ndev->phydev;
3159 
3160 	if (!netif_running(ndev))
3161 		return -EINVAL;
3162 
3163 	if (!phydev)
3164 		return -ENODEV;
3165 
3166 	if (fep->bufdesc_ex) {
3167 		bool use_fec_hwts = !phy_has_hwtstamp(phydev);
3168 
3169 		if (cmd == SIOCSHWTSTAMP) {
3170 			if (use_fec_hwts)
3171 				return fec_ptp_set(ndev, rq);
3172 			fec_ptp_disable_hwts(ndev);
3173 		} else if (cmd == SIOCGHWTSTAMP) {
3174 			if (use_fec_hwts)
3175 				return fec_ptp_get(ndev, rq);
3176 		}
3177 	}
3178 
3179 	return phy_mii_ioctl(phydev, rq, cmd);
3180 }
3181 
3182 static void fec_enet_free_buffers(struct net_device *ndev)
3183 {
3184 	struct fec_enet_private *fep = netdev_priv(ndev);
3185 	unsigned int i;
3186 	struct sk_buff *skb;
3187 	struct fec_enet_priv_tx_q *txq;
3188 	struct fec_enet_priv_rx_q *rxq;
3189 	unsigned int q;
3190 
3191 	for (q = 0; q < fep->num_rx_queues; q++) {
3192 		rxq = fep->rx_queue[q];
3193 		for (i = 0; i < rxq->bd.ring_size; i++)
3194 			page_pool_release_page(rxq->page_pool, rxq->rx_skb_info[i].page);
3195 
3196 		for (i = 0; i < XDP_STATS_TOTAL; i++)
3197 			rxq->stats[i] = 0;
3198 
3199 		if (xdp_rxq_info_is_reg(&rxq->xdp_rxq))
3200 			xdp_rxq_info_unreg(&rxq->xdp_rxq);
3201 		page_pool_destroy(rxq->page_pool);
3202 		rxq->page_pool = NULL;
3203 	}
3204 
3205 	for (q = 0; q < fep->num_tx_queues; q++) {
3206 		txq = fep->tx_queue[q];
3207 		for (i = 0; i < txq->bd.ring_size; i++) {
3208 			kfree(txq->tx_bounce[i]);
3209 			txq->tx_bounce[i] = NULL;
3210 			skb = txq->tx_skbuff[i];
3211 			txq->tx_skbuff[i] = NULL;
3212 			dev_kfree_skb(skb);
3213 		}
3214 	}
3215 }
3216 
3217 static void fec_enet_free_queue(struct net_device *ndev)
3218 {
3219 	struct fec_enet_private *fep = netdev_priv(ndev);
3220 	int i;
3221 	struct fec_enet_priv_tx_q *txq;
3222 
3223 	for (i = 0; i < fep->num_tx_queues; i++)
3224 		if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) {
3225 			txq = fep->tx_queue[i];
3226 			dma_free_coherent(&fep->pdev->dev,
3227 					  txq->bd.ring_size * TSO_HEADER_SIZE,
3228 					  txq->tso_hdrs,
3229 					  txq->tso_hdrs_dma);
3230 		}
3231 
3232 	for (i = 0; i < fep->num_rx_queues; i++)
3233 		kfree(fep->rx_queue[i]);
3234 	for (i = 0; i < fep->num_tx_queues; i++)
3235 		kfree(fep->tx_queue[i]);
3236 }
3237 
3238 static int fec_enet_alloc_queue(struct net_device *ndev)
3239 {
3240 	struct fec_enet_private *fep = netdev_priv(ndev);
3241 	int i;
3242 	int ret = 0;
3243 	struct fec_enet_priv_tx_q *txq;
3244 
3245 	for (i = 0; i < fep->num_tx_queues; i++) {
3246 		txq = kzalloc(sizeof(*txq), GFP_KERNEL);
3247 		if (!txq) {
3248 			ret = -ENOMEM;
3249 			goto alloc_failed;
3250 		}
3251 
3252 		fep->tx_queue[i] = txq;
3253 		txq->bd.ring_size = TX_RING_SIZE;
3254 		fep->total_tx_ring_size += fep->tx_queue[i]->bd.ring_size;
3255 
3256 		txq->tx_stop_threshold = FEC_MAX_SKB_DESCS;
3257 		txq->tx_wake_threshold =
3258 			(txq->bd.ring_size - txq->tx_stop_threshold) / 2;
3259 
3260 		txq->tso_hdrs = dma_alloc_coherent(&fep->pdev->dev,
3261 					txq->bd.ring_size * TSO_HEADER_SIZE,
3262 					&txq->tso_hdrs_dma,
3263 					GFP_KERNEL);
3264 		if (!txq->tso_hdrs) {
3265 			ret = -ENOMEM;
3266 			goto alloc_failed;
3267 		}
3268 	}
3269 
3270 	for (i = 0; i < fep->num_rx_queues; i++) {
3271 		fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]),
3272 					   GFP_KERNEL);
3273 		if (!fep->rx_queue[i]) {
3274 			ret = -ENOMEM;
3275 			goto alloc_failed;
3276 		}
3277 
3278 		fep->rx_queue[i]->bd.ring_size = RX_RING_SIZE;
3279 		fep->total_rx_ring_size += fep->rx_queue[i]->bd.ring_size;
3280 	}
3281 	return ret;
3282 
3283 alloc_failed:
3284 	fec_enet_free_queue(ndev);
3285 	return ret;
3286 }
3287 
3288 static int
3289 fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue)
3290 {
3291 	struct fec_enet_private *fep = netdev_priv(ndev);
3292 	struct fec_enet_priv_rx_q *rxq;
3293 	dma_addr_t phys_addr;
3294 	struct bufdesc	*bdp;
3295 	struct page *page;
3296 	int i, err;
3297 
3298 	rxq = fep->rx_queue[queue];
3299 	bdp = rxq->bd.base;
3300 
3301 	err = fec_enet_create_page_pool(fep, rxq, rxq->bd.ring_size);
3302 	if (err < 0) {
3303 		netdev_err(ndev, "%s failed queue %d (%d)\n", __func__, queue, err);
3304 		return err;
3305 	}
3306 
3307 	for (i = 0; i < rxq->bd.ring_size; i++) {
3308 		page = page_pool_dev_alloc_pages(rxq->page_pool);
3309 		if (!page)
3310 			goto err_alloc;
3311 
3312 		phys_addr = page_pool_get_dma_addr(page) + FEC_ENET_XDP_HEADROOM;
3313 		bdp->cbd_bufaddr = cpu_to_fec32(phys_addr);
3314 
3315 		rxq->rx_skb_info[i].page = page;
3316 		rxq->rx_skb_info[i].offset = FEC_ENET_XDP_HEADROOM;
3317 		bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY);
3318 
3319 		if (fep->bufdesc_ex) {
3320 			struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
3321 			ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT);
3322 		}
3323 
3324 		bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
3325 	}
3326 
3327 	/* Set the last buffer to wrap. */
3328 	bdp = fec_enet_get_prevdesc(bdp, &rxq->bd);
3329 	bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
3330 	return 0;
3331 
3332  err_alloc:
3333 	fec_enet_free_buffers(ndev);
3334 	return -ENOMEM;
3335 }
3336 
3337 static int
3338 fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue)
3339 {
3340 	struct fec_enet_private *fep = netdev_priv(ndev);
3341 	unsigned int i;
3342 	struct bufdesc  *bdp;
3343 	struct fec_enet_priv_tx_q *txq;
3344 
3345 	txq = fep->tx_queue[queue];
3346 	bdp = txq->bd.base;
3347 	for (i = 0; i < txq->bd.ring_size; i++) {
3348 		txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
3349 		if (!txq->tx_bounce[i])
3350 			goto err_alloc;
3351 
3352 		bdp->cbd_sc = cpu_to_fec16(0);
3353 		bdp->cbd_bufaddr = cpu_to_fec32(0);
3354 
3355 		if (fep->bufdesc_ex) {
3356 			struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
3357 			ebdp->cbd_esc = cpu_to_fec32(BD_ENET_TX_INT);
3358 		}
3359 
3360 		bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
3361 	}
3362 
3363 	/* Set the last buffer to wrap. */
3364 	bdp = fec_enet_get_prevdesc(bdp, &txq->bd);
3365 	bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
3366 
3367 	return 0;
3368 
3369  err_alloc:
3370 	fec_enet_free_buffers(ndev);
3371 	return -ENOMEM;
3372 }
3373 
3374 static int fec_enet_alloc_buffers(struct net_device *ndev)
3375 {
3376 	struct fec_enet_private *fep = netdev_priv(ndev);
3377 	unsigned int i;
3378 
3379 	for (i = 0; i < fep->num_rx_queues; i++)
3380 		if (fec_enet_alloc_rxq_buffers(ndev, i))
3381 			return -ENOMEM;
3382 
3383 	for (i = 0; i < fep->num_tx_queues; i++)
3384 		if (fec_enet_alloc_txq_buffers(ndev, i))
3385 			return -ENOMEM;
3386 	return 0;
3387 }
3388 
3389 static int
3390 fec_enet_open(struct net_device *ndev)
3391 {
3392 	struct fec_enet_private *fep = netdev_priv(ndev);
3393 	int ret;
3394 	bool reset_again;
3395 
3396 	ret = pm_runtime_resume_and_get(&fep->pdev->dev);
3397 	if (ret < 0)
3398 		return ret;
3399 
3400 	pinctrl_pm_select_default_state(&fep->pdev->dev);
3401 	ret = fec_enet_clk_enable(ndev, true);
3402 	if (ret)
3403 		goto clk_enable;
3404 
3405 	/* During the first fec_enet_open call the PHY isn't probed at this
3406 	 * point. Therefore the phy_reset_after_clk_enable() call within
3407 	 * fec_enet_clk_enable() fails. As we need this reset in order to be
3408 	 * sure the PHY is working correctly we check if we need to reset again
3409 	 * later when the PHY is probed
3410 	 */
3411 	if (ndev->phydev && ndev->phydev->drv)
3412 		reset_again = false;
3413 	else
3414 		reset_again = true;
3415 
3416 	/* I should reset the ring buffers here, but I don't yet know
3417 	 * a simple way to do that.
3418 	 */
3419 
3420 	ret = fec_enet_alloc_buffers(ndev);
3421 	if (ret)
3422 		goto err_enet_alloc;
3423 
3424 	/* Init MAC prior to mii bus probe */
3425 	fec_restart(ndev);
3426 
3427 	/* Call phy_reset_after_clk_enable() again if it failed during
3428 	 * phy_reset_after_clk_enable() before because the PHY wasn't probed.
3429 	 */
3430 	if (reset_again)
3431 		fec_enet_phy_reset_after_clk_enable(ndev);
3432 
3433 	/* Probe and connect to PHY when open the interface */
3434 	ret = fec_enet_mii_probe(ndev);
3435 	if (ret)
3436 		goto err_enet_mii_probe;
3437 
3438 	if (fep->quirks & FEC_QUIRK_ERR006687)
3439 		imx6q_cpuidle_fec_irqs_used();
3440 
3441 	if (fep->quirks & FEC_QUIRK_HAS_PMQOS)
3442 		cpu_latency_qos_add_request(&fep->pm_qos_req, 0);
3443 
3444 	napi_enable(&fep->napi);
3445 	phy_start(ndev->phydev);
3446 	netif_tx_start_all_queues(ndev);
3447 
3448 	device_set_wakeup_enable(&ndev->dev, fep->wol_flag &
3449 				 FEC_WOL_FLAG_ENABLE);
3450 
3451 	return 0;
3452 
3453 err_enet_mii_probe:
3454 	fec_enet_free_buffers(ndev);
3455 err_enet_alloc:
3456 	fec_enet_clk_enable(ndev, false);
3457 clk_enable:
3458 	pm_runtime_mark_last_busy(&fep->pdev->dev);
3459 	pm_runtime_put_autosuspend(&fep->pdev->dev);
3460 	pinctrl_pm_select_sleep_state(&fep->pdev->dev);
3461 	return ret;
3462 }
3463 
3464 static int
3465 fec_enet_close(struct net_device *ndev)
3466 {
3467 	struct fec_enet_private *fep = netdev_priv(ndev);
3468 
3469 	phy_stop(ndev->phydev);
3470 
3471 	if (netif_device_present(ndev)) {
3472 		napi_disable(&fep->napi);
3473 		netif_tx_disable(ndev);
3474 		fec_stop(ndev);
3475 	}
3476 
3477 	phy_disconnect(ndev->phydev);
3478 
3479 	if (fep->quirks & FEC_QUIRK_ERR006687)
3480 		imx6q_cpuidle_fec_irqs_unused();
3481 
3482 	fec_enet_update_ethtool_stats(ndev);
3483 
3484 	fec_enet_clk_enable(ndev, false);
3485 	if (fep->quirks & FEC_QUIRK_HAS_PMQOS)
3486 		cpu_latency_qos_remove_request(&fep->pm_qos_req);
3487 
3488 	pinctrl_pm_select_sleep_state(&fep->pdev->dev);
3489 	pm_runtime_mark_last_busy(&fep->pdev->dev);
3490 	pm_runtime_put_autosuspend(&fep->pdev->dev);
3491 
3492 	fec_enet_free_buffers(ndev);
3493 
3494 	return 0;
3495 }
3496 
3497 /* Set or clear the multicast filter for this adaptor.
3498  * Skeleton taken from sunlance driver.
3499  * The CPM Ethernet implementation allows Multicast as well as individual
3500  * MAC address filtering.  Some of the drivers check to make sure it is
3501  * a group multicast address, and discard those that are not.  I guess I
3502  * will do the same for now, but just remove the test if you want
3503  * individual filtering as well (do the upper net layers want or support
3504  * this kind of feature?).
3505  */
3506 
3507 #define FEC_HASH_BITS	6		/* #bits in hash */
3508 
3509 static void set_multicast_list(struct net_device *ndev)
3510 {
3511 	struct fec_enet_private *fep = netdev_priv(ndev);
3512 	struct netdev_hw_addr *ha;
3513 	unsigned int crc, tmp;
3514 	unsigned char hash;
3515 	unsigned int hash_high = 0, hash_low = 0;
3516 
3517 	if (ndev->flags & IFF_PROMISC) {
3518 		tmp = readl(fep->hwp + FEC_R_CNTRL);
3519 		tmp |= 0x8;
3520 		writel(tmp, fep->hwp + FEC_R_CNTRL);
3521 		return;
3522 	}
3523 
3524 	tmp = readl(fep->hwp + FEC_R_CNTRL);
3525 	tmp &= ~0x8;
3526 	writel(tmp, fep->hwp + FEC_R_CNTRL);
3527 
3528 	if (ndev->flags & IFF_ALLMULTI) {
3529 		/* Catch all multicast addresses, so set the
3530 		 * filter to all 1's
3531 		 */
3532 		writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
3533 		writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
3534 
3535 		return;
3536 	}
3537 
3538 	/* Add the addresses in hash register */
3539 	netdev_for_each_mc_addr(ha, ndev) {
3540 		/* calculate crc32 value of mac address */
3541 		crc = ether_crc_le(ndev->addr_len, ha->addr);
3542 
3543 		/* only upper 6 bits (FEC_HASH_BITS) are used
3544 		 * which point to specific bit in the hash registers
3545 		 */
3546 		hash = (crc >> (32 - FEC_HASH_BITS)) & 0x3f;
3547 
3548 		if (hash > 31)
3549 			hash_high |= 1 << (hash - 32);
3550 		else
3551 			hash_low |= 1 << hash;
3552 	}
3553 
3554 	writel(hash_high, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
3555 	writel(hash_low, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
3556 }
3557 
3558 /* Set a MAC change in hardware. */
3559 static int
3560 fec_set_mac_address(struct net_device *ndev, void *p)
3561 {
3562 	struct fec_enet_private *fep = netdev_priv(ndev);
3563 	struct sockaddr *addr = p;
3564 
3565 	if (addr) {
3566 		if (!is_valid_ether_addr(addr->sa_data))
3567 			return -EADDRNOTAVAIL;
3568 		eth_hw_addr_set(ndev, addr->sa_data);
3569 	}
3570 
3571 	/* Add netif status check here to avoid system hang in below case:
3572 	 * ifconfig ethx down; ifconfig ethx hw ether xx:xx:xx:xx:xx:xx;
3573 	 * After ethx down, fec all clocks are gated off and then register
3574 	 * access causes system hang.
3575 	 */
3576 	if (!netif_running(ndev))
3577 		return 0;
3578 
3579 	writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
3580 		(ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
3581 		fep->hwp + FEC_ADDR_LOW);
3582 	writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
3583 		fep->hwp + FEC_ADDR_HIGH);
3584 	return 0;
3585 }
3586 
3587 #ifdef CONFIG_NET_POLL_CONTROLLER
3588 /**
3589  * fec_poll_controller - FEC Poll controller function
3590  * @dev: The FEC network adapter
3591  *
3592  * Polled functionality used by netconsole and others in non interrupt mode
3593  *
3594  */
3595 static void fec_poll_controller(struct net_device *dev)
3596 {
3597 	int i;
3598 	struct fec_enet_private *fep = netdev_priv(dev);
3599 
3600 	for (i = 0; i < FEC_IRQ_NUM; i++) {
3601 		if (fep->irq[i] > 0) {
3602 			disable_irq(fep->irq[i]);
3603 			fec_enet_interrupt(fep->irq[i], dev);
3604 			enable_irq(fep->irq[i]);
3605 		}
3606 	}
3607 }
3608 #endif
3609 
3610 static inline void fec_enet_set_netdev_features(struct net_device *netdev,
3611 	netdev_features_t features)
3612 {
3613 	struct fec_enet_private *fep = netdev_priv(netdev);
3614 	netdev_features_t changed = features ^ netdev->features;
3615 
3616 	netdev->features = features;
3617 
3618 	/* Receive checksum has been changed */
3619 	if (changed & NETIF_F_RXCSUM) {
3620 		if (features & NETIF_F_RXCSUM)
3621 			fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3622 		else
3623 			fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED;
3624 	}
3625 }
3626 
3627 static int fec_set_features(struct net_device *netdev,
3628 	netdev_features_t features)
3629 {
3630 	struct fec_enet_private *fep = netdev_priv(netdev);
3631 	netdev_features_t changed = features ^ netdev->features;
3632 
3633 	if (netif_running(netdev) && changed & NETIF_F_RXCSUM) {
3634 		napi_disable(&fep->napi);
3635 		netif_tx_lock_bh(netdev);
3636 		fec_stop(netdev);
3637 		fec_enet_set_netdev_features(netdev, features);
3638 		fec_restart(netdev);
3639 		netif_tx_wake_all_queues(netdev);
3640 		netif_tx_unlock_bh(netdev);
3641 		napi_enable(&fep->napi);
3642 	} else {
3643 		fec_enet_set_netdev_features(netdev, features);
3644 	}
3645 
3646 	return 0;
3647 }
3648 
3649 static u16 fec_enet_get_raw_vlan_tci(struct sk_buff *skb)
3650 {
3651 	struct vlan_ethhdr *vhdr;
3652 	unsigned short vlan_TCI = 0;
3653 
3654 	if (skb->protocol == htons(ETH_P_ALL)) {
3655 		vhdr = (struct vlan_ethhdr *)(skb->data);
3656 		vlan_TCI = ntohs(vhdr->h_vlan_TCI);
3657 	}
3658 
3659 	return vlan_TCI;
3660 }
3661 
3662 static u16 fec_enet_select_queue(struct net_device *ndev, struct sk_buff *skb,
3663 				 struct net_device *sb_dev)
3664 {
3665 	struct fec_enet_private *fep = netdev_priv(ndev);
3666 	u16 vlan_tag;
3667 
3668 	if (!(fep->quirks & FEC_QUIRK_HAS_AVB))
3669 		return netdev_pick_tx(ndev, skb, NULL);
3670 
3671 	vlan_tag = fec_enet_get_raw_vlan_tci(skb);
3672 	if (!vlan_tag)
3673 		return vlan_tag;
3674 
3675 	return fec_enet_vlan_pri_to_queue[vlan_tag >> 13];
3676 }
3677 
3678 static int fec_enet_bpf(struct net_device *dev, struct netdev_bpf *bpf)
3679 {
3680 	struct fec_enet_private *fep = netdev_priv(dev);
3681 	bool is_run = netif_running(dev);
3682 	struct bpf_prog *old_prog;
3683 
3684 	switch (bpf->command) {
3685 	case XDP_SETUP_PROG:
3686 		/* No need to support the SoCs that require to
3687 		 * do the frame swap because the performance wouldn't be
3688 		 * better than the skb mode.
3689 		 */
3690 		if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
3691 			return -EOPNOTSUPP;
3692 
3693 		if (is_run) {
3694 			napi_disable(&fep->napi);
3695 			netif_tx_disable(dev);
3696 		}
3697 
3698 		old_prog = xchg(&fep->xdp_prog, bpf->prog);
3699 		fec_restart(dev);
3700 
3701 		if (is_run) {
3702 			napi_enable(&fep->napi);
3703 			netif_tx_start_all_queues(dev);
3704 		}
3705 
3706 		if (old_prog)
3707 			bpf_prog_put(old_prog);
3708 
3709 		return 0;
3710 
3711 	case XDP_SETUP_XSK_POOL:
3712 		return -EOPNOTSUPP;
3713 
3714 	default:
3715 		return -EOPNOTSUPP;
3716 	}
3717 }
3718 
3719 static int
3720 fec_enet_xdp_get_tx_queue(struct fec_enet_private *fep, int index)
3721 {
3722 	if (unlikely(index < 0))
3723 		return 0;
3724 
3725 	return (index % fep->num_tx_queues);
3726 }
3727 
3728 static int fec_enet_txq_xmit_frame(struct fec_enet_private *fep,
3729 				   struct fec_enet_priv_tx_q *txq,
3730 				   struct xdp_frame *frame)
3731 {
3732 	unsigned int index, status, estatus;
3733 	struct bufdesc *bdp, *last_bdp;
3734 	dma_addr_t dma_addr;
3735 	int entries_free;
3736 
3737 	entries_free = fec_enet_get_free_txdesc_num(txq);
3738 	if (entries_free < MAX_SKB_FRAGS + 1) {
3739 		netdev_err(fep->netdev, "NOT enough BD for SG!\n");
3740 		return NETDEV_TX_OK;
3741 	}
3742 
3743 	/* Fill in a Tx ring entry */
3744 	bdp = txq->bd.cur;
3745 	last_bdp = bdp;
3746 	status = fec16_to_cpu(bdp->cbd_sc);
3747 	status &= ~BD_ENET_TX_STATS;
3748 
3749 	index = fec_enet_get_bd_index(bdp, &txq->bd);
3750 
3751 	dma_addr = dma_map_single(&fep->pdev->dev, frame->data,
3752 				  frame->len, DMA_TO_DEVICE);
3753 	if (dma_mapping_error(&fep->pdev->dev, dma_addr))
3754 		return FEC_ENET_XDP_CONSUMED;
3755 
3756 	status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
3757 	if (fep->bufdesc_ex)
3758 		estatus = BD_ENET_TX_INT;
3759 
3760 	bdp->cbd_bufaddr = cpu_to_fec32(dma_addr);
3761 	bdp->cbd_datlen = cpu_to_fec16(frame->len);
3762 
3763 	if (fep->bufdesc_ex) {
3764 		struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
3765 
3766 		if (fep->quirks & FEC_QUIRK_HAS_AVB)
3767 			estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
3768 
3769 		ebdp->cbd_bdu = 0;
3770 		ebdp->cbd_esc = cpu_to_fec32(estatus);
3771 	}
3772 
3773 	index = fec_enet_get_bd_index(last_bdp, &txq->bd);
3774 	txq->tx_skbuff[index] = NULL;
3775 
3776 	/* Send it on its way.  Tell FEC it's ready, interrupt when done,
3777 	 * it's the last BD of the frame, and to put the CRC on the end.
3778 	 */
3779 	status |= (BD_ENET_TX_READY | BD_ENET_TX_TC);
3780 	bdp->cbd_sc = cpu_to_fec16(status);
3781 
3782 	/* If this was the last BD in the ring, start at the beginning again. */
3783 	bdp = fec_enet_get_nextdesc(last_bdp, &txq->bd);
3784 
3785 	txq->bd.cur = bdp;
3786 
3787 	return 0;
3788 }
3789 
3790 static int fec_enet_xdp_xmit(struct net_device *dev,
3791 			     int num_frames,
3792 			     struct xdp_frame **frames,
3793 			     u32 flags)
3794 {
3795 	struct fec_enet_private *fep = netdev_priv(dev);
3796 	struct fec_enet_priv_tx_q *txq;
3797 	int cpu = smp_processor_id();
3798 	struct netdev_queue *nq;
3799 	unsigned int queue;
3800 	int i;
3801 
3802 	queue = fec_enet_xdp_get_tx_queue(fep, cpu);
3803 	txq = fep->tx_queue[queue];
3804 	nq = netdev_get_tx_queue(fep->netdev, queue);
3805 
3806 	__netif_tx_lock(nq, cpu);
3807 
3808 	for (i = 0; i < num_frames; i++)
3809 		fec_enet_txq_xmit_frame(fep, txq, frames[i]);
3810 
3811 	/* Make sure the update to bdp and tx_skbuff are performed. */
3812 	wmb();
3813 
3814 	/* Trigger transmission start */
3815 	writel(0, txq->bd.reg_desc_active);
3816 
3817 	__netif_tx_unlock(nq);
3818 
3819 	return num_frames;
3820 }
3821 
3822 static const struct net_device_ops fec_netdev_ops = {
3823 	.ndo_open		= fec_enet_open,
3824 	.ndo_stop		= fec_enet_close,
3825 	.ndo_start_xmit		= fec_enet_start_xmit,
3826 	.ndo_select_queue       = fec_enet_select_queue,
3827 	.ndo_set_rx_mode	= set_multicast_list,
3828 	.ndo_validate_addr	= eth_validate_addr,
3829 	.ndo_tx_timeout		= fec_timeout,
3830 	.ndo_set_mac_address	= fec_set_mac_address,
3831 	.ndo_eth_ioctl		= fec_enet_ioctl,
3832 #ifdef CONFIG_NET_POLL_CONTROLLER
3833 	.ndo_poll_controller	= fec_poll_controller,
3834 #endif
3835 	.ndo_set_features	= fec_set_features,
3836 	.ndo_bpf		= fec_enet_bpf,
3837 	.ndo_xdp_xmit		= fec_enet_xdp_xmit,
3838 };
3839 
3840 static const unsigned short offset_des_active_rxq[] = {
3841 	FEC_R_DES_ACTIVE_0, FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2
3842 };
3843 
3844 static const unsigned short offset_des_active_txq[] = {
3845 	FEC_X_DES_ACTIVE_0, FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2
3846 };
3847 
3848  /*
3849   * XXX:  We need to clean up on failure exits here.
3850   *
3851   */
3852 static int fec_enet_init(struct net_device *ndev)
3853 {
3854 	struct fec_enet_private *fep = netdev_priv(ndev);
3855 	struct bufdesc *cbd_base;
3856 	dma_addr_t bd_dma;
3857 	int bd_size;
3858 	unsigned int i;
3859 	unsigned dsize = fep->bufdesc_ex ? sizeof(struct bufdesc_ex) :
3860 			sizeof(struct bufdesc);
3861 	unsigned dsize_log2 = __fls(dsize);
3862 	int ret;
3863 
3864 	WARN_ON(dsize != (1 << dsize_log2));
3865 #if defined(CONFIG_ARM) || defined(CONFIG_ARM64)
3866 	fep->rx_align = 0xf;
3867 	fep->tx_align = 0xf;
3868 #else
3869 	fep->rx_align = 0x3;
3870 	fep->tx_align = 0x3;
3871 #endif
3872 	fep->rx_pkts_itr = FEC_ITR_ICFT_DEFAULT;
3873 	fep->tx_pkts_itr = FEC_ITR_ICFT_DEFAULT;
3874 	fep->rx_time_itr = FEC_ITR_ICTT_DEFAULT;
3875 	fep->tx_time_itr = FEC_ITR_ICTT_DEFAULT;
3876 
3877 	/* Check mask of the streaming and coherent API */
3878 	ret = dma_set_mask_and_coherent(&fep->pdev->dev, DMA_BIT_MASK(32));
3879 	if (ret < 0) {
3880 		dev_warn(&fep->pdev->dev, "No suitable DMA available\n");
3881 		return ret;
3882 	}
3883 
3884 	ret = fec_enet_alloc_queue(ndev);
3885 	if (ret)
3886 		return ret;
3887 
3888 	bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) * dsize;
3889 
3890 	/* Allocate memory for buffer descriptors. */
3891 	cbd_base = dmam_alloc_coherent(&fep->pdev->dev, bd_size, &bd_dma,
3892 				       GFP_KERNEL);
3893 	if (!cbd_base) {
3894 		ret = -ENOMEM;
3895 		goto free_queue_mem;
3896 	}
3897 
3898 	/* Get the Ethernet address */
3899 	ret = fec_get_mac(ndev);
3900 	if (ret)
3901 		goto free_queue_mem;
3902 
3903 	/* make sure MAC we just acquired is programmed into the hw */
3904 	fec_set_mac_address(ndev, NULL);
3905 
3906 	/* Set receive and transmit descriptor base. */
3907 	for (i = 0; i < fep->num_rx_queues; i++) {
3908 		struct fec_enet_priv_rx_q *rxq = fep->rx_queue[i];
3909 		unsigned size = dsize * rxq->bd.ring_size;
3910 
3911 		rxq->bd.qid = i;
3912 		rxq->bd.base = cbd_base;
3913 		rxq->bd.cur = cbd_base;
3914 		rxq->bd.dma = bd_dma;
3915 		rxq->bd.dsize = dsize;
3916 		rxq->bd.dsize_log2 = dsize_log2;
3917 		rxq->bd.reg_desc_active = fep->hwp + offset_des_active_rxq[i];
3918 		bd_dma += size;
3919 		cbd_base = (struct bufdesc *)(((void *)cbd_base) + size);
3920 		rxq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize);
3921 	}
3922 
3923 	for (i = 0; i < fep->num_tx_queues; i++) {
3924 		struct fec_enet_priv_tx_q *txq = fep->tx_queue[i];
3925 		unsigned size = dsize * txq->bd.ring_size;
3926 
3927 		txq->bd.qid = i;
3928 		txq->bd.base = cbd_base;
3929 		txq->bd.cur = cbd_base;
3930 		txq->bd.dma = bd_dma;
3931 		txq->bd.dsize = dsize;
3932 		txq->bd.dsize_log2 = dsize_log2;
3933 		txq->bd.reg_desc_active = fep->hwp + offset_des_active_txq[i];
3934 		bd_dma += size;
3935 		cbd_base = (struct bufdesc *)(((void *)cbd_base) + size);
3936 		txq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize);
3937 	}
3938 
3939 
3940 	/* The FEC Ethernet specific entries in the device structure */
3941 	ndev->watchdog_timeo = TX_TIMEOUT;
3942 	ndev->netdev_ops = &fec_netdev_ops;
3943 	ndev->ethtool_ops = &fec_enet_ethtool_ops;
3944 
3945 	writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
3946 	netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi);
3947 
3948 	if (fep->quirks & FEC_QUIRK_HAS_VLAN)
3949 		/* enable hw VLAN support */
3950 		ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
3951 
3952 	if (fep->quirks & FEC_QUIRK_HAS_CSUM) {
3953 		netif_set_tso_max_segs(ndev, FEC_MAX_TSO_SEGS);
3954 
3955 		/* enable hw accelerator */
3956 		ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
3957 				| NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO);
3958 		fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3959 	}
3960 
3961 	if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) {
3962 		fep->tx_align = 0;
3963 		fep->rx_align = 0x3f;
3964 	}
3965 
3966 	ndev->hw_features = ndev->features;
3967 
3968 	fec_restart(ndev);
3969 
3970 	if (fep->quirks & FEC_QUIRK_MIB_CLEAR)
3971 		fec_enet_clear_ethtool_stats(ndev);
3972 	else
3973 		fec_enet_update_ethtool_stats(ndev);
3974 
3975 	return 0;
3976 
3977 free_queue_mem:
3978 	fec_enet_free_queue(ndev);
3979 	return ret;
3980 }
3981 
3982 #ifdef CONFIG_OF
3983 static int fec_reset_phy(struct platform_device *pdev)
3984 {
3985 	int err, phy_reset;
3986 	bool active_high = false;
3987 	int msec = 1, phy_post_delay = 0;
3988 	struct device_node *np = pdev->dev.of_node;
3989 
3990 	if (!np)
3991 		return 0;
3992 
3993 	err = of_property_read_u32(np, "phy-reset-duration", &msec);
3994 	/* A sane reset duration should not be longer than 1s */
3995 	if (!err && msec > 1000)
3996 		msec = 1;
3997 
3998 	phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
3999 	if (phy_reset == -EPROBE_DEFER)
4000 		return phy_reset;
4001 	else if (!gpio_is_valid(phy_reset))
4002 		return 0;
4003 
4004 	err = of_property_read_u32(np, "phy-reset-post-delay", &phy_post_delay);
4005 	/* valid reset duration should be less than 1s */
4006 	if (!err && phy_post_delay > 1000)
4007 		return -EINVAL;
4008 
4009 	active_high = of_property_read_bool(np, "phy-reset-active-high");
4010 
4011 	err = devm_gpio_request_one(&pdev->dev, phy_reset,
4012 			active_high ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW,
4013 			"phy-reset");
4014 	if (err) {
4015 		dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
4016 		return err;
4017 	}
4018 
4019 	if (msec > 20)
4020 		msleep(msec);
4021 	else
4022 		usleep_range(msec * 1000, msec * 1000 + 1000);
4023 
4024 	gpio_set_value_cansleep(phy_reset, !active_high);
4025 
4026 	if (!phy_post_delay)
4027 		return 0;
4028 
4029 	if (phy_post_delay > 20)
4030 		msleep(phy_post_delay);
4031 	else
4032 		usleep_range(phy_post_delay * 1000,
4033 			     phy_post_delay * 1000 + 1000);
4034 
4035 	return 0;
4036 }
4037 #else /* CONFIG_OF */
4038 static int fec_reset_phy(struct platform_device *pdev)
4039 {
4040 	/*
4041 	 * In case of platform probe, the reset has been done
4042 	 * by machine code.
4043 	 */
4044 	return 0;
4045 }
4046 #endif /* CONFIG_OF */
4047 
4048 static void
4049 fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx)
4050 {
4051 	struct device_node *np = pdev->dev.of_node;
4052 
4053 	*num_tx = *num_rx = 1;
4054 
4055 	if (!np || !of_device_is_available(np))
4056 		return;
4057 
4058 	/* parse the num of tx and rx queues */
4059 	of_property_read_u32(np, "fsl,num-tx-queues", num_tx);
4060 
4061 	of_property_read_u32(np, "fsl,num-rx-queues", num_rx);
4062 
4063 	if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) {
4064 		dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n",
4065 			 *num_tx);
4066 		*num_tx = 1;
4067 		return;
4068 	}
4069 
4070 	if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) {
4071 		dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n",
4072 			 *num_rx);
4073 		*num_rx = 1;
4074 		return;
4075 	}
4076 
4077 }
4078 
4079 static int fec_enet_get_irq_cnt(struct platform_device *pdev)
4080 {
4081 	int irq_cnt = platform_irq_count(pdev);
4082 
4083 	if (irq_cnt > FEC_IRQ_NUM)
4084 		irq_cnt = FEC_IRQ_NUM;	/* last for pps */
4085 	else if (irq_cnt == 2)
4086 		irq_cnt = 1;	/* last for pps */
4087 	else if (irq_cnt <= 0)
4088 		irq_cnt = 1;	/* At least 1 irq is needed */
4089 	return irq_cnt;
4090 }
4091 
4092 static void fec_enet_get_wakeup_irq(struct platform_device *pdev)
4093 {
4094 	struct net_device *ndev = platform_get_drvdata(pdev);
4095 	struct fec_enet_private *fep = netdev_priv(ndev);
4096 
4097 	if (fep->quirks & FEC_QUIRK_WAKEUP_FROM_INT2)
4098 		fep->wake_irq = fep->irq[2];
4099 	else
4100 		fep->wake_irq = fep->irq[0];
4101 }
4102 
4103 static int fec_enet_init_stop_mode(struct fec_enet_private *fep,
4104 				   struct device_node *np)
4105 {
4106 	struct device_node *gpr_np;
4107 	u32 out_val[3];
4108 	int ret = 0;
4109 
4110 	gpr_np = of_parse_phandle(np, "fsl,stop-mode", 0);
4111 	if (!gpr_np)
4112 		return 0;
4113 
4114 	ret = of_property_read_u32_array(np, "fsl,stop-mode", out_val,
4115 					 ARRAY_SIZE(out_val));
4116 	if (ret) {
4117 		dev_dbg(&fep->pdev->dev, "no stop mode property\n");
4118 		goto out;
4119 	}
4120 
4121 	fep->stop_gpr.gpr = syscon_node_to_regmap(gpr_np);
4122 	if (IS_ERR(fep->stop_gpr.gpr)) {
4123 		dev_err(&fep->pdev->dev, "could not find gpr regmap\n");
4124 		ret = PTR_ERR(fep->stop_gpr.gpr);
4125 		fep->stop_gpr.gpr = NULL;
4126 		goto out;
4127 	}
4128 
4129 	fep->stop_gpr.reg = out_val[1];
4130 	fep->stop_gpr.bit = out_val[2];
4131 
4132 out:
4133 	of_node_put(gpr_np);
4134 
4135 	return ret;
4136 }
4137 
4138 static int
4139 fec_probe(struct platform_device *pdev)
4140 {
4141 	struct fec_enet_private *fep;
4142 	struct fec_platform_data *pdata;
4143 	phy_interface_t interface;
4144 	struct net_device *ndev;
4145 	int i, irq, ret = 0;
4146 	const struct of_device_id *of_id;
4147 	static int dev_id;
4148 	struct device_node *np = pdev->dev.of_node, *phy_node;
4149 	int num_tx_qs;
4150 	int num_rx_qs;
4151 	char irq_name[8];
4152 	int irq_cnt;
4153 	struct fec_devinfo *dev_info;
4154 
4155 	fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs);
4156 
4157 	/* Init network device */
4158 	ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private) +
4159 				  FEC_STATS_SIZE, num_tx_qs, num_rx_qs);
4160 	if (!ndev)
4161 		return -ENOMEM;
4162 
4163 	SET_NETDEV_DEV(ndev, &pdev->dev);
4164 
4165 	/* setup board info structure */
4166 	fep = netdev_priv(ndev);
4167 
4168 	of_id = of_match_device(fec_dt_ids, &pdev->dev);
4169 	if (of_id)
4170 		pdev->id_entry = of_id->data;
4171 	dev_info = (struct fec_devinfo *)pdev->id_entry->driver_data;
4172 	if (dev_info)
4173 		fep->quirks = dev_info->quirks;
4174 
4175 	fep->netdev = ndev;
4176 	fep->num_rx_queues = num_rx_qs;
4177 	fep->num_tx_queues = num_tx_qs;
4178 
4179 #if !defined(CONFIG_M5272)
4180 	/* default enable pause frame auto negotiation */
4181 	if (fep->quirks & FEC_QUIRK_HAS_GBIT)
4182 		fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
4183 #endif
4184 
4185 	/* Select default pin state */
4186 	pinctrl_pm_select_default_state(&pdev->dev);
4187 
4188 	fep->hwp = devm_platform_ioremap_resource(pdev, 0);
4189 	if (IS_ERR(fep->hwp)) {
4190 		ret = PTR_ERR(fep->hwp);
4191 		goto failed_ioremap;
4192 	}
4193 
4194 	fep->pdev = pdev;
4195 	fep->dev_id = dev_id++;
4196 
4197 	platform_set_drvdata(pdev, ndev);
4198 
4199 	if ((of_machine_is_compatible("fsl,imx6q") ||
4200 	     of_machine_is_compatible("fsl,imx6dl")) &&
4201 	    !of_property_read_bool(np, "fsl,err006687-workaround-present"))
4202 		fep->quirks |= FEC_QUIRK_ERR006687;
4203 
4204 	ret = fec_enet_ipc_handle_init(fep);
4205 	if (ret)
4206 		goto failed_ipc_init;
4207 
4208 	if (of_get_property(np, "fsl,magic-packet", NULL))
4209 		fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET;
4210 
4211 	ret = fec_enet_init_stop_mode(fep, np);
4212 	if (ret)
4213 		goto failed_stop_mode;
4214 
4215 	phy_node = of_parse_phandle(np, "phy-handle", 0);
4216 	if (!phy_node && of_phy_is_fixed_link(np)) {
4217 		ret = of_phy_register_fixed_link(np);
4218 		if (ret < 0) {
4219 			dev_err(&pdev->dev,
4220 				"broken fixed-link specification\n");
4221 			goto failed_phy;
4222 		}
4223 		phy_node = of_node_get(np);
4224 	}
4225 	fep->phy_node = phy_node;
4226 
4227 	ret = of_get_phy_mode(pdev->dev.of_node, &interface);
4228 	if (ret) {
4229 		pdata = dev_get_platdata(&pdev->dev);
4230 		if (pdata)
4231 			fep->phy_interface = pdata->phy;
4232 		else
4233 			fep->phy_interface = PHY_INTERFACE_MODE_MII;
4234 	} else {
4235 		fep->phy_interface = interface;
4236 	}
4237 
4238 	ret = fec_enet_parse_rgmii_delay(fep, np);
4239 	if (ret)
4240 		goto failed_rgmii_delay;
4241 
4242 	fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
4243 	if (IS_ERR(fep->clk_ipg)) {
4244 		ret = PTR_ERR(fep->clk_ipg);
4245 		goto failed_clk;
4246 	}
4247 
4248 	fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
4249 	if (IS_ERR(fep->clk_ahb)) {
4250 		ret = PTR_ERR(fep->clk_ahb);
4251 		goto failed_clk;
4252 	}
4253 
4254 	fep->itr_clk_rate = clk_get_rate(fep->clk_ahb);
4255 
4256 	/* enet_out is optional, depends on board */
4257 	fep->clk_enet_out = devm_clk_get_optional(&pdev->dev, "enet_out");
4258 	if (IS_ERR(fep->clk_enet_out)) {
4259 		ret = PTR_ERR(fep->clk_enet_out);
4260 		goto failed_clk;
4261 	}
4262 
4263 	fep->ptp_clk_on = false;
4264 	mutex_init(&fep->ptp_clk_mutex);
4265 
4266 	/* clk_ref is optional, depends on board */
4267 	fep->clk_ref = devm_clk_get_optional(&pdev->dev, "enet_clk_ref");
4268 	if (IS_ERR(fep->clk_ref)) {
4269 		ret = PTR_ERR(fep->clk_ref);
4270 		goto failed_clk;
4271 	}
4272 	fep->clk_ref_rate = clk_get_rate(fep->clk_ref);
4273 
4274 	/* clk_2x_txclk is optional, depends on board */
4275 	if (fep->rgmii_txc_dly || fep->rgmii_rxc_dly) {
4276 		fep->clk_2x_txclk = devm_clk_get(&pdev->dev, "enet_2x_txclk");
4277 		if (IS_ERR(fep->clk_2x_txclk))
4278 			fep->clk_2x_txclk = NULL;
4279 	}
4280 
4281 	fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX;
4282 	fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
4283 	if (IS_ERR(fep->clk_ptp)) {
4284 		fep->clk_ptp = NULL;
4285 		fep->bufdesc_ex = false;
4286 	}
4287 
4288 	ret = fec_enet_clk_enable(ndev, true);
4289 	if (ret)
4290 		goto failed_clk;
4291 
4292 	ret = clk_prepare_enable(fep->clk_ipg);
4293 	if (ret)
4294 		goto failed_clk_ipg;
4295 	ret = clk_prepare_enable(fep->clk_ahb);
4296 	if (ret)
4297 		goto failed_clk_ahb;
4298 
4299 	fep->reg_phy = devm_regulator_get_optional(&pdev->dev, "phy");
4300 	if (!IS_ERR(fep->reg_phy)) {
4301 		ret = regulator_enable(fep->reg_phy);
4302 		if (ret) {
4303 			dev_err(&pdev->dev,
4304 				"Failed to enable phy regulator: %d\n", ret);
4305 			goto failed_regulator;
4306 		}
4307 	} else {
4308 		if (PTR_ERR(fep->reg_phy) == -EPROBE_DEFER) {
4309 			ret = -EPROBE_DEFER;
4310 			goto failed_regulator;
4311 		}
4312 		fep->reg_phy = NULL;
4313 	}
4314 
4315 	pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT);
4316 	pm_runtime_use_autosuspend(&pdev->dev);
4317 	pm_runtime_get_noresume(&pdev->dev);
4318 	pm_runtime_set_active(&pdev->dev);
4319 	pm_runtime_enable(&pdev->dev);
4320 
4321 	ret = fec_reset_phy(pdev);
4322 	if (ret)
4323 		goto failed_reset;
4324 
4325 	irq_cnt = fec_enet_get_irq_cnt(pdev);
4326 	if (fep->bufdesc_ex)
4327 		fec_ptp_init(pdev, irq_cnt);
4328 
4329 	ret = fec_enet_init(ndev);
4330 	if (ret)
4331 		goto failed_init;
4332 
4333 	for (i = 0; i < irq_cnt; i++) {
4334 		snprintf(irq_name, sizeof(irq_name), "int%d", i);
4335 		irq = platform_get_irq_byname_optional(pdev, irq_name);
4336 		if (irq < 0)
4337 			irq = platform_get_irq(pdev, i);
4338 		if (irq < 0) {
4339 			ret = irq;
4340 			goto failed_irq;
4341 		}
4342 		ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt,
4343 				       0, pdev->name, ndev);
4344 		if (ret)
4345 			goto failed_irq;
4346 
4347 		fep->irq[i] = irq;
4348 	}
4349 
4350 	/* Decide which interrupt line is wakeup capable */
4351 	fec_enet_get_wakeup_irq(pdev);
4352 
4353 	ret = fec_enet_mii_init(pdev);
4354 	if (ret)
4355 		goto failed_mii_init;
4356 
4357 	/* Carrier starts down, phylib will bring it up */
4358 	netif_carrier_off(ndev);
4359 	fec_enet_clk_enable(ndev, false);
4360 	pinctrl_pm_select_sleep_state(&pdev->dev);
4361 
4362 	ndev->max_mtu = PKT_MAXBUF_SIZE - ETH_HLEN - ETH_FCS_LEN;
4363 
4364 	ret = register_netdev(ndev);
4365 	if (ret)
4366 		goto failed_register;
4367 
4368 	device_init_wakeup(&ndev->dev, fep->wol_flag &
4369 			   FEC_WOL_HAS_MAGIC_PACKET);
4370 
4371 	if (fep->bufdesc_ex && fep->ptp_clock)
4372 		netdev_info(ndev, "registered PHC device %d\n", fep->dev_id);
4373 
4374 	fep->rx_copybreak = COPYBREAK_DEFAULT;
4375 	INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work);
4376 
4377 	pm_runtime_mark_last_busy(&pdev->dev);
4378 	pm_runtime_put_autosuspend(&pdev->dev);
4379 
4380 	return 0;
4381 
4382 failed_register:
4383 	fec_enet_mii_remove(fep);
4384 failed_mii_init:
4385 failed_irq:
4386 failed_init:
4387 	fec_ptp_stop(pdev);
4388 failed_reset:
4389 	pm_runtime_put_noidle(&pdev->dev);
4390 	pm_runtime_disable(&pdev->dev);
4391 	if (fep->reg_phy)
4392 		regulator_disable(fep->reg_phy);
4393 failed_regulator:
4394 	clk_disable_unprepare(fep->clk_ahb);
4395 failed_clk_ahb:
4396 	clk_disable_unprepare(fep->clk_ipg);
4397 failed_clk_ipg:
4398 	fec_enet_clk_enable(ndev, false);
4399 failed_clk:
4400 failed_rgmii_delay:
4401 	if (of_phy_is_fixed_link(np))
4402 		of_phy_deregister_fixed_link(np);
4403 	of_node_put(phy_node);
4404 failed_stop_mode:
4405 failed_ipc_init:
4406 failed_phy:
4407 	dev_id--;
4408 failed_ioremap:
4409 	free_netdev(ndev);
4410 
4411 	return ret;
4412 }
4413 
4414 static int
4415 fec_drv_remove(struct platform_device *pdev)
4416 {
4417 	struct net_device *ndev = platform_get_drvdata(pdev);
4418 	struct fec_enet_private *fep = netdev_priv(ndev);
4419 	struct device_node *np = pdev->dev.of_node;
4420 	int ret;
4421 
4422 	ret = pm_runtime_resume_and_get(&pdev->dev);
4423 	if (ret < 0)
4424 		return ret;
4425 
4426 	cancel_work_sync(&fep->tx_timeout_work);
4427 	fec_ptp_stop(pdev);
4428 	unregister_netdev(ndev);
4429 	fec_enet_mii_remove(fep);
4430 	if (fep->reg_phy)
4431 		regulator_disable(fep->reg_phy);
4432 
4433 	if (of_phy_is_fixed_link(np))
4434 		of_phy_deregister_fixed_link(np);
4435 	of_node_put(fep->phy_node);
4436 
4437 	clk_disable_unprepare(fep->clk_ahb);
4438 	clk_disable_unprepare(fep->clk_ipg);
4439 	pm_runtime_put_noidle(&pdev->dev);
4440 	pm_runtime_disable(&pdev->dev);
4441 
4442 	free_netdev(ndev);
4443 	return 0;
4444 }
4445 
4446 static int __maybe_unused fec_suspend(struct device *dev)
4447 {
4448 	struct net_device *ndev = dev_get_drvdata(dev);
4449 	struct fec_enet_private *fep = netdev_priv(ndev);
4450 	int ret;
4451 
4452 	rtnl_lock();
4453 	if (netif_running(ndev)) {
4454 		if (fep->wol_flag & FEC_WOL_FLAG_ENABLE)
4455 			fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON;
4456 		phy_stop(ndev->phydev);
4457 		napi_disable(&fep->napi);
4458 		netif_tx_lock_bh(ndev);
4459 		netif_device_detach(ndev);
4460 		netif_tx_unlock_bh(ndev);
4461 		fec_stop(ndev);
4462 		if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) {
4463 			fec_irqs_disable(ndev);
4464 			pinctrl_pm_select_sleep_state(&fep->pdev->dev);
4465 		} else {
4466 			fec_irqs_disable_except_wakeup(ndev);
4467 			if (fep->wake_irq > 0) {
4468 				disable_irq(fep->wake_irq);
4469 				enable_irq_wake(fep->wake_irq);
4470 			}
4471 			fec_enet_stop_mode(fep, true);
4472 		}
4473 		/* It's safe to disable clocks since interrupts are masked */
4474 		fec_enet_clk_enable(ndev, false);
4475 
4476 		fep->rpm_active = !pm_runtime_status_suspended(dev);
4477 		if (fep->rpm_active) {
4478 			ret = pm_runtime_force_suspend(dev);
4479 			if (ret < 0) {
4480 				rtnl_unlock();
4481 				return ret;
4482 			}
4483 		}
4484 	}
4485 	rtnl_unlock();
4486 
4487 	if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE))
4488 		regulator_disable(fep->reg_phy);
4489 
4490 	/* SOC supply clock to phy, when clock is disabled, phy link down
4491 	 * SOC control phy regulator, when regulator is disabled, phy link down
4492 	 */
4493 	if (fep->clk_enet_out || fep->reg_phy)
4494 		fep->link = 0;
4495 
4496 	return 0;
4497 }
4498 
4499 static int __maybe_unused fec_resume(struct device *dev)
4500 {
4501 	struct net_device *ndev = dev_get_drvdata(dev);
4502 	struct fec_enet_private *fep = netdev_priv(ndev);
4503 	int ret;
4504 	int val;
4505 
4506 	if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) {
4507 		ret = regulator_enable(fep->reg_phy);
4508 		if (ret)
4509 			return ret;
4510 	}
4511 
4512 	rtnl_lock();
4513 	if (netif_running(ndev)) {
4514 		if (fep->rpm_active)
4515 			pm_runtime_force_resume(dev);
4516 
4517 		ret = fec_enet_clk_enable(ndev, true);
4518 		if (ret) {
4519 			rtnl_unlock();
4520 			goto failed_clk;
4521 		}
4522 		if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) {
4523 			fec_enet_stop_mode(fep, false);
4524 			if (fep->wake_irq) {
4525 				disable_irq_wake(fep->wake_irq);
4526 				enable_irq(fep->wake_irq);
4527 			}
4528 
4529 			val = readl(fep->hwp + FEC_ECNTRL);
4530 			val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
4531 			writel(val, fep->hwp + FEC_ECNTRL);
4532 			fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON;
4533 		} else {
4534 			pinctrl_pm_select_default_state(&fep->pdev->dev);
4535 		}
4536 		fec_restart(ndev);
4537 		netif_tx_lock_bh(ndev);
4538 		netif_device_attach(ndev);
4539 		netif_tx_unlock_bh(ndev);
4540 		napi_enable(&fep->napi);
4541 		phy_init_hw(ndev->phydev);
4542 		phy_start(ndev->phydev);
4543 	}
4544 	rtnl_unlock();
4545 
4546 	return 0;
4547 
4548 failed_clk:
4549 	if (fep->reg_phy)
4550 		regulator_disable(fep->reg_phy);
4551 	return ret;
4552 }
4553 
4554 static int __maybe_unused fec_runtime_suspend(struct device *dev)
4555 {
4556 	struct net_device *ndev = dev_get_drvdata(dev);
4557 	struct fec_enet_private *fep = netdev_priv(ndev);
4558 
4559 	clk_disable_unprepare(fep->clk_ahb);
4560 	clk_disable_unprepare(fep->clk_ipg);
4561 
4562 	return 0;
4563 }
4564 
4565 static int __maybe_unused fec_runtime_resume(struct device *dev)
4566 {
4567 	struct net_device *ndev = dev_get_drvdata(dev);
4568 	struct fec_enet_private *fep = netdev_priv(ndev);
4569 	int ret;
4570 
4571 	ret = clk_prepare_enable(fep->clk_ahb);
4572 	if (ret)
4573 		return ret;
4574 	ret = clk_prepare_enable(fep->clk_ipg);
4575 	if (ret)
4576 		goto failed_clk_ipg;
4577 
4578 	return 0;
4579 
4580 failed_clk_ipg:
4581 	clk_disable_unprepare(fep->clk_ahb);
4582 	return ret;
4583 }
4584 
4585 static const struct dev_pm_ops fec_pm_ops = {
4586 	SET_SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume)
4587 	SET_RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL)
4588 };
4589 
4590 static struct platform_driver fec_driver = {
4591 	.driver	= {
4592 		.name	= DRIVER_NAME,
4593 		.pm	= &fec_pm_ops,
4594 		.of_match_table = fec_dt_ids,
4595 		.suppress_bind_attrs = true,
4596 	},
4597 	.id_table = fec_devtype,
4598 	.probe	= fec_probe,
4599 	.remove	= fec_drv_remove,
4600 };
4601 
4602 module_platform_driver(fec_driver);
4603 
4604 MODULE_LICENSE("GPL");
4605