1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. 4 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) 5 * 6 * Right now, I am very wasteful with the buffers. I allocate memory 7 * pages and then divide them into 2K frame buffers. This way I know I 8 * have buffers large enough to hold one frame within one buffer descriptor. 9 * Once I get this working, I will use 64 or 128 byte CPM buffers, which 10 * will be much more memory efficient and will easily handle lots of 11 * small packets. 12 * 13 * Much better multiple PHY support by Magnus Damm. 14 * Copyright (c) 2000 Ericsson Radio Systems AB. 15 * 16 * Support for FEC controller of ColdFire processors. 17 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) 18 * 19 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) 20 * Copyright (c) 2004-2006 Macq Electronique SA. 21 * 22 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. 23 */ 24 25 #include <linux/module.h> 26 #include <linux/kernel.h> 27 #include <linux/string.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/ptrace.h> 30 #include <linux/errno.h> 31 #include <linux/ioport.h> 32 #include <linux/slab.h> 33 #include <linux/interrupt.h> 34 #include <linux/delay.h> 35 #include <linux/netdevice.h> 36 #include <linux/etherdevice.h> 37 #include <linux/skbuff.h> 38 #include <linux/in.h> 39 #include <linux/ip.h> 40 #include <net/ip.h> 41 #include <net/selftests.h> 42 #include <net/tso.h> 43 #include <linux/tcp.h> 44 #include <linux/udp.h> 45 #include <linux/icmp.h> 46 #include <linux/spinlock.h> 47 #include <linux/workqueue.h> 48 #include <linux/bitops.h> 49 #include <linux/io.h> 50 #include <linux/irq.h> 51 #include <linux/clk.h> 52 #include <linux/crc32.h> 53 #include <linux/platform_device.h> 54 #include <linux/mdio.h> 55 #include <linux/phy.h> 56 #include <linux/fec.h> 57 #include <linux/of.h> 58 #include <linux/of_device.h> 59 #include <linux/of_gpio.h> 60 #include <linux/of_mdio.h> 61 #include <linux/of_net.h> 62 #include <linux/regulator/consumer.h> 63 #include <linux/if_vlan.h> 64 #include <linux/pinctrl/consumer.h> 65 #include <linux/prefetch.h> 66 #include <linux/mfd/syscon.h> 67 #include <linux/regmap.h> 68 #include <soc/imx/cpuidle.h> 69 70 #include <asm/cacheflush.h> 71 72 #include "fec.h" 73 74 static void set_multicast_list(struct net_device *ndev); 75 static void fec_enet_itr_coal_init(struct net_device *ndev); 76 77 #define DRIVER_NAME "fec" 78 79 /* Pause frame feild and FIFO threshold */ 80 #define FEC_ENET_FCE (1 << 5) 81 #define FEC_ENET_RSEM_V 0x84 82 #define FEC_ENET_RSFL_V 16 83 #define FEC_ENET_RAEM_V 0x8 84 #define FEC_ENET_RAFL_V 0x8 85 #define FEC_ENET_OPD_V 0xFFF0 86 #define FEC_MDIO_PM_TIMEOUT 100 /* ms */ 87 88 struct fec_devinfo { 89 u32 quirks; 90 }; 91 92 static const struct fec_devinfo fec_imx25_info = { 93 .quirks = FEC_QUIRK_USE_GASKET | FEC_QUIRK_MIB_CLEAR | 94 FEC_QUIRK_HAS_FRREG, 95 }; 96 97 static const struct fec_devinfo fec_imx27_info = { 98 .quirks = FEC_QUIRK_MIB_CLEAR | FEC_QUIRK_HAS_FRREG, 99 }; 100 101 static const struct fec_devinfo fec_imx28_info = { 102 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME | 103 FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC | 104 FEC_QUIRK_HAS_FRREG | FEC_QUIRK_CLEAR_SETUP_MII | 105 FEC_QUIRK_NO_HARD_RESET, 106 }; 107 108 static const struct fec_devinfo fec_imx6q_info = { 109 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 110 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 111 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 | 112 FEC_QUIRK_HAS_RACC | FEC_QUIRK_CLEAR_SETUP_MII, 113 }; 114 115 static const struct fec_devinfo fec_mvf600_info = { 116 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC, 117 }; 118 119 static const struct fec_devinfo fec_imx6x_info = { 120 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 121 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 122 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 123 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 124 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE | 125 FEC_QUIRK_CLEAR_SETUP_MII, 126 }; 127 128 static const struct fec_devinfo fec_imx6ul_info = { 129 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 130 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 131 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR007885 | 132 FEC_QUIRK_BUG_CAPTURE | FEC_QUIRK_HAS_RACC | 133 FEC_QUIRK_HAS_COALESCE | FEC_QUIRK_CLEAR_SETUP_MII, 134 }; 135 136 static struct platform_device_id fec_devtype[] = { 137 { 138 /* keep it for coldfire */ 139 .name = DRIVER_NAME, 140 .driver_data = 0, 141 }, { 142 .name = "imx25-fec", 143 .driver_data = (kernel_ulong_t)&fec_imx25_info, 144 }, { 145 .name = "imx27-fec", 146 .driver_data = (kernel_ulong_t)&fec_imx27_info, 147 }, { 148 .name = "imx28-fec", 149 .driver_data = (kernel_ulong_t)&fec_imx28_info, 150 }, { 151 .name = "imx6q-fec", 152 .driver_data = (kernel_ulong_t)&fec_imx6q_info, 153 }, { 154 .name = "mvf600-fec", 155 .driver_data = (kernel_ulong_t)&fec_mvf600_info, 156 }, { 157 .name = "imx6sx-fec", 158 .driver_data = (kernel_ulong_t)&fec_imx6x_info, 159 }, { 160 .name = "imx6ul-fec", 161 .driver_data = (kernel_ulong_t)&fec_imx6ul_info, 162 }, { 163 /* sentinel */ 164 } 165 }; 166 MODULE_DEVICE_TABLE(platform, fec_devtype); 167 168 enum imx_fec_type { 169 IMX25_FEC = 1, /* runs on i.mx25/50/53 */ 170 IMX27_FEC, /* runs on i.mx27/35/51 */ 171 IMX28_FEC, 172 IMX6Q_FEC, 173 MVF600_FEC, 174 IMX6SX_FEC, 175 IMX6UL_FEC, 176 }; 177 178 static const struct of_device_id fec_dt_ids[] = { 179 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], }, 180 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], }, 181 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], }, 182 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], }, 183 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], }, 184 { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], }, 185 { .compatible = "fsl,imx6ul-fec", .data = &fec_devtype[IMX6UL_FEC], }, 186 { /* sentinel */ } 187 }; 188 MODULE_DEVICE_TABLE(of, fec_dt_ids); 189 190 static unsigned char macaddr[ETH_ALEN]; 191 module_param_array(macaddr, byte, NULL, 0); 192 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address"); 193 194 #if defined(CONFIG_M5272) 195 /* 196 * Some hardware gets it MAC address out of local flash memory. 197 * if this is non-zero then assume it is the address to get MAC from. 198 */ 199 #if defined(CONFIG_NETtel) 200 #define FEC_FLASHMAC 0xf0006006 201 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) 202 #define FEC_FLASHMAC 0xf0006000 203 #elif defined(CONFIG_CANCam) 204 #define FEC_FLASHMAC 0xf0020000 205 #elif defined (CONFIG_M5272C3) 206 #define FEC_FLASHMAC (0xffe04000 + 4) 207 #elif defined(CONFIG_MOD5272) 208 #define FEC_FLASHMAC 0xffc0406b 209 #else 210 #define FEC_FLASHMAC 0 211 #endif 212 #endif /* CONFIG_M5272 */ 213 214 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets. 215 * 216 * 2048 byte skbufs are allocated. However, alignment requirements 217 * varies between FEC variants. Worst case is 64, so round down by 64. 218 */ 219 #define PKT_MAXBUF_SIZE (round_down(2048 - 64, 64)) 220 #define PKT_MINBUF_SIZE 64 221 222 /* FEC receive acceleration */ 223 #define FEC_RACC_IPDIS (1 << 1) 224 #define FEC_RACC_PRODIS (1 << 2) 225 #define FEC_RACC_SHIFT16 BIT(7) 226 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS) 227 228 /* MIB Control Register */ 229 #define FEC_MIB_CTRLSTAT_DISABLE BIT(31) 230 231 /* 232 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame 233 * size bits. Other FEC hardware does not, so we need to take that into 234 * account when setting it. 235 */ 236 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 237 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \ 238 defined(CONFIG_ARM64) 239 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) 240 #else 241 #define OPT_FRAME_SIZE 0 242 #endif 243 244 /* FEC MII MMFR bits definition */ 245 #define FEC_MMFR_ST (1 << 30) 246 #define FEC_MMFR_ST_C45 (0) 247 #define FEC_MMFR_OP_READ (2 << 28) 248 #define FEC_MMFR_OP_READ_C45 (3 << 28) 249 #define FEC_MMFR_OP_WRITE (1 << 28) 250 #define FEC_MMFR_OP_ADDR_WRITE (0) 251 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23) 252 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18) 253 #define FEC_MMFR_TA (2 << 16) 254 #define FEC_MMFR_DATA(v) (v & 0xffff) 255 /* FEC ECR bits definition */ 256 #define FEC_ECR_MAGICEN (1 << 2) 257 #define FEC_ECR_SLEEP (1 << 3) 258 259 #define FEC_MII_TIMEOUT 30000 /* us */ 260 261 /* Transmitter timeout */ 262 #define TX_TIMEOUT (2 * HZ) 263 264 #define FEC_PAUSE_FLAG_AUTONEG 0x1 265 #define FEC_PAUSE_FLAG_ENABLE 0x2 266 #define FEC_WOL_HAS_MAGIC_PACKET (0x1 << 0) 267 #define FEC_WOL_FLAG_ENABLE (0x1 << 1) 268 #define FEC_WOL_FLAG_SLEEP_ON (0x1 << 2) 269 270 #define COPYBREAK_DEFAULT 256 271 272 /* Max number of allowed TCP segments for software TSO */ 273 #define FEC_MAX_TSO_SEGS 100 274 #define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) 275 276 #define IS_TSO_HEADER(txq, addr) \ 277 ((addr >= txq->tso_hdrs_dma) && \ 278 (addr < txq->tso_hdrs_dma + txq->bd.ring_size * TSO_HEADER_SIZE)) 279 280 static int mii_cnt; 281 282 static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, 283 struct bufdesc_prop *bd) 284 { 285 return (bdp >= bd->last) ? bd->base 286 : (struct bufdesc *)(((void *)bdp) + bd->dsize); 287 } 288 289 static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, 290 struct bufdesc_prop *bd) 291 { 292 return (bdp <= bd->base) ? bd->last 293 : (struct bufdesc *)(((void *)bdp) - bd->dsize); 294 } 295 296 static int fec_enet_get_bd_index(struct bufdesc *bdp, 297 struct bufdesc_prop *bd) 298 { 299 return ((const char *)bdp - (const char *)bd->base) >> bd->dsize_log2; 300 } 301 302 static int fec_enet_get_free_txdesc_num(struct fec_enet_priv_tx_q *txq) 303 { 304 int entries; 305 306 entries = (((const char *)txq->dirty_tx - 307 (const char *)txq->bd.cur) >> txq->bd.dsize_log2) - 1; 308 309 return entries >= 0 ? entries : entries + txq->bd.ring_size; 310 } 311 312 static void swap_buffer(void *bufaddr, int len) 313 { 314 int i; 315 unsigned int *buf = bufaddr; 316 317 for (i = 0; i < len; i += 4, buf++) 318 swab32s(buf); 319 } 320 321 static void swap_buffer2(void *dst_buf, void *src_buf, int len) 322 { 323 int i; 324 unsigned int *src = src_buf; 325 unsigned int *dst = dst_buf; 326 327 for (i = 0; i < len; i += 4, src++, dst++) 328 *dst = swab32p(src); 329 } 330 331 static void fec_dump(struct net_device *ndev) 332 { 333 struct fec_enet_private *fep = netdev_priv(ndev); 334 struct bufdesc *bdp; 335 struct fec_enet_priv_tx_q *txq; 336 int index = 0; 337 338 netdev_info(ndev, "TX ring dump\n"); 339 pr_info("Nr SC addr len SKB\n"); 340 341 txq = fep->tx_queue[0]; 342 bdp = txq->bd.base; 343 344 do { 345 pr_info("%3u %c%c 0x%04x 0x%08x %4u %p\n", 346 index, 347 bdp == txq->bd.cur ? 'S' : ' ', 348 bdp == txq->dirty_tx ? 'H' : ' ', 349 fec16_to_cpu(bdp->cbd_sc), 350 fec32_to_cpu(bdp->cbd_bufaddr), 351 fec16_to_cpu(bdp->cbd_datlen), 352 txq->tx_skbuff[index]); 353 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 354 index++; 355 } while (bdp != txq->bd.base); 356 } 357 358 static inline bool is_ipv4_pkt(struct sk_buff *skb) 359 { 360 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4; 361 } 362 363 static int 364 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev) 365 { 366 /* Only run for packets requiring a checksum. */ 367 if (skb->ip_summed != CHECKSUM_PARTIAL) 368 return 0; 369 370 if (unlikely(skb_cow_head(skb, 0))) 371 return -1; 372 373 if (is_ipv4_pkt(skb)) 374 ip_hdr(skb)->check = 0; 375 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0; 376 377 return 0; 378 } 379 380 static struct bufdesc * 381 fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq, 382 struct sk_buff *skb, 383 struct net_device *ndev) 384 { 385 struct fec_enet_private *fep = netdev_priv(ndev); 386 struct bufdesc *bdp = txq->bd.cur; 387 struct bufdesc_ex *ebdp; 388 int nr_frags = skb_shinfo(skb)->nr_frags; 389 int frag, frag_len; 390 unsigned short status; 391 unsigned int estatus = 0; 392 skb_frag_t *this_frag; 393 unsigned int index; 394 void *bufaddr; 395 dma_addr_t addr; 396 int i; 397 398 for (frag = 0; frag < nr_frags; frag++) { 399 this_frag = &skb_shinfo(skb)->frags[frag]; 400 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 401 ebdp = (struct bufdesc_ex *)bdp; 402 403 status = fec16_to_cpu(bdp->cbd_sc); 404 status &= ~BD_ENET_TX_STATS; 405 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 406 frag_len = skb_frag_size(&skb_shinfo(skb)->frags[frag]); 407 408 /* Handle the last BD specially */ 409 if (frag == nr_frags - 1) { 410 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 411 if (fep->bufdesc_ex) { 412 estatus |= BD_ENET_TX_INT; 413 if (unlikely(skb_shinfo(skb)->tx_flags & 414 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 415 estatus |= BD_ENET_TX_TS; 416 } 417 } 418 419 if (fep->bufdesc_ex) { 420 if (fep->quirks & FEC_QUIRK_HAS_AVB) 421 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 422 if (skb->ip_summed == CHECKSUM_PARTIAL) 423 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 424 ebdp->cbd_bdu = 0; 425 ebdp->cbd_esc = cpu_to_fec32(estatus); 426 } 427 428 bufaddr = skb_frag_address(this_frag); 429 430 index = fec_enet_get_bd_index(bdp, &txq->bd); 431 if (((unsigned long) bufaddr) & fep->tx_align || 432 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 433 memcpy(txq->tx_bounce[index], bufaddr, frag_len); 434 bufaddr = txq->tx_bounce[index]; 435 436 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 437 swap_buffer(bufaddr, frag_len); 438 } 439 440 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len, 441 DMA_TO_DEVICE); 442 if (dma_mapping_error(&fep->pdev->dev, addr)) { 443 if (net_ratelimit()) 444 netdev_err(ndev, "Tx DMA memory map failed\n"); 445 goto dma_mapping_error; 446 } 447 448 bdp->cbd_bufaddr = cpu_to_fec32(addr); 449 bdp->cbd_datlen = cpu_to_fec16(frag_len); 450 /* Make sure the updates to rest of the descriptor are 451 * performed before transferring ownership. 452 */ 453 wmb(); 454 bdp->cbd_sc = cpu_to_fec16(status); 455 } 456 457 return bdp; 458 dma_mapping_error: 459 bdp = txq->bd.cur; 460 for (i = 0; i < frag; i++) { 461 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 462 dma_unmap_single(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr), 463 fec16_to_cpu(bdp->cbd_datlen), DMA_TO_DEVICE); 464 } 465 return ERR_PTR(-ENOMEM); 466 } 467 468 static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq, 469 struct sk_buff *skb, struct net_device *ndev) 470 { 471 struct fec_enet_private *fep = netdev_priv(ndev); 472 int nr_frags = skb_shinfo(skb)->nr_frags; 473 struct bufdesc *bdp, *last_bdp; 474 void *bufaddr; 475 dma_addr_t addr; 476 unsigned short status; 477 unsigned short buflen; 478 unsigned int estatus = 0; 479 unsigned int index; 480 int entries_free; 481 482 entries_free = fec_enet_get_free_txdesc_num(txq); 483 if (entries_free < MAX_SKB_FRAGS + 1) { 484 dev_kfree_skb_any(skb); 485 if (net_ratelimit()) 486 netdev_err(ndev, "NOT enough BD for SG!\n"); 487 return NETDEV_TX_OK; 488 } 489 490 /* Protocol checksum off-load for TCP and UDP. */ 491 if (fec_enet_clear_csum(skb, ndev)) { 492 dev_kfree_skb_any(skb); 493 return NETDEV_TX_OK; 494 } 495 496 /* Fill in a Tx ring entry */ 497 bdp = txq->bd.cur; 498 last_bdp = bdp; 499 status = fec16_to_cpu(bdp->cbd_sc); 500 status &= ~BD_ENET_TX_STATS; 501 502 /* Set buffer length and buffer pointer */ 503 bufaddr = skb->data; 504 buflen = skb_headlen(skb); 505 506 index = fec_enet_get_bd_index(bdp, &txq->bd); 507 if (((unsigned long) bufaddr) & fep->tx_align || 508 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 509 memcpy(txq->tx_bounce[index], skb->data, buflen); 510 bufaddr = txq->tx_bounce[index]; 511 512 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 513 swap_buffer(bufaddr, buflen); 514 } 515 516 /* Push the data cache so the CPM does not get stale memory data. */ 517 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE); 518 if (dma_mapping_error(&fep->pdev->dev, addr)) { 519 dev_kfree_skb_any(skb); 520 if (net_ratelimit()) 521 netdev_err(ndev, "Tx DMA memory map failed\n"); 522 return NETDEV_TX_OK; 523 } 524 525 if (nr_frags) { 526 last_bdp = fec_enet_txq_submit_frag_skb(txq, skb, ndev); 527 if (IS_ERR(last_bdp)) { 528 dma_unmap_single(&fep->pdev->dev, addr, 529 buflen, DMA_TO_DEVICE); 530 dev_kfree_skb_any(skb); 531 return NETDEV_TX_OK; 532 } 533 } else { 534 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 535 if (fep->bufdesc_ex) { 536 estatus = BD_ENET_TX_INT; 537 if (unlikely(skb_shinfo(skb)->tx_flags & 538 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 539 estatus |= BD_ENET_TX_TS; 540 } 541 } 542 bdp->cbd_bufaddr = cpu_to_fec32(addr); 543 bdp->cbd_datlen = cpu_to_fec16(buflen); 544 545 if (fep->bufdesc_ex) { 546 547 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 548 549 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 550 fep->hwts_tx_en)) 551 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 552 553 if (fep->quirks & FEC_QUIRK_HAS_AVB) 554 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 555 556 if (skb->ip_summed == CHECKSUM_PARTIAL) 557 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 558 559 ebdp->cbd_bdu = 0; 560 ebdp->cbd_esc = cpu_to_fec32(estatus); 561 } 562 563 index = fec_enet_get_bd_index(last_bdp, &txq->bd); 564 /* Save skb pointer */ 565 txq->tx_skbuff[index] = skb; 566 567 /* Make sure the updates to rest of the descriptor are performed before 568 * transferring ownership. 569 */ 570 wmb(); 571 572 /* Send it on its way. Tell FEC it's ready, interrupt when done, 573 * it's the last BD of the frame, and to put the CRC on the end. 574 */ 575 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC); 576 bdp->cbd_sc = cpu_to_fec16(status); 577 578 /* If this was the last BD in the ring, start at the beginning again. */ 579 bdp = fec_enet_get_nextdesc(last_bdp, &txq->bd); 580 581 skb_tx_timestamp(skb); 582 583 /* Make sure the update to bdp and tx_skbuff are performed before 584 * txq->bd.cur. 585 */ 586 wmb(); 587 txq->bd.cur = bdp; 588 589 /* Trigger transmission start */ 590 writel(0, txq->bd.reg_desc_active); 591 592 return 0; 593 } 594 595 static int 596 fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb, 597 struct net_device *ndev, 598 struct bufdesc *bdp, int index, char *data, 599 int size, bool last_tcp, bool is_last) 600 { 601 struct fec_enet_private *fep = netdev_priv(ndev); 602 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 603 unsigned short status; 604 unsigned int estatus = 0; 605 dma_addr_t addr; 606 607 status = fec16_to_cpu(bdp->cbd_sc); 608 status &= ~BD_ENET_TX_STATS; 609 610 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 611 612 if (((unsigned long) data) & fep->tx_align || 613 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 614 memcpy(txq->tx_bounce[index], data, size); 615 data = txq->tx_bounce[index]; 616 617 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 618 swap_buffer(data, size); 619 } 620 621 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE); 622 if (dma_mapping_error(&fep->pdev->dev, addr)) { 623 dev_kfree_skb_any(skb); 624 if (net_ratelimit()) 625 netdev_err(ndev, "Tx DMA memory map failed\n"); 626 return NETDEV_TX_BUSY; 627 } 628 629 bdp->cbd_datlen = cpu_to_fec16(size); 630 bdp->cbd_bufaddr = cpu_to_fec32(addr); 631 632 if (fep->bufdesc_ex) { 633 if (fep->quirks & FEC_QUIRK_HAS_AVB) 634 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 635 if (skb->ip_summed == CHECKSUM_PARTIAL) 636 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 637 ebdp->cbd_bdu = 0; 638 ebdp->cbd_esc = cpu_to_fec32(estatus); 639 } 640 641 /* Handle the last BD specially */ 642 if (last_tcp) 643 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC); 644 if (is_last) { 645 status |= BD_ENET_TX_INTR; 646 if (fep->bufdesc_ex) 647 ebdp->cbd_esc |= cpu_to_fec32(BD_ENET_TX_INT); 648 } 649 650 bdp->cbd_sc = cpu_to_fec16(status); 651 652 return 0; 653 } 654 655 static int 656 fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq, 657 struct sk_buff *skb, struct net_device *ndev, 658 struct bufdesc *bdp, int index) 659 { 660 struct fec_enet_private *fep = netdev_priv(ndev); 661 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 662 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 663 void *bufaddr; 664 unsigned long dmabuf; 665 unsigned short status; 666 unsigned int estatus = 0; 667 668 status = fec16_to_cpu(bdp->cbd_sc); 669 status &= ~BD_ENET_TX_STATS; 670 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 671 672 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 673 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE; 674 if (((unsigned long)bufaddr) & fep->tx_align || 675 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 676 memcpy(txq->tx_bounce[index], skb->data, hdr_len); 677 bufaddr = txq->tx_bounce[index]; 678 679 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 680 swap_buffer(bufaddr, hdr_len); 681 682 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr, 683 hdr_len, DMA_TO_DEVICE); 684 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) { 685 dev_kfree_skb_any(skb); 686 if (net_ratelimit()) 687 netdev_err(ndev, "Tx DMA memory map failed\n"); 688 return NETDEV_TX_BUSY; 689 } 690 } 691 692 bdp->cbd_bufaddr = cpu_to_fec32(dmabuf); 693 bdp->cbd_datlen = cpu_to_fec16(hdr_len); 694 695 if (fep->bufdesc_ex) { 696 if (fep->quirks & FEC_QUIRK_HAS_AVB) 697 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 698 if (skb->ip_summed == CHECKSUM_PARTIAL) 699 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 700 ebdp->cbd_bdu = 0; 701 ebdp->cbd_esc = cpu_to_fec32(estatus); 702 } 703 704 bdp->cbd_sc = cpu_to_fec16(status); 705 706 return 0; 707 } 708 709 static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq, 710 struct sk_buff *skb, 711 struct net_device *ndev) 712 { 713 struct fec_enet_private *fep = netdev_priv(ndev); 714 int hdr_len, total_len, data_left; 715 struct bufdesc *bdp = txq->bd.cur; 716 struct tso_t tso; 717 unsigned int index = 0; 718 int ret; 719 720 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(txq)) { 721 dev_kfree_skb_any(skb); 722 if (net_ratelimit()) 723 netdev_err(ndev, "NOT enough BD for TSO!\n"); 724 return NETDEV_TX_OK; 725 } 726 727 /* Protocol checksum off-load for TCP and UDP. */ 728 if (fec_enet_clear_csum(skb, ndev)) { 729 dev_kfree_skb_any(skb); 730 return NETDEV_TX_OK; 731 } 732 733 /* Initialize the TSO handler, and prepare the first payload */ 734 hdr_len = tso_start(skb, &tso); 735 736 total_len = skb->len - hdr_len; 737 while (total_len > 0) { 738 char *hdr; 739 740 index = fec_enet_get_bd_index(bdp, &txq->bd); 741 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); 742 total_len -= data_left; 743 744 /* prepare packet headers: MAC + IP + TCP */ 745 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 746 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); 747 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index); 748 if (ret) 749 goto err_release; 750 751 while (data_left > 0) { 752 int size; 753 754 size = min_t(int, tso.size, data_left); 755 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 756 index = fec_enet_get_bd_index(bdp, &txq->bd); 757 ret = fec_enet_txq_put_data_tso(txq, skb, ndev, 758 bdp, index, 759 tso.data, size, 760 size == data_left, 761 total_len == 0); 762 if (ret) 763 goto err_release; 764 765 data_left -= size; 766 tso_build_data(skb, &tso, size); 767 } 768 769 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 770 } 771 772 /* Save skb pointer */ 773 txq->tx_skbuff[index] = skb; 774 775 skb_tx_timestamp(skb); 776 txq->bd.cur = bdp; 777 778 /* Trigger transmission start */ 779 if (!(fep->quirks & FEC_QUIRK_ERR007885) || 780 !readl(txq->bd.reg_desc_active) || 781 !readl(txq->bd.reg_desc_active) || 782 !readl(txq->bd.reg_desc_active) || 783 !readl(txq->bd.reg_desc_active)) 784 writel(0, txq->bd.reg_desc_active); 785 786 return 0; 787 788 err_release: 789 /* TODO: Release all used data descriptors for TSO */ 790 return ret; 791 } 792 793 static netdev_tx_t 794 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) 795 { 796 struct fec_enet_private *fep = netdev_priv(ndev); 797 int entries_free; 798 unsigned short queue; 799 struct fec_enet_priv_tx_q *txq; 800 struct netdev_queue *nq; 801 int ret; 802 803 queue = skb_get_queue_mapping(skb); 804 txq = fep->tx_queue[queue]; 805 nq = netdev_get_tx_queue(ndev, queue); 806 807 if (skb_is_gso(skb)) 808 ret = fec_enet_txq_submit_tso(txq, skb, ndev); 809 else 810 ret = fec_enet_txq_submit_skb(txq, skb, ndev); 811 if (ret) 812 return ret; 813 814 entries_free = fec_enet_get_free_txdesc_num(txq); 815 if (entries_free <= txq->tx_stop_threshold) 816 netif_tx_stop_queue(nq); 817 818 return NETDEV_TX_OK; 819 } 820 821 /* Init RX & TX buffer descriptors 822 */ 823 static void fec_enet_bd_init(struct net_device *dev) 824 { 825 struct fec_enet_private *fep = netdev_priv(dev); 826 struct fec_enet_priv_tx_q *txq; 827 struct fec_enet_priv_rx_q *rxq; 828 struct bufdesc *bdp; 829 unsigned int i; 830 unsigned int q; 831 832 for (q = 0; q < fep->num_rx_queues; q++) { 833 /* Initialize the receive buffer descriptors. */ 834 rxq = fep->rx_queue[q]; 835 bdp = rxq->bd.base; 836 837 for (i = 0; i < rxq->bd.ring_size; i++) { 838 839 /* Initialize the BD for every fragment in the page. */ 840 if (bdp->cbd_bufaddr) 841 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); 842 else 843 bdp->cbd_sc = cpu_to_fec16(0); 844 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 845 } 846 847 /* Set the last buffer to wrap */ 848 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); 849 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 850 851 rxq->bd.cur = rxq->bd.base; 852 } 853 854 for (q = 0; q < fep->num_tx_queues; q++) { 855 /* ...and the same for transmit */ 856 txq = fep->tx_queue[q]; 857 bdp = txq->bd.base; 858 txq->bd.cur = bdp; 859 860 for (i = 0; i < txq->bd.ring_size; i++) { 861 /* Initialize the BD for every fragment in the page. */ 862 bdp->cbd_sc = cpu_to_fec16(0); 863 if (bdp->cbd_bufaddr && 864 !IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr))) 865 dma_unmap_single(&fep->pdev->dev, 866 fec32_to_cpu(bdp->cbd_bufaddr), 867 fec16_to_cpu(bdp->cbd_datlen), 868 DMA_TO_DEVICE); 869 if (txq->tx_skbuff[i]) { 870 dev_kfree_skb_any(txq->tx_skbuff[i]); 871 txq->tx_skbuff[i] = NULL; 872 } 873 bdp->cbd_bufaddr = cpu_to_fec32(0); 874 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 875 } 876 877 /* Set the last buffer to wrap */ 878 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); 879 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 880 txq->dirty_tx = bdp; 881 } 882 } 883 884 static void fec_enet_active_rxring(struct net_device *ndev) 885 { 886 struct fec_enet_private *fep = netdev_priv(ndev); 887 int i; 888 889 for (i = 0; i < fep->num_rx_queues; i++) 890 writel(0, fep->rx_queue[i]->bd.reg_desc_active); 891 } 892 893 static void fec_enet_enable_ring(struct net_device *ndev) 894 { 895 struct fec_enet_private *fep = netdev_priv(ndev); 896 struct fec_enet_priv_tx_q *txq; 897 struct fec_enet_priv_rx_q *rxq; 898 int i; 899 900 for (i = 0; i < fep->num_rx_queues; i++) { 901 rxq = fep->rx_queue[i]; 902 writel(rxq->bd.dma, fep->hwp + FEC_R_DES_START(i)); 903 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i)); 904 905 /* enable DMA1/2 */ 906 if (i) 907 writel(RCMR_MATCHEN | RCMR_CMP(i), 908 fep->hwp + FEC_RCMR(i)); 909 } 910 911 for (i = 0; i < fep->num_tx_queues; i++) { 912 txq = fep->tx_queue[i]; 913 writel(txq->bd.dma, fep->hwp + FEC_X_DES_START(i)); 914 915 /* enable DMA1/2 */ 916 if (i) 917 writel(DMA_CLASS_EN | IDLE_SLOPE(i), 918 fep->hwp + FEC_DMA_CFG(i)); 919 } 920 } 921 922 static void fec_enet_reset_skb(struct net_device *ndev) 923 { 924 struct fec_enet_private *fep = netdev_priv(ndev); 925 struct fec_enet_priv_tx_q *txq; 926 int i, j; 927 928 for (i = 0; i < fep->num_tx_queues; i++) { 929 txq = fep->tx_queue[i]; 930 931 for (j = 0; j < txq->bd.ring_size; j++) { 932 if (txq->tx_skbuff[j]) { 933 dev_kfree_skb_any(txq->tx_skbuff[j]); 934 txq->tx_skbuff[j] = NULL; 935 } 936 } 937 } 938 } 939 940 /* 941 * This function is called to start or restart the FEC during a link 942 * change, transmit timeout, or to reconfigure the FEC. The network 943 * packet processing for this device must be stopped before this call. 944 */ 945 static void 946 fec_restart(struct net_device *ndev) 947 { 948 struct fec_enet_private *fep = netdev_priv(ndev); 949 u32 temp_mac[2]; 950 u32 rcntl = OPT_FRAME_SIZE | 0x04; 951 u32 ecntl = 0x2; /* ETHEREN */ 952 953 /* Whack a reset. We should wait for this. 954 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC 955 * instead of reset MAC itself. 956 */ 957 if (fep->quirks & FEC_QUIRK_HAS_AVB || 958 ((fep->quirks & FEC_QUIRK_NO_HARD_RESET) && fep->link)) { 959 writel(0, fep->hwp + FEC_ECNTRL); 960 } else { 961 writel(1, fep->hwp + FEC_ECNTRL); 962 udelay(10); 963 } 964 965 /* 966 * enet-mac reset will reset mac address registers too, 967 * so need to reconfigure it. 968 */ 969 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN); 970 writel((__force u32)cpu_to_be32(temp_mac[0]), 971 fep->hwp + FEC_ADDR_LOW); 972 writel((__force u32)cpu_to_be32(temp_mac[1]), 973 fep->hwp + FEC_ADDR_HIGH); 974 975 /* Clear any outstanding interrupt, except MDIO. */ 976 writel((0xffffffff & ~FEC_ENET_MII), fep->hwp + FEC_IEVENT); 977 978 fec_enet_bd_init(ndev); 979 980 fec_enet_enable_ring(ndev); 981 982 /* Reset tx SKB buffers. */ 983 fec_enet_reset_skb(ndev); 984 985 /* Enable MII mode */ 986 if (fep->full_duplex == DUPLEX_FULL) { 987 /* FD enable */ 988 writel(0x04, fep->hwp + FEC_X_CNTRL); 989 } else { 990 /* No Rcv on Xmit */ 991 rcntl |= 0x02; 992 writel(0x0, fep->hwp + FEC_X_CNTRL); 993 } 994 995 /* Set MII speed */ 996 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 997 998 #if !defined(CONFIG_M5272) 999 if (fep->quirks & FEC_QUIRK_HAS_RACC) { 1000 u32 val = readl(fep->hwp + FEC_RACC); 1001 1002 /* align IP header */ 1003 val |= FEC_RACC_SHIFT16; 1004 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED) 1005 /* set RX checksum */ 1006 val |= FEC_RACC_OPTIONS; 1007 else 1008 val &= ~FEC_RACC_OPTIONS; 1009 writel(val, fep->hwp + FEC_RACC); 1010 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_FTRL); 1011 } 1012 #endif 1013 1014 /* 1015 * The phy interface and speed need to get configured 1016 * differently on enet-mac. 1017 */ 1018 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 1019 /* Enable flow control and length check */ 1020 rcntl |= 0x40000000 | 0x00000020; 1021 1022 /* RGMII, RMII or MII */ 1023 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII || 1024 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 1025 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID || 1026 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) 1027 rcntl |= (1 << 6); 1028 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 1029 rcntl |= (1 << 8); 1030 else 1031 rcntl &= ~(1 << 8); 1032 1033 /* 1G, 100M or 10M */ 1034 if (ndev->phydev) { 1035 if (ndev->phydev->speed == SPEED_1000) 1036 ecntl |= (1 << 5); 1037 else if (ndev->phydev->speed == SPEED_100) 1038 rcntl &= ~(1 << 9); 1039 else 1040 rcntl |= (1 << 9); 1041 } 1042 } else { 1043 #ifdef FEC_MIIGSK_ENR 1044 if (fep->quirks & FEC_QUIRK_USE_GASKET) { 1045 u32 cfgr; 1046 /* disable the gasket and wait */ 1047 writel(0, fep->hwp + FEC_MIIGSK_ENR); 1048 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4) 1049 udelay(1); 1050 1051 /* 1052 * configure the gasket: 1053 * RMII, 50 MHz, no loopback, no echo 1054 * MII, 25 MHz, no loopback, no echo 1055 */ 1056 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 1057 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII; 1058 if (ndev->phydev && ndev->phydev->speed == SPEED_10) 1059 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M; 1060 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR); 1061 1062 /* re-enable the gasket */ 1063 writel(2, fep->hwp + FEC_MIIGSK_ENR); 1064 } 1065 #endif 1066 } 1067 1068 #if !defined(CONFIG_M5272) 1069 /* enable pause frame*/ 1070 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) || 1071 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) && 1072 ndev->phydev && ndev->phydev->pause)) { 1073 rcntl |= FEC_ENET_FCE; 1074 1075 /* set FIFO threshold parameter to reduce overrun */ 1076 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM); 1077 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL); 1078 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM); 1079 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL); 1080 1081 /* OPD */ 1082 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD); 1083 } else { 1084 rcntl &= ~FEC_ENET_FCE; 1085 } 1086 #endif /* !defined(CONFIG_M5272) */ 1087 1088 writel(rcntl, fep->hwp + FEC_R_CNTRL); 1089 1090 /* Setup multicast filter. */ 1091 set_multicast_list(ndev); 1092 #ifndef CONFIG_M5272 1093 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); 1094 writel(0, fep->hwp + FEC_HASH_TABLE_LOW); 1095 #endif 1096 1097 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 1098 /* enable ENET endian swap */ 1099 ecntl |= (1 << 8); 1100 /* enable ENET store and forward mode */ 1101 writel(1 << 8, fep->hwp + FEC_X_WMRK); 1102 } 1103 1104 if (fep->bufdesc_ex) 1105 ecntl |= (1 << 4); 1106 1107 #ifndef CONFIG_M5272 1108 /* Enable the MIB statistic event counters */ 1109 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT); 1110 #endif 1111 1112 /* And last, enable the transmit and receive processing */ 1113 writel(ecntl, fep->hwp + FEC_ECNTRL); 1114 fec_enet_active_rxring(ndev); 1115 1116 if (fep->bufdesc_ex) 1117 fec_ptp_start_cyclecounter(ndev); 1118 1119 /* Enable interrupts we wish to service */ 1120 if (fep->link) 1121 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1122 else 1123 writel(0, fep->hwp + FEC_IMASK); 1124 1125 /* Init the interrupt coalescing */ 1126 fec_enet_itr_coal_init(ndev); 1127 1128 } 1129 1130 static void fec_enet_stop_mode(struct fec_enet_private *fep, bool enabled) 1131 { 1132 struct fec_platform_data *pdata = fep->pdev->dev.platform_data; 1133 struct fec_stop_mode_gpr *stop_gpr = &fep->stop_gpr; 1134 1135 if (stop_gpr->gpr) { 1136 if (enabled) 1137 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg, 1138 BIT(stop_gpr->bit), 1139 BIT(stop_gpr->bit)); 1140 else 1141 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg, 1142 BIT(stop_gpr->bit), 0); 1143 } else if (pdata && pdata->sleep_mode_enable) { 1144 pdata->sleep_mode_enable(enabled); 1145 } 1146 } 1147 1148 static void 1149 fec_stop(struct net_device *ndev) 1150 { 1151 struct fec_enet_private *fep = netdev_priv(ndev); 1152 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8); 1153 u32 val; 1154 1155 /* We cannot expect a graceful transmit stop without link !!! */ 1156 if (fep->link) { 1157 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ 1158 udelay(10); 1159 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) 1160 netdev_err(ndev, "Graceful transmit stop did not complete!\n"); 1161 } 1162 1163 /* Whack a reset. We should wait for this. 1164 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC 1165 * instead of reset MAC itself. 1166 */ 1167 if (!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1168 if (fep->quirks & FEC_QUIRK_HAS_AVB) { 1169 writel(0, fep->hwp + FEC_ECNTRL); 1170 } else { 1171 writel(1, fep->hwp + FEC_ECNTRL); 1172 udelay(10); 1173 } 1174 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1175 } else { 1176 writel(FEC_DEFAULT_IMASK | FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK); 1177 val = readl(fep->hwp + FEC_ECNTRL); 1178 val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP); 1179 writel(val, fep->hwp + FEC_ECNTRL); 1180 fec_enet_stop_mode(fep, true); 1181 } 1182 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1183 1184 /* We have to keep ENET enabled to have MII interrupt stay working */ 1185 if (fep->quirks & FEC_QUIRK_ENET_MAC && 1186 !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1187 writel(2, fep->hwp + FEC_ECNTRL); 1188 writel(rmii_mode, fep->hwp + FEC_R_CNTRL); 1189 } 1190 } 1191 1192 1193 static void 1194 fec_timeout(struct net_device *ndev, unsigned int txqueue) 1195 { 1196 struct fec_enet_private *fep = netdev_priv(ndev); 1197 1198 fec_dump(ndev); 1199 1200 ndev->stats.tx_errors++; 1201 1202 schedule_work(&fep->tx_timeout_work); 1203 } 1204 1205 static void fec_enet_timeout_work(struct work_struct *work) 1206 { 1207 struct fec_enet_private *fep = 1208 container_of(work, struct fec_enet_private, tx_timeout_work); 1209 struct net_device *ndev = fep->netdev; 1210 1211 rtnl_lock(); 1212 if (netif_device_present(ndev) || netif_running(ndev)) { 1213 napi_disable(&fep->napi); 1214 netif_tx_lock_bh(ndev); 1215 fec_restart(ndev); 1216 netif_tx_wake_all_queues(ndev); 1217 netif_tx_unlock_bh(ndev); 1218 napi_enable(&fep->napi); 1219 } 1220 rtnl_unlock(); 1221 } 1222 1223 static void 1224 fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts, 1225 struct skb_shared_hwtstamps *hwtstamps) 1226 { 1227 unsigned long flags; 1228 u64 ns; 1229 1230 spin_lock_irqsave(&fep->tmreg_lock, flags); 1231 ns = timecounter_cyc2time(&fep->tc, ts); 1232 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 1233 1234 memset(hwtstamps, 0, sizeof(*hwtstamps)); 1235 hwtstamps->hwtstamp = ns_to_ktime(ns); 1236 } 1237 1238 static void 1239 fec_enet_tx_queue(struct net_device *ndev, u16 queue_id) 1240 { 1241 struct fec_enet_private *fep; 1242 struct bufdesc *bdp; 1243 unsigned short status; 1244 struct sk_buff *skb; 1245 struct fec_enet_priv_tx_q *txq; 1246 struct netdev_queue *nq; 1247 int index = 0; 1248 int entries_free; 1249 1250 fep = netdev_priv(ndev); 1251 1252 txq = fep->tx_queue[queue_id]; 1253 /* get next bdp of dirty_tx */ 1254 nq = netdev_get_tx_queue(ndev, queue_id); 1255 bdp = txq->dirty_tx; 1256 1257 /* get next bdp of dirty_tx */ 1258 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1259 1260 while (bdp != READ_ONCE(txq->bd.cur)) { 1261 /* Order the load of bd.cur and cbd_sc */ 1262 rmb(); 1263 status = fec16_to_cpu(READ_ONCE(bdp->cbd_sc)); 1264 if (status & BD_ENET_TX_READY) 1265 break; 1266 1267 index = fec_enet_get_bd_index(bdp, &txq->bd); 1268 1269 skb = txq->tx_skbuff[index]; 1270 txq->tx_skbuff[index] = NULL; 1271 if (!IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr))) 1272 dma_unmap_single(&fep->pdev->dev, 1273 fec32_to_cpu(bdp->cbd_bufaddr), 1274 fec16_to_cpu(bdp->cbd_datlen), 1275 DMA_TO_DEVICE); 1276 bdp->cbd_bufaddr = cpu_to_fec32(0); 1277 if (!skb) 1278 goto skb_done; 1279 1280 /* Check for errors. */ 1281 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | 1282 BD_ENET_TX_RL | BD_ENET_TX_UN | 1283 BD_ENET_TX_CSL)) { 1284 ndev->stats.tx_errors++; 1285 if (status & BD_ENET_TX_HB) /* No heartbeat */ 1286 ndev->stats.tx_heartbeat_errors++; 1287 if (status & BD_ENET_TX_LC) /* Late collision */ 1288 ndev->stats.tx_window_errors++; 1289 if (status & BD_ENET_TX_RL) /* Retrans limit */ 1290 ndev->stats.tx_aborted_errors++; 1291 if (status & BD_ENET_TX_UN) /* Underrun */ 1292 ndev->stats.tx_fifo_errors++; 1293 if (status & BD_ENET_TX_CSL) /* Carrier lost */ 1294 ndev->stats.tx_carrier_errors++; 1295 } else { 1296 ndev->stats.tx_packets++; 1297 ndev->stats.tx_bytes += skb->len; 1298 } 1299 1300 /* NOTE: SKBTX_IN_PROGRESS being set does not imply it's we who 1301 * are to time stamp the packet, so we still need to check time 1302 * stamping enabled flag. 1303 */ 1304 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS && 1305 fep->hwts_tx_en) && 1306 fep->bufdesc_ex) { 1307 struct skb_shared_hwtstamps shhwtstamps; 1308 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1309 1310 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), &shhwtstamps); 1311 skb_tstamp_tx(skb, &shhwtstamps); 1312 } 1313 1314 /* Deferred means some collisions occurred during transmit, 1315 * but we eventually sent the packet OK. 1316 */ 1317 if (status & BD_ENET_TX_DEF) 1318 ndev->stats.collisions++; 1319 1320 /* Free the sk buffer associated with this last transmit */ 1321 dev_kfree_skb_any(skb); 1322 skb_done: 1323 /* Make sure the update to bdp and tx_skbuff are performed 1324 * before dirty_tx 1325 */ 1326 wmb(); 1327 txq->dirty_tx = bdp; 1328 1329 /* Update pointer to next buffer descriptor to be transmitted */ 1330 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1331 1332 /* Since we have freed up a buffer, the ring is no longer full 1333 */ 1334 if (netif_tx_queue_stopped(nq)) { 1335 entries_free = fec_enet_get_free_txdesc_num(txq); 1336 if (entries_free >= txq->tx_wake_threshold) 1337 netif_tx_wake_queue(nq); 1338 } 1339 } 1340 1341 /* ERR006358: Keep the transmitter going */ 1342 if (bdp != txq->bd.cur && 1343 readl(txq->bd.reg_desc_active) == 0) 1344 writel(0, txq->bd.reg_desc_active); 1345 } 1346 1347 static void fec_enet_tx(struct net_device *ndev) 1348 { 1349 struct fec_enet_private *fep = netdev_priv(ndev); 1350 int i; 1351 1352 /* Make sure that AVB queues are processed first. */ 1353 for (i = fep->num_tx_queues - 1; i >= 0; i--) 1354 fec_enet_tx_queue(ndev, i); 1355 } 1356 1357 static int 1358 fec_enet_new_rxbdp(struct net_device *ndev, struct bufdesc *bdp, struct sk_buff *skb) 1359 { 1360 struct fec_enet_private *fep = netdev_priv(ndev); 1361 int off; 1362 1363 off = ((unsigned long)skb->data) & fep->rx_align; 1364 if (off) 1365 skb_reserve(skb, fep->rx_align + 1 - off); 1366 1367 bdp->cbd_bufaddr = cpu_to_fec32(dma_map_single(&fep->pdev->dev, skb->data, FEC_ENET_RX_FRSIZE - fep->rx_align, DMA_FROM_DEVICE)); 1368 if (dma_mapping_error(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr))) { 1369 if (net_ratelimit()) 1370 netdev_err(ndev, "Rx DMA memory map failed\n"); 1371 return -ENOMEM; 1372 } 1373 1374 return 0; 1375 } 1376 1377 static bool fec_enet_copybreak(struct net_device *ndev, struct sk_buff **skb, 1378 struct bufdesc *bdp, u32 length, bool swap) 1379 { 1380 struct fec_enet_private *fep = netdev_priv(ndev); 1381 struct sk_buff *new_skb; 1382 1383 if (length > fep->rx_copybreak) 1384 return false; 1385 1386 new_skb = netdev_alloc_skb(ndev, length); 1387 if (!new_skb) 1388 return false; 1389 1390 dma_sync_single_for_cpu(&fep->pdev->dev, 1391 fec32_to_cpu(bdp->cbd_bufaddr), 1392 FEC_ENET_RX_FRSIZE - fep->rx_align, 1393 DMA_FROM_DEVICE); 1394 if (!swap) 1395 memcpy(new_skb->data, (*skb)->data, length); 1396 else 1397 swap_buffer2(new_skb->data, (*skb)->data, length); 1398 *skb = new_skb; 1399 1400 return true; 1401 } 1402 1403 /* During a receive, the bd_rx.cur points to the current incoming buffer. 1404 * When we update through the ring, if the next incoming buffer has 1405 * not been given to the system, we just set the empty indicator, 1406 * effectively tossing the packet. 1407 */ 1408 static int 1409 fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id) 1410 { 1411 struct fec_enet_private *fep = netdev_priv(ndev); 1412 struct fec_enet_priv_rx_q *rxq; 1413 struct bufdesc *bdp; 1414 unsigned short status; 1415 struct sk_buff *skb_new = NULL; 1416 struct sk_buff *skb; 1417 ushort pkt_len; 1418 __u8 *data; 1419 int pkt_received = 0; 1420 struct bufdesc_ex *ebdp = NULL; 1421 bool vlan_packet_rcvd = false; 1422 u16 vlan_tag; 1423 int index = 0; 1424 bool is_copybreak; 1425 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME; 1426 1427 #ifdef CONFIG_M532x 1428 flush_cache_all(); 1429 #endif 1430 rxq = fep->rx_queue[queue_id]; 1431 1432 /* First, grab all of the stats for the incoming packet. 1433 * These get messed up if we get called due to a busy condition. 1434 */ 1435 bdp = rxq->bd.cur; 1436 1437 while (!((status = fec16_to_cpu(bdp->cbd_sc)) & BD_ENET_RX_EMPTY)) { 1438 1439 if (pkt_received >= budget) 1440 break; 1441 pkt_received++; 1442 1443 writel(FEC_ENET_RXF, fep->hwp + FEC_IEVENT); 1444 1445 /* Check for errors. */ 1446 status ^= BD_ENET_RX_LAST; 1447 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | 1448 BD_ENET_RX_CR | BD_ENET_RX_OV | BD_ENET_RX_LAST | 1449 BD_ENET_RX_CL)) { 1450 ndev->stats.rx_errors++; 1451 if (status & BD_ENET_RX_OV) { 1452 /* FIFO overrun */ 1453 ndev->stats.rx_fifo_errors++; 1454 goto rx_processing_done; 1455 } 1456 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH 1457 | BD_ENET_RX_LAST)) { 1458 /* Frame too long or too short. */ 1459 ndev->stats.rx_length_errors++; 1460 if (status & BD_ENET_RX_LAST) 1461 netdev_err(ndev, "rcv is not +last\n"); 1462 } 1463 if (status & BD_ENET_RX_CR) /* CRC Error */ 1464 ndev->stats.rx_crc_errors++; 1465 /* Report late collisions as a frame error. */ 1466 if (status & (BD_ENET_RX_NO | BD_ENET_RX_CL)) 1467 ndev->stats.rx_frame_errors++; 1468 goto rx_processing_done; 1469 } 1470 1471 /* Process the incoming frame. */ 1472 ndev->stats.rx_packets++; 1473 pkt_len = fec16_to_cpu(bdp->cbd_datlen); 1474 ndev->stats.rx_bytes += pkt_len; 1475 1476 index = fec_enet_get_bd_index(bdp, &rxq->bd); 1477 skb = rxq->rx_skbuff[index]; 1478 1479 /* The packet length includes FCS, but we don't want to 1480 * include that when passing upstream as it messes up 1481 * bridging applications. 1482 */ 1483 is_copybreak = fec_enet_copybreak(ndev, &skb, bdp, pkt_len - 4, 1484 need_swap); 1485 if (!is_copybreak) { 1486 skb_new = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE); 1487 if (unlikely(!skb_new)) { 1488 ndev->stats.rx_dropped++; 1489 goto rx_processing_done; 1490 } 1491 dma_unmap_single(&fep->pdev->dev, 1492 fec32_to_cpu(bdp->cbd_bufaddr), 1493 FEC_ENET_RX_FRSIZE - fep->rx_align, 1494 DMA_FROM_DEVICE); 1495 } 1496 1497 prefetch(skb->data - NET_IP_ALIGN); 1498 skb_put(skb, pkt_len - 4); 1499 data = skb->data; 1500 1501 if (!is_copybreak && need_swap) 1502 swap_buffer(data, pkt_len); 1503 1504 #if !defined(CONFIG_M5272) 1505 if (fep->quirks & FEC_QUIRK_HAS_RACC) 1506 data = skb_pull_inline(skb, 2); 1507 #endif 1508 1509 /* Extract the enhanced buffer descriptor */ 1510 ebdp = NULL; 1511 if (fep->bufdesc_ex) 1512 ebdp = (struct bufdesc_ex *)bdp; 1513 1514 /* If this is a VLAN packet remove the VLAN Tag */ 1515 vlan_packet_rcvd = false; 1516 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) && 1517 fep->bufdesc_ex && 1518 (ebdp->cbd_esc & cpu_to_fec32(BD_ENET_RX_VLAN))) { 1519 /* Push and remove the vlan tag */ 1520 struct vlan_hdr *vlan_header = 1521 (struct vlan_hdr *) (data + ETH_HLEN); 1522 vlan_tag = ntohs(vlan_header->h_vlan_TCI); 1523 1524 vlan_packet_rcvd = true; 1525 1526 memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2); 1527 skb_pull(skb, VLAN_HLEN); 1528 } 1529 1530 skb->protocol = eth_type_trans(skb, ndev); 1531 1532 /* Get receive timestamp from the skb */ 1533 if (fep->hwts_rx_en && fep->bufdesc_ex) 1534 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), 1535 skb_hwtstamps(skb)); 1536 1537 if (fep->bufdesc_ex && 1538 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) { 1539 if (!(ebdp->cbd_esc & cpu_to_fec32(FLAG_RX_CSUM_ERROR))) { 1540 /* don't check it */ 1541 skb->ip_summed = CHECKSUM_UNNECESSARY; 1542 } else { 1543 skb_checksum_none_assert(skb); 1544 } 1545 } 1546 1547 /* Handle received VLAN packets */ 1548 if (vlan_packet_rcvd) 1549 __vlan_hwaccel_put_tag(skb, 1550 htons(ETH_P_8021Q), 1551 vlan_tag); 1552 1553 skb_record_rx_queue(skb, queue_id); 1554 napi_gro_receive(&fep->napi, skb); 1555 1556 if (is_copybreak) { 1557 dma_sync_single_for_device(&fep->pdev->dev, 1558 fec32_to_cpu(bdp->cbd_bufaddr), 1559 FEC_ENET_RX_FRSIZE - fep->rx_align, 1560 DMA_FROM_DEVICE); 1561 } else { 1562 rxq->rx_skbuff[index] = skb_new; 1563 fec_enet_new_rxbdp(ndev, bdp, skb_new); 1564 } 1565 1566 rx_processing_done: 1567 /* Clear the status flags for this buffer */ 1568 status &= ~BD_ENET_RX_STATS; 1569 1570 /* Mark the buffer empty */ 1571 status |= BD_ENET_RX_EMPTY; 1572 1573 if (fep->bufdesc_ex) { 1574 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1575 1576 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); 1577 ebdp->cbd_prot = 0; 1578 ebdp->cbd_bdu = 0; 1579 } 1580 /* Make sure the updates to rest of the descriptor are 1581 * performed before transferring ownership. 1582 */ 1583 wmb(); 1584 bdp->cbd_sc = cpu_to_fec16(status); 1585 1586 /* Update BD pointer to next entry */ 1587 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 1588 1589 /* Doing this here will keep the FEC running while we process 1590 * incoming frames. On a heavily loaded network, we should be 1591 * able to keep up at the expense of system resources. 1592 */ 1593 writel(0, rxq->bd.reg_desc_active); 1594 } 1595 rxq->bd.cur = bdp; 1596 return pkt_received; 1597 } 1598 1599 static int fec_enet_rx(struct net_device *ndev, int budget) 1600 { 1601 struct fec_enet_private *fep = netdev_priv(ndev); 1602 int i, done = 0; 1603 1604 /* Make sure that AVB queues are processed first. */ 1605 for (i = fep->num_rx_queues - 1; i >= 0; i--) 1606 done += fec_enet_rx_queue(ndev, budget - done, i); 1607 1608 return done; 1609 } 1610 1611 static bool fec_enet_collect_events(struct fec_enet_private *fep) 1612 { 1613 uint int_events; 1614 1615 int_events = readl(fep->hwp + FEC_IEVENT); 1616 1617 /* Don't clear MDIO events, we poll for those */ 1618 int_events &= ~FEC_ENET_MII; 1619 1620 writel(int_events, fep->hwp + FEC_IEVENT); 1621 1622 return int_events != 0; 1623 } 1624 1625 static irqreturn_t 1626 fec_enet_interrupt(int irq, void *dev_id) 1627 { 1628 struct net_device *ndev = dev_id; 1629 struct fec_enet_private *fep = netdev_priv(ndev); 1630 irqreturn_t ret = IRQ_NONE; 1631 1632 if (fec_enet_collect_events(fep) && fep->link) { 1633 ret = IRQ_HANDLED; 1634 1635 if (napi_schedule_prep(&fep->napi)) { 1636 /* Disable interrupts */ 1637 writel(0, fep->hwp + FEC_IMASK); 1638 __napi_schedule(&fep->napi); 1639 } 1640 } 1641 1642 return ret; 1643 } 1644 1645 static int fec_enet_rx_napi(struct napi_struct *napi, int budget) 1646 { 1647 struct net_device *ndev = napi->dev; 1648 struct fec_enet_private *fep = netdev_priv(ndev); 1649 int done = 0; 1650 1651 do { 1652 done += fec_enet_rx(ndev, budget - done); 1653 fec_enet_tx(ndev); 1654 } while ((done < budget) && fec_enet_collect_events(fep)); 1655 1656 if (done < budget) { 1657 napi_complete_done(napi, done); 1658 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1659 } 1660 1661 return done; 1662 } 1663 1664 /* ------------------------------------------------------------------------- */ 1665 static int fec_get_mac(struct net_device *ndev) 1666 { 1667 struct fec_enet_private *fep = netdev_priv(ndev); 1668 unsigned char *iap, tmpaddr[ETH_ALEN]; 1669 int ret; 1670 1671 /* 1672 * try to get mac address in following order: 1673 * 1674 * 1) module parameter via kernel command line in form 1675 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0 1676 */ 1677 iap = macaddr; 1678 1679 /* 1680 * 2) from device tree data 1681 */ 1682 if (!is_valid_ether_addr(iap)) { 1683 struct device_node *np = fep->pdev->dev.of_node; 1684 if (np) { 1685 ret = of_get_mac_address(np, tmpaddr); 1686 if (!ret) 1687 iap = tmpaddr; 1688 else if (ret == -EPROBE_DEFER) 1689 return ret; 1690 } 1691 } 1692 1693 /* 1694 * 3) from flash or fuse (via platform data) 1695 */ 1696 if (!is_valid_ether_addr(iap)) { 1697 #ifdef CONFIG_M5272 1698 if (FEC_FLASHMAC) 1699 iap = (unsigned char *)FEC_FLASHMAC; 1700 #else 1701 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev); 1702 1703 if (pdata) 1704 iap = (unsigned char *)&pdata->mac; 1705 #endif 1706 } 1707 1708 /* 1709 * 4) FEC mac registers set by bootloader 1710 */ 1711 if (!is_valid_ether_addr(iap)) { 1712 *((__be32 *) &tmpaddr[0]) = 1713 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW)); 1714 *((__be16 *) &tmpaddr[4]) = 1715 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16); 1716 iap = &tmpaddr[0]; 1717 } 1718 1719 /* 1720 * 5) random mac address 1721 */ 1722 if (!is_valid_ether_addr(iap)) { 1723 /* Report it and use a random ethernet address instead */ 1724 dev_err(&fep->pdev->dev, "Invalid MAC address: %pM\n", iap); 1725 eth_hw_addr_random(ndev); 1726 dev_info(&fep->pdev->dev, "Using random MAC address: %pM\n", 1727 ndev->dev_addr); 1728 return 0; 1729 } 1730 1731 memcpy(ndev->dev_addr, iap, ETH_ALEN); 1732 1733 /* Adjust MAC if using macaddr */ 1734 if (iap == macaddr) 1735 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id; 1736 1737 return 0; 1738 } 1739 1740 /* ------------------------------------------------------------------------- */ 1741 1742 /* 1743 * Phy section 1744 */ 1745 static void fec_enet_adjust_link(struct net_device *ndev) 1746 { 1747 struct fec_enet_private *fep = netdev_priv(ndev); 1748 struct phy_device *phy_dev = ndev->phydev; 1749 int status_change = 0; 1750 1751 /* 1752 * If the netdev is down, or is going down, we're not interested 1753 * in link state events, so just mark our idea of the link as down 1754 * and ignore the event. 1755 */ 1756 if (!netif_running(ndev) || !netif_device_present(ndev)) { 1757 fep->link = 0; 1758 } else if (phy_dev->link) { 1759 if (!fep->link) { 1760 fep->link = phy_dev->link; 1761 status_change = 1; 1762 } 1763 1764 if (fep->full_duplex != phy_dev->duplex) { 1765 fep->full_duplex = phy_dev->duplex; 1766 status_change = 1; 1767 } 1768 1769 if (phy_dev->speed != fep->speed) { 1770 fep->speed = phy_dev->speed; 1771 status_change = 1; 1772 } 1773 1774 /* if any of the above changed restart the FEC */ 1775 if (status_change) { 1776 napi_disable(&fep->napi); 1777 netif_tx_lock_bh(ndev); 1778 fec_restart(ndev); 1779 netif_tx_wake_all_queues(ndev); 1780 netif_tx_unlock_bh(ndev); 1781 napi_enable(&fep->napi); 1782 } 1783 } else { 1784 if (fep->link) { 1785 napi_disable(&fep->napi); 1786 netif_tx_lock_bh(ndev); 1787 fec_stop(ndev); 1788 netif_tx_unlock_bh(ndev); 1789 napi_enable(&fep->napi); 1790 fep->link = phy_dev->link; 1791 status_change = 1; 1792 } 1793 } 1794 1795 if (status_change) 1796 phy_print_status(phy_dev); 1797 } 1798 1799 static int fec_enet_mdio_wait(struct fec_enet_private *fep) 1800 { 1801 uint ievent; 1802 int ret; 1803 1804 ret = readl_poll_timeout_atomic(fep->hwp + FEC_IEVENT, ievent, 1805 ievent & FEC_ENET_MII, 2, 30000); 1806 1807 if (!ret) 1808 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); 1809 1810 return ret; 1811 } 1812 1813 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) 1814 { 1815 struct fec_enet_private *fep = bus->priv; 1816 struct device *dev = &fep->pdev->dev; 1817 int ret = 0, frame_start, frame_addr, frame_op; 1818 bool is_c45 = !!(regnum & MII_ADDR_C45); 1819 1820 ret = pm_runtime_resume_and_get(dev); 1821 if (ret < 0) 1822 return ret; 1823 1824 if (is_c45) { 1825 frame_start = FEC_MMFR_ST_C45; 1826 1827 /* write address */ 1828 frame_addr = (regnum >> 16); 1829 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE | 1830 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 1831 FEC_MMFR_TA | (regnum & 0xFFFF), 1832 fep->hwp + FEC_MII_DATA); 1833 1834 /* wait for end of transfer */ 1835 ret = fec_enet_mdio_wait(fep); 1836 if (ret) { 1837 netdev_err(fep->netdev, "MDIO address write timeout\n"); 1838 goto out; 1839 } 1840 1841 frame_op = FEC_MMFR_OP_READ_C45; 1842 1843 } else { 1844 /* C22 read */ 1845 frame_op = FEC_MMFR_OP_READ; 1846 frame_start = FEC_MMFR_ST; 1847 frame_addr = regnum; 1848 } 1849 1850 /* start a read op */ 1851 writel(frame_start | frame_op | 1852 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 1853 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); 1854 1855 /* wait for end of transfer */ 1856 ret = fec_enet_mdio_wait(fep); 1857 if (ret) { 1858 netdev_err(fep->netdev, "MDIO read timeout\n"); 1859 goto out; 1860 } 1861 1862 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); 1863 1864 out: 1865 pm_runtime_mark_last_busy(dev); 1866 pm_runtime_put_autosuspend(dev); 1867 1868 return ret; 1869 } 1870 1871 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, 1872 u16 value) 1873 { 1874 struct fec_enet_private *fep = bus->priv; 1875 struct device *dev = &fep->pdev->dev; 1876 int ret, frame_start, frame_addr; 1877 bool is_c45 = !!(regnum & MII_ADDR_C45); 1878 1879 ret = pm_runtime_resume_and_get(dev); 1880 if (ret < 0) 1881 return ret; 1882 1883 if (is_c45) { 1884 frame_start = FEC_MMFR_ST_C45; 1885 1886 /* write address */ 1887 frame_addr = (regnum >> 16); 1888 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE | 1889 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 1890 FEC_MMFR_TA | (regnum & 0xFFFF), 1891 fep->hwp + FEC_MII_DATA); 1892 1893 /* wait for end of transfer */ 1894 ret = fec_enet_mdio_wait(fep); 1895 if (ret) { 1896 netdev_err(fep->netdev, "MDIO address write timeout\n"); 1897 goto out; 1898 } 1899 } else { 1900 /* C22 write */ 1901 frame_start = FEC_MMFR_ST; 1902 frame_addr = regnum; 1903 } 1904 1905 /* start a write op */ 1906 writel(frame_start | FEC_MMFR_OP_WRITE | 1907 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 1908 FEC_MMFR_TA | FEC_MMFR_DATA(value), 1909 fep->hwp + FEC_MII_DATA); 1910 1911 /* wait for end of transfer */ 1912 ret = fec_enet_mdio_wait(fep); 1913 if (ret) 1914 netdev_err(fep->netdev, "MDIO write timeout\n"); 1915 1916 out: 1917 pm_runtime_mark_last_busy(dev); 1918 pm_runtime_put_autosuspend(dev); 1919 1920 return ret; 1921 } 1922 1923 static void fec_enet_phy_reset_after_clk_enable(struct net_device *ndev) 1924 { 1925 struct fec_enet_private *fep = netdev_priv(ndev); 1926 struct phy_device *phy_dev = ndev->phydev; 1927 1928 if (phy_dev) { 1929 phy_reset_after_clk_enable(phy_dev); 1930 } else if (fep->phy_node) { 1931 /* 1932 * If the PHY still is not bound to the MAC, but there is 1933 * OF PHY node and a matching PHY device instance already, 1934 * use the OF PHY node to obtain the PHY device instance, 1935 * and then use that PHY device instance when triggering 1936 * the PHY reset. 1937 */ 1938 phy_dev = of_phy_find_device(fep->phy_node); 1939 phy_reset_after_clk_enable(phy_dev); 1940 put_device(&phy_dev->mdio.dev); 1941 } 1942 } 1943 1944 static int fec_enet_clk_enable(struct net_device *ndev, bool enable) 1945 { 1946 struct fec_enet_private *fep = netdev_priv(ndev); 1947 int ret; 1948 1949 if (enable) { 1950 ret = clk_prepare_enable(fep->clk_enet_out); 1951 if (ret) 1952 return ret; 1953 1954 if (fep->clk_ptp) { 1955 mutex_lock(&fep->ptp_clk_mutex); 1956 ret = clk_prepare_enable(fep->clk_ptp); 1957 if (ret) { 1958 mutex_unlock(&fep->ptp_clk_mutex); 1959 goto failed_clk_ptp; 1960 } else { 1961 fep->ptp_clk_on = true; 1962 } 1963 mutex_unlock(&fep->ptp_clk_mutex); 1964 } 1965 1966 ret = clk_prepare_enable(fep->clk_ref); 1967 if (ret) 1968 goto failed_clk_ref; 1969 1970 fec_enet_phy_reset_after_clk_enable(ndev); 1971 } else { 1972 clk_disable_unprepare(fep->clk_enet_out); 1973 if (fep->clk_ptp) { 1974 mutex_lock(&fep->ptp_clk_mutex); 1975 clk_disable_unprepare(fep->clk_ptp); 1976 fep->ptp_clk_on = false; 1977 mutex_unlock(&fep->ptp_clk_mutex); 1978 } 1979 clk_disable_unprepare(fep->clk_ref); 1980 } 1981 1982 return 0; 1983 1984 failed_clk_ref: 1985 if (fep->clk_ptp) { 1986 mutex_lock(&fep->ptp_clk_mutex); 1987 clk_disable_unprepare(fep->clk_ptp); 1988 fep->ptp_clk_on = false; 1989 mutex_unlock(&fep->ptp_clk_mutex); 1990 } 1991 failed_clk_ptp: 1992 clk_disable_unprepare(fep->clk_enet_out); 1993 1994 return ret; 1995 } 1996 1997 static int fec_enet_mii_probe(struct net_device *ndev) 1998 { 1999 struct fec_enet_private *fep = netdev_priv(ndev); 2000 struct phy_device *phy_dev = NULL; 2001 char mdio_bus_id[MII_BUS_ID_SIZE]; 2002 char phy_name[MII_BUS_ID_SIZE + 3]; 2003 int phy_id; 2004 int dev_id = fep->dev_id; 2005 2006 if (fep->phy_node) { 2007 phy_dev = of_phy_connect(ndev, fep->phy_node, 2008 &fec_enet_adjust_link, 0, 2009 fep->phy_interface); 2010 if (!phy_dev) { 2011 netdev_err(ndev, "Unable to connect to phy\n"); 2012 return -ENODEV; 2013 } 2014 } else { 2015 /* check for attached phy */ 2016 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) { 2017 if (!mdiobus_is_registered_device(fep->mii_bus, phy_id)) 2018 continue; 2019 if (dev_id--) 2020 continue; 2021 strlcpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE); 2022 break; 2023 } 2024 2025 if (phy_id >= PHY_MAX_ADDR) { 2026 netdev_info(ndev, "no PHY, assuming direct connection to switch\n"); 2027 strlcpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); 2028 phy_id = 0; 2029 } 2030 2031 snprintf(phy_name, sizeof(phy_name), 2032 PHY_ID_FMT, mdio_bus_id, phy_id); 2033 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, 2034 fep->phy_interface); 2035 } 2036 2037 if (IS_ERR(phy_dev)) { 2038 netdev_err(ndev, "could not attach to PHY\n"); 2039 return PTR_ERR(phy_dev); 2040 } 2041 2042 /* mask with MAC supported features */ 2043 if (fep->quirks & FEC_QUIRK_HAS_GBIT) { 2044 phy_set_max_speed(phy_dev, 1000); 2045 phy_remove_link_mode(phy_dev, 2046 ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 2047 #if !defined(CONFIG_M5272) 2048 phy_support_sym_pause(phy_dev); 2049 #endif 2050 } 2051 else 2052 phy_set_max_speed(phy_dev, 100); 2053 2054 fep->link = 0; 2055 fep->full_duplex = 0; 2056 2057 phy_dev->mac_managed_pm = 1; 2058 2059 phy_attached_info(phy_dev); 2060 2061 return 0; 2062 } 2063 2064 static int fec_enet_mii_init(struct platform_device *pdev) 2065 { 2066 static struct mii_bus *fec0_mii_bus; 2067 struct net_device *ndev = platform_get_drvdata(pdev); 2068 struct fec_enet_private *fep = netdev_priv(ndev); 2069 bool suppress_preamble = false; 2070 struct device_node *node; 2071 int err = -ENXIO; 2072 u32 mii_speed, holdtime; 2073 u32 bus_freq; 2074 2075 /* 2076 * The i.MX28 dual fec interfaces are not equal. 2077 * Here are the differences: 2078 * 2079 * - fec0 supports MII & RMII modes while fec1 only supports RMII 2080 * - fec0 acts as the 1588 time master while fec1 is slave 2081 * - external phys can only be configured by fec0 2082 * 2083 * That is to say fec1 can not work independently. It only works 2084 * when fec0 is working. The reason behind this design is that the 2085 * second interface is added primarily for Switch mode. 2086 * 2087 * Because of the last point above, both phys are attached on fec0 2088 * mdio interface in board design, and need to be configured by 2089 * fec0 mii_bus. 2090 */ 2091 if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) { 2092 /* fec1 uses fec0 mii_bus */ 2093 if (mii_cnt && fec0_mii_bus) { 2094 fep->mii_bus = fec0_mii_bus; 2095 mii_cnt++; 2096 return 0; 2097 } 2098 return -ENOENT; 2099 } 2100 2101 bus_freq = 2500000; /* 2.5MHz by default */ 2102 node = of_get_child_by_name(pdev->dev.of_node, "mdio"); 2103 if (node) { 2104 of_property_read_u32(node, "clock-frequency", &bus_freq); 2105 suppress_preamble = of_property_read_bool(node, 2106 "suppress-preamble"); 2107 } 2108 2109 /* 2110 * Set MII speed (= clk_get_rate() / 2 * phy_speed) 2111 * 2112 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while 2113 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28 2114 * Reference Manual has an error on this, and gets fixed on i.MX6Q 2115 * document. 2116 */ 2117 mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), bus_freq * 2); 2118 if (fep->quirks & FEC_QUIRK_ENET_MAC) 2119 mii_speed--; 2120 if (mii_speed > 63) { 2121 dev_err(&pdev->dev, 2122 "fec clock (%lu) too fast to get right mii speed\n", 2123 clk_get_rate(fep->clk_ipg)); 2124 err = -EINVAL; 2125 goto err_out; 2126 } 2127 2128 /* 2129 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka 2130 * MII_SPEED) register that defines the MDIO output hold time. Earlier 2131 * versions are RAZ there, so just ignore the difference and write the 2132 * register always. 2133 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns. 2134 * HOLDTIME + 1 is the number of clk cycles the fec is holding the 2135 * output. 2136 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive). 2137 * Given that ceil(clkrate / 5000000) <= 64, the calculation for 2138 * holdtime cannot result in a value greater than 3. 2139 */ 2140 holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1; 2141 2142 fep->phy_speed = mii_speed << 1 | holdtime << 8; 2143 2144 if (suppress_preamble) 2145 fep->phy_speed |= BIT(7); 2146 2147 if (fep->quirks & FEC_QUIRK_CLEAR_SETUP_MII) { 2148 /* Clear MMFR to avoid to generate MII event by writing MSCR. 2149 * MII event generation condition: 2150 * - writing MSCR: 2151 * - mmfr[31:0]_not_zero & mscr[7:0]_is_zero & 2152 * mscr_reg_data_in[7:0] != 0 2153 * - writing MMFR: 2154 * - mscr[7:0]_not_zero 2155 */ 2156 writel(0, fep->hwp + FEC_MII_DATA); 2157 } 2158 2159 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 2160 2161 /* Clear any pending transaction complete indication */ 2162 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); 2163 2164 fep->mii_bus = mdiobus_alloc(); 2165 if (fep->mii_bus == NULL) { 2166 err = -ENOMEM; 2167 goto err_out; 2168 } 2169 2170 fep->mii_bus->name = "fec_enet_mii_bus"; 2171 fep->mii_bus->read = fec_enet_mdio_read; 2172 fep->mii_bus->write = fec_enet_mdio_write; 2173 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 2174 pdev->name, fep->dev_id + 1); 2175 fep->mii_bus->priv = fep; 2176 fep->mii_bus->parent = &pdev->dev; 2177 2178 err = of_mdiobus_register(fep->mii_bus, node); 2179 if (err) 2180 goto err_out_free_mdiobus; 2181 of_node_put(node); 2182 2183 mii_cnt++; 2184 2185 /* save fec0 mii_bus */ 2186 if (fep->quirks & FEC_QUIRK_SINGLE_MDIO) 2187 fec0_mii_bus = fep->mii_bus; 2188 2189 return 0; 2190 2191 err_out_free_mdiobus: 2192 mdiobus_free(fep->mii_bus); 2193 err_out: 2194 of_node_put(node); 2195 return err; 2196 } 2197 2198 static void fec_enet_mii_remove(struct fec_enet_private *fep) 2199 { 2200 if (--mii_cnt == 0) { 2201 mdiobus_unregister(fep->mii_bus); 2202 mdiobus_free(fep->mii_bus); 2203 } 2204 } 2205 2206 static void fec_enet_get_drvinfo(struct net_device *ndev, 2207 struct ethtool_drvinfo *info) 2208 { 2209 struct fec_enet_private *fep = netdev_priv(ndev); 2210 2211 strlcpy(info->driver, fep->pdev->dev.driver->name, 2212 sizeof(info->driver)); 2213 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info)); 2214 } 2215 2216 static int fec_enet_get_regs_len(struct net_device *ndev) 2217 { 2218 struct fec_enet_private *fep = netdev_priv(ndev); 2219 struct resource *r; 2220 int s = 0; 2221 2222 r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0); 2223 if (r) 2224 s = resource_size(r); 2225 2226 return s; 2227 } 2228 2229 /* List of registers that can be safety be read to dump them with ethtool */ 2230 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 2231 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \ 2232 defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST) 2233 static __u32 fec_enet_register_version = 2; 2234 static u32 fec_enet_register_offset[] = { 2235 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0, 2236 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL, 2237 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1, 2238 FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH, 2239 FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, 2240 FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1, 2241 FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2, 2242 FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0, 2243 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM, 2244 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2, 2245 FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1, 2246 FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME, 2247 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT, 2248 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG, 2249 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255, 2250 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047, 2251 RMON_T_P_GTE2048, RMON_T_OCTETS, 2252 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF, 2253 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE, 2254 IEEE_T_FDXFC, IEEE_T_OCTETS_OK, 2255 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN, 2256 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB, 2257 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255, 2258 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047, 2259 RMON_R_P_GTE2048, RMON_R_OCTETS, 2260 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR, 2261 IEEE_R_FDXFC, IEEE_R_OCTETS_OK 2262 }; 2263 #else 2264 static __u32 fec_enet_register_version = 1; 2265 static u32 fec_enet_register_offset[] = { 2266 FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0, 2267 FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0, 2268 FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED, 2269 FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL, 2270 FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, 2271 FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0, 2272 FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0, 2273 FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0, 2274 FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2 2275 }; 2276 #endif 2277 2278 static void fec_enet_get_regs(struct net_device *ndev, 2279 struct ethtool_regs *regs, void *regbuf) 2280 { 2281 struct fec_enet_private *fep = netdev_priv(ndev); 2282 u32 __iomem *theregs = (u32 __iomem *)fep->hwp; 2283 struct device *dev = &fep->pdev->dev; 2284 u32 *buf = (u32 *)regbuf; 2285 u32 i, off; 2286 int ret; 2287 2288 ret = pm_runtime_resume_and_get(dev); 2289 if (ret < 0) 2290 return; 2291 2292 regs->version = fec_enet_register_version; 2293 2294 memset(buf, 0, regs->len); 2295 2296 for (i = 0; i < ARRAY_SIZE(fec_enet_register_offset); i++) { 2297 off = fec_enet_register_offset[i]; 2298 2299 if ((off == FEC_R_BOUND || off == FEC_R_FSTART) && 2300 !(fep->quirks & FEC_QUIRK_HAS_FRREG)) 2301 continue; 2302 2303 off >>= 2; 2304 buf[off] = readl(&theregs[off]); 2305 } 2306 2307 pm_runtime_mark_last_busy(dev); 2308 pm_runtime_put_autosuspend(dev); 2309 } 2310 2311 static int fec_enet_get_ts_info(struct net_device *ndev, 2312 struct ethtool_ts_info *info) 2313 { 2314 struct fec_enet_private *fep = netdev_priv(ndev); 2315 2316 if (fep->bufdesc_ex) { 2317 2318 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 2319 SOF_TIMESTAMPING_RX_SOFTWARE | 2320 SOF_TIMESTAMPING_SOFTWARE | 2321 SOF_TIMESTAMPING_TX_HARDWARE | 2322 SOF_TIMESTAMPING_RX_HARDWARE | 2323 SOF_TIMESTAMPING_RAW_HARDWARE; 2324 if (fep->ptp_clock) 2325 info->phc_index = ptp_clock_index(fep->ptp_clock); 2326 else 2327 info->phc_index = -1; 2328 2329 info->tx_types = (1 << HWTSTAMP_TX_OFF) | 2330 (1 << HWTSTAMP_TX_ON); 2331 2332 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 2333 (1 << HWTSTAMP_FILTER_ALL); 2334 return 0; 2335 } else { 2336 return ethtool_op_get_ts_info(ndev, info); 2337 } 2338 } 2339 2340 #if !defined(CONFIG_M5272) 2341 2342 static void fec_enet_get_pauseparam(struct net_device *ndev, 2343 struct ethtool_pauseparam *pause) 2344 { 2345 struct fec_enet_private *fep = netdev_priv(ndev); 2346 2347 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0; 2348 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0; 2349 pause->rx_pause = pause->tx_pause; 2350 } 2351 2352 static int fec_enet_set_pauseparam(struct net_device *ndev, 2353 struct ethtool_pauseparam *pause) 2354 { 2355 struct fec_enet_private *fep = netdev_priv(ndev); 2356 2357 if (!ndev->phydev) 2358 return -ENODEV; 2359 2360 if (pause->tx_pause != pause->rx_pause) { 2361 netdev_info(ndev, 2362 "hardware only support enable/disable both tx and rx"); 2363 return -EINVAL; 2364 } 2365 2366 fep->pause_flag = 0; 2367 2368 /* tx pause must be same as rx pause */ 2369 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0; 2370 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0; 2371 2372 phy_set_sym_pause(ndev->phydev, pause->rx_pause, pause->tx_pause, 2373 pause->autoneg); 2374 2375 if (pause->autoneg) { 2376 if (netif_running(ndev)) 2377 fec_stop(ndev); 2378 phy_start_aneg(ndev->phydev); 2379 } 2380 if (netif_running(ndev)) { 2381 napi_disable(&fep->napi); 2382 netif_tx_lock_bh(ndev); 2383 fec_restart(ndev); 2384 netif_tx_wake_all_queues(ndev); 2385 netif_tx_unlock_bh(ndev); 2386 napi_enable(&fep->napi); 2387 } 2388 2389 return 0; 2390 } 2391 2392 static const struct fec_stat { 2393 char name[ETH_GSTRING_LEN]; 2394 u16 offset; 2395 } fec_stats[] = { 2396 /* RMON TX */ 2397 { "tx_dropped", RMON_T_DROP }, 2398 { "tx_packets", RMON_T_PACKETS }, 2399 { "tx_broadcast", RMON_T_BC_PKT }, 2400 { "tx_multicast", RMON_T_MC_PKT }, 2401 { "tx_crc_errors", RMON_T_CRC_ALIGN }, 2402 { "tx_undersize", RMON_T_UNDERSIZE }, 2403 { "tx_oversize", RMON_T_OVERSIZE }, 2404 { "tx_fragment", RMON_T_FRAG }, 2405 { "tx_jabber", RMON_T_JAB }, 2406 { "tx_collision", RMON_T_COL }, 2407 { "tx_64byte", RMON_T_P64 }, 2408 { "tx_65to127byte", RMON_T_P65TO127 }, 2409 { "tx_128to255byte", RMON_T_P128TO255 }, 2410 { "tx_256to511byte", RMON_T_P256TO511 }, 2411 { "tx_512to1023byte", RMON_T_P512TO1023 }, 2412 { "tx_1024to2047byte", RMON_T_P1024TO2047 }, 2413 { "tx_GTE2048byte", RMON_T_P_GTE2048 }, 2414 { "tx_octets", RMON_T_OCTETS }, 2415 2416 /* IEEE TX */ 2417 { "IEEE_tx_drop", IEEE_T_DROP }, 2418 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK }, 2419 { "IEEE_tx_1col", IEEE_T_1COL }, 2420 { "IEEE_tx_mcol", IEEE_T_MCOL }, 2421 { "IEEE_tx_def", IEEE_T_DEF }, 2422 { "IEEE_tx_lcol", IEEE_T_LCOL }, 2423 { "IEEE_tx_excol", IEEE_T_EXCOL }, 2424 { "IEEE_tx_macerr", IEEE_T_MACERR }, 2425 { "IEEE_tx_cserr", IEEE_T_CSERR }, 2426 { "IEEE_tx_sqe", IEEE_T_SQE }, 2427 { "IEEE_tx_fdxfc", IEEE_T_FDXFC }, 2428 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK }, 2429 2430 /* RMON RX */ 2431 { "rx_packets", RMON_R_PACKETS }, 2432 { "rx_broadcast", RMON_R_BC_PKT }, 2433 { "rx_multicast", RMON_R_MC_PKT }, 2434 { "rx_crc_errors", RMON_R_CRC_ALIGN }, 2435 { "rx_undersize", RMON_R_UNDERSIZE }, 2436 { "rx_oversize", RMON_R_OVERSIZE }, 2437 { "rx_fragment", RMON_R_FRAG }, 2438 { "rx_jabber", RMON_R_JAB }, 2439 { "rx_64byte", RMON_R_P64 }, 2440 { "rx_65to127byte", RMON_R_P65TO127 }, 2441 { "rx_128to255byte", RMON_R_P128TO255 }, 2442 { "rx_256to511byte", RMON_R_P256TO511 }, 2443 { "rx_512to1023byte", RMON_R_P512TO1023 }, 2444 { "rx_1024to2047byte", RMON_R_P1024TO2047 }, 2445 { "rx_GTE2048byte", RMON_R_P_GTE2048 }, 2446 { "rx_octets", RMON_R_OCTETS }, 2447 2448 /* IEEE RX */ 2449 { "IEEE_rx_drop", IEEE_R_DROP }, 2450 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK }, 2451 { "IEEE_rx_crc", IEEE_R_CRC }, 2452 { "IEEE_rx_align", IEEE_R_ALIGN }, 2453 { "IEEE_rx_macerr", IEEE_R_MACERR }, 2454 { "IEEE_rx_fdxfc", IEEE_R_FDXFC }, 2455 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK }, 2456 }; 2457 2458 #define FEC_STATS_SIZE (ARRAY_SIZE(fec_stats) * sizeof(u64)) 2459 2460 static void fec_enet_update_ethtool_stats(struct net_device *dev) 2461 { 2462 struct fec_enet_private *fep = netdev_priv(dev); 2463 int i; 2464 2465 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2466 fep->ethtool_stats[i] = readl(fep->hwp + fec_stats[i].offset); 2467 } 2468 2469 static void fec_enet_get_ethtool_stats(struct net_device *dev, 2470 struct ethtool_stats *stats, u64 *data) 2471 { 2472 struct fec_enet_private *fep = netdev_priv(dev); 2473 2474 if (netif_running(dev)) 2475 fec_enet_update_ethtool_stats(dev); 2476 2477 memcpy(data, fep->ethtool_stats, FEC_STATS_SIZE); 2478 } 2479 2480 static void fec_enet_get_strings(struct net_device *netdev, 2481 u32 stringset, u8 *data) 2482 { 2483 int i; 2484 switch (stringset) { 2485 case ETH_SS_STATS: 2486 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2487 memcpy(data + i * ETH_GSTRING_LEN, 2488 fec_stats[i].name, ETH_GSTRING_LEN); 2489 break; 2490 case ETH_SS_TEST: 2491 net_selftest_get_strings(data); 2492 break; 2493 } 2494 } 2495 2496 static int fec_enet_get_sset_count(struct net_device *dev, int sset) 2497 { 2498 switch (sset) { 2499 case ETH_SS_STATS: 2500 return ARRAY_SIZE(fec_stats); 2501 case ETH_SS_TEST: 2502 return net_selftest_get_count(); 2503 default: 2504 return -EOPNOTSUPP; 2505 } 2506 } 2507 2508 static void fec_enet_clear_ethtool_stats(struct net_device *dev) 2509 { 2510 struct fec_enet_private *fep = netdev_priv(dev); 2511 int i; 2512 2513 /* Disable MIB statistics counters */ 2514 writel(FEC_MIB_CTRLSTAT_DISABLE, fep->hwp + FEC_MIB_CTRLSTAT); 2515 2516 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2517 writel(0, fep->hwp + fec_stats[i].offset); 2518 2519 /* Don't disable MIB statistics counters */ 2520 writel(0, fep->hwp + FEC_MIB_CTRLSTAT); 2521 } 2522 2523 #else /* !defined(CONFIG_M5272) */ 2524 #define FEC_STATS_SIZE 0 2525 static inline void fec_enet_update_ethtool_stats(struct net_device *dev) 2526 { 2527 } 2528 2529 static inline void fec_enet_clear_ethtool_stats(struct net_device *dev) 2530 { 2531 } 2532 #endif /* !defined(CONFIG_M5272) */ 2533 2534 /* ITR clock source is enet system clock (clk_ahb). 2535 * TCTT unit is cycle_ns * 64 cycle 2536 * So, the ICTT value = X us / (cycle_ns * 64) 2537 */ 2538 static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us) 2539 { 2540 struct fec_enet_private *fep = netdev_priv(ndev); 2541 2542 return us * (fep->itr_clk_rate / 64000) / 1000; 2543 } 2544 2545 /* Set threshold for interrupt coalescing */ 2546 static void fec_enet_itr_coal_set(struct net_device *ndev) 2547 { 2548 struct fec_enet_private *fep = netdev_priv(ndev); 2549 int rx_itr, tx_itr; 2550 2551 /* Must be greater than zero to avoid unpredictable behavior */ 2552 if (!fep->rx_time_itr || !fep->rx_pkts_itr || 2553 !fep->tx_time_itr || !fep->tx_pkts_itr) 2554 return; 2555 2556 /* Select enet system clock as Interrupt Coalescing 2557 * timer Clock Source 2558 */ 2559 rx_itr = FEC_ITR_CLK_SEL; 2560 tx_itr = FEC_ITR_CLK_SEL; 2561 2562 /* set ICFT and ICTT */ 2563 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr); 2564 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr)); 2565 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr); 2566 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr)); 2567 2568 rx_itr |= FEC_ITR_EN; 2569 tx_itr |= FEC_ITR_EN; 2570 2571 writel(tx_itr, fep->hwp + FEC_TXIC0); 2572 writel(rx_itr, fep->hwp + FEC_RXIC0); 2573 if (fep->quirks & FEC_QUIRK_HAS_AVB) { 2574 writel(tx_itr, fep->hwp + FEC_TXIC1); 2575 writel(rx_itr, fep->hwp + FEC_RXIC1); 2576 writel(tx_itr, fep->hwp + FEC_TXIC2); 2577 writel(rx_itr, fep->hwp + FEC_RXIC2); 2578 } 2579 } 2580 2581 static int 2582 fec_enet_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec) 2583 { 2584 struct fec_enet_private *fep = netdev_priv(ndev); 2585 2586 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) 2587 return -EOPNOTSUPP; 2588 2589 ec->rx_coalesce_usecs = fep->rx_time_itr; 2590 ec->rx_max_coalesced_frames = fep->rx_pkts_itr; 2591 2592 ec->tx_coalesce_usecs = fep->tx_time_itr; 2593 ec->tx_max_coalesced_frames = fep->tx_pkts_itr; 2594 2595 return 0; 2596 } 2597 2598 static int 2599 fec_enet_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec) 2600 { 2601 struct fec_enet_private *fep = netdev_priv(ndev); 2602 struct device *dev = &fep->pdev->dev; 2603 unsigned int cycle; 2604 2605 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) 2606 return -EOPNOTSUPP; 2607 2608 if (ec->rx_max_coalesced_frames > 255) { 2609 dev_err(dev, "Rx coalesced frames exceed hardware limitation\n"); 2610 return -EINVAL; 2611 } 2612 2613 if (ec->tx_max_coalesced_frames > 255) { 2614 dev_err(dev, "Tx coalesced frame exceed hardware limitation\n"); 2615 return -EINVAL; 2616 } 2617 2618 cycle = fec_enet_us_to_itr_clock(ndev, ec->rx_coalesce_usecs); 2619 if (cycle > 0xFFFF) { 2620 dev_err(dev, "Rx coalesced usec exceed hardware limitation\n"); 2621 return -EINVAL; 2622 } 2623 2624 cycle = fec_enet_us_to_itr_clock(ndev, ec->tx_coalesce_usecs); 2625 if (cycle > 0xFFFF) { 2626 dev_err(dev, "Tx coalesced usec exceed hardware limitation\n"); 2627 return -EINVAL; 2628 } 2629 2630 fep->rx_time_itr = ec->rx_coalesce_usecs; 2631 fep->rx_pkts_itr = ec->rx_max_coalesced_frames; 2632 2633 fep->tx_time_itr = ec->tx_coalesce_usecs; 2634 fep->tx_pkts_itr = ec->tx_max_coalesced_frames; 2635 2636 fec_enet_itr_coal_set(ndev); 2637 2638 return 0; 2639 } 2640 2641 static void fec_enet_itr_coal_init(struct net_device *ndev) 2642 { 2643 struct ethtool_coalesce ec; 2644 2645 ec.rx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT; 2646 ec.rx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT; 2647 2648 ec.tx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT; 2649 ec.tx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT; 2650 2651 fec_enet_set_coalesce(ndev, &ec); 2652 } 2653 2654 static int fec_enet_get_tunable(struct net_device *netdev, 2655 const struct ethtool_tunable *tuna, 2656 void *data) 2657 { 2658 struct fec_enet_private *fep = netdev_priv(netdev); 2659 int ret = 0; 2660 2661 switch (tuna->id) { 2662 case ETHTOOL_RX_COPYBREAK: 2663 *(u32 *)data = fep->rx_copybreak; 2664 break; 2665 default: 2666 ret = -EINVAL; 2667 break; 2668 } 2669 2670 return ret; 2671 } 2672 2673 static int fec_enet_set_tunable(struct net_device *netdev, 2674 const struct ethtool_tunable *tuna, 2675 const void *data) 2676 { 2677 struct fec_enet_private *fep = netdev_priv(netdev); 2678 int ret = 0; 2679 2680 switch (tuna->id) { 2681 case ETHTOOL_RX_COPYBREAK: 2682 fep->rx_copybreak = *(u32 *)data; 2683 break; 2684 default: 2685 ret = -EINVAL; 2686 break; 2687 } 2688 2689 return ret; 2690 } 2691 2692 static void 2693 fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2694 { 2695 struct fec_enet_private *fep = netdev_priv(ndev); 2696 2697 if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) { 2698 wol->supported = WAKE_MAGIC; 2699 wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0; 2700 } else { 2701 wol->supported = wol->wolopts = 0; 2702 } 2703 } 2704 2705 static int 2706 fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2707 { 2708 struct fec_enet_private *fep = netdev_priv(ndev); 2709 2710 if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET)) 2711 return -EINVAL; 2712 2713 if (wol->wolopts & ~WAKE_MAGIC) 2714 return -EINVAL; 2715 2716 device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC); 2717 if (device_may_wakeup(&ndev->dev)) { 2718 fep->wol_flag |= FEC_WOL_FLAG_ENABLE; 2719 if (fep->irq[0] > 0) 2720 enable_irq_wake(fep->irq[0]); 2721 } else { 2722 fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE); 2723 if (fep->irq[0] > 0) 2724 disable_irq_wake(fep->irq[0]); 2725 } 2726 2727 return 0; 2728 } 2729 2730 static const struct ethtool_ops fec_enet_ethtool_ops = { 2731 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 2732 ETHTOOL_COALESCE_MAX_FRAMES, 2733 .get_drvinfo = fec_enet_get_drvinfo, 2734 .get_regs_len = fec_enet_get_regs_len, 2735 .get_regs = fec_enet_get_regs, 2736 .nway_reset = phy_ethtool_nway_reset, 2737 .get_link = ethtool_op_get_link, 2738 .get_coalesce = fec_enet_get_coalesce, 2739 .set_coalesce = fec_enet_set_coalesce, 2740 #ifndef CONFIG_M5272 2741 .get_pauseparam = fec_enet_get_pauseparam, 2742 .set_pauseparam = fec_enet_set_pauseparam, 2743 .get_strings = fec_enet_get_strings, 2744 .get_ethtool_stats = fec_enet_get_ethtool_stats, 2745 .get_sset_count = fec_enet_get_sset_count, 2746 #endif 2747 .get_ts_info = fec_enet_get_ts_info, 2748 .get_tunable = fec_enet_get_tunable, 2749 .set_tunable = fec_enet_set_tunable, 2750 .get_wol = fec_enet_get_wol, 2751 .set_wol = fec_enet_set_wol, 2752 .get_link_ksettings = phy_ethtool_get_link_ksettings, 2753 .set_link_ksettings = phy_ethtool_set_link_ksettings, 2754 .self_test = net_selftest, 2755 }; 2756 2757 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) 2758 { 2759 struct fec_enet_private *fep = netdev_priv(ndev); 2760 struct phy_device *phydev = ndev->phydev; 2761 2762 if (!netif_running(ndev)) 2763 return -EINVAL; 2764 2765 if (!phydev) 2766 return -ENODEV; 2767 2768 if (fep->bufdesc_ex) { 2769 bool use_fec_hwts = !phy_has_hwtstamp(phydev); 2770 2771 if (cmd == SIOCSHWTSTAMP) { 2772 if (use_fec_hwts) 2773 return fec_ptp_set(ndev, rq); 2774 fec_ptp_disable_hwts(ndev); 2775 } else if (cmd == SIOCGHWTSTAMP) { 2776 if (use_fec_hwts) 2777 return fec_ptp_get(ndev, rq); 2778 } 2779 } 2780 2781 return phy_mii_ioctl(phydev, rq, cmd); 2782 } 2783 2784 static void fec_enet_free_buffers(struct net_device *ndev) 2785 { 2786 struct fec_enet_private *fep = netdev_priv(ndev); 2787 unsigned int i; 2788 struct sk_buff *skb; 2789 struct bufdesc *bdp; 2790 struct fec_enet_priv_tx_q *txq; 2791 struct fec_enet_priv_rx_q *rxq; 2792 unsigned int q; 2793 2794 for (q = 0; q < fep->num_rx_queues; q++) { 2795 rxq = fep->rx_queue[q]; 2796 bdp = rxq->bd.base; 2797 for (i = 0; i < rxq->bd.ring_size; i++) { 2798 skb = rxq->rx_skbuff[i]; 2799 rxq->rx_skbuff[i] = NULL; 2800 if (skb) { 2801 dma_unmap_single(&fep->pdev->dev, 2802 fec32_to_cpu(bdp->cbd_bufaddr), 2803 FEC_ENET_RX_FRSIZE - fep->rx_align, 2804 DMA_FROM_DEVICE); 2805 dev_kfree_skb(skb); 2806 } 2807 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 2808 } 2809 } 2810 2811 for (q = 0; q < fep->num_tx_queues; q++) { 2812 txq = fep->tx_queue[q]; 2813 for (i = 0; i < txq->bd.ring_size; i++) { 2814 kfree(txq->tx_bounce[i]); 2815 txq->tx_bounce[i] = NULL; 2816 skb = txq->tx_skbuff[i]; 2817 txq->tx_skbuff[i] = NULL; 2818 dev_kfree_skb(skb); 2819 } 2820 } 2821 } 2822 2823 static void fec_enet_free_queue(struct net_device *ndev) 2824 { 2825 struct fec_enet_private *fep = netdev_priv(ndev); 2826 int i; 2827 struct fec_enet_priv_tx_q *txq; 2828 2829 for (i = 0; i < fep->num_tx_queues; i++) 2830 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) { 2831 txq = fep->tx_queue[i]; 2832 dma_free_coherent(&fep->pdev->dev, 2833 txq->bd.ring_size * TSO_HEADER_SIZE, 2834 txq->tso_hdrs, 2835 txq->tso_hdrs_dma); 2836 } 2837 2838 for (i = 0; i < fep->num_rx_queues; i++) 2839 kfree(fep->rx_queue[i]); 2840 for (i = 0; i < fep->num_tx_queues; i++) 2841 kfree(fep->tx_queue[i]); 2842 } 2843 2844 static int fec_enet_alloc_queue(struct net_device *ndev) 2845 { 2846 struct fec_enet_private *fep = netdev_priv(ndev); 2847 int i; 2848 int ret = 0; 2849 struct fec_enet_priv_tx_q *txq; 2850 2851 for (i = 0; i < fep->num_tx_queues; i++) { 2852 txq = kzalloc(sizeof(*txq), GFP_KERNEL); 2853 if (!txq) { 2854 ret = -ENOMEM; 2855 goto alloc_failed; 2856 } 2857 2858 fep->tx_queue[i] = txq; 2859 txq->bd.ring_size = TX_RING_SIZE; 2860 fep->total_tx_ring_size += fep->tx_queue[i]->bd.ring_size; 2861 2862 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS; 2863 txq->tx_wake_threshold = 2864 (txq->bd.ring_size - txq->tx_stop_threshold) / 2; 2865 2866 txq->tso_hdrs = dma_alloc_coherent(&fep->pdev->dev, 2867 txq->bd.ring_size * TSO_HEADER_SIZE, 2868 &txq->tso_hdrs_dma, 2869 GFP_KERNEL); 2870 if (!txq->tso_hdrs) { 2871 ret = -ENOMEM; 2872 goto alloc_failed; 2873 } 2874 } 2875 2876 for (i = 0; i < fep->num_rx_queues; i++) { 2877 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]), 2878 GFP_KERNEL); 2879 if (!fep->rx_queue[i]) { 2880 ret = -ENOMEM; 2881 goto alloc_failed; 2882 } 2883 2884 fep->rx_queue[i]->bd.ring_size = RX_RING_SIZE; 2885 fep->total_rx_ring_size += fep->rx_queue[i]->bd.ring_size; 2886 } 2887 return ret; 2888 2889 alloc_failed: 2890 fec_enet_free_queue(ndev); 2891 return ret; 2892 } 2893 2894 static int 2895 fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue) 2896 { 2897 struct fec_enet_private *fep = netdev_priv(ndev); 2898 unsigned int i; 2899 struct sk_buff *skb; 2900 struct bufdesc *bdp; 2901 struct fec_enet_priv_rx_q *rxq; 2902 2903 rxq = fep->rx_queue[queue]; 2904 bdp = rxq->bd.base; 2905 for (i = 0; i < rxq->bd.ring_size; i++) { 2906 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE); 2907 if (!skb) 2908 goto err_alloc; 2909 2910 if (fec_enet_new_rxbdp(ndev, bdp, skb)) { 2911 dev_kfree_skb(skb); 2912 goto err_alloc; 2913 } 2914 2915 rxq->rx_skbuff[i] = skb; 2916 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); 2917 2918 if (fep->bufdesc_ex) { 2919 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 2920 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); 2921 } 2922 2923 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 2924 } 2925 2926 /* Set the last buffer to wrap. */ 2927 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); 2928 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 2929 return 0; 2930 2931 err_alloc: 2932 fec_enet_free_buffers(ndev); 2933 return -ENOMEM; 2934 } 2935 2936 static int 2937 fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue) 2938 { 2939 struct fec_enet_private *fep = netdev_priv(ndev); 2940 unsigned int i; 2941 struct bufdesc *bdp; 2942 struct fec_enet_priv_tx_q *txq; 2943 2944 txq = fep->tx_queue[queue]; 2945 bdp = txq->bd.base; 2946 for (i = 0; i < txq->bd.ring_size; i++) { 2947 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); 2948 if (!txq->tx_bounce[i]) 2949 goto err_alloc; 2950 2951 bdp->cbd_sc = cpu_to_fec16(0); 2952 bdp->cbd_bufaddr = cpu_to_fec32(0); 2953 2954 if (fep->bufdesc_ex) { 2955 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 2956 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_TX_INT); 2957 } 2958 2959 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 2960 } 2961 2962 /* Set the last buffer to wrap. */ 2963 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); 2964 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 2965 2966 return 0; 2967 2968 err_alloc: 2969 fec_enet_free_buffers(ndev); 2970 return -ENOMEM; 2971 } 2972 2973 static int fec_enet_alloc_buffers(struct net_device *ndev) 2974 { 2975 struct fec_enet_private *fep = netdev_priv(ndev); 2976 unsigned int i; 2977 2978 for (i = 0; i < fep->num_rx_queues; i++) 2979 if (fec_enet_alloc_rxq_buffers(ndev, i)) 2980 return -ENOMEM; 2981 2982 for (i = 0; i < fep->num_tx_queues; i++) 2983 if (fec_enet_alloc_txq_buffers(ndev, i)) 2984 return -ENOMEM; 2985 return 0; 2986 } 2987 2988 static int 2989 fec_enet_open(struct net_device *ndev) 2990 { 2991 struct fec_enet_private *fep = netdev_priv(ndev); 2992 int ret; 2993 bool reset_again; 2994 2995 ret = pm_runtime_resume_and_get(&fep->pdev->dev); 2996 if (ret < 0) 2997 return ret; 2998 2999 pinctrl_pm_select_default_state(&fep->pdev->dev); 3000 ret = fec_enet_clk_enable(ndev, true); 3001 if (ret) 3002 goto clk_enable; 3003 3004 /* During the first fec_enet_open call the PHY isn't probed at this 3005 * point. Therefore the phy_reset_after_clk_enable() call within 3006 * fec_enet_clk_enable() fails. As we need this reset in order to be 3007 * sure the PHY is working correctly we check if we need to reset again 3008 * later when the PHY is probed 3009 */ 3010 if (ndev->phydev && ndev->phydev->drv) 3011 reset_again = false; 3012 else 3013 reset_again = true; 3014 3015 /* I should reset the ring buffers here, but I don't yet know 3016 * a simple way to do that. 3017 */ 3018 3019 ret = fec_enet_alloc_buffers(ndev); 3020 if (ret) 3021 goto err_enet_alloc; 3022 3023 /* Init MAC prior to mii bus probe */ 3024 fec_restart(ndev); 3025 3026 /* Call phy_reset_after_clk_enable() again if it failed during 3027 * phy_reset_after_clk_enable() before because the PHY wasn't probed. 3028 */ 3029 if (reset_again) 3030 fec_enet_phy_reset_after_clk_enable(ndev); 3031 3032 /* Probe and connect to PHY when open the interface */ 3033 ret = fec_enet_mii_probe(ndev); 3034 if (ret) 3035 goto err_enet_mii_probe; 3036 3037 if (fep->quirks & FEC_QUIRK_ERR006687) 3038 imx6q_cpuidle_fec_irqs_used(); 3039 3040 napi_enable(&fep->napi); 3041 phy_start(ndev->phydev); 3042 netif_tx_start_all_queues(ndev); 3043 3044 device_set_wakeup_enable(&ndev->dev, fep->wol_flag & 3045 FEC_WOL_FLAG_ENABLE); 3046 3047 return 0; 3048 3049 err_enet_mii_probe: 3050 fec_enet_free_buffers(ndev); 3051 err_enet_alloc: 3052 fec_enet_clk_enable(ndev, false); 3053 clk_enable: 3054 pm_runtime_mark_last_busy(&fep->pdev->dev); 3055 pm_runtime_put_autosuspend(&fep->pdev->dev); 3056 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3057 return ret; 3058 } 3059 3060 static int 3061 fec_enet_close(struct net_device *ndev) 3062 { 3063 struct fec_enet_private *fep = netdev_priv(ndev); 3064 3065 phy_stop(ndev->phydev); 3066 3067 if (netif_device_present(ndev)) { 3068 napi_disable(&fep->napi); 3069 netif_tx_disable(ndev); 3070 fec_stop(ndev); 3071 } 3072 3073 phy_disconnect(ndev->phydev); 3074 3075 if (fep->quirks & FEC_QUIRK_ERR006687) 3076 imx6q_cpuidle_fec_irqs_unused(); 3077 3078 fec_enet_update_ethtool_stats(ndev); 3079 3080 fec_enet_clk_enable(ndev, false); 3081 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3082 pm_runtime_mark_last_busy(&fep->pdev->dev); 3083 pm_runtime_put_autosuspend(&fep->pdev->dev); 3084 3085 fec_enet_free_buffers(ndev); 3086 3087 return 0; 3088 } 3089 3090 /* Set or clear the multicast filter for this adaptor. 3091 * Skeleton taken from sunlance driver. 3092 * The CPM Ethernet implementation allows Multicast as well as individual 3093 * MAC address filtering. Some of the drivers check to make sure it is 3094 * a group multicast address, and discard those that are not. I guess I 3095 * will do the same for now, but just remove the test if you want 3096 * individual filtering as well (do the upper net layers want or support 3097 * this kind of feature?). 3098 */ 3099 3100 #define FEC_HASH_BITS 6 /* #bits in hash */ 3101 3102 static void set_multicast_list(struct net_device *ndev) 3103 { 3104 struct fec_enet_private *fep = netdev_priv(ndev); 3105 struct netdev_hw_addr *ha; 3106 unsigned int crc, tmp; 3107 unsigned char hash; 3108 unsigned int hash_high = 0, hash_low = 0; 3109 3110 if (ndev->flags & IFF_PROMISC) { 3111 tmp = readl(fep->hwp + FEC_R_CNTRL); 3112 tmp |= 0x8; 3113 writel(tmp, fep->hwp + FEC_R_CNTRL); 3114 return; 3115 } 3116 3117 tmp = readl(fep->hwp + FEC_R_CNTRL); 3118 tmp &= ~0x8; 3119 writel(tmp, fep->hwp + FEC_R_CNTRL); 3120 3121 if (ndev->flags & IFF_ALLMULTI) { 3122 /* Catch all multicast addresses, so set the 3123 * filter to all 1's 3124 */ 3125 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 3126 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 3127 3128 return; 3129 } 3130 3131 /* Add the addresses in hash register */ 3132 netdev_for_each_mc_addr(ha, ndev) { 3133 /* calculate crc32 value of mac address */ 3134 crc = ether_crc_le(ndev->addr_len, ha->addr); 3135 3136 /* only upper 6 bits (FEC_HASH_BITS) are used 3137 * which point to specific bit in the hash registers 3138 */ 3139 hash = (crc >> (32 - FEC_HASH_BITS)) & 0x3f; 3140 3141 if (hash > 31) 3142 hash_high |= 1 << (hash - 32); 3143 else 3144 hash_low |= 1 << hash; 3145 } 3146 3147 writel(hash_high, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 3148 writel(hash_low, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 3149 } 3150 3151 /* Set a MAC change in hardware. */ 3152 static int 3153 fec_set_mac_address(struct net_device *ndev, void *p) 3154 { 3155 struct fec_enet_private *fep = netdev_priv(ndev); 3156 struct sockaddr *addr = p; 3157 3158 if (addr) { 3159 if (!is_valid_ether_addr(addr->sa_data)) 3160 return -EADDRNOTAVAIL; 3161 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len); 3162 } 3163 3164 /* Add netif status check here to avoid system hang in below case: 3165 * ifconfig ethx down; ifconfig ethx hw ether xx:xx:xx:xx:xx:xx; 3166 * After ethx down, fec all clocks are gated off and then register 3167 * access causes system hang. 3168 */ 3169 if (!netif_running(ndev)) 3170 return 0; 3171 3172 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) | 3173 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24), 3174 fep->hwp + FEC_ADDR_LOW); 3175 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24), 3176 fep->hwp + FEC_ADDR_HIGH); 3177 return 0; 3178 } 3179 3180 #ifdef CONFIG_NET_POLL_CONTROLLER 3181 /** 3182 * fec_poll_controller - FEC Poll controller function 3183 * @dev: The FEC network adapter 3184 * 3185 * Polled functionality used by netconsole and others in non interrupt mode 3186 * 3187 */ 3188 static void fec_poll_controller(struct net_device *dev) 3189 { 3190 int i; 3191 struct fec_enet_private *fep = netdev_priv(dev); 3192 3193 for (i = 0; i < FEC_IRQ_NUM; i++) { 3194 if (fep->irq[i] > 0) { 3195 disable_irq(fep->irq[i]); 3196 fec_enet_interrupt(fep->irq[i], dev); 3197 enable_irq(fep->irq[i]); 3198 } 3199 } 3200 } 3201 #endif 3202 3203 static inline void fec_enet_set_netdev_features(struct net_device *netdev, 3204 netdev_features_t features) 3205 { 3206 struct fec_enet_private *fep = netdev_priv(netdev); 3207 netdev_features_t changed = features ^ netdev->features; 3208 3209 netdev->features = features; 3210 3211 /* Receive checksum has been changed */ 3212 if (changed & NETIF_F_RXCSUM) { 3213 if (features & NETIF_F_RXCSUM) 3214 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 3215 else 3216 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED; 3217 } 3218 } 3219 3220 static int fec_set_features(struct net_device *netdev, 3221 netdev_features_t features) 3222 { 3223 struct fec_enet_private *fep = netdev_priv(netdev); 3224 netdev_features_t changed = features ^ netdev->features; 3225 3226 if (netif_running(netdev) && changed & NETIF_F_RXCSUM) { 3227 napi_disable(&fep->napi); 3228 netif_tx_lock_bh(netdev); 3229 fec_stop(netdev); 3230 fec_enet_set_netdev_features(netdev, features); 3231 fec_restart(netdev); 3232 netif_tx_wake_all_queues(netdev); 3233 netif_tx_unlock_bh(netdev); 3234 napi_enable(&fep->napi); 3235 } else { 3236 fec_enet_set_netdev_features(netdev, features); 3237 } 3238 3239 return 0; 3240 } 3241 3242 static const struct net_device_ops fec_netdev_ops = { 3243 .ndo_open = fec_enet_open, 3244 .ndo_stop = fec_enet_close, 3245 .ndo_start_xmit = fec_enet_start_xmit, 3246 .ndo_set_rx_mode = set_multicast_list, 3247 .ndo_validate_addr = eth_validate_addr, 3248 .ndo_tx_timeout = fec_timeout, 3249 .ndo_set_mac_address = fec_set_mac_address, 3250 .ndo_do_ioctl = fec_enet_ioctl, 3251 #ifdef CONFIG_NET_POLL_CONTROLLER 3252 .ndo_poll_controller = fec_poll_controller, 3253 #endif 3254 .ndo_set_features = fec_set_features, 3255 }; 3256 3257 static const unsigned short offset_des_active_rxq[] = { 3258 FEC_R_DES_ACTIVE_0, FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2 3259 }; 3260 3261 static const unsigned short offset_des_active_txq[] = { 3262 FEC_X_DES_ACTIVE_0, FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2 3263 }; 3264 3265 /* 3266 * XXX: We need to clean up on failure exits here. 3267 * 3268 */ 3269 static int fec_enet_init(struct net_device *ndev) 3270 { 3271 struct fec_enet_private *fep = netdev_priv(ndev); 3272 struct bufdesc *cbd_base; 3273 dma_addr_t bd_dma; 3274 int bd_size; 3275 unsigned int i; 3276 unsigned dsize = fep->bufdesc_ex ? sizeof(struct bufdesc_ex) : 3277 sizeof(struct bufdesc); 3278 unsigned dsize_log2 = __fls(dsize); 3279 int ret; 3280 3281 WARN_ON(dsize != (1 << dsize_log2)); 3282 #if defined(CONFIG_ARM) || defined(CONFIG_ARM64) 3283 fep->rx_align = 0xf; 3284 fep->tx_align = 0xf; 3285 #else 3286 fep->rx_align = 0x3; 3287 fep->tx_align = 0x3; 3288 #endif 3289 3290 /* Check mask of the streaming and coherent API */ 3291 ret = dma_set_mask_and_coherent(&fep->pdev->dev, DMA_BIT_MASK(32)); 3292 if (ret < 0) { 3293 dev_warn(&fep->pdev->dev, "No suitable DMA available\n"); 3294 return ret; 3295 } 3296 3297 ret = fec_enet_alloc_queue(ndev); 3298 if (ret) 3299 return ret; 3300 3301 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) * dsize; 3302 3303 /* Allocate memory for buffer descriptors. */ 3304 cbd_base = dmam_alloc_coherent(&fep->pdev->dev, bd_size, &bd_dma, 3305 GFP_KERNEL); 3306 if (!cbd_base) { 3307 ret = -ENOMEM; 3308 goto free_queue_mem; 3309 } 3310 3311 /* Get the Ethernet address */ 3312 ret = fec_get_mac(ndev); 3313 if (ret) 3314 goto free_queue_mem; 3315 3316 /* make sure MAC we just acquired is programmed into the hw */ 3317 fec_set_mac_address(ndev, NULL); 3318 3319 /* Set receive and transmit descriptor base. */ 3320 for (i = 0; i < fep->num_rx_queues; i++) { 3321 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[i]; 3322 unsigned size = dsize * rxq->bd.ring_size; 3323 3324 rxq->bd.qid = i; 3325 rxq->bd.base = cbd_base; 3326 rxq->bd.cur = cbd_base; 3327 rxq->bd.dma = bd_dma; 3328 rxq->bd.dsize = dsize; 3329 rxq->bd.dsize_log2 = dsize_log2; 3330 rxq->bd.reg_desc_active = fep->hwp + offset_des_active_rxq[i]; 3331 bd_dma += size; 3332 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size); 3333 rxq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); 3334 } 3335 3336 for (i = 0; i < fep->num_tx_queues; i++) { 3337 struct fec_enet_priv_tx_q *txq = fep->tx_queue[i]; 3338 unsigned size = dsize * txq->bd.ring_size; 3339 3340 txq->bd.qid = i; 3341 txq->bd.base = cbd_base; 3342 txq->bd.cur = cbd_base; 3343 txq->bd.dma = bd_dma; 3344 txq->bd.dsize = dsize; 3345 txq->bd.dsize_log2 = dsize_log2; 3346 txq->bd.reg_desc_active = fep->hwp + offset_des_active_txq[i]; 3347 bd_dma += size; 3348 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size); 3349 txq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); 3350 } 3351 3352 3353 /* The FEC Ethernet specific entries in the device structure */ 3354 ndev->watchdog_timeo = TX_TIMEOUT; 3355 ndev->netdev_ops = &fec_netdev_ops; 3356 ndev->ethtool_ops = &fec_enet_ethtool_ops; 3357 3358 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK); 3359 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT); 3360 3361 if (fep->quirks & FEC_QUIRK_HAS_VLAN) 3362 /* enable hw VLAN support */ 3363 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; 3364 3365 if (fep->quirks & FEC_QUIRK_HAS_CSUM) { 3366 ndev->gso_max_segs = FEC_MAX_TSO_SEGS; 3367 3368 /* enable hw accelerator */ 3369 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM 3370 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO); 3371 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 3372 } 3373 3374 if (fep->quirks & FEC_QUIRK_HAS_AVB) { 3375 fep->tx_align = 0; 3376 fep->rx_align = 0x3f; 3377 } 3378 3379 ndev->hw_features = ndev->features; 3380 3381 fec_restart(ndev); 3382 3383 if (fep->quirks & FEC_QUIRK_MIB_CLEAR) 3384 fec_enet_clear_ethtool_stats(ndev); 3385 else 3386 fec_enet_update_ethtool_stats(ndev); 3387 3388 return 0; 3389 3390 free_queue_mem: 3391 fec_enet_free_queue(ndev); 3392 return ret; 3393 } 3394 3395 #ifdef CONFIG_OF 3396 static int fec_reset_phy(struct platform_device *pdev) 3397 { 3398 int err, phy_reset; 3399 bool active_high = false; 3400 int msec = 1, phy_post_delay = 0; 3401 struct device_node *np = pdev->dev.of_node; 3402 3403 if (!np) 3404 return 0; 3405 3406 err = of_property_read_u32(np, "phy-reset-duration", &msec); 3407 /* A sane reset duration should not be longer than 1s */ 3408 if (!err && msec > 1000) 3409 msec = 1; 3410 3411 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0); 3412 if (phy_reset == -EPROBE_DEFER) 3413 return phy_reset; 3414 else if (!gpio_is_valid(phy_reset)) 3415 return 0; 3416 3417 err = of_property_read_u32(np, "phy-reset-post-delay", &phy_post_delay); 3418 /* valid reset duration should be less than 1s */ 3419 if (!err && phy_post_delay > 1000) 3420 return -EINVAL; 3421 3422 active_high = of_property_read_bool(np, "phy-reset-active-high"); 3423 3424 err = devm_gpio_request_one(&pdev->dev, phy_reset, 3425 active_high ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW, 3426 "phy-reset"); 3427 if (err) { 3428 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err); 3429 return err; 3430 } 3431 3432 if (msec > 20) 3433 msleep(msec); 3434 else 3435 usleep_range(msec * 1000, msec * 1000 + 1000); 3436 3437 gpio_set_value_cansleep(phy_reset, !active_high); 3438 3439 if (!phy_post_delay) 3440 return 0; 3441 3442 if (phy_post_delay > 20) 3443 msleep(phy_post_delay); 3444 else 3445 usleep_range(phy_post_delay * 1000, 3446 phy_post_delay * 1000 + 1000); 3447 3448 return 0; 3449 } 3450 #else /* CONFIG_OF */ 3451 static int fec_reset_phy(struct platform_device *pdev) 3452 { 3453 /* 3454 * In case of platform probe, the reset has been done 3455 * by machine code. 3456 */ 3457 return 0; 3458 } 3459 #endif /* CONFIG_OF */ 3460 3461 static void 3462 fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx) 3463 { 3464 struct device_node *np = pdev->dev.of_node; 3465 3466 *num_tx = *num_rx = 1; 3467 3468 if (!np || !of_device_is_available(np)) 3469 return; 3470 3471 /* parse the num of tx and rx queues */ 3472 of_property_read_u32(np, "fsl,num-tx-queues", num_tx); 3473 3474 of_property_read_u32(np, "fsl,num-rx-queues", num_rx); 3475 3476 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) { 3477 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n", 3478 *num_tx); 3479 *num_tx = 1; 3480 return; 3481 } 3482 3483 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) { 3484 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n", 3485 *num_rx); 3486 *num_rx = 1; 3487 return; 3488 } 3489 3490 } 3491 3492 static int fec_enet_get_irq_cnt(struct platform_device *pdev) 3493 { 3494 int irq_cnt = platform_irq_count(pdev); 3495 3496 if (irq_cnt > FEC_IRQ_NUM) 3497 irq_cnt = FEC_IRQ_NUM; /* last for pps */ 3498 else if (irq_cnt == 2) 3499 irq_cnt = 1; /* last for pps */ 3500 else if (irq_cnt <= 0) 3501 irq_cnt = 1; /* At least 1 irq is needed */ 3502 return irq_cnt; 3503 } 3504 3505 static int fec_enet_init_stop_mode(struct fec_enet_private *fep, 3506 struct device_node *np) 3507 { 3508 struct device_node *gpr_np; 3509 u32 out_val[3]; 3510 int ret = 0; 3511 3512 gpr_np = of_parse_phandle(np, "fsl,stop-mode", 0); 3513 if (!gpr_np) 3514 return 0; 3515 3516 ret = of_property_read_u32_array(np, "fsl,stop-mode", out_val, 3517 ARRAY_SIZE(out_val)); 3518 if (ret) { 3519 dev_dbg(&fep->pdev->dev, "no stop mode property\n"); 3520 return ret; 3521 } 3522 3523 fep->stop_gpr.gpr = syscon_node_to_regmap(gpr_np); 3524 if (IS_ERR(fep->stop_gpr.gpr)) { 3525 dev_err(&fep->pdev->dev, "could not find gpr regmap\n"); 3526 ret = PTR_ERR(fep->stop_gpr.gpr); 3527 fep->stop_gpr.gpr = NULL; 3528 goto out; 3529 } 3530 3531 fep->stop_gpr.reg = out_val[1]; 3532 fep->stop_gpr.bit = out_val[2]; 3533 3534 out: 3535 of_node_put(gpr_np); 3536 3537 return ret; 3538 } 3539 3540 static int 3541 fec_probe(struct platform_device *pdev) 3542 { 3543 struct fec_enet_private *fep; 3544 struct fec_platform_data *pdata; 3545 phy_interface_t interface; 3546 struct net_device *ndev; 3547 int i, irq, ret = 0; 3548 const struct of_device_id *of_id; 3549 static int dev_id; 3550 struct device_node *np = pdev->dev.of_node, *phy_node; 3551 int num_tx_qs; 3552 int num_rx_qs; 3553 char irq_name[8]; 3554 int irq_cnt; 3555 struct fec_devinfo *dev_info; 3556 3557 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs); 3558 3559 /* Init network device */ 3560 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private) + 3561 FEC_STATS_SIZE, num_tx_qs, num_rx_qs); 3562 if (!ndev) 3563 return -ENOMEM; 3564 3565 SET_NETDEV_DEV(ndev, &pdev->dev); 3566 3567 /* setup board info structure */ 3568 fep = netdev_priv(ndev); 3569 3570 of_id = of_match_device(fec_dt_ids, &pdev->dev); 3571 if (of_id) 3572 pdev->id_entry = of_id->data; 3573 dev_info = (struct fec_devinfo *)pdev->id_entry->driver_data; 3574 if (dev_info) 3575 fep->quirks = dev_info->quirks; 3576 3577 fep->netdev = ndev; 3578 fep->num_rx_queues = num_rx_qs; 3579 fep->num_tx_queues = num_tx_qs; 3580 3581 #if !defined(CONFIG_M5272) 3582 /* default enable pause frame auto negotiation */ 3583 if (fep->quirks & FEC_QUIRK_HAS_GBIT) 3584 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG; 3585 #endif 3586 3587 /* Select default pin state */ 3588 pinctrl_pm_select_default_state(&pdev->dev); 3589 3590 fep->hwp = devm_platform_ioremap_resource(pdev, 0); 3591 if (IS_ERR(fep->hwp)) { 3592 ret = PTR_ERR(fep->hwp); 3593 goto failed_ioremap; 3594 } 3595 3596 fep->pdev = pdev; 3597 fep->dev_id = dev_id++; 3598 3599 platform_set_drvdata(pdev, ndev); 3600 3601 if ((of_machine_is_compatible("fsl,imx6q") || 3602 of_machine_is_compatible("fsl,imx6dl")) && 3603 !of_property_read_bool(np, "fsl,err006687-workaround-present")) 3604 fep->quirks |= FEC_QUIRK_ERR006687; 3605 3606 if (of_get_property(np, "fsl,magic-packet", NULL)) 3607 fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET; 3608 3609 ret = fec_enet_init_stop_mode(fep, np); 3610 if (ret) 3611 goto failed_stop_mode; 3612 3613 phy_node = of_parse_phandle(np, "phy-handle", 0); 3614 if (!phy_node && of_phy_is_fixed_link(np)) { 3615 ret = of_phy_register_fixed_link(np); 3616 if (ret < 0) { 3617 dev_err(&pdev->dev, 3618 "broken fixed-link specification\n"); 3619 goto failed_phy; 3620 } 3621 phy_node = of_node_get(np); 3622 } 3623 fep->phy_node = phy_node; 3624 3625 ret = of_get_phy_mode(pdev->dev.of_node, &interface); 3626 if (ret) { 3627 pdata = dev_get_platdata(&pdev->dev); 3628 if (pdata) 3629 fep->phy_interface = pdata->phy; 3630 else 3631 fep->phy_interface = PHY_INTERFACE_MODE_MII; 3632 } else { 3633 fep->phy_interface = interface; 3634 } 3635 3636 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 3637 if (IS_ERR(fep->clk_ipg)) { 3638 ret = PTR_ERR(fep->clk_ipg); 3639 goto failed_clk; 3640 } 3641 3642 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 3643 if (IS_ERR(fep->clk_ahb)) { 3644 ret = PTR_ERR(fep->clk_ahb); 3645 goto failed_clk; 3646 } 3647 3648 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb); 3649 3650 /* enet_out is optional, depends on board */ 3651 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out"); 3652 if (IS_ERR(fep->clk_enet_out)) 3653 fep->clk_enet_out = NULL; 3654 3655 fep->ptp_clk_on = false; 3656 mutex_init(&fep->ptp_clk_mutex); 3657 3658 /* clk_ref is optional, depends on board */ 3659 fep->clk_ref = devm_clk_get(&pdev->dev, "enet_clk_ref"); 3660 if (IS_ERR(fep->clk_ref)) 3661 fep->clk_ref = NULL; 3662 3663 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX; 3664 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp"); 3665 if (IS_ERR(fep->clk_ptp)) { 3666 fep->clk_ptp = NULL; 3667 fep->bufdesc_ex = false; 3668 } 3669 3670 ret = fec_enet_clk_enable(ndev, true); 3671 if (ret) 3672 goto failed_clk; 3673 3674 ret = clk_prepare_enable(fep->clk_ipg); 3675 if (ret) 3676 goto failed_clk_ipg; 3677 ret = clk_prepare_enable(fep->clk_ahb); 3678 if (ret) 3679 goto failed_clk_ahb; 3680 3681 fep->reg_phy = devm_regulator_get_optional(&pdev->dev, "phy"); 3682 if (!IS_ERR(fep->reg_phy)) { 3683 ret = regulator_enable(fep->reg_phy); 3684 if (ret) { 3685 dev_err(&pdev->dev, 3686 "Failed to enable phy regulator: %d\n", ret); 3687 goto failed_regulator; 3688 } 3689 } else { 3690 if (PTR_ERR(fep->reg_phy) == -EPROBE_DEFER) { 3691 ret = -EPROBE_DEFER; 3692 goto failed_regulator; 3693 } 3694 fep->reg_phy = NULL; 3695 } 3696 3697 pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT); 3698 pm_runtime_use_autosuspend(&pdev->dev); 3699 pm_runtime_get_noresume(&pdev->dev); 3700 pm_runtime_set_active(&pdev->dev); 3701 pm_runtime_enable(&pdev->dev); 3702 3703 ret = fec_reset_phy(pdev); 3704 if (ret) 3705 goto failed_reset; 3706 3707 irq_cnt = fec_enet_get_irq_cnt(pdev); 3708 if (fep->bufdesc_ex) 3709 fec_ptp_init(pdev, irq_cnt); 3710 3711 ret = fec_enet_init(ndev); 3712 if (ret) 3713 goto failed_init; 3714 3715 for (i = 0; i < irq_cnt; i++) { 3716 snprintf(irq_name, sizeof(irq_name), "int%d", i); 3717 irq = platform_get_irq_byname_optional(pdev, irq_name); 3718 if (irq < 0) 3719 irq = platform_get_irq(pdev, i); 3720 if (irq < 0) { 3721 ret = irq; 3722 goto failed_irq; 3723 } 3724 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt, 3725 0, pdev->name, ndev); 3726 if (ret) 3727 goto failed_irq; 3728 3729 fep->irq[i] = irq; 3730 } 3731 3732 ret = fec_enet_mii_init(pdev); 3733 if (ret) 3734 goto failed_mii_init; 3735 3736 /* Carrier starts down, phylib will bring it up */ 3737 netif_carrier_off(ndev); 3738 fec_enet_clk_enable(ndev, false); 3739 pinctrl_pm_select_sleep_state(&pdev->dev); 3740 3741 ndev->max_mtu = PKT_MAXBUF_SIZE - ETH_HLEN - ETH_FCS_LEN; 3742 3743 ret = register_netdev(ndev); 3744 if (ret) 3745 goto failed_register; 3746 3747 device_init_wakeup(&ndev->dev, fep->wol_flag & 3748 FEC_WOL_HAS_MAGIC_PACKET); 3749 3750 if (fep->bufdesc_ex && fep->ptp_clock) 3751 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id); 3752 3753 fep->rx_copybreak = COPYBREAK_DEFAULT; 3754 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work); 3755 3756 pm_runtime_mark_last_busy(&pdev->dev); 3757 pm_runtime_put_autosuspend(&pdev->dev); 3758 3759 return 0; 3760 3761 failed_register: 3762 fec_enet_mii_remove(fep); 3763 failed_mii_init: 3764 failed_irq: 3765 failed_init: 3766 fec_ptp_stop(pdev); 3767 failed_reset: 3768 pm_runtime_put_noidle(&pdev->dev); 3769 pm_runtime_disable(&pdev->dev); 3770 if (fep->reg_phy) 3771 regulator_disable(fep->reg_phy); 3772 failed_regulator: 3773 clk_disable_unprepare(fep->clk_ahb); 3774 failed_clk_ahb: 3775 clk_disable_unprepare(fep->clk_ipg); 3776 failed_clk_ipg: 3777 fec_enet_clk_enable(ndev, false); 3778 failed_clk: 3779 if (of_phy_is_fixed_link(np)) 3780 of_phy_deregister_fixed_link(np); 3781 of_node_put(phy_node); 3782 failed_stop_mode: 3783 failed_phy: 3784 dev_id--; 3785 failed_ioremap: 3786 free_netdev(ndev); 3787 3788 return ret; 3789 } 3790 3791 static int 3792 fec_drv_remove(struct platform_device *pdev) 3793 { 3794 struct net_device *ndev = platform_get_drvdata(pdev); 3795 struct fec_enet_private *fep = netdev_priv(ndev); 3796 struct device_node *np = pdev->dev.of_node; 3797 int ret; 3798 3799 ret = pm_runtime_resume_and_get(&pdev->dev); 3800 if (ret < 0) 3801 return ret; 3802 3803 cancel_work_sync(&fep->tx_timeout_work); 3804 fec_ptp_stop(pdev); 3805 unregister_netdev(ndev); 3806 fec_enet_mii_remove(fep); 3807 if (fep->reg_phy) 3808 regulator_disable(fep->reg_phy); 3809 3810 if (of_phy_is_fixed_link(np)) 3811 of_phy_deregister_fixed_link(np); 3812 of_node_put(fep->phy_node); 3813 free_netdev(ndev); 3814 3815 clk_disable_unprepare(fep->clk_ahb); 3816 clk_disable_unprepare(fep->clk_ipg); 3817 pm_runtime_put_noidle(&pdev->dev); 3818 pm_runtime_disable(&pdev->dev); 3819 3820 return 0; 3821 } 3822 3823 static int __maybe_unused fec_suspend(struct device *dev) 3824 { 3825 struct net_device *ndev = dev_get_drvdata(dev); 3826 struct fec_enet_private *fep = netdev_priv(ndev); 3827 3828 rtnl_lock(); 3829 if (netif_running(ndev)) { 3830 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) 3831 fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON; 3832 phy_stop(ndev->phydev); 3833 napi_disable(&fep->napi); 3834 netif_tx_lock_bh(ndev); 3835 netif_device_detach(ndev); 3836 netif_tx_unlock_bh(ndev); 3837 fec_stop(ndev); 3838 fec_enet_clk_enable(ndev, false); 3839 if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) 3840 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3841 } 3842 rtnl_unlock(); 3843 3844 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) 3845 regulator_disable(fep->reg_phy); 3846 3847 /* SOC supply clock to phy, when clock is disabled, phy link down 3848 * SOC control phy regulator, when regulator is disabled, phy link down 3849 */ 3850 if (fep->clk_enet_out || fep->reg_phy) 3851 fep->link = 0; 3852 3853 return 0; 3854 } 3855 3856 static int __maybe_unused fec_resume(struct device *dev) 3857 { 3858 struct net_device *ndev = dev_get_drvdata(dev); 3859 struct fec_enet_private *fep = netdev_priv(ndev); 3860 int ret; 3861 int val; 3862 3863 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) { 3864 ret = regulator_enable(fep->reg_phy); 3865 if (ret) 3866 return ret; 3867 } 3868 3869 rtnl_lock(); 3870 if (netif_running(ndev)) { 3871 ret = fec_enet_clk_enable(ndev, true); 3872 if (ret) { 3873 rtnl_unlock(); 3874 goto failed_clk; 3875 } 3876 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) { 3877 fec_enet_stop_mode(fep, false); 3878 3879 val = readl(fep->hwp + FEC_ECNTRL); 3880 val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP); 3881 writel(val, fep->hwp + FEC_ECNTRL); 3882 fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON; 3883 } else { 3884 pinctrl_pm_select_default_state(&fep->pdev->dev); 3885 } 3886 fec_restart(ndev); 3887 netif_tx_lock_bh(ndev); 3888 netif_device_attach(ndev); 3889 netif_tx_unlock_bh(ndev); 3890 napi_enable(&fep->napi); 3891 phy_init_hw(ndev->phydev); 3892 phy_start(ndev->phydev); 3893 } 3894 rtnl_unlock(); 3895 3896 return 0; 3897 3898 failed_clk: 3899 if (fep->reg_phy) 3900 regulator_disable(fep->reg_phy); 3901 return ret; 3902 } 3903 3904 static int __maybe_unused fec_runtime_suspend(struct device *dev) 3905 { 3906 struct net_device *ndev = dev_get_drvdata(dev); 3907 struct fec_enet_private *fep = netdev_priv(ndev); 3908 3909 clk_disable_unprepare(fep->clk_ahb); 3910 clk_disable_unprepare(fep->clk_ipg); 3911 3912 return 0; 3913 } 3914 3915 static int __maybe_unused fec_runtime_resume(struct device *dev) 3916 { 3917 struct net_device *ndev = dev_get_drvdata(dev); 3918 struct fec_enet_private *fep = netdev_priv(ndev); 3919 int ret; 3920 3921 ret = clk_prepare_enable(fep->clk_ahb); 3922 if (ret) 3923 return ret; 3924 ret = clk_prepare_enable(fep->clk_ipg); 3925 if (ret) 3926 goto failed_clk_ipg; 3927 3928 return 0; 3929 3930 failed_clk_ipg: 3931 clk_disable_unprepare(fep->clk_ahb); 3932 return ret; 3933 } 3934 3935 static const struct dev_pm_ops fec_pm_ops = { 3936 SET_SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume) 3937 SET_RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL) 3938 }; 3939 3940 static struct platform_driver fec_driver = { 3941 .driver = { 3942 .name = DRIVER_NAME, 3943 .pm = &fec_pm_ops, 3944 .of_match_table = fec_dt_ids, 3945 .suppress_bind_attrs = true, 3946 }, 3947 .id_table = fec_devtype, 3948 .probe = fec_probe, 3949 .remove = fec_drv_remove, 3950 }; 3951 3952 module_platform_driver(fec_driver); 3953 3954 MODULE_ALIAS("platform:"DRIVER_NAME); 3955 MODULE_LICENSE("GPL"); 3956