1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. 4 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) 5 * 6 * Right now, I am very wasteful with the buffers. I allocate memory 7 * pages and then divide them into 2K frame buffers. This way I know I 8 * have buffers large enough to hold one frame within one buffer descriptor. 9 * Once I get this working, I will use 64 or 128 byte CPM buffers, which 10 * will be much more memory efficient and will easily handle lots of 11 * small packets. 12 * 13 * Much better multiple PHY support by Magnus Damm. 14 * Copyright (c) 2000 Ericsson Radio Systems AB. 15 * 16 * Support for FEC controller of ColdFire processors. 17 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) 18 * 19 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) 20 * Copyright (c) 2004-2006 Macq Electronique SA. 21 * 22 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. 23 */ 24 25 #include <linux/module.h> 26 #include <linux/kernel.h> 27 #include <linux/string.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/ptrace.h> 30 #include <linux/errno.h> 31 #include <linux/ioport.h> 32 #include <linux/slab.h> 33 #include <linux/interrupt.h> 34 #include <linux/delay.h> 35 #include <linux/netdevice.h> 36 #include <linux/etherdevice.h> 37 #include <linux/skbuff.h> 38 #include <linux/in.h> 39 #include <linux/ip.h> 40 #include <net/ip.h> 41 #include <net/tso.h> 42 #include <linux/tcp.h> 43 #include <linux/udp.h> 44 #include <linux/icmp.h> 45 #include <linux/spinlock.h> 46 #include <linux/workqueue.h> 47 #include <linux/bitops.h> 48 #include <linux/io.h> 49 #include <linux/irq.h> 50 #include <linux/clk.h> 51 #include <linux/crc32.h> 52 #include <linux/platform_device.h> 53 #include <linux/mdio.h> 54 #include <linux/phy.h> 55 #include <linux/fec.h> 56 #include <linux/of.h> 57 #include <linux/of_device.h> 58 #include <linux/of_gpio.h> 59 #include <linux/of_mdio.h> 60 #include <linux/of_net.h> 61 #include <linux/regulator/consumer.h> 62 #include <linux/if_vlan.h> 63 #include <linux/pinctrl/consumer.h> 64 #include <linux/prefetch.h> 65 #include <linux/mfd/syscon.h> 66 #include <linux/regmap.h> 67 #include <soc/imx/cpuidle.h> 68 69 #include <asm/cacheflush.h> 70 71 #include "fec.h" 72 73 static void set_multicast_list(struct net_device *ndev); 74 static void fec_enet_itr_coal_init(struct net_device *ndev); 75 76 #define DRIVER_NAME "fec" 77 78 #define FEC_ENET_GET_QUQUE(_x) ((_x == 0) ? 1 : ((_x == 1) ? 2 : 0)) 79 80 /* Pause frame feild and FIFO threshold */ 81 #define FEC_ENET_FCE (1 << 5) 82 #define FEC_ENET_RSEM_V 0x84 83 #define FEC_ENET_RSFL_V 16 84 #define FEC_ENET_RAEM_V 0x8 85 #define FEC_ENET_RAFL_V 0x8 86 #define FEC_ENET_OPD_V 0xFFF0 87 #define FEC_MDIO_PM_TIMEOUT 100 /* ms */ 88 89 struct fec_devinfo { 90 u32 quirks; 91 }; 92 93 static const struct fec_devinfo fec_imx25_info = { 94 .quirks = FEC_QUIRK_USE_GASKET | FEC_QUIRK_MIB_CLEAR | 95 FEC_QUIRK_HAS_FRREG, 96 }; 97 98 static const struct fec_devinfo fec_imx27_info = { 99 .quirks = FEC_QUIRK_MIB_CLEAR | FEC_QUIRK_HAS_FRREG, 100 }; 101 102 static const struct fec_devinfo fec_imx28_info = { 103 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME | 104 FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC | 105 FEC_QUIRK_HAS_FRREG, 106 }; 107 108 static const struct fec_devinfo fec_imx6q_info = { 109 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 110 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 111 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 | 112 FEC_QUIRK_HAS_RACC, 113 }; 114 115 static const struct fec_devinfo fec_mvf600_info = { 116 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC, 117 }; 118 119 static const struct fec_devinfo fec_imx6x_info = { 120 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 121 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 122 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 123 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 124 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE, 125 }; 126 127 static const struct fec_devinfo fec_imx6ul_info = { 128 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 129 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 130 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR007885 | 131 FEC_QUIRK_BUG_CAPTURE | FEC_QUIRK_HAS_RACC | 132 FEC_QUIRK_HAS_COALESCE, 133 }; 134 135 static struct platform_device_id fec_devtype[] = { 136 { 137 /* keep it for coldfire */ 138 .name = DRIVER_NAME, 139 .driver_data = 0, 140 }, { 141 .name = "imx25-fec", 142 .driver_data = (kernel_ulong_t)&fec_imx25_info, 143 }, { 144 .name = "imx27-fec", 145 .driver_data = (kernel_ulong_t)&fec_imx27_info, 146 }, { 147 .name = "imx28-fec", 148 .driver_data = (kernel_ulong_t)&fec_imx28_info, 149 }, { 150 .name = "imx6q-fec", 151 .driver_data = (kernel_ulong_t)&fec_imx6q_info, 152 }, { 153 .name = "mvf600-fec", 154 .driver_data = (kernel_ulong_t)&fec_mvf600_info, 155 }, { 156 .name = "imx6sx-fec", 157 .driver_data = (kernel_ulong_t)&fec_imx6x_info, 158 }, { 159 .name = "imx6ul-fec", 160 .driver_data = (kernel_ulong_t)&fec_imx6ul_info, 161 }, { 162 /* sentinel */ 163 } 164 }; 165 MODULE_DEVICE_TABLE(platform, fec_devtype); 166 167 enum imx_fec_type { 168 IMX25_FEC = 1, /* runs on i.mx25/50/53 */ 169 IMX27_FEC, /* runs on i.mx27/35/51 */ 170 IMX28_FEC, 171 IMX6Q_FEC, 172 MVF600_FEC, 173 IMX6SX_FEC, 174 IMX6UL_FEC, 175 }; 176 177 static const struct of_device_id fec_dt_ids[] = { 178 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], }, 179 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], }, 180 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], }, 181 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], }, 182 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], }, 183 { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], }, 184 { .compatible = "fsl,imx6ul-fec", .data = &fec_devtype[IMX6UL_FEC], }, 185 { /* sentinel */ } 186 }; 187 MODULE_DEVICE_TABLE(of, fec_dt_ids); 188 189 static unsigned char macaddr[ETH_ALEN]; 190 module_param_array(macaddr, byte, NULL, 0); 191 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address"); 192 193 #if defined(CONFIG_M5272) 194 /* 195 * Some hardware gets it MAC address out of local flash memory. 196 * if this is non-zero then assume it is the address to get MAC from. 197 */ 198 #if defined(CONFIG_NETtel) 199 #define FEC_FLASHMAC 0xf0006006 200 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) 201 #define FEC_FLASHMAC 0xf0006000 202 #elif defined(CONFIG_CANCam) 203 #define FEC_FLASHMAC 0xf0020000 204 #elif defined (CONFIG_M5272C3) 205 #define FEC_FLASHMAC (0xffe04000 + 4) 206 #elif defined(CONFIG_MOD5272) 207 #define FEC_FLASHMAC 0xffc0406b 208 #else 209 #define FEC_FLASHMAC 0 210 #endif 211 #endif /* CONFIG_M5272 */ 212 213 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets. 214 * 215 * 2048 byte skbufs are allocated. However, alignment requirements 216 * varies between FEC variants. Worst case is 64, so round down by 64. 217 */ 218 #define PKT_MAXBUF_SIZE (round_down(2048 - 64, 64)) 219 #define PKT_MINBUF_SIZE 64 220 221 /* FEC receive acceleration */ 222 #define FEC_RACC_IPDIS (1 << 1) 223 #define FEC_RACC_PRODIS (1 << 2) 224 #define FEC_RACC_SHIFT16 BIT(7) 225 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS) 226 227 /* MIB Control Register */ 228 #define FEC_MIB_CTRLSTAT_DISABLE BIT(31) 229 230 /* 231 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame 232 * size bits. Other FEC hardware does not, so we need to take that into 233 * account when setting it. 234 */ 235 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 236 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \ 237 defined(CONFIG_ARM64) 238 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) 239 #else 240 #define OPT_FRAME_SIZE 0 241 #endif 242 243 /* FEC MII MMFR bits definition */ 244 #define FEC_MMFR_ST (1 << 30) 245 #define FEC_MMFR_ST_C45 (0) 246 #define FEC_MMFR_OP_READ (2 << 28) 247 #define FEC_MMFR_OP_READ_C45 (3 << 28) 248 #define FEC_MMFR_OP_WRITE (1 << 28) 249 #define FEC_MMFR_OP_ADDR_WRITE (0) 250 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23) 251 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18) 252 #define FEC_MMFR_TA (2 << 16) 253 #define FEC_MMFR_DATA(v) (v & 0xffff) 254 /* FEC ECR bits definition */ 255 #define FEC_ECR_MAGICEN (1 << 2) 256 #define FEC_ECR_SLEEP (1 << 3) 257 258 #define FEC_MII_TIMEOUT 30000 /* us */ 259 260 /* Transmitter timeout */ 261 #define TX_TIMEOUT (2 * HZ) 262 263 #define FEC_PAUSE_FLAG_AUTONEG 0x1 264 #define FEC_PAUSE_FLAG_ENABLE 0x2 265 #define FEC_WOL_HAS_MAGIC_PACKET (0x1 << 0) 266 #define FEC_WOL_FLAG_ENABLE (0x1 << 1) 267 #define FEC_WOL_FLAG_SLEEP_ON (0x1 << 2) 268 269 #define COPYBREAK_DEFAULT 256 270 271 /* Max number of allowed TCP segments for software TSO */ 272 #define FEC_MAX_TSO_SEGS 100 273 #define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) 274 275 #define IS_TSO_HEADER(txq, addr) \ 276 ((addr >= txq->tso_hdrs_dma) && \ 277 (addr < txq->tso_hdrs_dma + txq->bd.ring_size * TSO_HEADER_SIZE)) 278 279 static int mii_cnt; 280 281 static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, 282 struct bufdesc_prop *bd) 283 { 284 return (bdp >= bd->last) ? bd->base 285 : (struct bufdesc *)(((void *)bdp) + bd->dsize); 286 } 287 288 static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, 289 struct bufdesc_prop *bd) 290 { 291 return (bdp <= bd->base) ? bd->last 292 : (struct bufdesc *)(((void *)bdp) - bd->dsize); 293 } 294 295 static int fec_enet_get_bd_index(struct bufdesc *bdp, 296 struct bufdesc_prop *bd) 297 { 298 return ((const char *)bdp - (const char *)bd->base) >> bd->dsize_log2; 299 } 300 301 static int fec_enet_get_free_txdesc_num(struct fec_enet_priv_tx_q *txq) 302 { 303 int entries; 304 305 entries = (((const char *)txq->dirty_tx - 306 (const char *)txq->bd.cur) >> txq->bd.dsize_log2) - 1; 307 308 return entries >= 0 ? entries : entries + txq->bd.ring_size; 309 } 310 311 static void swap_buffer(void *bufaddr, int len) 312 { 313 int i; 314 unsigned int *buf = bufaddr; 315 316 for (i = 0; i < len; i += 4, buf++) 317 swab32s(buf); 318 } 319 320 static void swap_buffer2(void *dst_buf, void *src_buf, int len) 321 { 322 int i; 323 unsigned int *src = src_buf; 324 unsigned int *dst = dst_buf; 325 326 for (i = 0; i < len; i += 4, src++, dst++) 327 *dst = swab32p(src); 328 } 329 330 static void fec_dump(struct net_device *ndev) 331 { 332 struct fec_enet_private *fep = netdev_priv(ndev); 333 struct bufdesc *bdp; 334 struct fec_enet_priv_tx_q *txq; 335 int index = 0; 336 337 netdev_info(ndev, "TX ring dump\n"); 338 pr_info("Nr SC addr len SKB\n"); 339 340 txq = fep->tx_queue[0]; 341 bdp = txq->bd.base; 342 343 do { 344 pr_info("%3u %c%c 0x%04x 0x%08x %4u %p\n", 345 index, 346 bdp == txq->bd.cur ? 'S' : ' ', 347 bdp == txq->dirty_tx ? 'H' : ' ', 348 fec16_to_cpu(bdp->cbd_sc), 349 fec32_to_cpu(bdp->cbd_bufaddr), 350 fec16_to_cpu(bdp->cbd_datlen), 351 txq->tx_skbuff[index]); 352 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 353 index++; 354 } while (bdp != txq->bd.base); 355 } 356 357 static inline bool is_ipv4_pkt(struct sk_buff *skb) 358 { 359 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4; 360 } 361 362 static int 363 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev) 364 { 365 /* Only run for packets requiring a checksum. */ 366 if (skb->ip_summed != CHECKSUM_PARTIAL) 367 return 0; 368 369 if (unlikely(skb_cow_head(skb, 0))) 370 return -1; 371 372 if (is_ipv4_pkt(skb)) 373 ip_hdr(skb)->check = 0; 374 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0; 375 376 return 0; 377 } 378 379 static struct bufdesc * 380 fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq, 381 struct sk_buff *skb, 382 struct net_device *ndev) 383 { 384 struct fec_enet_private *fep = netdev_priv(ndev); 385 struct bufdesc *bdp = txq->bd.cur; 386 struct bufdesc_ex *ebdp; 387 int nr_frags = skb_shinfo(skb)->nr_frags; 388 int frag, frag_len; 389 unsigned short status; 390 unsigned int estatus = 0; 391 skb_frag_t *this_frag; 392 unsigned int index; 393 void *bufaddr; 394 dma_addr_t addr; 395 int i; 396 397 for (frag = 0; frag < nr_frags; frag++) { 398 this_frag = &skb_shinfo(skb)->frags[frag]; 399 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 400 ebdp = (struct bufdesc_ex *)bdp; 401 402 status = fec16_to_cpu(bdp->cbd_sc); 403 status &= ~BD_ENET_TX_STATS; 404 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 405 frag_len = skb_frag_size(&skb_shinfo(skb)->frags[frag]); 406 407 /* Handle the last BD specially */ 408 if (frag == nr_frags - 1) { 409 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 410 if (fep->bufdesc_ex) { 411 estatus |= BD_ENET_TX_INT; 412 if (unlikely(skb_shinfo(skb)->tx_flags & 413 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 414 estatus |= BD_ENET_TX_TS; 415 } 416 } 417 418 if (fep->bufdesc_ex) { 419 if (fep->quirks & FEC_QUIRK_HAS_AVB) 420 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 421 if (skb->ip_summed == CHECKSUM_PARTIAL) 422 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 423 ebdp->cbd_bdu = 0; 424 ebdp->cbd_esc = cpu_to_fec32(estatus); 425 } 426 427 bufaddr = skb_frag_address(this_frag); 428 429 index = fec_enet_get_bd_index(bdp, &txq->bd); 430 if (((unsigned long) bufaddr) & fep->tx_align || 431 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 432 memcpy(txq->tx_bounce[index], bufaddr, frag_len); 433 bufaddr = txq->tx_bounce[index]; 434 435 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 436 swap_buffer(bufaddr, frag_len); 437 } 438 439 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len, 440 DMA_TO_DEVICE); 441 if (dma_mapping_error(&fep->pdev->dev, addr)) { 442 if (net_ratelimit()) 443 netdev_err(ndev, "Tx DMA memory map failed\n"); 444 goto dma_mapping_error; 445 } 446 447 bdp->cbd_bufaddr = cpu_to_fec32(addr); 448 bdp->cbd_datlen = cpu_to_fec16(frag_len); 449 /* Make sure the updates to rest of the descriptor are 450 * performed before transferring ownership. 451 */ 452 wmb(); 453 bdp->cbd_sc = cpu_to_fec16(status); 454 } 455 456 return bdp; 457 dma_mapping_error: 458 bdp = txq->bd.cur; 459 for (i = 0; i < frag; i++) { 460 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 461 dma_unmap_single(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr), 462 fec16_to_cpu(bdp->cbd_datlen), DMA_TO_DEVICE); 463 } 464 return ERR_PTR(-ENOMEM); 465 } 466 467 static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq, 468 struct sk_buff *skb, struct net_device *ndev) 469 { 470 struct fec_enet_private *fep = netdev_priv(ndev); 471 int nr_frags = skb_shinfo(skb)->nr_frags; 472 struct bufdesc *bdp, *last_bdp; 473 void *bufaddr; 474 dma_addr_t addr; 475 unsigned short status; 476 unsigned short buflen; 477 unsigned int estatus = 0; 478 unsigned int index; 479 int entries_free; 480 481 entries_free = fec_enet_get_free_txdesc_num(txq); 482 if (entries_free < MAX_SKB_FRAGS + 1) { 483 dev_kfree_skb_any(skb); 484 if (net_ratelimit()) 485 netdev_err(ndev, "NOT enough BD for SG!\n"); 486 return NETDEV_TX_OK; 487 } 488 489 /* Protocol checksum off-load for TCP and UDP. */ 490 if (fec_enet_clear_csum(skb, ndev)) { 491 dev_kfree_skb_any(skb); 492 return NETDEV_TX_OK; 493 } 494 495 /* Fill in a Tx ring entry */ 496 bdp = txq->bd.cur; 497 last_bdp = bdp; 498 status = fec16_to_cpu(bdp->cbd_sc); 499 status &= ~BD_ENET_TX_STATS; 500 501 /* Set buffer length and buffer pointer */ 502 bufaddr = skb->data; 503 buflen = skb_headlen(skb); 504 505 index = fec_enet_get_bd_index(bdp, &txq->bd); 506 if (((unsigned long) bufaddr) & fep->tx_align || 507 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 508 memcpy(txq->tx_bounce[index], skb->data, buflen); 509 bufaddr = txq->tx_bounce[index]; 510 511 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 512 swap_buffer(bufaddr, buflen); 513 } 514 515 /* Push the data cache so the CPM does not get stale memory data. */ 516 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE); 517 if (dma_mapping_error(&fep->pdev->dev, addr)) { 518 dev_kfree_skb_any(skb); 519 if (net_ratelimit()) 520 netdev_err(ndev, "Tx DMA memory map failed\n"); 521 return NETDEV_TX_OK; 522 } 523 524 if (nr_frags) { 525 last_bdp = fec_enet_txq_submit_frag_skb(txq, skb, ndev); 526 if (IS_ERR(last_bdp)) { 527 dma_unmap_single(&fep->pdev->dev, addr, 528 buflen, DMA_TO_DEVICE); 529 dev_kfree_skb_any(skb); 530 return NETDEV_TX_OK; 531 } 532 } else { 533 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 534 if (fep->bufdesc_ex) { 535 estatus = BD_ENET_TX_INT; 536 if (unlikely(skb_shinfo(skb)->tx_flags & 537 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 538 estatus |= BD_ENET_TX_TS; 539 } 540 } 541 bdp->cbd_bufaddr = cpu_to_fec32(addr); 542 bdp->cbd_datlen = cpu_to_fec16(buflen); 543 544 if (fep->bufdesc_ex) { 545 546 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 547 548 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 549 fep->hwts_tx_en)) 550 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 551 552 if (fep->quirks & FEC_QUIRK_HAS_AVB) 553 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 554 555 if (skb->ip_summed == CHECKSUM_PARTIAL) 556 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 557 558 ebdp->cbd_bdu = 0; 559 ebdp->cbd_esc = cpu_to_fec32(estatus); 560 } 561 562 index = fec_enet_get_bd_index(last_bdp, &txq->bd); 563 /* Save skb pointer */ 564 txq->tx_skbuff[index] = skb; 565 566 /* Make sure the updates to rest of the descriptor are performed before 567 * transferring ownership. 568 */ 569 wmb(); 570 571 /* Send it on its way. Tell FEC it's ready, interrupt when done, 572 * it's the last BD of the frame, and to put the CRC on the end. 573 */ 574 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC); 575 bdp->cbd_sc = cpu_to_fec16(status); 576 577 /* If this was the last BD in the ring, start at the beginning again. */ 578 bdp = fec_enet_get_nextdesc(last_bdp, &txq->bd); 579 580 skb_tx_timestamp(skb); 581 582 /* Make sure the update to bdp and tx_skbuff are performed before 583 * txq->bd.cur. 584 */ 585 wmb(); 586 txq->bd.cur = bdp; 587 588 /* Trigger transmission start */ 589 writel(0, txq->bd.reg_desc_active); 590 591 return 0; 592 } 593 594 static int 595 fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb, 596 struct net_device *ndev, 597 struct bufdesc *bdp, int index, char *data, 598 int size, bool last_tcp, bool is_last) 599 { 600 struct fec_enet_private *fep = netdev_priv(ndev); 601 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 602 unsigned short status; 603 unsigned int estatus = 0; 604 dma_addr_t addr; 605 606 status = fec16_to_cpu(bdp->cbd_sc); 607 status &= ~BD_ENET_TX_STATS; 608 609 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 610 611 if (((unsigned long) data) & fep->tx_align || 612 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 613 memcpy(txq->tx_bounce[index], data, size); 614 data = txq->tx_bounce[index]; 615 616 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 617 swap_buffer(data, size); 618 } 619 620 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE); 621 if (dma_mapping_error(&fep->pdev->dev, addr)) { 622 dev_kfree_skb_any(skb); 623 if (net_ratelimit()) 624 netdev_err(ndev, "Tx DMA memory map failed\n"); 625 return NETDEV_TX_BUSY; 626 } 627 628 bdp->cbd_datlen = cpu_to_fec16(size); 629 bdp->cbd_bufaddr = cpu_to_fec32(addr); 630 631 if (fep->bufdesc_ex) { 632 if (fep->quirks & FEC_QUIRK_HAS_AVB) 633 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 634 if (skb->ip_summed == CHECKSUM_PARTIAL) 635 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 636 ebdp->cbd_bdu = 0; 637 ebdp->cbd_esc = cpu_to_fec32(estatus); 638 } 639 640 /* Handle the last BD specially */ 641 if (last_tcp) 642 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC); 643 if (is_last) { 644 status |= BD_ENET_TX_INTR; 645 if (fep->bufdesc_ex) 646 ebdp->cbd_esc |= cpu_to_fec32(BD_ENET_TX_INT); 647 } 648 649 bdp->cbd_sc = cpu_to_fec16(status); 650 651 return 0; 652 } 653 654 static int 655 fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq, 656 struct sk_buff *skb, struct net_device *ndev, 657 struct bufdesc *bdp, int index) 658 { 659 struct fec_enet_private *fep = netdev_priv(ndev); 660 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 661 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 662 void *bufaddr; 663 unsigned long dmabuf; 664 unsigned short status; 665 unsigned int estatus = 0; 666 667 status = fec16_to_cpu(bdp->cbd_sc); 668 status &= ~BD_ENET_TX_STATS; 669 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 670 671 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 672 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE; 673 if (((unsigned long)bufaddr) & fep->tx_align || 674 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 675 memcpy(txq->tx_bounce[index], skb->data, hdr_len); 676 bufaddr = txq->tx_bounce[index]; 677 678 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 679 swap_buffer(bufaddr, hdr_len); 680 681 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr, 682 hdr_len, DMA_TO_DEVICE); 683 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) { 684 dev_kfree_skb_any(skb); 685 if (net_ratelimit()) 686 netdev_err(ndev, "Tx DMA memory map failed\n"); 687 return NETDEV_TX_BUSY; 688 } 689 } 690 691 bdp->cbd_bufaddr = cpu_to_fec32(dmabuf); 692 bdp->cbd_datlen = cpu_to_fec16(hdr_len); 693 694 if (fep->bufdesc_ex) { 695 if (fep->quirks & FEC_QUIRK_HAS_AVB) 696 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 697 if (skb->ip_summed == CHECKSUM_PARTIAL) 698 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 699 ebdp->cbd_bdu = 0; 700 ebdp->cbd_esc = cpu_to_fec32(estatus); 701 } 702 703 bdp->cbd_sc = cpu_to_fec16(status); 704 705 return 0; 706 } 707 708 static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq, 709 struct sk_buff *skb, 710 struct net_device *ndev) 711 { 712 struct fec_enet_private *fep = netdev_priv(ndev); 713 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 714 int total_len, data_left; 715 struct bufdesc *bdp = txq->bd.cur; 716 struct tso_t tso; 717 unsigned int index = 0; 718 int ret; 719 720 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(txq)) { 721 dev_kfree_skb_any(skb); 722 if (net_ratelimit()) 723 netdev_err(ndev, "NOT enough BD for TSO!\n"); 724 return NETDEV_TX_OK; 725 } 726 727 /* Protocol checksum off-load for TCP and UDP. */ 728 if (fec_enet_clear_csum(skb, ndev)) { 729 dev_kfree_skb_any(skb); 730 return NETDEV_TX_OK; 731 } 732 733 /* Initialize the TSO handler, and prepare the first payload */ 734 tso_start(skb, &tso); 735 736 total_len = skb->len - hdr_len; 737 while (total_len > 0) { 738 char *hdr; 739 740 index = fec_enet_get_bd_index(bdp, &txq->bd); 741 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); 742 total_len -= data_left; 743 744 /* prepare packet headers: MAC + IP + TCP */ 745 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 746 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); 747 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index); 748 if (ret) 749 goto err_release; 750 751 while (data_left > 0) { 752 int size; 753 754 size = min_t(int, tso.size, data_left); 755 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 756 index = fec_enet_get_bd_index(bdp, &txq->bd); 757 ret = fec_enet_txq_put_data_tso(txq, skb, ndev, 758 bdp, index, 759 tso.data, size, 760 size == data_left, 761 total_len == 0); 762 if (ret) 763 goto err_release; 764 765 data_left -= size; 766 tso_build_data(skb, &tso, size); 767 } 768 769 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 770 } 771 772 /* Save skb pointer */ 773 txq->tx_skbuff[index] = skb; 774 775 skb_tx_timestamp(skb); 776 txq->bd.cur = bdp; 777 778 /* Trigger transmission start */ 779 if (!(fep->quirks & FEC_QUIRK_ERR007885) || 780 !readl(txq->bd.reg_desc_active) || 781 !readl(txq->bd.reg_desc_active) || 782 !readl(txq->bd.reg_desc_active) || 783 !readl(txq->bd.reg_desc_active)) 784 writel(0, txq->bd.reg_desc_active); 785 786 return 0; 787 788 err_release: 789 /* TODO: Release all used data descriptors for TSO */ 790 return ret; 791 } 792 793 static netdev_tx_t 794 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) 795 { 796 struct fec_enet_private *fep = netdev_priv(ndev); 797 int entries_free; 798 unsigned short queue; 799 struct fec_enet_priv_tx_q *txq; 800 struct netdev_queue *nq; 801 int ret; 802 803 queue = skb_get_queue_mapping(skb); 804 txq = fep->tx_queue[queue]; 805 nq = netdev_get_tx_queue(ndev, queue); 806 807 if (skb_is_gso(skb)) 808 ret = fec_enet_txq_submit_tso(txq, skb, ndev); 809 else 810 ret = fec_enet_txq_submit_skb(txq, skb, ndev); 811 if (ret) 812 return ret; 813 814 entries_free = fec_enet_get_free_txdesc_num(txq); 815 if (entries_free <= txq->tx_stop_threshold) 816 netif_tx_stop_queue(nq); 817 818 return NETDEV_TX_OK; 819 } 820 821 /* Init RX & TX buffer descriptors 822 */ 823 static void fec_enet_bd_init(struct net_device *dev) 824 { 825 struct fec_enet_private *fep = netdev_priv(dev); 826 struct fec_enet_priv_tx_q *txq; 827 struct fec_enet_priv_rx_q *rxq; 828 struct bufdesc *bdp; 829 unsigned int i; 830 unsigned int q; 831 832 for (q = 0; q < fep->num_rx_queues; q++) { 833 /* Initialize the receive buffer descriptors. */ 834 rxq = fep->rx_queue[q]; 835 bdp = rxq->bd.base; 836 837 for (i = 0; i < rxq->bd.ring_size; i++) { 838 839 /* Initialize the BD for every fragment in the page. */ 840 if (bdp->cbd_bufaddr) 841 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); 842 else 843 bdp->cbd_sc = cpu_to_fec16(0); 844 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 845 } 846 847 /* Set the last buffer to wrap */ 848 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); 849 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 850 851 rxq->bd.cur = rxq->bd.base; 852 } 853 854 for (q = 0; q < fep->num_tx_queues; q++) { 855 /* ...and the same for transmit */ 856 txq = fep->tx_queue[q]; 857 bdp = txq->bd.base; 858 txq->bd.cur = bdp; 859 860 for (i = 0; i < txq->bd.ring_size; i++) { 861 /* Initialize the BD for every fragment in the page. */ 862 bdp->cbd_sc = cpu_to_fec16(0); 863 if (bdp->cbd_bufaddr && 864 !IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr))) 865 dma_unmap_single(&fep->pdev->dev, 866 fec32_to_cpu(bdp->cbd_bufaddr), 867 fec16_to_cpu(bdp->cbd_datlen), 868 DMA_TO_DEVICE); 869 if (txq->tx_skbuff[i]) { 870 dev_kfree_skb_any(txq->tx_skbuff[i]); 871 txq->tx_skbuff[i] = NULL; 872 } 873 bdp->cbd_bufaddr = cpu_to_fec32(0); 874 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 875 } 876 877 /* Set the last buffer to wrap */ 878 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); 879 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 880 txq->dirty_tx = bdp; 881 } 882 } 883 884 static void fec_enet_active_rxring(struct net_device *ndev) 885 { 886 struct fec_enet_private *fep = netdev_priv(ndev); 887 int i; 888 889 for (i = 0; i < fep->num_rx_queues; i++) 890 writel(0, fep->rx_queue[i]->bd.reg_desc_active); 891 } 892 893 static void fec_enet_enable_ring(struct net_device *ndev) 894 { 895 struct fec_enet_private *fep = netdev_priv(ndev); 896 struct fec_enet_priv_tx_q *txq; 897 struct fec_enet_priv_rx_q *rxq; 898 int i; 899 900 for (i = 0; i < fep->num_rx_queues; i++) { 901 rxq = fep->rx_queue[i]; 902 writel(rxq->bd.dma, fep->hwp + FEC_R_DES_START(i)); 903 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i)); 904 905 /* enable DMA1/2 */ 906 if (i) 907 writel(RCMR_MATCHEN | RCMR_CMP(i), 908 fep->hwp + FEC_RCMR(i)); 909 } 910 911 for (i = 0; i < fep->num_tx_queues; i++) { 912 txq = fep->tx_queue[i]; 913 writel(txq->bd.dma, fep->hwp + FEC_X_DES_START(i)); 914 915 /* enable DMA1/2 */ 916 if (i) 917 writel(DMA_CLASS_EN | IDLE_SLOPE(i), 918 fep->hwp + FEC_DMA_CFG(i)); 919 } 920 } 921 922 static void fec_enet_reset_skb(struct net_device *ndev) 923 { 924 struct fec_enet_private *fep = netdev_priv(ndev); 925 struct fec_enet_priv_tx_q *txq; 926 int i, j; 927 928 for (i = 0; i < fep->num_tx_queues; i++) { 929 txq = fep->tx_queue[i]; 930 931 for (j = 0; j < txq->bd.ring_size; j++) { 932 if (txq->tx_skbuff[j]) { 933 dev_kfree_skb_any(txq->tx_skbuff[j]); 934 txq->tx_skbuff[j] = NULL; 935 } 936 } 937 } 938 } 939 940 /* 941 * This function is called to start or restart the FEC during a link 942 * change, transmit timeout, or to reconfigure the FEC. The network 943 * packet processing for this device must be stopped before this call. 944 */ 945 static void 946 fec_restart(struct net_device *ndev) 947 { 948 struct fec_enet_private *fep = netdev_priv(ndev); 949 u32 val; 950 u32 temp_mac[2]; 951 u32 rcntl = OPT_FRAME_SIZE | 0x04; 952 u32 ecntl = 0x2; /* ETHEREN */ 953 954 /* Whack a reset. We should wait for this. 955 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC 956 * instead of reset MAC itself. 957 */ 958 if (fep->quirks & FEC_QUIRK_HAS_AVB) { 959 writel(0, fep->hwp + FEC_ECNTRL); 960 } else { 961 writel(1, fep->hwp + FEC_ECNTRL); 962 udelay(10); 963 } 964 965 /* 966 * enet-mac reset will reset mac address registers too, 967 * so need to reconfigure it. 968 */ 969 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN); 970 writel((__force u32)cpu_to_be32(temp_mac[0]), 971 fep->hwp + FEC_ADDR_LOW); 972 writel((__force u32)cpu_to_be32(temp_mac[1]), 973 fep->hwp + FEC_ADDR_HIGH); 974 975 /* Clear any outstanding interrupt, except MDIO. */ 976 writel((0xffffffff & ~FEC_ENET_MII), fep->hwp + FEC_IEVENT); 977 978 fec_enet_bd_init(ndev); 979 980 fec_enet_enable_ring(ndev); 981 982 /* Reset tx SKB buffers. */ 983 fec_enet_reset_skb(ndev); 984 985 /* Enable MII mode */ 986 if (fep->full_duplex == DUPLEX_FULL) { 987 /* FD enable */ 988 writel(0x04, fep->hwp + FEC_X_CNTRL); 989 } else { 990 /* No Rcv on Xmit */ 991 rcntl |= 0x02; 992 writel(0x0, fep->hwp + FEC_X_CNTRL); 993 } 994 995 /* Set MII speed */ 996 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 997 998 #if !defined(CONFIG_M5272) 999 if (fep->quirks & FEC_QUIRK_HAS_RACC) { 1000 val = readl(fep->hwp + FEC_RACC); 1001 /* align IP header */ 1002 val |= FEC_RACC_SHIFT16; 1003 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED) 1004 /* set RX checksum */ 1005 val |= FEC_RACC_OPTIONS; 1006 else 1007 val &= ~FEC_RACC_OPTIONS; 1008 writel(val, fep->hwp + FEC_RACC); 1009 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_FTRL); 1010 } 1011 #endif 1012 1013 /* 1014 * The phy interface and speed need to get configured 1015 * differently on enet-mac. 1016 */ 1017 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 1018 /* Enable flow control and length check */ 1019 rcntl |= 0x40000000 | 0x00000020; 1020 1021 /* RGMII, RMII or MII */ 1022 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII || 1023 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 1024 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID || 1025 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) 1026 rcntl |= (1 << 6); 1027 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 1028 rcntl |= (1 << 8); 1029 else 1030 rcntl &= ~(1 << 8); 1031 1032 /* 1G, 100M or 10M */ 1033 if (ndev->phydev) { 1034 if (ndev->phydev->speed == SPEED_1000) 1035 ecntl |= (1 << 5); 1036 else if (ndev->phydev->speed == SPEED_100) 1037 rcntl &= ~(1 << 9); 1038 else 1039 rcntl |= (1 << 9); 1040 } 1041 } else { 1042 #ifdef FEC_MIIGSK_ENR 1043 if (fep->quirks & FEC_QUIRK_USE_GASKET) { 1044 u32 cfgr; 1045 /* disable the gasket and wait */ 1046 writel(0, fep->hwp + FEC_MIIGSK_ENR); 1047 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4) 1048 udelay(1); 1049 1050 /* 1051 * configure the gasket: 1052 * RMII, 50 MHz, no loopback, no echo 1053 * MII, 25 MHz, no loopback, no echo 1054 */ 1055 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 1056 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII; 1057 if (ndev->phydev && ndev->phydev->speed == SPEED_10) 1058 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M; 1059 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR); 1060 1061 /* re-enable the gasket */ 1062 writel(2, fep->hwp + FEC_MIIGSK_ENR); 1063 } 1064 #endif 1065 } 1066 1067 #if !defined(CONFIG_M5272) 1068 /* enable pause frame*/ 1069 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) || 1070 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) && 1071 ndev->phydev && ndev->phydev->pause)) { 1072 rcntl |= FEC_ENET_FCE; 1073 1074 /* set FIFO threshold parameter to reduce overrun */ 1075 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM); 1076 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL); 1077 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM); 1078 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL); 1079 1080 /* OPD */ 1081 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD); 1082 } else { 1083 rcntl &= ~FEC_ENET_FCE; 1084 } 1085 #endif /* !defined(CONFIG_M5272) */ 1086 1087 writel(rcntl, fep->hwp + FEC_R_CNTRL); 1088 1089 /* Setup multicast filter. */ 1090 set_multicast_list(ndev); 1091 #ifndef CONFIG_M5272 1092 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); 1093 writel(0, fep->hwp + FEC_HASH_TABLE_LOW); 1094 #endif 1095 1096 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 1097 /* enable ENET endian swap */ 1098 ecntl |= (1 << 8); 1099 /* enable ENET store and forward mode */ 1100 writel(1 << 8, fep->hwp + FEC_X_WMRK); 1101 } 1102 1103 if (fep->bufdesc_ex) 1104 ecntl |= (1 << 4); 1105 1106 #ifndef CONFIG_M5272 1107 /* Enable the MIB statistic event counters */ 1108 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT); 1109 #endif 1110 1111 /* And last, enable the transmit and receive processing */ 1112 writel(ecntl, fep->hwp + FEC_ECNTRL); 1113 fec_enet_active_rxring(ndev); 1114 1115 if (fep->bufdesc_ex) 1116 fec_ptp_start_cyclecounter(ndev); 1117 1118 /* Enable interrupts we wish to service */ 1119 if (fep->link) 1120 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1121 else 1122 writel(0, fep->hwp + FEC_IMASK); 1123 1124 /* Init the interrupt coalescing */ 1125 fec_enet_itr_coal_init(ndev); 1126 1127 } 1128 1129 static void fec_enet_stop_mode(struct fec_enet_private *fep, bool enabled) 1130 { 1131 struct fec_platform_data *pdata = fep->pdev->dev.platform_data; 1132 struct fec_stop_mode_gpr *stop_gpr = &fep->stop_gpr; 1133 1134 if (stop_gpr->gpr) { 1135 if (enabled) 1136 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg, 1137 BIT(stop_gpr->bit), 1138 BIT(stop_gpr->bit)); 1139 else 1140 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg, 1141 BIT(stop_gpr->bit), 0); 1142 } else if (pdata && pdata->sleep_mode_enable) { 1143 pdata->sleep_mode_enable(enabled); 1144 } 1145 } 1146 1147 static void 1148 fec_stop(struct net_device *ndev) 1149 { 1150 struct fec_enet_private *fep = netdev_priv(ndev); 1151 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8); 1152 u32 val; 1153 1154 /* We cannot expect a graceful transmit stop without link !!! */ 1155 if (fep->link) { 1156 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ 1157 udelay(10); 1158 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) 1159 netdev_err(ndev, "Graceful transmit stop did not complete!\n"); 1160 } 1161 1162 /* Whack a reset. We should wait for this. 1163 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC 1164 * instead of reset MAC itself. 1165 */ 1166 if (!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1167 if (fep->quirks & FEC_QUIRK_HAS_AVB) { 1168 writel(0, fep->hwp + FEC_ECNTRL); 1169 } else { 1170 writel(1, fep->hwp + FEC_ECNTRL); 1171 udelay(10); 1172 } 1173 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1174 } else { 1175 writel(FEC_DEFAULT_IMASK | FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK); 1176 val = readl(fep->hwp + FEC_ECNTRL); 1177 val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP); 1178 writel(val, fep->hwp + FEC_ECNTRL); 1179 fec_enet_stop_mode(fep, true); 1180 } 1181 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1182 1183 /* We have to keep ENET enabled to have MII interrupt stay working */ 1184 if (fep->quirks & FEC_QUIRK_ENET_MAC && 1185 !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1186 writel(2, fep->hwp + FEC_ECNTRL); 1187 writel(rmii_mode, fep->hwp + FEC_R_CNTRL); 1188 } 1189 } 1190 1191 1192 static void 1193 fec_timeout(struct net_device *ndev, unsigned int txqueue) 1194 { 1195 struct fec_enet_private *fep = netdev_priv(ndev); 1196 1197 fec_dump(ndev); 1198 1199 ndev->stats.tx_errors++; 1200 1201 schedule_work(&fep->tx_timeout_work); 1202 } 1203 1204 static void fec_enet_timeout_work(struct work_struct *work) 1205 { 1206 struct fec_enet_private *fep = 1207 container_of(work, struct fec_enet_private, tx_timeout_work); 1208 struct net_device *ndev = fep->netdev; 1209 1210 rtnl_lock(); 1211 if (netif_device_present(ndev) || netif_running(ndev)) { 1212 napi_disable(&fep->napi); 1213 netif_tx_lock_bh(ndev); 1214 fec_restart(ndev); 1215 netif_tx_wake_all_queues(ndev); 1216 netif_tx_unlock_bh(ndev); 1217 napi_enable(&fep->napi); 1218 } 1219 rtnl_unlock(); 1220 } 1221 1222 static void 1223 fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts, 1224 struct skb_shared_hwtstamps *hwtstamps) 1225 { 1226 unsigned long flags; 1227 u64 ns; 1228 1229 spin_lock_irqsave(&fep->tmreg_lock, flags); 1230 ns = timecounter_cyc2time(&fep->tc, ts); 1231 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 1232 1233 memset(hwtstamps, 0, sizeof(*hwtstamps)); 1234 hwtstamps->hwtstamp = ns_to_ktime(ns); 1235 } 1236 1237 static void 1238 fec_enet_tx_queue(struct net_device *ndev, u16 queue_id) 1239 { 1240 struct fec_enet_private *fep; 1241 struct bufdesc *bdp; 1242 unsigned short status; 1243 struct sk_buff *skb; 1244 struct fec_enet_priv_tx_q *txq; 1245 struct netdev_queue *nq; 1246 int index = 0; 1247 int entries_free; 1248 1249 fep = netdev_priv(ndev); 1250 1251 queue_id = FEC_ENET_GET_QUQUE(queue_id); 1252 1253 txq = fep->tx_queue[queue_id]; 1254 /* get next bdp of dirty_tx */ 1255 nq = netdev_get_tx_queue(ndev, queue_id); 1256 bdp = txq->dirty_tx; 1257 1258 /* get next bdp of dirty_tx */ 1259 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1260 1261 while (bdp != READ_ONCE(txq->bd.cur)) { 1262 /* Order the load of bd.cur and cbd_sc */ 1263 rmb(); 1264 status = fec16_to_cpu(READ_ONCE(bdp->cbd_sc)); 1265 if (status & BD_ENET_TX_READY) 1266 break; 1267 1268 index = fec_enet_get_bd_index(bdp, &txq->bd); 1269 1270 skb = txq->tx_skbuff[index]; 1271 txq->tx_skbuff[index] = NULL; 1272 if (!IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr))) 1273 dma_unmap_single(&fep->pdev->dev, 1274 fec32_to_cpu(bdp->cbd_bufaddr), 1275 fec16_to_cpu(bdp->cbd_datlen), 1276 DMA_TO_DEVICE); 1277 bdp->cbd_bufaddr = cpu_to_fec32(0); 1278 if (!skb) 1279 goto skb_done; 1280 1281 /* Check for errors. */ 1282 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | 1283 BD_ENET_TX_RL | BD_ENET_TX_UN | 1284 BD_ENET_TX_CSL)) { 1285 ndev->stats.tx_errors++; 1286 if (status & BD_ENET_TX_HB) /* No heartbeat */ 1287 ndev->stats.tx_heartbeat_errors++; 1288 if (status & BD_ENET_TX_LC) /* Late collision */ 1289 ndev->stats.tx_window_errors++; 1290 if (status & BD_ENET_TX_RL) /* Retrans limit */ 1291 ndev->stats.tx_aborted_errors++; 1292 if (status & BD_ENET_TX_UN) /* Underrun */ 1293 ndev->stats.tx_fifo_errors++; 1294 if (status & BD_ENET_TX_CSL) /* Carrier lost */ 1295 ndev->stats.tx_carrier_errors++; 1296 } else { 1297 ndev->stats.tx_packets++; 1298 ndev->stats.tx_bytes += skb->len; 1299 } 1300 1301 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) && 1302 fep->bufdesc_ex) { 1303 struct skb_shared_hwtstamps shhwtstamps; 1304 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1305 1306 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), &shhwtstamps); 1307 skb_tstamp_tx(skb, &shhwtstamps); 1308 } 1309 1310 /* Deferred means some collisions occurred during transmit, 1311 * but we eventually sent the packet OK. 1312 */ 1313 if (status & BD_ENET_TX_DEF) 1314 ndev->stats.collisions++; 1315 1316 /* Free the sk buffer associated with this last transmit */ 1317 dev_kfree_skb_any(skb); 1318 skb_done: 1319 /* Make sure the update to bdp and tx_skbuff are performed 1320 * before dirty_tx 1321 */ 1322 wmb(); 1323 txq->dirty_tx = bdp; 1324 1325 /* Update pointer to next buffer descriptor to be transmitted */ 1326 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1327 1328 /* Since we have freed up a buffer, the ring is no longer full 1329 */ 1330 if (netif_tx_queue_stopped(nq)) { 1331 entries_free = fec_enet_get_free_txdesc_num(txq); 1332 if (entries_free >= txq->tx_wake_threshold) 1333 netif_tx_wake_queue(nq); 1334 } 1335 } 1336 1337 /* ERR006358: Keep the transmitter going */ 1338 if (bdp != txq->bd.cur && 1339 readl(txq->bd.reg_desc_active) == 0) 1340 writel(0, txq->bd.reg_desc_active); 1341 } 1342 1343 static void 1344 fec_enet_tx(struct net_device *ndev) 1345 { 1346 struct fec_enet_private *fep = netdev_priv(ndev); 1347 u16 queue_id; 1348 /* First process class A queue, then Class B and Best Effort queue */ 1349 for_each_set_bit(queue_id, &fep->work_tx, FEC_ENET_MAX_TX_QS) { 1350 clear_bit(queue_id, &fep->work_tx); 1351 fec_enet_tx_queue(ndev, queue_id); 1352 } 1353 return; 1354 } 1355 1356 static int 1357 fec_enet_new_rxbdp(struct net_device *ndev, struct bufdesc *bdp, struct sk_buff *skb) 1358 { 1359 struct fec_enet_private *fep = netdev_priv(ndev); 1360 int off; 1361 1362 off = ((unsigned long)skb->data) & fep->rx_align; 1363 if (off) 1364 skb_reserve(skb, fep->rx_align + 1 - off); 1365 1366 bdp->cbd_bufaddr = cpu_to_fec32(dma_map_single(&fep->pdev->dev, skb->data, FEC_ENET_RX_FRSIZE - fep->rx_align, DMA_FROM_DEVICE)); 1367 if (dma_mapping_error(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr))) { 1368 if (net_ratelimit()) 1369 netdev_err(ndev, "Rx DMA memory map failed\n"); 1370 return -ENOMEM; 1371 } 1372 1373 return 0; 1374 } 1375 1376 static bool fec_enet_copybreak(struct net_device *ndev, struct sk_buff **skb, 1377 struct bufdesc *bdp, u32 length, bool swap) 1378 { 1379 struct fec_enet_private *fep = netdev_priv(ndev); 1380 struct sk_buff *new_skb; 1381 1382 if (length > fep->rx_copybreak) 1383 return false; 1384 1385 new_skb = netdev_alloc_skb(ndev, length); 1386 if (!new_skb) 1387 return false; 1388 1389 dma_sync_single_for_cpu(&fep->pdev->dev, 1390 fec32_to_cpu(bdp->cbd_bufaddr), 1391 FEC_ENET_RX_FRSIZE - fep->rx_align, 1392 DMA_FROM_DEVICE); 1393 if (!swap) 1394 memcpy(new_skb->data, (*skb)->data, length); 1395 else 1396 swap_buffer2(new_skb->data, (*skb)->data, length); 1397 *skb = new_skb; 1398 1399 return true; 1400 } 1401 1402 /* During a receive, the bd_rx.cur points to the current incoming buffer. 1403 * When we update through the ring, if the next incoming buffer has 1404 * not been given to the system, we just set the empty indicator, 1405 * effectively tossing the packet. 1406 */ 1407 static int 1408 fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id) 1409 { 1410 struct fec_enet_private *fep = netdev_priv(ndev); 1411 struct fec_enet_priv_rx_q *rxq; 1412 struct bufdesc *bdp; 1413 unsigned short status; 1414 struct sk_buff *skb_new = NULL; 1415 struct sk_buff *skb; 1416 ushort pkt_len; 1417 __u8 *data; 1418 int pkt_received = 0; 1419 struct bufdesc_ex *ebdp = NULL; 1420 bool vlan_packet_rcvd = false; 1421 u16 vlan_tag; 1422 int index = 0; 1423 bool is_copybreak; 1424 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME; 1425 1426 #ifdef CONFIG_M532x 1427 flush_cache_all(); 1428 #endif 1429 queue_id = FEC_ENET_GET_QUQUE(queue_id); 1430 rxq = fep->rx_queue[queue_id]; 1431 1432 /* First, grab all of the stats for the incoming packet. 1433 * These get messed up if we get called due to a busy condition. 1434 */ 1435 bdp = rxq->bd.cur; 1436 1437 while (!((status = fec16_to_cpu(bdp->cbd_sc)) & BD_ENET_RX_EMPTY)) { 1438 1439 if (pkt_received >= budget) 1440 break; 1441 pkt_received++; 1442 1443 writel(FEC_ENET_RXF, fep->hwp + FEC_IEVENT); 1444 1445 /* Check for errors. */ 1446 status ^= BD_ENET_RX_LAST; 1447 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | 1448 BD_ENET_RX_CR | BD_ENET_RX_OV | BD_ENET_RX_LAST | 1449 BD_ENET_RX_CL)) { 1450 ndev->stats.rx_errors++; 1451 if (status & BD_ENET_RX_OV) { 1452 /* FIFO overrun */ 1453 ndev->stats.rx_fifo_errors++; 1454 goto rx_processing_done; 1455 } 1456 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH 1457 | BD_ENET_RX_LAST)) { 1458 /* Frame too long or too short. */ 1459 ndev->stats.rx_length_errors++; 1460 if (status & BD_ENET_RX_LAST) 1461 netdev_err(ndev, "rcv is not +last\n"); 1462 } 1463 if (status & BD_ENET_RX_CR) /* CRC Error */ 1464 ndev->stats.rx_crc_errors++; 1465 /* Report late collisions as a frame error. */ 1466 if (status & (BD_ENET_RX_NO | BD_ENET_RX_CL)) 1467 ndev->stats.rx_frame_errors++; 1468 goto rx_processing_done; 1469 } 1470 1471 /* Process the incoming frame. */ 1472 ndev->stats.rx_packets++; 1473 pkt_len = fec16_to_cpu(bdp->cbd_datlen); 1474 ndev->stats.rx_bytes += pkt_len; 1475 1476 index = fec_enet_get_bd_index(bdp, &rxq->bd); 1477 skb = rxq->rx_skbuff[index]; 1478 1479 /* The packet length includes FCS, but we don't want to 1480 * include that when passing upstream as it messes up 1481 * bridging applications. 1482 */ 1483 is_copybreak = fec_enet_copybreak(ndev, &skb, bdp, pkt_len - 4, 1484 need_swap); 1485 if (!is_copybreak) { 1486 skb_new = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE); 1487 if (unlikely(!skb_new)) { 1488 ndev->stats.rx_dropped++; 1489 goto rx_processing_done; 1490 } 1491 dma_unmap_single(&fep->pdev->dev, 1492 fec32_to_cpu(bdp->cbd_bufaddr), 1493 FEC_ENET_RX_FRSIZE - fep->rx_align, 1494 DMA_FROM_DEVICE); 1495 } 1496 1497 prefetch(skb->data - NET_IP_ALIGN); 1498 skb_put(skb, pkt_len - 4); 1499 data = skb->data; 1500 1501 if (!is_copybreak && need_swap) 1502 swap_buffer(data, pkt_len); 1503 1504 #if !defined(CONFIG_M5272) 1505 if (fep->quirks & FEC_QUIRK_HAS_RACC) 1506 data = skb_pull_inline(skb, 2); 1507 #endif 1508 1509 /* Extract the enhanced buffer descriptor */ 1510 ebdp = NULL; 1511 if (fep->bufdesc_ex) 1512 ebdp = (struct bufdesc_ex *)bdp; 1513 1514 /* If this is a VLAN packet remove the VLAN Tag */ 1515 vlan_packet_rcvd = false; 1516 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) && 1517 fep->bufdesc_ex && 1518 (ebdp->cbd_esc & cpu_to_fec32(BD_ENET_RX_VLAN))) { 1519 /* Push and remove the vlan tag */ 1520 struct vlan_hdr *vlan_header = 1521 (struct vlan_hdr *) (data + ETH_HLEN); 1522 vlan_tag = ntohs(vlan_header->h_vlan_TCI); 1523 1524 vlan_packet_rcvd = true; 1525 1526 memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2); 1527 skb_pull(skb, VLAN_HLEN); 1528 } 1529 1530 skb->protocol = eth_type_trans(skb, ndev); 1531 1532 /* Get receive timestamp from the skb */ 1533 if (fep->hwts_rx_en && fep->bufdesc_ex) 1534 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), 1535 skb_hwtstamps(skb)); 1536 1537 if (fep->bufdesc_ex && 1538 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) { 1539 if (!(ebdp->cbd_esc & cpu_to_fec32(FLAG_RX_CSUM_ERROR))) { 1540 /* don't check it */ 1541 skb->ip_summed = CHECKSUM_UNNECESSARY; 1542 } else { 1543 skb_checksum_none_assert(skb); 1544 } 1545 } 1546 1547 /* Handle received VLAN packets */ 1548 if (vlan_packet_rcvd) 1549 __vlan_hwaccel_put_tag(skb, 1550 htons(ETH_P_8021Q), 1551 vlan_tag); 1552 1553 napi_gro_receive(&fep->napi, skb); 1554 1555 if (is_copybreak) { 1556 dma_sync_single_for_device(&fep->pdev->dev, 1557 fec32_to_cpu(bdp->cbd_bufaddr), 1558 FEC_ENET_RX_FRSIZE - fep->rx_align, 1559 DMA_FROM_DEVICE); 1560 } else { 1561 rxq->rx_skbuff[index] = skb_new; 1562 fec_enet_new_rxbdp(ndev, bdp, skb_new); 1563 } 1564 1565 rx_processing_done: 1566 /* Clear the status flags for this buffer */ 1567 status &= ~BD_ENET_RX_STATS; 1568 1569 /* Mark the buffer empty */ 1570 status |= BD_ENET_RX_EMPTY; 1571 1572 if (fep->bufdesc_ex) { 1573 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1574 1575 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); 1576 ebdp->cbd_prot = 0; 1577 ebdp->cbd_bdu = 0; 1578 } 1579 /* Make sure the updates to rest of the descriptor are 1580 * performed before transferring ownership. 1581 */ 1582 wmb(); 1583 bdp->cbd_sc = cpu_to_fec16(status); 1584 1585 /* Update BD pointer to next entry */ 1586 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 1587 1588 /* Doing this here will keep the FEC running while we process 1589 * incoming frames. On a heavily loaded network, we should be 1590 * able to keep up at the expense of system resources. 1591 */ 1592 writel(0, rxq->bd.reg_desc_active); 1593 } 1594 rxq->bd.cur = bdp; 1595 return pkt_received; 1596 } 1597 1598 static int 1599 fec_enet_rx(struct net_device *ndev, int budget) 1600 { 1601 int pkt_received = 0; 1602 u16 queue_id; 1603 struct fec_enet_private *fep = netdev_priv(ndev); 1604 1605 for_each_set_bit(queue_id, &fep->work_rx, FEC_ENET_MAX_RX_QS) { 1606 int ret; 1607 1608 ret = fec_enet_rx_queue(ndev, 1609 budget - pkt_received, queue_id); 1610 1611 if (ret < budget - pkt_received) 1612 clear_bit(queue_id, &fep->work_rx); 1613 1614 pkt_received += ret; 1615 } 1616 return pkt_received; 1617 } 1618 1619 static bool 1620 fec_enet_collect_events(struct fec_enet_private *fep, uint int_events) 1621 { 1622 if (int_events == 0) 1623 return false; 1624 1625 if (int_events & FEC_ENET_RXF_0) 1626 fep->work_rx |= (1 << 2); 1627 if (int_events & FEC_ENET_RXF_1) 1628 fep->work_rx |= (1 << 0); 1629 if (int_events & FEC_ENET_RXF_2) 1630 fep->work_rx |= (1 << 1); 1631 1632 if (int_events & FEC_ENET_TXF_0) 1633 fep->work_tx |= (1 << 2); 1634 if (int_events & FEC_ENET_TXF_1) 1635 fep->work_tx |= (1 << 0); 1636 if (int_events & FEC_ENET_TXF_2) 1637 fep->work_tx |= (1 << 1); 1638 1639 return true; 1640 } 1641 1642 static irqreturn_t 1643 fec_enet_interrupt(int irq, void *dev_id) 1644 { 1645 struct net_device *ndev = dev_id; 1646 struct fec_enet_private *fep = netdev_priv(ndev); 1647 uint int_events; 1648 irqreturn_t ret = IRQ_NONE; 1649 1650 int_events = readl(fep->hwp + FEC_IEVENT); 1651 1652 /* Don't clear MDIO events, we poll for those */ 1653 int_events &= ~FEC_ENET_MII; 1654 1655 writel(int_events, fep->hwp + FEC_IEVENT); 1656 fec_enet_collect_events(fep, int_events); 1657 1658 if ((fep->work_tx || fep->work_rx) && fep->link) { 1659 ret = IRQ_HANDLED; 1660 1661 if (napi_schedule_prep(&fep->napi)) { 1662 /* Disable interrupts */ 1663 writel(0, fep->hwp + FEC_IMASK); 1664 __napi_schedule(&fep->napi); 1665 } 1666 } 1667 1668 return ret; 1669 } 1670 1671 static int fec_enet_rx_napi(struct napi_struct *napi, int budget) 1672 { 1673 struct net_device *ndev = napi->dev; 1674 struct fec_enet_private *fep = netdev_priv(ndev); 1675 int pkts; 1676 1677 pkts = fec_enet_rx(ndev, budget); 1678 1679 fec_enet_tx(ndev); 1680 1681 if (pkts < budget) { 1682 napi_complete_done(napi, pkts); 1683 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1684 } 1685 return pkts; 1686 } 1687 1688 /* ------------------------------------------------------------------------- */ 1689 static void fec_get_mac(struct net_device *ndev) 1690 { 1691 struct fec_enet_private *fep = netdev_priv(ndev); 1692 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev); 1693 unsigned char *iap, tmpaddr[ETH_ALEN]; 1694 1695 /* 1696 * try to get mac address in following order: 1697 * 1698 * 1) module parameter via kernel command line in form 1699 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0 1700 */ 1701 iap = macaddr; 1702 1703 /* 1704 * 2) from device tree data 1705 */ 1706 if (!is_valid_ether_addr(iap)) { 1707 struct device_node *np = fep->pdev->dev.of_node; 1708 if (np) { 1709 const char *mac = of_get_mac_address(np); 1710 if (!IS_ERR(mac)) 1711 iap = (unsigned char *) mac; 1712 } 1713 } 1714 1715 /* 1716 * 3) from flash or fuse (via platform data) 1717 */ 1718 if (!is_valid_ether_addr(iap)) { 1719 #ifdef CONFIG_M5272 1720 if (FEC_FLASHMAC) 1721 iap = (unsigned char *)FEC_FLASHMAC; 1722 #else 1723 if (pdata) 1724 iap = (unsigned char *)&pdata->mac; 1725 #endif 1726 } 1727 1728 /* 1729 * 4) FEC mac registers set by bootloader 1730 */ 1731 if (!is_valid_ether_addr(iap)) { 1732 *((__be32 *) &tmpaddr[0]) = 1733 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW)); 1734 *((__be16 *) &tmpaddr[4]) = 1735 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16); 1736 iap = &tmpaddr[0]; 1737 } 1738 1739 /* 1740 * 5) random mac address 1741 */ 1742 if (!is_valid_ether_addr(iap)) { 1743 /* Report it and use a random ethernet address instead */ 1744 dev_err(&fep->pdev->dev, "Invalid MAC address: %pM\n", iap); 1745 eth_hw_addr_random(ndev); 1746 dev_info(&fep->pdev->dev, "Using random MAC address: %pM\n", 1747 ndev->dev_addr); 1748 return; 1749 } 1750 1751 memcpy(ndev->dev_addr, iap, ETH_ALEN); 1752 1753 /* Adjust MAC if using macaddr */ 1754 if (iap == macaddr) 1755 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id; 1756 } 1757 1758 /* ------------------------------------------------------------------------- */ 1759 1760 /* 1761 * Phy section 1762 */ 1763 static void fec_enet_adjust_link(struct net_device *ndev) 1764 { 1765 struct fec_enet_private *fep = netdev_priv(ndev); 1766 struct phy_device *phy_dev = ndev->phydev; 1767 int status_change = 0; 1768 1769 /* 1770 * If the netdev is down, or is going down, we're not interested 1771 * in link state events, so just mark our idea of the link as down 1772 * and ignore the event. 1773 */ 1774 if (!netif_running(ndev) || !netif_device_present(ndev)) { 1775 fep->link = 0; 1776 } else if (phy_dev->link) { 1777 if (!fep->link) { 1778 fep->link = phy_dev->link; 1779 status_change = 1; 1780 } 1781 1782 if (fep->full_duplex != phy_dev->duplex) { 1783 fep->full_duplex = phy_dev->duplex; 1784 status_change = 1; 1785 } 1786 1787 if (phy_dev->speed != fep->speed) { 1788 fep->speed = phy_dev->speed; 1789 status_change = 1; 1790 } 1791 1792 /* if any of the above changed restart the FEC */ 1793 if (status_change) { 1794 napi_disable(&fep->napi); 1795 netif_tx_lock_bh(ndev); 1796 fec_restart(ndev); 1797 netif_tx_wake_all_queues(ndev); 1798 netif_tx_unlock_bh(ndev); 1799 napi_enable(&fep->napi); 1800 } 1801 } else { 1802 if (fep->link) { 1803 napi_disable(&fep->napi); 1804 netif_tx_lock_bh(ndev); 1805 fec_stop(ndev); 1806 netif_tx_unlock_bh(ndev); 1807 napi_enable(&fep->napi); 1808 fep->link = phy_dev->link; 1809 status_change = 1; 1810 } 1811 } 1812 1813 if (status_change) 1814 phy_print_status(phy_dev); 1815 } 1816 1817 static int fec_enet_mdio_wait(struct fec_enet_private *fep) 1818 { 1819 uint ievent; 1820 int ret; 1821 1822 ret = readl_poll_timeout_atomic(fep->hwp + FEC_IEVENT, ievent, 1823 ievent & FEC_ENET_MII, 2, 30000); 1824 1825 if (!ret) 1826 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); 1827 1828 return ret; 1829 } 1830 1831 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) 1832 { 1833 struct fec_enet_private *fep = bus->priv; 1834 struct device *dev = &fep->pdev->dev; 1835 int ret = 0, frame_start, frame_addr, frame_op; 1836 bool is_c45 = !!(regnum & MII_ADDR_C45); 1837 1838 ret = pm_runtime_get_sync(dev); 1839 if (ret < 0) 1840 return ret; 1841 1842 if (is_c45) { 1843 frame_start = FEC_MMFR_ST_C45; 1844 1845 /* write address */ 1846 frame_addr = (regnum >> 16); 1847 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE | 1848 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 1849 FEC_MMFR_TA | (regnum & 0xFFFF), 1850 fep->hwp + FEC_MII_DATA); 1851 1852 /* wait for end of transfer */ 1853 ret = fec_enet_mdio_wait(fep); 1854 if (ret) { 1855 netdev_err(fep->netdev, "MDIO address write timeout\n"); 1856 goto out; 1857 } 1858 1859 frame_op = FEC_MMFR_OP_READ_C45; 1860 1861 } else { 1862 /* C22 read */ 1863 frame_op = FEC_MMFR_OP_READ; 1864 frame_start = FEC_MMFR_ST; 1865 frame_addr = regnum; 1866 } 1867 1868 /* start a read op */ 1869 writel(frame_start | frame_op | 1870 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 1871 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); 1872 1873 /* wait for end of transfer */ 1874 ret = fec_enet_mdio_wait(fep); 1875 if (ret) { 1876 netdev_err(fep->netdev, "MDIO read timeout\n"); 1877 goto out; 1878 } 1879 1880 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); 1881 1882 out: 1883 pm_runtime_mark_last_busy(dev); 1884 pm_runtime_put_autosuspend(dev); 1885 1886 return ret; 1887 } 1888 1889 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, 1890 u16 value) 1891 { 1892 struct fec_enet_private *fep = bus->priv; 1893 struct device *dev = &fep->pdev->dev; 1894 int ret, frame_start, frame_addr; 1895 bool is_c45 = !!(regnum & MII_ADDR_C45); 1896 1897 ret = pm_runtime_get_sync(dev); 1898 if (ret < 0) 1899 return ret; 1900 else 1901 ret = 0; 1902 1903 if (is_c45) { 1904 frame_start = FEC_MMFR_ST_C45; 1905 1906 /* write address */ 1907 frame_addr = (regnum >> 16); 1908 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE | 1909 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 1910 FEC_MMFR_TA | (regnum & 0xFFFF), 1911 fep->hwp + FEC_MII_DATA); 1912 1913 /* wait for end of transfer */ 1914 ret = fec_enet_mdio_wait(fep); 1915 if (ret) { 1916 netdev_err(fep->netdev, "MDIO address write timeout\n"); 1917 goto out; 1918 } 1919 } else { 1920 /* C22 write */ 1921 frame_start = FEC_MMFR_ST; 1922 frame_addr = regnum; 1923 } 1924 1925 /* start a write op */ 1926 writel(frame_start | FEC_MMFR_OP_WRITE | 1927 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 1928 FEC_MMFR_TA | FEC_MMFR_DATA(value), 1929 fep->hwp + FEC_MII_DATA); 1930 1931 /* wait for end of transfer */ 1932 ret = fec_enet_mdio_wait(fep); 1933 if (ret) 1934 netdev_err(fep->netdev, "MDIO write timeout\n"); 1935 1936 out: 1937 pm_runtime_mark_last_busy(dev); 1938 pm_runtime_put_autosuspend(dev); 1939 1940 return ret; 1941 } 1942 1943 static int fec_enet_clk_enable(struct net_device *ndev, bool enable) 1944 { 1945 struct fec_enet_private *fep = netdev_priv(ndev); 1946 int ret; 1947 1948 if (enable) { 1949 ret = clk_prepare_enable(fep->clk_enet_out); 1950 if (ret) 1951 return ret; 1952 1953 if (fep->clk_ptp) { 1954 mutex_lock(&fep->ptp_clk_mutex); 1955 ret = clk_prepare_enable(fep->clk_ptp); 1956 if (ret) { 1957 mutex_unlock(&fep->ptp_clk_mutex); 1958 goto failed_clk_ptp; 1959 } else { 1960 fep->ptp_clk_on = true; 1961 } 1962 mutex_unlock(&fep->ptp_clk_mutex); 1963 } 1964 1965 ret = clk_prepare_enable(fep->clk_ref); 1966 if (ret) 1967 goto failed_clk_ref; 1968 1969 phy_reset_after_clk_enable(ndev->phydev); 1970 } else { 1971 clk_disable_unprepare(fep->clk_enet_out); 1972 if (fep->clk_ptp) { 1973 mutex_lock(&fep->ptp_clk_mutex); 1974 clk_disable_unprepare(fep->clk_ptp); 1975 fep->ptp_clk_on = false; 1976 mutex_unlock(&fep->ptp_clk_mutex); 1977 } 1978 clk_disable_unprepare(fep->clk_ref); 1979 } 1980 1981 return 0; 1982 1983 failed_clk_ref: 1984 if (fep->clk_ptp) { 1985 mutex_lock(&fep->ptp_clk_mutex); 1986 clk_disable_unprepare(fep->clk_ptp); 1987 fep->ptp_clk_on = false; 1988 mutex_unlock(&fep->ptp_clk_mutex); 1989 } 1990 failed_clk_ptp: 1991 if (fep->clk_enet_out) 1992 clk_disable_unprepare(fep->clk_enet_out); 1993 1994 return ret; 1995 } 1996 1997 static int fec_enet_mii_probe(struct net_device *ndev) 1998 { 1999 struct fec_enet_private *fep = netdev_priv(ndev); 2000 struct phy_device *phy_dev = NULL; 2001 char mdio_bus_id[MII_BUS_ID_SIZE]; 2002 char phy_name[MII_BUS_ID_SIZE + 3]; 2003 int phy_id; 2004 int dev_id = fep->dev_id; 2005 2006 if (fep->phy_node) { 2007 phy_dev = of_phy_connect(ndev, fep->phy_node, 2008 &fec_enet_adjust_link, 0, 2009 fep->phy_interface); 2010 if (!phy_dev) { 2011 netdev_err(ndev, "Unable to connect to phy\n"); 2012 return -ENODEV; 2013 } 2014 } else { 2015 /* check for attached phy */ 2016 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) { 2017 if (!mdiobus_is_registered_device(fep->mii_bus, phy_id)) 2018 continue; 2019 if (dev_id--) 2020 continue; 2021 strlcpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE); 2022 break; 2023 } 2024 2025 if (phy_id >= PHY_MAX_ADDR) { 2026 netdev_info(ndev, "no PHY, assuming direct connection to switch\n"); 2027 strlcpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); 2028 phy_id = 0; 2029 } 2030 2031 snprintf(phy_name, sizeof(phy_name), 2032 PHY_ID_FMT, mdio_bus_id, phy_id); 2033 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, 2034 fep->phy_interface); 2035 } 2036 2037 if (IS_ERR(phy_dev)) { 2038 netdev_err(ndev, "could not attach to PHY\n"); 2039 return PTR_ERR(phy_dev); 2040 } 2041 2042 /* mask with MAC supported features */ 2043 if (fep->quirks & FEC_QUIRK_HAS_GBIT) { 2044 phy_set_max_speed(phy_dev, 1000); 2045 phy_remove_link_mode(phy_dev, 2046 ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 2047 #if !defined(CONFIG_M5272) 2048 phy_support_sym_pause(phy_dev); 2049 #endif 2050 } 2051 else 2052 phy_set_max_speed(phy_dev, 100); 2053 2054 fep->link = 0; 2055 fep->full_duplex = 0; 2056 2057 phy_attached_info(phy_dev); 2058 2059 return 0; 2060 } 2061 2062 static int fec_enet_mii_init(struct platform_device *pdev) 2063 { 2064 static struct mii_bus *fec0_mii_bus; 2065 struct net_device *ndev = platform_get_drvdata(pdev); 2066 struct fec_enet_private *fep = netdev_priv(ndev); 2067 bool suppress_preamble = false; 2068 struct device_node *node; 2069 int err = -ENXIO; 2070 u32 mii_speed, holdtime; 2071 u32 bus_freq; 2072 2073 /* 2074 * The i.MX28 dual fec interfaces are not equal. 2075 * Here are the differences: 2076 * 2077 * - fec0 supports MII & RMII modes while fec1 only supports RMII 2078 * - fec0 acts as the 1588 time master while fec1 is slave 2079 * - external phys can only be configured by fec0 2080 * 2081 * That is to say fec1 can not work independently. It only works 2082 * when fec0 is working. The reason behind this design is that the 2083 * second interface is added primarily for Switch mode. 2084 * 2085 * Because of the last point above, both phys are attached on fec0 2086 * mdio interface in board design, and need to be configured by 2087 * fec0 mii_bus. 2088 */ 2089 if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) { 2090 /* fec1 uses fec0 mii_bus */ 2091 if (mii_cnt && fec0_mii_bus) { 2092 fep->mii_bus = fec0_mii_bus; 2093 mii_cnt++; 2094 return 0; 2095 } 2096 return -ENOENT; 2097 } 2098 2099 bus_freq = 2500000; /* 2.5MHz by default */ 2100 node = of_get_child_by_name(pdev->dev.of_node, "mdio"); 2101 if (node) { 2102 of_property_read_u32(node, "clock-frequency", &bus_freq); 2103 suppress_preamble = of_property_read_bool(node, 2104 "suppress-preamble"); 2105 } 2106 2107 /* 2108 * Set MII speed (= clk_get_rate() / 2 * phy_speed) 2109 * 2110 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while 2111 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28 2112 * Reference Manual has an error on this, and gets fixed on i.MX6Q 2113 * document. 2114 */ 2115 mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), bus_freq * 2); 2116 if (fep->quirks & FEC_QUIRK_ENET_MAC) 2117 mii_speed--; 2118 if (mii_speed > 63) { 2119 dev_err(&pdev->dev, 2120 "fec clock (%lu) too fast to get right mii speed\n", 2121 clk_get_rate(fep->clk_ipg)); 2122 err = -EINVAL; 2123 goto err_out; 2124 } 2125 2126 /* 2127 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka 2128 * MII_SPEED) register that defines the MDIO output hold time. Earlier 2129 * versions are RAZ there, so just ignore the difference and write the 2130 * register always. 2131 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns. 2132 * HOLDTIME + 1 is the number of clk cycles the fec is holding the 2133 * output. 2134 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive). 2135 * Given that ceil(clkrate / 5000000) <= 64, the calculation for 2136 * holdtime cannot result in a value greater than 3. 2137 */ 2138 holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1; 2139 2140 fep->phy_speed = mii_speed << 1 | holdtime << 8; 2141 2142 if (suppress_preamble) 2143 fep->phy_speed |= BIT(7); 2144 2145 /* Clear MMFR to avoid to generate MII event by writing MSCR. 2146 * MII event generation condition: 2147 * - writing MSCR: 2148 * - mmfr[31:0]_not_zero & mscr[7:0]_is_zero & 2149 * mscr_reg_data_in[7:0] != 0 2150 * - writing MMFR: 2151 * - mscr[7:0]_not_zero 2152 */ 2153 writel(0, fep->hwp + FEC_MII_DATA); 2154 2155 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 2156 2157 /* Clear any pending transaction complete indication */ 2158 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); 2159 2160 fep->mii_bus = mdiobus_alloc(); 2161 if (fep->mii_bus == NULL) { 2162 err = -ENOMEM; 2163 goto err_out; 2164 } 2165 2166 fep->mii_bus->name = "fec_enet_mii_bus"; 2167 fep->mii_bus->read = fec_enet_mdio_read; 2168 fep->mii_bus->write = fec_enet_mdio_write; 2169 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 2170 pdev->name, fep->dev_id + 1); 2171 fep->mii_bus->priv = fep; 2172 fep->mii_bus->parent = &pdev->dev; 2173 2174 err = of_mdiobus_register(fep->mii_bus, node); 2175 of_node_put(node); 2176 if (err) 2177 goto err_out_free_mdiobus; 2178 2179 mii_cnt++; 2180 2181 /* save fec0 mii_bus */ 2182 if (fep->quirks & FEC_QUIRK_SINGLE_MDIO) 2183 fec0_mii_bus = fep->mii_bus; 2184 2185 return 0; 2186 2187 err_out_free_mdiobus: 2188 mdiobus_free(fep->mii_bus); 2189 err_out: 2190 return err; 2191 } 2192 2193 static void fec_enet_mii_remove(struct fec_enet_private *fep) 2194 { 2195 if (--mii_cnt == 0) { 2196 mdiobus_unregister(fep->mii_bus); 2197 mdiobus_free(fep->mii_bus); 2198 } 2199 } 2200 2201 static void fec_enet_get_drvinfo(struct net_device *ndev, 2202 struct ethtool_drvinfo *info) 2203 { 2204 struct fec_enet_private *fep = netdev_priv(ndev); 2205 2206 strlcpy(info->driver, fep->pdev->dev.driver->name, 2207 sizeof(info->driver)); 2208 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info)); 2209 } 2210 2211 static int fec_enet_get_regs_len(struct net_device *ndev) 2212 { 2213 struct fec_enet_private *fep = netdev_priv(ndev); 2214 struct resource *r; 2215 int s = 0; 2216 2217 r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0); 2218 if (r) 2219 s = resource_size(r); 2220 2221 return s; 2222 } 2223 2224 /* List of registers that can be safety be read to dump them with ethtool */ 2225 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 2226 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \ 2227 defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST) 2228 static __u32 fec_enet_register_version = 2; 2229 static u32 fec_enet_register_offset[] = { 2230 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0, 2231 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL, 2232 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1, 2233 FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH, 2234 FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, 2235 FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1, 2236 FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2, 2237 FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0, 2238 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM, 2239 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2, 2240 FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1, 2241 FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME, 2242 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT, 2243 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG, 2244 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255, 2245 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047, 2246 RMON_T_P_GTE2048, RMON_T_OCTETS, 2247 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF, 2248 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE, 2249 IEEE_T_FDXFC, IEEE_T_OCTETS_OK, 2250 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN, 2251 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB, 2252 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255, 2253 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047, 2254 RMON_R_P_GTE2048, RMON_R_OCTETS, 2255 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR, 2256 IEEE_R_FDXFC, IEEE_R_OCTETS_OK 2257 }; 2258 #else 2259 static __u32 fec_enet_register_version = 1; 2260 static u32 fec_enet_register_offset[] = { 2261 FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0, 2262 FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0, 2263 FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED, 2264 FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL, 2265 FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, 2266 FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0, 2267 FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0, 2268 FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0, 2269 FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2 2270 }; 2271 #endif 2272 2273 static void fec_enet_get_regs(struct net_device *ndev, 2274 struct ethtool_regs *regs, void *regbuf) 2275 { 2276 struct fec_enet_private *fep = netdev_priv(ndev); 2277 u32 __iomem *theregs = (u32 __iomem *)fep->hwp; 2278 struct device *dev = &fep->pdev->dev; 2279 u32 *buf = (u32 *)regbuf; 2280 u32 i, off; 2281 int ret; 2282 2283 ret = pm_runtime_get_sync(dev); 2284 if (ret < 0) 2285 return; 2286 2287 regs->version = fec_enet_register_version; 2288 2289 memset(buf, 0, regs->len); 2290 2291 for (i = 0; i < ARRAY_SIZE(fec_enet_register_offset); i++) { 2292 off = fec_enet_register_offset[i]; 2293 2294 if ((off == FEC_R_BOUND || off == FEC_R_FSTART) && 2295 !(fep->quirks & FEC_QUIRK_HAS_FRREG)) 2296 continue; 2297 2298 off >>= 2; 2299 buf[off] = readl(&theregs[off]); 2300 } 2301 2302 pm_runtime_mark_last_busy(dev); 2303 pm_runtime_put_autosuspend(dev); 2304 } 2305 2306 static int fec_enet_get_ts_info(struct net_device *ndev, 2307 struct ethtool_ts_info *info) 2308 { 2309 struct fec_enet_private *fep = netdev_priv(ndev); 2310 2311 if (fep->bufdesc_ex) { 2312 2313 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 2314 SOF_TIMESTAMPING_RX_SOFTWARE | 2315 SOF_TIMESTAMPING_SOFTWARE | 2316 SOF_TIMESTAMPING_TX_HARDWARE | 2317 SOF_TIMESTAMPING_RX_HARDWARE | 2318 SOF_TIMESTAMPING_RAW_HARDWARE; 2319 if (fep->ptp_clock) 2320 info->phc_index = ptp_clock_index(fep->ptp_clock); 2321 else 2322 info->phc_index = -1; 2323 2324 info->tx_types = (1 << HWTSTAMP_TX_OFF) | 2325 (1 << HWTSTAMP_TX_ON); 2326 2327 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 2328 (1 << HWTSTAMP_FILTER_ALL); 2329 return 0; 2330 } else { 2331 return ethtool_op_get_ts_info(ndev, info); 2332 } 2333 } 2334 2335 #if !defined(CONFIG_M5272) 2336 2337 static void fec_enet_get_pauseparam(struct net_device *ndev, 2338 struct ethtool_pauseparam *pause) 2339 { 2340 struct fec_enet_private *fep = netdev_priv(ndev); 2341 2342 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0; 2343 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0; 2344 pause->rx_pause = pause->tx_pause; 2345 } 2346 2347 static int fec_enet_set_pauseparam(struct net_device *ndev, 2348 struct ethtool_pauseparam *pause) 2349 { 2350 struct fec_enet_private *fep = netdev_priv(ndev); 2351 2352 if (!ndev->phydev) 2353 return -ENODEV; 2354 2355 if (pause->tx_pause != pause->rx_pause) { 2356 netdev_info(ndev, 2357 "hardware only support enable/disable both tx and rx"); 2358 return -EINVAL; 2359 } 2360 2361 fep->pause_flag = 0; 2362 2363 /* tx pause must be same as rx pause */ 2364 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0; 2365 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0; 2366 2367 phy_set_sym_pause(ndev->phydev, pause->rx_pause, pause->tx_pause, 2368 pause->autoneg); 2369 2370 if (pause->autoneg) { 2371 if (netif_running(ndev)) 2372 fec_stop(ndev); 2373 phy_start_aneg(ndev->phydev); 2374 } 2375 if (netif_running(ndev)) { 2376 napi_disable(&fep->napi); 2377 netif_tx_lock_bh(ndev); 2378 fec_restart(ndev); 2379 netif_tx_wake_all_queues(ndev); 2380 netif_tx_unlock_bh(ndev); 2381 napi_enable(&fep->napi); 2382 } 2383 2384 return 0; 2385 } 2386 2387 static const struct fec_stat { 2388 char name[ETH_GSTRING_LEN]; 2389 u16 offset; 2390 } fec_stats[] = { 2391 /* RMON TX */ 2392 { "tx_dropped", RMON_T_DROP }, 2393 { "tx_packets", RMON_T_PACKETS }, 2394 { "tx_broadcast", RMON_T_BC_PKT }, 2395 { "tx_multicast", RMON_T_MC_PKT }, 2396 { "tx_crc_errors", RMON_T_CRC_ALIGN }, 2397 { "tx_undersize", RMON_T_UNDERSIZE }, 2398 { "tx_oversize", RMON_T_OVERSIZE }, 2399 { "tx_fragment", RMON_T_FRAG }, 2400 { "tx_jabber", RMON_T_JAB }, 2401 { "tx_collision", RMON_T_COL }, 2402 { "tx_64byte", RMON_T_P64 }, 2403 { "tx_65to127byte", RMON_T_P65TO127 }, 2404 { "tx_128to255byte", RMON_T_P128TO255 }, 2405 { "tx_256to511byte", RMON_T_P256TO511 }, 2406 { "tx_512to1023byte", RMON_T_P512TO1023 }, 2407 { "tx_1024to2047byte", RMON_T_P1024TO2047 }, 2408 { "tx_GTE2048byte", RMON_T_P_GTE2048 }, 2409 { "tx_octets", RMON_T_OCTETS }, 2410 2411 /* IEEE TX */ 2412 { "IEEE_tx_drop", IEEE_T_DROP }, 2413 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK }, 2414 { "IEEE_tx_1col", IEEE_T_1COL }, 2415 { "IEEE_tx_mcol", IEEE_T_MCOL }, 2416 { "IEEE_tx_def", IEEE_T_DEF }, 2417 { "IEEE_tx_lcol", IEEE_T_LCOL }, 2418 { "IEEE_tx_excol", IEEE_T_EXCOL }, 2419 { "IEEE_tx_macerr", IEEE_T_MACERR }, 2420 { "IEEE_tx_cserr", IEEE_T_CSERR }, 2421 { "IEEE_tx_sqe", IEEE_T_SQE }, 2422 { "IEEE_tx_fdxfc", IEEE_T_FDXFC }, 2423 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK }, 2424 2425 /* RMON RX */ 2426 { "rx_packets", RMON_R_PACKETS }, 2427 { "rx_broadcast", RMON_R_BC_PKT }, 2428 { "rx_multicast", RMON_R_MC_PKT }, 2429 { "rx_crc_errors", RMON_R_CRC_ALIGN }, 2430 { "rx_undersize", RMON_R_UNDERSIZE }, 2431 { "rx_oversize", RMON_R_OVERSIZE }, 2432 { "rx_fragment", RMON_R_FRAG }, 2433 { "rx_jabber", RMON_R_JAB }, 2434 { "rx_64byte", RMON_R_P64 }, 2435 { "rx_65to127byte", RMON_R_P65TO127 }, 2436 { "rx_128to255byte", RMON_R_P128TO255 }, 2437 { "rx_256to511byte", RMON_R_P256TO511 }, 2438 { "rx_512to1023byte", RMON_R_P512TO1023 }, 2439 { "rx_1024to2047byte", RMON_R_P1024TO2047 }, 2440 { "rx_GTE2048byte", RMON_R_P_GTE2048 }, 2441 { "rx_octets", RMON_R_OCTETS }, 2442 2443 /* IEEE RX */ 2444 { "IEEE_rx_drop", IEEE_R_DROP }, 2445 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK }, 2446 { "IEEE_rx_crc", IEEE_R_CRC }, 2447 { "IEEE_rx_align", IEEE_R_ALIGN }, 2448 { "IEEE_rx_macerr", IEEE_R_MACERR }, 2449 { "IEEE_rx_fdxfc", IEEE_R_FDXFC }, 2450 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK }, 2451 }; 2452 2453 #define FEC_STATS_SIZE (ARRAY_SIZE(fec_stats) * sizeof(u64)) 2454 2455 static void fec_enet_update_ethtool_stats(struct net_device *dev) 2456 { 2457 struct fec_enet_private *fep = netdev_priv(dev); 2458 int i; 2459 2460 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2461 fep->ethtool_stats[i] = readl(fep->hwp + fec_stats[i].offset); 2462 } 2463 2464 static void fec_enet_get_ethtool_stats(struct net_device *dev, 2465 struct ethtool_stats *stats, u64 *data) 2466 { 2467 struct fec_enet_private *fep = netdev_priv(dev); 2468 2469 if (netif_running(dev)) 2470 fec_enet_update_ethtool_stats(dev); 2471 2472 memcpy(data, fep->ethtool_stats, FEC_STATS_SIZE); 2473 } 2474 2475 static void fec_enet_get_strings(struct net_device *netdev, 2476 u32 stringset, u8 *data) 2477 { 2478 int i; 2479 switch (stringset) { 2480 case ETH_SS_STATS: 2481 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2482 memcpy(data + i * ETH_GSTRING_LEN, 2483 fec_stats[i].name, ETH_GSTRING_LEN); 2484 break; 2485 } 2486 } 2487 2488 static int fec_enet_get_sset_count(struct net_device *dev, int sset) 2489 { 2490 switch (sset) { 2491 case ETH_SS_STATS: 2492 return ARRAY_SIZE(fec_stats); 2493 default: 2494 return -EOPNOTSUPP; 2495 } 2496 } 2497 2498 static void fec_enet_clear_ethtool_stats(struct net_device *dev) 2499 { 2500 struct fec_enet_private *fep = netdev_priv(dev); 2501 int i; 2502 2503 /* Disable MIB statistics counters */ 2504 writel(FEC_MIB_CTRLSTAT_DISABLE, fep->hwp + FEC_MIB_CTRLSTAT); 2505 2506 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2507 writel(0, fep->hwp + fec_stats[i].offset); 2508 2509 /* Don't disable MIB statistics counters */ 2510 writel(0, fep->hwp + FEC_MIB_CTRLSTAT); 2511 } 2512 2513 #else /* !defined(CONFIG_M5272) */ 2514 #define FEC_STATS_SIZE 0 2515 static inline void fec_enet_update_ethtool_stats(struct net_device *dev) 2516 { 2517 } 2518 2519 static inline void fec_enet_clear_ethtool_stats(struct net_device *dev) 2520 { 2521 } 2522 #endif /* !defined(CONFIG_M5272) */ 2523 2524 /* ITR clock source is enet system clock (clk_ahb). 2525 * TCTT unit is cycle_ns * 64 cycle 2526 * So, the ICTT value = X us / (cycle_ns * 64) 2527 */ 2528 static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us) 2529 { 2530 struct fec_enet_private *fep = netdev_priv(ndev); 2531 2532 return us * (fep->itr_clk_rate / 64000) / 1000; 2533 } 2534 2535 /* Set threshold for interrupt coalescing */ 2536 static void fec_enet_itr_coal_set(struct net_device *ndev) 2537 { 2538 struct fec_enet_private *fep = netdev_priv(ndev); 2539 int rx_itr, tx_itr; 2540 2541 /* Must be greater than zero to avoid unpredictable behavior */ 2542 if (!fep->rx_time_itr || !fep->rx_pkts_itr || 2543 !fep->tx_time_itr || !fep->tx_pkts_itr) 2544 return; 2545 2546 /* Select enet system clock as Interrupt Coalescing 2547 * timer Clock Source 2548 */ 2549 rx_itr = FEC_ITR_CLK_SEL; 2550 tx_itr = FEC_ITR_CLK_SEL; 2551 2552 /* set ICFT and ICTT */ 2553 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr); 2554 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr)); 2555 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr); 2556 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr)); 2557 2558 rx_itr |= FEC_ITR_EN; 2559 tx_itr |= FEC_ITR_EN; 2560 2561 writel(tx_itr, fep->hwp + FEC_TXIC0); 2562 writel(rx_itr, fep->hwp + FEC_RXIC0); 2563 if (fep->quirks & FEC_QUIRK_HAS_AVB) { 2564 writel(tx_itr, fep->hwp + FEC_TXIC1); 2565 writel(rx_itr, fep->hwp + FEC_RXIC1); 2566 writel(tx_itr, fep->hwp + FEC_TXIC2); 2567 writel(rx_itr, fep->hwp + FEC_RXIC2); 2568 } 2569 } 2570 2571 static int 2572 fec_enet_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec) 2573 { 2574 struct fec_enet_private *fep = netdev_priv(ndev); 2575 2576 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) 2577 return -EOPNOTSUPP; 2578 2579 ec->rx_coalesce_usecs = fep->rx_time_itr; 2580 ec->rx_max_coalesced_frames = fep->rx_pkts_itr; 2581 2582 ec->tx_coalesce_usecs = fep->tx_time_itr; 2583 ec->tx_max_coalesced_frames = fep->tx_pkts_itr; 2584 2585 return 0; 2586 } 2587 2588 static int 2589 fec_enet_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec) 2590 { 2591 struct fec_enet_private *fep = netdev_priv(ndev); 2592 struct device *dev = &fep->pdev->dev; 2593 unsigned int cycle; 2594 2595 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) 2596 return -EOPNOTSUPP; 2597 2598 if (ec->rx_max_coalesced_frames > 255) { 2599 dev_err(dev, "Rx coalesced frames exceed hardware limitation\n"); 2600 return -EINVAL; 2601 } 2602 2603 if (ec->tx_max_coalesced_frames > 255) { 2604 dev_err(dev, "Tx coalesced frame exceed hardware limitation\n"); 2605 return -EINVAL; 2606 } 2607 2608 cycle = fec_enet_us_to_itr_clock(ndev, ec->rx_coalesce_usecs); 2609 if (cycle > 0xFFFF) { 2610 dev_err(dev, "Rx coalesced usec exceed hardware limitation\n"); 2611 return -EINVAL; 2612 } 2613 2614 cycle = fec_enet_us_to_itr_clock(ndev, ec->tx_coalesce_usecs); 2615 if (cycle > 0xFFFF) { 2616 dev_err(dev, "Tx coalesced usec exceed hardware limitation\n"); 2617 return -EINVAL; 2618 } 2619 2620 fep->rx_time_itr = ec->rx_coalesce_usecs; 2621 fep->rx_pkts_itr = ec->rx_max_coalesced_frames; 2622 2623 fep->tx_time_itr = ec->tx_coalesce_usecs; 2624 fep->tx_pkts_itr = ec->tx_max_coalesced_frames; 2625 2626 fec_enet_itr_coal_set(ndev); 2627 2628 return 0; 2629 } 2630 2631 static void fec_enet_itr_coal_init(struct net_device *ndev) 2632 { 2633 struct ethtool_coalesce ec; 2634 2635 ec.rx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT; 2636 ec.rx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT; 2637 2638 ec.tx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT; 2639 ec.tx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT; 2640 2641 fec_enet_set_coalesce(ndev, &ec); 2642 } 2643 2644 static int fec_enet_get_tunable(struct net_device *netdev, 2645 const struct ethtool_tunable *tuna, 2646 void *data) 2647 { 2648 struct fec_enet_private *fep = netdev_priv(netdev); 2649 int ret = 0; 2650 2651 switch (tuna->id) { 2652 case ETHTOOL_RX_COPYBREAK: 2653 *(u32 *)data = fep->rx_copybreak; 2654 break; 2655 default: 2656 ret = -EINVAL; 2657 break; 2658 } 2659 2660 return ret; 2661 } 2662 2663 static int fec_enet_set_tunable(struct net_device *netdev, 2664 const struct ethtool_tunable *tuna, 2665 const void *data) 2666 { 2667 struct fec_enet_private *fep = netdev_priv(netdev); 2668 int ret = 0; 2669 2670 switch (tuna->id) { 2671 case ETHTOOL_RX_COPYBREAK: 2672 fep->rx_copybreak = *(u32 *)data; 2673 break; 2674 default: 2675 ret = -EINVAL; 2676 break; 2677 } 2678 2679 return ret; 2680 } 2681 2682 static void 2683 fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2684 { 2685 struct fec_enet_private *fep = netdev_priv(ndev); 2686 2687 if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) { 2688 wol->supported = WAKE_MAGIC; 2689 wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0; 2690 } else { 2691 wol->supported = wol->wolopts = 0; 2692 } 2693 } 2694 2695 static int 2696 fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2697 { 2698 struct fec_enet_private *fep = netdev_priv(ndev); 2699 2700 if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET)) 2701 return -EINVAL; 2702 2703 if (wol->wolopts & ~WAKE_MAGIC) 2704 return -EINVAL; 2705 2706 device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC); 2707 if (device_may_wakeup(&ndev->dev)) { 2708 fep->wol_flag |= FEC_WOL_FLAG_ENABLE; 2709 if (fep->irq[0] > 0) 2710 enable_irq_wake(fep->irq[0]); 2711 } else { 2712 fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE); 2713 if (fep->irq[0] > 0) 2714 disable_irq_wake(fep->irq[0]); 2715 } 2716 2717 return 0; 2718 } 2719 2720 static const struct ethtool_ops fec_enet_ethtool_ops = { 2721 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 2722 ETHTOOL_COALESCE_MAX_FRAMES, 2723 .get_drvinfo = fec_enet_get_drvinfo, 2724 .get_regs_len = fec_enet_get_regs_len, 2725 .get_regs = fec_enet_get_regs, 2726 .nway_reset = phy_ethtool_nway_reset, 2727 .get_link = ethtool_op_get_link, 2728 .get_coalesce = fec_enet_get_coalesce, 2729 .set_coalesce = fec_enet_set_coalesce, 2730 #ifndef CONFIG_M5272 2731 .get_pauseparam = fec_enet_get_pauseparam, 2732 .set_pauseparam = fec_enet_set_pauseparam, 2733 .get_strings = fec_enet_get_strings, 2734 .get_ethtool_stats = fec_enet_get_ethtool_stats, 2735 .get_sset_count = fec_enet_get_sset_count, 2736 #endif 2737 .get_ts_info = fec_enet_get_ts_info, 2738 .get_tunable = fec_enet_get_tunable, 2739 .set_tunable = fec_enet_set_tunable, 2740 .get_wol = fec_enet_get_wol, 2741 .set_wol = fec_enet_set_wol, 2742 .get_link_ksettings = phy_ethtool_get_link_ksettings, 2743 .set_link_ksettings = phy_ethtool_set_link_ksettings, 2744 }; 2745 2746 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) 2747 { 2748 struct fec_enet_private *fep = netdev_priv(ndev); 2749 struct phy_device *phydev = ndev->phydev; 2750 2751 if (!netif_running(ndev)) 2752 return -EINVAL; 2753 2754 if (!phydev) 2755 return -ENODEV; 2756 2757 if (fep->bufdesc_ex) { 2758 if (cmd == SIOCSHWTSTAMP) 2759 return fec_ptp_set(ndev, rq); 2760 if (cmd == SIOCGHWTSTAMP) 2761 return fec_ptp_get(ndev, rq); 2762 } 2763 2764 return phy_mii_ioctl(phydev, rq, cmd); 2765 } 2766 2767 static void fec_enet_free_buffers(struct net_device *ndev) 2768 { 2769 struct fec_enet_private *fep = netdev_priv(ndev); 2770 unsigned int i; 2771 struct sk_buff *skb; 2772 struct bufdesc *bdp; 2773 struct fec_enet_priv_tx_q *txq; 2774 struct fec_enet_priv_rx_q *rxq; 2775 unsigned int q; 2776 2777 for (q = 0; q < fep->num_rx_queues; q++) { 2778 rxq = fep->rx_queue[q]; 2779 bdp = rxq->bd.base; 2780 for (i = 0; i < rxq->bd.ring_size; i++) { 2781 skb = rxq->rx_skbuff[i]; 2782 rxq->rx_skbuff[i] = NULL; 2783 if (skb) { 2784 dma_unmap_single(&fep->pdev->dev, 2785 fec32_to_cpu(bdp->cbd_bufaddr), 2786 FEC_ENET_RX_FRSIZE - fep->rx_align, 2787 DMA_FROM_DEVICE); 2788 dev_kfree_skb(skb); 2789 } 2790 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 2791 } 2792 } 2793 2794 for (q = 0; q < fep->num_tx_queues; q++) { 2795 txq = fep->tx_queue[q]; 2796 for (i = 0; i < txq->bd.ring_size; i++) { 2797 kfree(txq->tx_bounce[i]); 2798 txq->tx_bounce[i] = NULL; 2799 skb = txq->tx_skbuff[i]; 2800 txq->tx_skbuff[i] = NULL; 2801 dev_kfree_skb(skb); 2802 } 2803 } 2804 } 2805 2806 static void fec_enet_free_queue(struct net_device *ndev) 2807 { 2808 struct fec_enet_private *fep = netdev_priv(ndev); 2809 int i; 2810 struct fec_enet_priv_tx_q *txq; 2811 2812 for (i = 0; i < fep->num_tx_queues; i++) 2813 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) { 2814 txq = fep->tx_queue[i]; 2815 dma_free_coherent(&fep->pdev->dev, 2816 txq->bd.ring_size * TSO_HEADER_SIZE, 2817 txq->tso_hdrs, 2818 txq->tso_hdrs_dma); 2819 } 2820 2821 for (i = 0; i < fep->num_rx_queues; i++) 2822 kfree(fep->rx_queue[i]); 2823 for (i = 0; i < fep->num_tx_queues; i++) 2824 kfree(fep->tx_queue[i]); 2825 } 2826 2827 static int fec_enet_alloc_queue(struct net_device *ndev) 2828 { 2829 struct fec_enet_private *fep = netdev_priv(ndev); 2830 int i; 2831 int ret = 0; 2832 struct fec_enet_priv_tx_q *txq; 2833 2834 for (i = 0; i < fep->num_tx_queues; i++) { 2835 txq = kzalloc(sizeof(*txq), GFP_KERNEL); 2836 if (!txq) { 2837 ret = -ENOMEM; 2838 goto alloc_failed; 2839 } 2840 2841 fep->tx_queue[i] = txq; 2842 txq->bd.ring_size = TX_RING_SIZE; 2843 fep->total_tx_ring_size += fep->tx_queue[i]->bd.ring_size; 2844 2845 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS; 2846 txq->tx_wake_threshold = 2847 (txq->bd.ring_size - txq->tx_stop_threshold) / 2; 2848 2849 txq->tso_hdrs = dma_alloc_coherent(&fep->pdev->dev, 2850 txq->bd.ring_size * TSO_HEADER_SIZE, 2851 &txq->tso_hdrs_dma, 2852 GFP_KERNEL); 2853 if (!txq->tso_hdrs) { 2854 ret = -ENOMEM; 2855 goto alloc_failed; 2856 } 2857 } 2858 2859 for (i = 0; i < fep->num_rx_queues; i++) { 2860 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]), 2861 GFP_KERNEL); 2862 if (!fep->rx_queue[i]) { 2863 ret = -ENOMEM; 2864 goto alloc_failed; 2865 } 2866 2867 fep->rx_queue[i]->bd.ring_size = RX_RING_SIZE; 2868 fep->total_rx_ring_size += fep->rx_queue[i]->bd.ring_size; 2869 } 2870 return ret; 2871 2872 alloc_failed: 2873 fec_enet_free_queue(ndev); 2874 return ret; 2875 } 2876 2877 static int 2878 fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue) 2879 { 2880 struct fec_enet_private *fep = netdev_priv(ndev); 2881 unsigned int i; 2882 struct sk_buff *skb; 2883 struct bufdesc *bdp; 2884 struct fec_enet_priv_rx_q *rxq; 2885 2886 rxq = fep->rx_queue[queue]; 2887 bdp = rxq->bd.base; 2888 for (i = 0; i < rxq->bd.ring_size; i++) { 2889 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE); 2890 if (!skb) 2891 goto err_alloc; 2892 2893 if (fec_enet_new_rxbdp(ndev, bdp, skb)) { 2894 dev_kfree_skb(skb); 2895 goto err_alloc; 2896 } 2897 2898 rxq->rx_skbuff[i] = skb; 2899 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); 2900 2901 if (fep->bufdesc_ex) { 2902 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 2903 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); 2904 } 2905 2906 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 2907 } 2908 2909 /* Set the last buffer to wrap. */ 2910 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); 2911 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 2912 return 0; 2913 2914 err_alloc: 2915 fec_enet_free_buffers(ndev); 2916 return -ENOMEM; 2917 } 2918 2919 static int 2920 fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue) 2921 { 2922 struct fec_enet_private *fep = netdev_priv(ndev); 2923 unsigned int i; 2924 struct bufdesc *bdp; 2925 struct fec_enet_priv_tx_q *txq; 2926 2927 txq = fep->tx_queue[queue]; 2928 bdp = txq->bd.base; 2929 for (i = 0; i < txq->bd.ring_size; i++) { 2930 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); 2931 if (!txq->tx_bounce[i]) 2932 goto err_alloc; 2933 2934 bdp->cbd_sc = cpu_to_fec16(0); 2935 bdp->cbd_bufaddr = cpu_to_fec32(0); 2936 2937 if (fep->bufdesc_ex) { 2938 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 2939 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_TX_INT); 2940 } 2941 2942 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 2943 } 2944 2945 /* Set the last buffer to wrap. */ 2946 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); 2947 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 2948 2949 return 0; 2950 2951 err_alloc: 2952 fec_enet_free_buffers(ndev); 2953 return -ENOMEM; 2954 } 2955 2956 static int fec_enet_alloc_buffers(struct net_device *ndev) 2957 { 2958 struct fec_enet_private *fep = netdev_priv(ndev); 2959 unsigned int i; 2960 2961 for (i = 0; i < fep->num_rx_queues; i++) 2962 if (fec_enet_alloc_rxq_buffers(ndev, i)) 2963 return -ENOMEM; 2964 2965 for (i = 0; i < fep->num_tx_queues; i++) 2966 if (fec_enet_alloc_txq_buffers(ndev, i)) 2967 return -ENOMEM; 2968 return 0; 2969 } 2970 2971 static int 2972 fec_enet_open(struct net_device *ndev) 2973 { 2974 struct fec_enet_private *fep = netdev_priv(ndev); 2975 int ret; 2976 bool reset_again; 2977 2978 ret = pm_runtime_get_sync(&fep->pdev->dev); 2979 if (ret < 0) 2980 return ret; 2981 2982 pinctrl_pm_select_default_state(&fep->pdev->dev); 2983 ret = fec_enet_clk_enable(ndev, true); 2984 if (ret) 2985 goto clk_enable; 2986 2987 /* During the first fec_enet_open call the PHY isn't probed at this 2988 * point. Therefore the phy_reset_after_clk_enable() call within 2989 * fec_enet_clk_enable() fails. As we need this reset in order to be 2990 * sure the PHY is working correctly we check if we need to reset again 2991 * later when the PHY is probed 2992 */ 2993 if (ndev->phydev && ndev->phydev->drv) 2994 reset_again = false; 2995 else 2996 reset_again = true; 2997 2998 /* I should reset the ring buffers here, but I don't yet know 2999 * a simple way to do that. 3000 */ 3001 3002 ret = fec_enet_alloc_buffers(ndev); 3003 if (ret) 3004 goto err_enet_alloc; 3005 3006 /* Init MAC prior to mii bus probe */ 3007 fec_restart(ndev); 3008 3009 /* Probe and connect to PHY when open the interface */ 3010 ret = fec_enet_mii_probe(ndev); 3011 if (ret) 3012 goto err_enet_mii_probe; 3013 3014 /* Call phy_reset_after_clk_enable() again if it failed during 3015 * phy_reset_after_clk_enable() before because the PHY wasn't probed. 3016 */ 3017 if (reset_again) 3018 phy_reset_after_clk_enable(ndev->phydev); 3019 3020 if (fep->quirks & FEC_QUIRK_ERR006687) 3021 imx6q_cpuidle_fec_irqs_used(); 3022 3023 napi_enable(&fep->napi); 3024 phy_start(ndev->phydev); 3025 netif_tx_start_all_queues(ndev); 3026 3027 device_set_wakeup_enable(&ndev->dev, fep->wol_flag & 3028 FEC_WOL_FLAG_ENABLE); 3029 3030 return 0; 3031 3032 err_enet_mii_probe: 3033 fec_enet_free_buffers(ndev); 3034 err_enet_alloc: 3035 fec_enet_clk_enable(ndev, false); 3036 clk_enable: 3037 pm_runtime_mark_last_busy(&fep->pdev->dev); 3038 pm_runtime_put_autosuspend(&fep->pdev->dev); 3039 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3040 return ret; 3041 } 3042 3043 static int 3044 fec_enet_close(struct net_device *ndev) 3045 { 3046 struct fec_enet_private *fep = netdev_priv(ndev); 3047 3048 phy_stop(ndev->phydev); 3049 3050 if (netif_device_present(ndev)) { 3051 napi_disable(&fep->napi); 3052 netif_tx_disable(ndev); 3053 fec_stop(ndev); 3054 } 3055 3056 phy_disconnect(ndev->phydev); 3057 3058 if (fep->quirks & FEC_QUIRK_ERR006687) 3059 imx6q_cpuidle_fec_irqs_unused(); 3060 3061 fec_enet_update_ethtool_stats(ndev); 3062 3063 fec_enet_clk_enable(ndev, false); 3064 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3065 pm_runtime_mark_last_busy(&fep->pdev->dev); 3066 pm_runtime_put_autosuspend(&fep->pdev->dev); 3067 3068 fec_enet_free_buffers(ndev); 3069 3070 return 0; 3071 } 3072 3073 /* Set or clear the multicast filter for this adaptor. 3074 * Skeleton taken from sunlance driver. 3075 * The CPM Ethernet implementation allows Multicast as well as individual 3076 * MAC address filtering. Some of the drivers check to make sure it is 3077 * a group multicast address, and discard those that are not. I guess I 3078 * will do the same for now, but just remove the test if you want 3079 * individual filtering as well (do the upper net layers want or support 3080 * this kind of feature?). 3081 */ 3082 3083 #define FEC_HASH_BITS 6 /* #bits in hash */ 3084 3085 static void set_multicast_list(struct net_device *ndev) 3086 { 3087 struct fec_enet_private *fep = netdev_priv(ndev); 3088 struct netdev_hw_addr *ha; 3089 unsigned int crc, tmp; 3090 unsigned char hash; 3091 unsigned int hash_high = 0, hash_low = 0; 3092 3093 if (ndev->flags & IFF_PROMISC) { 3094 tmp = readl(fep->hwp + FEC_R_CNTRL); 3095 tmp |= 0x8; 3096 writel(tmp, fep->hwp + FEC_R_CNTRL); 3097 return; 3098 } 3099 3100 tmp = readl(fep->hwp + FEC_R_CNTRL); 3101 tmp &= ~0x8; 3102 writel(tmp, fep->hwp + FEC_R_CNTRL); 3103 3104 if (ndev->flags & IFF_ALLMULTI) { 3105 /* Catch all multicast addresses, so set the 3106 * filter to all 1's 3107 */ 3108 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 3109 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 3110 3111 return; 3112 } 3113 3114 /* Add the addresses in hash register */ 3115 netdev_for_each_mc_addr(ha, ndev) { 3116 /* calculate crc32 value of mac address */ 3117 crc = ether_crc_le(ndev->addr_len, ha->addr); 3118 3119 /* only upper 6 bits (FEC_HASH_BITS) are used 3120 * which point to specific bit in the hash registers 3121 */ 3122 hash = (crc >> (32 - FEC_HASH_BITS)) & 0x3f; 3123 3124 if (hash > 31) 3125 hash_high |= 1 << (hash - 32); 3126 else 3127 hash_low |= 1 << hash; 3128 } 3129 3130 writel(hash_high, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 3131 writel(hash_low, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 3132 } 3133 3134 /* Set a MAC change in hardware. */ 3135 static int 3136 fec_set_mac_address(struct net_device *ndev, void *p) 3137 { 3138 struct fec_enet_private *fep = netdev_priv(ndev); 3139 struct sockaddr *addr = p; 3140 3141 if (addr) { 3142 if (!is_valid_ether_addr(addr->sa_data)) 3143 return -EADDRNOTAVAIL; 3144 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len); 3145 } 3146 3147 /* Add netif status check here to avoid system hang in below case: 3148 * ifconfig ethx down; ifconfig ethx hw ether xx:xx:xx:xx:xx:xx; 3149 * After ethx down, fec all clocks are gated off and then register 3150 * access causes system hang. 3151 */ 3152 if (!netif_running(ndev)) 3153 return 0; 3154 3155 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) | 3156 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24), 3157 fep->hwp + FEC_ADDR_LOW); 3158 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24), 3159 fep->hwp + FEC_ADDR_HIGH); 3160 return 0; 3161 } 3162 3163 #ifdef CONFIG_NET_POLL_CONTROLLER 3164 /** 3165 * fec_poll_controller - FEC Poll controller function 3166 * @dev: The FEC network adapter 3167 * 3168 * Polled functionality used by netconsole and others in non interrupt mode 3169 * 3170 */ 3171 static void fec_poll_controller(struct net_device *dev) 3172 { 3173 int i; 3174 struct fec_enet_private *fep = netdev_priv(dev); 3175 3176 for (i = 0; i < FEC_IRQ_NUM; i++) { 3177 if (fep->irq[i] > 0) { 3178 disable_irq(fep->irq[i]); 3179 fec_enet_interrupt(fep->irq[i], dev); 3180 enable_irq(fep->irq[i]); 3181 } 3182 } 3183 } 3184 #endif 3185 3186 static inline void fec_enet_set_netdev_features(struct net_device *netdev, 3187 netdev_features_t features) 3188 { 3189 struct fec_enet_private *fep = netdev_priv(netdev); 3190 netdev_features_t changed = features ^ netdev->features; 3191 3192 netdev->features = features; 3193 3194 /* Receive checksum has been changed */ 3195 if (changed & NETIF_F_RXCSUM) { 3196 if (features & NETIF_F_RXCSUM) 3197 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 3198 else 3199 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED; 3200 } 3201 } 3202 3203 static int fec_set_features(struct net_device *netdev, 3204 netdev_features_t features) 3205 { 3206 struct fec_enet_private *fep = netdev_priv(netdev); 3207 netdev_features_t changed = features ^ netdev->features; 3208 3209 if (netif_running(netdev) && changed & NETIF_F_RXCSUM) { 3210 napi_disable(&fep->napi); 3211 netif_tx_lock_bh(netdev); 3212 fec_stop(netdev); 3213 fec_enet_set_netdev_features(netdev, features); 3214 fec_restart(netdev); 3215 netif_tx_wake_all_queues(netdev); 3216 netif_tx_unlock_bh(netdev); 3217 napi_enable(&fep->napi); 3218 } else { 3219 fec_enet_set_netdev_features(netdev, features); 3220 } 3221 3222 return 0; 3223 } 3224 3225 static const struct net_device_ops fec_netdev_ops = { 3226 .ndo_open = fec_enet_open, 3227 .ndo_stop = fec_enet_close, 3228 .ndo_start_xmit = fec_enet_start_xmit, 3229 .ndo_set_rx_mode = set_multicast_list, 3230 .ndo_validate_addr = eth_validate_addr, 3231 .ndo_tx_timeout = fec_timeout, 3232 .ndo_set_mac_address = fec_set_mac_address, 3233 .ndo_do_ioctl = fec_enet_ioctl, 3234 #ifdef CONFIG_NET_POLL_CONTROLLER 3235 .ndo_poll_controller = fec_poll_controller, 3236 #endif 3237 .ndo_set_features = fec_set_features, 3238 }; 3239 3240 static const unsigned short offset_des_active_rxq[] = { 3241 FEC_R_DES_ACTIVE_0, FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2 3242 }; 3243 3244 static const unsigned short offset_des_active_txq[] = { 3245 FEC_X_DES_ACTIVE_0, FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2 3246 }; 3247 3248 /* 3249 * XXX: We need to clean up on failure exits here. 3250 * 3251 */ 3252 static int fec_enet_init(struct net_device *ndev) 3253 { 3254 struct fec_enet_private *fep = netdev_priv(ndev); 3255 struct bufdesc *cbd_base; 3256 dma_addr_t bd_dma; 3257 int bd_size; 3258 unsigned int i; 3259 unsigned dsize = fep->bufdesc_ex ? sizeof(struct bufdesc_ex) : 3260 sizeof(struct bufdesc); 3261 unsigned dsize_log2 = __fls(dsize); 3262 int ret; 3263 3264 WARN_ON(dsize != (1 << dsize_log2)); 3265 #if defined(CONFIG_ARM) || defined(CONFIG_ARM64) 3266 fep->rx_align = 0xf; 3267 fep->tx_align = 0xf; 3268 #else 3269 fep->rx_align = 0x3; 3270 fep->tx_align = 0x3; 3271 #endif 3272 3273 /* Check mask of the streaming and coherent API */ 3274 ret = dma_set_mask_and_coherent(&fep->pdev->dev, DMA_BIT_MASK(32)); 3275 if (ret < 0) { 3276 dev_warn(&fep->pdev->dev, "No suitable DMA available\n"); 3277 return ret; 3278 } 3279 3280 fec_enet_alloc_queue(ndev); 3281 3282 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) * dsize; 3283 3284 /* Allocate memory for buffer descriptors. */ 3285 cbd_base = dmam_alloc_coherent(&fep->pdev->dev, bd_size, &bd_dma, 3286 GFP_KERNEL); 3287 if (!cbd_base) { 3288 return -ENOMEM; 3289 } 3290 3291 /* Get the Ethernet address */ 3292 fec_get_mac(ndev); 3293 /* make sure MAC we just acquired is programmed into the hw */ 3294 fec_set_mac_address(ndev, NULL); 3295 3296 /* Set receive and transmit descriptor base. */ 3297 for (i = 0; i < fep->num_rx_queues; i++) { 3298 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[i]; 3299 unsigned size = dsize * rxq->bd.ring_size; 3300 3301 rxq->bd.qid = i; 3302 rxq->bd.base = cbd_base; 3303 rxq->bd.cur = cbd_base; 3304 rxq->bd.dma = bd_dma; 3305 rxq->bd.dsize = dsize; 3306 rxq->bd.dsize_log2 = dsize_log2; 3307 rxq->bd.reg_desc_active = fep->hwp + offset_des_active_rxq[i]; 3308 bd_dma += size; 3309 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size); 3310 rxq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); 3311 } 3312 3313 for (i = 0; i < fep->num_tx_queues; i++) { 3314 struct fec_enet_priv_tx_q *txq = fep->tx_queue[i]; 3315 unsigned size = dsize * txq->bd.ring_size; 3316 3317 txq->bd.qid = i; 3318 txq->bd.base = cbd_base; 3319 txq->bd.cur = cbd_base; 3320 txq->bd.dma = bd_dma; 3321 txq->bd.dsize = dsize; 3322 txq->bd.dsize_log2 = dsize_log2; 3323 txq->bd.reg_desc_active = fep->hwp + offset_des_active_txq[i]; 3324 bd_dma += size; 3325 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size); 3326 txq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); 3327 } 3328 3329 3330 /* The FEC Ethernet specific entries in the device structure */ 3331 ndev->watchdog_timeo = TX_TIMEOUT; 3332 ndev->netdev_ops = &fec_netdev_ops; 3333 ndev->ethtool_ops = &fec_enet_ethtool_ops; 3334 3335 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK); 3336 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT); 3337 3338 if (fep->quirks & FEC_QUIRK_HAS_VLAN) 3339 /* enable hw VLAN support */ 3340 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; 3341 3342 if (fep->quirks & FEC_QUIRK_HAS_CSUM) { 3343 ndev->gso_max_segs = FEC_MAX_TSO_SEGS; 3344 3345 /* enable hw accelerator */ 3346 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM 3347 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO); 3348 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 3349 } 3350 3351 if (fep->quirks & FEC_QUIRK_HAS_AVB) { 3352 fep->tx_align = 0; 3353 fep->rx_align = 0x3f; 3354 } 3355 3356 ndev->hw_features = ndev->features; 3357 3358 fec_restart(ndev); 3359 3360 if (fep->quirks & FEC_QUIRK_MIB_CLEAR) 3361 fec_enet_clear_ethtool_stats(ndev); 3362 else 3363 fec_enet_update_ethtool_stats(ndev); 3364 3365 return 0; 3366 } 3367 3368 #ifdef CONFIG_OF 3369 static int fec_reset_phy(struct platform_device *pdev) 3370 { 3371 int err, phy_reset; 3372 bool active_high = false; 3373 int msec = 1, phy_post_delay = 0; 3374 struct device_node *np = pdev->dev.of_node; 3375 3376 if (!np) 3377 return 0; 3378 3379 err = of_property_read_u32(np, "phy-reset-duration", &msec); 3380 /* A sane reset duration should not be longer than 1s */ 3381 if (!err && msec > 1000) 3382 msec = 1; 3383 3384 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0); 3385 if (phy_reset == -EPROBE_DEFER) 3386 return phy_reset; 3387 else if (!gpio_is_valid(phy_reset)) 3388 return 0; 3389 3390 err = of_property_read_u32(np, "phy-reset-post-delay", &phy_post_delay); 3391 /* valid reset duration should be less than 1s */ 3392 if (!err && phy_post_delay > 1000) 3393 return -EINVAL; 3394 3395 active_high = of_property_read_bool(np, "phy-reset-active-high"); 3396 3397 err = devm_gpio_request_one(&pdev->dev, phy_reset, 3398 active_high ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW, 3399 "phy-reset"); 3400 if (err) { 3401 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err); 3402 return err; 3403 } 3404 3405 if (msec > 20) 3406 msleep(msec); 3407 else 3408 usleep_range(msec * 1000, msec * 1000 + 1000); 3409 3410 gpio_set_value_cansleep(phy_reset, !active_high); 3411 3412 if (!phy_post_delay) 3413 return 0; 3414 3415 if (phy_post_delay > 20) 3416 msleep(phy_post_delay); 3417 else 3418 usleep_range(phy_post_delay * 1000, 3419 phy_post_delay * 1000 + 1000); 3420 3421 return 0; 3422 } 3423 #else /* CONFIG_OF */ 3424 static int fec_reset_phy(struct platform_device *pdev) 3425 { 3426 /* 3427 * In case of platform probe, the reset has been done 3428 * by machine code. 3429 */ 3430 return 0; 3431 } 3432 #endif /* CONFIG_OF */ 3433 3434 static void 3435 fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx) 3436 { 3437 struct device_node *np = pdev->dev.of_node; 3438 3439 *num_tx = *num_rx = 1; 3440 3441 if (!np || !of_device_is_available(np)) 3442 return; 3443 3444 /* parse the num of tx and rx queues */ 3445 of_property_read_u32(np, "fsl,num-tx-queues", num_tx); 3446 3447 of_property_read_u32(np, "fsl,num-rx-queues", num_rx); 3448 3449 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) { 3450 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n", 3451 *num_tx); 3452 *num_tx = 1; 3453 return; 3454 } 3455 3456 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) { 3457 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n", 3458 *num_rx); 3459 *num_rx = 1; 3460 return; 3461 } 3462 3463 } 3464 3465 static int fec_enet_get_irq_cnt(struct platform_device *pdev) 3466 { 3467 int irq_cnt = platform_irq_count(pdev); 3468 3469 if (irq_cnt > FEC_IRQ_NUM) 3470 irq_cnt = FEC_IRQ_NUM; /* last for pps */ 3471 else if (irq_cnt == 2) 3472 irq_cnt = 1; /* last for pps */ 3473 else if (irq_cnt <= 0) 3474 irq_cnt = 1; /* At least 1 irq is needed */ 3475 return irq_cnt; 3476 } 3477 3478 static int fec_enet_init_stop_mode(struct fec_enet_private *fep, 3479 struct device_node *np) 3480 { 3481 struct device_node *gpr_np; 3482 u32 out_val[3]; 3483 int ret = 0; 3484 3485 gpr_np = of_parse_phandle(np, "fsl,stop-mode", 0); 3486 if (!gpr_np) 3487 return 0; 3488 3489 ret = of_property_read_u32_array(np, "fsl,stop-mode", out_val, 3490 ARRAY_SIZE(out_val)); 3491 if (ret) { 3492 dev_dbg(&fep->pdev->dev, "no stop mode property\n"); 3493 return ret; 3494 } 3495 3496 fep->stop_gpr.gpr = syscon_node_to_regmap(gpr_np); 3497 if (IS_ERR(fep->stop_gpr.gpr)) { 3498 dev_err(&fep->pdev->dev, "could not find gpr regmap\n"); 3499 ret = PTR_ERR(fep->stop_gpr.gpr); 3500 fep->stop_gpr.gpr = NULL; 3501 goto out; 3502 } 3503 3504 fep->stop_gpr.reg = out_val[1]; 3505 fep->stop_gpr.bit = out_val[2]; 3506 3507 out: 3508 of_node_put(gpr_np); 3509 3510 return ret; 3511 } 3512 3513 static int 3514 fec_probe(struct platform_device *pdev) 3515 { 3516 struct fec_enet_private *fep; 3517 struct fec_platform_data *pdata; 3518 phy_interface_t interface; 3519 struct net_device *ndev; 3520 int i, irq, ret = 0; 3521 const struct of_device_id *of_id; 3522 static int dev_id; 3523 struct device_node *np = pdev->dev.of_node, *phy_node; 3524 int num_tx_qs; 3525 int num_rx_qs; 3526 char irq_name[8]; 3527 int irq_cnt; 3528 struct fec_devinfo *dev_info; 3529 3530 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs); 3531 3532 /* Init network device */ 3533 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private) + 3534 FEC_STATS_SIZE, num_tx_qs, num_rx_qs); 3535 if (!ndev) 3536 return -ENOMEM; 3537 3538 SET_NETDEV_DEV(ndev, &pdev->dev); 3539 3540 /* setup board info structure */ 3541 fep = netdev_priv(ndev); 3542 3543 of_id = of_match_device(fec_dt_ids, &pdev->dev); 3544 if (of_id) 3545 pdev->id_entry = of_id->data; 3546 dev_info = (struct fec_devinfo *)pdev->id_entry->driver_data; 3547 if (dev_info) 3548 fep->quirks = dev_info->quirks; 3549 3550 fep->netdev = ndev; 3551 fep->num_rx_queues = num_rx_qs; 3552 fep->num_tx_queues = num_tx_qs; 3553 3554 #if !defined(CONFIG_M5272) 3555 /* default enable pause frame auto negotiation */ 3556 if (fep->quirks & FEC_QUIRK_HAS_GBIT) 3557 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG; 3558 #endif 3559 3560 /* Select default pin state */ 3561 pinctrl_pm_select_default_state(&pdev->dev); 3562 3563 fep->hwp = devm_platform_ioremap_resource(pdev, 0); 3564 if (IS_ERR(fep->hwp)) { 3565 ret = PTR_ERR(fep->hwp); 3566 goto failed_ioremap; 3567 } 3568 3569 fep->pdev = pdev; 3570 fep->dev_id = dev_id++; 3571 3572 platform_set_drvdata(pdev, ndev); 3573 3574 if ((of_machine_is_compatible("fsl,imx6q") || 3575 of_machine_is_compatible("fsl,imx6dl")) && 3576 !of_property_read_bool(np, "fsl,err006687-workaround-present")) 3577 fep->quirks |= FEC_QUIRK_ERR006687; 3578 3579 if (of_get_property(np, "fsl,magic-packet", NULL)) 3580 fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET; 3581 3582 ret = fec_enet_init_stop_mode(fep, np); 3583 if (ret) 3584 goto failed_stop_mode; 3585 3586 phy_node = of_parse_phandle(np, "phy-handle", 0); 3587 if (!phy_node && of_phy_is_fixed_link(np)) { 3588 ret = of_phy_register_fixed_link(np); 3589 if (ret < 0) { 3590 dev_err(&pdev->dev, 3591 "broken fixed-link specification\n"); 3592 goto failed_phy; 3593 } 3594 phy_node = of_node_get(np); 3595 } 3596 fep->phy_node = phy_node; 3597 3598 ret = of_get_phy_mode(pdev->dev.of_node, &interface); 3599 if (ret) { 3600 pdata = dev_get_platdata(&pdev->dev); 3601 if (pdata) 3602 fep->phy_interface = pdata->phy; 3603 else 3604 fep->phy_interface = PHY_INTERFACE_MODE_MII; 3605 } else { 3606 fep->phy_interface = interface; 3607 } 3608 3609 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 3610 if (IS_ERR(fep->clk_ipg)) { 3611 ret = PTR_ERR(fep->clk_ipg); 3612 goto failed_clk; 3613 } 3614 3615 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 3616 if (IS_ERR(fep->clk_ahb)) { 3617 ret = PTR_ERR(fep->clk_ahb); 3618 goto failed_clk; 3619 } 3620 3621 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb); 3622 3623 /* enet_out is optional, depends on board */ 3624 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out"); 3625 if (IS_ERR(fep->clk_enet_out)) 3626 fep->clk_enet_out = NULL; 3627 3628 fep->ptp_clk_on = false; 3629 mutex_init(&fep->ptp_clk_mutex); 3630 3631 /* clk_ref is optional, depends on board */ 3632 fep->clk_ref = devm_clk_get(&pdev->dev, "enet_clk_ref"); 3633 if (IS_ERR(fep->clk_ref)) 3634 fep->clk_ref = NULL; 3635 3636 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX; 3637 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp"); 3638 if (IS_ERR(fep->clk_ptp)) { 3639 fep->clk_ptp = NULL; 3640 fep->bufdesc_ex = false; 3641 } 3642 3643 ret = fec_enet_clk_enable(ndev, true); 3644 if (ret) 3645 goto failed_clk; 3646 3647 ret = clk_prepare_enable(fep->clk_ipg); 3648 if (ret) 3649 goto failed_clk_ipg; 3650 ret = clk_prepare_enable(fep->clk_ahb); 3651 if (ret) 3652 goto failed_clk_ahb; 3653 3654 fep->reg_phy = devm_regulator_get_optional(&pdev->dev, "phy"); 3655 if (!IS_ERR(fep->reg_phy)) { 3656 ret = regulator_enable(fep->reg_phy); 3657 if (ret) { 3658 dev_err(&pdev->dev, 3659 "Failed to enable phy regulator: %d\n", ret); 3660 goto failed_regulator; 3661 } 3662 } else { 3663 if (PTR_ERR(fep->reg_phy) == -EPROBE_DEFER) { 3664 ret = -EPROBE_DEFER; 3665 goto failed_regulator; 3666 } 3667 fep->reg_phy = NULL; 3668 } 3669 3670 pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT); 3671 pm_runtime_use_autosuspend(&pdev->dev); 3672 pm_runtime_get_noresume(&pdev->dev); 3673 pm_runtime_set_active(&pdev->dev); 3674 pm_runtime_enable(&pdev->dev); 3675 3676 ret = fec_reset_phy(pdev); 3677 if (ret) 3678 goto failed_reset; 3679 3680 irq_cnt = fec_enet_get_irq_cnt(pdev); 3681 if (fep->bufdesc_ex) 3682 fec_ptp_init(pdev, irq_cnt); 3683 3684 ret = fec_enet_init(ndev); 3685 if (ret) 3686 goto failed_init; 3687 3688 for (i = 0; i < irq_cnt; i++) { 3689 snprintf(irq_name, sizeof(irq_name), "int%d", i); 3690 irq = platform_get_irq_byname_optional(pdev, irq_name); 3691 if (irq < 0) 3692 irq = platform_get_irq(pdev, i); 3693 if (irq < 0) { 3694 ret = irq; 3695 goto failed_irq; 3696 } 3697 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt, 3698 0, pdev->name, ndev); 3699 if (ret) 3700 goto failed_irq; 3701 3702 fep->irq[i] = irq; 3703 } 3704 3705 ret = fec_enet_mii_init(pdev); 3706 if (ret) 3707 goto failed_mii_init; 3708 3709 /* Carrier starts down, phylib will bring it up */ 3710 netif_carrier_off(ndev); 3711 fec_enet_clk_enable(ndev, false); 3712 pinctrl_pm_select_sleep_state(&pdev->dev); 3713 3714 ret = register_netdev(ndev); 3715 if (ret) 3716 goto failed_register; 3717 3718 device_init_wakeup(&ndev->dev, fep->wol_flag & 3719 FEC_WOL_HAS_MAGIC_PACKET); 3720 3721 if (fep->bufdesc_ex && fep->ptp_clock) 3722 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id); 3723 3724 fep->rx_copybreak = COPYBREAK_DEFAULT; 3725 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work); 3726 3727 pm_runtime_mark_last_busy(&pdev->dev); 3728 pm_runtime_put_autosuspend(&pdev->dev); 3729 3730 return 0; 3731 3732 failed_register: 3733 fec_enet_mii_remove(fep); 3734 failed_mii_init: 3735 failed_irq: 3736 failed_init: 3737 fec_ptp_stop(pdev); 3738 if (fep->reg_phy) 3739 regulator_disable(fep->reg_phy); 3740 failed_reset: 3741 pm_runtime_put_noidle(&pdev->dev); 3742 pm_runtime_disable(&pdev->dev); 3743 failed_regulator: 3744 clk_disable_unprepare(fep->clk_ahb); 3745 failed_clk_ahb: 3746 clk_disable_unprepare(fep->clk_ipg); 3747 failed_clk_ipg: 3748 fec_enet_clk_enable(ndev, false); 3749 failed_clk: 3750 if (of_phy_is_fixed_link(np)) 3751 of_phy_deregister_fixed_link(np); 3752 of_node_put(phy_node); 3753 failed_stop_mode: 3754 failed_phy: 3755 dev_id--; 3756 failed_ioremap: 3757 free_netdev(ndev); 3758 3759 return ret; 3760 } 3761 3762 static int 3763 fec_drv_remove(struct platform_device *pdev) 3764 { 3765 struct net_device *ndev = platform_get_drvdata(pdev); 3766 struct fec_enet_private *fep = netdev_priv(ndev); 3767 struct device_node *np = pdev->dev.of_node; 3768 int ret; 3769 3770 ret = pm_runtime_get_sync(&pdev->dev); 3771 if (ret < 0) 3772 return ret; 3773 3774 cancel_work_sync(&fep->tx_timeout_work); 3775 fec_ptp_stop(pdev); 3776 unregister_netdev(ndev); 3777 fec_enet_mii_remove(fep); 3778 if (fep->reg_phy) 3779 regulator_disable(fep->reg_phy); 3780 3781 if (of_phy_is_fixed_link(np)) 3782 of_phy_deregister_fixed_link(np); 3783 of_node_put(fep->phy_node); 3784 free_netdev(ndev); 3785 3786 clk_disable_unprepare(fep->clk_ahb); 3787 clk_disable_unprepare(fep->clk_ipg); 3788 pm_runtime_put_noidle(&pdev->dev); 3789 pm_runtime_disable(&pdev->dev); 3790 3791 return 0; 3792 } 3793 3794 static int __maybe_unused fec_suspend(struct device *dev) 3795 { 3796 struct net_device *ndev = dev_get_drvdata(dev); 3797 struct fec_enet_private *fep = netdev_priv(ndev); 3798 3799 rtnl_lock(); 3800 if (netif_running(ndev)) { 3801 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) 3802 fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON; 3803 phy_stop(ndev->phydev); 3804 napi_disable(&fep->napi); 3805 netif_tx_lock_bh(ndev); 3806 netif_device_detach(ndev); 3807 netif_tx_unlock_bh(ndev); 3808 fec_stop(ndev); 3809 fec_enet_clk_enable(ndev, false); 3810 if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) 3811 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3812 } 3813 rtnl_unlock(); 3814 3815 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) 3816 regulator_disable(fep->reg_phy); 3817 3818 /* SOC supply clock to phy, when clock is disabled, phy link down 3819 * SOC control phy regulator, when regulator is disabled, phy link down 3820 */ 3821 if (fep->clk_enet_out || fep->reg_phy) 3822 fep->link = 0; 3823 3824 return 0; 3825 } 3826 3827 static int __maybe_unused fec_resume(struct device *dev) 3828 { 3829 struct net_device *ndev = dev_get_drvdata(dev); 3830 struct fec_enet_private *fep = netdev_priv(ndev); 3831 int ret; 3832 int val; 3833 3834 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) { 3835 ret = regulator_enable(fep->reg_phy); 3836 if (ret) 3837 return ret; 3838 } 3839 3840 rtnl_lock(); 3841 if (netif_running(ndev)) { 3842 ret = fec_enet_clk_enable(ndev, true); 3843 if (ret) { 3844 rtnl_unlock(); 3845 goto failed_clk; 3846 } 3847 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) { 3848 fec_enet_stop_mode(fep, false); 3849 3850 val = readl(fep->hwp + FEC_ECNTRL); 3851 val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP); 3852 writel(val, fep->hwp + FEC_ECNTRL); 3853 fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON; 3854 } else { 3855 pinctrl_pm_select_default_state(&fep->pdev->dev); 3856 } 3857 fec_restart(ndev); 3858 netif_tx_lock_bh(ndev); 3859 netif_device_attach(ndev); 3860 netif_tx_unlock_bh(ndev); 3861 napi_enable(&fep->napi); 3862 phy_start(ndev->phydev); 3863 } 3864 rtnl_unlock(); 3865 3866 return 0; 3867 3868 failed_clk: 3869 if (fep->reg_phy) 3870 regulator_disable(fep->reg_phy); 3871 return ret; 3872 } 3873 3874 static int __maybe_unused fec_runtime_suspend(struct device *dev) 3875 { 3876 struct net_device *ndev = dev_get_drvdata(dev); 3877 struct fec_enet_private *fep = netdev_priv(ndev); 3878 3879 clk_disable_unprepare(fep->clk_ahb); 3880 clk_disable_unprepare(fep->clk_ipg); 3881 3882 return 0; 3883 } 3884 3885 static int __maybe_unused fec_runtime_resume(struct device *dev) 3886 { 3887 struct net_device *ndev = dev_get_drvdata(dev); 3888 struct fec_enet_private *fep = netdev_priv(ndev); 3889 int ret; 3890 3891 ret = clk_prepare_enable(fep->clk_ahb); 3892 if (ret) 3893 return ret; 3894 ret = clk_prepare_enable(fep->clk_ipg); 3895 if (ret) 3896 goto failed_clk_ipg; 3897 3898 return 0; 3899 3900 failed_clk_ipg: 3901 clk_disable_unprepare(fep->clk_ahb); 3902 return ret; 3903 } 3904 3905 static const struct dev_pm_ops fec_pm_ops = { 3906 SET_SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume) 3907 SET_RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL) 3908 }; 3909 3910 static struct platform_driver fec_driver = { 3911 .driver = { 3912 .name = DRIVER_NAME, 3913 .pm = &fec_pm_ops, 3914 .of_match_table = fec_dt_ids, 3915 .suppress_bind_attrs = true, 3916 }, 3917 .id_table = fec_devtype, 3918 .probe = fec_probe, 3919 .remove = fec_drv_remove, 3920 }; 3921 3922 module_platform_driver(fec_driver); 3923 3924 MODULE_ALIAS("platform:"DRIVER_NAME); 3925 MODULE_LICENSE("GPL"); 3926