1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. 4 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) 5 * 6 * Right now, I am very wasteful with the buffers. I allocate memory 7 * pages and then divide them into 2K frame buffers. This way I know I 8 * have buffers large enough to hold one frame within one buffer descriptor. 9 * Once I get this working, I will use 64 or 128 byte CPM buffers, which 10 * will be much more memory efficient and will easily handle lots of 11 * small packets. 12 * 13 * Much better multiple PHY support by Magnus Damm. 14 * Copyright (c) 2000 Ericsson Radio Systems AB. 15 * 16 * Support for FEC controller of ColdFire processors. 17 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) 18 * 19 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) 20 * Copyright (c) 2004-2006 Macq Electronique SA. 21 * 22 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. 23 */ 24 25 #include <linux/module.h> 26 #include <linux/kernel.h> 27 #include <linux/string.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/ptrace.h> 30 #include <linux/errno.h> 31 #include <linux/ioport.h> 32 #include <linux/slab.h> 33 #include <linux/interrupt.h> 34 #include <linux/delay.h> 35 #include <linux/netdevice.h> 36 #include <linux/etherdevice.h> 37 #include <linux/skbuff.h> 38 #include <linux/in.h> 39 #include <linux/ip.h> 40 #include <net/ip.h> 41 #include <net/selftests.h> 42 #include <net/tso.h> 43 #include <linux/tcp.h> 44 #include <linux/udp.h> 45 #include <linux/icmp.h> 46 #include <linux/spinlock.h> 47 #include <linux/workqueue.h> 48 #include <linux/bitops.h> 49 #include <linux/io.h> 50 #include <linux/irq.h> 51 #include <linux/clk.h> 52 #include <linux/crc32.h> 53 #include <linux/platform_device.h> 54 #include <linux/mdio.h> 55 #include <linux/phy.h> 56 #include <linux/fec.h> 57 #include <linux/of.h> 58 #include <linux/of_device.h> 59 #include <linux/of_gpio.h> 60 #include <linux/of_mdio.h> 61 #include <linux/of_net.h> 62 #include <linux/regulator/consumer.h> 63 #include <linux/if_vlan.h> 64 #include <linux/pinctrl/consumer.h> 65 #include <linux/prefetch.h> 66 #include <linux/mfd/syscon.h> 67 #include <linux/regmap.h> 68 #include <soc/imx/cpuidle.h> 69 70 #include <asm/cacheflush.h> 71 72 #include "fec.h" 73 74 static void set_multicast_list(struct net_device *ndev); 75 static void fec_enet_itr_coal_init(struct net_device *ndev); 76 77 #define DRIVER_NAME "fec" 78 79 static const u16 fec_enet_vlan_pri_to_queue[8] = {0, 0, 1, 1, 1, 2, 2, 2}; 80 81 /* Pause frame feild and FIFO threshold */ 82 #define FEC_ENET_FCE (1 << 5) 83 #define FEC_ENET_RSEM_V 0x84 84 #define FEC_ENET_RSFL_V 16 85 #define FEC_ENET_RAEM_V 0x8 86 #define FEC_ENET_RAFL_V 0x8 87 #define FEC_ENET_OPD_V 0xFFF0 88 #define FEC_MDIO_PM_TIMEOUT 100 /* ms */ 89 90 struct fec_devinfo { 91 u32 quirks; 92 }; 93 94 static const struct fec_devinfo fec_imx25_info = { 95 .quirks = FEC_QUIRK_USE_GASKET | FEC_QUIRK_MIB_CLEAR | 96 FEC_QUIRK_HAS_FRREG, 97 }; 98 99 static const struct fec_devinfo fec_imx27_info = { 100 .quirks = FEC_QUIRK_MIB_CLEAR | FEC_QUIRK_HAS_FRREG, 101 }; 102 103 static const struct fec_devinfo fec_imx28_info = { 104 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME | 105 FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC | 106 FEC_QUIRK_HAS_FRREG | FEC_QUIRK_CLEAR_SETUP_MII | 107 FEC_QUIRK_NO_HARD_RESET, 108 }; 109 110 static const struct fec_devinfo fec_imx6q_info = { 111 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 112 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 113 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 | 114 FEC_QUIRK_HAS_RACC | FEC_QUIRK_CLEAR_SETUP_MII | 115 FEC_QUIRK_HAS_PMQOS, 116 }; 117 118 static const struct fec_devinfo fec_mvf600_info = { 119 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC, 120 }; 121 122 static const struct fec_devinfo fec_imx6x_info = { 123 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 124 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 125 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 126 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 127 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE | 128 FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES, 129 }; 130 131 static const struct fec_devinfo fec_imx6ul_info = { 132 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 133 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 134 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR007885 | 135 FEC_QUIRK_BUG_CAPTURE | FEC_QUIRK_HAS_RACC | 136 FEC_QUIRK_HAS_COALESCE | FEC_QUIRK_CLEAR_SETUP_MII, 137 }; 138 139 static const struct fec_devinfo fec_imx8mq_info = { 140 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 141 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 142 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 143 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 144 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE | 145 FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES | 146 FEC_QUIRK_HAS_EEE | FEC_QUIRK_WAKEUP_FROM_INT2, 147 }; 148 149 static const struct fec_devinfo fec_imx8qm_info = { 150 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 151 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 152 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 153 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 154 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE | 155 FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES | 156 FEC_QUIRK_DELAYED_CLKS_SUPPORT, 157 }; 158 159 static struct platform_device_id fec_devtype[] = { 160 { 161 /* keep it for coldfire */ 162 .name = DRIVER_NAME, 163 .driver_data = 0, 164 }, { 165 .name = "imx25-fec", 166 .driver_data = (kernel_ulong_t)&fec_imx25_info, 167 }, { 168 .name = "imx27-fec", 169 .driver_data = (kernel_ulong_t)&fec_imx27_info, 170 }, { 171 .name = "imx28-fec", 172 .driver_data = (kernel_ulong_t)&fec_imx28_info, 173 }, { 174 .name = "imx6q-fec", 175 .driver_data = (kernel_ulong_t)&fec_imx6q_info, 176 }, { 177 .name = "mvf600-fec", 178 .driver_data = (kernel_ulong_t)&fec_mvf600_info, 179 }, { 180 .name = "imx6sx-fec", 181 .driver_data = (kernel_ulong_t)&fec_imx6x_info, 182 }, { 183 .name = "imx6ul-fec", 184 .driver_data = (kernel_ulong_t)&fec_imx6ul_info, 185 }, { 186 .name = "imx8mq-fec", 187 .driver_data = (kernel_ulong_t)&fec_imx8mq_info, 188 }, { 189 .name = "imx8qm-fec", 190 .driver_data = (kernel_ulong_t)&fec_imx8qm_info, 191 }, { 192 /* sentinel */ 193 } 194 }; 195 MODULE_DEVICE_TABLE(platform, fec_devtype); 196 197 enum imx_fec_type { 198 IMX25_FEC = 1, /* runs on i.mx25/50/53 */ 199 IMX27_FEC, /* runs on i.mx27/35/51 */ 200 IMX28_FEC, 201 IMX6Q_FEC, 202 MVF600_FEC, 203 IMX6SX_FEC, 204 IMX6UL_FEC, 205 IMX8MQ_FEC, 206 IMX8QM_FEC, 207 }; 208 209 static const struct of_device_id fec_dt_ids[] = { 210 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], }, 211 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], }, 212 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], }, 213 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], }, 214 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], }, 215 { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], }, 216 { .compatible = "fsl,imx6ul-fec", .data = &fec_devtype[IMX6UL_FEC], }, 217 { .compatible = "fsl,imx8mq-fec", .data = &fec_devtype[IMX8MQ_FEC], }, 218 { .compatible = "fsl,imx8qm-fec", .data = &fec_devtype[IMX8QM_FEC], }, 219 { /* sentinel */ } 220 }; 221 MODULE_DEVICE_TABLE(of, fec_dt_ids); 222 223 static unsigned char macaddr[ETH_ALEN]; 224 module_param_array(macaddr, byte, NULL, 0); 225 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address"); 226 227 #if defined(CONFIG_M5272) 228 /* 229 * Some hardware gets it MAC address out of local flash memory. 230 * if this is non-zero then assume it is the address to get MAC from. 231 */ 232 #if defined(CONFIG_NETtel) 233 #define FEC_FLASHMAC 0xf0006006 234 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) 235 #define FEC_FLASHMAC 0xf0006000 236 #elif defined(CONFIG_CANCam) 237 #define FEC_FLASHMAC 0xf0020000 238 #elif defined (CONFIG_M5272C3) 239 #define FEC_FLASHMAC (0xffe04000 + 4) 240 #elif defined(CONFIG_MOD5272) 241 #define FEC_FLASHMAC 0xffc0406b 242 #else 243 #define FEC_FLASHMAC 0 244 #endif 245 #endif /* CONFIG_M5272 */ 246 247 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets. 248 * 249 * 2048 byte skbufs are allocated. However, alignment requirements 250 * varies between FEC variants. Worst case is 64, so round down by 64. 251 */ 252 #define PKT_MAXBUF_SIZE (round_down(2048 - 64, 64)) 253 #define PKT_MINBUF_SIZE 64 254 255 /* FEC receive acceleration */ 256 #define FEC_RACC_IPDIS (1 << 1) 257 #define FEC_RACC_PRODIS (1 << 2) 258 #define FEC_RACC_SHIFT16 BIT(7) 259 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS) 260 261 /* MIB Control Register */ 262 #define FEC_MIB_CTRLSTAT_DISABLE BIT(31) 263 264 /* 265 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame 266 * size bits. Other FEC hardware does not, so we need to take that into 267 * account when setting it. 268 */ 269 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 270 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \ 271 defined(CONFIG_ARM64) 272 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) 273 #else 274 #define OPT_FRAME_SIZE 0 275 #endif 276 277 /* FEC MII MMFR bits definition */ 278 #define FEC_MMFR_ST (1 << 30) 279 #define FEC_MMFR_ST_C45 (0) 280 #define FEC_MMFR_OP_READ (2 << 28) 281 #define FEC_MMFR_OP_READ_C45 (3 << 28) 282 #define FEC_MMFR_OP_WRITE (1 << 28) 283 #define FEC_MMFR_OP_ADDR_WRITE (0) 284 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23) 285 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18) 286 #define FEC_MMFR_TA (2 << 16) 287 #define FEC_MMFR_DATA(v) (v & 0xffff) 288 /* FEC ECR bits definition */ 289 #define FEC_ECR_MAGICEN (1 << 2) 290 #define FEC_ECR_SLEEP (1 << 3) 291 292 #define FEC_MII_TIMEOUT 30000 /* us */ 293 294 /* Transmitter timeout */ 295 #define TX_TIMEOUT (2 * HZ) 296 297 #define FEC_PAUSE_FLAG_AUTONEG 0x1 298 #define FEC_PAUSE_FLAG_ENABLE 0x2 299 #define FEC_WOL_HAS_MAGIC_PACKET (0x1 << 0) 300 #define FEC_WOL_FLAG_ENABLE (0x1 << 1) 301 #define FEC_WOL_FLAG_SLEEP_ON (0x1 << 2) 302 303 #define COPYBREAK_DEFAULT 256 304 305 /* Max number of allowed TCP segments for software TSO */ 306 #define FEC_MAX_TSO_SEGS 100 307 #define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) 308 309 #define IS_TSO_HEADER(txq, addr) \ 310 ((addr >= txq->tso_hdrs_dma) && \ 311 (addr < txq->tso_hdrs_dma + txq->bd.ring_size * TSO_HEADER_SIZE)) 312 313 static int mii_cnt; 314 315 static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, 316 struct bufdesc_prop *bd) 317 { 318 return (bdp >= bd->last) ? bd->base 319 : (struct bufdesc *)(((void *)bdp) + bd->dsize); 320 } 321 322 static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, 323 struct bufdesc_prop *bd) 324 { 325 return (bdp <= bd->base) ? bd->last 326 : (struct bufdesc *)(((void *)bdp) - bd->dsize); 327 } 328 329 static int fec_enet_get_bd_index(struct bufdesc *bdp, 330 struct bufdesc_prop *bd) 331 { 332 return ((const char *)bdp - (const char *)bd->base) >> bd->dsize_log2; 333 } 334 335 static int fec_enet_get_free_txdesc_num(struct fec_enet_priv_tx_q *txq) 336 { 337 int entries; 338 339 entries = (((const char *)txq->dirty_tx - 340 (const char *)txq->bd.cur) >> txq->bd.dsize_log2) - 1; 341 342 return entries >= 0 ? entries : entries + txq->bd.ring_size; 343 } 344 345 static void swap_buffer(void *bufaddr, int len) 346 { 347 int i; 348 unsigned int *buf = bufaddr; 349 350 for (i = 0; i < len; i += 4, buf++) 351 swab32s(buf); 352 } 353 354 static void swap_buffer2(void *dst_buf, void *src_buf, int len) 355 { 356 int i; 357 unsigned int *src = src_buf; 358 unsigned int *dst = dst_buf; 359 360 for (i = 0; i < len; i += 4, src++, dst++) 361 *dst = swab32p(src); 362 } 363 364 static void fec_dump(struct net_device *ndev) 365 { 366 struct fec_enet_private *fep = netdev_priv(ndev); 367 struct bufdesc *bdp; 368 struct fec_enet_priv_tx_q *txq; 369 int index = 0; 370 371 netdev_info(ndev, "TX ring dump\n"); 372 pr_info("Nr SC addr len SKB\n"); 373 374 txq = fep->tx_queue[0]; 375 bdp = txq->bd.base; 376 377 do { 378 pr_info("%3u %c%c 0x%04x 0x%08x %4u %p\n", 379 index, 380 bdp == txq->bd.cur ? 'S' : ' ', 381 bdp == txq->dirty_tx ? 'H' : ' ', 382 fec16_to_cpu(bdp->cbd_sc), 383 fec32_to_cpu(bdp->cbd_bufaddr), 384 fec16_to_cpu(bdp->cbd_datlen), 385 txq->tx_skbuff[index]); 386 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 387 index++; 388 } while (bdp != txq->bd.base); 389 } 390 391 static inline bool is_ipv4_pkt(struct sk_buff *skb) 392 { 393 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4; 394 } 395 396 static int 397 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev) 398 { 399 /* Only run for packets requiring a checksum. */ 400 if (skb->ip_summed != CHECKSUM_PARTIAL) 401 return 0; 402 403 if (unlikely(skb_cow_head(skb, 0))) 404 return -1; 405 406 if (is_ipv4_pkt(skb)) 407 ip_hdr(skb)->check = 0; 408 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0; 409 410 return 0; 411 } 412 413 static struct bufdesc * 414 fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq, 415 struct sk_buff *skb, 416 struct net_device *ndev) 417 { 418 struct fec_enet_private *fep = netdev_priv(ndev); 419 struct bufdesc *bdp = txq->bd.cur; 420 struct bufdesc_ex *ebdp; 421 int nr_frags = skb_shinfo(skb)->nr_frags; 422 int frag, frag_len; 423 unsigned short status; 424 unsigned int estatus = 0; 425 skb_frag_t *this_frag; 426 unsigned int index; 427 void *bufaddr; 428 dma_addr_t addr; 429 int i; 430 431 for (frag = 0; frag < nr_frags; frag++) { 432 this_frag = &skb_shinfo(skb)->frags[frag]; 433 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 434 ebdp = (struct bufdesc_ex *)bdp; 435 436 status = fec16_to_cpu(bdp->cbd_sc); 437 status &= ~BD_ENET_TX_STATS; 438 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 439 frag_len = skb_frag_size(&skb_shinfo(skb)->frags[frag]); 440 441 /* Handle the last BD specially */ 442 if (frag == nr_frags - 1) { 443 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 444 if (fep->bufdesc_ex) { 445 estatus |= BD_ENET_TX_INT; 446 if (unlikely(skb_shinfo(skb)->tx_flags & 447 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 448 estatus |= BD_ENET_TX_TS; 449 } 450 } 451 452 if (fep->bufdesc_ex) { 453 if (fep->quirks & FEC_QUIRK_HAS_AVB) 454 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 455 if (skb->ip_summed == CHECKSUM_PARTIAL) 456 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 457 458 ebdp->cbd_bdu = 0; 459 ebdp->cbd_esc = cpu_to_fec32(estatus); 460 } 461 462 bufaddr = skb_frag_address(this_frag); 463 464 index = fec_enet_get_bd_index(bdp, &txq->bd); 465 if (((unsigned long) bufaddr) & fep->tx_align || 466 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 467 memcpy(txq->tx_bounce[index], bufaddr, frag_len); 468 bufaddr = txq->tx_bounce[index]; 469 470 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 471 swap_buffer(bufaddr, frag_len); 472 } 473 474 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len, 475 DMA_TO_DEVICE); 476 if (dma_mapping_error(&fep->pdev->dev, addr)) { 477 if (net_ratelimit()) 478 netdev_err(ndev, "Tx DMA memory map failed\n"); 479 goto dma_mapping_error; 480 } 481 482 bdp->cbd_bufaddr = cpu_to_fec32(addr); 483 bdp->cbd_datlen = cpu_to_fec16(frag_len); 484 /* Make sure the updates to rest of the descriptor are 485 * performed before transferring ownership. 486 */ 487 wmb(); 488 bdp->cbd_sc = cpu_to_fec16(status); 489 } 490 491 return bdp; 492 dma_mapping_error: 493 bdp = txq->bd.cur; 494 for (i = 0; i < frag; i++) { 495 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 496 dma_unmap_single(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr), 497 fec16_to_cpu(bdp->cbd_datlen), DMA_TO_DEVICE); 498 } 499 return ERR_PTR(-ENOMEM); 500 } 501 502 static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq, 503 struct sk_buff *skb, struct net_device *ndev) 504 { 505 struct fec_enet_private *fep = netdev_priv(ndev); 506 int nr_frags = skb_shinfo(skb)->nr_frags; 507 struct bufdesc *bdp, *last_bdp; 508 void *bufaddr; 509 dma_addr_t addr; 510 unsigned short status; 511 unsigned short buflen; 512 unsigned int estatus = 0; 513 unsigned int index; 514 int entries_free; 515 516 entries_free = fec_enet_get_free_txdesc_num(txq); 517 if (entries_free < MAX_SKB_FRAGS + 1) { 518 dev_kfree_skb_any(skb); 519 if (net_ratelimit()) 520 netdev_err(ndev, "NOT enough BD for SG!\n"); 521 return NETDEV_TX_OK; 522 } 523 524 /* Protocol checksum off-load for TCP and UDP. */ 525 if (fec_enet_clear_csum(skb, ndev)) { 526 dev_kfree_skb_any(skb); 527 return NETDEV_TX_OK; 528 } 529 530 /* Fill in a Tx ring entry */ 531 bdp = txq->bd.cur; 532 last_bdp = bdp; 533 status = fec16_to_cpu(bdp->cbd_sc); 534 status &= ~BD_ENET_TX_STATS; 535 536 /* Set buffer length and buffer pointer */ 537 bufaddr = skb->data; 538 buflen = skb_headlen(skb); 539 540 index = fec_enet_get_bd_index(bdp, &txq->bd); 541 if (((unsigned long) bufaddr) & fep->tx_align || 542 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 543 memcpy(txq->tx_bounce[index], skb->data, buflen); 544 bufaddr = txq->tx_bounce[index]; 545 546 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 547 swap_buffer(bufaddr, buflen); 548 } 549 550 /* Push the data cache so the CPM does not get stale memory data. */ 551 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE); 552 if (dma_mapping_error(&fep->pdev->dev, addr)) { 553 dev_kfree_skb_any(skb); 554 if (net_ratelimit()) 555 netdev_err(ndev, "Tx DMA memory map failed\n"); 556 return NETDEV_TX_OK; 557 } 558 559 if (nr_frags) { 560 last_bdp = fec_enet_txq_submit_frag_skb(txq, skb, ndev); 561 if (IS_ERR(last_bdp)) { 562 dma_unmap_single(&fep->pdev->dev, addr, 563 buflen, DMA_TO_DEVICE); 564 dev_kfree_skb_any(skb); 565 return NETDEV_TX_OK; 566 } 567 } else { 568 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 569 if (fep->bufdesc_ex) { 570 estatus = BD_ENET_TX_INT; 571 if (unlikely(skb_shinfo(skb)->tx_flags & 572 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 573 estatus |= BD_ENET_TX_TS; 574 } 575 } 576 bdp->cbd_bufaddr = cpu_to_fec32(addr); 577 bdp->cbd_datlen = cpu_to_fec16(buflen); 578 579 if (fep->bufdesc_ex) { 580 581 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 582 583 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 584 fep->hwts_tx_en)) 585 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 586 587 if (fep->quirks & FEC_QUIRK_HAS_AVB) 588 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 589 590 if (skb->ip_summed == CHECKSUM_PARTIAL) 591 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 592 593 ebdp->cbd_bdu = 0; 594 ebdp->cbd_esc = cpu_to_fec32(estatus); 595 } 596 597 index = fec_enet_get_bd_index(last_bdp, &txq->bd); 598 /* Save skb pointer */ 599 txq->tx_skbuff[index] = skb; 600 601 /* Make sure the updates to rest of the descriptor are performed before 602 * transferring ownership. 603 */ 604 wmb(); 605 606 /* Send it on its way. Tell FEC it's ready, interrupt when done, 607 * it's the last BD of the frame, and to put the CRC on the end. 608 */ 609 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC); 610 bdp->cbd_sc = cpu_to_fec16(status); 611 612 /* If this was the last BD in the ring, start at the beginning again. */ 613 bdp = fec_enet_get_nextdesc(last_bdp, &txq->bd); 614 615 skb_tx_timestamp(skb); 616 617 /* Make sure the update to bdp and tx_skbuff are performed before 618 * txq->bd.cur. 619 */ 620 wmb(); 621 txq->bd.cur = bdp; 622 623 /* Trigger transmission start */ 624 writel(0, txq->bd.reg_desc_active); 625 626 return 0; 627 } 628 629 static int 630 fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb, 631 struct net_device *ndev, 632 struct bufdesc *bdp, int index, char *data, 633 int size, bool last_tcp, bool is_last) 634 { 635 struct fec_enet_private *fep = netdev_priv(ndev); 636 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 637 unsigned short status; 638 unsigned int estatus = 0; 639 dma_addr_t addr; 640 641 status = fec16_to_cpu(bdp->cbd_sc); 642 status &= ~BD_ENET_TX_STATS; 643 644 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 645 646 if (((unsigned long) data) & fep->tx_align || 647 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 648 memcpy(txq->tx_bounce[index], data, size); 649 data = txq->tx_bounce[index]; 650 651 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 652 swap_buffer(data, size); 653 } 654 655 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE); 656 if (dma_mapping_error(&fep->pdev->dev, addr)) { 657 dev_kfree_skb_any(skb); 658 if (net_ratelimit()) 659 netdev_err(ndev, "Tx DMA memory map failed\n"); 660 return NETDEV_TX_BUSY; 661 } 662 663 bdp->cbd_datlen = cpu_to_fec16(size); 664 bdp->cbd_bufaddr = cpu_to_fec32(addr); 665 666 if (fep->bufdesc_ex) { 667 if (fep->quirks & FEC_QUIRK_HAS_AVB) 668 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 669 if (skb->ip_summed == CHECKSUM_PARTIAL) 670 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 671 ebdp->cbd_bdu = 0; 672 ebdp->cbd_esc = cpu_to_fec32(estatus); 673 } 674 675 /* Handle the last BD specially */ 676 if (last_tcp) 677 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC); 678 if (is_last) { 679 status |= BD_ENET_TX_INTR; 680 if (fep->bufdesc_ex) 681 ebdp->cbd_esc |= cpu_to_fec32(BD_ENET_TX_INT); 682 } 683 684 bdp->cbd_sc = cpu_to_fec16(status); 685 686 return 0; 687 } 688 689 static int 690 fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq, 691 struct sk_buff *skb, struct net_device *ndev, 692 struct bufdesc *bdp, int index) 693 { 694 struct fec_enet_private *fep = netdev_priv(ndev); 695 int hdr_len = skb_tcp_all_headers(skb); 696 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 697 void *bufaddr; 698 unsigned long dmabuf; 699 unsigned short status; 700 unsigned int estatus = 0; 701 702 status = fec16_to_cpu(bdp->cbd_sc); 703 status &= ~BD_ENET_TX_STATS; 704 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 705 706 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 707 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE; 708 if (((unsigned long)bufaddr) & fep->tx_align || 709 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 710 memcpy(txq->tx_bounce[index], skb->data, hdr_len); 711 bufaddr = txq->tx_bounce[index]; 712 713 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 714 swap_buffer(bufaddr, hdr_len); 715 716 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr, 717 hdr_len, DMA_TO_DEVICE); 718 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) { 719 dev_kfree_skb_any(skb); 720 if (net_ratelimit()) 721 netdev_err(ndev, "Tx DMA memory map failed\n"); 722 return NETDEV_TX_BUSY; 723 } 724 } 725 726 bdp->cbd_bufaddr = cpu_to_fec32(dmabuf); 727 bdp->cbd_datlen = cpu_to_fec16(hdr_len); 728 729 if (fep->bufdesc_ex) { 730 if (fep->quirks & FEC_QUIRK_HAS_AVB) 731 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 732 if (skb->ip_summed == CHECKSUM_PARTIAL) 733 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 734 ebdp->cbd_bdu = 0; 735 ebdp->cbd_esc = cpu_to_fec32(estatus); 736 } 737 738 bdp->cbd_sc = cpu_to_fec16(status); 739 740 return 0; 741 } 742 743 static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq, 744 struct sk_buff *skb, 745 struct net_device *ndev) 746 { 747 struct fec_enet_private *fep = netdev_priv(ndev); 748 int hdr_len, total_len, data_left; 749 struct bufdesc *bdp = txq->bd.cur; 750 struct tso_t tso; 751 unsigned int index = 0; 752 int ret; 753 754 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(txq)) { 755 dev_kfree_skb_any(skb); 756 if (net_ratelimit()) 757 netdev_err(ndev, "NOT enough BD for TSO!\n"); 758 return NETDEV_TX_OK; 759 } 760 761 /* Protocol checksum off-load for TCP and UDP. */ 762 if (fec_enet_clear_csum(skb, ndev)) { 763 dev_kfree_skb_any(skb); 764 return NETDEV_TX_OK; 765 } 766 767 /* Initialize the TSO handler, and prepare the first payload */ 768 hdr_len = tso_start(skb, &tso); 769 770 total_len = skb->len - hdr_len; 771 while (total_len > 0) { 772 char *hdr; 773 774 index = fec_enet_get_bd_index(bdp, &txq->bd); 775 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); 776 total_len -= data_left; 777 778 /* prepare packet headers: MAC + IP + TCP */ 779 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 780 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); 781 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index); 782 if (ret) 783 goto err_release; 784 785 while (data_left > 0) { 786 int size; 787 788 size = min_t(int, tso.size, data_left); 789 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 790 index = fec_enet_get_bd_index(bdp, &txq->bd); 791 ret = fec_enet_txq_put_data_tso(txq, skb, ndev, 792 bdp, index, 793 tso.data, size, 794 size == data_left, 795 total_len == 0); 796 if (ret) 797 goto err_release; 798 799 data_left -= size; 800 tso_build_data(skb, &tso, size); 801 } 802 803 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 804 } 805 806 /* Save skb pointer */ 807 txq->tx_skbuff[index] = skb; 808 809 skb_tx_timestamp(skb); 810 txq->bd.cur = bdp; 811 812 /* Trigger transmission start */ 813 if (!(fep->quirks & FEC_QUIRK_ERR007885) || 814 !readl(txq->bd.reg_desc_active) || 815 !readl(txq->bd.reg_desc_active) || 816 !readl(txq->bd.reg_desc_active) || 817 !readl(txq->bd.reg_desc_active)) 818 writel(0, txq->bd.reg_desc_active); 819 820 return 0; 821 822 err_release: 823 /* TODO: Release all used data descriptors for TSO */ 824 return ret; 825 } 826 827 static netdev_tx_t 828 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) 829 { 830 struct fec_enet_private *fep = netdev_priv(ndev); 831 int entries_free; 832 unsigned short queue; 833 struct fec_enet_priv_tx_q *txq; 834 struct netdev_queue *nq; 835 int ret; 836 837 queue = skb_get_queue_mapping(skb); 838 txq = fep->tx_queue[queue]; 839 nq = netdev_get_tx_queue(ndev, queue); 840 841 if (skb_is_gso(skb)) 842 ret = fec_enet_txq_submit_tso(txq, skb, ndev); 843 else 844 ret = fec_enet_txq_submit_skb(txq, skb, ndev); 845 if (ret) 846 return ret; 847 848 entries_free = fec_enet_get_free_txdesc_num(txq); 849 if (entries_free <= txq->tx_stop_threshold) 850 netif_tx_stop_queue(nq); 851 852 return NETDEV_TX_OK; 853 } 854 855 /* Init RX & TX buffer descriptors 856 */ 857 static void fec_enet_bd_init(struct net_device *dev) 858 { 859 struct fec_enet_private *fep = netdev_priv(dev); 860 struct fec_enet_priv_tx_q *txq; 861 struct fec_enet_priv_rx_q *rxq; 862 struct bufdesc *bdp; 863 unsigned int i; 864 unsigned int q; 865 866 for (q = 0; q < fep->num_rx_queues; q++) { 867 /* Initialize the receive buffer descriptors. */ 868 rxq = fep->rx_queue[q]; 869 bdp = rxq->bd.base; 870 871 for (i = 0; i < rxq->bd.ring_size; i++) { 872 873 /* Initialize the BD for every fragment in the page. */ 874 if (bdp->cbd_bufaddr) 875 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); 876 else 877 bdp->cbd_sc = cpu_to_fec16(0); 878 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 879 } 880 881 /* Set the last buffer to wrap */ 882 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); 883 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 884 885 rxq->bd.cur = rxq->bd.base; 886 } 887 888 for (q = 0; q < fep->num_tx_queues; q++) { 889 /* ...and the same for transmit */ 890 txq = fep->tx_queue[q]; 891 bdp = txq->bd.base; 892 txq->bd.cur = bdp; 893 894 for (i = 0; i < txq->bd.ring_size; i++) { 895 /* Initialize the BD for every fragment in the page. */ 896 bdp->cbd_sc = cpu_to_fec16(0); 897 if (bdp->cbd_bufaddr && 898 !IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr))) 899 dma_unmap_single(&fep->pdev->dev, 900 fec32_to_cpu(bdp->cbd_bufaddr), 901 fec16_to_cpu(bdp->cbd_datlen), 902 DMA_TO_DEVICE); 903 if (txq->tx_skbuff[i]) { 904 dev_kfree_skb_any(txq->tx_skbuff[i]); 905 txq->tx_skbuff[i] = NULL; 906 } 907 bdp->cbd_bufaddr = cpu_to_fec32(0); 908 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 909 } 910 911 /* Set the last buffer to wrap */ 912 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); 913 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 914 txq->dirty_tx = bdp; 915 } 916 } 917 918 static void fec_enet_active_rxring(struct net_device *ndev) 919 { 920 struct fec_enet_private *fep = netdev_priv(ndev); 921 int i; 922 923 for (i = 0; i < fep->num_rx_queues; i++) 924 writel(0, fep->rx_queue[i]->bd.reg_desc_active); 925 } 926 927 static void fec_enet_enable_ring(struct net_device *ndev) 928 { 929 struct fec_enet_private *fep = netdev_priv(ndev); 930 struct fec_enet_priv_tx_q *txq; 931 struct fec_enet_priv_rx_q *rxq; 932 int i; 933 934 for (i = 0; i < fep->num_rx_queues; i++) { 935 rxq = fep->rx_queue[i]; 936 writel(rxq->bd.dma, fep->hwp + FEC_R_DES_START(i)); 937 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i)); 938 939 /* enable DMA1/2 */ 940 if (i) 941 writel(RCMR_MATCHEN | RCMR_CMP(i), 942 fep->hwp + FEC_RCMR(i)); 943 } 944 945 for (i = 0; i < fep->num_tx_queues; i++) { 946 txq = fep->tx_queue[i]; 947 writel(txq->bd.dma, fep->hwp + FEC_X_DES_START(i)); 948 949 /* enable DMA1/2 */ 950 if (i) 951 writel(DMA_CLASS_EN | IDLE_SLOPE(i), 952 fep->hwp + FEC_DMA_CFG(i)); 953 } 954 } 955 956 static void fec_enet_reset_skb(struct net_device *ndev) 957 { 958 struct fec_enet_private *fep = netdev_priv(ndev); 959 struct fec_enet_priv_tx_q *txq; 960 int i, j; 961 962 for (i = 0; i < fep->num_tx_queues; i++) { 963 txq = fep->tx_queue[i]; 964 965 for (j = 0; j < txq->bd.ring_size; j++) { 966 if (txq->tx_skbuff[j]) { 967 dev_kfree_skb_any(txq->tx_skbuff[j]); 968 txq->tx_skbuff[j] = NULL; 969 } 970 } 971 } 972 } 973 974 /* 975 * This function is called to start or restart the FEC during a link 976 * change, transmit timeout, or to reconfigure the FEC. The network 977 * packet processing for this device must be stopped before this call. 978 */ 979 static void 980 fec_restart(struct net_device *ndev) 981 { 982 struct fec_enet_private *fep = netdev_priv(ndev); 983 u32 temp_mac[2]; 984 u32 rcntl = OPT_FRAME_SIZE | 0x04; 985 u32 ecntl = 0x2; /* ETHEREN */ 986 987 /* Whack a reset. We should wait for this. 988 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC 989 * instead of reset MAC itself. 990 */ 991 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES || 992 ((fep->quirks & FEC_QUIRK_NO_HARD_RESET) && fep->link)) { 993 writel(0, fep->hwp + FEC_ECNTRL); 994 } else { 995 writel(1, fep->hwp + FEC_ECNTRL); 996 udelay(10); 997 } 998 999 /* 1000 * enet-mac reset will reset mac address registers too, 1001 * so need to reconfigure it. 1002 */ 1003 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN); 1004 writel((__force u32)cpu_to_be32(temp_mac[0]), 1005 fep->hwp + FEC_ADDR_LOW); 1006 writel((__force u32)cpu_to_be32(temp_mac[1]), 1007 fep->hwp + FEC_ADDR_HIGH); 1008 1009 /* Clear any outstanding interrupt, except MDIO. */ 1010 writel((0xffffffff & ~FEC_ENET_MII), fep->hwp + FEC_IEVENT); 1011 1012 fec_enet_bd_init(ndev); 1013 1014 fec_enet_enable_ring(ndev); 1015 1016 /* Reset tx SKB buffers. */ 1017 fec_enet_reset_skb(ndev); 1018 1019 /* Enable MII mode */ 1020 if (fep->full_duplex == DUPLEX_FULL) { 1021 /* FD enable */ 1022 writel(0x04, fep->hwp + FEC_X_CNTRL); 1023 } else { 1024 /* No Rcv on Xmit */ 1025 rcntl |= 0x02; 1026 writel(0x0, fep->hwp + FEC_X_CNTRL); 1027 } 1028 1029 /* Set MII speed */ 1030 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1031 1032 #if !defined(CONFIG_M5272) 1033 if (fep->quirks & FEC_QUIRK_HAS_RACC) { 1034 u32 val = readl(fep->hwp + FEC_RACC); 1035 1036 /* align IP header */ 1037 val |= FEC_RACC_SHIFT16; 1038 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED) 1039 /* set RX checksum */ 1040 val |= FEC_RACC_OPTIONS; 1041 else 1042 val &= ~FEC_RACC_OPTIONS; 1043 writel(val, fep->hwp + FEC_RACC); 1044 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_FTRL); 1045 } 1046 #endif 1047 1048 /* 1049 * The phy interface and speed need to get configured 1050 * differently on enet-mac. 1051 */ 1052 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 1053 /* Enable flow control and length check */ 1054 rcntl |= 0x40000000 | 0x00000020; 1055 1056 /* RGMII, RMII or MII */ 1057 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII || 1058 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 1059 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID || 1060 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) 1061 rcntl |= (1 << 6); 1062 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 1063 rcntl |= (1 << 8); 1064 else 1065 rcntl &= ~(1 << 8); 1066 1067 /* 1G, 100M or 10M */ 1068 if (ndev->phydev) { 1069 if (ndev->phydev->speed == SPEED_1000) 1070 ecntl |= (1 << 5); 1071 else if (ndev->phydev->speed == SPEED_100) 1072 rcntl &= ~(1 << 9); 1073 else 1074 rcntl |= (1 << 9); 1075 } 1076 } else { 1077 #ifdef FEC_MIIGSK_ENR 1078 if (fep->quirks & FEC_QUIRK_USE_GASKET) { 1079 u32 cfgr; 1080 /* disable the gasket and wait */ 1081 writel(0, fep->hwp + FEC_MIIGSK_ENR); 1082 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4) 1083 udelay(1); 1084 1085 /* 1086 * configure the gasket: 1087 * RMII, 50 MHz, no loopback, no echo 1088 * MII, 25 MHz, no loopback, no echo 1089 */ 1090 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 1091 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII; 1092 if (ndev->phydev && ndev->phydev->speed == SPEED_10) 1093 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M; 1094 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR); 1095 1096 /* re-enable the gasket */ 1097 writel(2, fep->hwp + FEC_MIIGSK_ENR); 1098 } 1099 #endif 1100 } 1101 1102 #if !defined(CONFIG_M5272) 1103 /* enable pause frame*/ 1104 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) || 1105 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) && 1106 ndev->phydev && ndev->phydev->pause)) { 1107 rcntl |= FEC_ENET_FCE; 1108 1109 /* set FIFO threshold parameter to reduce overrun */ 1110 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM); 1111 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL); 1112 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM); 1113 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL); 1114 1115 /* OPD */ 1116 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD); 1117 } else { 1118 rcntl &= ~FEC_ENET_FCE; 1119 } 1120 #endif /* !defined(CONFIG_M5272) */ 1121 1122 writel(rcntl, fep->hwp + FEC_R_CNTRL); 1123 1124 /* Setup multicast filter. */ 1125 set_multicast_list(ndev); 1126 #ifndef CONFIG_M5272 1127 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); 1128 writel(0, fep->hwp + FEC_HASH_TABLE_LOW); 1129 #endif 1130 1131 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 1132 /* enable ENET endian swap */ 1133 ecntl |= (1 << 8); 1134 /* enable ENET store and forward mode */ 1135 writel(1 << 8, fep->hwp + FEC_X_WMRK); 1136 } 1137 1138 if (fep->bufdesc_ex) 1139 ecntl |= (1 << 4); 1140 1141 if (fep->quirks & FEC_QUIRK_DELAYED_CLKS_SUPPORT && 1142 fep->rgmii_txc_dly) 1143 ecntl |= FEC_ENET_TXC_DLY; 1144 if (fep->quirks & FEC_QUIRK_DELAYED_CLKS_SUPPORT && 1145 fep->rgmii_rxc_dly) 1146 ecntl |= FEC_ENET_RXC_DLY; 1147 1148 #ifndef CONFIG_M5272 1149 /* Enable the MIB statistic event counters */ 1150 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT); 1151 #endif 1152 1153 /* And last, enable the transmit and receive processing */ 1154 writel(ecntl, fep->hwp + FEC_ECNTRL); 1155 fec_enet_active_rxring(ndev); 1156 1157 if (fep->bufdesc_ex) 1158 fec_ptp_start_cyclecounter(ndev); 1159 1160 /* Enable interrupts we wish to service */ 1161 if (fep->link) 1162 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1163 else 1164 writel(0, fep->hwp + FEC_IMASK); 1165 1166 /* Init the interrupt coalescing */ 1167 fec_enet_itr_coal_init(ndev); 1168 1169 } 1170 1171 static void fec_enet_stop_mode(struct fec_enet_private *fep, bool enabled) 1172 { 1173 struct fec_platform_data *pdata = fep->pdev->dev.platform_data; 1174 struct fec_stop_mode_gpr *stop_gpr = &fep->stop_gpr; 1175 1176 if (stop_gpr->gpr) { 1177 if (enabled) 1178 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg, 1179 BIT(stop_gpr->bit), 1180 BIT(stop_gpr->bit)); 1181 else 1182 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg, 1183 BIT(stop_gpr->bit), 0); 1184 } else if (pdata && pdata->sleep_mode_enable) { 1185 pdata->sleep_mode_enable(enabled); 1186 } 1187 } 1188 1189 static void fec_irqs_disable(struct net_device *ndev) 1190 { 1191 struct fec_enet_private *fep = netdev_priv(ndev); 1192 1193 writel(0, fep->hwp + FEC_IMASK); 1194 } 1195 1196 static void fec_irqs_disable_except_wakeup(struct net_device *ndev) 1197 { 1198 struct fec_enet_private *fep = netdev_priv(ndev); 1199 1200 writel(0, fep->hwp + FEC_IMASK); 1201 writel(FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK); 1202 } 1203 1204 static void 1205 fec_stop(struct net_device *ndev) 1206 { 1207 struct fec_enet_private *fep = netdev_priv(ndev); 1208 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8); 1209 u32 val; 1210 1211 /* We cannot expect a graceful transmit stop without link !!! */ 1212 if (fep->link) { 1213 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ 1214 udelay(10); 1215 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) 1216 netdev_err(ndev, "Graceful transmit stop did not complete!\n"); 1217 } 1218 1219 /* Whack a reset. We should wait for this. 1220 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC 1221 * instead of reset MAC itself. 1222 */ 1223 if (!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1224 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) { 1225 writel(0, fep->hwp + FEC_ECNTRL); 1226 } else { 1227 writel(1, fep->hwp + FEC_ECNTRL); 1228 udelay(10); 1229 } 1230 } else { 1231 val = readl(fep->hwp + FEC_ECNTRL); 1232 val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP); 1233 writel(val, fep->hwp + FEC_ECNTRL); 1234 } 1235 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1236 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1237 1238 /* We have to keep ENET enabled to have MII interrupt stay working */ 1239 if (fep->quirks & FEC_QUIRK_ENET_MAC && 1240 !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1241 writel(2, fep->hwp + FEC_ECNTRL); 1242 writel(rmii_mode, fep->hwp + FEC_R_CNTRL); 1243 } 1244 } 1245 1246 1247 static void 1248 fec_timeout(struct net_device *ndev, unsigned int txqueue) 1249 { 1250 struct fec_enet_private *fep = netdev_priv(ndev); 1251 1252 fec_dump(ndev); 1253 1254 ndev->stats.tx_errors++; 1255 1256 schedule_work(&fep->tx_timeout_work); 1257 } 1258 1259 static void fec_enet_timeout_work(struct work_struct *work) 1260 { 1261 struct fec_enet_private *fep = 1262 container_of(work, struct fec_enet_private, tx_timeout_work); 1263 struct net_device *ndev = fep->netdev; 1264 1265 rtnl_lock(); 1266 if (netif_device_present(ndev) || netif_running(ndev)) { 1267 napi_disable(&fep->napi); 1268 netif_tx_lock_bh(ndev); 1269 fec_restart(ndev); 1270 netif_tx_wake_all_queues(ndev); 1271 netif_tx_unlock_bh(ndev); 1272 napi_enable(&fep->napi); 1273 } 1274 rtnl_unlock(); 1275 } 1276 1277 static void 1278 fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts, 1279 struct skb_shared_hwtstamps *hwtstamps) 1280 { 1281 unsigned long flags; 1282 u64 ns; 1283 1284 spin_lock_irqsave(&fep->tmreg_lock, flags); 1285 ns = timecounter_cyc2time(&fep->tc, ts); 1286 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 1287 1288 memset(hwtstamps, 0, sizeof(*hwtstamps)); 1289 hwtstamps->hwtstamp = ns_to_ktime(ns); 1290 } 1291 1292 static void 1293 fec_enet_tx_queue(struct net_device *ndev, u16 queue_id) 1294 { 1295 struct fec_enet_private *fep; 1296 struct bufdesc *bdp; 1297 unsigned short status; 1298 struct sk_buff *skb; 1299 struct fec_enet_priv_tx_q *txq; 1300 struct netdev_queue *nq; 1301 int index = 0; 1302 int entries_free; 1303 1304 fep = netdev_priv(ndev); 1305 1306 txq = fep->tx_queue[queue_id]; 1307 /* get next bdp of dirty_tx */ 1308 nq = netdev_get_tx_queue(ndev, queue_id); 1309 bdp = txq->dirty_tx; 1310 1311 /* get next bdp of dirty_tx */ 1312 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1313 1314 while (bdp != READ_ONCE(txq->bd.cur)) { 1315 /* Order the load of bd.cur and cbd_sc */ 1316 rmb(); 1317 status = fec16_to_cpu(READ_ONCE(bdp->cbd_sc)); 1318 if (status & BD_ENET_TX_READY) 1319 break; 1320 1321 index = fec_enet_get_bd_index(bdp, &txq->bd); 1322 1323 skb = txq->tx_skbuff[index]; 1324 txq->tx_skbuff[index] = NULL; 1325 if (!IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr))) 1326 dma_unmap_single(&fep->pdev->dev, 1327 fec32_to_cpu(bdp->cbd_bufaddr), 1328 fec16_to_cpu(bdp->cbd_datlen), 1329 DMA_TO_DEVICE); 1330 bdp->cbd_bufaddr = cpu_to_fec32(0); 1331 if (!skb) 1332 goto skb_done; 1333 1334 /* Check for errors. */ 1335 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | 1336 BD_ENET_TX_RL | BD_ENET_TX_UN | 1337 BD_ENET_TX_CSL)) { 1338 ndev->stats.tx_errors++; 1339 if (status & BD_ENET_TX_HB) /* No heartbeat */ 1340 ndev->stats.tx_heartbeat_errors++; 1341 if (status & BD_ENET_TX_LC) /* Late collision */ 1342 ndev->stats.tx_window_errors++; 1343 if (status & BD_ENET_TX_RL) /* Retrans limit */ 1344 ndev->stats.tx_aborted_errors++; 1345 if (status & BD_ENET_TX_UN) /* Underrun */ 1346 ndev->stats.tx_fifo_errors++; 1347 if (status & BD_ENET_TX_CSL) /* Carrier lost */ 1348 ndev->stats.tx_carrier_errors++; 1349 } else { 1350 ndev->stats.tx_packets++; 1351 ndev->stats.tx_bytes += skb->len; 1352 } 1353 1354 /* NOTE: SKBTX_IN_PROGRESS being set does not imply it's we who 1355 * are to time stamp the packet, so we still need to check time 1356 * stamping enabled flag. 1357 */ 1358 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS && 1359 fep->hwts_tx_en) && 1360 fep->bufdesc_ex) { 1361 struct skb_shared_hwtstamps shhwtstamps; 1362 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1363 1364 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), &shhwtstamps); 1365 skb_tstamp_tx(skb, &shhwtstamps); 1366 } 1367 1368 /* Deferred means some collisions occurred during transmit, 1369 * but we eventually sent the packet OK. 1370 */ 1371 if (status & BD_ENET_TX_DEF) 1372 ndev->stats.collisions++; 1373 1374 /* Free the sk buffer associated with this last transmit */ 1375 dev_kfree_skb_any(skb); 1376 skb_done: 1377 /* Make sure the update to bdp and tx_skbuff are performed 1378 * before dirty_tx 1379 */ 1380 wmb(); 1381 txq->dirty_tx = bdp; 1382 1383 /* Update pointer to next buffer descriptor to be transmitted */ 1384 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1385 1386 /* Since we have freed up a buffer, the ring is no longer full 1387 */ 1388 if (netif_tx_queue_stopped(nq)) { 1389 entries_free = fec_enet_get_free_txdesc_num(txq); 1390 if (entries_free >= txq->tx_wake_threshold) 1391 netif_tx_wake_queue(nq); 1392 } 1393 } 1394 1395 /* ERR006358: Keep the transmitter going */ 1396 if (bdp != txq->bd.cur && 1397 readl(txq->bd.reg_desc_active) == 0) 1398 writel(0, txq->bd.reg_desc_active); 1399 } 1400 1401 static void fec_enet_tx(struct net_device *ndev) 1402 { 1403 struct fec_enet_private *fep = netdev_priv(ndev); 1404 int i; 1405 1406 /* Make sure that AVB queues are processed first. */ 1407 for (i = fep->num_tx_queues - 1; i >= 0; i--) 1408 fec_enet_tx_queue(ndev, i); 1409 } 1410 1411 static int 1412 fec_enet_new_rxbdp(struct net_device *ndev, struct bufdesc *bdp, struct sk_buff *skb) 1413 { 1414 struct fec_enet_private *fep = netdev_priv(ndev); 1415 int off; 1416 1417 off = ((unsigned long)skb->data) & fep->rx_align; 1418 if (off) 1419 skb_reserve(skb, fep->rx_align + 1 - off); 1420 1421 bdp->cbd_bufaddr = cpu_to_fec32(dma_map_single(&fep->pdev->dev, skb->data, FEC_ENET_RX_FRSIZE - fep->rx_align, DMA_FROM_DEVICE)); 1422 if (dma_mapping_error(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr))) { 1423 if (net_ratelimit()) 1424 netdev_err(ndev, "Rx DMA memory map failed\n"); 1425 return -ENOMEM; 1426 } 1427 1428 return 0; 1429 } 1430 1431 static bool fec_enet_copybreak(struct net_device *ndev, struct sk_buff **skb, 1432 struct bufdesc *bdp, u32 length, bool swap) 1433 { 1434 struct fec_enet_private *fep = netdev_priv(ndev); 1435 struct sk_buff *new_skb; 1436 1437 if (length > fep->rx_copybreak) 1438 return false; 1439 1440 new_skb = netdev_alloc_skb(ndev, length); 1441 if (!new_skb) 1442 return false; 1443 1444 dma_sync_single_for_cpu(&fep->pdev->dev, 1445 fec32_to_cpu(bdp->cbd_bufaddr), 1446 FEC_ENET_RX_FRSIZE - fep->rx_align, 1447 DMA_FROM_DEVICE); 1448 if (!swap) 1449 memcpy(new_skb->data, (*skb)->data, length); 1450 else 1451 swap_buffer2(new_skb->data, (*skb)->data, length); 1452 *skb = new_skb; 1453 1454 return true; 1455 } 1456 1457 /* During a receive, the bd_rx.cur points to the current incoming buffer. 1458 * When we update through the ring, if the next incoming buffer has 1459 * not been given to the system, we just set the empty indicator, 1460 * effectively tossing the packet. 1461 */ 1462 static int 1463 fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id) 1464 { 1465 struct fec_enet_private *fep = netdev_priv(ndev); 1466 struct fec_enet_priv_rx_q *rxq; 1467 struct bufdesc *bdp; 1468 unsigned short status; 1469 struct sk_buff *skb_new = NULL; 1470 struct sk_buff *skb; 1471 ushort pkt_len; 1472 __u8 *data; 1473 int pkt_received = 0; 1474 struct bufdesc_ex *ebdp = NULL; 1475 bool vlan_packet_rcvd = false; 1476 u16 vlan_tag; 1477 int index = 0; 1478 bool is_copybreak; 1479 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME; 1480 1481 #ifdef CONFIG_M532x 1482 flush_cache_all(); 1483 #endif 1484 rxq = fep->rx_queue[queue_id]; 1485 1486 /* First, grab all of the stats for the incoming packet. 1487 * These get messed up if we get called due to a busy condition. 1488 */ 1489 bdp = rxq->bd.cur; 1490 1491 while (!((status = fec16_to_cpu(bdp->cbd_sc)) & BD_ENET_RX_EMPTY)) { 1492 1493 if (pkt_received >= budget) 1494 break; 1495 pkt_received++; 1496 1497 writel(FEC_ENET_RXF_GET(queue_id), fep->hwp + FEC_IEVENT); 1498 1499 /* Check for errors. */ 1500 status ^= BD_ENET_RX_LAST; 1501 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | 1502 BD_ENET_RX_CR | BD_ENET_RX_OV | BD_ENET_RX_LAST | 1503 BD_ENET_RX_CL)) { 1504 ndev->stats.rx_errors++; 1505 if (status & BD_ENET_RX_OV) { 1506 /* FIFO overrun */ 1507 ndev->stats.rx_fifo_errors++; 1508 goto rx_processing_done; 1509 } 1510 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH 1511 | BD_ENET_RX_LAST)) { 1512 /* Frame too long or too short. */ 1513 ndev->stats.rx_length_errors++; 1514 if (status & BD_ENET_RX_LAST) 1515 netdev_err(ndev, "rcv is not +last\n"); 1516 } 1517 if (status & BD_ENET_RX_CR) /* CRC Error */ 1518 ndev->stats.rx_crc_errors++; 1519 /* Report late collisions as a frame error. */ 1520 if (status & (BD_ENET_RX_NO | BD_ENET_RX_CL)) 1521 ndev->stats.rx_frame_errors++; 1522 goto rx_processing_done; 1523 } 1524 1525 /* Process the incoming frame. */ 1526 ndev->stats.rx_packets++; 1527 pkt_len = fec16_to_cpu(bdp->cbd_datlen); 1528 ndev->stats.rx_bytes += pkt_len; 1529 1530 index = fec_enet_get_bd_index(bdp, &rxq->bd); 1531 skb = rxq->rx_skbuff[index]; 1532 1533 /* The packet length includes FCS, but we don't want to 1534 * include that when passing upstream as it messes up 1535 * bridging applications. 1536 */ 1537 is_copybreak = fec_enet_copybreak(ndev, &skb, bdp, pkt_len - 4, 1538 need_swap); 1539 if (!is_copybreak) { 1540 skb_new = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE); 1541 if (unlikely(!skb_new)) { 1542 ndev->stats.rx_dropped++; 1543 goto rx_processing_done; 1544 } 1545 dma_unmap_single(&fep->pdev->dev, 1546 fec32_to_cpu(bdp->cbd_bufaddr), 1547 FEC_ENET_RX_FRSIZE - fep->rx_align, 1548 DMA_FROM_DEVICE); 1549 } 1550 1551 prefetch(skb->data - NET_IP_ALIGN); 1552 skb_put(skb, pkt_len - 4); 1553 data = skb->data; 1554 1555 if (!is_copybreak && need_swap) 1556 swap_buffer(data, pkt_len); 1557 1558 #if !defined(CONFIG_M5272) 1559 if (fep->quirks & FEC_QUIRK_HAS_RACC) 1560 data = skb_pull_inline(skb, 2); 1561 #endif 1562 1563 /* Extract the enhanced buffer descriptor */ 1564 ebdp = NULL; 1565 if (fep->bufdesc_ex) 1566 ebdp = (struct bufdesc_ex *)bdp; 1567 1568 /* If this is a VLAN packet remove the VLAN Tag */ 1569 vlan_packet_rcvd = false; 1570 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) && 1571 fep->bufdesc_ex && 1572 (ebdp->cbd_esc & cpu_to_fec32(BD_ENET_RX_VLAN))) { 1573 /* Push and remove the vlan tag */ 1574 struct vlan_hdr *vlan_header = 1575 (struct vlan_hdr *) (data + ETH_HLEN); 1576 vlan_tag = ntohs(vlan_header->h_vlan_TCI); 1577 1578 vlan_packet_rcvd = true; 1579 1580 memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2); 1581 skb_pull(skb, VLAN_HLEN); 1582 } 1583 1584 skb->protocol = eth_type_trans(skb, ndev); 1585 1586 /* Get receive timestamp from the skb */ 1587 if (fep->hwts_rx_en && fep->bufdesc_ex) 1588 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), 1589 skb_hwtstamps(skb)); 1590 1591 if (fep->bufdesc_ex && 1592 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) { 1593 if (!(ebdp->cbd_esc & cpu_to_fec32(FLAG_RX_CSUM_ERROR))) { 1594 /* don't check it */ 1595 skb->ip_summed = CHECKSUM_UNNECESSARY; 1596 } else { 1597 skb_checksum_none_assert(skb); 1598 } 1599 } 1600 1601 /* Handle received VLAN packets */ 1602 if (vlan_packet_rcvd) 1603 __vlan_hwaccel_put_tag(skb, 1604 htons(ETH_P_8021Q), 1605 vlan_tag); 1606 1607 skb_record_rx_queue(skb, queue_id); 1608 napi_gro_receive(&fep->napi, skb); 1609 1610 if (is_copybreak) { 1611 dma_sync_single_for_device(&fep->pdev->dev, 1612 fec32_to_cpu(bdp->cbd_bufaddr), 1613 FEC_ENET_RX_FRSIZE - fep->rx_align, 1614 DMA_FROM_DEVICE); 1615 } else { 1616 rxq->rx_skbuff[index] = skb_new; 1617 fec_enet_new_rxbdp(ndev, bdp, skb_new); 1618 } 1619 1620 rx_processing_done: 1621 /* Clear the status flags for this buffer */ 1622 status &= ~BD_ENET_RX_STATS; 1623 1624 /* Mark the buffer empty */ 1625 status |= BD_ENET_RX_EMPTY; 1626 1627 if (fep->bufdesc_ex) { 1628 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1629 1630 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); 1631 ebdp->cbd_prot = 0; 1632 ebdp->cbd_bdu = 0; 1633 } 1634 /* Make sure the updates to rest of the descriptor are 1635 * performed before transferring ownership. 1636 */ 1637 wmb(); 1638 bdp->cbd_sc = cpu_to_fec16(status); 1639 1640 /* Update BD pointer to next entry */ 1641 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 1642 1643 /* Doing this here will keep the FEC running while we process 1644 * incoming frames. On a heavily loaded network, we should be 1645 * able to keep up at the expense of system resources. 1646 */ 1647 writel(0, rxq->bd.reg_desc_active); 1648 } 1649 rxq->bd.cur = bdp; 1650 return pkt_received; 1651 } 1652 1653 static int fec_enet_rx(struct net_device *ndev, int budget) 1654 { 1655 struct fec_enet_private *fep = netdev_priv(ndev); 1656 int i, done = 0; 1657 1658 /* Make sure that AVB queues are processed first. */ 1659 for (i = fep->num_rx_queues - 1; i >= 0; i--) 1660 done += fec_enet_rx_queue(ndev, budget - done, i); 1661 1662 return done; 1663 } 1664 1665 static bool fec_enet_collect_events(struct fec_enet_private *fep) 1666 { 1667 uint int_events; 1668 1669 int_events = readl(fep->hwp + FEC_IEVENT); 1670 1671 /* Don't clear MDIO events, we poll for those */ 1672 int_events &= ~FEC_ENET_MII; 1673 1674 writel(int_events, fep->hwp + FEC_IEVENT); 1675 1676 return int_events != 0; 1677 } 1678 1679 static irqreturn_t 1680 fec_enet_interrupt(int irq, void *dev_id) 1681 { 1682 struct net_device *ndev = dev_id; 1683 struct fec_enet_private *fep = netdev_priv(ndev); 1684 irqreturn_t ret = IRQ_NONE; 1685 1686 if (fec_enet_collect_events(fep) && fep->link) { 1687 ret = IRQ_HANDLED; 1688 1689 if (napi_schedule_prep(&fep->napi)) { 1690 /* Disable interrupts */ 1691 writel(0, fep->hwp + FEC_IMASK); 1692 __napi_schedule(&fep->napi); 1693 } 1694 } 1695 1696 return ret; 1697 } 1698 1699 static int fec_enet_rx_napi(struct napi_struct *napi, int budget) 1700 { 1701 struct net_device *ndev = napi->dev; 1702 struct fec_enet_private *fep = netdev_priv(ndev); 1703 int done = 0; 1704 1705 do { 1706 done += fec_enet_rx(ndev, budget - done); 1707 fec_enet_tx(ndev); 1708 } while ((done < budget) && fec_enet_collect_events(fep)); 1709 1710 if (done < budget) { 1711 napi_complete_done(napi, done); 1712 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1713 } 1714 1715 return done; 1716 } 1717 1718 /* ------------------------------------------------------------------------- */ 1719 static int fec_get_mac(struct net_device *ndev) 1720 { 1721 struct fec_enet_private *fep = netdev_priv(ndev); 1722 unsigned char *iap, tmpaddr[ETH_ALEN]; 1723 int ret; 1724 1725 /* 1726 * try to get mac address in following order: 1727 * 1728 * 1) module parameter via kernel command line in form 1729 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0 1730 */ 1731 iap = macaddr; 1732 1733 /* 1734 * 2) from device tree data 1735 */ 1736 if (!is_valid_ether_addr(iap)) { 1737 struct device_node *np = fep->pdev->dev.of_node; 1738 if (np) { 1739 ret = of_get_mac_address(np, tmpaddr); 1740 if (!ret) 1741 iap = tmpaddr; 1742 else if (ret == -EPROBE_DEFER) 1743 return ret; 1744 } 1745 } 1746 1747 /* 1748 * 3) from flash or fuse (via platform data) 1749 */ 1750 if (!is_valid_ether_addr(iap)) { 1751 #ifdef CONFIG_M5272 1752 if (FEC_FLASHMAC) 1753 iap = (unsigned char *)FEC_FLASHMAC; 1754 #else 1755 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev); 1756 1757 if (pdata) 1758 iap = (unsigned char *)&pdata->mac; 1759 #endif 1760 } 1761 1762 /* 1763 * 4) FEC mac registers set by bootloader 1764 */ 1765 if (!is_valid_ether_addr(iap)) { 1766 *((__be32 *) &tmpaddr[0]) = 1767 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW)); 1768 *((__be16 *) &tmpaddr[4]) = 1769 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16); 1770 iap = &tmpaddr[0]; 1771 } 1772 1773 /* 1774 * 5) random mac address 1775 */ 1776 if (!is_valid_ether_addr(iap)) { 1777 /* Report it and use a random ethernet address instead */ 1778 dev_err(&fep->pdev->dev, "Invalid MAC address: %pM\n", iap); 1779 eth_hw_addr_random(ndev); 1780 dev_info(&fep->pdev->dev, "Using random MAC address: %pM\n", 1781 ndev->dev_addr); 1782 return 0; 1783 } 1784 1785 /* Adjust MAC if using macaddr */ 1786 eth_hw_addr_gen(ndev, iap, iap == macaddr ? fep->dev_id : 0); 1787 1788 return 0; 1789 } 1790 1791 /* ------------------------------------------------------------------------- */ 1792 1793 /* 1794 * Phy section 1795 */ 1796 static void fec_enet_adjust_link(struct net_device *ndev) 1797 { 1798 struct fec_enet_private *fep = netdev_priv(ndev); 1799 struct phy_device *phy_dev = ndev->phydev; 1800 int status_change = 0; 1801 1802 /* 1803 * If the netdev is down, or is going down, we're not interested 1804 * in link state events, so just mark our idea of the link as down 1805 * and ignore the event. 1806 */ 1807 if (!netif_running(ndev) || !netif_device_present(ndev)) { 1808 fep->link = 0; 1809 } else if (phy_dev->link) { 1810 if (!fep->link) { 1811 fep->link = phy_dev->link; 1812 status_change = 1; 1813 } 1814 1815 if (fep->full_duplex != phy_dev->duplex) { 1816 fep->full_duplex = phy_dev->duplex; 1817 status_change = 1; 1818 } 1819 1820 if (phy_dev->speed != fep->speed) { 1821 fep->speed = phy_dev->speed; 1822 status_change = 1; 1823 } 1824 1825 /* if any of the above changed restart the FEC */ 1826 if (status_change) { 1827 napi_disable(&fep->napi); 1828 netif_tx_lock_bh(ndev); 1829 fec_restart(ndev); 1830 netif_tx_wake_all_queues(ndev); 1831 netif_tx_unlock_bh(ndev); 1832 napi_enable(&fep->napi); 1833 } 1834 } else { 1835 if (fep->link) { 1836 napi_disable(&fep->napi); 1837 netif_tx_lock_bh(ndev); 1838 fec_stop(ndev); 1839 netif_tx_unlock_bh(ndev); 1840 napi_enable(&fep->napi); 1841 fep->link = phy_dev->link; 1842 status_change = 1; 1843 } 1844 } 1845 1846 if (status_change) 1847 phy_print_status(phy_dev); 1848 } 1849 1850 static int fec_enet_mdio_wait(struct fec_enet_private *fep) 1851 { 1852 uint ievent; 1853 int ret; 1854 1855 ret = readl_poll_timeout_atomic(fep->hwp + FEC_IEVENT, ievent, 1856 ievent & FEC_ENET_MII, 2, 30000); 1857 1858 if (!ret) 1859 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); 1860 1861 return ret; 1862 } 1863 1864 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) 1865 { 1866 struct fec_enet_private *fep = bus->priv; 1867 struct device *dev = &fep->pdev->dev; 1868 int ret = 0, frame_start, frame_addr, frame_op; 1869 bool is_c45 = !!(regnum & MII_ADDR_C45); 1870 1871 ret = pm_runtime_resume_and_get(dev); 1872 if (ret < 0) 1873 return ret; 1874 1875 if (is_c45) { 1876 frame_start = FEC_MMFR_ST_C45; 1877 1878 /* write address */ 1879 frame_addr = (regnum >> 16); 1880 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE | 1881 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 1882 FEC_MMFR_TA | (regnum & 0xFFFF), 1883 fep->hwp + FEC_MII_DATA); 1884 1885 /* wait for end of transfer */ 1886 ret = fec_enet_mdio_wait(fep); 1887 if (ret) { 1888 netdev_err(fep->netdev, "MDIO address write timeout\n"); 1889 goto out; 1890 } 1891 1892 frame_op = FEC_MMFR_OP_READ_C45; 1893 1894 } else { 1895 /* C22 read */ 1896 frame_op = FEC_MMFR_OP_READ; 1897 frame_start = FEC_MMFR_ST; 1898 frame_addr = regnum; 1899 } 1900 1901 /* start a read op */ 1902 writel(frame_start | frame_op | 1903 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 1904 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); 1905 1906 /* wait for end of transfer */ 1907 ret = fec_enet_mdio_wait(fep); 1908 if (ret) { 1909 netdev_err(fep->netdev, "MDIO read timeout\n"); 1910 goto out; 1911 } 1912 1913 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); 1914 1915 out: 1916 pm_runtime_mark_last_busy(dev); 1917 pm_runtime_put_autosuspend(dev); 1918 1919 return ret; 1920 } 1921 1922 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, 1923 u16 value) 1924 { 1925 struct fec_enet_private *fep = bus->priv; 1926 struct device *dev = &fep->pdev->dev; 1927 int ret, frame_start, frame_addr; 1928 bool is_c45 = !!(regnum & MII_ADDR_C45); 1929 1930 ret = pm_runtime_resume_and_get(dev); 1931 if (ret < 0) 1932 return ret; 1933 1934 if (is_c45) { 1935 frame_start = FEC_MMFR_ST_C45; 1936 1937 /* write address */ 1938 frame_addr = (regnum >> 16); 1939 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE | 1940 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 1941 FEC_MMFR_TA | (regnum & 0xFFFF), 1942 fep->hwp + FEC_MII_DATA); 1943 1944 /* wait for end of transfer */ 1945 ret = fec_enet_mdio_wait(fep); 1946 if (ret) { 1947 netdev_err(fep->netdev, "MDIO address write timeout\n"); 1948 goto out; 1949 } 1950 } else { 1951 /* C22 write */ 1952 frame_start = FEC_MMFR_ST; 1953 frame_addr = regnum; 1954 } 1955 1956 /* start a write op */ 1957 writel(frame_start | FEC_MMFR_OP_WRITE | 1958 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 1959 FEC_MMFR_TA | FEC_MMFR_DATA(value), 1960 fep->hwp + FEC_MII_DATA); 1961 1962 /* wait for end of transfer */ 1963 ret = fec_enet_mdio_wait(fep); 1964 if (ret) 1965 netdev_err(fep->netdev, "MDIO write timeout\n"); 1966 1967 out: 1968 pm_runtime_mark_last_busy(dev); 1969 pm_runtime_put_autosuspend(dev); 1970 1971 return ret; 1972 } 1973 1974 static void fec_enet_phy_reset_after_clk_enable(struct net_device *ndev) 1975 { 1976 struct fec_enet_private *fep = netdev_priv(ndev); 1977 struct phy_device *phy_dev = ndev->phydev; 1978 1979 if (phy_dev) { 1980 phy_reset_after_clk_enable(phy_dev); 1981 } else if (fep->phy_node) { 1982 /* 1983 * If the PHY still is not bound to the MAC, but there is 1984 * OF PHY node and a matching PHY device instance already, 1985 * use the OF PHY node to obtain the PHY device instance, 1986 * and then use that PHY device instance when triggering 1987 * the PHY reset. 1988 */ 1989 phy_dev = of_phy_find_device(fep->phy_node); 1990 phy_reset_after_clk_enable(phy_dev); 1991 put_device(&phy_dev->mdio.dev); 1992 } 1993 } 1994 1995 static int fec_enet_clk_enable(struct net_device *ndev, bool enable) 1996 { 1997 struct fec_enet_private *fep = netdev_priv(ndev); 1998 int ret; 1999 2000 if (enable) { 2001 ret = clk_prepare_enable(fep->clk_enet_out); 2002 if (ret) 2003 return ret; 2004 2005 if (fep->clk_ptp) { 2006 mutex_lock(&fep->ptp_clk_mutex); 2007 ret = clk_prepare_enable(fep->clk_ptp); 2008 if (ret) { 2009 mutex_unlock(&fep->ptp_clk_mutex); 2010 goto failed_clk_ptp; 2011 } else { 2012 fep->ptp_clk_on = true; 2013 } 2014 mutex_unlock(&fep->ptp_clk_mutex); 2015 } 2016 2017 ret = clk_prepare_enable(fep->clk_ref); 2018 if (ret) 2019 goto failed_clk_ref; 2020 2021 ret = clk_prepare_enable(fep->clk_2x_txclk); 2022 if (ret) 2023 goto failed_clk_2x_txclk; 2024 2025 fec_enet_phy_reset_after_clk_enable(ndev); 2026 } else { 2027 clk_disable_unprepare(fep->clk_enet_out); 2028 if (fep->clk_ptp) { 2029 mutex_lock(&fep->ptp_clk_mutex); 2030 clk_disable_unprepare(fep->clk_ptp); 2031 fep->ptp_clk_on = false; 2032 mutex_unlock(&fep->ptp_clk_mutex); 2033 } 2034 clk_disable_unprepare(fep->clk_ref); 2035 clk_disable_unprepare(fep->clk_2x_txclk); 2036 } 2037 2038 return 0; 2039 2040 failed_clk_2x_txclk: 2041 if (fep->clk_ref) 2042 clk_disable_unprepare(fep->clk_ref); 2043 failed_clk_ref: 2044 if (fep->clk_ptp) { 2045 mutex_lock(&fep->ptp_clk_mutex); 2046 clk_disable_unprepare(fep->clk_ptp); 2047 fep->ptp_clk_on = false; 2048 mutex_unlock(&fep->ptp_clk_mutex); 2049 } 2050 failed_clk_ptp: 2051 clk_disable_unprepare(fep->clk_enet_out); 2052 2053 return ret; 2054 } 2055 2056 static int fec_enet_parse_rgmii_delay(struct fec_enet_private *fep, 2057 struct device_node *np) 2058 { 2059 u32 rgmii_tx_delay, rgmii_rx_delay; 2060 2061 /* For rgmii tx internal delay, valid values are 0ps and 2000ps */ 2062 if (!of_property_read_u32(np, "tx-internal-delay-ps", &rgmii_tx_delay)) { 2063 if (rgmii_tx_delay != 0 && rgmii_tx_delay != 2000) { 2064 dev_err(&fep->pdev->dev, "The only allowed RGMII TX delay values are: 0ps, 2000ps"); 2065 return -EINVAL; 2066 } else if (rgmii_tx_delay == 2000) { 2067 fep->rgmii_txc_dly = true; 2068 } 2069 } 2070 2071 /* For rgmii rx internal delay, valid values are 0ps and 2000ps */ 2072 if (!of_property_read_u32(np, "rx-internal-delay-ps", &rgmii_rx_delay)) { 2073 if (rgmii_rx_delay != 0 && rgmii_rx_delay != 2000) { 2074 dev_err(&fep->pdev->dev, "The only allowed RGMII RX delay values are: 0ps, 2000ps"); 2075 return -EINVAL; 2076 } else if (rgmii_rx_delay == 2000) { 2077 fep->rgmii_rxc_dly = true; 2078 } 2079 } 2080 2081 return 0; 2082 } 2083 2084 static int fec_enet_mii_probe(struct net_device *ndev) 2085 { 2086 struct fec_enet_private *fep = netdev_priv(ndev); 2087 struct phy_device *phy_dev = NULL; 2088 char mdio_bus_id[MII_BUS_ID_SIZE]; 2089 char phy_name[MII_BUS_ID_SIZE + 3]; 2090 int phy_id; 2091 int dev_id = fep->dev_id; 2092 2093 if (fep->phy_node) { 2094 phy_dev = of_phy_connect(ndev, fep->phy_node, 2095 &fec_enet_adjust_link, 0, 2096 fep->phy_interface); 2097 if (!phy_dev) { 2098 netdev_err(ndev, "Unable to connect to phy\n"); 2099 return -ENODEV; 2100 } 2101 } else { 2102 /* check for attached phy */ 2103 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) { 2104 if (!mdiobus_is_registered_device(fep->mii_bus, phy_id)) 2105 continue; 2106 if (dev_id--) 2107 continue; 2108 strlcpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE); 2109 break; 2110 } 2111 2112 if (phy_id >= PHY_MAX_ADDR) { 2113 netdev_info(ndev, "no PHY, assuming direct connection to switch\n"); 2114 strlcpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); 2115 phy_id = 0; 2116 } 2117 2118 snprintf(phy_name, sizeof(phy_name), 2119 PHY_ID_FMT, mdio_bus_id, phy_id); 2120 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, 2121 fep->phy_interface); 2122 } 2123 2124 if (IS_ERR(phy_dev)) { 2125 netdev_err(ndev, "could not attach to PHY\n"); 2126 return PTR_ERR(phy_dev); 2127 } 2128 2129 /* mask with MAC supported features */ 2130 if (fep->quirks & FEC_QUIRK_HAS_GBIT) { 2131 phy_set_max_speed(phy_dev, 1000); 2132 phy_remove_link_mode(phy_dev, 2133 ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 2134 #if !defined(CONFIG_M5272) 2135 phy_support_sym_pause(phy_dev); 2136 #endif 2137 } 2138 else 2139 phy_set_max_speed(phy_dev, 100); 2140 2141 fep->link = 0; 2142 fep->full_duplex = 0; 2143 2144 phy_dev->mac_managed_pm = 1; 2145 2146 phy_attached_info(phy_dev); 2147 2148 return 0; 2149 } 2150 2151 static int fec_enet_mii_init(struct platform_device *pdev) 2152 { 2153 static struct mii_bus *fec0_mii_bus; 2154 struct net_device *ndev = platform_get_drvdata(pdev); 2155 struct fec_enet_private *fep = netdev_priv(ndev); 2156 bool suppress_preamble = false; 2157 struct device_node *node; 2158 int err = -ENXIO; 2159 u32 mii_speed, holdtime; 2160 u32 bus_freq; 2161 2162 /* 2163 * The i.MX28 dual fec interfaces are not equal. 2164 * Here are the differences: 2165 * 2166 * - fec0 supports MII & RMII modes while fec1 only supports RMII 2167 * - fec0 acts as the 1588 time master while fec1 is slave 2168 * - external phys can only be configured by fec0 2169 * 2170 * That is to say fec1 can not work independently. It only works 2171 * when fec0 is working. The reason behind this design is that the 2172 * second interface is added primarily for Switch mode. 2173 * 2174 * Because of the last point above, both phys are attached on fec0 2175 * mdio interface in board design, and need to be configured by 2176 * fec0 mii_bus. 2177 */ 2178 if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) { 2179 /* fec1 uses fec0 mii_bus */ 2180 if (mii_cnt && fec0_mii_bus) { 2181 fep->mii_bus = fec0_mii_bus; 2182 mii_cnt++; 2183 return 0; 2184 } 2185 return -ENOENT; 2186 } 2187 2188 bus_freq = 2500000; /* 2.5MHz by default */ 2189 node = of_get_child_by_name(pdev->dev.of_node, "mdio"); 2190 if (node) { 2191 of_property_read_u32(node, "clock-frequency", &bus_freq); 2192 suppress_preamble = of_property_read_bool(node, 2193 "suppress-preamble"); 2194 } 2195 2196 /* 2197 * Set MII speed (= clk_get_rate() / 2 * phy_speed) 2198 * 2199 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while 2200 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28 2201 * Reference Manual has an error on this, and gets fixed on i.MX6Q 2202 * document. 2203 */ 2204 mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), bus_freq * 2); 2205 if (fep->quirks & FEC_QUIRK_ENET_MAC) 2206 mii_speed--; 2207 if (mii_speed > 63) { 2208 dev_err(&pdev->dev, 2209 "fec clock (%lu) too fast to get right mii speed\n", 2210 clk_get_rate(fep->clk_ipg)); 2211 err = -EINVAL; 2212 goto err_out; 2213 } 2214 2215 /* 2216 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka 2217 * MII_SPEED) register that defines the MDIO output hold time. Earlier 2218 * versions are RAZ there, so just ignore the difference and write the 2219 * register always. 2220 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns. 2221 * HOLDTIME + 1 is the number of clk cycles the fec is holding the 2222 * output. 2223 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive). 2224 * Given that ceil(clkrate / 5000000) <= 64, the calculation for 2225 * holdtime cannot result in a value greater than 3. 2226 */ 2227 holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1; 2228 2229 fep->phy_speed = mii_speed << 1 | holdtime << 8; 2230 2231 if (suppress_preamble) 2232 fep->phy_speed |= BIT(7); 2233 2234 if (fep->quirks & FEC_QUIRK_CLEAR_SETUP_MII) { 2235 /* Clear MMFR to avoid to generate MII event by writing MSCR. 2236 * MII event generation condition: 2237 * - writing MSCR: 2238 * - mmfr[31:0]_not_zero & mscr[7:0]_is_zero & 2239 * mscr_reg_data_in[7:0] != 0 2240 * - writing MMFR: 2241 * - mscr[7:0]_not_zero 2242 */ 2243 writel(0, fep->hwp + FEC_MII_DATA); 2244 } 2245 2246 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 2247 2248 /* Clear any pending transaction complete indication */ 2249 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); 2250 2251 fep->mii_bus = mdiobus_alloc(); 2252 if (fep->mii_bus == NULL) { 2253 err = -ENOMEM; 2254 goto err_out; 2255 } 2256 2257 fep->mii_bus->name = "fec_enet_mii_bus"; 2258 fep->mii_bus->read = fec_enet_mdio_read; 2259 fep->mii_bus->write = fec_enet_mdio_write; 2260 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 2261 pdev->name, fep->dev_id + 1); 2262 fep->mii_bus->priv = fep; 2263 fep->mii_bus->parent = &pdev->dev; 2264 2265 err = of_mdiobus_register(fep->mii_bus, node); 2266 if (err) 2267 goto err_out_free_mdiobus; 2268 of_node_put(node); 2269 2270 mii_cnt++; 2271 2272 /* save fec0 mii_bus */ 2273 if (fep->quirks & FEC_QUIRK_SINGLE_MDIO) 2274 fec0_mii_bus = fep->mii_bus; 2275 2276 return 0; 2277 2278 err_out_free_mdiobus: 2279 mdiobus_free(fep->mii_bus); 2280 err_out: 2281 of_node_put(node); 2282 return err; 2283 } 2284 2285 static void fec_enet_mii_remove(struct fec_enet_private *fep) 2286 { 2287 if (--mii_cnt == 0) { 2288 mdiobus_unregister(fep->mii_bus); 2289 mdiobus_free(fep->mii_bus); 2290 } 2291 } 2292 2293 static void fec_enet_get_drvinfo(struct net_device *ndev, 2294 struct ethtool_drvinfo *info) 2295 { 2296 struct fec_enet_private *fep = netdev_priv(ndev); 2297 2298 strlcpy(info->driver, fep->pdev->dev.driver->name, 2299 sizeof(info->driver)); 2300 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info)); 2301 } 2302 2303 static int fec_enet_get_regs_len(struct net_device *ndev) 2304 { 2305 struct fec_enet_private *fep = netdev_priv(ndev); 2306 struct resource *r; 2307 int s = 0; 2308 2309 r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0); 2310 if (r) 2311 s = resource_size(r); 2312 2313 return s; 2314 } 2315 2316 /* List of registers that can be safety be read to dump them with ethtool */ 2317 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 2318 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \ 2319 defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST) 2320 static __u32 fec_enet_register_version = 2; 2321 static u32 fec_enet_register_offset[] = { 2322 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0, 2323 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL, 2324 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1, 2325 FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH, 2326 FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, 2327 FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1, 2328 FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2, 2329 FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0, 2330 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM, 2331 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2, 2332 FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1, 2333 FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME, 2334 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT, 2335 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG, 2336 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255, 2337 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047, 2338 RMON_T_P_GTE2048, RMON_T_OCTETS, 2339 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF, 2340 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE, 2341 IEEE_T_FDXFC, IEEE_T_OCTETS_OK, 2342 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN, 2343 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB, 2344 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255, 2345 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047, 2346 RMON_R_P_GTE2048, RMON_R_OCTETS, 2347 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR, 2348 IEEE_R_FDXFC, IEEE_R_OCTETS_OK 2349 }; 2350 #else 2351 static __u32 fec_enet_register_version = 1; 2352 static u32 fec_enet_register_offset[] = { 2353 FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0, 2354 FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0, 2355 FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED, 2356 FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL, 2357 FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, 2358 FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0, 2359 FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0, 2360 FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0, 2361 FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2 2362 }; 2363 #endif 2364 2365 static void fec_enet_get_regs(struct net_device *ndev, 2366 struct ethtool_regs *regs, void *regbuf) 2367 { 2368 struct fec_enet_private *fep = netdev_priv(ndev); 2369 u32 __iomem *theregs = (u32 __iomem *)fep->hwp; 2370 struct device *dev = &fep->pdev->dev; 2371 u32 *buf = (u32 *)regbuf; 2372 u32 i, off; 2373 int ret; 2374 2375 ret = pm_runtime_resume_and_get(dev); 2376 if (ret < 0) 2377 return; 2378 2379 regs->version = fec_enet_register_version; 2380 2381 memset(buf, 0, regs->len); 2382 2383 for (i = 0; i < ARRAY_SIZE(fec_enet_register_offset); i++) { 2384 off = fec_enet_register_offset[i]; 2385 2386 if ((off == FEC_R_BOUND || off == FEC_R_FSTART) && 2387 !(fep->quirks & FEC_QUIRK_HAS_FRREG)) 2388 continue; 2389 2390 off >>= 2; 2391 buf[off] = readl(&theregs[off]); 2392 } 2393 2394 pm_runtime_mark_last_busy(dev); 2395 pm_runtime_put_autosuspend(dev); 2396 } 2397 2398 static int fec_enet_get_ts_info(struct net_device *ndev, 2399 struct ethtool_ts_info *info) 2400 { 2401 struct fec_enet_private *fep = netdev_priv(ndev); 2402 2403 if (fep->bufdesc_ex) { 2404 2405 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 2406 SOF_TIMESTAMPING_RX_SOFTWARE | 2407 SOF_TIMESTAMPING_SOFTWARE | 2408 SOF_TIMESTAMPING_TX_HARDWARE | 2409 SOF_TIMESTAMPING_RX_HARDWARE | 2410 SOF_TIMESTAMPING_RAW_HARDWARE; 2411 if (fep->ptp_clock) 2412 info->phc_index = ptp_clock_index(fep->ptp_clock); 2413 else 2414 info->phc_index = -1; 2415 2416 info->tx_types = (1 << HWTSTAMP_TX_OFF) | 2417 (1 << HWTSTAMP_TX_ON); 2418 2419 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 2420 (1 << HWTSTAMP_FILTER_ALL); 2421 return 0; 2422 } else { 2423 return ethtool_op_get_ts_info(ndev, info); 2424 } 2425 } 2426 2427 #if !defined(CONFIG_M5272) 2428 2429 static void fec_enet_get_pauseparam(struct net_device *ndev, 2430 struct ethtool_pauseparam *pause) 2431 { 2432 struct fec_enet_private *fep = netdev_priv(ndev); 2433 2434 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0; 2435 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0; 2436 pause->rx_pause = pause->tx_pause; 2437 } 2438 2439 static int fec_enet_set_pauseparam(struct net_device *ndev, 2440 struct ethtool_pauseparam *pause) 2441 { 2442 struct fec_enet_private *fep = netdev_priv(ndev); 2443 2444 if (!ndev->phydev) 2445 return -ENODEV; 2446 2447 if (pause->tx_pause != pause->rx_pause) { 2448 netdev_info(ndev, 2449 "hardware only support enable/disable both tx and rx"); 2450 return -EINVAL; 2451 } 2452 2453 fep->pause_flag = 0; 2454 2455 /* tx pause must be same as rx pause */ 2456 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0; 2457 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0; 2458 2459 phy_set_sym_pause(ndev->phydev, pause->rx_pause, pause->tx_pause, 2460 pause->autoneg); 2461 2462 if (pause->autoneg) { 2463 if (netif_running(ndev)) 2464 fec_stop(ndev); 2465 phy_start_aneg(ndev->phydev); 2466 } 2467 if (netif_running(ndev)) { 2468 napi_disable(&fep->napi); 2469 netif_tx_lock_bh(ndev); 2470 fec_restart(ndev); 2471 netif_tx_wake_all_queues(ndev); 2472 netif_tx_unlock_bh(ndev); 2473 napi_enable(&fep->napi); 2474 } 2475 2476 return 0; 2477 } 2478 2479 static const struct fec_stat { 2480 char name[ETH_GSTRING_LEN]; 2481 u16 offset; 2482 } fec_stats[] = { 2483 /* RMON TX */ 2484 { "tx_dropped", RMON_T_DROP }, 2485 { "tx_packets", RMON_T_PACKETS }, 2486 { "tx_broadcast", RMON_T_BC_PKT }, 2487 { "tx_multicast", RMON_T_MC_PKT }, 2488 { "tx_crc_errors", RMON_T_CRC_ALIGN }, 2489 { "tx_undersize", RMON_T_UNDERSIZE }, 2490 { "tx_oversize", RMON_T_OVERSIZE }, 2491 { "tx_fragment", RMON_T_FRAG }, 2492 { "tx_jabber", RMON_T_JAB }, 2493 { "tx_collision", RMON_T_COL }, 2494 { "tx_64byte", RMON_T_P64 }, 2495 { "tx_65to127byte", RMON_T_P65TO127 }, 2496 { "tx_128to255byte", RMON_T_P128TO255 }, 2497 { "tx_256to511byte", RMON_T_P256TO511 }, 2498 { "tx_512to1023byte", RMON_T_P512TO1023 }, 2499 { "tx_1024to2047byte", RMON_T_P1024TO2047 }, 2500 { "tx_GTE2048byte", RMON_T_P_GTE2048 }, 2501 { "tx_octets", RMON_T_OCTETS }, 2502 2503 /* IEEE TX */ 2504 { "IEEE_tx_drop", IEEE_T_DROP }, 2505 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK }, 2506 { "IEEE_tx_1col", IEEE_T_1COL }, 2507 { "IEEE_tx_mcol", IEEE_T_MCOL }, 2508 { "IEEE_tx_def", IEEE_T_DEF }, 2509 { "IEEE_tx_lcol", IEEE_T_LCOL }, 2510 { "IEEE_tx_excol", IEEE_T_EXCOL }, 2511 { "IEEE_tx_macerr", IEEE_T_MACERR }, 2512 { "IEEE_tx_cserr", IEEE_T_CSERR }, 2513 { "IEEE_tx_sqe", IEEE_T_SQE }, 2514 { "IEEE_tx_fdxfc", IEEE_T_FDXFC }, 2515 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK }, 2516 2517 /* RMON RX */ 2518 { "rx_packets", RMON_R_PACKETS }, 2519 { "rx_broadcast", RMON_R_BC_PKT }, 2520 { "rx_multicast", RMON_R_MC_PKT }, 2521 { "rx_crc_errors", RMON_R_CRC_ALIGN }, 2522 { "rx_undersize", RMON_R_UNDERSIZE }, 2523 { "rx_oversize", RMON_R_OVERSIZE }, 2524 { "rx_fragment", RMON_R_FRAG }, 2525 { "rx_jabber", RMON_R_JAB }, 2526 { "rx_64byte", RMON_R_P64 }, 2527 { "rx_65to127byte", RMON_R_P65TO127 }, 2528 { "rx_128to255byte", RMON_R_P128TO255 }, 2529 { "rx_256to511byte", RMON_R_P256TO511 }, 2530 { "rx_512to1023byte", RMON_R_P512TO1023 }, 2531 { "rx_1024to2047byte", RMON_R_P1024TO2047 }, 2532 { "rx_GTE2048byte", RMON_R_P_GTE2048 }, 2533 { "rx_octets", RMON_R_OCTETS }, 2534 2535 /* IEEE RX */ 2536 { "IEEE_rx_drop", IEEE_R_DROP }, 2537 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK }, 2538 { "IEEE_rx_crc", IEEE_R_CRC }, 2539 { "IEEE_rx_align", IEEE_R_ALIGN }, 2540 { "IEEE_rx_macerr", IEEE_R_MACERR }, 2541 { "IEEE_rx_fdxfc", IEEE_R_FDXFC }, 2542 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK }, 2543 }; 2544 2545 #define FEC_STATS_SIZE (ARRAY_SIZE(fec_stats) * sizeof(u64)) 2546 2547 static void fec_enet_update_ethtool_stats(struct net_device *dev) 2548 { 2549 struct fec_enet_private *fep = netdev_priv(dev); 2550 int i; 2551 2552 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2553 fep->ethtool_stats[i] = readl(fep->hwp + fec_stats[i].offset); 2554 } 2555 2556 static void fec_enet_get_ethtool_stats(struct net_device *dev, 2557 struct ethtool_stats *stats, u64 *data) 2558 { 2559 struct fec_enet_private *fep = netdev_priv(dev); 2560 2561 if (netif_running(dev)) 2562 fec_enet_update_ethtool_stats(dev); 2563 2564 memcpy(data, fep->ethtool_stats, FEC_STATS_SIZE); 2565 } 2566 2567 static void fec_enet_get_strings(struct net_device *netdev, 2568 u32 stringset, u8 *data) 2569 { 2570 int i; 2571 switch (stringset) { 2572 case ETH_SS_STATS: 2573 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2574 memcpy(data + i * ETH_GSTRING_LEN, 2575 fec_stats[i].name, ETH_GSTRING_LEN); 2576 break; 2577 case ETH_SS_TEST: 2578 net_selftest_get_strings(data); 2579 break; 2580 } 2581 } 2582 2583 static int fec_enet_get_sset_count(struct net_device *dev, int sset) 2584 { 2585 switch (sset) { 2586 case ETH_SS_STATS: 2587 return ARRAY_SIZE(fec_stats); 2588 case ETH_SS_TEST: 2589 return net_selftest_get_count(); 2590 default: 2591 return -EOPNOTSUPP; 2592 } 2593 } 2594 2595 static void fec_enet_clear_ethtool_stats(struct net_device *dev) 2596 { 2597 struct fec_enet_private *fep = netdev_priv(dev); 2598 int i; 2599 2600 /* Disable MIB statistics counters */ 2601 writel(FEC_MIB_CTRLSTAT_DISABLE, fep->hwp + FEC_MIB_CTRLSTAT); 2602 2603 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2604 writel(0, fep->hwp + fec_stats[i].offset); 2605 2606 /* Don't disable MIB statistics counters */ 2607 writel(0, fep->hwp + FEC_MIB_CTRLSTAT); 2608 } 2609 2610 #else /* !defined(CONFIG_M5272) */ 2611 #define FEC_STATS_SIZE 0 2612 static inline void fec_enet_update_ethtool_stats(struct net_device *dev) 2613 { 2614 } 2615 2616 static inline void fec_enet_clear_ethtool_stats(struct net_device *dev) 2617 { 2618 } 2619 #endif /* !defined(CONFIG_M5272) */ 2620 2621 /* ITR clock source is enet system clock (clk_ahb). 2622 * TCTT unit is cycle_ns * 64 cycle 2623 * So, the ICTT value = X us / (cycle_ns * 64) 2624 */ 2625 static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us) 2626 { 2627 struct fec_enet_private *fep = netdev_priv(ndev); 2628 2629 return us * (fep->itr_clk_rate / 64000) / 1000; 2630 } 2631 2632 /* Set threshold for interrupt coalescing */ 2633 static void fec_enet_itr_coal_set(struct net_device *ndev) 2634 { 2635 struct fec_enet_private *fep = netdev_priv(ndev); 2636 int rx_itr, tx_itr; 2637 2638 /* Must be greater than zero to avoid unpredictable behavior */ 2639 if (!fep->rx_time_itr || !fep->rx_pkts_itr || 2640 !fep->tx_time_itr || !fep->tx_pkts_itr) 2641 return; 2642 2643 /* Select enet system clock as Interrupt Coalescing 2644 * timer Clock Source 2645 */ 2646 rx_itr = FEC_ITR_CLK_SEL; 2647 tx_itr = FEC_ITR_CLK_SEL; 2648 2649 /* set ICFT and ICTT */ 2650 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr); 2651 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr)); 2652 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr); 2653 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr)); 2654 2655 rx_itr |= FEC_ITR_EN; 2656 tx_itr |= FEC_ITR_EN; 2657 2658 writel(tx_itr, fep->hwp + FEC_TXIC0); 2659 writel(rx_itr, fep->hwp + FEC_RXIC0); 2660 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) { 2661 writel(tx_itr, fep->hwp + FEC_TXIC1); 2662 writel(rx_itr, fep->hwp + FEC_RXIC1); 2663 writel(tx_itr, fep->hwp + FEC_TXIC2); 2664 writel(rx_itr, fep->hwp + FEC_RXIC2); 2665 } 2666 } 2667 2668 static int fec_enet_get_coalesce(struct net_device *ndev, 2669 struct ethtool_coalesce *ec, 2670 struct kernel_ethtool_coalesce *kernel_coal, 2671 struct netlink_ext_ack *extack) 2672 { 2673 struct fec_enet_private *fep = netdev_priv(ndev); 2674 2675 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) 2676 return -EOPNOTSUPP; 2677 2678 ec->rx_coalesce_usecs = fep->rx_time_itr; 2679 ec->rx_max_coalesced_frames = fep->rx_pkts_itr; 2680 2681 ec->tx_coalesce_usecs = fep->tx_time_itr; 2682 ec->tx_max_coalesced_frames = fep->tx_pkts_itr; 2683 2684 return 0; 2685 } 2686 2687 static int fec_enet_set_coalesce(struct net_device *ndev, 2688 struct ethtool_coalesce *ec, 2689 struct kernel_ethtool_coalesce *kernel_coal, 2690 struct netlink_ext_ack *extack) 2691 { 2692 struct fec_enet_private *fep = netdev_priv(ndev); 2693 struct device *dev = &fep->pdev->dev; 2694 unsigned int cycle; 2695 2696 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) 2697 return -EOPNOTSUPP; 2698 2699 if (ec->rx_max_coalesced_frames > 255) { 2700 dev_err(dev, "Rx coalesced frames exceed hardware limitation\n"); 2701 return -EINVAL; 2702 } 2703 2704 if (ec->tx_max_coalesced_frames > 255) { 2705 dev_err(dev, "Tx coalesced frame exceed hardware limitation\n"); 2706 return -EINVAL; 2707 } 2708 2709 cycle = fec_enet_us_to_itr_clock(ndev, ec->rx_coalesce_usecs); 2710 if (cycle > 0xFFFF) { 2711 dev_err(dev, "Rx coalesced usec exceed hardware limitation\n"); 2712 return -EINVAL; 2713 } 2714 2715 cycle = fec_enet_us_to_itr_clock(ndev, ec->tx_coalesce_usecs); 2716 if (cycle > 0xFFFF) { 2717 dev_err(dev, "Tx coalesced usec exceed hardware limitation\n"); 2718 return -EINVAL; 2719 } 2720 2721 fep->rx_time_itr = ec->rx_coalesce_usecs; 2722 fep->rx_pkts_itr = ec->rx_max_coalesced_frames; 2723 2724 fep->tx_time_itr = ec->tx_coalesce_usecs; 2725 fep->tx_pkts_itr = ec->tx_max_coalesced_frames; 2726 2727 fec_enet_itr_coal_set(ndev); 2728 2729 return 0; 2730 } 2731 2732 static void fec_enet_itr_coal_init(struct net_device *ndev) 2733 { 2734 struct ethtool_coalesce ec; 2735 2736 ec.rx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT; 2737 ec.rx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT; 2738 2739 ec.tx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT; 2740 ec.tx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT; 2741 2742 fec_enet_set_coalesce(ndev, &ec, NULL, NULL); 2743 } 2744 2745 static int fec_enet_get_tunable(struct net_device *netdev, 2746 const struct ethtool_tunable *tuna, 2747 void *data) 2748 { 2749 struct fec_enet_private *fep = netdev_priv(netdev); 2750 int ret = 0; 2751 2752 switch (tuna->id) { 2753 case ETHTOOL_RX_COPYBREAK: 2754 *(u32 *)data = fep->rx_copybreak; 2755 break; 2756 default: 2757 ret = -EINVAL; 2758 break; 2759 } 2760 2761 return ret; 2762 } 2763 2764 static int fec_enet_set_tunable(struct net_device *netdev, 2765 const struct ethtool_tunable *tuna, 2766 const void *data) 2767 { 2768 struct fec_enet_private *fep = netdev_priv(netdev); 2769 int ret = 0; 2770 2771 switch (tuna->id) { 2772 case ETHTOOL_RX_COPYBREAK: 2773 fep->rx_copybreak = *(u32 *)data; 2774 break; 2775 default: 2776 ret = -EINVAL; 2777 break; 2778 } 2779 2780 return ret; 2781 } 2782 2783 /* LPI Sleep Ts count base on tx clk (clk_ref). 2784 * The lpi sleep cnt value = X us / (cycle_ns). 2785 */ 2786 static int fec_enet_us_to_tx_cycle(struct net_device *ndev, int us) 2787 { 2788 struct fec_enet_private *fep = netdev_priv(ndev); 2789 2790 return us * (fep->clk_ref_rate / 1000) / 1000; 2791 } 2792 2793 static int fec_enet_eee_mode_set(struct net_device *ndev, bool enable) 2794 { 2795 struct fec_enet_private *fep = netdev_priv(ndev); 2796 struct ethtool_eee *p = &fep->eee; 2797 unsigned int sleep_cycle, wake_cycle; 2798 int ret = 0; 2799 2800 if (enable) { 2801 ret = phy_init_eee(ndev->phydev, false); 2802 if (ret) 2803 return ret; 2804 2805 sleep_cycle = fec_enet_us_to_tx_cycle(ndev, p->tx_lpi_timer); 2806 wake_cycle = sleep_cycle; 2807 } else { 2808 sleep_cycle = 0; 2809 wake_cycle = 0; 2810 } 2811 2812 p->tx_lpi_enabled = enable; 2813 p->eee_enabled = enable; 2814 p->eee_active = enable; 2815 2816 writel(sleep_cycle, fep->hwp + FEC_LPI_SLEEP); 2817 writel(wake_cycle, fep->hwp + FEC_LPI_WAKE); 2818 2819 return 0; 2820 } 2821 2822 static int 2823 fec_enet_get_eee(struct net_device *ndev, struct ethtool_eee *edata) 2824 { 2825 struct fec_enet_private *fep = netdev_priv(ndev); 2826 struct ethtool_eee *p = &fep->eee; 2827 2828 if (!(fep->quirks & FEC_QUIRK_HAS_EEE)) 2829 return -EOPNOTSUPP; 2830 2831 if (!netif_running(ndev)) 2832 return -ENETDOWN; 2833 2834 edata->eee_enabled = p->eee_enabled; 2835 edata->eee_active = p->eee_active; 2836 edata->tx_lpi_timer = p->tx_lpi_timer; 2837 edata->tx_lpi_enabled = p->tx_lpi_enabled; 2838 2839 return phy_ethtool_get_eee(ndev->phydev, edata); 2840 } 2841 2842 static int 2843 fec_enet_set_eee(struct net_device *ndev, struct ethtool_eee *edata) 2844 { 2845 struct fec_enet_private *fep = netdev_priv(ndev); 2846 struct ethtool_eee *p = &fep->eee; 2847 int ret = 0; 2848 2849 if (!(fep->quirks & FEC_QUIRK_HAS_EEE)) 2850 return -EOPNOTSUPP; 2851 2852 if (!netif_running(ndev)) 2853 return -ENETDOWN; 2854 2855 p->tx_lpi_timer = edata->tx_lpi_timer; 2856 2857 if (!edata->eee_enabled || !edata->tx_lpi_enabled || 2858 !edata->tx_lpi_timer) 2859 ret = fec_enet_eee_mode_set(ndev, false); 2860 else 2861 ret = fec_enet_eee_mode_set(ndev, true); 2862 2863 if (ret) 2864 return ret; 2865 2866 return phy_ethtool_set_eee(ndev->phydev, edata); 2867 } 2868 2869 static void 2870 fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2871 { 2872 struct fec_enet_private *fep = netdev_priv(ndev); 2873 2874 if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) { 2875 wol->supported = WAKE_MAGIC; 2876 wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0; 2877 } else { 2878 wol->supported = wol->wolopts = 0; 2879 } 2880 } 2881 2882 static int 2883 fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2884 { 2885 struct fec_enet_private *fep = netdev_priv(ndev); 2886 2887 if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET)) 2888 return -EINVAL; 2889 2890 if (wol->wolopts & ~WAKE_MAGIC) 2891 return -EINVAL; 2892 2893 device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC); 2894 if (device_may_wakeup(&ndev->dev)) 2895 fep->wol_flag |= FEC_WOL_FLAG_ENABLE; 2896 else 2897 fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE); 2898 2899 return 0; 2900 } 2901 2902 static const struct ethtool_ops fec_enet_ethtool_ops = { 2903 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 2904 ETHTOOL_COALESCE_MAX_FRAMES, 2905 .get_drvinfo = fec_enet_get_drvinfo, 2906 .get_regs_len = fec_enet_get_regs_len, 2907 .get_regs = fec_enet_get_regs, 2908 .nway_reset = phy_ethtool_nway_reset, 2909 .get_link = ethtool_op_get_link, 2910 .get_coalesce = fec_enet_get_coalesce, 2911 .set_coalesce = fec_enet_set_coalesce, 2912 #ifndef CONFIG_M5272 2913 .get_pauseparam = fec_enet_get_pauseparam, 2914 .set_pauseparam = fec_enet_set_pauseparam, 2915 .get_strings = fec_enet_get_strings, 2916 .get_ethtool_stats = fec_enet_get_ethtool_stats, 2917 .get_sset_count = fec_enet_get_sset_count, 2918 #endif 2919 .get_ts_info = fec_enet_get_ts_info, 2920 .get_tunable = fec_enet_get_tunable, 2921 .set_tunable = fec_enet_set_tunable, 2922 .get_wol = fec_enet_get_wol, 2923 .set_wol = fec_enet_set_wol, 2924 .get_eee = fec_enet_get_eee, 2925 .set_eee = fec_enet_set_eee, 2926 .get_link_ksettings = phy_ethtool_get_link_ksettings, 2927 .set_link_ksettings = phy_ethtool_set_link_ksettings, 2928 .self_test = net_selftest, 2929 }; 2930 2931 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) 2932 { 2933 struct fec_enet_private *fep = netdev_priv(ndev); 2934 struct phy_device *phydev = ndev->phydev; 2935 2936 if (!netif_running(ndev)) 2937 return -EINVAL; 2938 2939 if (!phydev) 2940 return -ENODEV; 2941 2942 if (fep->bufdesc_ex) { 2943 bool use_fec_hwts = !phy_has_hwtstamp(phydev); 2944 2945 if (cmd == SIOCSHWTSTAMP) { 2946 if (use_fec_hwts) 2947 return fec_ptp_set(ndev, rq); 2948 fec_ptp_disable_hwts(ndev); 2949 } else if (cmd == SIOCGHWTSTAMP) { 2950 if (use_fec_hwts) 2951 return fec_ptp_get(ndev, rq); 2952 } 2953 } 2954 2955 return phy_mii_ioctl(phydev, rq, cmd); 2956 } 2957 2958 static void fec_enet_free_buffers(struct net_device *ndev) 2959 { 2960 struct fec_enet_private *fep = netdev_priv(ndev); 2961 unsigned int i; 2962 struct sk_buff *skb; 2963 struct bufdesc *bdp; 2964 struct fec_enet_priv_tx_q *txq; 2965 struct fec_enet_priv_rx_q *rxq; 2966 unsigned int q; 2967 2968 for (q = 0; q < fep->num_rx_queues; q++) { 2969 rxq = fep->rx_queue[q]; 2970 bdp = rxq->bd.base; 2971 for (i = 0; i < rxq->bd.ring_size; i++) { 2972 skb = rxq->rx_skbuff[i]; 2973 rxq->rx_skbuff[i] = NULL; 2974 if (skb) { 2975 dma_unmap_single(&fep->pdev->dev, 2976 fec32_to_cpu(bdp->cbd_bufaddr), 2977 FEC_ENET_RX_FRSIZE - fep->rx_align, 2978 DMA_FROM_DEVICE); 2979 dev_kfree_skb(skb); 2980 } 2981 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 2982 } 2983 } 2984 2985 for (q = 0; q < fep->num_tx_queues; q++) { 2986 txq = fep->tx_queue[q]; 2987 for (i = 0; i < txq->bd.ring_size; i++) { 2988 kfree(txq->tx_bounce[i]); 2989 txq->tx_bounce[i] = NULL; 2990 skb = txq->tx_skbuff[i]; 2991 txq->tx_skbuff[i] = NULL; 2992 dev_kfree_skb(skb); 2993 } 2994 } 2995 } 2996 2997 static void fec_enet_free_queue(struct net_device *ndev) 2998 { 2999 struct fec_enet_private *fep = netdev_priv(ndev); 3000 int i; 3001 struct fec_enet_priv_tx_q *txq; 3002 3003 for (i = 0; i < fep->num_tx_queues; i++) 3004 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) { 3005 txq = fep->tx_queue[i]; 3006 dma_free_coherent(&fep->pdev->dev, 3007 txq->bd.ring_size * TSO_HEADER_SIZE, 3008 txq->tso_hdrs, 3009 txq->tso_hdrs_dma); 3010 } 3011 3012 for (i = 0; i < fep->num_rx_queues; i++) 3013 kfree(fep->rx_queue[i]); 3014 for (i = 0; i < fep->num_tx_queues; i++) 3015 kfree(fep->tx_queue[i]); 3016 } 3017 3018 static int fec_enet_alloc_queue(struct net_device *ndev) 3019 { 3020 struct fec_enet_private *fep = netdev_priv(ndev); 3021 int i; 3022 int ret = 0; 3023 struct fec_enet_priv_tx_q *txq; 3024 3025 for (i = 0; i < fep->num_tx_queues; i++) { 3026 txq = kzalloc(sizeof(*txq), GFP_KERNEL); 3027 if (!txq) { 3028 ret = -ENOMEM; 3029 goto alloc_failed; 3030 } 3031 3032 fep->tx_queue[i] = txq; 3033 txq->bd.ring_size = TX_RING_SIZE; 3034 fep->total_tx_ring_size += fep->tx_queue[i]->bd.ring_size; 3035 3036 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS; 3037 txq->tx_wake_threshold = 3038 (txq->bd.ring_size - txq->tx_stop_threshold) / 2; 3039 3040 txq->tso_hdrs = dma_alloc_coherent(&fep->pdev->dev, 3041 txq->bd.ring_size * TSO_HEADER_SIZE, 3042 &txq->tso_hdrs_dma, 3043 GFP_KERNEL); 3044 if (!txq->tso_hdrs) { 3045 ret = -ENOMEM; 3046 goto alloc_failed; 3047 } 3048 } 3049 3050 for (i = 0; i < fep->num_rx_queues; i++) { 3051 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]), 3052 GFP_KERNEL); 3053 if (!fep->rx_queue[i]) { 3054 ret = -ENOMEM; 3055 goto alloc_failed; 3056 } 3057 3058 fep->rx_queue[i]->bd.ring_size = RX_RING_SIZE; 3059 fep->total_rx_ring_size += fep->rx_queue[i]->bd.ring_size; 3060 } 3061 return ret; 3062 3063 alloc_failed: 3064 fec_enet_free_queue(ndev); 3065 return ret; 3066 } 3067 3068 static int 3069 fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue) 3070 { 3071 struct fec_enet_private *fep = netdev_priv(ndev); 3072 unsigned int i; 3073 struct sk_buff *skb; 3074 struct bufdesc *bdp; 3075 struct fec_enet_priv_rx_q *rxq; 3076 3077 rxq = fep->rx_queue[queue]; 3078 bdp = rxq->bd.base; 3079 for (i = 0; i < rxq->bd.ring_size; i++) { 3080 skb = __netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE, GFP_KERNEL); 3081 if (!skb) 3082 goto err_alloc; 3083 3084 if (fec_enet_new_rxbdp(ndev, bdp, skb)) { 3085 dev_kfree_skb(skb); 3086 goto err_alloc; 3087 } 3088 3089 rxq->rx_skbuff[i] = skb; 3090 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); 3091 3092 if (fep->bufdesc_ex) { 3093 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 3094 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); 3095 } 3096 3097 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 3098 } 3099 3100 /* Set the last buffer to wrap. */ 3101 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); 3102 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 3103 return 0; 3104 3105 err_alloc: 3106 fec_enet_free_buffers(ndev); 3107 return -ENOMEM; 3108 } 3109 3110 static int 3111 fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue) 3112 { 3113 struct fec_enet_private *fep = netdev_priv(ndev); 3114 unsigned int i; 3115 struct bufdesc *bdp; 3116 struct fec_enet_priv_tx_q *txq; 3117 3118 txq = fep->tx_queue[queue]; 3119 bdp = txq->bd.base; 3120 for (i = 0; i < txq->bd.ring_size; i++) { 3121 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); 3122 if (!txq->tx_bounce[i]) 3123 goto err_alloc; 3124 3125 bdp->cbd_sc = cpu_to_fec16(0); 3126 bdp->cbd_bufaddr = cpu_to_fec32(0); 3127 3128 if (fep->bufdesc_ex) { 3129 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 3130 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_TX_INT); 3131 } 3132 3133 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 3134 } 3135 3136 /* Set the last buffer to wrap. */ 3137 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); 3138 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 3139 3140 return 0; 3141 3142 err_alloc: 3143 fec_enet_free_buffers(ndev); 3144 return -ENOMEM; 3145 } 3146 3147 static int fec_enet_alloc_buffers(struct net_device *ndev) 3148 { 3149 struct fec_enet_private *fep = netdev_priv(ndev); 3150 unsigned int i; 3151 3152 for (i = 0; i < fep->num_rx_queues; i++) 3153 if (fec_enet_alloc_rxq_buffers(ndev, i)) 3154 return -ENOMEM; 3155 3156 for (i = 0; i < fep->num_tx_queues; i++) 3157 if (fec_enet_alloc_txq_buffers(ndev, i)) 3158 return -ENOMEM; 3159 return 0; 3160 } 3161 3162 static int 3163 fec_enet_open(struct net_device *ndev) 3164 { 3165 struct fec_enet_private *fep = netdev_priv(ndev); 3166 int ret; 3167 bool reset_again; 3168 3169 ret = pm_runtime_resume_and_get(&fep->pdev->dev); 3170 if (ret < 0) 3171 return ret; 3172 3173 pinctrl_pm_select_default_state(&fep->pdev->dev); 3174 ret = fec_enet_clk_enable(ndev, true); 3175 if (ret) 3176 goto clk_enable; 3177 3178 /* During the first fec_enet_open call the PHY isn't probed at this 3179 * point. Therefore the phy_reset_after_clk_enable() call within 3180 * fec_enet_clk_enable() fails. As we need this reset in order to be 3181 * sure the PHY is working correctly we check if we need to reset again 3182 * later when the PHY is probed 3183 */ 3184 if (ndev->phydev && ndev->phydev->drv) 3185 reset_again = false; 3186 else 3187 reset_again = true; 3188 3189 /* I should reset the ring buffers here, but I don't yet know 3190 * a simple way to do that. 3191 */ 3192 3193 ret = fec_enet_alloc_buffers(ndev); 3194 if (ret) 3195 goto err_enet_alloc; 3196 3197 /* Init MAC prior to mii bus probe */ 3198 fec_restart(ndev); 3199 3200 /* Call phy_reset_after_clk_enable() again if it failed during 3201 * phy_reset_after_clk_enable() before because the PHY wasn't probed. 3202 */ 3203 if (reset_again) 3204 fec_enet_phy_reset_after_clk_enable(ndev); 3205 3206 /* Probe and connect to PHY when open the interface */ 3207 ret = fec_enet_mii_probe(ndev); 3208 if (ret) 3209 goto err_enet_mii_probe; 3210 3211 if (fep->quirks & FEC_QUIRK_ERR006687) 3212 imx6q_cpuidle_fec_irqs_used(); 3213 3214 if (fep->quirks & FEC_QUIRK_HAS_PMQOS) 3215 cpu_latency_qos_add_request(&fep->pm_qos_req, 0); 3216 3217 napi_enable(&fep->napi); 3218 phy_start(ndev->phydev); 3219 netif_tx_start_all_queues(ndev); 3220 3221 device_set_wakeup_enable(&ndev->dev, fep->wol_flag & 3222 FEC_WOL_FLAG_ENABLE); 3223 3224 return 0; 3225 3226 err_enet_mii_probe: 3227 fec_enet_free_buffers(ndev); 3228 err_enet_alloc: 3229 fec_enet_clk_enable(ndev, false); 3230 clk_enable: 3231 pm_runtime_mark_last_busy(&fep->pdev->dev); 3232 pm_runtime_put_autosuspend(&fep->pdev->dev); 3233 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3234 return ret; 3235 } 3236 3237 static int 3238 fec_enet_close(struct net_device *ndev) 3239 { 3240 struct fec_enet_private *fep = netdev_priv(ndev); 3241 3242 phy_stop(ndev->phydev); 3243 3244 if (netif_device_present(ndev)) { 3245 napi_disable(&fep->napi); 3246 netif_tx_disable(ndev); 3247 fec_stop(ndev); 3248 } 3249 3250 phy_disconnect(ndev->phydev); 3251 3252 if (fep->quirks & FEC_QUIRK_ERR006687) 3253 imx6q_cpuidle_fec_irqs_unused(); 3254 3255 fec_enet_update_ethtool_stats(ndev); 3256 3257 fec_enet_clk_enable(ndev, false); 3258 if (fep->quirks & FEC_QUIRK_HAS_PMQOS) 3259 cpu_latency_qos_remove_request(&fep->pm_qos_req); 3260 3261 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3262 pm_runtime_mark_last_busy(&fep->pdev->dev); 3263 pm_runtime_put_autosuspend(&fep->pdev->dev); 3264 3265 fec_enet_free_buffers(ndev); 3266 3267 return 0; 3268 } 3269 3270 /* Set or clear the multicast filter for this adaptor. 3271 * Skeleton taken from sunlance driver. 3272 * The CPM Ethernet implementation allows Multicast as well as individual 3273 * MAC address filtering. Some of the drivers check to make sure it is 3274 * a group multicast address, and discard those that are not. I guess I 3275 * will do the same for now, but just remove the test if you want 3276 * individual filtering as well (do the upper net layers want or support 3277 * this kind of feature?). 3278 */ 3279 3280 #define FEC_HASH_BITS 6 /* #bits in hash */ 3281 3282 static void set_multicast_list(struct net_device *ndev) 3283 { 3284 struct fec_enet_private *fep = netdev_priv(ndev); 3285 struct netdev_hw_addr *ha; 3286 unsigned int crc, tmp; 3287 unsigned char hash; 3288 unsigned int hash_high = 0, hash_low = 0; 3289 3290 if (ndev->flags & IFF_PROMISC) { 3291 tmp = readl(fep->hwp + FEC_R_CNTRL); 3292 tmp |= 0x8; 3293 writel(tmp, fep->hwp + FEC_R_CNTRL); 3294 return; 3295 } 3296 3297 tmp = readl(fep->hwp + FEC_R_CNTRL); 3298 tmp &= ~0x8; 3299 writel(tmp, fep->hwp + FEC_R_CNTRL); 3300 3301 if (ndev->flags & IFF_ALLMULTI) { 3302 /* Catch all multicast addresses, so set the 3303 * filter to all 1's 3304 */ 3305 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 3306 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 3307 3308 return; 3309 } 3310 3311 /* Add the addresses in hash register */ 3312 netdev_for_each_mc_addr(ha, ndev) { 3313 /* calculate crc32 value of mac address */ 3314 crc = ether_crc_le(ndev->addr_len, ha->addr); 3315 3316 /* only upper 6 bits (FEC_HASH_BITS) are used 3317 * which point to specific bit in the hash registers 3318 */ 3319 hash = (crc >> (32 - FEC_HASH_BITS)) & 0x3f; 3320 3321 if (hash > 31) 3322 hash_high |= 1 << (hash - 32); 3323 else 3324 hash_low |= 1 << hash; 3325 } 3326 3327 writel(hash_high, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 3328 writel(hash_low, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 3329 } 3330 3331 /* Set a MAC change in hardware. */ 3332 static int 3333 fec_set_mac_address(struct net_device *ndev, void *p) 3334 { 3335 struct fec_enet_private *fep = netdev_priv(ndev); 3336 struct sockaddr *addr = p; 3337 3338 if (addr) { 3339 if (!is_valid_ether_addr(addr->sa_data)) 3340 return -EADDRNOTAVAIL; 3341 eth_hw_addr_set(ndev, addr->sa_data); 3342 } 3343 3344 /* Add netif status check here to avoid system hang in below case: 3345 * ifconfig ethx down; ifconfig ethx hw ether xx:xx:xx:xx:xx:xx; 3346 * After ethx down, fec all clocks are gated off and then register 3347 * access causes system hang. 3348 */ 3349 if (!netif_running(ndev)) 3350 return 0; 3351 3352 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) | 3353 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24), 3354 fep->hwp + FEC_ADDR_LOW); 3355 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24), 3356 fep->hwp + FEC_ADDR_HIGH); 3357 return 0; 3358 } 3359 3360 #ifdef CONFIG_NET_POLL_CONTROLLER 3361 /** 3362 * fec_poll_controller - FEC Poll controller function 3363 * @dev: The FEC network adapter 3364 * 3365 * Polled functionality used by netconsole and others in non interrupt mode 3366 * 3367 */ 3368 static void fec_poll_controller(struct net_device *dev) 3369 { 3370 int i; 3371 struct fec_enet_private *fep = netdev_priv(dev); 3372 3373 for (i = 0; i < FEC_IRQ_NUM; i++) { 3374 if (fep->irq[i] > 0) { 3375 disable_irq(fep->irq[i]); 3376 fec_enet_interrupt(fep->irq[i], dev); 3377 enable_irq(fep->irq[i]); 3378 } 3379 } 3380 } 3381 #endif 3382 3383 static inline void fec_enet_set_netdev_features(struct net_device *netdev, 3384 netdev_features_t features) 3385 { 3386 struct fec_enet_private *fep = netdev_priv(netdev); 3387 netdev_features_t changed = features ^ netdev->features; 3388 3389 netdev->features = features; 3390 3391 /* Receive checksum has been changed */ 3392 if (changed & NETIF_F_RXCSUM) { 3393 if (features & NETIF_F_RXCSUM) 3394 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 3395 else 3396 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED; 3397 } 3398 } 3399 3400 static int fec_set_features(struct net_device *netdev, 3401 netdev_features_t features) 3402 { 3403 struct fec_enet_private *fep = netdev_priv(netdev); 3404 netdev_features_t changed = features ^ netdev->features; 3405 3406 if (netif_running(netdev) && changed & NETIF_F_RXCSUM) { 3407 napi_disable(&fep->napi); 3408 netif_tx_lock_bh(netdev); 3409 fec_stop(netdev); 3410 fec_enet_set_netdev_features(netdev, features); 3411 fec_restart(netdev); 3412 netif_tx_wake_all_queues(netdev); 3413 netif_tx_unlock_bh(netdev); 3414 napi_enable(&fep->napi); 3415 } else { 3416 fec_enet_set_netdev_features(netdev, features); 3417 } 3418 3419 return 0; 3420 } 3421 3422 static u16 fec_enet_get_raw_vlan_tci(struct sk_buff *skb) 3423 { 3424 struct vlan_ethhdr *vhdr; 3425 unsigned short vlan_TCI = 0; 3426 3427 if (skb->protocol == htons(ETH_P_ALL)) { 3428 vhdr = (struct vlan_ethhdr *)(skb->data); 3429 vlan_TCI = ntohs(vhdr->h_vlan_TCI); 3430 } 3431 3432 return vlan_TCI; 3433 } 3434 3435 static u16 fec_enet_select_queue(struct net_device *ndev, struct sk_buff *skb, 3436 struct net_device *sb_dev) 3437 { 3438 struct fec_enet_private *fep = netdev_priv(ndev); 3439 u16 vlan_tag; 3440 3441 if (!(fep->quirks & FEC_QUIRK_HAS_AVB)) 3442 return netdev_pick_tx(ndev, skb, NULL); 3443 3444 vlan_tag = fec_enet_get_raw_vlan_tci(skb); 3445 if (!vlan_tag) 3446 return vlan_tag; 3447 3448 return fec_enet_vlan_pri_to_queue[vlan_tag >> 13]; 3449 } 3450 3451 static const struct net_device_ops fec_netdev_ops = { 3452 .ndo_open = fec_enet_open, 3453 .ndo_stop = fec_enet_close, 3454 .ndo_start_xmit = fec_enet_start_xmit, 3455 .ndo_select_queue = fec_enet_select_queue, 3456 .ndo_set_rx_mode = set_multicast_list, 3457 .ndo_validate_addr = eth_validate_addr, 3458 .ndo_tx_timeout = fec_timeout, 3459 .ndo_set_mac_address = fec_set_mac_address, 3460 .ndo_eth_ioctl = fec_enet_ioctl, 3461 #ifdef CONFIG_NET_POLL_CONTROLLER 3462 .ndo_poll_controller = fec_poll_controller, 3463 #endif 3464 .ndo_set_features = fec_set_features, 3465 }; 3466 3467 static const unsigned short offset_des_active_rxq[] = { 3468 FEC_R_DES_ACTIVE_0, FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2 3469 }; 3470 3471 static const unsigned short offset_des_active_txq[] = { 3472 FEC_X_DES_ACTIVE_0, FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2 3473 }; 3474 3475 /* 3476 * XXX: We need to clean up on failure exits here. 3477 * 3478 */ 3479 static int fec_enet_init(struct net_device *ndev) 3480 { 3481 struct fec_enet_private *fep = netdev_priv(ndev); 3482 struct bufdesc *cbd_base; 3483 dma_addr_t bd_dma; 3484 int bd_size; 3485 unsigned int i; 3486 unsigned dsize = fep->bufdesc_ex ? sizeof(struct bufdesc_ex) : 3487 sizeof(struct bufdesc); 3488 unsigned dsize_log2 = __fls(dsize); 3489 int ret; 3490 3491 WARN_ON(dsize != (1 << dsize_log2)); 3492 #if defined(CONFIG_ARM) || defined(CONFIG_ARM64) 3493 fep->rx_align = 0xf; 3494 fep->tx_align = 0xf; 3495 #else 3496 fep->rx_align = 0x3; 3497 fep->tx_align = 0x3; 3498 #endif 3499 3500 /* Check mask of the streaming and coherent API */ 3501 ret = dma_set_mask_and_coherent(&fep->pdev->dev, DMA_BIT_MASK(32)); 3502 if (ret < 0) { 3503 dev_warn(&fep->pdev->dev, "No suitable DMA available\n"); 3504 return ret; 3505 } 3506 3507 ret = fec_enet_alloc_queue(ndev); 3508 if (ret) 3509 return ret; 3510 3511 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) * dsize; 3512 3513 /* Allocate memory for buffer descriptors. */ 3514 cbd_base = dmam_alloc_coherent(&fep->pdev->dev, bd_size, &bd_dma, 3515 GFP_KERNEL); 3516 if (!cbd_base) { 3517 ret = -ENOMEM; 3518 goto free_queue_mem; 3519 } 3520 3521 /* Get the Ethernet address */ 3522 ret = fec_get_mac(ndev); 3523 if (ret) 3524 goto free_queue_mem; 3525 3526 /* make sure MAC we just acquired is programmed into the hw */ 3527 fec_set_mac_address(ndev, NULL); 3528 3529 /* Set receive and transmit descriptor base. */ 3530 for (i = 0; i < fep->num_rx_queues; i++) { 3531 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[i]; 3532 unsigned size = dsize * rxq->bd.ring_size; 3533 3534 rxq->bd.qid = i; 3535 rxq->bd.base = cbd_base; 3536 rxq->bd.cur = cbd_base; 3537 rxq->bd.dma = bd_dma; 3538 rxq->bd.dsize = dsize; 3539 rxq->bd.dsize_log2 = dsize_log2; 3540 rxq->bd.reg_desc_active = fep->hwp + offset_des_active_rxq[i]; 3541 bd_dma += size; 3542 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size); 3543 rxq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); 3544 } 3545 3546 for (i = 0; i < fep->num_tx_queues; i++) { 3547 struct fec_enet_priv_tx_q *txq = fep->tx_queue[i]; 3548 unsigned size = dsize * txq->bd.ring_size; 3549 3550 txq->bd.qid = i; 3551 txq->bd.base = cbd_base; 3552 txq->bd.cur = cbd_base; 3553 txq->bd.dma = bd_dma; 3554 txq->bd.dsize = dsize; 3555 txq->bd.dsize_log2 = dsize_log2; 3556 txq->bd.reg_desc_active = fep->hwp + offset_des_active_txq[i]; 3557 bd_dma += size; 3558 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size); 3559 txq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); 3560 } 3561 3562 3563 /* The FEC Ethernet specific entries in the device structure */ 3564 ndev->watchdog_timeo = TX_TIMEOUT; 3565 ndev->netdev_ops = &fec_netdev_ops; 3566 ndev->ethtool_ops = &fec_enet_ethtool_ops; 3567 3568 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK); 3569 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT); 3570 3571 if (fep->quirks & FEC_QUIRK_HAS_VLAN) 3572 /* enable hw VLAN support */ 3573 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; 3574 3575 if (fep->quirks & FEC_QUIRK_HAS_CSUM) { 3576 netif_set_tso_max_segs(ndev, FEC_MAX_TSO_SEGS); 3577 3578 /* enable hw accelerator */ 3579 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM 3580 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO); 3581 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 3582 } 3583 3584 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) { 3585 fep->tx_align = 0; 3586 fep->rx_align = 0x3f; 3587 } 3588 3589 ndev->hw_features = ndev->features; 3590 3591 fec_restart(ndev); 3592 3593 if (fep->quirks & FEC_QUIRK_MIB_CLEAR) 3594 fec_enet_clear_ethtool_stats(ndev); 3595 else 3596 fec_enet_update_ethtool_stats(ndev); 3597 3598 return 0; 3599 3600 free_queue_mem: 3601 fec_enet_free_queue(ndev); 3602 return ret; 3603 } 3604 3605 #ifdef CONFIG_OF 3606 static int fec_reset_phy(struct platform_device *pdev) 3607 { 3608 int err, phy_reset; 3609 bool active_high = false; 3610 int msec = 1, phy_post_delay = 0; 3611 struct device_node *np = pdev->dev.of_node; 3612 3613 if (!np) 3614 return 0; 3615 3616 err = of_property_read_u32(np, "phy-reset-duration", &msec); 3617 /* A sane reset duration should not be longer than 1s */ 3618 if (!err && msec > 1000) 3619 msec = 1; 3620 3621 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0); 3622 if (phy_reset == -EPROBE_DEFER) 3623 return phy_reset; 3624 else if (!gpio_is_valid(phy_reset)) 3625 return 0; 3626 3627 err = of_property_read_u32(np, "phy-reset-post-delay", &phy_post_delay); 3628 /* valid reset duration should be less than 1s */ 3629 if (!err && phy_post_delay > 1000) 3630 return -EINVAL; 3631 3632 active_high = of_property_read_bool(np, "phy-reset-active-high"); 3633 3634 err = devm_gpio_request_one(&pdev->dev, phy_reset, 3635 active_high ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW, 3636 "phy-reset"); 3637 if (err) { 3638 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err); 3639 return err; 3640 } 3641 3642 if (msec > 20) 3643 msleep(msec); 3644 else 3645 usleep_range(msec * 1000, msec * 1000 + 1000); 3646 3647 gpio_set_value_cansleep(phy_reset, !active_high); 3648 3649 if (!phy_post_delay) 3650 return 0; 3651 3652 if (phy_post_delay > 20) 3653 msleep(phy_post_delay); 3654 else 3655 usleep_range(phy_post_delay * 1000, 3656 phy_post_delay * 1000 + 1000); 3657 3658 return 0; 3659 } 3660 #else /* CONFIG_OF */ 3661 static int fec_reset_phy(struct platform_device *pdev) 3662 { 3663 /* 3664 * In case of platform probe, the reset has been done 3665 * by machine code. 3666 */ 3667 return 0; 3668 } 3669 #endif /* CONFIG_OF */ 3670 3671 static void 3672 fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx) 3673 { 3674 struct device_node *np = pdev->dev.of_node; 3675 3676 *num_tx = *num_rx = 1; 3677 3678 if (!np || !of_device_is_available(np)) 3679 return; 3680 3681 /* parse the num of tx and rx queues */ 3682 of_property_read_u32(np, "fsl,num-tx-queues", num_tx); 3683 3684 of_property_read_u32(np, "fsl,num-rx-queues", num_rx); 3685 3686 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) { 3687 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n", 3688 *num_tx); 3689 *num_tx = 1; 3690 return; 3691 } 3692 3693 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) { 3694 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n", 3695 *num_rx); 3696 *num_rx = 1; 3697 return; 3698 } 3699 3700 } 3701 3702 static int fec_enet_get_irq_cnt(struct platform_device *pdev) 3703 { 3704 int irq_cnt = platform_irq_count(pdev); 3705 3706 if (irq_cnt > FEC_IRQ_NUM) 3707 irq_cnt = FEC_IRQ_NUM; /* last for pps */ 3708 else if (irq_cnt == 2) 3709 irq_cnt = 1; /* last for pps */ 3710 else if (irq_cnt <= 0) 3711 irq_cnt = 1; /* At least 1 irq is needed */ 3712 return irq_cnt; 3713 } 3714 3715 static void fec_enet_get_wakeup_irq(struct platform_device *pdev) 3716 { 3717 struct net_device *ndev = platform_get_drvdata(pdev); 3718 struct fec_enet_private *fep = netdev_priv(ndev); 3719 3720 if (fep->quirks & FEC_QUIRK_WAKEUP_FROM_INT2) 3721 fep->wake_irq = fep->irq[2]; 3722 else 3723 fep->wake_irq = fep->irq[0]; 3724 } 3725 3726 static int fec_enet_init_stop_mode(struct fec_enet_private *fep, 3727 struct device_node *np) 3728 { 3729 struct device_node *gpr_np; 3730 u32 out_val[3]; 3731 int ret = 0; 3732 3733 gpr_np = of_parse_phandle(np, "fsl,stop-mode", 0); 3734 if (!gpr_np) 3735 return 0; 3736 3737 ret = of_property_read_u32_array(np, "fsl,stop-mode", out_val, 3738 ARRAY_SIZE(out_val)); 3739 if (ret) { 3740 dev_dbg(&fep->pdev->dev, "no stop mode property\n"); 3741 goto out; 3742 } 3743 3744 fep->stop_gpr.gpr = syscon_node_to_regmap(gpr_np); 3745 if (IS_ERR(fep->stop_gpr.gpr)) { 3746 dev_err(&fep->pdev->dev, "could not find gpr regmap\n"); 3747 ret = PTR_ERR(fep->stop_gpr.gpr); 3748 fep->stop_gpr.gpr = NULL; 3749 goto out; 3750 } 3751 3752 fep->stop_gpr.reg = out_val[1]; 3753 fep->stop_gpr.bit = out_val[2]; 3754 3755 out: 3756 of_node_put(gpr_np); 3757 3758 return ret; 3759 } 3760 3761 static int 3762 fec_probe(struct platform_device *pdev) 3763 { 3764 struct fec_enet_private *fep; 3765 struct fec_platform_data *pdata; 3766 phy_interface_t interface; 3767 struct net_device *ndev; 3768 int i, irq, ret = 0; 3769 const struct of_device_id *of_id; 3770 static int dev_id; 3771 struct device_node *np = pdev->dev.of_node, *phy_node; 3772 int num_tx_qs; 3773 int num_rx_qs; 3774 char irq_name[8]; 3775 int irq_cnt; 3776 struct fec_devinfo *dev_info; 3777 3778 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs); 3779 3780 /* Init network device */ 3781 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private) + 3782 FEC_STATS_SIZE, num_tx_qs, num_rx_qs); 3783 if (!ndev) 3784 return -ENOMEM; 3785 3786 SET_NETDEV_DEV(ndev, &pdev->dev); 3787 3788 /* setup board info structure */ 3789 fep = netdev_priv(ndev); 3790 3791 of_id = of_match_device(fec_dt_ids, &pdev->dev); 3792 if (of_id) 3793 pdev->id_entry = of_id->data; 3794 dev_info = (struct fec_devinfo *)pdev->id_entry->driver_data; 3795 if (dev_info) 3796 fep->quirks = dev_info->quirks; 3797 3798 fep->netdev = ndev; 3799 fep->num_rx_queues = num_rx_qs; 3800 fep->num_tx_queues = num_tx_qs; 3801 3802 #if !defined(CONFIG_M5272) 3803 /* default enable pause frame auto negotiation */ 3804 if (fep->quirks & FEC_QUIRK_HAS_GBIT) 3805 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG; 3806 #endif 3807 3808 /* Select default pin state */ 3809 pinctrl_pm_select_default_state(&pdev->dev); 3810 3811 fep->hwp = devm_platform_ioremap_resource(pdev, 0); 3812 if (IS_ERR(fep->hwp)) { 3813 ret = PTR_ERR(fep->hwp); 3814 goto failed_ioremap; 3815 } 3816 3817 fep->pdev = pdev; 3818 fep->dev_id = dev_id++; 3819 3820 platform_set_drvdata(pdev, ndev); 3821 3822 if ((of_machine_is_compatible("fsl,imx6q") || 3823 of_machine_is_compatible("fsl,imx6dl")) && 3824 !of_property_read_bool(np, "fsl,err006687-workaround-present")) 3825 fep->quirks |= FEC_QUIRK_ERR006687; 3826 3827 if (of_get_property(np, "fsl,magic-packet", NULL)) 3828 fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET; 3829 3830 ret = fec_enet_init_stop_mode(fep, np); 3831 if (ret) 3832 goto failed_stop_mode; 3833 3834 phy_node = of_parse_phandle(np, "phy-handle", 0); 3835 if (!phy_node && of_phy_is_fixed_link(np)) { 3836 ret = of_phy_register_fixed_link(np); 3837 if (ret < 0) { 3838 dev_err(&pdev->dev, 3839 "broken fixed-link specification\n"); 3840 goto failed_phy; 3841 } 3842 phy_node = of_node_get(np); 3843 } 3844 fep->phy_node = phy_node; 3845 3846 ret = of_get_phy_mode(pdev->dev.of_node, &interface); 3847 if (ret) { 3848 pdata = dev_get_platdata(&pdev->dev); 3849 if (pdata) 3850 fep->phy_interface = pdata->phy; 3851 else 3852 fep->phy_interface = PHY_INTERFACE_MODE_MII; 3853 } else { 3854 fep->phy_interface = interface; 3855 } 3856 3857 ret = fec_enet_parse_rgmii_delay(fep, np); 3858 if (ret) 3859 goto failed_rgmii_delay; 3860 3861 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 3862 if (IS_ERR(fep->clk_ipg)) { 3863 ret = PTR_ERR(fep->clk_ipg); 3864 goto failed_clk; 3865 } 3866 3867 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 3868 if (IS_ERR(fep->clk_ahb)) { 3869 ret = PTR_ERR(fep->clk_ahb); 3870 goto failed_clk; 3871 } 3872 3873 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb); 3874 3875 /* enet_out is optional, depends on board */ 3876 fep->clk_enet_out = devm_clk_get_optional(&pdev->dev, "enet_out"); 3877 if (IS_ERR(fep->clk_enet_out)) { 3878 ret = PTR_ERR(fep->clk_enet_out); 3879 goto failed_clk; 3880 } 3881 3882 fep->ptp_clk_on = false; 3883 mutex_init(&fep->ptp_clk_mutex); 3884 3885 /* clk_ref is optional, depends on board */ 3886 fep->clk_ref = devm_clk_get_optional(&pdev->dev, "enet_clk_ref"); 3887 if (IS_ERR(fep->clk_ref)) { 3888 ret = PTR_ERR(fep->clk_ref); 3889 goto failed_clk; 3890 } 3891 fep->clk_ref_rate = clk_get_rate(fep->clk_ref); 3892 3893 /* clk_2x_txclk is optional, depends on board */ 3894 if (fep->rgmii_txc_dly || fep->rgmii_rxc_dly) { 3895 fep->clk_2x_txclk = devm_clk_get(&pdev->dev, "enet_2x_txclk"); 3896 if (IS_ERR(fep->clk_2x_txclk)) 3897 fep->clk_2x_txclk = NULL; 3898 } 3899 3900 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX; 3901 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp"); 3902 if (IS_ERR(fep->clk_ptp)) { 3903 fep->clk_ptp = NULL; 3904 fep->bufdesc_ex = false; 3905 } 3906 3907 ret = fec_enet_clk_enable(ndev, true); 3908 if (ret) 3909 goto failed_clk; 3910 3911 ret = clk_prepare_enable(fep->clk_ipg); 3912 if (ret) 3913 goto failed_clk_ipg; 3914 ret = clk_prepare_enable(fep->clk_ahb); 3915 if (ret) 3916 goto failed_clk_ahb; 3917 3918 fep->reg_phy = devm_regulator_get_optional(&pdev->dev, "phy"); 3919 if (!IS_ERR(fep->reg_phy)) { 3920 ret = regulator_enable(fep->reg_phy); 3921 if (ret) { 3922 dev_err(&pdev->dev, 3923 "Failed to enable phy regulator: %d\n", ret); 3924 goto failed_regulator; 3925 } 3926 } else { 3927 if (PTR_ERR(fep->reg_phy) == -EPROBE_DEFER) { 3928 ret = -EPROBE_DEFER; 3929 goto failed_regulator; 3930 } 3931 fep->reg_phy = NULL; 3932 } 3933 3934 pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT); 3935 pm_runtime_use_autosuspend(&pdev->dev); 3936 pm_runtime_get_noresume(&pdev->dev); 3937 pm_runtime_set_active(&pdev->dev); 3938 pm_runtime_enable(&pdev->dev); 3939 3940 ret = fec_reset_phy(pdev); 3941 if (ret) 3942 goto failed_reset; 3943 3944 irq_cnt = fec_enet_get_irq_cnt(pdev); 3945 if (fep->bufdesc_ex) 3946 fec_ptp_init(pdev, irq_cnt); 3947 3948 ret = fec_enet_init(ndev); 3949 if (ret) 3950 goto failed_init; 3951 3952 for (i = 0; i < irq_cnt; i++) { 3953 snprintf(irq_name, sizeof(irq_name), "int%d", i); 3954 irq = platform_get_irq_byname_optional(pdev, irq_name); 3955 if (irq < 0) 3956 irq = platform_get_irq(pdev, i); 3957 if (irq < 0) { 3958 ret = irq; 3959 goto failed_irq; 3960 } 3961 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt, 3962 0, pdev->name, ndev); 3963 if (ret) 3964 goto failed_irq; 3965 3966 fep->irq[i] = irq; 3967 } 3968 3969 /* Decide which interrupt line is wakeup capable */ 3970 fec_enet_get_wakeup_irq(pdev); 3971 3972 ret = fec_enet_mii_init(pdev); 3973 if (ret) 3974 goto failed_mii_init; 3975 3976 /* Carrier starts down, phylib will bring it up */ 3977 netif_carrier_off(ndev); 3978 fec_enet_clk_enable(ndev, false); 3979 pinctrl_pm_select_sleep_state(&pdev->dev); 3980 3981 ndev->max_mtu = PKT_MAXBUF_SIZE - ETH_HLEN - ETH_FCS_LEN; 3982 3983 ret = register_netdev(ndev); 3984 if (ret) 3985 goto failed_register; 3986 3987 device_init_wakeup(&ndev->dev, fep->wol_flag & 3988 FEC_WOL_HAS_MAGIC_PACKET); 3989 3990 if (fep->bufdesc_ex && fep->ptp_clock) 3991 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id); 3992 3993 fep->rx_copybreak = COPYBREAK_DEFAULT; 3994 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work); 3995 3996 pm_runtime_mark_last_busy(&pdev->dev); 3997 pm_runtime_put_autosuspend(&pdev->dev); 3998 3999 return 0; 4000 4001 failed_register: 4002 fec_enet_mii_remove(fep); 4003 failed_mii_init: 4004 failed_irq: 4005 failed_init: 4006 fec_ptp_stop(pdev); 4007 failed_reset: 4008 pm_runtime_put_noidle(&pdev->dev); 4009 pm_runtime_disable(&pdev->dev); 4010 if (fep->reg_phy) 4011 regulator_disable(fep->reg_phy); 4012 failed_regulator: 4013 clk_disable_unprepare(fep->clk_ahb); 4014 failed_clk_ahb: 4015 clk_disable_unprepare(fep->clk_ipg); 4016 failed_clk_ipg: 4017 fec_enet_clk_enable(ndev, false); 4018 failed_clk: 4019 failed_rgmii_delay: 4020 if (of_phy_is_fixed_link(np)) 4021 of_phy_deregister_fixed_link(np); 4022 of_node_put(phy_node); 4023 failed_stop_mode: 4024 failed_phy: 4025 dev_id--; 4026 failed_ioremap: 4027 free_netdev(ndev); 4028 4029 return ret; 4030 } 4031 4032 static int 4033 fec_drv_remove(struct platform_device *pdev) 4034 { 4035 struct net_device *ndev = platform_get_drvdata(pdev); 4036 struct fec_enet_private *fep = netdev_priv(ndev); 4037 struct device_node *np = pdev->dev.of_node; 4038 int ret; 4039 4040 ret = pm_runtime_resume_and_get(&pdev->dev); 4041 if (ret < 0) 4042 return ret; 4043 4044 cancel_work_sync(&fep->tx_timeout_work); 4045 fec_ptp_stop(pdev); 4046 unregister_netdev(ndev); 4047 fec_enet_mii_remove(fep); 4048 if (fep->reg_phy) 4049 regulator_disable(fep->reg_phy); 4050 4051 if (of_phy_is_fixed_link(np)) 4052 of_phy_deregister_fixed_link(np); 4053 of_node_put(fep->phy_node); 4054 4055 clk_disable_unprepare(fep->clk_ahb); 4056 clk_disable_unprepare(fep->clk_ipg); 4057 pm_runtime_put_noidle(&pdev->dev); 4058 pm_runtime_disable(&pdev->dev); 4059 4060 free_netdev(ndev); 4061 return 0; 4062 } 4063 4064 static int __maybe_unused fec_suspend(struct device *dev) 4065 { 4066 struct net_device *ndev = dev_get_drvdata(dev); 4067 struct fec_enet_private *fep = netdev_priv(ndev); 4068 4069 rtnl_lock(); 4070 if (netif_running(ndev)) { 4071 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) 4072 fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON; 4073 phy_stop(ndev->phydev); 4074 napi_disable(&fep->napi); 4075 netif_tx_lock_bh(ndev); 4076 netif_device_detach(ndev); 4077 netif_tx_unlock_bh(ndev); 4078 fec_stop(ndev); 4079 if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) { 4080 fec_irqs_disable(ndev); 4081 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 4082 } else { 4083 fec_irqs_disable_except_wakeup(ndev); 4084 if (fep->wake_irq > 0) { 4085 disable_irq(fep->wake_irq); 4086 enable_irq_wake(fep->wake_irq); 4087 } 4088 fec_enet_stop_mode(fep, true); 4089 } 4090 /* It's safe to disable clocks since interrupts are masked */ 4091 fec_enet_clk_enable(ndev, false); 4092 } 4093 rtnl_unlock(); 4094 4095 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) 4096 regulator_disable(fep->reg_phy); 4097 4098 /* SOC supply clock to phy, when clock is disabled, phy link down 4099 * SOC control phy regulator, when regulator is disabled, phy link down 4100 */ 4101 if (fep->clk_enet_out || fep->reg_phy) 4102 fep->link = 0; 4103 4104 return 0; 4105 } 4106 4107 static int __maybe_unused fec_resume(struct device *dev) 4108 { 4109 struct net_device *ndev = dev_get_drvdata(dev); 4110 struct fec_enet_private *fep = netdev_priv(ndev); 4111 int ret; 4112 int val; 4113 4114 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) { 4115 ret = regulator_enable(fep->reg_phy); 4116 if (ret) 4117 return ret; 4118 } 4119 4120 rtnl_lock(); 4121 if (netif_running(ndev)) { 4122 ret = fec_enet_clk_enable(ndev, true); 4123 if (ret) { 4124 rtnl_unlock(); 4125 goto failed_clk; 4126 } 4127 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) { 4128 fec_enet_stop_mode(fep, false); 4129 if (fep->wake_irq) { 4130 disable_irq_wake(fep->wake_irq); 4131 enable_irq(fep->wake_irq); 4132 } 4133 4134 val = readl(fep->hwp + FEC_ECNTRL); 4135 val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP); 4136 writel(val, fep->hwp + FEC_ECNTRL); 4137 fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON; 4138 } else { 4139 pinctrl_pm_select_default_state(&fep->pdev->dev); 4140 } 4141 fec_restart(ndev); 4142 netif_tx_lock_bh(ndev); 4143 netif_device_attach(ndev); 4144 netif_tx_unlock_bh(ndev); 4145 napi_enable(&fep->napi); 4146 phy_init_hw(ndev->phydev); 4147 phy_start(ndev->phydev); 4148 } 4149 rtnl_unlock(); 4150 4151 return 0; 4152 4153 failed_clk: 4154 if (fep->reg_phy) 4155 regulator_disable(fep->reg_phy); 4156 return ret; 4157 } 4158 4159 static int __maybe_unused fec_runtime_suspend(struct device *dev) 4160 { 4161 struct net_device *ndev = dev_get_drvdata(dev); 4162 struct fec_enet_private *fep = netdev_priv(ndev); 4163 4164 clk_disable_unprepare(fep->clk_ahb); 4165 clk_disable_unprepare(fep->clk_ipg); 4166 4167 return 0; 4168 } 4169 4170 static int __maybe_unused fec_runtime_resume(struct device *dev) 4171 { 4172 struct net_device *ndev = dev_get_drvdata(dev); 4173 struct fec_enet_private *fep = netdev_priv(ndev); 4174 int ret; 4175 4176 ret = clk_prepare_enable(fep->clk_ahb); 4177 if (ret) 4178 return ret; 4179 ret = clk_prepare_enable(fep->clk_ipg); 4180 if (ret) 4181 goto failed_clk_ipg; 4182 4183 return 0; 4184 4185 failed_clk_ipg: 4186 clk_disable_unprepare(fep->clk_ahb); 4187 return ret; 4188 } 4189 4190 static const struct dev_pm_ops fec_pm_ops = { 4191 SET_SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume) 4192 SET_RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL) 4193 }; 4194 4195 static struct platform_driver fec_driver = { 4196 .driver = { 4197 .name = DRIVER_NAME, 4198 .pm = &fec_pm_ops, 4199 .of_match_table = fec_dt_ids, 4200 .suppress_bind_attrs = true, 4201 }, 4202 .id_table = fec_devtype, 4203 .probe = fec_probe, 4204 .remove = fec_drv_remove, 4205 }; 4206 4207 module_platform_driver(fec_driver); 4208 4209 MODULE_LICENSE("GPL"); 4210