1 /****************************************************************************/ 2 3 /* 4 * fec.h -- Fast Ethernet Controller for Motorola ColdFire SoC 5 * processors. 6 * 7 * (C) Copyright 2000-2005, Greg Ungerer (gerg@snapgear.com) 8 * (C) Copyright 2000-2001, Lineo (www.lineo.com) 9 */ 10 11 /****************************************************************************/ 12 #ifndef FEC_H 13 #define FEC_H 14 /****************************************************************************/ 15 16 #include <linux/clocksource.h> 17 #include <linux/net_tstamp.h> 18 #include <linux/ptp_clock_kernel.h> 19 #include <linux/timecounter.h> 20 21 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 22 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) 23 /* 24 * Just figures, Motorola would have to change the offsets for 25 * registers in the same peripheral device on different models 26 * of the ColdFire! 27 */ 28 #define FEC_IEVENT 0x004 /* Interrupt event reg */ 29 #define FEC_IMASK 0x008 /* Interrupt mask reg */ 30 #define FEC_R_DES_ACTIVE_0 0x010 /* Receive descriptor reg */ 31 #define FEC_X_DES_ACTIVE_0 0x014 /* Transmit descriptor reg */ 32 #define FEC_ECNTRL 0x024 /* Ethernet control reg */ 33 #define FEC_MII_DATA 0x040 /* MII manage frame reg */ 34 #define FEC_MII_SPEED 0x044 /* MII speed control reg */ 35 #define FEC_MIB_CTRLSTAT 0x064 /* MIB control/status reg */ 36 #define FEC_R_CNTRL 0x084 /* Receive control reg */ 37 #define FEC_X_CNTRL 0x0c4 /* Transmit Control reg */ 38 #define FEC_ADDR_LOW 0x0e4 /* Low 32bits MAC address */ 39 #define FEC_ADDR_HIGH 0x0e8 /* High 16bits MAC address */ 40 #define FEC_OPD 0x0ec /* Opcode + Pause duration */ 41 #define FEC_TXIC0 0x0f0 /* Tx Interrupt Coalescing for ring 0 */ 42 #define FEC_TXIC1 0x0f4 /* Tx Interrupt Coalescing for ring 1 */ 43 #define FEC_TXIC2 0x0f8 /* Tx Interrupt Coalescing for ring 2 */ 44 #define FEC_RXIC0 0x100 /* Rx Interrupt Coalescing for ring 0 */ 45 #define FEC_RXIC1 0x104 /* Rx Interrupt Coalescing for ring 1 */ 46 #define FEC_RXIC2 0x108 /* Rx Interrupt Coalescing for ring 2 */ 47 #define FEC_HASH_TABLE_HIGH 0x118 /* High 32bits hash table */ 48 #define FEC_HASH_TABLE_LOW 0x11c /* Low 32bits hash table */ 49 #define FEC_GRP_HASH_TABLE_HIGH 0x120 /* High 32bits hash table */ 50 #define FEC_GRP_HASH_TABLE_LOW 0x124 /* Low 32bits hash table */ 51 #define FEC_X_WMRK 0x144 /* FIFO transmit water mark */ 52 #define FEC_R_BOUND 0x14c /* FIFO receive bound reg */ 53 #define FEC_R_FSTART 0x150 /* FIFO receive start reg */ 54 #define FEC_R_DES_START_1 0x160 /* Receive descriptor ring 1 */ 55 #define FEC_X_DES_START_1 0x164 /* Transmit descriptor ring 1 */ 56 #define FEC_R_BUFF_SIZE_1 0x168 /* Maximum receive buff ring1 size */ 57 #define FEC_R_DES_START_2 0x16c /* Receive descriptor ring 2 */ 58 #define FEC_X_DES_START_2 0x170 /* Transmit descriptor ring 2 */ 59 #define FEC_R_BUFF_SIZE_2 0x174 /* Maximum receive buff ring2 size */ 60 #define FEC_R_DES_START_0 0x180 /* Receive descriptor ring */ 61 #define FEC_X_DES_START_0 0x184 /* Transmit descriptor ring */ 62 #define FEC_R_BUFF_SIZE_0 0x188 /* Maximum receive buff size */ 63 #define FEC_R_FIFO_RSFL 0x190 /* Receive FIFO section full threshold */ 64 #define FEC_R_FIFO_RSEM 0x194 /* Receive FIFO section empty threshold */ 65 #define FEC_R_FIFO_RAEM 0x198 /* Receive FIFO almost empty threshold */ 66 #define FEC_R_FIFO_RAFL 0x19c /* Receive FIFO almost full threshold */ 67 #define FEC_FTRL 0x1b0 /* Frame truncation receive length*/ 68 #define FEC_RACC 0x1c4 /* Receive Accelerator function */ 69 #define FEC_RCMR_1 0x1c8 /* Receive classification match ring 1 */ 70 #define FEC_RCMR_2 0x1cc /* Receive classification match ring 2 */ 71 #define FEC_DMA_CFG_1 0x1d8 /* DMA class configuration for ring 1 */ 72 #define FEC_DMA_CFG_2 0x1dc /* DMA class Configuration for ring 2 */ 73 #define FEC_R_DES_ACTIVE_1 0x1e0 /* Rx descriptor active for ring 1 */ 74 #define FEC_X_DES_ACTIVE_1 0x1e4 /* Tx descriptor active for ring 1 */ 75 #define FEC_R_DES_ACTIVE_2 0x1e8 /* Rx descriptor active for ring 2 */ 76 #define FEC_X_DES_ACTIVE_2 0x1ec /* Tx descriptor active for ring 2 */ 77 #define FEC_QOS_SCHEME 0x1f0 /* Set multi queues Qos scheme */ 78 #define FEC_MIIGSK_CFGR 0x300 /* MIIGSK Configuration reg */ 79 #define FEC_MIIGSK_ENR 0x308 /* MIIGSK Enable reg */ 80 81 #define BM_MIIGSK_CFGR_MII 0x00 82 #define BM_MIIGSK_CFGR_RMII 0x01 83 #define BM_MIIGSK_CFGR_FRCONT_10M 0x40 84 85 #define RMON_T_DROP 0x200 /* Count of frames not cntd correctly */ 86 #define RMON_T_PACKETS 0x204 /* RMON TX packet count */ 87 #define RMON_T_BC_PKT 0x208 /* RMON TX broadcast pkts */ 88 #define RMON_T_MC_PKT 0x20c /* RMON TX multicast pkts */ 89 #define RMON_T_CRC_ALIGN 0x210 /* RMON TX pkts with CRC align err */ 90 #define RMON_T_UNDERSIZE 0x214 /* RMON TX pkts < 64 bytes, good CRC */ 91 #define RMON_T_OVERSIZE 0x218 /* RMON TX pkts > MAX_FL bytes good CRC */ 92 #define RMON_T_FRAG 0x21c /* RMON TX pkts < 64 bytes, bad CRC */ 93 #define RMON_T_JAB 0x220 /* RMON TX pkts > MAX_FL bytes, bad CRC */ 94 #define RMON_T_COL 0x224 /* RMON TX collision count */ 95 #define RMON_T_P64 0x228 /* RMON TX 64 byte pkts */ 96 #define RMON_T_P65TO127 0x22c /* RMON TX 65 to 127 byte pkts */ 97 #define RMON_T_P128TO255 0x230 /* RMON TX 128 to 255 byte pkts */ 98 #define RMON_T_P256TO511 0x234 /* RMON TX 256 to 511 byte pkts */ 99 #define RMON_T_P512TO1023 0x238 /* RMON TX 512 to 1023 byte pkts */ 100 #define RMON_T_P1024TO2047 0x23c /* RMON TX 1024 to 2047 byte pkts */ 101 #define RMON_T_P_GTE2048 0x240 /* RMON TX pkts > 2048 bytes */ 102 #define RMON_T_OCTETS 0x244 /* RMON TX octets */ 103 #define IEEE_T_DROP 0x248 /* Count of frames not counted crtly */ 104 #define IEEE_T_FRAME_OK 0x24c /* Frames tx'd OK */ 105 #define IEEE_T_1COL 0x250 /* Frames tx'd with single collision */ 106 #define IEEE_T_MCOL 0x254 /* Frames tx'd with multiple collision */ 107 #define IEEE_T_DEF 0x258 /* Frames tx'd after deferral delay */ 108 #define IEEE_T_LCOL 0x25c /* Frames tx'd with late collision */ 109 #define IEEE_T_EXCOL 0x260 /* Frames tx'd with excesv collisions */ 110 #define IEEE_T_MACERR 0x264 /* Frames tx'd with TX FIFO underrun */ 111 #define IEEE_T_CSERR 0x268 /* Frames tx'd with carrier sense err */ 112 #define IEEE_T_SQE 0x26c /* Frames tx'd with SQE err */ 113 #define IEEE_T_FDXFC 0x270 /* Flow control pause frames tx'd */ 114 #define IEEE_T_OCTETS_OK 0x274 /* Octet count for frames tx'd w/o err */ 115 #define RMON_R_PACKETS 0x284 /* RMON RX packet count */ 116 #define RMON_R_BC_PKT 0x288 /* RMON RX broadcast pkts */ 117 #define RMON_R_MC_PKT 0x28c /* RMON RX multicast pkts */ 118 #define RMON_R_CRC_ALIGN 0x290 /* RMON RX pkts with CRC alignment err */ 119 #define RMON_R_UNDERSIZE 0x294 /* RMON RX pkts < 64 bytes, good CRC */ 120 #define RMON_R_OVERSIZE 0x298 /* RMON RX pkts > MAX_FL bytes good CRC */ 121 #define RMON_R_FRAG 0x29c /* RMON RX pkts < 64 bytes, bad CRC */ 122 #define RMON_R_JAB 0x2a0 /* RMON RX pkts > MAX_FL bytes, bad CRC */ 123 #define RMON_R_RESVD_O 0x2a4 /* Reserved */ 124 #define RMON_R_P64 0x2a8 /* RMON RX 64 byte pkts */ 125 #define RMON_R_P65TO127 0x2ac /* RMON RX 65 to 127 byte pkts */ 126 #define RMON_R_P128TO255 0x2b0 /* RMON RX 128 to 255 byte pkts */ 127 #define RMON_R_P256TO511 0x2b4 /* RMON RX 256 to 511 byte pkts */ 128 #define RMON_R_P512TO1023 0x2b8 /* RMON RX 512 to 1023 byte pkts */ 129 #define RMON_R_P1024TO2047 0x2bc /* RMON RX 1024 to 2047 byte pkts */ 130 #define RMON_R_P_GTE2048 0x2c0 /* RMON RX pkts > 2048 bytes */ 131 #define RMON_R_OCTETS 0x2c4 /* RMON RX octets */ 132 #define IEEE_R_DROP 0x2c8 /* Count frames not counted correctly */ 133 #define IEEE_R_FRAME_OK 0x2cc /* Frames rx'd OK */ 134 #define IEEE_R_CRC 0x2d0 /* Frames rx'd with CRC err */ 135 #define IEEE_R_ALIGN 0x2d4 /* Frames rx'd with alignment err */ 136 #define IEEE_R_MACERR 0x2d8 /* Receive FIFO overflow count */ 137 #define IEEE_R_FDXFC 0x2dc /* Flow control pause frames rx'd */ 138 #define IEEE_R_OCTETS_OK 0x2e0 /* Octet cnt for frames rx'd w/o err */ 139 140 #else 141 142 #define FEC_ECNTRL 0x000 /* Ethernet control reg */ 143 #define FEC_IEVENT 0x004 /* Interrupt even reg */ 144 #define FEC_IMASK 0x008 /* Interrupt mask reg */ 145 #define FEC_IVEC 0x00c /* Interrupt vec status reg */ 146 #define FEC_R_DES_ACTIVE_0 0x010 /* Receive descriptor reg */ 147 #define FEC_R_DES_ACTIVE_1 FEC_R_DES_ACTIVE_0 148 #define FEC_R_DES_ACTIVE_2 FEC_R_DES_ACTIVE_0 149 #define FEC_X_DES_ACTIVE_0 0x014 /* Transmit descriptor reg */ 150 #define FEC_X_DES_ACTIVE_1 FEC_X_DES_ACTIVE_0 151 #define FEC_X_DES_ACTIVE_2 FEC_X_DES_ACTIVE_0 152 #define FEC_MII_DATA 0x040 /* MII manage frame reg */ 153 #define FEC_MII_SPEED 0x044 /* MII speed control reg */ 154 #define FEC_R_BOUND 0x08c /* FIFO receive bound reg */ 155 #define FEC_R_FSTART 0x090 /* FIFO receive start reg */ 156 #define FEC_X_WMRK 0x0a4 /* FIFO transmit water mark */ 157 #define FEC_X_FSTART 0x0ac /* FIFO transmit start reg */ 158 #define FEC_R_CNTRL 0x104 /* Receive control reg */ 159 #define FEC_MAX_FRM_LEN 0x108 /* Maximum frame length reg */ 160 #define FEC_X_CNTRL 0x144 /* Transmit Control reg */ 161 #define FEC_ADDR_LOW 0x3c0 /* Low 32bits MAC address */ 162 #define FEC_ADDR_HIGH 0x3c4 /* High 16bits MAC address */ 163 #define FEC_GRP_HASH_TABLE_HIGH 0x3c8 /* High 32bits hash table */ 164 #define FEC_GRP_HASH_TABLE_LOW 0x3cc /* Low 32bits hash table */ 165 #define FEC_R_DES_START_0 0x3d0 /* Receive descriptor ring */ 166 #define FEC_R_DES_START_1 FEC_R_DES_START_0 167 #define FEC_R_DES_START_2 FEC_R_DES_START_0 168 #define FEC_X_DES_START_0 0x3d4 /* Transmit descriptor ring */ 169 #define FEC_X_DES_START_1 FEC_X_DES_START_0 170 #define FEC_X_DES_START_2 FEC_X_DES_START_0 171 #define FEC_R_BUFF_SIZE_0 0x3d8 /* Maximum receive buff size */ 172 #define FEC_R_BUFF_SIZE_1 FEC_R_BUFF_SIZE_0 173 #define FEC_R_BUFF_SIZE_2 FEC_R_BUFF_SIZE_0 174 #define FEC_FIFO_RAM 0x400 /* FIFO RAM buffer */ 175 /* Not existed in real chip 176 * Just for pass build. 177 */ 178 #define FEC_RCMR_1 0xfff 179 #define FEC_RCMR_2 0xfff 180 #define FEC_DMA_CFG_1 0xfff 181 #define FEC_DMA_CFG_2 0xfff 182 #define FEC_TXIC0 0xfff 183 #define FEC_TXIC1 0xfff 184 #define FEC_TXIC2 0xfff 185 #define FEC_RXIC0 0xfff 186 #define FEC_RXIC1 0xfff 187 #define FEC_RXIC2 0xfff 188 #endif /* CONFIG_M5272 */ 189 190 191 /* 192 * Define the buffer descriptor structure. 193 * 194 * Evidently, ARM SoCs have the FEC block generated in a 195 * little endian mode so adjust endianness accordingly. 196 */ 197 #if defined(CONFIG_ARM) 198 #define fec32_to_cpu le32_to_cpu 199 #define fec16_to_cpu le16_to_cpu 200 #define cpu_to_fec32 cpu_to_le32 201 #define cpu_to_fec16 cpu_to_le16 202 #define __fec32 __le32 203 #define __fec16 __le16 204 205 struct bufdesc { 206 __fec16 cbd_datlen; /* Data length */ 207 __fec16 cbd_sc; /* Control and status info */ 208 __fec32 cbd_bufaddr; /* Buffer address */ 209 }; 210 #else 211 #define fec32_to_cpu be32_to_cpu 212 #define fec16_to_cpu be16_to_cpu 213 #define cpu_to_fec32 cpu_to_be32 214 #define cpu_to_fec16 cpu_to_be16 215 #define __fec32 __be32 216 #define __fec16 __be16 217 218 struct bufdesc { 219 __fec16 cbd_sc; /* Control and status info */ 220 __fec16 cbd_datlen; /* Data length */ 221 __fec32 cbd_bufaddr; /* Buffer address */ 222 }; 223 #endif 224 225 struct bufdesc_ex { 226 struct bufdesc desc; 227 __fec32 cbd_esc; 228 __fec32 cbd_prot; 229 __fec32 cbd_bdu; 230 __fec32 ts; 231 __fec16 res0[4]; 232 }; 233 234 /* 235 * The following definitions courtesy of commproc.h, which where 236 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net). 237 */ 238 #define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */ 239 #define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ 240 #define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */ 241 #define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ 242 #define BD_SC_CM ((ushort)0x0200) /* Continuous mode */ 243 #define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */ 244 #define BD_SC_P ((ushort)0x0100) /* xmt preamble */ 245 #define BD_SC_BR ((ushort)0x0020) /* Break received */ 246 #define BD_SC_FR ((ushort)0x0010) /* Framing error */ 247 #define BD_SC_PR ((ushort)0x0008) /* Parity error */ 248 #define BD_SC_OV ((ushort)0x0002) /* Overrun */ 249 #define BD_SC_CD ((ushort)0x0001) /* ?? */ 250 251 /* Buffer descriptor control/status used by Ethernet receive. 252 */ 253 #define BD_ENET_RX_EMPTY ((ushort)0x8000) 254 #define BD_ENET_RX_WRAP ((ushort)0x2000) 255 #define BD_ENET_RX_INTR ((ushort)0x1000) 256 #define BD_ENET_RX_LAST ((ushort)0x0800) 257 #define BD_ENET_RX_FIRST ((ushort)0x0400) 258 #define BD_ENET_RX_MISS ((ushort)0x0100) 259 #define BD_ENET_RX_LG ((ushort)0x0020) 260 #define BD_ENET_RX_NO ((ushort)0x0010) 261 #define BD_ENET_RX_SH ((ushort)0x0008) 262 #define BD_ENET_RX_CR ((ushort)0x0004) 263 #define BD_ENET_RX_OV ((ushort)0x0002) 264 #define BD_ENET_RX_CL ((ushort)0x0001) 265 #define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */ 266 267 /* Enhanced buffer descriptor control/status used by Ethernet receive */ 268 #define BD_ENET_RX_VLAN 0x00000004 269 270 /* Buffer descriptor control/status used by Ethernet transmit. 271 */ 272 #define BD_ENET_TX_READY ((ushort)0x8000) 273 #define BD_ENET_TX_PAD ((ushort)0x4000) 274 #define BD_ENET_TX_WRAP ((ushort)0x2000) 275 #define BD_ENET_TX_INTR ((ushort)0x1000) 276 #define BD_ENET_TX_LAST ((ushort)0x0800) 277 #define BD_ENET_TX_TC ((ushort)0x0400) 278 #define BD_ENET_TX_DEF ((ushort)0x0200) 279 #define BD_ENET_TX_HB ((ushort)0x0100) 280 #define BD_ENET_TX_LC ((ushort)0x0080) 281 #define BD_ENET_TX_RL ((ushort)0x0040) 282 #define BD_ENET_TX_RCMASK ((ushort)0x003c) 283 #define BD_ENET_TX_UN ((ushort)0x0002) 284 #define BD_ENET_TX_CSL ((ushort)0x0001) 285 #define BD_ENET_TX_STATS ((ushort)0x0fff) /* All status bits */ 286 287 /* enhanced buffer descriptor control/status used by Ethernet transmit */ 288 #define BD_ENET_TX_INT 0x40000000 289 #define BD_ENET_TX_TS 0x20000000 290 #define BD_ENET_TX_PINS 0x10000000 291 #define BD_ENET_TX_IINS 0x08000000 292 293 294 /* This device has up to three irqs on some platforms */ 295 #define FEC_IRQ_NUM 3 296 297 /* Maximum number of queues supported 298 * ENET with AVB IP can support up to 3 independent tx queues and rx queues. 299 * User can point the queue number that is less than or equal to 3. 300 */ 301 #define FEC_ENET_MAX_TX_QS 3 302 #define FEC_ENET_MAX_RX_QS 3 303 304 #define FEC_R_DES_START(X) (((X) == 1) ? FEC_R_DES_START_1 : \ 305 (((X) == 2) ? \ 306 FEC_R_DES_START_2 : FEC_R_DES_START_0)) 307 #define FEC_X_DES_START(X) (((X) == 1) ? FEC_X_DES_START_1 : \ 308 (((X) == 2) ? \ 309 FEC_X_DES_START_2 : FEC_X_DES_START_0)) 310 #define FEC_R_BUFF_SIZE(X) (((X) == 1) ? FEC_R_BUFF_SIZE_1 : \ 311 (((X) == 2) ? \ 312 FEC_R_BUFF_SIZE_2 : FEC_R_BUFF_SIZE_0)) 313 314 #define FEC_DMA_CFG(X) (((X) == 2) ? FEC_DMA_CFG_2 : FEC_DMA_CFG_1) 315 316 #define DMA_CLASS_EN (1 << 16) 317 #define FEC_RCMR(X) (((X) == 2) ? FEC_RCMR_2 : FEC_RCMR_1) 318 #define IDLE_SLOPE_MASK 0xffff 319 #define IDLE_SLOPE_1 0x200 /* BW fraction: 0.5 */ 320 #define IDLE_SLOPE_2 0x200 /* BW fraction: 0.5 */ 321 #define IDLE_SLOPE(X) (((X) == 1) ? \ 322 (IDLE_SLOPE_1 & IDLE_SLOPE_MASK) : \ 323 (IDLE_SLOPE_2 & IDLE_SLOPE_MASK)) 324 #define RCMR_MATCHEN (0x1 << 16) 325 #define RCMR_CMP_CFG(v, n) (((v) & 0x7) << (n << 2)) 326 #define RCMR_CMP_1 (RCMR_CMP_CFG(0, 0) | RCMR_CMP_CFG(1, 1) | \ 327 RCMR_CMP_CFG(2, 2) | RCMR_CMP_CFG(3, 3)) 328 #define RCMR_CMP_2 (RCMR_CMP_CFG(4, 0) | RCMR_CMP_CFG(5, 1) | \ 329 RCMR_CMP_CFG(6, 2) | RCMR_CMP_CFG(7, 3)) 330 #define RCMR_CMP(X) (((X) == 1) ? RCMR_CMP_1 : RCMR_CMP_2) 331 #define FEC_TX_BD_FTYPE(X) (((X) & 0xf) << 20) 332 333 /* The number of Tx and Rx buffers. These are allocated from the page 334 * pool. The code may assume these are power of two, so it it best 335 * to keep them that size. 336 * We don't need to allocate pages for the transmitter. We just use 337 * the skbuffer directly. 338 */ 339 340 #define FEC_ENET_RX_PAGES 256 341 #define FEC_ENET_RX_FRSIZE 2048 342 #define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE) 343 #define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES) 344 #define FEC_ENET_TX_FRSIZE 2048 345 #define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE) 346 #define TX_RING_SIZE 512 /* Must be power of two */ 347 #define TX_RING_MOD_MASK 511 /* for this to work */ 348 349 #define BD_ENET_RX_INT 0x00800000 350 #define BD_ENET_RX_PTP ((ushort)0x0400) 351 #define BD_ENET_RX_ICE 0x00000020 352 #define BD_ENET_RX_PCR 0x00000010 353 #define FLAG_RX_CSUM_ENABLED (BD_ENET_RX_ICE | BD_ENET_RX_PCR) 354 #define FLAG_RX_CSUM_ERROR (BD_ENET_RX_ICE | BD_ENET_RX_PCR) 355 356 /* Interrupt events/masks. */ 357 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */ 358 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */ 359 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */ 360 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */ 361 #define FEC_ENET_TXF_0 ((uint)0x08000000) /* Full frame transmitted */ 362 #define FEC_ENET_TXF_1 ((uint)0x00000008) /* Full frame transmitted */ 363 #define FEC_ENET_TXF_2 ((uint)0x00000080) /* Full frame transmitted */ 364 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */ 365 #define FEC_ENET_RXF_0 ((uint)0x02000000) /* Full frame received */ 366 #define FEC_ENET_RXF_1 ((uint)0x00000002) /* Full frame received */ 367 #define FEC_ENET_RXF_2 ((uint)0x00000020) /* Full frame received */ 368 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */ 369 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */ 370 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */ 371 #define FEC_ENET_WAKEUP ((uint)0x00020000) /* Wakeup request */ 372 #define FEC_ENET_TXF (FEC_ENET_TXF_0 | FEC_ENET_TXF_1 | FEC_ENET_TXF_2) 373 #define FEC_ENET_RXF (FEC_ENET_RXF_0 | FEC_ENET_RXF_1 | FEC_ENET_RXF_2) 374 #define FEC_ENET_TS_AVAIL ((uint)0x00010000) 375 #define FEC_ENET_TS_TIMER ((uint)0x00008000) 376 377 #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII | FEC_ENET_TS_TIMER) 378 #define FEC_NAPI_IMASK (FEC_ENET_MII | FEC_ENET_TS_TIMER) 379 #define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF)) 380 381 /* ENET interrupt coalescing macro define */ 382 #define FEC_ITR_CLK_SEL (0x1 << 30) 383 #define FEC_ITR_EN (0x1 << 31) 384 #define FEC_ITR_ICFT(X) (((X) & 0xff) << 20) 385 #define FEC_ITR_ICTT(X) ((X) & 0xffff) 386 #define FEC_ITR_ICFT_DEFAULT 200 /* Set 200 frame count threshold */ 387 #define FEC_ITR_ICTT_DEFAULT 1000 /* Set 1000us timer threshold */ 388 389 #define FEC_VLAN_TAG_LEN 0x04 390 #define FEC_ETHTYPE_LEN 0x02 391 392 /* Controller is ENET-MAC */ 393 #define FEC_QUIRK_ENET_MAC (1 << 0) 394 /* Controller needs driver to swap frame */ 395 #define FEC_QUIRK_SWAP_FRAME (1 << 1) 396 /* Controller uses gasket */ 397 #define FEC_QUIRK_USE_GASKET (1 << 2) 398 /* Controller has GBIT support */ 399 #define FEC_QUIRK_HAS_GBIT (1 << 3) 400 /* Controller has extend desc buffer */ 401 #define FEC_QUIRK_HAS_BUFDESC_EX (1 << 4) 402 /* Controller has hardware checksum support */ 403 #define FEC_QUIRK_HAS_CSUM (1 << 5) 404 /* Controller has hardware vlan support */ 405 #define FEC_QUIRK_HAS_VLAN (1 << 6) 406 /* ENET IP errata ERR006358 407 * 408 * If the ready bit in the transmit buffer descriptor (TxBD[R]) is previously 409 * detected as not set during a prior frame transmission, then the 410 * ENET_TDAR[TDAR] bit is cleared at a later time, even if additional TxBDs 411 * were added to the ring and the ENET_TDAR[TDAR] bit is set. This results in 412 * frames not being transmitted until there is a 0-to-1 transition on 413 * ENET_TDAR[TDAR]. 414 */ 415 #define FEC_QUIRK_ERR006358 (1 << 7) 416 /* ENET IP hw AVB 417 * 418 * i.MX6SX ENET IP add Audio Video Bridging (AVB) feature support. 419 * - Two class indicators on receive with configurable priority 420 * - Two class indicators and line speed timer on transmit allowing 421 * implementation class credit based shapers externally 422 * - Additional DMA registers provisioned to allow managing up to 3 423 * independent rings 424 */ 425 #define FEC_QUIRK_HAS_AVB (1 << 8) 426 /* There is a TDAR race condition for mutliQ when the software sets TDAR 427 * and the UDMA clears TDAR simultaneously or in a small window (2-4 cycles). 428 * This will cause the udma_tx and udma_tx_arbiter state machines to hang. 429 * The issue exist at i.MX6SX enet IP. 430 */ 431 #define FEC_QUIRK_ERR007885 (1 << 9) 432 /* ENET Block Guide/ Chapter for the iMX6SX (PELE) address one issue: 433 * After set ENET_ATCR[Capture], there need some time cycles before the counter 434 * value is capture in the register clock domain. 435 * The wait-time-cycles is at least 6 clock cycles of the slower clock between 436 * the register clock and the 1588 clock. The 1588 ts_clk is fixed to 25Mhz, 437 * register clock is 66Mhz, so the wait-time-cycles must be greater than 240ns 438 * (40ns * 6). 439 */ 440 #define FEC_QUIRK_BUG_CAPTURE (1 << 10) 441 /* Controller has only one MDIO bus */ 442 #define FEC_QUIRK_SINGLE_MDIO (1 << 11) 443 /* Controller supports RACC register */ 444 #define FEC_QUIRK_HAS_RACC (1 << 12) 445 /* Controller supports interrupt coalesc */ 446 #define FEC_QUIRK_HAS_COALESCE (1 << 13) 447 /* Interrupt doesn't wake CPU from deep idle */ 448 #define FEC_QUIRK_ERR006687 (1 << 14) 449 450 struct bufdesc_prop { 451 int qid; 452 /* Address of Rx and Tx buffers */ 453 struct bufdesc *base; 454 struct bufdesc *last; 455 struct bufdesc *cur; 456 void __iomem *reg_desc_active; 457 dma_addr_t dma; 458 unsigned short ring_size; 459 unsigned char dsize; 460 unsigned char dsize_log2; 461 }; 462 463 struct fec_enet_priv_tx_q { 464 struct bufdesc_prop bd; 465 unsigned char *tx_bounce[TX_RING_SIZE]; 466 struct sk_buff *tx_skbuff[TX_RING_SIZE]; 467 468 unsigned short tx_stop_threshold; 469 unsigned short tx_wake_threshold; 470 471 struct bufdesc *dirty_tx; 472 char *tso_hdrs; 473 dma_addr_t tso_hdrs_dma; 474 }; 475 476 struct fec_enet_priv_rx_q { 477 struct bufdesc_prop bd; 478 struct sk_buff *rx_skbuff[RX_RING_SIZE]; 479 }; 480 481 /* The FEC buffer descriptors track the ring buffers. The rx_bd_base and 482 * tx_bd_base always point to the base of the buffer descriptors. The 483 * cur_rx and cur_tx point to the currently available buffer. 484 * The dirty_tx tracks the current buffer that is being sent by the 485 * controller. The cur_tx and dirty_tx are equal under both completely 486 * empty and completely full conditions. The empty/ready indicator in 487 * the buffer descriptor determines the actual condition. 488 */ 489 struct fec_enet_private { 490 /* Hardware registers of the FEC device */ 491 void __iomem *hwp; 492 493 struct net_device *netdev; 494 495 struct clk *clk_ipg; 496 struct clk *clk_ahb; 497 struct clk *clk_ref; 498 struct clk *clk_enet_out; 499 struct clk *clk_ptp; 500 501 bool ptp_clk_on; 502 struct mutex ptp_clk_mutex; 503 unsigned int num_tx_queues; 504 unsigned int num_rx_queues; 505 506 /* The saved address of a sent-in-place packet/buffer, for skfree(). */ 507 struct fec_enet_priv_tx_q *tx_queue[FEC_ENET_MAX_TX_QS]; 508 struct fec_enet_priv_rx_q *rx_queue[FEC_ENET_MAX_RX_QS]; 509 510 unsigned int total_tx_ring_size; 511 unsigned int total_rx_ring_size; 512 513 unsigned long work_tx; 514 unsigned long work_rx; 515 unsigned long work_ts; 516 unsigned long work_mdio; 517 518 struct platform_device *pdev; 519 520 int dev_id; 521 522 /* Phylib and MDIO interface */ 523 struct mii_bus *mii_bus; 524 int mii_timeout; 525 uint phy_speed; 526 phy_interface_t phy_interface; 527 struct device_node *phy_node; 528 int link; 529 int full_duplex; 530 int speed; 531 struct completion mdio_done; 532 int irq[FEC_IRQ_NUM]; 533 bool bufdesc_ex; 534 int pause_flag; 535 int wol_flag; 536 u32 quirks; 537 538 struct napi_struct napi; 539 int csum_flags; 540 541 struct work_struct tx_timeout_work; 542 543 struct ptp_clock *ptp_clock; 544 struct ptp_clock_info ptp_caps; 545 unsigned long last_overflow_check; 546 spinlock_t tmreg_lock; 547 struct cyclecounter cc; 548 struct timecounter tc; 549 int rx_hwtstamp_filter; 550 u32 base_incval; 551 u32 cycle_speed; 552 int hwts_rx_en; 553 int hwts_tx_en; 554 struct delayed_work time_keep; 555 struct regulator *reg_phy; 556 557 unsigned int tx_align; 558 unsigned int rx_align; 559 560 /* hw interrupt coalesce */ 561 unsigned int rx_pkts_itr; 562 unsigned int rx_time_itr; 563 unsigned int tx_pkts_itr; 564 unsigned int tx_time_itr; 565 unsigned int itr_clk_rate; 566 567 u32 rx_copybreak; 568 569 /* ptp clock period in ns*/ 570 unsigned int ptp_inc; 571 572 /* pps */ 573 int pps_channel; 574 unsigned int reload_period; 575 int pps_enable; 576 unsigned int next_counter; 577 }; 578 579 void fec_ptp_init(struct platform_device *pdev); 580 void fec_ptp_stop(struct platform_device *pdev); 581 void fec_ptp_start_cyclecounter(struct net_device *ndev); 582 int fec_ptp_set(struct net_device *ndev, struct ifreq *ifr); 583 int fec_ptp_get(struct net_device *ndev, struct ifreq *ifr); 584 uint fec_ptp_check_pps_event(struct fec_enet_private *fep); 585 586 /****************************************************************************/ 587 #endif /* FEC_H */ 588