1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2 /* Copyright 2017-2019 NXP */ 3 4 #include <linux/mdio.h> 5 #include <linux/module.h> 6 #include <linux/fsl/enetc_mdio.h> 7 #include <linux/of_mdio.h> 8 #include <linux/of_net.h> 9 #include "enetc_pf.h" 10 11 #define ENETC_DRV_NAME_STR "ENETC PF driver" 12 13 static void enetc_pf_get_primary_mac_addr(struct enetc_hw *hw, int si, u8 *addr) 14 { 15 u32 upper = __raw_readl(hw->port + ENETC_PSIPMAR0(si)); 16 u16 lower = __raw_readw(hw->port + ENETC_PSIPMAR1(si)); 17 18 *(u32 *)addr = upper; 19 *(u16 *)(addr + 4) = lower; 20 } 21 22 static void enetc_pf_set_primary_mac_addr(struct enetc_hw *hw, int si, 23 const u8 *addr) 24 { 25 u32 upper = *(const u32 *)addr; 26 u16 lower = *(const u16 *)(addr + 4); 27 28 __raw_writel(upper, hw->port + ENETC_PSIPMAR0(si)); 29 __raw_writew(lower, hw->port + ENETC_PSIPMAR1(si)); 30 } 31 32 static int enetc_pf_set_mac_addr(struct net_device *ndev, void *addr) 33 { 34 struct enetc_ndev_priv *priv = netdev_priv(ndev); 35 struct sockaddr *saddr = addr; 36 37 if (!is_valid_ether_addr(saddr->sa_data)) 38 return -EADDRNOTAVAIL; 39 40 memcpy(ndev->dev_addr, saddr->sa_data, ndev->addr_len); 41 enetc_pf_set_primary_mac_addr(&priv->si->hw, 0, saddr->sa_data); 42 43 return 0; 44 } 45 46 static void enetc_set_vlan_promisc(struct enetc_hw *hw, char si_map) 47 { 48 u32 val = enetc_port_rd(hw, ENETC_PSIPVMR); 49 50 val &= ~ENETC_PSIPVMR_SET_VP(ENETC_VLAN_PROMISC_MAP_ALL); 51 enetc_port_wr(hw, ENETC_PSIPVMR, ENETC_PSIPVMR_SET_VP(si_map) | val); 52 } 53 54 static void enetc_enable_si_vlan_promisc(struct enetc_pf *pf, int si_idx) 55 { 56 pf->vlan_promisc_simap |= BIT(si_idx); 57 enetc_set_vlan_promisc(&pf->si->hw, pf->vlan_promisc_simap); 58 } 59 60 static void enetc_disable_si_vlan_promisc(struct enetc_pf *pf, int si_idx) 61 { 62 pf->vlan_promisc_simap &= ~BIT(si_idx); 63 enetc_set_vlan_promisc(&pf->si->hw, pf->vlan_promisc_simap); 64 } 65 66 static void enetc_set_isol_vlan(struct enetc_hw *hw, int si, u16 vlan, u8 qos) 67 { 68 u32 val = 0; 69 70 if (vlan) 71 val = ENETC_PSIVLAN_EN | ENETC_PSIVLAN_SET_QOS(qos) | vlan; 72 73 enetc_port_wr(hw, ENETC_PSIVLANR(si), val); 74 } 75 76 static int enetc_mac_addr_hash_idx(const u8 *addr) 77 { 78 u64 fold = __swab64(ether_addr_to_u64(addr)) >> 16; 79 u64 mask = 0; 80 int res = 0; 81 int i; 82 83 for (i = 0; i < 8; i++) 84 mask |= BIT_ULL(i * 6); 85 86 for (i = 0; i < 6; i++) 87 res |= (hweight64(fold & (mask << i)) & 0x1) << i; 88 89 return res; 90 } 91 92 static void enetc_reset_mac_addr_filter(struct enetc_mac_filter *filter) 93 { 94 filter->mac_addr_cnt = 0; 95 96 bitmap_zero(filter->mac_hash_table, 97 ENETC_MADDR_HASH_TBL_SZ); 98 } 99 100 static void enetc_add_mac_addr_em_filter(struct enetc_mac_filter *filter, 101 const unsigned char *addr) 102 { 103 /* add exact match addr */ 104 ether_addr_copy(filter->mac_addr, addr); 105 filter->mac_addr_cnt++; 106 } 107 108 static void enetc_add_mac_addr_ht_filter(struct enetc_mac_filter *filter, 109 const unsigned char *addr) 110 { 111 int idx = enetc_mac_addr_hash_idx(addr); 112 113 /* add hash table entry */ 114 __set_bit(idx, filter->mac_hash_table); 115 filter->mac_addr_cnt++; 116 } 117 118 static void enetc_clear_mac_ht_flt(struct enetc_si *si, int si_idx, int type) 119 { 120 bool err = si->errata & ENETC_ERR_UCMCSWP; 121 122 if (type == UC) { 123 enetc_port_wr(&si->hw, ENETC_PSIUMHFR0(si_idx, err), 0); 124 enetc_port_wr(&si->hw, ENETC_PSIUMHFR1(si_idx), 0); 125 } else { /* MC */ 126 enetc_port_wr(&si->hw, ENETC_PSIMMHFR0(si_idx, err), 0); 127 enetc_port_wr(&si->hw, ENETC_PSIMMHFR1(si_idx), 0); 128 } 129 } 130 131 static void enetc_set_mac_ht_flt(struct enetc_si *si, int si_idx, int type, 132 unsigned long hash) 133 { 134 bool err = si->errata & ENETC_ERR_UCMCSWP; 135 136 if (type == UC) { 137 enetc_port_wr(&si->hw, ENETC_PSIUMHFR0(si_idx, err), 138 lower_32_bits(hash)); 139 enetc_port_wr(&si->hw, ENETC_PSIUMHFR1(si_idx), 140 upper_32_bits(hash)); 141 } else { /* MC */ 142 enetc_port_wr(&si->hw, ENETC_PSIMMHFR0(si_idx, err), 143 lower_32_bits(hash)); 144 enetc_port_wr(&si->hw, ENETC_PSIMMHFR1(si_idx), 145 upper_32_bits(hash)); 146 } 147 } 148 149 static void enetc_sync_mac_filters(struct enetc_pf *pf) 150 { 151 struct enetc_mac_filter *f = pf->mac_filter; 152 struct enetc_si *si = pf->si; 153 int i, pos; 154 155 pos = EMETC_MAC_ADDR_FILT_RES; 156 157 for (i = 0; i < MADDR_TYPE; i++, f++) { 158 bool em = (f->mac_addr_cnt == 1) && (i == UC); 159 bool clear = !f->mac_addr_cnt; 160 161 if (clear) { 162 if (i == UC) 163 enetc_clear_mac_flt_entry(si, pos); 164 165 enetc_clear_mac_ht_flt(si, 0, i); 166 continue; 167 } 168 169 /* exact match filter */ 170 if (em) { 171 int err; 172 173 enetc_clear_mac_ht_flt(si, 0, UC); 174 175 err = enetc_set_mac_flt_entry(si, pos, f->mac_addr, 176 BIT(0)); 177 if (!err) 178 continue; 179 180 /* fallback to HT filtering */ 181 dev_warn(&si->pdev->dev, "fallback to HT filt (%d)\n", 182 err); 183 } 184 185 /* hash table filter, clear EM filter for UC entries */ 186 if (i == UC) 187 enetc_clear_mac_flt_entry(si, pos); 188 189 enetc_set_mac_ht_flt(si, 0, i, *f->mac_hash_table); 190 } 191 } 192 193 static void enetc_pf_set_rx_mode(struct net_device *ndev) 194 { 195 struct enetc_ndev_priv *priv = netdev_priv(ndev); 196 struct enetc_pf *pf = enetc_si_priv(priv->si); 197 struct enetc_hw *hw = &priv->si->hw; 198 bool uprom = false, mprom = false; 199 struct enetc_mac_filter *filter; 200 struct netdev_hw_addr *ha; 201 u32 psipmr = 0; 202 bool em; 203 204 if (ndev->flags & IFF_PROMISC) { 205 /* enable promisc mode for SI0 (PF) */ 206 psipmr = ENETC_PSIPMR_SET_UP(0) | ENETC_PSIPMR_SET_MP(0); 207 uprom = true; 208 mprom = true; 209 } else if (ndev->flags & IFF_ALLMULTI) { 210 /* enable multi cast promisc mode for SI0 (PF) */ 211 psipmr = ENETC_PSIPMR_SET_MP(0); 212 mprom = true; 213 } 214 215 /* first 2 filter entries belong to PF */ 216 if (!uprom) { 217 /* Update unicast filters */ 218 filter = &pf->mac_filter[UC]; 219 enetc_reset_mac_addr_filter(filter); 220 221 em = (netdev_uc_count(ndev) == 1); 222 netdev_for_each_uc_addr(ha, ndev) { 223 if (em) { 224 enetc_add_mac_addr_em_filter(filter, ha->addr); 225 break; 226 } 227 228 enetc_add_mac_addr_ht_filter(filter, ha->addr); 229 } 230 } 231 232 if (!mprom) { 233 /* Update multicast filters */ 234 filter = &pf->mac_filter[MC]; 235 enetc_reset_mac_addr_filter(filter); 236 237 netdev_for_each_mc_addr(ha, ndev) { 238 if (!is_multicast_ether_addr(ha->addr)) 239 continue; 240 241 enetc_add_mac_addr_ht_filter(filter, ha->addr); 242 } 243 } 244 245 if (!uprom || !mprom) 246 /* update PF entries */ 247 enetc_sync_mac_filters(pf); 248 249 psipmr |= enetc_port_rd(hw, ENETC_PSIPMR) & 250 ~(ENETC_PSIPMR_SET_UP(0) | ENETC_PSIPMR_SET_MP(0)); 251 enetc_port_wr(hw, ENETC_PSIPMR, psipmr); 252 } 253 254 static void enetc_set_vlan_ht_filter(struct enetc_hw *hw, int si_idx, 255 unsigned long hash) 256 { 257 enetc_port_wr(hw, ENETC_PSIVHFR0(si_idx), lower_32_bits(hash)); 258 enetc_port_wr(hw, ENETC_PSIVHFR1(si_idx), upper_32_bits(hash)); 259 } 260 261 static int enetc_vid_hash_idx(unsigned int vid) 262 { 263 int res = 0; 264 int i; 265 266 for (i = 0; i < 6; i++) 267 res |= (hweight8(vid & (BIT(i) | BIT(i + 6))) & 0x1) << i; 268 269 return res; 270 } 271 272 static void enetc_sync_vlan_ht_filter(struct enetc_pf *pf, bool rehash) 273 { 274 int i; 275 276 if (rehash) { 277 bitmap_zero(pf->vlan_ht_filter, ENETC_VLAN_HT_SIZE); 278 279 for_each_set_bit(i, pf->active_vlans, VLAN_N_VID) { 280 int hidx = enetc_vid_hash_idx(i); 281 282 __set_bit(hidx, pf->vlan_ht_filter); 283 } 284 } 285 286 enetc_set_vlan_ht_filter(&pf->si->hw, 0, *pf->vlan_ht_filter); 287 } 288 289 static int enetc_vlan_rx_add_vid(struct net_device *ndev, __be16 prot, u16 vid) 290 { 291 struct enetc_ndev_priv *priv = netdev_priv(ndev); 292 struct enetc_pf *pf = enetc_si_priv(priv->si); 293 int idx; 294 295 __set_bit(vid, pf->active_vlans); 296 297 idx = enetc_vid_hash_idx(vid); 298 if (!__test_and_set_bit(idx, pf->vlan_ht_filter)) 299 enetc_sync_vlan_ht_filter(pf, false); 300 301 return 0; 302 } 303 304 static int enetc_vlan_rx_del_vid(struct net_device *ndev, __be16 prot, u16 vid) 305 { 306 struct enetc_ndev_priv *priv = netdev_priv(ndev); 307 struct enetc_pf *pf = enetc_si_priv(priv->si); 308 309 __clear_bit(vid, pf->active_vlans); 310 enetc_sync_vlan_ht_filter(pf, true); 311 312 return 0; 313 } 314 315 static void enetc_set_loopback(struct net_device *ndev, bool en) 316 { 317 struct enetc_ndev_priv *priv = netdev_priv(ndev); 318 struct enetc_hw *hw = &priv->si->hw; 319 u32 reg; 320 321 reg = enetc_port_rd(hw, ENETC_PM0_IF_MODE); 322 if (reg & ENETC_PM0_IFM_RG) { 323 /* RGMII mode */ 324 reg = (reg & ~ENETC_PM0_IFM_RLP) | 325 (en ? ENETC_PM0_IFM_RLP : 0); 326 enetc_port_wr(hw, ENETC_PM0_IF_MODE, reg); 327 } else { 328 /* assume SGMII mode */ 329 reg = enetc_port_rd(hw, ENETC_PM0_CMD_CFG); 330 reg = (reg & ~ENETC_PM0_CMD_XGLP) | 331 (en ? ENETC_PM0_CMD_XGLP : 0); 332 reg = (reg & ~ENETC_PM0_CMD_PHY_TX_EN) | 333 (en ? ENETC_PM0_CMD_PHY_TX_EN : 0); 334 enetc_port_wr(hw, ENETC_PM0_CMD_CFG, reg); 335 enetc_port_wr(hw, ENETC_PM1_CMD_CFG, reg); 336 } 337 } 338 339 static int enetc_pf_set_vf_mac(struct net_device *ndev, int vf, u8 *mac) 340 { 341 struct enetc_ndev_priv *priv = netdev_priv(ndev); 342 struct enetc_pf *pf = enetc_si_priv(priv->si); 343 struct enetc_vf_state *vf_state; 344 345 if (vf >= pf->total_vfs) 346 return -EINVAL; 347 348 if (!is_valid_ether_addr(mac)) 349 return -EADDRNOTAVAIL; 350 351 vf_state = &pf->vf_state[vf]; 352 vf_state->flags |= ENETC_VF_FLAG_PF_SET_MAC; 353 enetc_pf_set_primary_mac_addr(&priv->si->hw, vf + 1, mac); 354 return 0; 355 } 356 357 static int enetc_pf_set_vf_vlan(struct net_device *ndev, int vf, u16 vlan, 358 u8 qos, __be16 proto) 359 { 360 struct enetc_ndev_priv *priv = netdev_priv(ndev); 361 struct enetc_pf *pf = enetc_si_priv(priv->si); 362 363 if (priv->si->errata & ENETC_ERR_VLAN_ISOL) 364 return -EOPNOTSUPP; 365 366 if (vf >= pf->total_vfs) 367 return -EINVAL; 368 369 if (proto != htons(ETH_P_8021Q)) 370 /* only C-tags supported for now */ 371 return -EPROTONOSUPPORT; 372 373 enetc_set_isol_vlan(&priv->si->hw, vf + 1, vlan, qos); 374 return 0; 375 } 376 377 static int enetc_pf_set_vf_spoofchk(struct net_device *ndev, int vf, bool en) 378 { 379 struct enetc_ndev_priv *priv = netdev_priv(ndev); 380 struct enetc_pf *pf = enetc_si_priv(priv->si); 381 u32 cfgr; 382 383 if (vf >= pf->total_vfs) 384 return -EINVAL; 385 386 cfgr = enetc_port_rd(&priv->si->hw, ENETC_PSICFGR0(vf + 1)); 387 cfgr = (cfgr & ~ENETC_PSICFGR0_ASE) | (en ? ENETC_PSICFGR0_ASE : 0); 388 enetc_port_wr(&priv->si->hw, ENETC_PSICFGR0(vf + 1), cfgr); 389 390 return 0; 391 } 392 393 static void enetc_port_setup_primary_mac_address(struct enetc_si *si) 394 { 395 unsigned char mac_addr[MAX_ADDR_LEN]; 396 struct enetc_pf *pf = enetc_si_priv(si); 397 struct enetc_hw *hw = &si->hw; 398 int i; 399 400 /* check MAC addresses for PF and all VFs, if any is 0 set it ro rand */ 401 for (i = 0; i < pf->total_vfs + 1; i++) { 402 enetc_pf_get_primary_mac_addr(hw, i, mac_addr); 403 if (!is_zero_ether_addr(mac_addr)) 404 continue; 405 eth_random_addr(mac_addr); 406 dev_info(&si->pdev->dev, "no MAC address specified for SI%d, using %pM\n", 407 i, mac_addr); 408 enetc_pf_set_primary_mac_addr(hw, i, mac_addr); 409 } 410 } 411 412 static void enetc_port_assign_rfs_entries(struct enetc_si *si) 413 { 414 struct enetc_pf *pf = enetc_si_priv(si); 415 struct enetc_hw *hw = &si->hw; 416 int num_entries, vf_entries, i; 417 u32 val; 418 419 /* split RFS entries between functions */ 420 val = enetc_port_rd(hw, ENETC_PRFSCAPR); 421 num_entries = ENETC_PRFSCAPR_GET_NUM_RFS(val); 422 vf_entries = num_entries / (pf->total_vfs + 1); 423 424 for (i = 0; i < pf->total_vfs; i++) 425 enetc_port_wr(hw, ENETC_PSIRFSCFGR(i + 1), vf_entries); 426 enetc_port_wr(hw, ENETC_PSIRFSCFGR(0), 427 num_entries - vf_entries * pf->total_vfs); 428 429 /* enable RFS on port */ 430 enetc_port_wr(hw, ENETC_PRFSMR, ENETC_PRFSMR_RFSE); 431 } 432 433 static void enetc_port_si_configure(struct enetc_si *si) 434 { 435 struct enetc_pf *pf = enetc_si_priv(si); 436 struct enetc_hw *hw = &si->hw; 437 int num_rings, i; 438 u32 val; 439 440 val = enetc_port_rd(hw, ENETC_PCAPR0); 441 num_rings = min(ENETC_PCAPR0_RXBDR(val), ENETC_PCAPR0_TXBDR(val)); 442 443 val = ENETC_PSICFGR0_SET_TXBDR(ENETC_PF_NUM_RINGS); 444 val |= ENETC_PSICFGR0_SET_RXBDR(ENETC_PF_NUM_RINGS); 445 446 if (unlikely(num_rings < ENETC_PF_NUM_RINGS)) { 447 val = ENETC_PSICFGR0_SET_TXBDR(num_rings); 448 val |= ENETC_PSICFGR0_SET_RXBDR(num_rings); 449 450 dev_warn(&si->pdev->dev, "Found %d rings, expected %d!\n", 451 num_rings, ENETC_PF_NUM_RINGS); 452 453 num_rings = 0; 454 } 455 456 /* Add default one-time settings for SI0 (PF) */ 457 val |= ENETC_PSICFGR0_SIVC(ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S); 458 459 enetc_port_wr(hw, ENETC_PSICFGR0(0), val); 460 461 if (num_rings) 462 num_rings -= ENETC_PF_NUM_RINGS; 463 464 /* Configure the SIs for each available VF */ 465 val = ENETC_PSICFGR0_SIVC(ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S); 466 val |= ENETC_PSICFGR0_VTE | ENETC_PSICFGR0_SIVIE; 467 468 if (num_rings) { 469 num_rings /= pf->total_vfs; 470 val |= ENETC_PSICFGR0_SET_TXBDR(num_rings); 471 val |= ENETC_PSICFGR0_SET_RXBDR(num_rings); 472 } 473 474 for (i = 0; i < pf->total_vfs; i++) 475 enetc_port_wr(hw, ENETC_PSICFGR0(i + 1), val); 476 477 /* Port level VLAN settings */ 478 val = ENETC_PVCLCTR_OVTPIDL(ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S); 479 enetc_port_wr(hw, ENETC_PVCLCTR, val); 480 /* use outer tag for VLAN filtering */ 481 enetc_port_wr(hw, ENETC_PSIVLANFMR, ENETC_PSIVLANFMR_VS); 482 } 483 484 static void enetc_configure_port_mac(struct enetc_hw *hw) 485 { 486 enetc_port_wr(hw, ENETC_PM0_MAXFRM, 487 ENETC_SET_MAXFRM(ENETC_RX_MAXFRM_SIZE)); 488 489 enetc_port_wr(hw, ENETC_PTCMSDUR(0), ENETC_MAC_MAXFRM_SIZE); 490 enetc_port_wr(hw, ENETC_PTXMBAR, 2 * ENETC_MAC_MAXFRM_SIZE); 491 492 enetc_port_wr(hw, ENETC_PM0_CMD_CFG, ENETC_PM0_CMD_PHY_TX_EN | 493 ENETC_PM0_CMD_TXP | ENETC_PM0_PROMISC); 494 495 enetc_port_wr(hw, ENETC_PM1_CMD_CFG, ENETC_PM0_CMD_PHY_TX_EN | 496 ENETC_PM0_CMD_TXP | ENETC_PM0_PROMISC); 497 498 /* On LS1028A, the MAC RX FIFO defaults to 2, which is too high 499 * and may lead to RX lock-up under traffic. Set it to 1 instead, 500 * as recommended by the hardware team. 501 */ 502 enetc_port_wr(hw, ENETC_PM0_RX_FIFO, ENETC_PM0_RX_FIFO_VAL); 503 } 504 505 static void enetc_mac_config(struct enetc_hw *hw, phy_interface_t phy_mode) 506 { 507 u32 val; 508 509 if (phy_interface_mode_is_rgmii(phy_mode)) { 510 val = enetc_port_rd(hw, ENETC_PM0_IF_MODE); 511 val &= ~ENETC_PM0_IFM_EN_AUTO; 512 val &= ENETC_PM0_IFM_IFMODE_MASK; 513 val |= ENETC_PM0_IFM_IFMODE_GMII | ENETC_PM0_IFM_RG; 514 enetc_port_wr(hw, ENETC_PM0_IF_MODE, val); 515 } 516 517 if (phy_mode == PHY_INTERFACE_MODE_USXGMII) { 518 val = ENETC_PM0_IFM_FULL_DPX | ENETC_PM0_IFM_IFMODE_XGMII; 519 enetc_port_wr(hw, ENETC_PM0_IF_MODE, val); 520 } 521 } 522 523 static void enetc_mac_enable(struct enetc_hw *hw, bool en) 524 { 525 u32 val = enetc_port_rd(hw, ENETC_PM0_CMD_CFG); 526 527 val &= ~(ENETC_PM0_TX_EN | ENETC_PM0_RX_EN); 528 val |= en ? (ENETC_PM0_TX_EN | ENETC_PM0_RX_EN) : 0; 529 530 enetc_port_wr(hw, ENETC_PM0_CMD_CFG, val); 531 enetc_port_wr(hw, ENETC_PM1_CMD_CFG, val); 532 } 533 534 static void enetc_configure_port_pmac(struct enetc_hw *hw) 535 { 536 u32 temp; 537 538 /* Set pMAC step lock */ 539 temp = enetc_port_rd(hw, ENETC_PFPMR); 540 enetc_port_wr(hw, ENETC_PFPMR, 541 temp | ENETC_PFPMR_PMACE | ENETC_PFPMR_MWLM); 542 543 temp = enetc_port_rd(hw, ENETC_MMCSR); 544 enetc_port_wr(hw, ENETC_MMCSR, temp | ENETC_MMCSR_ME); 545 } 546 547 static void enetc_configure_port(struct enetc_pf *pf) 548 { 549 u8 hash_key[ENETC_RSSHASH_KEY_SIZE]; 550 struct enetc_hw *hw = &pf->si->hw; 551 552 enetc_configure_port_pmac(hw); 553 554 enetc_configure_port_mac(hw); 555 556 enetc_port_si_configure(pf->si); 557 558 /* set up hash key */ 559 get_random_bytes(hash_key, ENETC_RSSHASH_KEY_SIZE); 560 enetc_set_rss_key(hw, hash_key); 561 562 /* split up RFS entries */ 563 enetc_port_assign_rfs_entries(pf->si); 564 565 /* fix-up primary MAC addresses, if not set already */ 566 enetc_port_setup_primary_mac_address(pf->si); 567 568 /* enforce VLAN promisc mode for all SIs */ 569 pf->vlan_promisc_simap = ENETC_VLAN_PROMISC_MAP_ALL; 570 enetc_set_vlan_promisc(hw, pf->vlan_promisc_simap); 571 572 enetc_port_wr(hw, ENETC_PSIPMR, 0); 573 574 /* enable port */ 575 enetc_port_wr(hw, ENETC_PMR, ENETC_PMR_EN); 576 } 577 578 /* Messaging */ 579 static u16 enetc_msg_pf_set_vf_primary_mac_addr(struct enetc_pf *pf, 580 int vf_id) 581 { 582 struct enetc_vf_state *vf_state = &pf->vf_state[vf_id]; 583 struct enetc_msg_swbd *msg = &pf->rxmsg[vf_id]; 584 struct enetc_msg_cmd_set_primary_mac *cmd; 585 struct device *dev = &pf->si->pdev->dev; 586 u16 cmd_id; 587 char *addr; 588 589 cmd = (struct enetc_msg_cmd_set_primary_mac *)msg->vaddr; 590 cmd_id = cmd->header.id; 591 if (cmd_id != ENETC_MSG_CMD_MNG_ADD) 592 return ENETC_MSG_CMD_STATUS_FAIL; 593 594 addr = cmd->mac.sa_data; 595 if (vf_state->flags & ENETC_VF_FLAG_PF_SET_MAC) 596 dev_warn(dev, "Attempt to override PF set mac addr for VF%d\n", 597 vf_id); 598 else 599 enetc_pf_set_primary_mac_addr(&pf->si->hw, vf_id + 1, addr); 600 601 return ENETC_MSG_CMD_STATUS_OK; 602 } 603 604 void enetc_msg_handle_rxmsg(struct enetc_pf *pf, int vf_id, u16 *status) 605 { 606 struct enetc_msg_swbd *msg = &pf->rxmsg[vf_id]; 607 struct device *dev = &pf->si->pdev->dev; 608 struct enetc_msg_cmd_header *cmd_hdr; 609 u16 cmd_type; 610 611 *status = ENETC_MSG_CMD_STATUS_OK; 612 cmd_hdr = (struct enetc_msg_cmd_header *)msg->vaddr; 613 cmd_type = cmd_hdr->type; 614 615 switch (cmd_type) { 616 case ENETC_MSG_CMD_MNG_MAC: 617 *status = enetc_msg_pf_set_vf_primary_mac_addr(pf, vf_id); 618 break; 619 default: 620 dev_err(dev, "command not supported (cmd_type: 0x%x)\n", 621 cmd_type); 622 } 623 } 624 625 #ifdef CONFIG_PCI_IOV 626 static int enetc_sriov_configure(struct pci_dev *pdev, int num_vfs) 627 { 628 struct enetc_si *si = pci_get_drvdata(pdev); 629 struct enetc_pf *pf = enetc_si_priv(si); 630 int err; 631 632 if (!num_vfs) { 633 enetc_msg_psi_free(pf); 634 kfree(pf->vf_state); 635 pf->num_vfs = 0; 636 pci_disable_sriov(pdev); 637 } else { 638 pf->num_vfs = num_vfs; 639 640 pf->vf_state = kcalloc(num_vfs, sizeof(struct enetc_vf_state), 641 GFP_KERNEL); 642 if (!pf->vf_state) { 643 pf->num_vfs = 0; 644 return -ENOMEM; 645 } 646 647 err = enetc_msg_psi_init(pf); 648 if (err) { 649 dev_err(&pdev->dev, "enetc_msg_psi_init (%d)\n", err); 650 goto err_msg_psi; 651 } 652 653 err = pci_enable_sriov(pdev, num_vfs); 654 if (err) { 655 dev_err(&pdev->dev, "pci_enable_sriov err %d\n", err); 656 goto err_en_sriov; 657 } 658 } 659 660 return num_vfs; 661 662 err_en_sriov: 663 enetc_msg_psi_free(pf); 664 err_msg_psi: 665 kfree(pf->vf_state); 666 pf->num_vfs = 0; 667 668 return err; 669 } 670 #else 671 #define enetc_sriov_configure(pdev, num_vfs) (void)0 672 #endif 673 674 static int enetc_pf_set_features(struct net_device *ndev, 675 netdev_features_t features) 676 { 677 netdev_features_t changed = ndev->features ^ features; 678 struct enetc_ndev_priv *priv = netdev_priv(ndev); 679 680 if (changed & NETIF_F_HW_VLAN_CTAG_FILTER) { 681 struct enetc_pf *pf = enetc_si_priv(priv->si); 682 683 if (!!(features & NETIF_F_HW_VLAN_CTAG_FILTER)) 684 enetc_disable_si_vlan_promisc(pf, 0); 685 else 686 enetc_enable_si_vlan_promisc(pf, 0); 687 } 688 689 if (changed & NETIF_F_LOOPBACK) 690 enetc_set_loopback(ndev, !!(features & NETIF_F_LOOPBACK)); 691 692 return enetc_set_features(ndev, features); 693 } 694 695 static const struct net_device_ops enetc_ndev_ops = { 696 .ndo_open = enetc_open, 697 .ndo_stop = enetc_close, 698 .ndo_start_xmit = enetc_xmit, 699 .ndo_get_stats = enetc_get_stats, 700 .ndo_set_mac_address = enetc_pf_set_mac_addr, 701 .ndo_set_rx_mode = enetc_pf_set_rx_mode, 702 .ndo_vlan_rx_add_vid = enetc_vlan_rx_add_vid, 703 .ndo_vlan_rx_kill_vid = enetc_vlan_rx_del_vid, 704 .ndo_set_vf_mac = enetc_pf_set_vf_mac, 705 .ndo_set_vf_vlan = enetc_pf_set_vf_vlan, 706 .ndo_set_vf_spoofchk = enetc_pf_set_vf_spoofchk, 707 .ndo_set_features = enetc_pf_set_features, 708 .ndo_do_ioctl = enetc_ioctl, 709 .ndo_setup_tc = enetc_setup_tc, 710 }; 711 712 static void enetc_pf_netdev_setup(struct enetc_si *si, struct net_device *ndev, 713 const struct net_device_ops *ndev_ops) 714 { 715 struct enetc_ndev_priv *priv = netdev_priv(ndev); 716 717 SET_NETDEV_DEV(ndev, &si->pdev->dev); 718 priv->ndev = ndev; 719 priv->si = si; 720 priv->dev = &si->pdev->dev; 721 si->ndev = ndev; 722 723 priv->msg_enable = (NETIF_MSG_WOL << 1) - 1; 724 ndev->netdev_ops = ndev_ops; 725 enetc_set_ethtool_ops(ndev); 726 ndev->watchdog_timeo = 5 * HZ; 727 ndev->max_mtu = ENETC_MAX_MTU; 728 729 ndev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM | 730 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX | 731 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_LOOPBACK; 732 ndev->features = NETIF_F_HIGHDMA | NETIF_F_SG | NETIF_F_RXCSUM | 733 NETIF_F_HW_VLAN_CTAG_TX | 734 NETIF_F_HW_VLAN_CTAG_RX; 735 736 if (si->num_rss) 737 ndev->hw_features |= NETIF_F_RXHASH; 738 739 ndev->priv_flags |= IFF_UNICAST_FLT; 740 741 if (si->hw_features & ENETC_SI_F_QBV) 742 priv->active_offloads |= ENETC_F_QBV; 743 744 if (si->hw_features & ENETC_SI_F_PSFP && !enetc_psfp_enable(priv)) { 745 priv->active_offloads |= ENETC_F_QCI; 746 ndev->features |= NETIF_F_HW_TC; 747 ndev->hw_features |= NETIF_F_HW_TC; 748 } 749 750 /* pick up primary MAC address from SI */ 751 enetc_get_primary_mac_addr(&si->hw, ndev->dev_addr); 752 } 753 754 static int enetc_mdio_probe(struct enetc_pf *pf, struct device_node *np) 755 { 756 struct device *dev = &pf->si->pdev->dev; 757 struct enetc_mdio_priv *mdio_priv; 758 struct mii_bus *bus; 759 int err; 760 761 bus = devm_mdiobus_alloc_size(dev, sizeof(*mdio_priv)); 762 if (!bus) 763 return -ENOMEM; 764 765 bus->name = "Freescale ENETC MDIO Bus"; 766 bus->read = enetc_mdio_read; 767 bus->write = enetc_mdio_write; 768 bus->parent = dev; 769 mdio_priv = bus->priv; 770 mdio_priv->hw = &pf->si->hw; 771 mdio_priv->mdio_base = ENETC_EMDIO_BASE; 772 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", dev_name(dev)); 773 774 err = of_mdiobus_register(bus, np); 775 if (err) { 776 dev_err(dev, "cannot register MDIO bus\n"); 777 return err; 778 } 779 780 pf->mdio = bus; 781 782 return 0; 783 } 784 785 static void enetc_mdio_remove(struct enetc_pf *pf) 786 { 787 if (pf->mdio) 788 mdiobus_unregister(pf->mdio); 789 } 790 791 static int enetc_imdio_create(struct enetc_pf *pf) 792 { 793 struct device *dev = &pf->si->pdev->dev; 794 struct enetc_mdio_priv *mdio_priv; 795 struct lynx_pcs *pcs_lynx; 796 struct mdio_device *pcs; 797 struct mii_bus *bus; 798 int err; 799 800 bus = mdiobus_alloc_size(sizeof(*mdio_priv)); 801 if (!bus) 802 return -ENOMEM; 803 804 bus->name = "Freescale ENETC internal MDIO Bus"; 805 bus->read = enetc_mdio_read; 806 bus->write = enetc_mdio_write; 807 bus->parent = dev; 808 bus->phy_mask = ~0; 809 mdio_priv = bus->priv; 810 mdio_priv->hw = &pf->si->hw; 811 mdio_priv->mdio_base = ENETC_PM_IMDIO_BASE; 812 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-imdio", dev_name(dev)); 813 814 err = mdiobus_register(bus); 815 if (err) { 816 dev_err(dev, "cannot register internal MDIO bus (%d)\n", err); 817 goto free_mdio_bus; 818 } 819 820 pcs = mdio_device_create(bus, 0); 821 if (IS_ERR(pcs)) { 822 err = PTR_ERR(pcs); 823 dev_err(dev, "cannot create pcs (%d)\n", err); 824 goto unregister_mdiobus; 825 } 826 827 pcs_lynx = lynx_pcs_create(pcs); 828 if (!pcs_lynx) { 829 mdio_device_free(pcs); 830 err = -ENOMEM; 831 dev_err(dev, "cannot create lynx pcs (%d)\n", err); 832 goto unregister_mdiobus; 833 } 834 835 pf->imdio = bus; 836 pf->pcs = pcs_lynx; 837 838 return 0; 839 840 unregister_mdiobus: 841 mdiobus_unregister(bus); 842 free_mdio_bus: 843 mdiobus_free(bus); 844 return err; 845 } 846 847 static void enetc_imdio_remove(struct enetc_pf *pf) 848 { 849 if (pf->pcs) { 850 mdio_device_free(pf->pcs->mdio); 851 lynx_pcs_destroy(pf->pcs); 852 } 853 if (pf->imdio) { 854 mdiobus_unregister(pf->imdio); 855 mdiobus_free(pf->imdio); 856 } 857 } 858 859 static bool enetc_port_has_pcs(struct enetc_pf *pf) 860 { 861 return (pf->if_mode == PHY_INTERFACE_MODE_SGMII || 862 pf->if_mode == PHY_INTERFACE_MODE_2500BASEX || 863 pf->if_mode == PHY_INTERFACE_MODE_USXGMII); 864 } 865 866 static int enetc_mdiobus_create(struct enetc_pf *pf, struct device_node *node) 867 { 868 struct device_node *mdio_np; 869 int err; 870 871 mdio_np = of_get_child_by_name(node, "mdio"); 872 if (mdio_np) { 873 err = enetc_mdio_probe(pf, mdio_np); 874 875 of_node_put(mdio_np); 876 if (err) 877 return err; 878 } 879 880 if (enetc_port_has_pcs(pf)) { 881 err = enetc_imdio_create(pf); 882 if (err) { 883 enetc_mdio_remove(pf); 884 return err; 885 } 886 } 887 888 return 0; 889 } 890 891 static void enetc_mdiobus_destroy(struct enetc_pf *pf) 892 { 893 enetc_mdio_remove(pf); 894 enetc_imdio_remove(pf); 895 } 896 897 static void enetc_pl_mac_validate(struct phylink_config *config, 898 unsigned long *supported, 899 struct phylink_link_state *state) 900 { 901 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 902 903 if (state->interface != PHY_INTERFACE_MODE_NA && 904 state->interface != PHY_INTERFACE_MODE_INTERNAL && 905 state->interface != PHY_INTERFACE_MODE_SGMII && 906 state->interface != PHY_INTERFACE_MODE_2500BASEX && 907 state->interface != PHY_INTERFACE_MODE_USXGMII && 908 !phy_interface_mode_is_rgmii(state->interface)) { 909 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); 910 return; 911 } 912 913 phylink_set_port_modes(mask); 914 phylink_set(mask, Autoneg); 915 phylink_set(mask, Pause); 916 phylink_set(mask, Asym_Pause); 917 phylink_set(mask, 10baseT_Half); 918 phylink_set(mask, 10baseT_Full); 919 phylink_set(mask, 100baseT_Half); 920 phylink_set(mask, 100baseT_Full); 921 phylink_set(mask, 100baseT_Half); 922 phylink_set(mask, 1000baseT_Half); 923 phylink_set(mask, 1000baseT_Full); 924 925 if (state->interface == PHY_INTERFACE_MODE_INTERNAL || 926 state->interface == PHY_INTERFACE_MODE_2500BASEX || 927 state->interface == PHY_INTERFACE_MODE_USXGMII) { 928 phylink_set(mask, 2500baseT_Full); 929 phylink_set(mask, 2500baseX_Full); 930 } 931 932 bitmap_and(supported, supported, mask, 933 __ETHTOOL_LINK_MODE_MASK_NBITS); 934 bitmap_and(state->advertising, state->advertising, mask, 935 __ETHTOOL_LINK_MODE_MASK_NBITS); 936 } 937 938 static void enetc_pl_mac_config(struct phylink_config *config, 939 unsigned int mode, 940 const struct phylink_link_state *state) 941 { 942 struct enetc_pf *pf = phylink_to_enetc_pf(config); 943 struct enetc_ndev_priv *priv; 944 945 enetc_mac_config(&pf->si->hw, state->interface); 946 947 priv = netdev_priv(pf->si->ndev); 948 if (pf->pcs) 949 phylink_set_pcs(priv->phylink, &pf->pcs->pcs); 950 } 951 952 static void enetc_force_rgmii_mac(struct enetc_hw *hw, int speed, int duplex) 953 { 954 u32 old_val, val; 955 956 old_val = val = enetc_port_rd(hw, ENETC_PM0_IF_MODE); 957 958 if (speed == SPEED_1000) { 959 val &= ~ENETC_PM0_IFM_SSP_MASK; 960 val |= ENETC_PM0_IFM_SSP_1000; 961 } else if (speed == SPEED_100) { 962 val &= ~ENETC_PM0_IFM_SSP_MASK; 963 val |= ENETC_PM0_IFM_SSP_100; 964 } else if (speed == SPEED_10) { 965 val &= ~ENETC_PM0_IFM_SSP_MASK; 966 val |= ENETC_PM0_IFM_SSP_10; 967 } 968 969 if (duplex == DUPLEX_FULL) 970 val |= ENETC_PM0_IFM_FULL_DPX; 971 else 972 val &= ~ENETC_PM0_IFM_FULL_DPX; 973 974 if (val == old_val) 975 return; 976 977 enetc_port_wr(hw, ENETC_PM0_IF_MODE, val); 978 } 979 980 static void enetc_pl_mac_link_up(struct phylink_config *config, 981 struct phy_device *phy, unsigned int mode, 982 phy_interface_t interface, int speed, 983 int duplex, bool tx_pause, bool rx_pause) 984 { 985 struct enetc_pf *pf = phylink_to_enetc_pf(config); 986 struct enetc_ndev_priv *priv; 987 988 priv = netdev_priv(pf->si->ndev); 989 if (priv->active_offloads & ENETC_F_QBV) 990 enetc_sched_speed_set(priv, speed); 991 992 if (!phylink_autoneg_inband(mode) && 993 phy_interface_mode_is_rgmii(interface)) 994 enetc_force_rgmii_mac(&pf->si->hw, speed, duplex); 995 996 enetc_mac_enable(&pf->si->hw, true); 997 } 998 999 static void enetc_pl_mac_link_down(struct phylink_config *config, 1000 unsigned int mode, 1001 phy_interface_t interface) 1002 { 1003 struct enetc_pf *pf = phylink_to_enetc_pf(config); 1004 1005 enetc_mac_enable(&pf->si->hw, false); 1006 } 1007 1008 static const struct phylink_mac_ops enetc_mac_phylink_ops = { 1009 .validate = enetc_pl_mac_validate, 1010 .mac_config = enetc_pl_mac_config, 1011 .mac_link_up = enetc_pl_mac_link_up, 1012 .mac_link_down = enetc_pl_mac_link_down, 1013 }; 1014 1015 static int enetc_phylink_create(struct enetc_ndev_priv *priv, 1016 struct device_node *node) 1017 { 1018 struct enetc_pf *pf = enetc_si_priv(priv->si); 1019 struct phylink *phylink; 1020 int err; 1021 1022 pf->phylink_config.dev = &priv->ndev->dev; 1023 pf->phylink_config.type = PHYLINK_NETDEV; 1024 1025 phylink = phylink_create(&pf->phylink_config, of_fwnode_handle(node), 1026 pf->if_mode, &enetc_mac_phylink_ops); 1027 if (IS_ERR(phylink)) { 1028 err = PTR_ERR(phylink); 1029 return err; 1030 } 1031 1032 priv->phylink = phylink; 1033 1034 return 0; 1035 } 1036 1037 static void enetc_phylink_destroy(struct enetc_ndev_priv *priv) 1038 { 1039 if (priv->phylink) 1040 phylink_destroy(priv->phylink); 1041 } 1042 1043 /* Initialize the entire shared memory for the flow steering entries 1044 * of this port (PF + VFs) 1045 */ 1046 static int enetc_init_port_rfs_memory(struct enetc_si *si) 1047 { 1048 struct enetc_cmd_rfse rfse = {0}; 1049 struct enetc_hw *hw = &si->hw; 1050 int num_rfs, i, err = 0; 1051 u32 val; 1052 1053 val = enetc_port_rd(hw, ENETC_PRFSCAPR); 1054 num_rfs = ENETC_PRFSCAPR_GET_NUM_RFS(val); 1055 1056 for (i = 0; i < num_rfs; i++) { 1057 err = enetc_set_fs_entry(si, &rfse, i); 1058 if (err) 1059 break; 1060 } 1061 1062 return err; 1063 } 1064 1065 static int enetc_init_port_rss_memory(struct enetc_si *si) 1066 { 1067 struct enetc_hw *hw = &si->hw; 1068 int num_rss, err; 1069 int *rss_table; 1070 u32 val; 1071 1072 val = enetc_port_rd(hw, ENETC_PRSSCAPR); 1073 num_rss = ENETC_PRSSCAPR_GET_NUM_RSS(val); 1074 if (!num_rss) 1075 return 0; 1076 1077 rss_table = kcalloc(num_rss, sizeof(*rss_table), GFP_KERNEL); 1078 if (!rss_table) 1079 return -ENOMEM; 1080 1081 err = enetc_set_rss_table(si, rss_table, num_rss); 1082 1083 kfree(rss_table); 1084 1085 return err; 1086 } 1087 1088 static int enetc_pf_probe(struct pci_dev *pdev, 1089 const struct pci_device_id *ent) 1090 { 1091 struct device_node *node = pdev->dev.of_node; 1092 struct enetc_ndev_priv *priv; 1093 struct net_device *ndev; 1094 struct enetc_si *si; 1095 struct enetc_pf *pf; 1096 int err; 1097 1098 err = enetc_pci_probe(pdev, KBUILD_MODNAME, sizeof(*pf)); 1099 if (err) { 1100 dev_err(&pdev->dev, "PCI probing failed\n"); 1101 return err; 1102 } 1103 1104 si = pci_get_drvdata(pdev); 1105 if (!si->hw.port || !si->hw.global) { 1106 err = -ENODEV; 1107 dev_err(&pdev->dev, "could not map PF space, probing a VF?\n"); 1108 goto err_map_pf_space; 1109 } 1110 1111 err = enetc_setup_cbdr(&pdev->dev, &si->hw, ENETC_CBDR_DEFAULT_SIZE, 1112 &si->cbd_ring); 1113 if (err) 1114 goto err_setup_cbdr; 1115 1116 err = enetc_init_port_rfs_memory(si); 1117 if (err) { 1118 dev_err(&pdev->dev, "Failed to initialize RFS memory\n"); 1119 goto err_init_port_rfs; 1120 } 1121 1122 err = enetc_init_port_rss_memory(si); 1123 if (err) { 1124 dev_err(&pdev->dev, "Failed to initialize RSS memory\n"); 1125 goto err_init_port_rss; 1126 } 1127 1128 if (node && !of_device_is_available(node)) { 1129 dev_info(&pdev->dev, "device is disabled, skipping\n"); 1130 err = -ENODEV; 1131 goto err_device_disabled; 1132 } 1133 1134 pf = enetc_si_priv(si); 1135 pf->si = si; 1136 pf->total_vfs = pci_sriov_get_totalvfs(pdev); 1137 1138 enetc_configure_port(pf); 1139 1140 enetc_get_si_caps(si); 1141 1142 ndev = alloc_etherdev_mq(sizeof(*priv), ENETC_MAX_NUM_TXQS); 1143 if (!ndev) { 1144 err = -ENOMEM; 1145 dev_err(&pdev->dev, "netdev creation failed\n"); 1146 goto err_alloc_netdev; 1147 } 1148 1149 enetc_pf_netdev_setup(si, ndev, &enetc_ndev_ops); 1150 1151 priv = netdev_priv(ndev); 1152 1153 enetc_init_si_rings_params(priv); 1154 1155 err = enetc_alloc_si_resources(priv); 1156 if (err) { 1157 dev_err(&pdev->dev, "SI resource alloc failed\n"); 1158 goto err_alloc_si_res; 1159 } 1160 1161 err = enetc_configure_si(priv); 1162 if (err) { 1163 dev_err(&pdev->dev, "Failed to configure SI\n"); 1164 goto err_config_si; 1165 } 1166 1167 err = enetc_alloc_msix(priv); 1168 if (err) { 1169 dev_err(&pdev->dev, "MSIX alloc failed\n"); 1170 goto err_alloc_msix; 1171 } 1172 1173 if (!of_get_phy_mode(node, &pf->if_mode)) { 1174 err = enetc_mdiobus_create(pf, node); 1175 if (err) 1176 goto err_mdiobus_create; 1177 1178 err = enetc_phylink_create(priv, node); 1179 if (err) 1180 goto err_phylink_create; 1181 } 1182 1183 err = register_netdev(ndev); 1184 if (err) 1185 goto err_reg_netdev; 1186 1187 return 0; 1188 1189 err_reg_netdev: 1190 enetc_phylink_destroy(priv); 1191 err_phylink_create: 1192 enetc_mdiobus_destroy(pf); 1193 err_mdiobus_create: 1194 enetc_free_msix(priv); 1195 err_config_si: 1196 err_alloc_msix: 1197 enetc_free_si_resources(priv); 1198 err_alloc_si_res: 1199 si->ndev = NULL; 1200 free_netdev(ndev); 1201 err_alloc_netdev: 1202 err_init_port_rss: 1203 err_init_port_rfs: 1204 err_device_disabled: 1205 enetc_teardown_cbdr(&si->cbd_ring); 1206 err_setup_cbdr: 1207 err_map_pf_space: 1208 enetc_pci_remove(pdev); 1209 1210 return err; 1211 } 1212 1213 static void enetc_pf_remove(struct pci_dev *pdev) 1214 { 1215 struct enetc_si *si = pci_get_drvdata(pdev); 1216 struct enetc_pf *pf = enetc_si_priv(si); 1217 struct enetc_ndev_priv *priv; 1218 1219 priv = netdev_priv(si->ndev); 1220 1221 if (pf->num_vfs) 1222 enetc_sriov_configure(pdev, 0); 1223 1224 unregister_netdev(si->ndev); 1225 1226 enetc_phylink_destroy(priv); 1227 enetc_mdiobus_destroy(pf); 1228 1229 enetc_free_msix(priv); 1230 1231 enetc_free_si_resources(priv); 1232 enetc_teardown_cbdr(&si->cbd_ring); 1233 1234 free_netdev(si->ndev); 1235 1236 enetc_pci_remove(pdev); 1237 } 1238 1239 static const struct pci_device_id enetc_pf_id_table[] = { 1240 { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, ENETC_DEV_ID_PF) }, 1241 { 0, } /* End of table. */ 1242 }; 1243 MODULE_DEVICE_TABLE(pci, enetc_pf_id_table); 1244 1245 static struct pci_driver enetc_pf_driver = { 1246 .name = KBUILD_MODNAME, 1247 .id_table = enetc_pf_id_table, 1248 .probe = enetc_pf_probe, 1249 .remove = enetc_pf_remove, 1250 #ifdef CONFIG_PCI_IOV 1251 .sriov_configure = enetc_sriov_configure, 1252 #endif 1253 }; 1254 module_pci_driver(enetc_pf_driver); 1255 1256 MODULE_DESCRIPTION(ENETC_DRV_NAME_STR); 1257 MODULE_LICENSE("Dual BSD/GPL"); 1258