1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2 /* Copyright 2017-2019 NXP */ 3 4 #include <asm/unaligned.h> 5 #include <linux/mdio.h> 6 #include <linux/module.h> 7 #include <linux/fsl/enetc_mdio.h> 8 #include <linux/of_platform.h> 9 #include <linux/of_mdio.h> 10 #include <linux/of_net.h> 11 #include "enetc_ierb.h" 12 #include "enetc_pf.h" 13 14 #define ENETC_DRV_NAME_STR "ENETC PF driver" 15 16 static void enetc_pf_get_primary_mac_addr(struct enetc_hw *hw, int si, u8 *addr) 17 { 18 u32 upper = __raw_readl(hw->port + ENETC_PSIPMAR0(si)); 19 u16 lower = __raw_readw(hw->port + ENETC_PSIPMAR1(si)); 20 21 put_unaligned_le32(upper, addr); 22 put_unaligned_le16(lower, addr + 4); 23 } 24 25 static void enetc_pf_set_primary_mac_addr(struct enetc_hw *hw, int si, 26 const u8 *addr) 27 { 28 u32 upper = get_unaligned_le32(addr); 29 u16 lower = get_unaligned_le16(addr + 4); 30 31 __raw_writel(upper, hw->port + ENETC_PSIPMAR0(si)); 32 __raw_writew(lower, hw->port + ENETC_PSIPMAR1(si)); 33 } 34 35 static int enetc_pf_set_mac_addr(struct net_device *ndev, void *addr) 36 { 37 struct enetc_ndev_priv *priv = netdev_priv(ndev); 38 struct sockaddr *saddr = addr; 39 40 if (!is_valid_ether_addr(saddr->sa_data)) 41 return -EADDRNOTAVAIL; 42 43 eth_hw_addr_set(ndev, saddr->sa_data); 44 enetc_pf_set_primary_mac_addr(&priv->si->hw, 0, saddr->sa_data); 45 46 return 0; 47 } 48 49 static void enetc_set_vlan_promisc(struct enetc_hw *hw, char si_map) 50 { 51 u32 val = enetc_port_rd(hw, ENETC_PSIPVMR); 52 53 val &= ~ENETC_PSIPVMR_SET_VP(ENETC_VLAN_PROMISC_MAP_ALL); 54 enetc_port_wr(hw, ENETC_PSIPVMR, ENETC_PSIPVMR_SET_VP(si_map) | val); 55 } 56 57 static void enetc_enable_si_vlan_promisc(struct enetc_pf *pf, int si_idx) 58 { 59 pf->vlan_promisc_simap |= BIT(si_idx); 60 enetc_set_vlan_promisc(&pf->si->hw, pf->vlan_promisc_simap); 61 } 62 63 static void enetc_disable_si_vlan_promisc(struct enetc_pf *pf, int si_idx) 64 { 65 pf->vlan_promisc_simap &= ~BIT(si_idx); 66 enetc_set_vlan_promisc(&pf->si->hw, pf->vlan_promisc_simap); 67 } 68 69 static void enetc_set_isol_vlan(struct enetc_hw *hw, int si, u16 vlan, u8 qos) 70 { 71 u32 val = 0; 72 73 if (vlan) 74 val = ENETC_PSIVLAN_EN | ENETC_PSIVLAN_SET_QOS(qos) | vlan; 75 76 enetc_port_wr(hw, ENETC_PSIVLANR(si), val); 77 } 78 79 static int enetc_mac_addr_hash_idx(const u8 *addr) 80 { 81 u64 fold = __swab64(ether_addr_to_u64(addr)) >> 16; 82 u64 mask = 0; 83 int res = 0; 84 int i; 85 86 for (i = 0; i < 8; i++) 87 mask |= BIT_ULL(i * 6); 88 89 for (i = 0; i < 6; i++) 90 res |= (hweight64(fold & (mask << i)) & 0x1) << i; 91 92 return res; 93 } 94 95 static void enetc_reset_mac_addr_filter(struct enetc_mac_filter *filter) 96 { 97 filter->mac_addr_cnt = 0; 98 99 bitmap_zero(filter->mac_hash_table, 100 ENETC_MADDR_HASH_TBL_SZ); 101 } 102 103 static void enetc_add_mac_addr_em_filter(struct enetc_mac_filter *filter, 104 const unsigned char *addr) 105 { 106 /* add exact match addr */ 107 ether_addr_copy(filter->mac_addr, addr); 108 filter->mac_addr_cnt++; 109 } 110 111 static void enetc_add_mac_addr_ht_filter(struct enetc_mac_filter *filter, 112 const unsigned char *addr) 113 { 114 int idx = enetc_mac_addr_hash_idx(addr); 115 116 /* add hash table entry */ 117 __set_bit(idx, filter->mac_hash_table); 118 filter->mac_addr_cnt++; 119 } 120 121 static void enetc_clear_mac_ht_flt(struct enetc_si *si, int si_idx, int type) 122 { 123 bool err = si->errata & ENETC_ERR_UCMCSWP; 124 125 if (type == UC) { 126 enetc_port_wr(&si->hw, ENETC_PSIUMHFR0(si_idx, err), 0); 127 enetc_port_wr(&si->hw, ENETC_PSIUMHFR1(si_idx), 0); 128 } else { /* MC */ 129 enetc_port_wr(&si->hw, ENETC_PSIMMHFR0(si_idx, err), 0); 130 enetc_port_wr(&si->hw, ENETC_PSIMMHFR1(si_idx), 0); 131 } 132 } 133 134 static void enetc_set_mac_ht_flt(struct enetc_si *si, int si_idx, int type, 135 unsigned long hash) 136 { 137 bool err = si->errata & ENETC_ERR_UCMCSWP; 138 139 if (type == UC) { 140 enetc_port_wr(&si->hw, ENETC_PSIUMHFR0(si_idx, err), 141 lower_32_bits(hash)); 142 enetc_port_wr(&si->hw, ENETC_PSIUMHFR1(si_idx), 143 upper_32_bits(hash)); 144 } else { /* MC */ 145 enetc_port_wr(&si->hw, ENETC_PSIMMHFR0(si_idx, err), 146 lower_32_bits(hash)); 147 enetc_port_wr(&si->hw, ENETC_PSIMMHFR1(si_idx), 148 upper_32_bits(hash)); 149 } 150 } 151 152 static void enetc_sync_mac_filters(struct enetc_pf *pf) 153 { 154 struct enetc_mac_filter *f = pf->mac_filter; 155 struct enetc_si *si = pf->si; 156 int i, pos; 157 158 pos = EMETC_MAC_ADDR_FILT_RES; 159 160 for (i = 0; i < MADDR_TYPE; i++, f++) { 161 bool em = (f->mac_addr_cnt == 1) && (i == UC); 162 bool clear = !f->mac_addr_cnt; 163 164 if (clear) { 165 if (i == UC) 166 enetc_clear_mac_flt_entry(si, pos); 167 168 enetc_clear_mac_ht_flt(si, 0, i); 169 continue; 170 } 171 172 /* exact match filter */ 173 if (em) { 174 int err; 175 176 enetc_clear_mac_ht_flt(si, 0, UC); 177 178 err = enetc_set_mac_flt_entry(si, pos, f->mac_addr, 179 BIT(0)); 180 if (!err) 181 continue; 182 183 /* fallback to HT filtering */ 184 dev_warn(&si->pdev->dev, "fallback to HT filt (%d)\n", 185 err); 186 } 187 188 /* hash table filter, clear EM filter for UC entries */ 189 if (i == UC) 190 enetc_clear_mac_flt_entry(si, pos); 191 192 enetc_set_mac_ht_flt(si, 0, i, *f->mac_hash_table); 193 } 194 } 195 196 static void enetc_pf_set_rx_mode(struct net_device *ndev) 197 { 198 struct enetc_ndev_priv *priv = netdev_priv(ndev); 199 struct enetc_pf *pf = enetc_si_priv(priv->si); 200 struct enetc_hw *hw = &priv->si->hw; 201 bool uprom = false, mprom = false; 202 struct enetc_mac_filter *filter; 203 struct netdev_hw_addr *ha; 204 u32 psipmr = 0; 205 bool em; 206 207 if (ndev->flags & IFF_PROMISC) { 208 /* enable promisc mode for SI0 (PF) */ 209 psipmr = ENETC_PSIPMR_SET_UP(0) | ENETC_PSIPMR_SET_MP(0); 210 uprom = true; 211 mprom = true; 212 } else if (ndev->flags & IFF_ALLMULTI) { 213 /* enable multi cast promisc mode for SI0 (PF) */ 214 psipmr = ENETC_PSIPMR_SET_MP(0); 215 mprom = true; 216 } 217 218 /* first 2 filter entries belong to PF */ 219 if (!uprom) { 220 /* Update unicast filters */ 221 filter = &pf->mac_filter[UC]; 222 enetc_reset_mac_addr_filter(filter); 223 224 em = (netdev_uc_count(ndev) == 1); 225 netdev_for_each_uc_addr(ha, ndev) { 226 if (em) { 227 enetc_add_mac_addr_em_filter(filter, ha->addr); 228 break; 229 } 230 231 enetc_add_mac_addr_ht_filter(filter, ha->addr); 232 } 233 } 234 235 if (!mprom) { 236 /* Update multicast filters */ 237 filter = &pf->mac_filter[MC]; 238 enetc_reset_mac_addr_filter(filter); 239 240 netdev_for_each_mc_addr(ha, ndev) { 241 if (!is_multicast_ether_addr(ha->addr)) 242 continue; 243 244 enetc_add_mac_addr_ht_filter(filter, ha->addr); 245 } 246 } 247 248 if (!uprom || !mprom) 249 /* update PF entries */ 250 enetc_sync_mac_filters(pf); 251 252 psipmr |= enetc_port_rd(hw, ENETC_PSIPMR) & 253 ~(ENETC_PSIPMR_SET_UP(0) | ENETC_PSIPMR_SET_MP(0)); 254 enetc_port_wr(hw, ENETC_PSIPMR, psipmr); 255 } 256 257 static void enetc_set_vlan_ht_filter(struct enetc_hw *hw, int si_idx, 258 unsigned long hash) 259 { 260 enetc_port_wr(hw, ENETC_PSIVHFR0(si_idx), lower_32_bits(hash)); 261 enetc_port_wr(hw, ENETC_PSIVHFR1(si_idx), upper_32_bits(hash)); 262 } 263 264 static int enetc_vid_hash_idx(unsigned int vid) 265 { 266 int res = 0; 267 int i; 268 269 for (i = 0; i < 6; i++) 270 res |= (hweight8(vid & (BIT(i) | BIT(i + 6))) & 0x1) << i; 271 272 return res; 273 } 274 275 static void enetc_sync_vlan_ht_filter(struct enetc_pf *pf, bool rehash) 276 { 277 int i; 278 279 if (rehash) { 280 bitmap_zero(pf->vlan_ht_filter, ENETC_VLAN_HT_SIZE); 281 282 for_each_set_bit(i, pf->active_vlans, VLAN_N_VID) { 283 int hidx = enetc_vid_hash_idx(i); 284 285 __set_bit(hidx, pf->vlan_ht_filter); 286 } 287 } 288 289 enetc_set_vlan_ht_filter(&pf->si->hw, 0, *pf->vlan_ht_filter); 290 } 291 292 static int enetc_vlan_rx_add_vid(struct net_device *ndev, __be16 prot, u16 vid) 293 { 294 struct enetc_ndev_priv *priv = netdev_priv(ndev); 295 struct enetc_pf *pf = enetc_si_priv(priv->si); 296 int idx; 297 298 __set_bit(vid, pf->active_vlans); 299 300 idx = enetc_vid_hash_idx(vid); 301 if (!__test_and_set_bit(idx, pf->vlan_ht_filter)) 302 enetc_sync_vlan_ht_filter(pf, false); 303 304 return 0; 305 } 306 307 static int enetc_vlan_rx_del_vid(struct net_device *ndev, __be16 prot, u16 vid) 308 { 309 struct enetc_ndev_priv *priv = netdev_priv(ndev); 310 struct enetc_pf *pf = enetc_si_priv(priv->si); 311 312 __clear_bit(vid, pf->active_vlans); 313 enetc_sync_vlan_ht_filter(pf, true); 314 315 return 0; 316 } 317 318 static void enetc_set_loopback(struct net_device *ndev, bool en) 319 { 320 struct enetc_ndev_priv *priv = netdev_priv(ndev); 321 struct enetc_hw *hw = &priv->si->hw; 322 u32 reg; 323 324 reg = enetc_port_rd(hw, ENETC_PM0_IF_MODE); 325 if (reg & ENETC_PM0_IFM_RG) { 326 /* RGMII mode */ 327 reg = (reg & ~ENETC_PM0_IFM_RLP) | 328 (en ? ENETC_PM0_IFM_RLP : 0); 329 enetc_port_wr(hw, ENETC_PM0_IF_MODE, reg); 330 } else { 331 /* assume SGMII mode */ 332 reg = enetc_port_rd(hw, ENETC_PM0_CMD_CFG); 333 reg = (reg & ~ENETC_PM0_CMD_XGLP) | 334 (en ? ENETC_PM0_CMD_XGLP : 0); 335 reg = (reg & ~ENETC_PM0_CMD_PHY_TX_EN) | 336 (en ? ENETC_PM0_CMD_PHY_TX_EN : 0); 337 enetc_port_wr(hw, ENETC_PM0_CMD_CFG, reg); 338 enetc_port_wr(hw, ENETC_PM1_CMD_CFG, reg); 339 } 340 } 341 342 static int enetc_pf_set_vf_mac(struct net_device *ndev, int vf, u8 *mac) 343 { 344 struct enetc_ndev_priv *priv = netdev_priv(ndev); 345 struct enetc_pf *pf = enetc_si_priv(priv->si); 346 struct enetc_vf_state *vf_state; 347 348 if (vf >= pf->total_vfs) 349 return -EINVAL; 350 351 if (!is_valid_ether_addr(mac)) 352 return -EADDRNOTAVAIL; 353 354 vf_state = &pf->vf_state[vf]; 355 vf_state->flags |= ENETC_VF_FLAG_PF_SET_MAC; 356 enetc_pf_set_primary_mac_addr(&priv->si->hw, vf + 1, mac); 357 return 0; 358 } 359 360 static int enetc_pf_set_vf_vlan(struct net_device *ndev, int vf, u16 vlan, 361 u8 qos, __be16 proto) 362 { 363 struct enetc_ndev_priv *priv = netdev_priv(ndev); 364 struct enetc_pf *pf = enetc_si_priv(priv->si); 365 366 if (priv->si->errata & ENETC_ERR_VLAN_ISOL) 367 return -EOPNOTSUPP; 368 369 if (vf >= pf->total_vfs) 370 return -EINVAL; 371 372 if (proto != htons(ETH_P_8021Q)) 373 /* only C-tags supported for now */ 374 return -EPROTONOSUPPORT; 375 376 enetc_set_isol_vlan(&priv->si->hw, vf + 1, vlan, qos); 377 return 0; 378 } 379 380 static int enetc_pf_set_vf_spoofchk(struct net_device *ndev, int vf, bool en) 381 { 382 struct enetc_ndev_priv *priv = netdev_priv(ndev); 383 struct enetc_pf *pf = enetc_si_priv(priv->si); 384 u32 cfgr; 385 386 if (vf >= pf->total_vfs) 387 return -EINVAL; 388 389 cfgr = enetc_port_rd(&priv->si->hw, ENETC_PSICFGR0(vf + 1)); 390 cfgr = (cfgr & ~ENETC_PSICFGR0_ASE) | (en ? ENETC_PSICFGR0_ASE : 0); 391 enetc_port_wr(&priv->si->hw, ENETC_PSICFGR0(vf + 1), cfgr); 392 393 return 0; 394 } 395 396 static int enetc_setup_mac_address(struct device_node *np, struct enetc_pf *pf, 397 int si) 398 { 399 struct device *dev = &pf->si->pdev->dev; 400 struct enetc_hw *hw = &pf->si->hw; 401 u8 mac_addr[ETH_ALEN] = { 0 }; 402 int err; 403 404 /* (1) try to get the MAC address from the device tree */ 405 if (np) { 406 err = of_get_mac_address(np, mac_addr); 407 if (err == -EPROBE_DEFER) 408 return err; 409 } 410 411 /* (2) bootloader supplied MAC address */ 412 if (is_zero_ether_addr(mac_addr)) 413 enetc_pf_get_primary_mac_addr(hw, si, mac_addr); 414 415 /* (3) choose a random one */ 416 if (is_zero_ether_addr(mac_addr)) { 417 eth_random_addr(mac_addr); 418 dev_info(dev, "no MAC address specified for SI%d, using %pM\n", 419 si, mac_addr); 420 } 421 422 enetc_pf_set_primary_mac_addr(hw, si, mac_addr); 423 424 return 0; 425 } 426 427 static int enetc_setup_mac_addresses(struct device_node *np, 428 struct enetc_pf *pf) 429 { 430 int err, i; 431 432 /* The PF might take its MAC from the device tree */ 433 err = enetc_setup_mac_address(np, pf, 0); 434 if (err) 435 return err; 436 437 for (i = 0; i < pf->total_vfs; i++) { 438 err = enetc_setup_mac_address(NULL, pf, i + 1); 439 if (err) 440 return err; 441 } 442 443 return 0; 444 } 445 446 static void enetc_port_assign_rfs_entries(struct enetc_si *si) 447 { 448 struct enetc_pf *pf = enetc_si_priv(si); 449 struct enetc_hw *hw = &si->hw; 450 int num_entries, vf_entries, i; 451 u32 val; 452 453 /* split RFS entries between functions */ 454 val = enetc_port_rd(hw, ENETC_PRFSCAPR); 455 num_entries = ENETC_PRFSCAPR_GET_NUM_RFS(val); 456 vf_entries = num_entries / (pf->total_vfs + 1); 457 458 for (i = 0; i < pf->total_vfs; i++) 459 enetc_port_wr(hw, ENETC_PSIRFSCFGR(i + 1), vf_entries); 460 enetc_port_wr(hw, ENETC_PSIRFSCFGR(0), 461 num_entries - vf_entries * pf->total_vfs); 462 463 /* enable RFS on port */ 464 enetc_port_wr(hw, ENETC_PRFSMR, ENETC_PRFSMR_RFSE); 465 } 466 467 static void enetc_port_si_configure(struct enetc_si *si) 468 { 469 struct enetc_pf *pf = enetc_si_priv(si); 470 struct enetc_hw *hw = &si->hw; 471 int num_rings, i; 472 u32 val; 473 474 val = enetc_port_rd(hw, ENETC_PCAPR0); 475 num_rings = min(ENETC_PCAPR0_RXBDR(val), ENETC_PCAPR0_TXBDR(val)); 476 477 val = ENETC_PSICFGR0_SET_TXBDR(ENETC_PF_NUM_RINGS); 478 val |= ENETC_PSICFGR0_SET_RXBDR(ENETC_PF_NUM_RINGS); 479 480 if (unlikely(num_rings < ENETC_PF_NUM_RINGS)) { 481 val = ENETC_PSICFGR0_SET_TXBDR(num_rings); 482 val |= ENETC_PSICFGR0_SET_RXBDR(num_rings); 483 484 dev_warn(&si->pdev->dev, "Found %d rings, expected %d!\n", 485 num_rings, ENETC_PF_NUM_RINGS); 486 487 num_rings = 0; 488 } 489 490 /* Add default one-time settings for SI0 (PF) */ 491 val |= ENETC_PSICFGR0_SIVC(ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S); 492 493 enetc_port_wr(hw, ENETC_PSICFGR0(0), val); 494 495 if (num_rings) 496 num_rings -= ENETC_PF_NUM_RINGS; 497 498 /* Configure the SIs for each available VF */ 499 val = ENETC_PSICFGR0_SIVC(ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S); 500 val |= ENETC_PSICFGR0_VTE | ENETC_PSICFGR0_SIVIE; 501 502 if (num_rings) { 503 num_rings /= pf->total_vfs; 504 val |= ENETC_PSICFGR0_SET_TXBDR(num_rings); 505 val |= ENETC_PSICFGR0_SET_RXBDR(num_rings); 506 } 507 508 for (i = 0; i < pf->total_vfs; i++) 509 enetc_port_wr(hw, ENETC_PSICFGR0(i + 1), val); 510 511 /* Port level VLAN settings */ 512 val = ENETC_PVCLCTR_OVTPIDL(ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S); 513 enetc_port_wr(hw, ENETC_PVCLCTR, val); 514 /* use outer tag for VLAN filtering */ 515 enetc_port_wr(hw, ENETC_PSIVLANFMR, ENETC_PSIVLANFMR_VS); 516 } 517 518 static void enetc_configure_port_mac(struct enetc_hw *hw) 519 { 520 int tc; 521 522 enetc_port_wr(hw, ENETC_PM0_MAXFRM, 523 ENETC_SET_MAXFRM(ENETC_RX_MAXFRM_SIZE)); 524 525 for (tc = 0; tc < 8; tc++) 526 enetc_port_wr(hw, ENETC_PTCMSDUR(tc), ENETC_MAC_MAXFRM_SIZE); 527 528 enetc_port_wr(hw, ENETC_PM0_CMD_CFG, ENETC_PM0_CMD_PHY_TX_EN | 529 ENETC_PM0_CMD_TXP | ENETC_PM0_PROMISC); 530 531 enetc_port_wr(hw, ENETC_PM1_CMD_CFG, ENETC_PM0_CMD_PHY_TX_EN | 532 ENETC_PM0_CMD_TXP | ENETC_PM0_PROMISC); 533 534 /* On LS1028A, the MAC RX FIFO defaults to 2, which is too high 535 * and may lead to RX lock-up under traffic. Set it to 1 instead, 536 * as recommended by the hardware team. 537 */ 538 enetc_port_wr(hw, ENETC_PM0_RX_FIFO, ENETC_PM0_RX_FIFO_VAL); 539 } 540 541 static void enetc_mac_config(struct enetc_hw *hw, phy_interface_t phy_mode) 542 { 543 u32 val; 544 545 if (phy_interface_mode_is_rgmii(phy_mode)) { 546 val = enetc_port_rd(hw, ENETC_PM0_IF_MODE); 547 val &= ~(ENETC_PM0_IFM_EN_AUTO | ENETC_PM0_IFM_IFMODE_MASK); 548 val |= ENETC_PM0_IFM_IFMODE_GMII | ENETC_PM0_IFM_RG; 549 enetc_port_wr(hw, ENETC_PM0_IF_MODE, val); 550 } 551 552 if (phy_mode == PHY_INTERFACE_MODE_USXGMII) { 553 val = ENETC_PM0_IFM_FULL_DPX | ENETC_PM0_IFM_IFMODE_XGMII; 554 enetc_port_wr(hw, ENETC_PM0_IF_MODE, val); 555 } 556 } 557 558 static void enetc_mac_enable(struct enetc_hw *hw, bool en) 559 { 560 u32 val = enetc_port_rd(hw, ENETC_PM0_CMD_CFG); 561 562 val &= ~(ENETC_PM0_TX_EN | ENETC_PM0_RX_EN); 563 val |= en ? (ENETC_PM0_TX_EN | ENETC_PM0_RX_EN) : 0; 564 565 enetc_port_wr(hw, ENETC_PM0_CMD_CFG, val); 566 enetc_port_wr(hw, ENETC_PM1_CMD_CFG, val); 567 } 568 569 static void enetc_configure_port_pmac(struct enetc_hw *hw) 570 { 571 u32 temp; 572 573 /* Set pMAC step lock */ 574 temp = enetc_port_rd(hw, ENETC_PFPMR); 575 enetc_port_wr(hw, ENETC_PFPMR, 576 temp | ENETC_PFPMR_PMACE | ENETC_PFPMR_MWLM); 577 578 temp = enetc_port_rd(hw, ENETC_MMCSR); 579 enetc_port_wr(hw, ENETC_MMCSR, temp | ENETC_MMCSR_ME); 580 } 581 582 static void enetc_configure_port(struct enetc_pf *pf) 583 { 584 u8 hash_key[ENETC_RSSHASH_KEY_SIZE]; 585 struct enetc_hw *hw = &pf->si->hw; 586 587 enetc_configure_port_pmac(hw); 588 589 enetc_configure_port_mac(hw); 590 591 enetc_port_si_configure(pf->si); 592 593 /* set up hash key */ 594 get_random_bytes(hash_key, ENETC_RSSHASH_KEY_SIZE); 595 enetc_set_rss_key(hw, hash_key); 596 597 /* split up RFS entries */ 598 enetc_port_assign_rfs_entries(pf->si); 599 600 /* enforce VLAN promisc mode for all SIs */ 601 pf->vlan_promisc_simap = ENETC_VLAN_PROMISC_MAP_ALL; 602 enetc_set_vlan_promisc(hw, pf->vlan_promisc_simap); 603 604 enetc_port_wr(hw, ENETC_PSIPMR, 0); 605 606 /* enable port */ 607 enetc_port_wr(hw, ENETC_PMR, ENETC_PMR_EN); 608 } 609 610 /* Messaging */ 611 static u16 enetc_msg_pf_set_vf_primary_mac_addr(struct enetc_pf *pf, 612 int vf_id) 613 { 614 struct enetc_vf_state *vf_state = &pf->vf_state[vf_id]; 615 struct enetc_msg_swbd *msg = &pf->rxmsg[vf_id]; 616 struct enetc_msg_cmd_set_primary_mac *cmd; 617 struct device *dev = &pf->si->pdev->dev; 618 u16 cmd_id; 619 char *addr; 620 621 cmd = (struct enetc_msg_cmd_set_primary_mac *)msg->vaddr; 622 cmd_id = cmd->header.id; 623 if (cmd_id != ENETC_MSG_CMD_MNG_ADD) 624 return ENETC_MSG_CMD_STATUS_FAIL; 625 626 addr = cmd->mac.sa_data; 627 if (vf_state->flags & ENETC_VF_FLAG_PF_SET_MAC) 628 dev_warn(dev, "Attempt to override PF set mac addr for VF%d\n", 629 vf_id); 630 else 631 enetc_pf_set_primary_mac_addr(&pf->si->hw, vf_id + 1, addr); 632 633 return ENETC_MSG_CMD_STATUS_OK; 634 } 635 636 void enetc_msg_handle_rxmsg(struct enetc_pf *pf, int vf_id, u16 *status) 637 { 638 struct enetc_msg_swbd *msg = &pf->rxmsg[vf_id]; 639 struct device *dev = &pf->si->pdev->dev; 640 struct enetc_msg_cmd_header *cmd_hdr; 641 u16 cmd_type; 642 643 *status = ENETC_MSG_CMD_STATUS_OK; 644 cmd_hdr = (struct enetc_msg_cmd_header *)msg->vaddr; 645 cmd_type = cmd_hdr->type; 646 647 switch (cmd_type) { 648 case ENETC_MSG_CMD_MNG_MAC: 649 *status = enetc_msg_pf_set_vf_primary_mac_addr(pf, vf_id); 650 break; 651 default: 652 dev_err(dev, "command not supported (cmd_type: 0x%x)\n", 653 cmd_type); 654 } 655 } 656 657 #ifdef CONFIG_PCI_IOV 658 static int enetc_sriov_configure(struct pci_dev *pdev, int num_vfs) 659 { 660 struct enetc_si *si = pci_get_drvdata(pdev); 661 struct enetc_pf *pf = enetc_si_priv(si); 662 int err; 663 664 if (!num_vfs) { 665 enetc_msg_psi_free(pf); 666 kfree(pf->vf_state); 667 pf->num_vfs = 0; 668 pci_disable_sriov(pdev); 669 } else { 670 pf->num_vfs = num_vfs; 671 672 pf->vf_state = kcalloc(num_vfs, sizeof(struct enetc_vf_state), 673 GFP_KERNEL); 674 if (!pf->vf_state) { 675 pf->num_vfs = 0; 676 return -ENOMEM; 677 } 678 679 err = enetc_msg_psi_init(pf); 680 if (err) { 681 dev_err(&pdev->dev, "enetc_msg_psi_init (%d)\n", err); 682 goto err_msg_psi; 683 } 684 685 err = pci_enable_sriov(pdev, num_vfs); 686 if (err) { 687 dev_err(&pdev->dev, "pci_enable_sriov err %d\n", err); 688 goto err_en_sriov; 689 } 690 } 691 692 return num_vfs; 693 694 err_en_sriov: 695 enetc_msg_psi_free(pf); 696 err_msg_psi: 697 kfree(pf->vf_state); 698 pf->num_vfs = 0; 699 700 return err; 701 } 702 #else 703 #define enetc_sriov_configure(pdev, num_vfs) (void)0 704 #endif 705 706 static int enetc_pf_set_features(struct net_device *ndev, 707 netdev_features_t features) 708 { 709 netdev_features_t changed = ndev->features ^ features; 710 struct enetc_ndev_priv *priv = netdev_priv(ndev); 711 712 if (changed & NETIF_F_HW_VLAN_CTAG_FILTER) { 713 struct enetc_pf *pf = enetc_si_priv(priv->si); 714 715 if (!!(features & NETIF_F_HW_VLAN_CTAG_FILTER)) 716 enetc_disable_si_vlan_promisc(pf, 0); 717 else 718 enetc_enable_si_vlan_promisc(pf, 0); 719 } 720 721 if (changed & NETIF_F_LOOPBACK) 722 enetc_set_loopback(ndev, !!(features & NETIF_F_LOOPBACK)); 723 724 return enetc_set_features(ndev, features); 725 } 726 727 static const struct net_device_ops enetc_ndev_ops = { 728 .ndo_open = enetc_open, 729 .ndo_stop = enetc_close, 730 .ndo_start_xmit = enetc_xmit, 731 .ndo_get_stats = enetc_get_stats, 732 .ndo_set_mac_address = enetc_pf_set_mac_addr, 733 .ndo_set_rx_mode = enetc_pf_set_rx_mode, 734 .ndo_vlan_rx_add_vid = enetc_vlan_rx_add_vid, 735 .ndo_vlan_rx_kill_vid = enetc_vlan_rx_del_vid, 736 .ndo_set_vf_mac = enetc_pf_set_vf_mac, 737 .ndo_set_vf_vlan = enetc_pf_set_vf_vlan, 738 .ndo_set_vf_spoofchk = enetc_pf_set_vf_spoofchk, 739 .ndo_set_features = enetc_pf_set_features, 740 .ndo_eth_ioctl = enetc_ioctl, 741 .ndo_setup_tc = enetc_setup_tc, 742 .ndo_bpf = enetc_setup_bpf, 743 .ndo_xdp_xmit = enetc_xdp_xmit, 744 }; 745 746 static void enetc_pf_netdev_setup(struct enetc_si *si, struct net_device *ndev, 747 const struct net_device_ops *ndev_ops) 748 { 749 struct enetc_ndev_priv *priv = netdev_priv(ndev); 750 751 SET_NETDEV_DEV(ndev, &si->pdev->dev); 752 priv->ndev = ndev; 753 priv->si = si; 754 priv->dev = &si->pdev->dev; 755 si->ndev = ndev; 756 757 priv->msg_enable = (NETIF_MSG_WOL << 1) - 1; 758 ndev->netdev_ops = ndev_ops; 759 enetc_set_ethtool_ops(ndev); 760 ndev->watchdog_timeo = 5 * HZ; 761 ndev->max_mtu = ENETC_MAX_MTU; 762 763 ndev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM | 764 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX | 765 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_LOOPBACK | 766 NETIF_F_HW_CSUM | NETIF_F_TSO | NETIF_F_TSO6; 767 ndev->features = NETIF_F_HIGHDMA | NETIF_F_SG | NETIF_F_RXCSUM | 768 NETIF_F_HW_VLAN_CTAG_TX | 769 NETIF_F_HW_VLAN_CTAG_RX | 770 NETIF_F_HW_CSUM | NETIF_F_TSO | NETIF_F_TSO6; 771 ndev->vlan_features = NETIF_F_SG | NETIF_F_HW_CSUM | 772 NETIF_F_TSO | NETIF_F_TSO6; 773 774 if (si->num_rss) 775 ndev->hw_features |= NETIF_F_RXHASH; 776 777 ndev->priv_flags |= IFF_UNICAST_FLT; 778 779 if (si->hw_features & ENETC_SI_F_QBV) 780 priv->active_offloads |= ENETC_F_QBV; 781 782 if (si->hw_features & ENETC_SI_F_PSFP && !enetc_psfp_enable(priv)) { 783 priv->active_offloads |= ENETC_F_QCI; 784 ndev->features |= NETIF_F_HW_TC; 785 ndev->hw_features |= NETIF_F_HW_TC; 786 } 787 788 /* pick up primary MAC address from SI */ 789 enetc_load_primary_mac_addr(&si->hw, ndev); 790 } 791 792 static int enetc_mdio_probe(struct enetc_pf *pf, struct device_node *np) 793 { 794 struct device *dev = &pf->si->pdev->dev; 795 struct enetc_mdio_priv *mdio_priv; 796 struct mii_bus *bus; 797 int err; 798 799 bus = devm_mdiobus_alloc_size(dev, sizeof(*mdio_priv)); 800 if (!bus) 801 return -ENOMEM; 802 803 bus->name = "Freescale ENETC MDIO Bus"; 804 bus->read = enetc_mdio_read; 805 bus->write = enetc_mdio_write; 806 bus->parent = dev; 807 mdio_priv = bus->priv; 808 mdio_priv->hw = &pf->si->hw; 809 mdio_priv->mdio_base = ENETC_EMDIO_BASE; 810 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", dev_name(dev)); 811 812 err = of_mdiobus_register(bus, np); 813 if (err) 814 return dev_err_probe(dev, err, "cannot register MDIO bus\n"); 815 816 pf->mdio = bus; 817 818 return 0; 819 } 820 821 static void enetc_mdio_remove(struct enetc_pf *pf) 822 { 823 if (pf->mdio) 824 mdiobus_unregister(pf->mdio); 825 } 826 827 static int enetc_imdio_create(struct enetc_pf *pf) 828 { 829 struct device *dev = &pf->si->pdev->dev; 830 struct enetc_mdio_priv *mdio_priv; 831 struct lynx_pcs *pcs_lynx; 832 struct mdio_device *pcs; 833 struct mii_bus *bus; 834 int err; 835 836 bus = mdiobus_alloc_size(sizeof(*mdio_priv)); 837 if (!bus) 838 return -ENOMEM; 839 840 bus->name = "Freescale ENETC internal MDIO Bus"; 841 bus->read = enetc_mdio_read; 842 bus->write = enetc_mdio_write; 843 bus->parent = dev; 844 bus->phy_mask = ~0; 845 mdio_priv = bus->priv; 846 mdio_priv->hw = &pf->si->hw; 847 mdio_priv->mdio_base = ENETC_PM_IMDIO_BASE; 848 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-imdio", dev_name(dev)); 849 850 err = mdiobus_register(bus); 851 if (err) { 852 dev_err(dev, "cannot register internal MDIO bus (%d)\n", err); 853 goto free_mdio_bus; 854 } 855 856 pcs = mdio_device_create(bus, 0); 857 if (IS_ERR(pcs)) { 858 err = PTR_ERR(pcs); 859 dev_err(dev, "cannot create pcs (%d)\n", err); 860 goto unregister_mdiobus; 861 } 862 863 pcs_lynx = lynx_pcs_create(pcs); 864 if (!pcs_lynx) { 865 mdio_device_free(pcs); 866 err = -ENOMEM; 867 dev_err(dev, "cannot create lynx pcs (%d)\n", err); 868 goto unregister_mdiobus; 869 } 870 871 pf->imdio = bus; 872 pf->pcs = pcs_lynx; 873 874 return 0; 875 876 unregister_mdiobus: 877 mdiobus_unregister(bus); 878 free_mdio_bus: 879 mdiobus_free(bus); 880 return err; 881 } 882 883 static void enetc_imdio_remove(struct enetc_pf *pf) 884 { 885 if (pf->pcs) { 886 mdio_device_free(pf->pcs->mdio); 887 lynx_pcs_destroy(pf->pcs); 888 } 889 if (pf->imdio) { 890 mdiobus_unregister(pf->imdio); 891 mdiobus_free(pf->imdio); 892 } 893 } 894 895 static bool enetc_port_has_pcs(struct enetc_pf *pf) 896 { 897 return (pf->if_mode == PHY_INTERFACE_MODE_SGMII || 898 pf->if_mode == PHY_INTERFACE_MODE_2500BASEX || 899 pf->if_mode == PHY_INTERFACE_MODE_USXGMII); 900 } 901 902 static int enetc_mdiobus_create(struct enetc_pf *pf, struct device_node *node) 903 { 904 struct device_node *mdio_np; 905 int err; 906 907 mdio_np = of_get_child_by_name(node, "mdio"); 908 if (mdio_np) { 909 err = enetc_mdio_probe(pf, mdio_np); 910 911 of_node_put(mdio_np); 912 if (err) 913 return err; 914 } 915 916 if (enetc_port_has_pcs(pf)) { 917 err = enetc_imdio_create(pf); 918 if (err) { 919 enetc_mdio_remove(pf); 920 return err; 921 } 922 } 923 924 return 0; 925 } 926 927 static void enetc_mdiobus_destroy(struct enetc_pf *pf) 928 { 929 enetc_mdio_remove(pf); 930 enetc_imdio_remove(pf); 931 } 932 933 static void enetc_pl_mac_validate(struct phylink_config *config, 934 unsigned long *supported, 935 struct phylink_link_state *state) 936 { 937 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 938 939 phylink_set_port_modes(mask); 940 phylink_set(mask, Autoneg); 941 phylink_set(mask, Pause); 942 phylink_set(mask, Asym_Pause); 943 phylink_set(mask, 10baseT_Half); 944 phylink_set(mask, 10baseT_Full); 945 phylink_set(mask, 100baseT_Half); 946 phylink_set(mask, 100baseT_Full); 947 phylink_set(mask, 100baseT_Half); 948 phylink_set(mask, 1000baseT_Half); 949 phylink_set(mask, 1000baseT_Full); 950 951 if (state->interface == PHY_INTERFACE_MODE_INTERNAL || 952 state->interface == PHY_INTERFACE_MODE_2500BASEX || 953 state->interface == PHY_INTERFACE_MODE_USXGMII) { 954 phylink_set(mask, 2500baseT_Full); 955 phylink_set(mask, 2500baseX_Full); 956 } 957 958 linkmode_and(supported, supported, mask); 959 linkmode_and(state->advertising, state->advertising, mask); 960 } 961 962 static void enetc_pl_mac_config(struct phylink_config *config, 963 unsigned int mode, 964 const struct phylink_link_state *state) 965 { 966 struct enetc_pf *pf = phylink_to_enetc_pf(config); 967 struct enetc_ndev_priv *priv; 968 969 enetc_mac_config(&pf->si->hw, state->interface); 970 971 priv = netdev_priv(pf->si->ndev); 972 if (pf->pcs) 973 phylink_set_pcs(priv->phylink, &pf->pcs->pcs); 974 } 975 976 static void enetc_force_rgmii_mac(struct enetc_hw *hw, int speed, int duplex) 977 { 978 u32 old_val, val; 979 980 old_val = val = enetc_port_rd(hw, ENETC_PM0_IF_MODE); 981 982 if (speed == SPEED_1000) { 983 val &= ~ENETC_PM0_IFM_SSP_MASK; 984 val |= ENETC_PM0_IFM_SSP_1000; 985 } else if (speed == SPEED_100) { 986 val &= ~ENETC_PM0_IFM_SSP_MASK; 987 val |= ENETC_PM0_IFM_SSP_100; 988 } else if (speed == SPEED_10) { 989 val &= ~ENETC_PM0_IFM_SSP_MASK; 990 val |= ENETC_PM0_IFM_SSP_10; 991 } 992 993 if (duplex == DUPLEX_FULL) 994 val |= ENETC_PM0_IFM_FULL_DPX; 995 else 996 val &= ~ENETC_PM0_IFM_FULL_DPX; 997 998 if (val == old_val) 999 return; 1000 1001 enetc_port_wr(hw, ENETC_PM0_IF_MODE, val); 1002 } 1003 1004 static void enetc_pl_mac_link_up(struct phylink_config *config, 1005 struct phy_device *phy, unsigned int mode, 1006 phy_interface_t interface, int speed, 1007 int duplex, bool tx_pause, bool rx_pause) 1008 { 1009 struct enetc_pf *pf = phylink_to_enetc_pf(config); 1010 u32 pause_off_thresh = 0, pause_on_thresh = 0; 1011 u32 init_quanta = 0, refresh_quanta = 0; 1012 struct enetc_hw *hw = &pf->si->hw; 1013 struct enetc_ndev_priv *priv; 1014 u32 rbmr, cmd_cfg; 1015 int idx; 1016 1017 priv = netdev_priv(pf->si->ndev); 1018 if (priv->active_offloads & ENETC_F_QBV) 1019 enetc_sched_speed_set(priv, speed); 1020 1021 if (!phylink_autoneg_inband(mode) && 1022 phy_interface_mode_is_rgmii(interface)) 1023 enetc_force_rgmii_mac(hw, speed, duplex); 1024 1025 /* Flow control */ 1026 for (idx = 0; idx < priv->num_rx_rings; idx++) { 1027 rbmr = enetc_rxbdr_rd(hw, idx, ENETC_RBMR); 1028 1029 if (tx_pause) 1030 rbmr |= ENETC_RBMR_CM; 1031 else 1032 rbmr &= ~ENETC_RBMR_CM; 1033 1034 enetc_rxbdr_wr(hw, idx, ENETC_RBMR, rbmr); 1035 } 1036 1037 if (tx_pause) { 1038 /* When the port first enters congestion, send a PAUSE request 1039 * with the maximum number of quanta. When the port exits 1040 * congestion, it will automatically send a PAUSE frame with 1041 * zero quanta. 1042 */ 1043 init_quanta = 0xffff; 1044 1045 /* Also, set up the refresh timer to send follow-up PAUSE 1046 * frames at half the quanta value, in case the congestion 1047 * condition persists. 1048 */ 1049 refresh_quanta = 0xffff / 2; 1050 1051 /* Start emitting PAUSE frames when 3 large frames (or more 1052 * smaller frames) have accumulated in the FIFO waiting to be 1053 * DMAed to the RX ring. 1054 */ 1055 pause_on_thresh = 3 * ENETC_MAC_MAXFRM_SIZE; 1056 pause_off_thresh = 1 * ENETC_MAC_MAXFRM_SIZE; 1057 } 1058 1059 enetc_port_wr(hw, ENETC_PM0_PAUSE_QUANTA, init_quanta); 1060 enetc_port_wr(hw, ENETC_PM1_PAUSE_QUANTA, init_quanta); 1061 enetc_port_wr(hw, ENETC_PM0_PAUSE_THRESH, refresh_quanta); 1062 enetc_port_wr(hw, ENETC_PM1_PAUSE_THRESH, refresh_quanta); 1063 enetc_port_wr(hw, ENETC_PPAUONTR, pause_on_thresh); 1064 enetc_port_wr(hw, ENETC_PPAUOFFTR, pause_off_thresh); 1065 1066 cmd_cfg = enetc_port_rd(hw, ENETC_PM0_CMD_CFG); 1067 1068 if (rx_pause) 1069 cmd_cfg &= ~ENETC_PM0_PAUSE_IGN; 1070 else 1071 cmd_cfg |= ENETC_PM0_PAUSE_IGN; 1072 1073 enetc_port_wr(hw, ENETC_PM0_CMD_CFG, cmd_cfg); 1074 enetc_port_wr(hw, ENETC_PM1_CMD_CFG, cmd_cfg); 1075 1076 enetc_mac_enable(hw, true); 1077 } 1078 1079 static void enetc_pl_mac_link_down(struct phylink_config *config, 1080 unsigned int mode, 1081 phy_interface_t interface) 1082 { 1083 struct enetc_pf *pf = phylink_to_enetc_pf(config); 1084 1085 enetc_mac_enable(&pf->si->hw, false); 1086 } 1087 1088 static const struct phylink_mac_ops enetc_mac_phylink_ops = { 1089 .validate = enetc_pl_mac_validate, 1090 .mac_config = enetc_pl_mac_config, 1091 .mac_link_up = enetc_pl_mac_link_up, 1092 .mac_link_down = enetc_pl_mac_link_down, 1093 }; 1094 1095 static int enetc_phylink_create(struct enetc_ndev_priv *priv, 1096 struct device_node *node) 1097 { 1098 struct enetc_pf *pf = enetc_si_priv(priv->si); 1099 struct phylink *phylink; 1100 int err; 1101 1102 pf->phylink_config.dev = &priv->ndev->dev; 1103 pf->phylink_config.type = PHYLINK_NETDEV; 1104 1105 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 1106 pf->phylink_config.supported_interfaces); 1107 __set_bit(PHY_INTERFACE_MODE_SGMII, 1108 pf->phylink_config.supported_interfaces); 1109 __set_bit(PHY_INTERFACE_MODE_2500BASEX, 1110 pf->phylink_config.supported_interfaces); 1111 __set_bit(PHY_INTERFACE_MODE_USXGMII, 1112 pf->phylink_config.supported_interfaces); 1113 phy_interface_set_rgmii(pf->phylink_config.supported_interfaces); 1114 1115 phylink = phylink_create(&pf->phylink_config, of_fwnode_handle(node), 1116 pf->if_mode, &enetc_mac_phylink_ops); 1117 if (IS_ERR(phylink)) { 1118 err = PTR_ERR(phylink); 1119 return err; 1120 } 1121 1122 priv->phylink = phylink; 1123 1124 return 0; 1125 } 1126 1127 static void enetc_phylink_destroy(struct enetc_ndev_priv *priv) 1128 { 1129 if (priv->phylink) 1130 phylink_destroy(priv->phylink); 1131 } 1132 1133 /* Initialize the entire shared memory for the flow steering entries 1134 * of this port (PF + VFs) 1135 */ 1136 static int enetc_init_port_rfs_memory(struct enetc_si *si) 1137 { 1138 struct enetc_cmd_rfse rfse = {0}; 1139 struct enetc_hw *hw = &si->hw; 1140 int num_rfs, i, err = 0; 1141 u32 val; 1142 1143 val = enetc_port_rd(hw, ENETC_PRFSCAPR); 1144 num_rfs = ENETC_PRFSCAPR_GET_NUM_RFS(val); 1145 1146 for (i = 0; i < num_rfs; i++) { 1147 err = enetc_set_fs_entry(si, &rfse, i); 1148 if (err) 1149 break; 1150 } 1151 1152 return err; 1153 } 1154 1155 static int enetc_init_port_rss_memory(struct enetc_si *si) 1156 { 1157 struct enetc_hw *hw = &si->hw; 1158 int num_rss, err; 1159 int *rss_table; 1160 u32 val; 1161 1162 val = enetc_port_rd(hw, ENETC_PRSSCAPR); 1163 num_rss = ENETC_PRSSCAPR_GET_NUM_RSS(val); 1164 if (!num_rss) 1165 return 0; 1166 1167 rss_table = kcalloc(num_rss, sizeof(*rss_table), GFP_KERNEL); 1168 if (!rss_table) 1169 return -ENOMEM; 1170 1171 err = enetc_set_rss_table(si, rss_table, num_rss); 1172 1173 kfree(rss_table); 1174 1175 return err; 1176 } 1177 1178 static int enetc_pf_register_with_ierb(struct pci_dev *pdev) 1179 { 1180 struct device_node *node = pdev->dev.of_node; 1181 struct platform_device *ierb_pdev; 1182 struct device_node *ierb_node; 1183 1184 /* Don't register with the IERB if the PF itself is disabled */ 1185 if (!node || !of_device_is_available(node)) 1186 return 0; 1187 1188 ierb_node = of_find_compatible_node(NULL, NULL, 1189 "fsl,ls1028a-enetc-ierb"); 1190 if (!ierb_node || !of_device_is_available(ierb_node)) 1191 return -ENODEV; 1192 1193 ierb_pdev = of_find_device_by_node(ierb_node); 1194 of_node_put(ierb_node); 1195 1196 if (!ierb_pdev) 1197 return -EPROBE_DEFER; 1198 1199 return enetc_ierb_register_pf(ierb_pdev, pdev); 1200 } 1201 1202 static int enetc_pf_probe(struct pci_dev *pdev, 1203 const struct pci_device_id *ent) 1204 { 1205 struct device_node *node = pdev->dev.of_node; 1206 struct enetc_ndev_priv *priv; 1207 struct net_device *ndev; 1208 struct enetc_si *si; 1209 struct enetc_pf *pf; 1210 int err; 1211 1212 err = enetc_pf_register_with_ierb(pdev); 1213 if (err == -EPROBE_DEFER) 1214 return err; 1215 if (err) 1216 dev_warn(&pdev->dev, 1217 "Could not register with IERB driver: %pe, please update the device tree\n", 1218 ERR_PTR(err)); 1219 1220 err = enetc_pci_probe(pdev, KBUILD_MODNAME, sizeof(*pf)); 1221 if (err) 1222 return dev_err_probe(&pdev->dev, err, "PCI probing failed\n"); 1223 1224 si = pci_get_drvdata(pdev); 1225 if (!si->hw.port || !si->hw.global) { 1226 err = -ENODEV; 1227 dev_err(&pdev->dev, "could not map PF space, probing a VF?\n"); 1228 goto err_map_pf_space; 1229 } 1230 1231 err = enetc_setup_cbdr(&pdev->dev, &si->hw, ENETC_CBDR_DEFAULT_SIZE, 1232 &si->cbd_ring); 1233 if (err) 1234 goto err_setup_cbdr; 1235 1236 err = enetc_init_port_rfs_memory(si); 1237 if (err) { 1238 dev_err(&pdev->dev, "Failed to initialize RFS memory\n"); 1239 goto err_init_port_rfs; 1240 } 1241 1242 err = enetc_init_port_rss_memory(si); 1243 if (err) { 1244 dev_err(&pdev->dev, "Failed to initialize RSS memory\n"); 1245 goto err_init_port_rss; 1246 } 1247 1248 if (node && !of_device_is_available(node)) { 1249 dev_info(&pdev->dev, "device is disabled, skipping\n"); 1250 err = -ENODEV; 1251 goto err_device_disabled; 1252 } 1253 1254 pf = enetc_si_priv(si); 1255 pf->si = si; 1256 pf->total_vfs = pci_sriov_get_totalvfs(pdev); 1257 1258 err = enetc_setup_mac_addresses(node, pf); 1259 if (err) 1260 goto err_setup_mac_addresses; 1261 1262 enetc_configure_port(pf); 1263 1264 enetc_get_si_caps(si); 1265 1266 ndev = alloc_etherdev_mq(sizeof(*priv), ENETC_MAX_NUM_TXQS); 1267 if (!ndev) { 1268 err = -ENOMEM; 1269 dev_err(&pdev->dev, "netdev creation failed\n"); 1270 goto err_alloc_netdev; 1271 } 1272 1273 enetc_pf_netdev_setup(si, ndev, &enetc_ndev_ops); 1274 1275 priv = netdev_priv(ndev); 1276 1277 enetc_init_si_rings_params(priv); 1278 1279 err = enetc_alloc_si_resources(priv); 1280 if (err) { 1281 dev_err(&pdev->dev, "SI resource alloc failed\n"); 1282 goto err_alloc_si_res; 1283 } 1284 1285 err = enetc_configure_si(priv); 1286 if (err) { 1287 dev_err(&pdev->dev, "Failed to configure SI\n"); 1288 goto err_config_si; 1289 } 1290 1291 err = enetc_alloc_msix(priv); 1292 if (err) { 1293 dev_err(&pdev->dev, "MSIX alloc failed\n"); 1294 goto err_alloc_msix; 1295 } 1296 1297 if (!of_get_phy_mode(node, &pf->if_mode)) { 1298 err = enetc_mdiobus_create(pf, node); 1299 if (err) 1300 goto err_mdiobus_create; 1301 1302 err = enetc_phylink_create(priv, node); 1303 if (err) 1304 goto err_phylink_create; 1305 } 1306 1307 err = register_netdev(ndev); 1308 if (err) 1309 goto err_reg_netdev; 1310 1311 return 0; 1312 1313 err_reg_netdev: 1314 enetc_phylink_destroy(priv); 1315 err_phylink_create: 1316 enetc_mdiobus_destroy(pf); 1317 err_mdiobus_create: 1318 enetc_free_msix(priv); 1319 err_config_si: 1320 err_alloc_msix: 1321 enetc_free_si_resources(priv); 1322 err_alloc_si_res: 1323 si->ndev = NULL; 1324 free_netdev(ndev); 1325 err_alloc_netdev: 1326 err_init_port_rss: 1327 err_init_port_rfs: 1328 err_device_disabled: 1329 err_setup_mac_addresses: 1330 enetc_teardown_cbdr(&si->cbd_ring); 1331 err_setup_cbdr: 1332 err_map_pf_space: 1333 enetc_pci_remove(pdev); 1334 1335 return err; 1336 } 1337 1338 static void enetc_pf_remove(struct pci_dev *pdev) 1339 { 1340 struct enetc_si *si = pci_get_drvdata(pdev); 1341 struct enetc_pf *pf = enetc_si_priv(si); 1342 struct enetc_ndev_priv *priv; 1343 1344 priv = netdev_priv(si->ndev); 1345 1346 if (pf->num_vfs) 1347 enetc_sriov_configure(pdev, 0); 1348 1349 unregister_netdev(si->ndev); 1350 1351 enetc_phylink_destroy(priv); 1352 enetc_mdiobus_destroy(pf); 1353 1354 enetc_free_msix(priv); 1355 1356 enetc_free_si_resources(priv); 1357 enetc_teardown_cbdr(&si->cbd_ring); 1358 1359 free_netdev(si->ndev); 1360 1361 enetc_pci_remove(pdev); 1362 } 1363 1364 static const struct pci_device_id enetc_pf_id_table[] = { 1365 { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, ENETC_DEV_ID_PF) }, 1366 { 0, } /* End of table. */ 1367 }; 1368 MODULE_DEVICE_TABLE(pci, enetc_pf_id_table); 1369 1370 static struct pci_driver enetc_pf_driver = { 1371 .name = KBUILD_MODNAME, 1372 .id_table = enetc_pf_id_table, 1373 .probe = enetc_pf_probe, 1374 .remove = enetc_pf_remove, 1375 #ifdef CONFIG_PCI_IOV 1376 .sriov_configure = enetc_sriov_configure, 1377 #endif 1378 }; 1379 module_pci_driver(enetc_pf_driver); 1380 1381 MODULE_DESCRIPTION(ENETC_DRV_NAME_STR); 1382 MODULE_LICENSE("Dual BSD/GPL"); 1383