1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2 /* Copyright 2017-2019 NXP */
3 
4 #include <asm/unaligned.h>
5 #include <linux/mdio.h>
6 #include <linux/module.h>
7 #include <linux/fsl/enetc_mdio.h>
8 #include <linux/of_platform.h>
9 #include <linux/of_mdio.h>
10 #include <linux/of_net.h>
11 #include <linux/pcs-lynx.h>
12 #include "enetc_ierb.h"
13 #include "enetc_pf.h"
14 
15 #define ENETC_DRV_NAME_STR "ENETC PF driver"
16 
17 static void enetc_pf_get_primary_mac_addr(struct enetc_hw *hw, int si, u8 *addr)
18 {
19 	u32 upper = __raw_readl(hw->port + ENETC_PSIPMAR0(si));
20 	u16 lower = __raw_readw(hw->port + ENETC_PSIPMAR1(si));
21 
22 	put_unaligned_le32(upper, addr);
23 	put_unaligned_le16(lower, addr + 4);
24 }
25 
26 static void enetc_pf_set_primary_mac_addr(struct enetc_hw *hw, int si,
27 					  const u8 *addr)
28 {
29 	u32 upper = get_unaligned_le32(addr);
30 	u16 lower = get_unaligned_le16(addr + 4);
31 
32 	__raw_writel(upper, hw->port + ENETC_PSIPMAR0(si));
33 	__raw_writew(lower, hw->port + ENETC_PSIPMAR1(si));
34 }
35 
36 static int enetc_pf_set_mac_addr(struct net_device *ndev, void *addr)
37 {
38 	struct enetc_ndev_priv *priv = netdev_priv(ndev);
39 	struct sockaddr *saddr = addr;
40 
41 	if (!is_valid_ether_addr(saddr->sa_data))
42 		return -EADDRNOTAVAIL;
43 
44 	eth_hw_addr_set(ndev, saddr->sa_data);
45 	enetc_pf_set_primary_mac_addr(&priv->si->hw, 0, saddr->sa_data);
46 
47 	return 0;
48 }
49 
50 static void enetc_set_vlan_promisc(struct enetc_hw *hw, char si_map)
51 {
52 	u32 val = enetc_port_rd(hw, ENETC_PSIPVMR);
53 
54 	val &= ~ENETC_PSIPVMR_SET_VP(ENETC_VLAN_PROMISC_MAP_ALL);
55 	enetc_port_wr(hw, ENETC_PSIPVMR, ENETC_PSIPVMR_SET_VP(si_map) | val);
56 }
57 
58 static void enetc_enable_si_vlan_promisc(struct enetc_pf *pf, int si_idx)
59 {
60 	pf->vlan_promisc_simap |= BIT(si_idx);
61 	enetc_set_vlan_promisc(&pf->si->hw, pf->vlan_promisc_simap);
62 }
63 
64 static void enetc_disable_si_vlan_promisc(struct enetc_pf *pf, int si_idx)
65 {
66 	pf->vlan_promisc_simap &= ~BIT(si_idx);
67 	enetc_set_vlan_promisc(&pf->si->hw, pf->vlan_promisc_simap);
68 }
69 
70 static void enetc_set_isol_vlan(struct enetc_hw *hw, int si, u16 vlan, u8 qos)
71 {
72 	u32 val = 0;
73 
74 	if (vlan)
75 		val = ENETC_PSIVLAN_EN | ENETC_PSIVLAN_SET_QOS(qos) | vlan;
76 
77 	enetc_port_wr(hw, ENETC_PSIVLANR(si), val);
78 }
79 
80 static int enetc_mac_addr_hash_idx(const u8 *addr)
81 {
82 	u64 fold = __swab64(ether_addr_to_u64(addr)) >> 16;
83 	u64 mask = 0;
84 	int res = 0;
85 	int i;
86 
87 	for (i = 0; i < 8; i++)
88 		mask |= BIT_ULL(i * 6);
89 
90 	for (i = 0; i < 6; i++)
91 		res |= (hweight64(fold & (mask << i)) & 0x1) << i;
92 
93 	return res;
94 }
95 
96 static void enetc_reset_mac_addr_filter(struct enetc_mac_filter *filter)
97 {
98 	filter->mac_addr_cnt = 0;
99 
100 	bitmap_zero(filter->mac_hash_table,
101 		    ENETC_MADDR_HASH_TBL_SZ);
102 }
103 
104 static void enetc_add_mac_addr_em_filter(struct enetc_mac_filter *filter,
105 					 const unsigned char *addr)
106 {
107 	/* add exact match addr */
108 	ether_addr_copy(filter->mac_addr, addr);
109 	filter->mac_addr_cnt++;
110 }
111 
112 static void enetc_add_mac_addr_ht_filter(struct enetc_mac_filter *filter,
113 					 const unsigned char *addr)
114 {
115 	int idx = enetc_mac_addr_hash_idx(addr);
116 
117 	/* add hash table entry */
118 	__set_bit(idx, filter->mac_hash_table);
119 	filter->mac_addr_cnt++;
120 }
121 
122 static void enetc_clear_mac_ht_flt(struct enetc_si *si, int si_idx, int type)
123 {
124 	bool err = si->errata & ENETC_ERR_UCMCSWP;
125 
126 	if (type == UC) {
127 		enetc_port_wr(&si->hw, ENETC_PSIUMHFR0(si_idx, err), 0);
128 		enetc_port_wr(&si->hw, ENETC_PSIUMHFR1(si_idx), 0);
129 	} else { /* MC */
130 		enetc_port_wr(&si->hw, ENETC_PSIMMHFR0(si_idx, err), 0);
131 		enetc_port_wr(&si->hw, ENETC_PSIMMHFR1(si_idx), 0);
132 	}
133 }
134 
135 static void enetc_set_mac_ht_flt(struct enetc_si *si, int si_idx, int type,
136 				 unsigned long hash)
137 {
138 	bool err = si->errata & ENETC_ERR_UCMCSWP;
139 
140 	if (type == UC) {
141 		enetc_port_wr(&si->hw, ENETC_PSIUMHFR0(si_idx, err),
142 			      lower_32_bits(hash));
143 		enetc_port_wr(&si->hw, ENETC_PSIUMHFR1(si_idx),
144 			      upper_32_bits(hash));
145 	} else { /* MC */
146 		enetc_port_wr(&si->hw, ENETC_PSIMMHFR0(si_idx, err),
147 			      lower_32_bits(hash));
148 		enetc_port_wr(&si->hw, ENETC_PSIMMHFR1(si_idx),
149 			      upper_32_bits(hash));
150 	}
151 }
152 
153 static void enetc_sync_mac_filters(struct enetc_pf *pf)
154 {
155 	struct enetc_mac_filter *f = pf->mac_filter;
156 	struct enetc_si *si = pf->si;
157 	int i, pos;
158 
159 	pos = EMETC_MAC_ADDR_FILT_RES;
160 
161 	for (i = 0; i < MADDR_TYPE; i++, f++) {
162 		bool em = (f->mac_addr_cnt == 1) && (i == UC);
163 		bool clear = !f->mac_addr_cnt;
164 
165 		if (clear) {
166 			if (i == UC)
167 				enetc_clear_mac_flt_entry(si, pos);
168 
169 			enetc_clear_mac_ht_flt(si, 0, i);
170 			continue;
171 		}
172 
173 		/* exact match filter */
174 		if (em) {
175 			int err;
176 
177 			enetc_clear_mac_ht_flt(si, 0, UC);
178 
179 			err = enetc_set_mac_flt_entry(si, pos, f->mac_addr,
180 						      BIT(0));
181 			if (!err)
182 				continue;
183 
184 			/* fallback to HT filtering */
185 			dev_warn(&si->pdev->dev, "fallback to HT filt (%d)\n",
186 				 err);
187 		}
188 
189 		/* hash table filter, clear EM filter for UC entries */
190 		if (i == UC)
191 			enetc_clear_mac_flt_entry(si, pos);
192 
193 		enetc_set_mac_ht_flt(si, 0, i, *f->mac_hash_table);
194 	}
195 }
196 
197 static void enetc_pf_set_rx_mode(struct net_device *ndev)
198 {
199 	struct enetc_ndev_priv *priv = netdev_priv(ndev);
200 	struct enetc_pf *pf = enetc_si_priv(priv->si);
201 	struct enetc_hw *hw = &priv->si->hw;
202 	bool uprom = false, mprom = false;
203 	struct enetc_mac_filter *filter;
204 	struct netdev_hw_addr *ha;
205 	u32 psipmr = 0;
206 	bool em;
207 
208 	if (ndev->flags & IFF_PROMISC) {
209 		/* enable promisc mode for SI0 (PF) */
210 		psipmr = ENETC_PSIPMR_SET_UP(0) | ENETC_PSIPMR_SET_MP(0);
211 		uprom = true;
212 		mprom = true;
213 	} else if (ndev->flags & IFF_ALLMULTI) {
214 		/* enable multi cast promisc mode for SI0 (PF) */
215 		psipmr = ENETC_PSIPMR_SET_MP(0);
216 		mprom = true;
217 	}
218 
219 	/* first 2 filter entries belong to PF */
220 	if (!uprom) {
221 		/* Update unicast filters */
222 		filter = &pf->mac_filter[UC];
223 		enetc_reset_mac_addr_filter(filter);
224 
225 		em = (netdev_uc_count(ndev) == 1);
226 		netdev_for_each_uc_addr(ha, ndev) {
227 			if (em) {
228 				enetc_add_mac_addr_em_filter(filter, ha->addr);
229 				break;
230 			}
231 
232 			enetc_add_mac_addr_ht_filter(filter, ha->addr);
233 		}
234 	}
235 
236 	if (!mprom) {
237 		/* Update multicast filters */
238 		filter = &pf->mac_filter[MC];
239 		enetc_reset_mac_addr_filter(filter);
240 
241 		netdev_for_each_mc_addr(ha, ndev) {
242 			if (!is_multicast_ether_addr(ha->addr))
243 				continue;
244 
245 			enetc_add_mac_addr_ht_filter(filter, ha->addr);
246 		}
247 	}
248 
249 	if (!uprom || !mprom)
250 		/* update PF entries */
251 		enetc_sync_mac_filters(pf);
252 
253 	psipmr |= enetc_port_rd(hw, ENETC_PSIPMR) &
254 		  ~(ENETC_PSIPMR_SET_UP(0) | ENETC_PSIPMR_SET_MP(0));
255 	enetc_port_wr(hw, ENETC_PSIPMR, psipmr);
256 }
257 
258 static void enetc_set_vlan_ht_filter(struct enetc_hw *hw, int si_idx,
259 				     unsigned long hash)
260 {
261 	enetc_port_wr(hw, ENETC_PSIVHFR0(si_idx), lower_32_bits(hash));
262 	enetc_port_wr(hw, ENETC_PSIVHFR1(si_idx), upper_32_bits(hash));
263 }
264 
265 static int enetc_vid_hash_idx(unsigned int vid)
266 {
267 	int res = 0;
268 	int i;
269 
270 	for (i = 0; i < 6; i++)
271 		res |= (hweight8(vid & (BIT(i) | BIT(i + 6))) & 0x1) << i;
272 
273 	return res;
274 }
275 
276 static void enetc_sync_vlan_ht_filter(struct enetc_pf *pf, bool rehash)
277 {
278 	int i;
279 
280 	if (rehash) {
281 		bitmap_zero(pf->vlan_ht_filter, ENETC_VLAN_HT_SIZE);
282 
283 		for_each_set_bit(i, pf->active_vlans, VLAN_N_VID) {
284 			int hidx = enetc_vid_hash_idx(i);
285 
286 			__set_bit(hidx, pf->vlan_ht_filter);
287 		}
288 	}
289 
290 	enetc_set_vlan_ht_filter(&pf->si->hw, 0, *pf->vlan_ht_filter);
291 }
292 
293 static int enetc_vlan_rx_add_vid(struct net_device *ndev, __be16 prot, u16 vid)
294 {
295 	struct enetc_ndev_priv *priv = netdev_priv(ndev);
296 	struct enetc_pf *pf = enetc_si_priv(priv->si);
297 	int idx;
298 
299 	__set_bit(vid, pf->active_vlans);
300 
301 	idx = enetc_vid_hash_idx(vid);
302 	if (!__test_and_set_bit(idx, pf->vlan_ht_filter))
303 		enetc_sync_vlan_ht_filter(pf, false);
304 
305 	return 0;
306 }
307 
308 static int enetc_vlan_rx_del_vid(struct net_device *ndev, __be16 prot, u16 vid)
309 {
310 	struct enetc_ndev_priv *priv = netdev_priv(ndev);
311 	struct enetc_pf *pf = enetc_si_priv(priv->si);
312 
313 	__clear_bit(vid, pf->active_vlans);
314 	enetc_sync_vlan_ht_filter(pf, true);
315 
316 	return 0;
317 }
318 
319 static void enetc_set_loopback(struct net_device *ndev, bool en)
320 {
321 	struct enetc_ndev_priv *priv = netdev_priv(ndev);
322 	struct enetc_si *si = priv->si;
323 	u32 reg;
324 
325 	reg = enetc_port_mac_rd(si, ENETC_PM0_IF_MODE);
326 	if (reg & ENETC_PM0_IFM_RG) {
327 		/* RGMII mode */
328 		reg = (reg & ~ENETC_PM0_IFM_RLP) |
329 		      (en ? ENETC_PM0_IFM_RLP : 0);
330 		enetc_port_mac_wr(si, ENETC_PM0_IF_MODE, reg);
331 	} else {
332 		/* assume SGMII mode */
333 		reg = enetc_port_mac_rd(si, ENETC_PM0_CMD_CFG);
334 		reg = (reg & ~ENETC_PM0_CMD_XGLP) |
335 		      (en ? ENETC_PM0_CMD_XGLP : 0);
336 		reg = (reg & ~ENETC_PM0_CMD_PHY_TX_EN) |
337 		      (en ? ENETC_PM0_CMD_PHY_TX_EN : 0);
338 		enetc_port_mac_wr(si, ENETC_PM0_CMD_CFG, reg);
339 	}
340 }
341 
342 static int enetc_pf_set_vf_mac(struct net_device *ndev, int vf, u8 *mac)
343 {
344 	struct enetc_ndev_priv *priv = netdev_priv(ndev);
345 	struct enetc_pf *pf = enetc_si_priv(priv->si);
346 	struct enetc_vf_state *vf_state;
347 
348 	if (vf >= pf->total_vfs)
349 		return -EINVAL;
350 
351 	if (!is_valid_ether_addr(mac))
352 		return -EADDRNOTAVAIL;
353 
354 	vf_state = &pf->vf_state[vf];
355 	vf_state->flags |= ENETC_VF_FLAG_PF_SET_MAC;
356 	enetc_pf_set_primary_mac_addr(&priv->si->hw, vf + 1, mac);
357 	return 0;
358 }
359 
360 static int enetc_pf_set_vf_vlan(struct net_device *ndev, int vf, u16 vlan,
361 				u8 qos, __be16 proto)
362 {
363 	struct enetc_ndev_priv *priv = netdev_priv(ndev);
364 	struct enetc_pf *pf = enetc_si_priv(priv->si);
365 
366 	if (priv->si->errata & ENETC_ERR_VLAN_ISOL)
367 		return -EOPNOTSUPP;
368 
369 	if (vf >= pf->total_vfs)
370 		return -EINVAL;
371 
372 	if (proto != htons(ETH_P_8021Q))
373 		/* only C-tags supported for now */
374 		return -EPROTONOSUPPORT;
375 
376 	enetc_set_isol_vlan(&priv->si->hw, vf + 1, vlan, qos);
377 	return 0;
378 }
379 
380 static int enetc_pf_set_vf_spoofchk(struct net_device *ndev, int vf, bool en)
381 {
382 	struct enetc_ndev_priv *priv = netdev_priv(ndev);
383 	struct enetc_pf *pf = enetc_si_priv(priv->si);
384 	u32 cfgr;
385 
386 	if (vf >= pf->total_vfs)
387 		return -EINVAL;
388 
389 	cfgr = enetc_port_rd(&priv->si->hw, ENETC_PSICFGR0(vf + 1));
390 	cfgr = (cfgr & ~ENETC_PSICFGR0_ASE) | (en ? ENETC_PSICFGR0_ASE : 0);
391 	enetc_port_wr(&priv->si->hw, ENETC_PSICFGR0(vf + 1), cfgr);
392 
393 	return 0;
394 }
395 
396 static int enetc_setup_mac_address(struct device_node *np, struct enetc_pf *pf,
397 				   int si)
398 {
399 	struct device *dev = &pf->si->pdev->dev;
400 	struct enetc_hw *hw = &pf->si->hw;
401 	u8 mac_addr[ETH_ALEN] = { 0 };
402 	int err;
403 
404 	/* (1) try to get the MAC address from the device tree */
405 	if (np) {
406 		err = of_get_mac_address(np, mac_addr);
407 		if (err == -EPROBE_DEFER)
408 			return err;
409 	}
410 
411 	/* (2) bootloader supplied MAC address */
412 	if (is_zero_ether_addr(mac_addr))
413 		enetc_pf_get_primary_mac_addr(hw, si, mac_addr);
414 
415 	/* (3) choose a random one */
416 	if (is_zero_ether_addr(mac_addr)) {
417 		eth_random_addr(mac_addr);
418 		dev_info(dev, "no MAC address specified for SI%d, using %pM\n",
419 			 si, mac_addr);
420 	}
421 
422 	enetc_pf_set_primary_mac_addr(hw, si, mac_addr);
423 
424 	return 0;
425 }
426 
427 static int enetc_setup_mac_addresses(struct device_node *np,
428 				     struct enetc_pf *pf)
429 {
430 	int err, i;
431 
432 	/* The PF might take its MAC from the device tree */
433 	err = enetc_setup_mac_address(np, pf, 0);
434 	if (err)
435 		return err;
436 
437 	for (i = 0; i < pf->total_vfs; i++) {
438 		err = enetc_setup_mac_address(NULL, pf, i + 1);
439 		if (err)
440 			return err;
441 	}
442 
443 	return 0;
444 }
445 
446 static void enetc_port_assign_rfs_entries(struct enetc_si *si)
447 {
448 	struct enetc_pf *pf = enetc_si_priv(si);
449 	struct enetc_hw *hw = &si->hw;
450 	int num_entries, vf_entries, i;
451 	u32 val;
452 
453 	/* split RFS entries between functions */
454 	val = enetc_port_rd(hw, ENETC_PRFSCAPR);
455 	num_entries = ENETC_PRFSCAPR_GET_NUM_RFS(val);
456 	vf_entries = num_entries / (pf->total_vfs + 1);
457 
458 	for (i = 0; i < pf->total_vfs; i++)
459 		enetc_port_wr(hw, ENETC_PSIRFSCFGR(i + 1), vf_entries);
460 	enetc_port_wr(hw, ENETC_PSIRFSCFGR(0),
461 		      num_entries - vf_entries * pf->total_vfs);
462 
463 	/* enable RFS on port */
464 	enetc_port_wr(hw, ENETC_PRFSMR, ENETC_PRFSMR_RFSE);
465 }
466 
467 static void enetc_port_si_configure(struct enetc_si *si)
468 {
469 	struct enetc_pf *pf = enetc_si_priv(si);
470 	struct enetc_hw *hw = &si->hw;
471 	int num_rings, i;
472 	u32 val;
473 
474 	val = enetc_port_rd(hw, ENETC_PCAPR0);
475 	num_rings = min(ENETC_PCAPR0_RXBDR(val), ENETC_PCAPR0_TXBDR(val));
476 
477 	val = ENETC_PSICFGR0_SET_TXBDR(ENETC_PF_NUM_RINGS);
478 	val |= ENETC_PSICFGR0_SET_RXBDR(ENETC_PF_NUM_RINGS);
479 
480 	if (unlikely(num_rings < ENETC_PF_NUM_RINGS)) {
481 		val = ENETC_PSICFGR0_SET_TXBDR(num_rings);
482 		val |= ENETC_PSICFGR0_SET_RXBDR(num_rings);
483 
484 		dev_warn(&si->pdev->dev, "Found %d rings, expected %d!\n",
485 			 num_rings, ENETC_PF_NUM_RINGS);
486 
487 		num_rings = 0;
488 	}
489 
490 	/* Add default one-time settings for SI0 (PF) */
491 	val |= ENETC_PSICFGR0_SIVC(ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S);
492 
493 	enetc_port_wr(hw, ENETC_PSICFGR0(0), val);
494 
495 	if (num_rings)
496 		num_rings -= ENETC_PF_NUM_RINGS;
497 
498 	/* Configure the SIs for each available VF */
499 	val = ENETC_PSICFGR0_SIVC(ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S);
500 	val |= ENETC_PSICFGR0_VTE | ENETC_PSICFGR0_SIVIE;
501 
502 	if (num_rings) {
503 		num_rings /= pf->total_vfs;
504 		val |= ENETC_PSICFGR0_SET_TXBDR(num_rings);
505 		val |= ENETC_PSICFGR0_SET_RXBDR(num_rings);
506 	}
507 
508 	for (i = 0; i < pf->total_vfs; i++)
509 		enetc_port_wr(hw, ENETC_PSICFGR0(i + 1), val);
510 
511 	/* Port level VLAN settings */
512 	val = ENETC_PVCLCTR_OVTPIDL(ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S);
513 	enetc_port_wr(hw, ENETC_PVCLCTR, val);
514 	/* use outer tag for VLAN filtering */
515 	enetc_port_wr(hw, ENETC_PSIVLANFMR, ENETC_PSIVLANFMR_VS);
516 }
517 
518 void enetc_set_ptcmsdur(struct enetc_hw *hw, u32 *max_sdu)
519 {
520 	int tc;
521 
522 	for (tc = 0; tc < 8; tc++) {
523 		u32 val = ENETC_MAC_MAXFRM_SIZE;
524 
525 		if (max_sdu[tc])
526 			val = max_sdu[tc] + VLAN_ETH_HLEN;
527 
528 		enetc_port_wr(hw, ENETC_PTCMSDUR(tc), val);
529 	}
530 }
531 
532 void enetc_reset_ptcmsdur(struct enetc_hw *hw)
533 {
534 	int tc;
535 
536 	for (tc = 0; tc < 8; tc++)
537 		enetc_port_wr(hw, ENETC_PTCMSDUR(tc), ENETC_MAC_MAXFRM_SIZE);
538 }
539 
540 static void enetc_configure_port_mac(struct enetc_si *si)
541 {
542 	struct enetc_hw *hw = &si->hw;
543 
544 	enetc_port_mac_wr(si, ENETC_PM0_MAXFRM,
545 			  ENETC_SET_MAXFRM(ENETC_RX_MAXFRM_SIZE));
546 
547 	enetc_reset_ptcmsdur(hw);
548 
549 	enetc_port_mac_wr(si, ENETC_PM0_CMD_CFG, ENETC_PM0_CMD_PHY_TX_EN |
550 			  ENETC_PM0_CMD_TXP | ENETC_PM0_PROMISC);
551 
552 	/* On LS1028A, the MAC RX FIFO defaults to 2, which is too high
553 	 * and may lead to RX lock-up under traffic. Set it to 1 instead,
554 	 * as recommended by the hardware team.
555 	 */
556 	enetc_port_mac_wr(si, ENETC_PM0_RX_FIFO, ENETC_PM0_RX_FIFO_VAL);
557 }
558 
559 static void enetc_mac_config(struct enetc_si *si, phy_interface_t phy_mode)
560 {
561 	u32 val;
562 
563 	if (phy_interface_mode_is_rgmii(phy_mode)) {
564 		val = enetc_port_mac_rd(si, ENETC_PM0_IF_MODE);
565 		val &= ~(ENETC_PM0_IFM_EN_AUTO | ENETC_PM0_IFM_IFMODE_MASK);
566 		val |= ENETC_PM0_IFM_IFMODE_GMII | ENETC_PM0_IFM_RG;
567 		enetc_port_mac_wr(si, ENETC_PM0_IF_MODE, val);
568 	}
569 
570 	if (phy_mode == PHY_INTERFACE_MODE_USXGMII) {
571 		val = ENETC_PM0_IFM_FULL_DPX | ENETC_PM0_IFM_IFMODE_XGMII;
572 		enetc_port_mac_wr(si, ENETC_PM0_IF_MODE, val);
573 	}
574 }
575 
576 static void enetc_mac_enable(struct enetc_si *si, bool en)
577 {
578 	u32 val = enetc_port_mac_rd(si, ENETC_PM0_CMD_CFG);
579 
580 	val &= ~(ENETC_PM0_TX_EN | ENETC_PM0_RX_EN);
581 	val |= en ? (ENETC_PM0_TX_EN | ENETC_PM0_RX_EN) : 0;
582 
583 	enetc_port_mac_wr(si, ENETC_PM0_CMD_CFG, val);
584 }
585 
586 static void enetc_configure_port(struct enetc_pf *pf)
587 {
588 	u8 hash_key[ENETC_RSSHASH_KEY_SIZE];
589 	struct enetc_hw *hw = &pf->si->hw;
590 
591 	enetc_configure_port_mac(pf->si);
592 
593 	enetc_port_si_configure(pf->si);
594 
595 	/* set up hash key */
596 	get_random_bytes(hash_key, ENETC_RSSHASH_KEY_SIZE);
597 	enetc_set_rss_key(hw, hash_key);
598 
599 	/* split up RFS entries */
600 	enetc_port_assign_rfs_entries(pf->si);
601 
602 	/* enforce VLAN promisc mode for all SIs */
603 	pf->vlan_promisc_simap = ENETC_VLAN_PROMISC_MAP_ALL;
604 	enetc_set_vlan_promisc(hw, pf->vlan_promisc_simap);
605 
606 	enetc_port_wr(hw, ENETC_PSIPMR, 0);
607 
608 	/* enable port */
609 	enetc_port_wr(hw, ENETC_PMR, ENETC_PMR_EN);
610 }
611 
612 /* Messaging */
613 static u16 enetc_msg_pf_set_vf_primary_mac_addr(struct enetc_pf *pf,
614 						int vf_id)
615 {
616 	struct enetc_vf_state *vf_state = &pf->vf_state[vf_id];
617 	struct enetc_msg_swbd *msg = &pf->rxmsg[vf_id];
618 	struct enetc_msg_cmd_set_primary_mac *cmd;
619 	struct device *dev = &pf->si->pdev->dev;
620 	u16 cmd_id;
621 	char *addr;
622 
623 	cmd = (struct enetc_msg_cmd_set_primary_mac *)msg->vaddr;
624 	cmd_id = cmd->header.id;
625 	if (cmd_id != ENETC_MSG_CMD_MNG_ADD)
626 		return ENETC_MSG_CMD_STATUS_FAIL;
627 
628 	addr = cmd->mac.sa_data;
629 	if (vf_state->flags & ENETC_VF_FLAG_PF_SET_MAC)
630 		dev_warn(dev, "Attempt to override PF set mac addr for VF%d\n",
631 			 vf_id);
632 	else
633 		enetc_pf_set_primary_mac_addr(&pf->si->hw, vf_id + 1, addr);
634 
635 	return ENETC_MSG_CMD_STATUS_OK;
636 }
637 
638 void enetc_msg_handle_rxmsg(struct enetc_pf *pf, int vf_id, u16 *status)
639 {
640 	struct enetc_msg_swbd *msg = &pf->rxmsg[vf_id];
641 	struct device *dev = &pf->si->pdev->dev;
642 	struct enetc_msg_cmd_header *cmd_hdr;
643 	u16 cmd_type;
644 
645 	*status = ENETC_MSG_CMD_STATUS_OK;
646 	cmd_hdr = (struct enetc_msg_cmd_header *)msg->vaddr;
647 	cmd_type = cmd_hdr->type;
648 
649 	switch (cmd_type) {
650 	case ENETC_MSG_CMD_MNG_MAC:
651 		*status = enetc_msg_pf_set_vf_primary_mac_addr(pf, vf_id);
652 		break;
653 	default:
654 		dev_err(dev, "command not supported (cmd_type: 0x%x)\n",
655 			cmd_type);
656 	}
657 }
658 
659 #ifdef CONFIG_PCI_IOV
660 static int enetc_sriov_configure(struct pci_dev *pdev, int num_vfs)
661 {
662 	struct enetc_si *si = pci_get_drvdata(pdev);
663 	struct enetc_pf *pf = enetc_si_priv(si);
664 	int err;
665 
666 	if (!num_vfs) {
667 		enetc_msg_psi_free(pf);
668 		kfree(pf->vf_state);
669 		pf->num_vfs = 0;
670 		pci_disable_sriov(pdev);
671 	} else {
672 		pf->num_vfs = num_vfs;
673 
674 		pf->vf_state = kcalloc(num_vfs, sizeof(struct enetc_vf_state),
675 				       GFP_KERNEL);
676 		if (!pf->vf_state) {
677 			pf->num_vfs = 0;
678 			return -ENOMEM;
679 		}
680 
681 		err = enetc_msg_psi_init(pf);
682 		if (err) {
683 			dev_err(&pdev->dev, "enetc_msg_psi_init (%d)\n", err);
684 			goto err_msg_psi;
685 		}
686 
687 		err = pci_enable_sriov(pdev, num_vfs);
688 		if (err) {
689 			dev_err(&pdev->dev, "pci_enable_sriov err %d\n", err);
690 			goto err_en_sriov;
691 		}
692 	}
693 
694 	return num_vfs;
695 
696 err_en_sriov:
697 	enetc_msg_psi_free(pf);
698 err_msg_psi:
699 	kfree(pf->vf_state);
700 	pf->num_vfs = 0;
701 
702 	return err;
703 }
704 #else
705 #define enetc_sriov_configure(pdev, num_vfs)	(void)0
706 #endif
707 
708 static int enetc_pf_set_features(struct net_device *ndev,
709 				 netdev_features_t features)
710 {
711 	netdev_features_t changed = ndev->features ^ features;
712 	struct enetc_ndev_priv *priv = netdev_priv(ndev);
713 	int err;
714 
715 	if (changed & NETIF_F_HW_TC) {
716 		err = enetc_set_psfp(ndev, !!(features & NETIF_F_HW_TC));
717 		if (err)
718 			return err;
719 	}
720 
721 	if (changed & NETIF_F_HW_VLAN_CTAG_FILTER) {
722 		struct enetc_pf *pf = enetc_si_priv(priv->si);
723 
724 		if (!!(features & NETIF_F_HW_VLAN_CTAG_FILTER))
725 			enetc_disable_si_vlan_promisc(pf, 0);
726 		else
727 			enetc_enable_si_vlan_promisc(pf, 0);
728 	}
729 
730 	if (changed & NETIF_F_LOOPBACK)
731 		enetc_set_loopback(ndev, !!(features & NETIF_F_LOOPBACK));
732 
733 	enetc_set_features(ndev, features);
734 
735 	return 0;
736 }
737 
738 static int enetc_pf_setup_tc(struct net_device *ndev, enum tc_setup_type type,
739 			     void *type_data)
740 {
741 	switch (type) {
742 	case TC_QUERY_CAPS:
743 		return enetc_qos_query_caps(ndev, type_data);
744 	case TC_SETUP_QDISC_MQPRIO:
745 		return enetc_setup_tc_mqprio(ndev, type_data);
746 	case TC_SETUP_QDISC_TAPRIO:
747 		return enetc_setup_tc_taprio(ndev, type_data);
748 	case TC_SETUP_QDISC_CBS:
749 		return enetc_setup_tc_cbs(ndev, type_data);
750 	case TC_SETUP_QDISC_ETF:
751 		return enetc_setup_tc_txtime(ndev, type_data);
752 	case TC_SETUP_BLOCK:
753 		return enetc_setup_tc_psfp(ndev, type_data);
754 	default:
755 		return -EOPNOTSUPP;
756 	}
757 }
758 
759 static const struct net_device_ops enetc_ndev_ops = {
760 	.ndo_open		= enetc_open,
761 	.ndo_stop		= enetc_close,
762 	.ndo_start_xmit		= enetc_xmit,
763 	.ndo_get_stats		= enetc_get_stats,
764 	.ndo_set_mac_address	= enetc_pf_set_mac_addr,
765 	.ndo_set_rx_mode	= enetc_pf_set_rx_mode,
766 	.ndo_vlan_rx_add_vid	= enetc_vlan_rx_add_vid,
767 	.ndo_vlan_rx_kill_vid	= enetc_vlan_rx_del_vid,
768 	.ndo_set_vf_mac		= enetc_pf_set_vf_mac,
769 	.ndo_set_vf_vlan	= enetc_pf_set_vf_vlan,
770 	.ndo_set_vf_spoofchk	= enetc_pf_set_vf_spoofchk,
771 	.ndo_set_features	= enetc_pf_set_features,
772 	.ndo_eth_ioctl		= enetc_ioctl,
773 	.ndo_setup_tc		= enetc_pf_setup_tc,
774 	.ndo_bpf		= enetc_setup_bpf,
775 	.ndo_xdp_xmit		= enetc_xdp_xmit,
776 };
777 
778 static void enetc_pf_netdev_setup(struct enetc_si *si, struct net_device *ndev,
779 				  const struct net_device_ops *ndev_ops)
780 {
781 	struct enetc_ndev_priv *priv = netdev_priv(ndev);
782 
783 	SET_NETDEV_DEV(ndev, &si->pdev->dev);
784 	priv->ndev = ndev;
785 	priv->si = si;
786 	priv->dev = &si->pdev->dev;
787 	si->ndev = ndev;
788 
789 	priv->msg_enable = (NETIF_MSG_WOL << 1) - 1;
790 	ndev->netdev_ops = ndev_ops;
791 	enetc_set_ethtool_ops(ndev);
792 	ndev->watchdog_timeo = 5 * HZ;
793 	ndev->max_mtu = ENETC_MAX_MTU;
794 
795 	ndev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM |
796 			    NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
797 			    NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_LOOPBACK |
798 			    NETIF_F_HW_CSUM | NETIF_F_TSO | NETIF_F_TSO6;
799 	ndev->features = NETIF_F_HIGHDMA | NETIF_F_SG | NETIF_F_RXCSUM |
800 			 NETIF_F_HW_VLAN_CTAG_TX |
801 			 NETIF_F_HW_VLAN_CTAG_RX |
802 			 NETIF_F_HW_CSUM | NETIF_F_TSO | NETIF_F_TSO6;
803 	ndev->vlan_features = NETIF_F_SG | NETIF_F_HW_CSUM |
804 			      NETIF_F_TSO | NETIF_F_TSO6;
805 
806 	if (si->num_rss)
807 		ndev->hw_features |= NETIF_F_RXHASH;
808 
809 	ndev->priv_flags |= IFF_UNICAST_FLT;
810 	ndev->xdp_features = NETDEV_XDP_ACT_BASIC | NETDEV_XDP_ACT_REDIRECT |
811 			     NETDEV_XDP_ACT_NDO_XMIT | NETDEV_XDP_ACT_RX_SG |
812 			     NETDEV_XDP_ACT_NDO_XMIT_SG;
813 
814 	if (si->hw_features & ENETC_SI_F_PSFP && !enetc_psfp_enable(priv)) {
815 		priv->active_offloads |= ENETC_F_QCI;
816 		ndev->features |= NETIF_F_HW_TC;
817 		ndev->hw_features |= NETIF_F_HW_TC;
818 	}
819 
820 	/* pick up primary MAC address from SI */
821 	enetc_load_primary_mac_addr(&si->hw, ndev);
822 }
823 
824 static int enetc_mdio_probe(struct enetc_pf *pf, struct device_node *np)
825 {
826 	struct device *dev = &pf->si->pdev->dev;
827 	struct enetc_mdio_priv *mdio_priv;
828 	struct mii_bus *bus;
829 	int err;
830 
831 	bus = devm_mdiobus_alloc_size(dev, sizeof(*mdio_priv));
832 	if (!bus)
833 		return -ENOMEM;
834 
835 	bus->name = "Freescale ENETC MDIO Bus";
836 	bus->read = enetc_mdio_read_c22;
837 	bus->write = enetc_mdio_write_c22;
838 	bus->read_c45 = enetc_mdio_read_c45;
839 	bus->write_c45 = enetc_mdio_write_c45;
840 	bus->parent = dev;
841 	mdio_priv = bus->priv;
842 	mdio_priv->hw = &pf->si->hw;
843 	mdio_priv->mdio_base = ENETC_EMDIO_BASE;
844 	snprintf(bus->id, MII_BUS_ID_SIZE, "%s", dev_name(dev));
845 
846 	err = of_mdiobus_register(bus, np);
847 	if (err)
848 		return dev_err_probe(dev, err, "cannot register MDIO bus\n");
849 
850 	pf->mdio = bus;
851 
852 	return 0;
853 }
854 
855 static void enetc_mdio_remove(struct enetc_pf *pf)
856 {
857 	if (pf->mdio)
858 		mdiobus_unregister(pf->mdio);
859 }
860 
861 static int enetc_imdio_create(struct enetc_pf *pf)
862 {
863 	struct device *dev = &pf->si->pdev->dev;
864 	struct enetc_mdio_priv *mdio_priv;
865 	struct phylink_pcs *phylink_pcs;
866 	struct mii_bus *bus;
867 	int err;
868 
869 	bus = mdiobus_alloc_size(sizeof(*mdio_priv));
870 	if (!bus)
871 		return -ENOMEM;
872 
873 	bus->name = "Freescale ENETC internal MDIO Bus";
874 	bus->read = enetc_mdio_read_c22;
875 	bus->write = enetc_mdio_write_c22;
876 	bus->read_c45 = enetc_mdio_read_c45;
877 	bus->write_c45 = enetc_mdio_write_c45;
878 	bus->parent = dev;
879 	bus->phy_mask = ~0;
880 	mdio_priv = bus->priv;
881 	mdio_priv->hw = &pf->si->hw;
882 	mdio_priv->mdio_base = ENETC_PM_IMDIO_BASE;
883 	snprintf(bus->id, MII_BUS_ID_SIZE, "%s-imdio", dev_name(dev));
884 
885 	err = mdiobus_register(bus);
886 	if (err) {
887 		dev_err(dev, "cannot register internal MDIO bus (%d)\n", err);
888 		goto free_mdio_bus;
889 	}
890 
891 	phylink_pcs = lynx_pcs_create_mdiodev(bus, 0);
892 	if (IS_ERR(phylink_pcs)) {
893 		err = PTR_ERR(phylink_pcs);
894 		dev_err(dev, "cannot create lynx pcs (%d)\n", err);
895 		goto unregister_mdiobus;
896 	}
897 
898 	pf->imdio = bus;
899 	pf->pcs = phylink_pcs;
900 
901 	return 0;
902 
903 unregister_mdiobus:
904 	mdiobus_unregister(bus);
905 free_mdio_bus:
906 	mdiobus_free(bus);
907 	return err;
908 }
909 
910 static void enetc_imdio_remove(struct enetc_pf *pf)
911 {
912 	if (pf->pcs)
913 		lynx_pcs_destroy(pf->pcs);
914 	if (pf->imdio) {
915 		mdiobus_unregister(pf->imdio);
916 		mdiobus_free(pf->imdio);
917 	}
918 }
919 
920 static bool enetc_port_has_pcs(struct enetc_pf *pf)
921 {
922 	return (pf->if_mode == PHY_INTERFACE_MODE_SGMII ||
923 		pf->if_mode == PHY_INTERFACE_MODE_2500BASEX ||
924 		pf->if_mode == PHY_INTERFACE_MODE_USXGMII);
925 }
926 
927 static int enetc_mdiobus_create(struct enetc_pf *pf, struct device_node *node)
928 {
929 	struct device_node *mdio_np;
930 	int err;
931 
932 	mdio_np = of_get_child_by_name(node, "mdio");
933 	if (mdio_np) {
934 		err = enetc_mdio_probe(pf, mdio_np);
935 
936 		of_node_put(mdio_np);
937 		if (err)
938 			return err;
939 	}
940 
941 	if (enetc_port_has_pcs(pf)) {
942 		err = enetc_imdio_create(pf);
943 		if (err) {
944 			enetc_mdio_remove(pf);
945 			return err;
946 		}
947 	}
948 
949 	return 0;
950 }
951 
952 static void enetc_mdiobus_destroy(struct enetc_pf *pf)
953 {
954 	enetc_mdio_remove(pf);
955 	enetc_imdio_remove(pf);
956 }
957 
958 static struct phylink_pcs *
959 enetc_pl_mac_select_pcs(struct phylink_config *config, phy_interface_t iface)
960 {
961 	struct enetc_pf *pf = phylink_to_enetc_pf(config);
962 
963 	return pf->pcs;
964 }
965 
966 static void enetc_pl_mac_config(struct phylink_config *config,
967 				unsigned int mode,
968 				const struct phylink_link_state *state)
969 {
970 	struct enetc_pf *pf = phylink_to_enetc_pf(config);
971 
972 	enetc_mac_config(pf->si, state->interface);
973 }
974 
975 static void enetc_force_rgmii_mac(struct enetc_si *si, int speed, int duplex)
976 {
977 	u32 old_val, val;
978 
979 	old_val = val = enetc_port_mac_rd(si, ENETC_PM0_IF_MODE);
980 
981 	if (speed == SPEED_1000) {
982 		val &= ~ENETC_PM0_IFM_SSP_MASK;
983 		val |= ENETC_PM0_IFM_SSP_1000;
984 	} else if (speed == SPEED_100) {
985 		val &= ~ENETC_PM0_IFM_SSP_MASK;
986 		val |= ENETC_PM0_IFM_SSP_100;
987 	} else if (speed == SPEED_10) {
988 		val &= ~ENETC_PM0_IFM_SSP_MASK;
989 		val |= ENETC_PM0_IFM_SSP_10;
990 	}
991 
992 	if (duplex == DUPLEX_FULL)
993 		val |= ENETC_PM0_IFM_FULL_DPX;
994 	else
995 		val &= ~ENETC_PM0_IFM_FULL_DPX;
996 
997 	if (val == old_val)
998 		return;
999 
1000 	enetc_port_mac_wr(si, ENETC_PM0_IF_MODE, val);
1001 }
1002 
1003 static void enetc_pl_mac_link_up(struct phylink_config *config,
1004 				 struct phy_device *phy, unsigned int mode,
1005 				 phy_interface_t interface, int speed,
1006 				 int duplex, bool tx_pause, bool rx_pause)
1007 {
1008 	struct enetc_pf *pf = phylink_to_enetc_pf(config);
1009 	u32 pause_off_thresh = 0, pause_on_thresh = 0;
1010 	u32 init_quanta = 0, refresh_quanta = 0;
1011 	struct enetc_hw *hw = &pf->si->hw;
1012 	struct enetc_si *si = pf->si;
1013 	struct enetc_ndev_priv *priv;
1014 	u32 rbmr, cmd_cfg;
1015 	int idx;
1016 
1017 	priv = netdev_priv(pf->si->ndev);
1018 
1019 	if (pf->si->hw_features & ENETC_SI_F_QBV)
1020 		enetc_sched_speed_set(priv, speed);
1021 
1022 	if (!phylink_autoneg_inband(mode) &&
1023 	    phy_interface_mode_is_rgmii(interface))
1024 		enetc_force_rgmii_mac(si, speed, duplex);
1025 
1026 	/* Flow control */
1027 	for (idx = 0; idx < priv->num_rx_rings; idx++) {
1028 		rbmr = enetc_rxbdr_rd(hw, idx, ENETC_RBMR);
1029 
1030 		if (tx_pause)
1031 			rbmr |= ENETC_RBMR_CM;
1032 		else
1033 			rbmr &= ~ENETC_RBMR_CM;
1034 
1035 		enetc_rxbdr_wr(hw, idx, ENETC_RBMR, rbmr);
1036 	}
1037 
1038 	if (tx_pause) {
1039 		/* When the port first enters congestion, send a PAUSE request
1040 		 * with the maximum number of quanta. When the port exits
1041 		 * congestion, it will automatically send a PAUSE frame with
1042 		 * zero quanta.
1043 		 */
1044 		init_quanta = 0xffff;
1045 
1046 		/* Also, set up the refresh timer to send follow-up PAUSE
1047 		 * frames at half the quanta value, in case the congestion
1048 		 * condition persists.
1049 		 */
1050 		refresh_quanta = 0xffff / 2;
1051 
1052 		/* Start emitting PAUSE frames when 3 large frames (or more
1053 		 * smaller frames) have accumulated in the FIFO waiting to be
1054 		 * DMAed to the RX ring.
1055 		 */
1056 		pause_on_thresh = 3 * ENETC_MAC_MAXFRM_SIZE;
1057 		pause_off_thresh = 1 * ENETC_MAC_MAXFRM_SIZE;
1058 	}
1059 
1060 	enetc_port_mac_wr(si, ENETC_PM0_PAUSE_QUANTA, init_quanta);
1061 	enetc_port_mac_wr(si, ENETC_PM0_PAUSE_THRESH, refresh_quanta);
1062 	enetc_port_wr(hw, ENETC_PPAUONTR, pause_on_thresh);
1063 	enetc_port_wr(hw, ENETC_PPAUOFFTR, pause_off_thresh);
1064 
1065 	cmd_cfg = enetc_port_mac_rd(si, ENETC_PM0_CMD_CFG);
1066 
1067 	if (rx_pause)
1068 		cmd_cfg &= ~ENETC_PM0_PAUSE_IGN;
1069 	else
1070 		cmd_cfg |= ENETC_PM0_PAUSE_IGN;
1071 
1072 	enetc_port_mac_wr(si, ENETC_PM0_CMD_CFG, cmd_cfg);
1073 
1074 	enetc_mac_enable(si, true);
1075 
1076 	if (si->hw_features & ENETC_SI_F_QBU)
1077 		enetc_mm_link_state_update(priv, true);
1078 }
1079 
1080 static void enetc_pl_mac_link_down(struct phylink_config *config,
1081 				   unsigned int mode,
1082 				   phy_interface_t interface)
1083 {
1084 	struct enetc_pf *pf = phylink_to_enetc_pf(config);
1085 	struct enetc_si *si = pf->si;
1086 	struct enetc_ndev_priv *priv;
1087 
1088 	priv = netdev_priv(si->ndev);
1089 
1090 	if (si->hw_features & ENETC_SI_F_QBU)
1091 		enetc_mm_link_state_update(priv, false);
1092 
1093 	enetc_mac_enable(si, false);
1094 }
1095 
1096 static const struct phylink_mac_ops enetc_mac_phylink_ops = {
1097 	.mac_select_pcs = enetc_pl_mac_select_pcs,
1098 	.mac_config = enetc_pl_mac_config,
1099 	.mac_link_up = enetc_pl_mac_link_up,
1100 	.mac_link_down = enetc_pl_mac_link_down,
1101 };
1102 
1103 static int enetc_phylink_create(struct enetc_ndev_priv *priv,
1104 				struct device_node *node)
1105 {
1106 	struct enetc_pf *pf = enetc_si_priv(priv->si);
1107 	struct phylink *phylink;
1108 	int err;
1109 
1110 	pf->phylink_config.dev = &priv->ndev->dev;
1111 	pf->phylink_config.type = PHYLINK_NETDEV;
1112 	pf->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
1113 		MAC_10 | MAC_100 | MAC_1000 | MAC_2500FD;
1114 
1115 	__set_bit(PHY_INTERFACE_MODE_INTERNAL,
1116 		  pf->phylink_config.supported_interfaces);
1117 	__set_bit(PHY_INTERFACE_MODE_SGMII,
1118 		  pf->phylink_config.supported_interfaces);
1119 	__set_bit(PHY_INTERFACE_MODE_2500BASEX,
1120 		  pf->phylink_config.supported_interfaces);
1121 	__set_bit(PHY_INTERFACE_MODE_USXGMII,
1122 		  pf->phylink_config.supported_interfaces);
1123 	phy_interface_set_rgmii(pf->phylink_config.supported_interfaces);
1124 
1125 	phylink = phylink_create(&pf->phylink_config, of_fwnode_handle(node),
1126 				 pf->if_mode, &enetc_mac_phylink_ops);
1127 	if (IS_ERR(phylink)) {
1128 		err = PTR_ERR(phylink);
1129 		return err;
1130 	}
1131 
1132 	priv->phylink = phylink;
1133 
1134 	return 0;
1135 }
1136 
1137 static void enetc_phylink_destroy(struct enetc_ndev_priv *priv)
1138 {
1139 	phylink_destroy(priv->phylink);
1140 }
1141 
1142 /* Initialize the entire shared memory for the flow steering entries
1143  * of this port (PF + VFs)
1144  */
1145 static int enetc_init_port_rfs_memory(struct enetc_si *si)
1146 {
1147 	struct enetc_cmd_rfse rfse = {0};
1148 	struct enetc_hw *hw = &si->hw;
1149 	int num_rfs, i, err = 0;
1150 	u32 val;
1151 
1152 	val = enetc_port_rd(hw, ENETC_PRFSCAPR);
1153 	num_rfs = ENETC_PRFSCAPR_GET_NUM_RFS(val);
1154 
1155 	for (i = 0; i < num_rfs; i++) {
1156 		err = enetc_set_fs_entry(si, &rfse, i);
1157 		if (err)
1158 			break;
1159 	}
1160 
1161 	return err;
1162 }
1163 
1164 static int enetc_init_port_rss_memory(struct enetc_si *si)
1165 {
1166 	struct enetc_hw *hw = &si->hw;
1167 	int num_rss, err;
1168 	int *rss_table;
1169 	u32 val;
1170 
1171 	val = enetc_port_rd(hw, ENETC_PRSSCAPR);
1172 	num_rss = ENETC_PRSSCAPR_GET_NUM_RSS(val);
1173 	if (!num_rss)
1174 		return 0;
1175 
1176 	rss_table = kcalloc(num_rss, sizeof(*rss_table), GFP_KERNEL);
1177 	if (!rss_table)
1178 		return -ENOMEM;
1179 
1180 	err = enetc_set_rss_table(si, rss_table, num_rss);
1181 
1182 	kfree(rss_table);
1183 
1184 	return err;
1185 }
1186 
1187 static int enetc_pf_register_with_ierb(struct pci_dev *pdev)
1188 {
1189 	struct device_node *node = pdev->dev.of_node;
1190 	struct platform_device *ierb_pdev;
1191 	struct device_node *ierb_node;
1192 
1193 	/* Don't register with the IERB if the PF itself is disabled */
1194 	if (!node || !of_device_is_available(node))
1195 		return 0;
1196 
1197 	ierb_node = of_find_compatible_node(NULL, NULL,
1198 					    "fsl,ls1028a-enetc-ierb");
1199 	if (!ierb_node || !of_device_is_available(ierb_node))
1200 		return -ENODEV;
1201 
1202 	ierb_pdev = of_find_device_by_node(ierb_node);
1203 	of_node_put(ierb_node);
1204 
1205 	if (!ierb_pdev)
1206 		return -EPROBE_DEFER;
1207 
1208 	return enetc_ierb_register_pf(ierb_pdev, pdev);
1209 }
1210 
1211 static int enetc_pf_probe(struct pci_dev *pdev,
1212 			  const struct pci_device_id *ent)
1213 {
1214 	struct device_node *node = pdev->dev.of_node;
1215 	struct enetc_ndev_priv *priv;
1216 	struct net_device *ndev;
1217 	struct enetc_si *si;
1218 	struct enetc_pf *pf;
1219 	int err;
1220 
1221 	err = enetc_pf_register_with_ierb(pdev);
1222 	if (err == -EPROBE_DEFER)
1223 		return err;
1224 	if (err)
1225 		dev_warn(&pdev->dev,
1226 			 "Could not register with IERB driver: %pe, please update the device tree\n",
1227 			 ERR_PTR(err));
1228 
1229 	err = enetc_pci_probe(pdev, KBUILD_MODNAME, sizeof(*pf));
1230 	if (err)
1231 		return dev_err_probe(&pdev->dev, err, "PCI probing failed\n");
1232 
1233 	si = pci_get_drvdata(pdev);
1234 	if (!si->hw.port || !si->hw.global) {
1235 		err = -ENODEV;
1236 		dev_err(&pdev->dev, "could not map PF space, probing a VF?\n");
1237 		goto err_map_pf_space;
1238 	}
1239 
1240 	err = enetc_setup_cbdr(&pdev->dev, &si->hw, ENETC_CBDR_DEFAULT_SIZE,
1241 			       &si->cbd_ring);
1242 	if (err)
1243 		goto err_setup_cbdr;
1244 
1245 	err = enetc_init_port_rfs_memory(si);
1246 	if (err) {
1247 		dev_err(&pdev->dev, "Failed to initialize RFS memory\n");
1248 		goto err_init_port_rfs;
1249 	}
1250 
1251 	err = enetc_init_port_rss_memory(si);
1252 	if (err) {
1253 		dev_err(&pdev->dev, "Failed to initialize RSS memory\n");
1254 		goto err_init_port_rss;
1255 	}
1256 
1257 	if (node && !of_device_is_available(node)) {
1258 		dev_info(&pdev->dev, "device is disabled, skipping\n");
1259 		err = -ENODEV;
1260 		goto err_device_disabled;
1261 	}
1262 
1263 	pf = enetc_si_priv(si);
1264 	pf->si = si;
1265 	pf->total_vfs = pci_sriov_get_totalvfs(pdev);
1266 
1267 	err = enetc_setup_mac_addresses(node, pf);
1268 	if (err)
1269 		goto err_setup_mac_addresses;
1270 
1271 	enetc_configure_port(pf);
1272 
1273 	enetc_get_si_caps(si);
1274 
1275 	ndev = alloc_etherdev_mq(sizeof(*priv), ENETC_MAX_NUM_TXQS);
1276 	if (!ndev) {
1277 		err = -ENOMEM;
1278 		dev_err(&pdev->dev, "netdev creation failed\n");
1279 		goto err_alloc_netdev;
1280 	}
1281 
1282 	enetc_pf_netdev_setup(si, ndev, &enetc_ndev_ops);
1283 
1284 	priv = netdev_priv(ndev);
1285 
1286 	mutex_init(&priv->mm_lock);
1287 
1288 	enetc_init_si_rings_params(priv);
1289 
1290 	err = enetc_alloc_si_resources(priv);
1291 	if (err) {
1292 		dev_err(&pdev->dev, "SI resource alloc failed\n");
1293 		goto err_alloc_si_res;
1294 	}
1295 
1296 	err = enetc_configure_si(priv);
1297 	if (err) {
1298 		dev_err(&pdev->dev, "Failed to configure SI\n");
1299 		goto err_config_si;
1300 	}
1301 
1302 	err = enetc_alloc_msix(priv);
1303 	if (err) {
1304 		dev_err(&pdev->dev, "MSIX alloc failed\n");
1305 		goto err_alloc_msix;
1306 	}
1307 
1308 	err = of_get_phy_mode(node, &pf->if_mode);
1309 	if (err) {
1310 		dev_err(&pdev->dev, "Failed to read PHY mode\n");
1311 		goto err_phy_mode;
1312 	}
1313 
1314 	err = enetc_mdiobus_create(pf, node);
1315 	if (err)
1316 		goto err_mdiobus_create;
1317 
1318 	err = enetc_phylink_create(priv, node);
1319 	if (err)
1320 		goto err_phylink_create;
1321 
1322 	err = register_netdev(ndev);
1323 	if (err)
1324 		goto err_reg_netdev;
1325 
1326 	return 0;
1327 
1328 err_reg_netdev:
1329 	enetc_phylink_destroy(priv);
1330 err_phylink_create:
1331 	enetc_mdiobus_destroy(pf);
1332 err_mdiobus_create:
1333 err_phy_mode:
1334 	enetc_free_msix(priv);
1335 err_config_si:
1336 err_alloc_msix:
1337 	enetc_free_si_resources(priv);
1338 err_alloc_si_res:
1339 	si->ndev = NULL;
1340 	free_netdev(ndev);
1341 err_alloc_netdev:
1342 err_init_port_rss:
1343 err_init_port_rfs:
1344 err_device_disabled:
1345 err_setup_mac_addresses:
1346 	enetc_teardown_cbdr(&si->cbd_ring);
1347 err_setup_cbdr:
1348 err_map_pf_space:
1349 	enetc_pci_remove(pdev);
1350 
1351 	return err;
1352 }
1353 
1354 static void enetc_pf_remove(struct pci_dev *pdev)
1355 {
1356 	struct enetc_si *si = pci_get_drvdata(pdev);
1357 	struct enetc_pf *pf = enetc_si_priv(si);
1358 	struct enetc_ndev_priv *priv;
1359 
1360 	priv = netdev_priv(si->ndev);
1361 
1362 	if (pf->num_vfs)
1363 		enetc_sriov_configure(pdev, 0);
1364 
1365 	unregister_netdev(si->ndev);
1366 
1367 	enetc_phylink_destroy(priv);
1368 	enetc_mdiobus_destroy(pf);
1369 
1370 	enetc_free_msix(priv);
1371 
1372 	enetc_free_si_resources(priv);
1373 	enetc_teardown_cbdr(&si->cbd_ring);
1374 
1375 	free_netdev(si->ndev);
1376 
1377 	enetc_pci_remove(pdev);
1378 }
1379 
1380 static const struct pci_device_id enetc_pf_id_table[] = {
1381 	{ PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, ENETC_DEV_ID_PF) },
1382 	{ 0, } /* End of table. */
1383 };
1384 MODULE_DEVICE_TABLE(pci, enetc_pf_id_table);
1385 
1386 static struct pci_driver enetc_pf_driver = {
1387 	.name = KBUILD_MODNAME,
1388 	.id_table = enetc_pf_id_table,
1389 	.probe = enetc_pf_probe,
1390 	.remove = enetc_pf_remove,
1391 #ifdef CONFIG_PCI_IOV
1392 	.sriov_configure = enetc_sriov_configure,
1393 #endif
1394 };
1395 module_pci_driver(enetc_pf_driver);
1396 
1397 MODULE_DESCRIPTION(ENETC_DRV_NAME_STR);
1398 MODULE_LICENSE("Dual BSD/GPL");
1399