1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ 2 /* Copyright 2017-2019 NXP */ 3 4 #include <linux/bitops.h> 5 6 /* ENETC device IDs */ 7 #define ENETC_DEV_ID_PF 0xe100 8 #define ENETC_DEV_ID_VF 0xef00 9 #define ENETC_DEV_ID_PTP 0xee02 10 11 /* ENETC register block BAR */ 12 #define ENETC_BAR_REGS 0 13 14 /** SI regs, offset: 0h */ 15 #define ENETC_SIMR 0 16 #define ENETC_SIMR_EN BIT(31) 17 #define ENETC_SIMR_RSSE BIT(0) 18 #define ENETC_SICTR0 0x18 19 #define ENETC_SICTR1 0x1c 20 #define ENETC_SIPCAPR0 0x20 21 #define ENETC_SIPCAPR0_QBV BIT(4) 22 #define ENETC_SIPCAPR0_PSFP BIT(9) 23 #define ENETC_SIPCAPR0_RSS BIT(8) 24 #define ENETC_SIPCAPR1 0x24 25 #define ENETC_SITGTGR 0x30 26 #define ENETC_SIRBGCR 0x38 27 /* cache attribute registers for transactions initiated by ENETC */ 28 #define ENETC_SICAR0 0x40 29 #define ENETC_SICAR1 0x44 30 #define ENETC_SICAR2 0x48 31 /* rd snoop, no alloc 32 * wr snoop, no alloc, partial cache line update for BDs and full cache line 33 * update for data 34 */ 35 #define ENETC_SICAR_RD_COHERENT 0x2b2b0000 36 #define ENETC_SICAR_WR_COHERENT 0x00006727 37 #define ENETC_SICAR_MSI 0x00300030 /* rd/wr device, no snoop, no alloc */ 38 39 #define ENETC_SIPMAR0 0x80 40 #define ENETC_SIPMAR1 0x84 41 42 /* VF-PF Message passing */ 43 #define ENETC_DEFAULT_MSG_SIZE 1024 /* and max size */ 44 /* msg size encoding: default and max msg value of 1024B encoded as 0 */ 45 static inline u32 enetc_vsi_set_msize(u32 size) 46 { 47 return size < ENETC_DEFAULT_MSG_SIZE ? size >> 5 : 0; 48 } 49 50 #define ENETC_PSIMSGRR 0x204 51 #define ENETC_PSIMSGRR_MR_MASK GENMASK(2, 1) 52 #define ENETC_PSIMSGRR_MR(n) BIT((n) + 1) /* n = VSI index */ 53 #define ENETC_PSIVMSGRCVAR0(n) (0x210 + (n) * 0x8) /* n = VSI index */ 54 #define ENETC_PSIVMSGRCVAR1(n) (0x214 + (n) * 0x8) 55 56 #define ENETC_VSIMSGSR 0x204 /* RO */ 57 #define ENETC_VSIMSGSR_MB BIT(0) 58 #define ENETC_VSIMSGSR_MS BIT(1) 59 #define ENETC_VSIMSGSNDAR0 0x210 60 #define ENETC_VSIMSGSNDAR1 0x214 61 62 #define ENETC_SIMSGSR_SET_MC(val) ((val) << 16) 63 #define ENETC_SIMSGSR_GET_MC(val) ((val) >> 16) 64 65 /* SI statistics */ 66 #define ENETC_SIROCT 0x300 67 #define ENETC_SIRFRM 0x308 68 #define ENETC_SIRUCA 0x310 69 #define ENETC_SIRMCA 0x318 70 #define ENETC_SITOCT 0x320 71 #define ENETC_SITFRM 0x328 72 #define ENETC_SITUCA 0x330 73 #define ENETC_SITMCA 0x338 74 #define ENETC_RBDCR(n) (0x8180 + (n) * 0x200) 75 76 /* Control BDR regs */ 77 #define ENETC_SICBDRMR 0x800 78 #define ENETC_SICBDRSR 0x804 /* RO */ 79 #define ENETC_SICBDRBAR0 0x810 80 #define ENETC_SICBDRBAR1 0x814 81 #define ENETC_SICBDRPIR 0x818 82 #define ENETC_SICBDRCIR 0x81c 83 #define ENETC_SICBDRLENR 0x820 84 85 #define ENETC_SICAPR0 0x900 86 #define ENETC_SICAPR1 0x904 87 88 #define ENETC_PSIIER 0xa00 89 #define ENETC_PSIIER_MR_MASK GENMASK(2, 1) 90 #define ENETC_PSIIDR 0xa08 91 #define ENETC_SITXIDR 0xa18 92 #define ENETC_SIRXIDR 0xa28 93 #define ENETC_SIMSIVR 0xa30 94 95 #define ENETC_SIMSITRV(n) (0xB00 + (n) * 0x4) 96 #define ENETC_SIMSIRRV(n) (0xB80 + (n) * 0x4) 97 98 #define ENETC_SIUEFDCR 0xe28 99 100 #define ENETC_SIRFSCAPR 0x1200 101 #define ENETC_SIRFSCAPR_GET_NUM_RFS(val) ((val) & 0x7f) 102 #define ENETC_SIRSSCAPR 0x1600 103 #define ENETC_SIRSSCAPR_GET_NUM_RSS(val) (BIT((val) & 0xf) * 32) 104 105 /** SI BDR sub-blocks, n = 0..7 */ 106 enum enetc_bdr_type {TX, RX}; 107 #define ENETC_BDR_OFF(i) ((i) * 0x200) 108 #define ENETC_BDR(t, i, r) (0x8000 + (t) * 0x100 + ENETC_BDR_OFF(i) + (r)) 109 /* RX BDR reg offsets */ 110 #define ENETC_RBMR 0 111 #define ENETC_RBMR_BDS BIT(2) 112 #define ENETC_RBMR_CM BIT(4) 113 #define ENETC_RBMR_VTE BIT(5) 114 #define ENETC_RBMR_EN BIT(31) 115 #define ENETC_RBSR 0x4 116 #define ENETC_RBBSR 0x8 117 #define ENETC_RBCIR 0xc 118 #define ENETC_RBBAR0 0x10 119 #define ENETC_RBBAR1 0x14 120 #define ENETC_RBPIR 0x18 121 #define ENETC_RBLENR 0x20 122 #define ENETC_RBIER 0xa0 123 #define ENETC_RBIER_RXTIE BIT(0) 124 #define ENETC_RBIDR 0xa4 125 #define ENETC_RBICR0 0xa8 126 #define ENETC_RBICR0_ICEN BIT(31) 127 #define ENETC_RBICR0_ICPT_MASK 0x1ff 128 #define ENETC_RBICR0_SET_ICPT(n) ((n) & ENETC_RBICR0_ICPT_MASK) 129 #define ENETC_RBICR1 0xac 130 131 /* TX BDR reg offsets */ 132 #define ENETC_TBMR 0 133 #define ENETC_TBSR_BUSY BIT(0) 134 #define ENETC_TBMR_VIH BIT(9) 135 #define ENETC_TBMR_PRIO_MASK GENMASK(2, 0) 136 #define ENETC_TBMR_SET_PRIO(val) ((val) & ENETC_TBMR_PRIO_MASK) 137 #define ENETC_TBMR_EN BIT(31) 138 #define ENETC_TBSR 0x4 139 #define ENETC_TBBAR0 0x10 140 #define ENETC_TBBAR1 0x14 141 #define ENETC_TBPIR 0x18 142 #define ENETC_TBCIR 0x1c 143 #define ENETC_TBCIR_IDX_MASK 0xffff 144 #define ENETC_TBLENR 0x20 145 #define ENETC_TBIER 0xa0 146 #define ENETC_TBIER_TXTIE BIT(0) 147 #define ENETC_TBIDR 0xa4 148 #define ENETC_TBICR0 0xa8 149 #define ENETC_TBICR0_ICEN BIT(31) 150 #define ENETC_TBICR0_ICPT_MASK 0xf 151 #define ENETC_TBICR0_SET_ICPT(n) ((ilog2(n) + 1) & ENETC_TBICR0_ICPT_MASK) 152 #define ENETC_TBICR1 0xac 153 154 #define ENETC_RTBLENR_LEN(n) ((n) & ~0x7) 155 156 /* Port regs, offset: 1_0000h */ 157 #define ENETC_PORT_BASE 0x10000 158 #define ENETC_PMR 0x0000 159 #define ENETC_PMR_EN GENMASK(18, 16) 160 #define ENETC_PMR_PSPEED_MASK GENMASK(11, 8) 161 #define ENETC_PMR_PSPEED_10M 0 162 #define ENETC_PMR_PSPEED_100M BIT(8) 163 #define ENETC_PMR_PSPEED_1000M BIT(9) 164 #define ENETC_PMR_PSPEED_2500M BIT(10) 165 #define ENETC_PSR 0x0004 /* RO */ 166 #define ENETC_PSIPMR 0x0018 167 #define ENETC_PSIPMR_SET_UP(n) BIT(n) /* n = SI index */ 168 #define ENETC_PSIPMR_SET_MP(n) BIT((n) + 16) 169 #define ENETC_PSIPVMR 0x001c 170 #define ENETC_VLAN_PROMISC_MAP_ALL 0x7 171 #define ENETC_PSIPVMR_SET_VP(simap) ((simap) & 0x7) 172 #define ENETC_PSIPVMR_SET_VUTA(simap) (((simap) & 0x7) << 16) 173 #define ENETC_PSIPMAR0(n) (0x0100 + (n) * 0x8) /* n = SI index */ 174 #define ENETC_PSIPMAR1(n) (0x0104 + (n) * 0x8) 175 #define ENETC_PVCLCTR 0x0208 176 #define ENETC_PCVLANR1 0x0210 177 #define ENETC_PCVLANR2 0x0214 178 #define ENETC_VLAN_TYPE_C BIT(0) 179 #define ENETC_VLAN_TYPE_S BIT(1) 180 #define ENETC_PVCLCTR_OVTPIDL(bmp) ((bmp) & 0xff) /* VLAN_TYPE */ 181 #define ENETC_PSIVLANR(n) (0x0240 + (n) * 4) /* n = SI index */ 182 #define ENETC_PSIVLAN_EN BIT(31) 183 #define ENETC_PSIVLAN_SET_QOS(val) ((u32)(val) << 12) 184 #define ENETC_PPAUONTR 0x0410 185 #define ENETC_PPAUOFFTR 0x0414 186 #define ENETC_PTXMBAR 0x0608 187 #define ENETC_PCAPR0 0x0900 188 #define ENETC_PCAPR0_RXBDR(val) ((val) >> 24) 189 #define ENETC_PCAPR0_TXBDR(val) (((val) >> 16) & 0xff) 190 #define ENETC_PCAPR1 0x0904 191 #define ENETC_PSICFGR0(n) (0x0940 + (n) * 0xc) /* n = SI index */ 192 #define ENETC_PSICFGR0_SET_TXBDR(val) ((val) & 0xff) 193 #define ENETC_PSICFGR0_SET_RXBDR(val) (((val) & 0xff) << 16) 194 #define ENETC_PSICFGR0_VTE BIT(12) 195 #define ENETC_PSICFGR0_SIVIE BIT(14) 196 #define ENETC_PSICFGR0_ASE BIT(15) 197 #define ENETC_PSICFGR0_SIVC(bmp) (((bmp) & 0xff) << 24) /* VLAN_TYPE */ 198 199 #define ENETC_PTCCBSR0(n) (0x1110 + (n) * 8) /* n = 0 to 7*/ 200 #define ENETC_CBSE BIT(31) 201 #define ENETC_CBS_BW_MASK GENMASK(6, 0) 202 #define ENETC_PTCCBSR1(n) (0x1114 + (n) * 8) /* n = 0 to 7*/ 203 #define ENETC_RSSHASH_KEY_SIZE 40 204 #define ENETC_PRSSCAPR 0x1404 205 #define ENETC_PRSSCAPR_GET_NUM_RSS(val) (BIT((val) & 0xf) * 32) 206 #define ENETC_PRSSK(n) (0x1410 + (n) * 4) /* n = [0..9] */ 207 #define ENETC_PSIVLANFMR 0x1700 208 #define ENETC_PSIVLANFMR_VS BIT(0) 209 #define ENETC_PRFSMR 0x1800 210 #define ENETC_PRFSMR_RFSE BIT(31) 211 #define ENETC_PRFSCAPR 0x1804 212 #define ENETC_PRFSCAPR_GET_NUM_RFS(val) ((((val) & 0xf) + 1) * 16) 213 #define ENETC_PSIRFSCFGR(n) (0x1814 + (n) * 4) /* n = SI index */ 214 #define ENETC_PFPMR 0x1900 215 #define ENETC_PFPMR_PMACE BIT(1) 216 #define ENETC_PFPMR_MWLM BIT(0) 217 #define ENETC_EMDIO_BASE 0x1c00 218 #define ENETC_PSIUMHFR0(n, err) (((err) ? 0x1d08 : 0x1d00) + (n) * 0x10) 219 #define ENETC_PSIUMHFR1(n) (0x1d04 + (n) * 0x10) 220 #define ENETC_PSIMMHFR0(n, err) (((err) ? 0x1d00 : 0x1d08) + (n) * 0x10) 221 #define ENETC_PSIMMHFR1(n) (0x1d0c + (n) * 0x10) 222 #define ENETC_PSIVHFR0(n) (0x1e00 + (n) * 8) /* n = SI index */ 223 #define ENETC_PSIVHFR1(n) (0x1e04 + (n) * 8) /* n = SI index */ 224 #define ENETC_MMCSR 0x1f00 225 #define ENETC_MMCSR_ME BIT(16) 226 #define ENETC_PTCMSDUR(n) (0x2020 + (n) * 4) /* n = TC index [0..7] */ 227 228 #define ENETC_PM0_CMD_CFG 0x8008 229 #define ENETC_PM1_CMD_CFG 0x9008 230 #define ENETC_PM0_TX_EN BIT(0) 231 #define ENETC_PM0_RX_EN BIT(1) 232 #define ENETC_PM0_PROMISC BIT(4) 233 #define ENETC_PM0_PAUSE_IGN BIT(8) 234 #define ENETC_PM0_CMD_XGLP BIT(10) 235 #define ENETC_PM0_CMD_TXP BIT(11) 236 #define ENETC_PM0_CMD_PHY_TX_EN BIT(15) 237 #define ENETC_PM0_CMD_SFD BIT(21) 238 #define ENETC_PM0_MAXFRM 0x8014 239 #define ENETC_SET_TX_MTU(val) ((val) << 16) 240 #define ENETC_SET_MAXFRM(val) ((val) & 0xffff) 241 #define ENETC_PM0_RX_FIFO 0x801c 242 #define ENETC_PM0_RX_FIFO_VAL 1 243 244 #define ENETC_PM_IMDIO_BASE 0x8030 245 246 #define ENETC_PM0_PAUSE_QUANTA 0x8054 247 #define ENETC_PM0_PAUSE_THRESH 0x8064 248 #define ENETC_PM1_PAUSE_QUANTA 0x9054 249 #define ENETC_PM1_PAUSE_THRESH 0x9064 250 251 #define ENETC_PM0_SINGLE_STEP 0x80c0 252 #define ENETC_PM1_SINGLE_STEP 0x90c0 253 #define ENETC_PM0_SINGLE_STEP_CH BIT(7) 254 #define ENETC_PM0_SINGLE_STEP_EN BIT(31) 255 #define ENETC_SET_SINGLE_STEP_OFFSET(v) (((v) & 0xff) << 8) 256 257 #define ENETC_PM0_IF_MODE 0x8300 258 #define ENETC_PM0_IFM_RG BIT(2) 259 #define ENETC_PM0_IFM_RLP (BIT(5) | BIT(11)) 260 #define ENETC_PM0_IFM_EN_AUTO BIT(15) 261 #define ENETC_PM0_IFM_SSP_MASK GENMASK(14, 13) 262 #define ENETC_PM0_IFM_SSP_1000 (2 << 13) 263 #define ENETC_PM0_IFM_SSP_100 (0 << 13) 264 #define ENETC_PM0_IFM_SSP_10 (1 << 13) 265 #define ENETC_PM0_IFM_FULL_DPX BIT(12) 266 #define ENETC_PM0_IFM_IFMODE_MASK GENMASK(1, 0) 267 #define ENETC_PM0_IFM_IFMODE_XGMII 0 268 #define ENETC_PM0_IFM_IFMODE_GMII 2 269 #define ENETC_PSIDCAPR 0x1b08 270 #define ENETC_PSIDCAPR_MSK GENMASK(15, 0) 271 #define ENETC_PSFCAPR 0x1b18 272 #define ENETC_PSFCAPR_MSK GENMASK(15, 0) 273 #define ENETC_PSGCAPR 0x1b28 274 #define ENETC_PSGCAPR_GCL_MSK GENMASK(18, 16) 275 #define ENETC_PSGCAPR_SGIT_MSK GENMASK(15, 0) 276 #define ENETC_PFMCAPR 0x1b38 277 #define ENETC_PFMCAPR_MSK GENMASK(15, 0) 278 279 /* MAC counters */ 280 #define ENETC_PM0_REOCT 0x8100 281 #define ENETC_PM0_RALN 0x8110 282 #define ENETC_PM0_RXPF 0x8118 283 #define ENETC_PM0_RFRM 0x8120 284 #define ENETC_PM0_RFCS 0x8128 285 #define ENETC_PM0_RVLAN 0x8130 286 #define ENETC_PM0_RERR 0x8138 287 #define ENETC_PM0_RUCA 0x8140 288 #define ENETC_PM0_RMCA 0x8148 289 #define ENETC_PM0_RBCA 0x8150 290 #define ENETC_PM0_RDRP 0x8158 291 #define ENETC_PM0_RPKT 0x8160 292 #define ENETC_PM0_RUND 0x8168 293 #define ENETC_PM0_R64 0x8170 294 #define ENETC_PM0_R127 0x8178 295 #define ENETC_PM0_R255 0x8180 296 #define ENETC_PM0_R511 0x8188 297 #define ENETC_PM0_R1023 0x8190 298 #define ENETC_PM0_R1522 0x8198 299 #define ENETC_PM0_R1523X 0x81A0 300 #define ENETC_PM0_ROVR 0x81A8 301 #define ENETC_PM0_RJBR 0x81B0 302 #define ENETC_PM0_RFRG 0x81B8 303 #define ENETC_PM0_RCNP 0x81C0 304 #define ENETC_PM0_RDRNTP 0x81C8 305 #define ENETC_PM0_TEOCT 0x8200 306 #define ENETC_PM0_TOCT 0x8208 307 #define ENETC_PM0_TCRSE 0x8210 308 #define ENETC_PM0_TXPF 0x8218 309 #define ENETC_PM0_TFRM 0x8220 310 #define ENETC_PM0_TFCS 0x8228 311 #define ENETC_PM0_TVLAN 0x8230 312 #define ENETC_PM0_TERR 0x8238 313 #define ENETC_PM0_TUCA 0x8240 314 #define ENETC_PM0_TMCA 0x8248 315 #define ENETC_PM0_TBCA 0x8250 316 #define ENETC_PM0_TPKT 0x8260 317 #define ENETC_PM0_TUND 0x8268 318 #define ENETC_PM0_T64 0x8270 319 #define ENETC_PM0_T127 0x8278 320 #define ENETC_PM0_T255 0x8280 321 #define ENETC_PM0_T511 0x8288 322 #define ENETC_PM0_T1023 0x8290 323 #define ENETC_PM0_T1522 0x8298 324 #define ENETC_PM0_T1523X 0x82A0 325 #define ENETC_PM0_TCNP 0x82C0 326 #define ENETC_PM0_TDFR 0x82D0 327 #define ENETC_PM0_TMCOL 0x82D8 328 #define ENETC_PM0_TSCOL 0x82E0 329 #define ENETC_PM0_TLCOL 0x82E8 330 #define ENETC_PM0_TECOL 0x82F0 331 332 /* Port counters */ 333 #define ENETC_PICDR(n) (0x0700 + (n) * 8) /* n = [0..3] */ 334 #define ENETC_PBFDSIR 0x0810 335 #define ENETC_PFDMSAPR 0x0814 336 #define ENETC_UFDMF 0x1680 337 #define ENETC_MFDMF 0x1684 338 #define ENETC_PUFDVFR 0x1780 339 #define ENETC_PMFDVFR 0x1784 340 #define ENETC_PBFDVFR 0x1788 341 342 /** Global regs, offset: 2_0000h */ 343 #define ENETC_GLOBAL_BASE 0x20000 344 #define ENETC_G_EIPBRR0 0x0bf8 345 #define ENETC_G_EIPBRR1 0x0bfc 346 #define ENETC_G_EPFBLPR(n) (0xd00 + 4 * (n)) 347 #define ENETC_G_EPFBLPR1_XGMII 0x80000000 348 349 /* PCI device info */ 350 struct enetc_hw { 351 /* SI registers, used by all PCI functions */ 352 void __iomem *reg; 353 /* Port registers, PF only */ 354 void __iomem *port; 355 /* IP global registers, PF only */ 356 void __iomem *global; 357 }; 358 359 /* ENETC register accessors */ 360 361 /* MDIO issue workaround (on LS1028A) - 362 * Due to a hardware issue, an access to MDIO registers 363 * that is concurrent with other ENETC register accesses 364 * may lead to the MDIO access being dropped or corrupted. 365 * To protect the MDIO accesses a readers-writers locking 366 * scheme is used, where the MDIO register accesses are 367 * protected by write locks to insure exclusivity, while 368 * the remaining ENETC registers are accessed under read 369 * locks since they only compete with MDIO accesses. 370 */ 371 extern rwlock_t enetc_mdio_lock; 372 373 /* use this locking primitive only on the fast datapath to 374 * group together multiple non-MDIO register accesses to 375 * minimize the overhead of the lock 376 */ 377 static inline void enetc_lock_mdio(void) 378 { 379 read_lock(&enetc_mdio_lock); 380 } 381 382 static inline void enetc_unlock_mdio(void) 383 { 384 read_unlock(&enetc_mdio_lock); 385 } 386 387 /* use these accessors only on the fast datapath under 388 * the enetc_lock_mdio() locking primitive to minimize 389 * the overhead of the lock 390 */ 391 static inline u32 enetc_rd_reg_hot(void __iomem *reg) 392 { 393 lockdep_assert_held(&enetc_mdio_lock); 394 395 return ioread32(reg); 396 } 397 398 static inline void enetc_wr_reg_hot(void __iomem *reg, u32 val) 399 { 400 lockdep_assert_held(&enetc_mdio_lock); 401 402 iowrite32(val, reg); 403 } 404 405 /* internal helpers for the MDIO w/a */ 406 static inline u32 _enetc_rd_reg_wa(void __iomem *reg) 407 { 408 u32 val; 409 410 enetc_lock_mdio(); 411 val = ioread32(reg); 412 enetc_unlock_mdio(); 413 414 return val; 415 } 416 417 static inline void _enetc_wr_reg_wa(void __iomem *reg, u32 val) 418 { 419 enetc_lock_mdio(); 420 iowrite32(val, reg); 421 enetc_unlock_mdio(); 422 } 423 424 static inline u32 _enetc_rd_mdio_reg_wa(void __iomem *reg) 425 { 426 unsigned long flags; 427 u32 val; 428 429 write_lock_irqsave(&enetc_mdio_lock, flags); 430 val = ioread32(reg); 431 write_unlock_irqrestore(&enetc_mdio_lock, flags); 432 433 return val; 434 } 435 436 static inline void _enetc_wr_mdio_reg_wa(void __iomem *reg, u32 val) 437 { 438 unsigned long flags; 439 440 write_lock_irqsave(&enetc_mdio_lock, flags); 441 iowrite32(val, reg); 442 write_unlock_irqrestore(&enetc_mdio_lock, flags); 443 } 444 445 #ifdef ioread64 446 static inline u64 _enetc_rd_reg64(void __iomem *reg) 447 { 448 return ioread64(reg); 449 } 450 #else 451 /* using this to read out stats on 32b systems */ 452 static inline u64 _enetc_rd_reg64(void __iomem *reg) 453 { 454 u32 low, high, tmp; 455 456 do { 457 high = ioread32(reg + 4); 458 low = ioread32(reg); 459 tmp = ioread32(reg + 4); 460 } while (high != tmp); 461 462 return le64_to_cpu((__le64)high << 32 | low); 463 } 464 #endif 465 466 static inline u64 _enetc_rd_reg64_wa(void __iomem *reg) 467 { 468 u64 val; 469 470 enetc_lock_mdio(); 471 val = _enetc_rd_reg64(reg); 472 enetc_unlock_mdio(); 473 474 return val; 475 } 476 477 /* general register accessors */ 478 #define enetc_rd_reg(reg) _enetc_rd_reg_wa((reg)) 479 #define enetc_wr_reg(reg, val) _enetc_wr_reg_wa((reg), (val)) 480 #define enetc_rd(hw, off) enetc_rd_reg((hw)->reg + (off)) 481 #define enetc_wr(hw, off, val) enetc_wr_reg((hw)->reg + (off), val) 482 #define enetc_rd_hot(hw, off) enetc_rd_reg_hot((hw)->reg + (off)) 483 #define enetc_wr_hot(hw, off, val) enetc_wr_reg_hot((hw)->reg + (off), val) 484 #define enetc_rd64(hw, off) _enetc_rd_reg64_wa((hw)->reg + (off)) 485 /* port register accessors - PF only */ 486 #define enetc_port_rd(hw, off) enetc_rd_reg((hw)->port + (off)) 487 #define enetc_port_wr(hw, off, val) enetc_wr_reg((hw)->port + (off), val) 488 #define enetc_port_rd_mdio(hw, off) _enetc_rd_mdio_reg_wa((hw)->port + (off)) 489 #define enetc_port_wr_mdio(hw, off, val) _enetc_wr_mdio_reg_wa(\ 490 (hw)->port + (off), val) 491 /* global register accessors - PF only */ 492 #define enetc_global_rd(hw, off) enetc_rd_reg((hw)->global + (off)) 493 #define enetc_global_wr(hw, off, val) enetc_wr_reg((hw)->global + (off), val) 494 /* BDR register accessors, see ENETC_BDR() */ 495 #define enetc_bdr_rd(hw, t, n, off) \ 496 enetc_rd(hw, ENETC_BDR(t, n, off)) 497 #define enetc_bdr_wr(hw, t, n, off, val) \ 498 enetc_wr(hw, ENETC_BDR(t, n, off), val) 499 #define enetc_txbdr_rd(hw, n, off) enetc_bdr_rd(hw, TX, n, off) 500 #define enetc_rxbdr_rd(hw, n, off) enetc_bdr_rd(hw, RX, n, off) 501 #define enetc_txbdr_wr(hw, n, off, val) \ 502 enetc_bdr_wr(hw, TX, n, off, val) 503 #define enetc_rxbdr_wr(hw, n, off, val) \ 504 enetc_bdr_wr(hw, RX, n, off, val) 505 506 /* Buffer Descriptors (BD) */ 507 union enetc_tx_bd { 508 struct { 509 __le64 addr; 510 __le16 buf_len; 511 __le16 frm_len; 512 union { 513 struct { 514 u8 reserved[3]; 515 u8 flags; 516 }; /* default layout */ 517 __le32 txstart; 518 __le32 lstatus; 519 }; 520 }; 521 struct { 522 __le32 tstamp; 523 __le16 tpid; 524 __le16 vid; 525 u8 reserved[6]; 526 u8 e_flags; 527 u8 flags; 528 } ext; /* Tx BD extension */ 529 struct { 530 __le32 tstamp; 531 u8 reserved[10]; 532 u8 status; 533 u8 flags; 534 } wb; /* writeback descriptor */ 535 }; 536 537 enum enetc_txbd_flags { 538 ENETC_TXBD_FLAGS_RES0 = BIT(0), /* reserved */ 539 ENETC_TXBD_FLAGS_TSE = BIT(1), 540 ENETC_TXBD_FLAGS_W = BIT(2), 541 ENETC_TXBD_FLAGS_RES3 = BIT(3), /* reserved */ 542 ENETC_TXBD_FLAGS_TXSTART = BIT(4), 543 ENETC_TXBD_FLAGS_EX = BIT(6), 544 ENETC_TXBD_FLAGS_F = BIT(7) 545 }; 546 #define ENETC_TXBD_TXSTART_MASK GENMASK(24, 0) 547 #define ENETC_TXBD_FLAGS_OFFSET 24 548 549 static inline __le32 enetc_txbd_set_tx_start(u64 tx_start, u8 flags) 550 { 551 u32 temp; 552 553 temp = (tx_start >> 5 & ENETC_TXBD_TXSTART_MASK) | 554 (flags << ENETC_TXBD_FLAGS_OFFSET); 555 556 return cpu_to_le32(temp); 557 } 558 559 static inline void enetc_clear_tx_bd(union enetc_tx_bd *txbd) 560 { 561 memset(txbd, 0, sizeof(*txbd)); 562 } 563 564 /* Extension flags */ 565 #define ENETC_TXBD_E_FLAGS_VLAN_INS BIT(0) 566 #define ENETC_TXBD_E_FLAGS_ONE_STEP_PTP BIT(1) 567 #define ENETC_TXBD_E_FLAGS_TWO_STEP_PTP BIT(2) 568 569 union enetc_rx_bd { 570 struct { 571 __le64 addr; 572 u8 reserved[8]; 573 } w; 574 struct { 575 __le16 inet_csum; 576 __le16 parse_summary; 577 __le32 rss_hash; 578 __le16 buf_len; 579 __le16 vlan_opt; 580 union { 581 struct { 582 __le16 flags; 583 __le16 error; 584 }; 585 __le32 lstatus; 586 }; 587 } r; 588 struct { 589 __le32 tstamp; 590 u8 reserved[12]; 591 } ext; 592 }; 593 594 #define ENETC_RXBD_LSTATUS_R BIT(30) 595 #define ENETC_RXBD_LSTATUS_F BIT(31) 596 #define ENETC_RXBD_ERR_MASK 0xff 597 #define ENETC_RXBD_LSTATUS(flags) ((flags) << 16) 598 #define ENETC_RXBD_FLAG_VLAN BIT(9) 599 #define ENETC_RXBD_FLAG_TSTMP BIT(10) 600 #define ENETC_RXBD_FLAG_TPID GENMASK(1, 0) 601 602 #define ENETC_MAC_ADDR_FILT_CNT 8 /* # of supported entries per port */ 603 #define EMETC_MAC_ADDR_FILT_RES 3 /* # of reserved entries at the beginning */ 604 #define ENETC_MAX_NUM_VFS 2 605 606 #define ENETC_CBD_FLAGS_SF BIT(7) /* short format */ 607 #define ENETC_CBD_STATUS_MASK 0xf 608 609 struct enetc_cmd_rfse { 610 u8 smac_h[6]; 611 u8 smac_m[6]; 612 u8 dmac_h[6]; 613 u8 dmac_m[6]; 614 __be32 sip_h[4]; 615 __be32 sip_m[4]; 616 __be32 dip_h[4]; 617 __be32 dip_m[4]; 618 u16 ethtype_h; 619 u16 ethtype_m; 620 u16 ethtype4_h; 621 u16 ethtype4_m; 622 u16 sport_h; 623 u16 sport_m; 624 u16 dport_h; 625 u16 dport_m; 626 u16 vlan_h; 627 u16 vlan_m; 628 u8 proto_h; 629 u8 proto_m; 630 u16 flags; 631 u16 result; 632 u16 mode; 633 }; 634 635 #define ENETC_RFSE_EN BIT(15) 636 #define ENETC_RFSE_MODE_BD 2 637 638 static inline void enetc_get_primary_mac_addr(struct enetc_hw *hw, u8 *addr) 639 { 640 *(u32 *)addr = __raw_readl(hw->reg + ENETC_SIPMAR0); 641 *(u16 *)(addr + 4) = __raw_readw(hw->reg + ENETC_SIPMAR1); 642 } 643 644 #define ENETC_SI_INT_IDX 0 645 /* base index for Rx/Tx interrupts */ 646 #define ENETC_BDR_INT_BASE_IDX 1 647 648 /* Messaging */ 649 650 /* Command completion status */ 651 enum enetc_msg_cmd_status { 652 ENETC_MSG_CMD_STATUS_OK, 653 ENETC_MSG_CMD_STATUS_FAIL 654 }; 655 656 /* VSI-PSI command message types */ 657 enum enetc_msg_cmd_type { 658 ENETC_MSG_CMD_MNG_MAC = 1, /* manage MAC address */ 659 ENETC_MSG_CMD_MNG_RX_MAC_FILTER,/* manage RX MAC table */ 660 ENETC_MSG_CMD_MNG_RX_VLAN_FILTER /* manage RX VLAN table */ 661 }; 662 663 /* VSI-PSI command action types */ 664 enum enetc_msg_cmd_action_type { 665 ENETC_MSG_CMD_MNG_ADD = 1, 666 ENETC_MSG_CMD_MNG_REMOVE 667 }; 668 669 /* PSI-VSI command header format */ 670 struct enetc_msg_cmd_header { 671 u16 type; /* command class type */ 672 u16 id; /* denotes the specific required action */ 673 }; 674 675 /* Common H/W utility functions */ 676 677 static inline void enetc_bdr_enable_rxvlan(struct enetc_hw *hw, int idx, 678 bool en) 679 { 680 u32 val = enetc_rxbdr_rd(hw, idx, ENETC_RBMR); 681 682 val = (val & ~ENETC_RBMR_VTE) | (en ? ENETC_RBMR_VTE : 0); 683 enetc_rxbdr_wr(hw, idx, ENETC_RBMR, val); 684 } 685 686 static inline void enetc_bdr_enable_txvlan(struct enetc_hw *hw, int idx, 687 bool en) 688 { 689 u32 val = enetc_txbdr_rd(hw, idx, ENETC_TBMR); 690 691 val = (val & ~ENETC_TBMR_VIH) | (en ? ENETC_TBMR_VIH : 0); 692 enetc_txbdr_wr(hw, idx, ENETC_TBMR, val); 693 } 694 695 static inline void enetc_set_bdr_prio(struct enetc_hw *hw, int bdr_idx, 696 int prio) 697 { 698 u32 val = enetc_txbdr_rd(hw, bdr_idx, ENETC_TBMR); 699 700 val &= ~ENETC_TBMR_PRIO_MASK; 701 val |= ENETC_TBMR_SET_PRIO(prio); 702 enetc_txbdr_wr(hw, bdr_idx, ENETC_TBMR, val); 703 } 704 705 enum bdcr_cmd_class { 706 BDCR_CMD_UNSPEC = 0, 707 BDCR_CMD_MAC_FILTER, 708 BDCR_CMD_VLAN_FILTER, 709 BDCR_CMD_RSS, 710 BDCR_CMD_RFS, 711 BDCR_CMD_PORT_GCL, 712 BDCR_CMD_RECV_CLASSIFIER, 713 BDCR_CMD_STREAM_IDENTIFY, 714 BDCR_CMD_STREAM_FILTER, 715 BDCR_CMD_STREAM_GCL, 716 BDCR_CMD_FLOW_METER, 717 __BDCR_CMD_MAX_LEN, 718 BDCR_CMD_MAX_LEN = __BDCR_CMD_MAX_LEN - 1, 719 }; 720 721 /* class 5, command 0 */ 722 struct tgs_gcl_conf { 723 u8 atc; /* init gate value */ 724 u8 res[7]; 725 struct { 726 u8 res1[4]; 727 __le16 acl_len; 728 u8 res2[2]; 729 }; 730 }; 731 732 /* gate control list entry */ 733 struct gce { 734 __le32 period; 735 u8 gate; 736 u8 res[3]; 737 }; 738 739 /* tgs_gcl_conf address point to this data space */ 740 struct tgs_gcl_data { 741 __le32 btl; 742 __le32 bth; 743 __le32 ct; 744 __le32 cte; 745 struct gce entry[]; 746 }; 747 748 /* class 7, command 0, Stream Identity Entry Configuration */ 749 struct streamid_conf { 750 __le32 stream_handle; /* init gate value */ 751 __le32 iports; 752 u8 id_type; 753 u8 oui[3]; 754 u8 res[3]; 755 u8 en; 756 }; 757 758 #define ENETC_CBDR_SID_VID_MASK 0xfff 759 #define ENETC_CBDR_SID_VIDM BIT(12) 760 #define ENETC_CBDR_SID_TG_MASK 0xc000 761 /* streamid_conf address point to this data space */ 762 struct streamid_data { 763 union { 764 u8 dmac[6]; 765 u8 smac[6]; 766 }; 767 u16 vid_vidm_tg; 768 }; 769 770 #define ENETC_CBDR_SFI_PRI_MASK 0x7 771 #define ENETC_CBDR_SFI_PRIM BIT(3) 772 #define ENETC_CBDR_SFI_BLOV BIT(4) 773 #define ENETC_CBDR_SFI_BLEN BIT(5) 774 #define ENETC_CBDR_SFI_MSDUEN BIT(6) 775 #define ENETC_CBDR_SFI_FMITEN BIT(7) 776 #define ENETC_CBDR_SFI_ENABLE BIT(7) 777 /* class 8, command 0, Stream Filter Instance, Short Format */ 778 struct sfi_conf { 779 __le32 stream_handle; 780 u8 multi; 781 u8 res[2]; 782 u8 sthm; 783 /* Max Service Data Unit or Flow Meter Instance Table index. 784 * Depending on the value of FLT this represents either Max 785 * Service Data Unit (max frame size) allowed by the filter 786 * entry or is an index into the Flow Meter Instance table 787 * index identifying the policer which will be used to police 788 * it. 789 */ 790 __le16 fm_inst_table_index; 791 __le16 msdu; 792 __le16 sg_inst_table_index; 793 u8 res1[2]; 794 __le32 input_ports; 795 u8 res2[3]; 796 u8 en; 797 }; 798 799 /* class 8, command 2 stream Filter Instance status query short format 800 * command no need structure define 801 * Stream Filter Instance Query Statistics Response data 802 */ 803 struct sfi_counter_data { 804 u32 matchl; 805 u32 matchh; 806 u32 msdu_dropl; 807 u32 msdu_droph; 808 u32 stream_gate_dropl; 809 u32 stream_gate_droph; 810 u32 flow_meter_dropl; 811 u32 flow_meter_droph; 812 }; 813 814 #define ENETC_CBDR_SGI_OIPV_MASK 0x7 815 #define ENETC_CBDR_SGI_OIPV_EN BIT(3) 816 #define ENETC_CBDR_SGI_CGTST BIT(6) 817 #define ENETC_CBDR_SGI_OGTST BIT(7) 818 #define ENETC_CBDR_SGI_CFG_CHG BIT(1) 819 #define ENETC_CBDR_SGI_CFG_PND BIT(2) 820 #define ENETC_CBDR_SGI_OEX BIT(4) 821 #define ENETC_CBDR_SGI_OEXEN BIT(5) 822 #define ENETC_CBDR_SGI_IRX BIT(6) 823 #define ENETC_CBDR_SGI_IRXEN BIT(7) 824 #define ENETC_CBDR_SGI_ACLLEN_MASK 0x3 825 #define ENETC_CBDR_SGI_OCLLEN_MASK 0xc 826 #define ENETC_CBDR_SGI_EN BIT(7) 827 /* class 9, command 0, Stream Gate Instance Table, Short Format 828 * class 9, command 2, Stream Gate Instance Table entry query write back 829 * Short Format 830 */ 831 struct sgi_table { 832 u8 res[8]; 833 u8 oipv; 834 u8 res0[2]; 835 u8 ocgtst; 836 u8 res1[7]; 837 u8 gset; 838 u8 oacl_len; 839 u8 res2[2]; 840 u8 en; 841 }; 842 843 #define ENETC_CBDR_SGI_AIPV_MASK 0x7 844 #define ENETC_CBDR_SGI_AIPV_EN BIT(3) 845 #define ENETC_CBDR_SGI_AGTST BIT(7) 846 847 /* class 9, command 1, Stream Gate Control List, Long Format */ 848 struct sgcl_conf { 849 u8 aipv; 850 u8 res[2]; 851 u8 agtst; 852 u8 res1[4]; 853 union { 854 struct { 855 u8 res2[4]; 856 u8 acl_len; 857 u8 res3[3]; 858 }; 859 u8 cct[8]; /* Config change time */ 860 }; 861 }; 862 863 #define ENETC_CBDR_SGL_IOMEN BIT(0) 864 #define ENETC_CBDR_SGL_IPVEN BIT(3) 865 #define ENETC_CBDR_SGL_GTST BIT(4) 866 #define ENETC_CBDR_SGL_IPV_MASK 0xe 867 /* Stream Gate Control List Entry */ 868 struct sgce { 869 u32 interval; 870 u8 msdu[3]; 871 u8 multi; 872 }; 873 874 /* stream control list class 9 , cmd 1 data buffer */ 875 struct sgcl_data { 876 u32 btl; 877 u32 bth; 878 u32 ct; 879 u32 cte; 880 struct sgce sgcl[0]; 881 }; 882 883 #define ENETC_CBDR_FMI_MR BIT(0) 884 #define ENETC_CBDR_FMI_MREN BIT(1) 885 #define ENETC_CBDR_FMI_DOY BIT(2) 886 #define ENETC_CBDR_FMI_CM BIT(3) 887 #define ENETC_CBDR_FMI_CF BIT(4) 888 #define ENETC_CBDR_FMI_NDOR BIT(5) 889 #define ENETC_CBDR_FMI_OALEN BIT(6) 890 #define ENETC_CBDR_FMI_IRFPP_MASK GENMASK(4, 0) 891 892 /* class 10: command 0/1, Flow Meter Instance Set, short Format */ 893 struct fmi_conf { 894 __le32 cir; 895 __le32 cbs; 896 __le32 eir; 897 __le32 ebs; 898 u8 conf; 899 u8 res1; 900 u8 ir_fpp; 901 u8 res2[4]; 902 u8 en; 903 }; 904 905 struct enetc_cbd { 906 union{ 907 struct sfi_conf sfi_conf; 908 struct sgi_table sgi_table; 909 struct fmi_conf fmi_conf; 910 struct { 911 __le32 addr[2]; 912 union { 913 __le32 opt[4]; 914 struct tgs_gcl_conf gcl_conf; 915 struct streamid_conf sid_set; 916 struct sgcl_conf sgcl_conf; 917 }; 918 }; /* Long format */ 919 __le32 data[6]; 920 }; 921 __le16 index; 922 __le16 length; 923 u8 cmd; 924 u8 cls; 925 u8 _res; 926 u8 status_flags; 927 }; 928 929 #define ENETC_CLK 400000000ULL 930 static inline u32 enetc_cycles_to_usecs(u32 cycles) 931 { 932 return (u32)div_u64(cycles * 1000000ULL, ENETC_CLK); 933 } 934 935 static inline u32 enetc_usecs_to_cycles(u32 usecs) 936 { 937 return (u32)div_u64(usecs * ENETC_CLK, 1000000ULL); 938 } 939 940 /* port time gating control register */ 941 #define ENETC_QBV_PTGCR_OFFSET 0x11a00 942 #define ENETC_QBV_TGE BIT(31) 943 #define ENETC_QBV_TGPE BIT(30) 944 945 /* Port time gating capability register */ 946 #define ENETC_QBV_PTGCAPR_OFFSET 0x11a08 947 #define ENETC_QBV_MAX_GCL_LEN_MASK GENMASK(15, 0) 948 949 /* Port time specific departure */ 950 #define ENETC_PTCTSDR(n) (0x1210 + 4 * (n)) 951 #define ENETC_TSDE BIT(31) 952 953 /* PSFP setting */ 954 #define ENETC_PPSFPMR 0x11b00 955 #define ENETC_PPSFPMR_PSFPEN BIT(0) 956 #define ENETC_PPSFPMR_VS BIT(1) 957 #define ENETC_PPSFPMR_PVC BIT(2) 958 #define ENETC_PPSFPMR_PVZC BIT(3) 959