1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ 2 /* Copyright 2017-2019 NXP */ 3 4 #include <linux/bitops.h> 5 6 /* ENETC device IDs */ 7 #define ENETC_DEV_ID_PF 0xe100 8 #define ENETC_DEV_ID_VF 0xef00 9 #define ENETC_DEV_ID_PTP 0xee02 10 11 /* ENETC register block BAR */ 12 #define ENETC_BAR_REGS 0 13 14 /** SI regs, offset: 0h */ 15 #define ENETC_SIMR 0 16 #define ENETC_SIMR_EN BIT(31) 17 #define ENETC_SIMR_RSSE BIT(0) 18 #define ENETC_SICTR0 0x18 19 #define ENETC_SICTR1 0x1c 20 #define ENETC_SIPCAPR0 0x20 21 #define ENETC_SIPCAPR0_QBV BIT(4) 22 #define ENETC_SIPCAPR0_PSFP BIT(9) 23 #define ENETC_SIPCAPR0_RSS BIT(8) 24 #define ENETC_SIPCAPR1 0x24 25 #define ENETC_SITGTGR 0x30 26 #define ENETC_SIRBGCR 0x38 27 /* cache attribute registers for transactions initiated by ENETC */ 28 #define ENETC_SICAR0 0x40 29 #define ENETC_SICAR1 0x44 30 #define ENETC_SICAR2 0x48 31 /* rd snoop, no alloc 32 * wr snoop, no alloc, partial cache line update for BDs and full cache line 33 * update for data 34 */ 35 #define ENETC_SICAR_RD_COHERENT 0x2b2b0000 36 #define ENETC_SICAR_WR_COHERENT 0x00006727 37 #define ENETC_SICAR_MSI 0x00300030 /* rd/wr device, no snoop, no alloc */ 38 39 #define ENETC_SIPMAR0 0x80 40 #define ENETC_SIPMAR1 0x84 41 42 /* VF-PF Message passing */ 43 #define ENETC_DEFAULT_MSG_SIZE 1024 /* and max size */ 44 /* msg size encoding: default and max msg value of 1024B encoded as 0 */ 45 static inline u32 enetc_vsi_set_msize(u32 size) 46 { 47 return size < ENETC_DEFAULT_MSG_SIZE ? size >> 5 : 0; 48 } 49 50 #define ENETC_PSIMSGRR 0x204 51 #define ENETC_PSIMSGRR_MR_MASK GENMASK(2, 1) 52 #define ENETC_PSIMSGRR_MR(n) BIT((n) + 1) /* n = VSI index */ 53 #define ENETC_PSIVMSGRCVAR0(n) (0x210 + (n) * 0x8) /* n = VSI index */ 54 #define ENETC_PSIVMSGRCVAR1(n) (0x214 + (n) * 0x8) 55 56 #define ENETC_VSIMSGSR 0x204 /* RO */ 57 #define ENETC_VSIMSGSR_MB BIT(0) 58 #define ENETC_VSIMSGSR_MS BIT(1) 59 #define ENETC_VSIMSGSNDAR0 0x210 60 #define ENETC_VSIMSGSNDAR1 0x214 61 62 #define ENETC_SIMSGSR_SET_MC(val) ((val) << 16) 63 #define ENETC_SIMSGSR_GET_MC(val) ((val) >> 16) 64 65 /* SI statistics */ 66 #define ENETC_SIROCT 0x300 67 #define ENETC_SIRFRM 0x308 68 #define ENETC_SIRUCA 0x310 69 #define ENETC_SIRMCA 0x318 70 #define ENETC_SITOCT 0x320 71 #define ENETC_SITFRM 0x328 72 #define ENETC_SITUCA 0x330 73 #define ENETC_SITMCA 0x338 74 #define ENETC_RBDCR(n) (0x8180 + (n) * 0x200) 75 76 /* Control BDR regs */ 77 #define ENETC_SICBDRMR 0x800 78 #define ENETC_SICBDRSR 0x804 /* RO */ 79 #define ENETC_SICBDRBAR0 0x810 80 #define ENETC_SICBDRBAR1 0x814 81 #define ENETC_SICBDRPIR 0x818 82 #define ENETC_SICBDRCIR 0x81c 83 #define ENETC_SICBDRLENR 0x820 84 85 #define ENETC_SICAPR0 0x900 86 #define ENETC_SICAPR1 0x904 87 88 #define ENETC_PSIIER 0xa00 89 #define ENETC_PSIIER_MR_MASK GENMASK(2, 1) 90 #define ENETC_PSIIDR 0xa08 91 #define ENETC_SITXIDR 0xa18 92 #define ENETC_SIRXIDR 0xa28 93 #define ENETC_SIMSIVR 0xa30 94 95 #define ENETC_SIMSITRV(n) (0xB00 + (n) * 0x4) 96 #define ENETC_SIMSIRRV(n) (0xB80 + (n) * 0x4) 97 98 #define ENETC_SIUEFDCR 0xe28 99 100 #define ENETC_SIRFSCAPR 0x1200 101 #define ENETC_SIRFSCAPR_GET_NUM_RFS(val) ((val) & 0x7f) 102 #define ENETC_SIRSSCAPR 0x1600 103 #define ENETC_SIRSSCAPR_GET_NUM_RSS(val) (BIT((val) & 0xf) * 32) 104 105 /** SI BDR sub-blocks, n = 0..7 */ 106 enum enetc_bdr_type {TX, RX}; 107 #define ENETC_BDR_OFF(i) ((i) * 0x200) 108 #define ENETC_BDR(t, i, r) (0x8000 + (t) * 0x100 + ENETC_BDR_OFF(i) + (r)) 109 /* RX BDR reg offsets */ 110 #define ENETC_RBMR 0 111 #define ENETC_RBMR_BDS BIT(2) 112 #define ENETC_RBMR_VTE BIT(5) 113 #define ENETC_RBMR_EN BIT(31) 114 #define ENETC_RBSR 0x4 115 #define ENETC_RBBSR 0x8 116 #define ENETC_RBCIR 0xc 117 #define ENETC_RBBAR0 0x10 118 #define ENETC_RBBAR1 0x14 119 #define ENETC_RBPIR 0x18 120 #define ENETC_RBLENR 0x20 121 #define ENETC_RBIER 0xa0 122 #define ENETC_RBIER_RXTIE BIT(0) 123 #define ENETC_RBIDR 0xa4 124 #define ENETC_RBICR0 0xa8 125 #define ENETC_RBICR0_ICEN BIT(31) 126 #define ENETC_RBICR0_ICPT_MASK 0x1ff 127 #define ENETC_RBICR0_SET_ICPT(n) ((n) & ENETC_RBICR0_ICPT_MASK) 128 #define ENETC_RBICR1 0xac 129 130 /* TX BDR reg offsets */ 131 #define ENETC_TBMR 0 132 #define ENETC_TBSR_BUSY BIT(0) 133 #define ENETC_TBMR_VIH BIT(9) 134 #define ENETC_TBMR_PRIO_MASK GENMASK(2, 0) 135 #define ENETC_TBMR_SET_PRIO(val) ((val) & ENETC_TBMR_PRIO_MASK) 136 #define ENETC_TBMR_EN BIT(31) 137 #define ENETC_TBSR 0x4 138 #define ENETC_TBBAR0 0x10 139 #define ENETC_TBBAR1 0x14 140 #define ENETC_TBPIR 0x18 141 #define ENETC_TBCIR 0x1c 142 #define ENETC_TBCIR_IDX_MASK 0xffff 143 #define ENETC_TBLENR 0x20 144 #define ENETC_TBIER 0xa0 145 #define ENETC_TBIER_TXTIE BIT(0) 146 #define ENETC_TBIDR 0xa4 147 #define ENETC_TBICR0 0xa8 148 #define ENETC_TBICR0_ICEN BIT(31) 149 #define ENETC_TBICR0_ICPT_MASK 0xf 150 #define ENETC_TBICR0_SET_ICPT(n) ((ilog2(n) + 1) & ENETC_TBICR0_ICPT_MASK) 151 #define ENETC_TBICR1 0xac 152 153 #define ENETC_RTBLENR_LEN(n) ((n) & ~0x7) 154 155 /* Port regs, offset: 1_0000h */ 156 #define ENETC_PORT_BASE 0x10000 157 #define ENETC_PMR 0x0000 158 #define ENETC_PMR_EN GENMASK(18, 16) 159 #define ENETC_PMR_PSPEED_MASK GENMASK(11, 8) 160 #define ENETC_PMR_PSPEED_10M 0 161 #define ENETC_PMR_PSPEED_100M BIT(8) 162 #define ENETC_PMR_PSPEED_1000M BIT(9) 163 #define ENETC_PMR_PSPEED_2500M BIT(10) 164 #define ENETC_PSR 0x0004 /* RO */ 165 #define ENETC_PSIPMR 0x0018 166 #define ENETC_PSIPMR_SET_UP(n) BIT(n) /* n = SI index */ 167 #define ENETC_PSIPMR_SET_MP(n) BIT((n) + 16) 168 #define ENETC_PSIPVMR 0x001c 169 #define ENETC_VLAN_PROMISC_MAP_ALL 0x7 170 #define ENETC_PSIPVMR_SET_VP(simap) ((simap) & 0x7) 171 #define ENETC_PSIPVMR_SET_VUTA(simap) (((simap) & 0x7) << 16) 172 #define ENETC_PSIPMAR0(n) (0x0100 + (n) * 0x8) /* n = SI index */ 173 #define ENETC_PSIPMAR1(n) (0x0104 + (n) * 0x8) 174 #define ENETC_PVCLCTR 0x0208 175 #define ENETC_VLAN_TYPE_C BIT(0) 176 #define ENETC_VLAN_TYPE_S BIT(1) 177 #define ENETC_PVCLCTR_OVTPIDL(bmp) ((bmp) & 0xff) /* VLAN_TYPE */ 178 #define ENETC_PSIVLANR(n) (0x0240 + (n) * 4) /* n = SI index */ 179 #define ENETC_PSIVLAN_EN BIT(31) 180 #define ENETC_PSIVLAN_SET_QOS(val) ((u32)(val) << 12) 181 #define ENETC_PTXMBAR 0x0608 182 #define ENETC_PCAPR0 0x0900 183 #define ENETC_PCAPR0_RXBDR(val) ((val) >> 24) 184 #define ENETC_PCAPR0_TXBDR(val) (((val) >> 16) & 0xff) 185 #define ENETC_PCAPR1 0x0904 186 #define ENETC_PSICFGR0(n) (0x0940 + (n) * 0xc) /* n = SI index */ 187 #define ENETC_PSICFGR0_SET_TXBDR(val) ((val) & 0xff) 188 #define ENETC_PSICFGR0_SET_RXBDR(val) (((val) & 0xff) << 16) 189 #define ENETC_PSICFGR0_VTE BIT(12) 190 #define ENETC_PSICFGR0_SIVIE BIT(14) 191 #define ENETC_PSICFGR0_ASE BIT(15) 192 #define ENETC_PSICFGR0_SIVC(bmp) (((bmp) & 0xff) << 24) /* VLAN_TYPE */ 193 194 #define ENETC_PTCCBSR0(n) (0x1110 + (n) * 8) /* n = 0 to 7*/ 195 #define ENETC_CBSE BIT(31) 196 #define ENETC_CBS_BW_MASK GENMASK(6, 0) 197 #define ENETC_PTCCBSR1(n) (0x1114 + (n) * 8) /* n = 0 to 7*/ 198 #define ENETC_RSSHASH_KEY_SIZE 40 199 #define ENETC_PRSSCAPR 0x1404 200 #define ENETC_PRSSCAPR_GET_NUM_RSS(val) (BIT((val) & 0xf) * 32) 201 #define ENETC_PRSSK(n) (0x1410 + (n) * 4) /* n = [0..9] */ 202 #define ENETC_PSIVLANFMR 0x1700 203 #define ENETC_PSIVLANFMR_VS BIT(0) 204 #define ENETC_PRFSMR 0x1800 205 #define ENETC_PRFSMR_RFSE BIT(31) 206 #define ENETC_PRFSCAPR 0x1804 207 #define ENETC_PRFSCAPR_GET_NUM_RFS(val) ((((val) & 0xf) + 1) * 16) 208 #define ENETC_PSIRFSCFGR(n) (0x1814 + (n) * 4) /* n = SI index */ 209 #define ENETC_PFPMR 0x1900 210 #define ENETC_PFPMR_PMACE BIT(1) 211 #define ENETC_PFPMR_MWLM BIT(0) 212 #define ENETC_EMDIO_BASE 0x1c00 213 #define ENETC_PSIUMHFR0(n, err) (((err) ? 0x1d08 : 0x1d00) + (n) * 0x10) 214 #define ENETC_PSIUMHFR1(n) (0x1d04 + (n) * 0x10) 215 #define ENETC_PSIMMHFR0(n, err) (((err) ? 0x1d00 : 0x1d08) + (n) * 0x10) 216 #define ENETC_PSIMMHFR1(n) (0x1d0c + (n) * 0x10) 217 #define ENETC_PSIVHFR0(n) (0x1e00 + (n) * 8) /* n = SI index */ 218 #define ENETC_PSIVHFR1(n) (0x1e04 + (n) * 8) /* n = SI index */ 219 #define ENETC_MMCSR 0x1f00 220 #define ENETC_MMCSR_ME BIT(16) 221 #define ENETC_PTCMSDUR(n) (0x2020 + (n) * 4) /* n = TC index [0..7] */ 222 223 #define ENETC_PM0_CMD_CFG 0x8008 224 #define ENETC_PM1_CMD_CFG 0x9008 225 #define ENETC_PM0_TX_EN BIT(0) 226 #define ENETC_PM0_RX_EN BIT(1) 227 #define ENETC_PM0_PROMISC BIT(4) 228 #define ENETC_PM0_CMD_XGLP BIT(10) 229 #define ENETC_PM0_CMD_TXP BIT(11) 230 #define ENETC_PM0_CMD_PHY_TX_EN BIT(15) 231 #define ENETC_PM0_CMD_SFD BIT(21) 232 #define ENETC_PM0_MAXFRM 0x8014 233 #define ENETC_SET_TX_MTU(val) ((val) << 16) 234 #define ENETC_SET_MAXFRM(val) ((val) & 0xffff) 235 236 #define ENETC_PM_IMDIO_BASE 0x8030 237 238 #define ENETC_PM0_IF_MODE 0x8300 239 #define ENETC_PMO_IFM_RG BIT(2) 240 #define ENETC_PM0_IFM_RLP (BIT(5) | BIT(11)) 241 #define ENETC_PM0_IFM_RGAUTO (BIT(15) | ENETC_PMO_IFM_RG | BIT(1)) 242 #define ENETC_PM0_IFM_XGMII BIT(12) 243 #define ENETC_PSIDCAPR 0x1b08 244 #define ENETC_PSIDCAPR_MSK GENMASK(15, 0) 245 #define ENETC_PSFCAPR 0x1b18 246 #define ENETC_PSFCAPR_MSK GENMASK(15, 0) 247 #define ENETC_PSGCAPR 0x1b28 248 #define ENETC_PSGCAPR_GCL_MSK GENMASK(18, 16) 249 #define ENETC_PSGCAPR_SGIT_MSK GENMASK(15, 0) 250 #define ENETC_PFMCAPR 0x1b38 251 #define ENETC_PFMCAPR_MSK GENMASK(15, 0) 252 253 /* MAC counters */ 254 #define ENETC_PM0_REOCT 0x8100 255 #define ENETC_PM0_RALN 0x8110 256 #define ENETC_PM0_RXPF 0x8118 257 #define ENETC_PM0_RFRM 0x8120 258 #define ENETC_PM0_RFCS 0x8128 259 #define ENETC_PM0_RVLAN 0x8130 260 #define ENETC_PM0_RERR 0x8138 261 #define ENETC_PM0_RUCA 0x8140 262 #define ENETC_PM0_RMCA 0x8148 263 #define ENETC_PM0_RBCA 0x8150 264 #define ENETC_PM0_RDRP 0x8158 265 #define ENETC_PM0_RPKT 0x8160 266 #define ENETC_PM0_RUND 0x8168 267 #define ENETC_PM0_R64 0x8170 268 #define ENETC_PM0_R127 0x8178 269 #define ENETC_PM0_R255 0x8180 270 #define ENETC_PM0_R511 0x8188 271 #define ENETC_PM0_R1023 0x8190 272 #define ENETC_PM0_R1522 0x8198 273 #define ENETC_PM0_R1523X 0x81A0 274 #define ENETC_PM0_ROVR 0x81A8 275 #define ENETC_PM0_RJBR 0x81B0 276 #define ENETC_PM0_RFRG 0x81B8 277 #define ENETC_PM0_RCNP 0x81C0 278 #define ENETC_PM0_RDRNTP 0x81C8 279 #define ENETC_PM0_TEOCT 0x8200 280 #define ENETC_PM0_TOCT 0x8208 281 #define ENETC_PM0_TCRSE 0x8210 282 #define ENETC_PM0_TXPF 0x8218 283 #define ENETC_PM0_TFRM 0x8220 284 #define ENETC_PM0_TFCS 0x8228 285 #define ENETC_PM0_TVLAN 0x8230 286 #define ENETC_PM0_TERR 0x8238 287 #define ENETC_PM0_TUCA 0x8240 288 #define ENETC_PM0_TMCA 0x8248 289 #define ENETC_PM0_TBCA 0x8250 290 #define ENETC_PM0_TPKT 0x8260 291 #define ENETC_PM0_TUND 0x8268 292 #define ENETC_PM0_T64 0x8270 293 #define ENETC_PM0_T127 0x8278 294 #define ENETC_PM0_T255 0x8280 295 #define ENETC_PM0_T511 0x8288 296 #define ENETC_PM0_T1023 0x8290 297 #define ENETC_PM0_T1522 0x8298 298 #define ENETC_PM0_T1523X 0x82A0 299 #define ENETC_PM0_TCNP 0x82C0 300 #define ENETC_PM0_TDFR 0x82D0 301 #define ENETC_PM0_TMCOL 0x82D8 302 #define ENETC_PM0_TSCOL 0x82E0 303 #define ENETC_PM0_TLCOL 0x82E8 304 #define ENETC_PM0_TECOL 0x82F0 305 306 /* Port counters */ 307 #define ENETC_PICDR(n) (0x0700 + (n) * 8) /* n = [0..3] */ 308 #define ENETC_PBFDSIR 0x0810 309 #define ENETC_PFDMSAPR 0x0814 310 #define ENETC_UFDMF 0x1680 311 #define ENETC_MFDMF 0x1684 312 #define ENETC_PUFDVFR 0x1780 313 #define ENETC_PMFDVFR 0x1784 314 #define ENETC_PBFDVFR 0x1788 315 316 /** Global regs, offset: 2_0000h */ 317 #define ENETC_GLOBAL_BASE 0x20000 318 #define ENETC_G_EIPBRR0 0x0bf8 319 #define ENETC_G_EIPBRR1 0x0bfc 320 #define ENETC_G_EPFBLPR(n) (0xd00 + 4 * (n)) 321 #define ENETC_G_EPFBLPR1_XGMII 0x80000000 322 323 /* PCI device info */ 324 struct enetc_hw { 325 /* SI registers, used by all PCI functions */ 326 void __iomem *reg; 327 /* Port registers, PF only */ 328 void __iomem *port; 329 /* IP global registers, PF only */ 330 void __iomem *global; 331 }; 332 333 /* ENETC register accessors */ 334 335 /* MDIO issue workaround (on LS1028A) - 336 * Due to a hardware issue, an access to MDIO registers 337 * that is concurrent with other ENETC register accesses 338 * may lead to the MDIO access being dropped or corrupted. 339 * To protect the MDIO accesses a readers-writers locking 340 * scheme is used, where the MDIO register accesses are 341 * protected by write locks to insure exclusivity, while 342 * the remaining ENETC registers are accessed under read 343 * locks since they only compete with MDIO accesses. 344 */ 345 extern rwlock_t enetc_mdio_lock; 346 347 /* use this locking primitive only on the fast datapath to 348 * group together multiple non-MDIO register accesses to 349 * minimize the overhead of the lock 350 */ 351 static inline void enetc_lock_mdio(void) 352 { 353 read_lock(&enetc_mdio_lock); 354 } 355 356 static inline void enetc_unlock_mdio(void) 357 { 358 read_unlock(&enetc_mdio_lock); 359 } 360 361 /* use these accessors only on the fast datapath under 362 * the enetc_lock_mdio() locking primitive to minimize 363 * the overhead of the lock 364 */ 365 static inline u32 enetc_rd_reg_hot(void __iomem *reg) 366 { 367 lockdep_assert_held(&enetc_mdio_lock); 368 369 return ioread32(reg); 370 } 371 372 static inline void enetc_wr_reg_hot(void __iomem *reg, u32 val) 373 { 374 lockdep_assert_held(&enetc_mdio_lock); 375 376 iowrite32(val, reg); 377 } 378 379 /* internal helpers for the MDIO w/a */ 380 static inline u32 _enetc_rd_reg_wa(void __iomem *reg) 381 { 382 u32 val; 383 384 enetc_lock_mdio(); 385 val = ioread32(reg); 386 enetc_unlock_mdio(); 387 388 return val; 389 } 390 391 static inline void _enetc_wr_reg_wa(void __iomem *reg, u32 val) 392 { 393 enetc_lock_mdio(); 394 iowrite32(val, reg); 395 enetc_unlock_mdio(); 396 } 397 398 static inline u32 _enetc_rd_mdio_reg_wa(void __iomem *reg) 399 { 400 unsigned long flags; 401 u32 val; 402 403 write_lock_irqsave(&enetc_mdio_lock, flags); 404 val = ioread32(reg); 405 write_unlock_irqrestore(&enetc_mdio_lock, flags); 406 407 return val; 408 } 409 410 static inline void _enetc_wr_mdio_reg_wa(void __iomem *reg, u32 val) 411 { 412 unsigned long flags; 413 414 write_lock_irqsave(&enetc_mdio_lock, flags); 415 iowrite32(val, reg); 416 write_unlock_irqrestore(&enetc_mdio_lock, flags); 417 } 418 419 #ifdef ioread64 420 static inline u64 _enetc_rd_reg64(void __iomem *reg) 421 { 422 return ioread64(reg); 423 } 424 #else 425 /* using this to read out stats on 32b systems */ 426 static inline u64 _enetc_rd_reg64(void __iomem *reg) 427 { 428 u32 low, high, tmp; 429 430 do { 431 high = ioread32(reg + 4); 432 low = ioread32(reg); 433 tmp = ioread32(reg + 4); 434 } while (high != tmp); 435 436 return le64_to_cpu((__le64)high << 32 | low); 437 } 438 #endif 439 440 static inline u64 _enetc_rd_reg64_wa(void __iomem *reg) 441 { 442 u64 val; 443 444 enetc_lock_mdio(); 445 val = _enetc_rd_reg64(reg); 446 enetc_unlock_mdio(); 447 448 return val; 449 } 450 451 /* general register accessors */ 452 #define enetc_rd_reg(reg) _enetc_rd_reg_wa((reg)) 453 #define enetc_wr_reg(reg, val) _enetc_wr_reg_wa((reg), (val)) 454 #define enetc_rd(hw, off) enetc_rd_reg((hw)->reg + (off)) 455 #define enetc_wr(hw, off, val) enetc_wr_reg((hw)->reg + (off), val) 456 #define enetc_rd64(hw, off) _enetc_rd_reg64_wa((hw)->reg + (off)) 457 /* port register accessors - PF only */ 458 #define enetc_port_rd(hw, off) enetc_rd_reg((hw)->port + (off)) 459 #define enetc_port_wr(hw, off, val) enetc_wr_reg((hw)->port + (off), val) 460 #define enetc_port_rd_mdio(hw, off) _enetc_rd_mdio_reg_wa((hw)->port + (off)) 461 #define enetc_port_wr_mdio(hw, off, val) _enetc_wr_mdio_reg_wa(\ 462 (hw)->port + (off), val) 463 /* global register accessors - PF only */ 464 #define enetc_global_rd(hw, off) enetc_rd_reg((hw)->global + (off)) 465 #define enetc_global_wr(hw, off, val) enetc_wr_reg((hw)->global + (off), val) 466 /* BDR register accessors, see ENETC_BDR() */ 467 #define enetc_bdr_rd(hw, t, n, off) \ 468 enetc_rd(hw, ENETC_BDR(t, n, off)) 469 #define enetc_bdr_wr(hw, t, n, off, val) \ 470 enetc_wr(hw, ENETC_BDR(t, n, off), val) 471 #define enetc_txbdr_rd(hw, n, off) enetc_bdr_rd(hw, TX, n, off) 472 #define enetc_rxbdr_rd(hw, n, off) enetc_bdr_rd(hw, RX, n, off) 473 #define enetc_txbdr_wr(hw, n, off, val) \ 474 enetc_bdr_wr(hw, TX, n, off, val) 475 #define enetc_rxbdr_wr(hw, n, off, val) \ 476 enetc_bdr_wr(hw, RX, n, off, val) 477 478 /* Buffer Descriptors (BD) */ 479 union enetc_tx_bd { 480 struct { 481 __le64 addr; 482 __le16 buf_len; 483 __le16 frm_len; 484 union { 485 struct { 486 u8 reserved[3]; 487 u8 flags; 488 }; /* default layout */ 489 __le32 txstart; 490 __le32 lstatus; 491 }; 492 }; 493 struct { 494 __le32 tstamp; 495 __le16 tpid; 496 __le16 vid; 497 u8 reserved[6]; 498 u8 e_flags; 499 u8 flags; 500 } ext; /* Tx BD extension */ 501 struct { 502 __le32 tstamp; 503 u8 reserved[10]; 504 u8 status; 505 u8 flags; 506 } wb; /* writeback descriptor */ 507 }; 508 509 enum enetc_txbd_flags { 510 ENETC_TXBD_FLAGS_RES0 = BIT(0), /* reserved */ 511 ENETC_TXBD_FLAGS_TSE = BIT(1), 512 ENETC_TXBD_FLAGS_W = BIT(2), 513 ENETC_TXBD_FLAGS_RES3 = BIT(3), /* reserved */ 514 ENETC_TXBD_FLAGS_TXSTART = BIT(4), 515 ENETC_TXBD_FLAGS_EX = BIT(6), 516 ENETC_TXBD_FLAGS_F = BIT(7) 517 }; 518 #define ENETC_TXBD_TXSTART_MASK GENMASK(24, 0) 519 #define ENETC_TXBD_FLAGS_OFFSET 24 520 521 static inline __le32 enetc_txbd_set_tx_start(u64 tx_start, u8 flags) 522 { 523 u32 temp; 524 525 temp = (tx_start >> 5 & ENETC_TXBD_TXSTART_MASK) | 526 (flags << ENETC_TXBD_FLAGS_OFFSET); 527 528 return cpu_to_le32(temp); 529 } 530 531 static inline void enetc_clear_tx_bd(union enetc_tx_bd *txbd) 532 { 533 memset(txbd, 0, sizeof(*txbd)); 534 } 535 536 /* Extension flags */ 537 #define ENETC_TXBD_E_FLAGS_VLAN_INS BIT(0) 538 #define ENETC_TXBD_E_FLAGS_TWO_STEP_PTP BIT(2) 539 540 union enetc_rx_bd { 541 struct { 542 __le64 addr; 543 u8 reserved[8]; 544 } w; 545 struct { 546 __le16 inet_csum; 547 __le16 parse_summary; 548 __le32 rss_hash; 549 __le16 buf_len; 550 __le16 vlan_opt; 551 union { 552 struct { 553 __le16 flags; 554 __le16 error; 555 }; 556 __le32 lstatus; 557 }; 558 } r; 559 struct { 560 __le32 tstamp; 561 u8 reserved[12]; 562 } ext; 563 }; 564 565 #define ENETC_RXBD_LSTATUS_R BIT(30) 566 #define ENETC_RXBD_LSTATUS_F BIT(31) 567 #define ENETC_RXBD_ERR_MASK 0xff 568 #define ENETC_RXBD_LSTATUS(flags) ((flags) << 16) 569 #define ENETC_RXBD_FLAG_VLAN BIT(9) 570 #define ENETC_RXBD_FLAG_TSTMP BIT(10) 571 572 #define ENETC_MAC_ADDR_FILT_CNT 8 /* # of supported entries per port */ 573 #define EMETC_MAC_ADDR_FILT_RES 3 /* # of reserved entries at the beginning */ 574 #define ENETC_MAX_NUM_VFS 2 575 576 #define ENETC_CBD_FLAGS_SF BIT(7) /* short format */ 577 #define ENETC_CBD_STATUS_MASK 0xf 578 579 struct enetc_cmd_rfse { 580 u8 smac_h[6]; 581 u8 smac_m[6]; 582 u8 dmac_h[6]; 583 u8 dmac_m[6]; 584 __be32 sip_h[4]; 585 __be32 sip_m[4]; 586 __be32 dip_h[4]; 587 __be32 dip_m[4]; 588 u16 ethtype_h; 589 u16 ethtype_m; 590 u16 ethtype4_h; 591 u16 ethtype4_m; 592 u16 sport_h; 593 u16 sport_m; 594 u16 dport_h; 595 u16 dport_m; 596 u16 vlan_h; 597 u16 vlan_m; 598 u8 proto_h; 599 u8 proto_m; 600 u16 flags; 601 u16 result; 602 u16 mode; 603 }; 604 605 #define ENETC_RFSE_EN BIT(15) 606 #define ENETC_RFSE_MODE_BD 2 607 608 static inline void enetc_get_primary_mac_addr(struct enetc_hw *hw, u8 *addr) 609 { 610 *(u32 *)addr = __raw_readl(hw->reg + ENETC_SIPMAR0); 611 *(u16 *)(addr + 4) = __raw_readw(hw->reg + ENETC_SIPMAR1); 612 } 613 614 #define ENETC_SI_INT_IDX 0 615 /* base index for Rx/Tx interrupts */ 616 #define ENETC_BDR_INT_BASE_IDX 1 617 618 /* Messaging */ 619 620 /* Command completion status */ 621 enum enetc_msg_cmd_status { 622 ENETC_MSG_CMD_STATUS_OK, 623 ENETC_MSG_CMD_STATUS_FAIL 624 }; 625 626 /* VSI-PSI command message types */ 627 enum enetc_msg_cmd_type { 628 ENETC_MSG_CMD_MNG_MAC = 1, /* manage MAC address */ 629 ENETC_MSG_CMD_MNG_RX_MAC_FILTER,/* manage RX MAC table */ 630 ENETC_MSG_CMD_MNG_RX_VLAN_FILTER /* manage RX VLAN table */ 631 }; 632 633 /* VSI-PSI command action types */ 634 enum enetc_msg_cmd_action_type { 635 ENETC_MSG_CMD_MNG_ADD = 1, 636 ENETC_MSG_CMD_MNG_REMOVE 637 }; 638 639 /* PSI-VSI command header format */ 640 struct enetc_msg_cmd_header { 641 u16 type; /* command class type */ 642 u16 id; /* denotes the specific required action */ 643 }; 644 645 /* Common H/W utility functions */ 646 647 static inline void enetc_bdr_enable_rxvlan(struct enetc_hw *hw, int idx, 648 bool en) 649 { 650 u32 val = enetc_rxbdr_rd(hw, idx, ENETC_RBMR); 651 652 val = (val & ~ENETC_RBMR_VTE) | (en ? ENETC_RBMR_VTE : 0); 653 enetc_rxbdr_wr(hw, idx, ENETC_RBMR, val); 654 } 655 656 static inline void enetc_bdr_enable_txvlan(struct enetc_hw *hw, int idx, 657 bool en) 658 { 659 u32 val = enetc_txbdr_rd(hw, idx, ENETC_TBMR); 660 661 val = (val & ~ENETC_TBMR_VIH) | (en ? ENETC_TBMR_VIH : 0); 662 enetc_txbdr_wr(hw, idx, ENETC_TBMR, val); 663 } 664 665 static inline void enetc_set_bdr_prio(struct enetc_hw *hw, int bdr_idx, 666 int prio) 667 { 668 u32 val = enetc_txbdr_rd(hw, bdr_idx, ENETC_TBMR); 669 670 val &= ~ENETC_TBMR_PRIO_MASK; 671 val |= ENETC_TBMR_SET_PRIO(prio); 672 enetc_txbdr_wr(hw, bdr_idx, ENETC_TBMR, val); 673 } 674 675 enum bdcr_cmd_class { 676 BDCR_CMD_UNSPEC = 0, 677 BDCR_CMD_MAC_FILTER, 678 BDCR_CMD_VLAN_FILTER, 679 BDCR_CMD_RSS, 680 BDCR_CMD_RFS, 681 BDCR_CMD_PORT_GCL, 682 BDCR_CMD_RECV_CLASSIFIER, 683 BDCR_CMD_STREAM_IDENTIFY, 684 BDCR_CMD_STREAM_FILTER, 685 BDCR_CMD_STREAM_GCL, 686 BDCR_CMD_FLOW_METER, 687 __BDCR_CMD_MAX_LEN, 688 BDCR_CMD_MAX_LEN = __BDCR_CMD_MAX_LEN - 1, 689 }; 690 691 /* class 5, command 0 */ 692 struct tgs_gcl_conf { 693 u8 atc; /* init gate value */ 694 u8 res[7]; 695 struct { 696 u8 res1[4]; 697 __le16 acl_len; 698 u8 res2[2]; 699 }; 700 }; 701 702 /* gate control list entry */ 703 struct gce { 704 __le32 period; 705 u8 gate; 706 u8 res[3]; 707 }; 708 709 /* tgs_gcl_conf address point to this data space */ 710 struct tgs_gcl_data { 711 __le32 btl; 712 __le32 bth; 713 __le32 ct; 714 __le32 cte; 715 struct gce entry[]; 716 }; 717 718 /* class 7, command 0, Stream Identity Entry Configuration */ 719 struct streamid_conf { 720 __le32 stream_handle; /* init gate value */ 721 __le32 iports; 722 u8 id_type; 723 u8 oui[3]; 724 u8 res[3]; 725 u8 en; 726 }; 727 728 #define ENETC_CBDR_SID_VID_MASK 0xfff 729 #define ENETC_CBDR_SID_VIDM BIT(12) 730 #define ENETC_CBDR_SID_TG_MASK 0xc000 731 /* streamid_conf address point to this data space */ 732 struct streamid_data { 733 union { 734 u8 dmac[6]; 735 u8 smac[6]; 736 }; 737 u16 vid_vidm_tg; 738 }; 739 740 #define ENETC_CBDR_SFI_PRI_MASK 0x7 741 #define ENETC_CBDR_SFI_PRIM BIT(3) 742 #define ENETC_CBDR_SFI_BLOV BIT(4) 743 #define ENETC_CBDR_SFI_BLEN BIT(5) 744 #define ENETC_CBDR_SFI_MSDUEN BIT(6) 745 #define ENETC_CBDR_SFI_FMITEN BIT(7) 746 #define ENETC_CBDR_SFI_ENABLE BIT(7) 747 /* class 8, command 0, Stream Filter Instance, Short Format */ 748 struct sfi_conf { 749 __le32 stream_handle; 750 u8 multi; 751 u8 res[2]; 752 u8 sthm; 753 /* Max Service Data Unit or Flow Meter Instance Table index. 754 * Depending on the value of FLT this represents either Max 755 * Service Data Unit (max frame size) allowed by the filter 756 * entry or is an index into the Flow Meter Instance table 757 * index identifying the policer which will be used to police 758 * it. 759 */ 760 __le16 fm_inst_table_index; 761 __le16 msdu; 762 __le16 sg_inst_table_index; 763 u8 res1[2]; 764 __le32 input_ports; 765 u8 res2[3]; 766 u8 en; 767 }; 768 769 /* class 8, command 2 stream Filter Instance status query short format 770 * command no need structure define 771 * Stream Filter Instance Query Statistics Response data 772 */ 773 struct sfi_counter_data { 774 u32 matchl; 775 u32 matchh; 776 u32 msdu_dropl; 777 u32 msdu_droph; 778 u32 stream_gate_dropl; 779 u32 stream_gate_droph; 780 u32 flow_meter_dropl; 781 u32 flow_meter_droph; 782 }; 783 784 #define ENETC_CBDR_SGI_OIPV_MASK 0x7 785 #define ENETC_CBDR_SGI_OIPV_EN BIT(3) 786 #define ENETC_CBDR_SGI_CGTST BIT(6) 787 #define ENETC_CBDR_SGI_OGTST BIT(7) 788 #define ENETC_CBDR_SGI_CFG_CHG BIT(1) 789 #define ENETC_CBDR_SGI_CFG_PND BIT(2) 790 #define ENETC_CBDR_SGI_OEX BIT(4) 791 #define ENETC_CBDR_SGI_OEXEN BIT(5) 792 #define ENETC_CBDR_SGI_IRX BIT(6) 793 #define ENETC_CBDR_SGI_IRXEN BIT(7) 794 #define ENETC_CBDR_SGI_ACLLEN_MASK 0x3 795 #define ENETC_CBDR_SGI_OCLLEN_MASK 0xc 796 #define ENETC_CBDR_SGI_EN BIT(7) 797 /* class 9, command 0, Stream Gate Instance Table, Short Format 798 * class 9, command 2, Stream Gate Instance Table entry query write back 799 * Short Format 800 */ 801 struct sgi_table { 802 u8 res[8]; 803 u8 oipv; 804 u8 res0[2]; 805 u8 ocgtst; 806 u8 res1[7]; 807 u8 gset; 808 u8 oacl_len; 809 u8 res2[2]; 810 u8 en; 811 }; 812 813 #define ENETC_CBDR_SGI_AIPV_MASK 0x7 814 #define ENETC_CBDR_SGI_AIPV_EN BIT(3) 815 #define ENETC_CBDR_SGI_AGTST BIT(7) 816 817 /* class 9, command 1, Stream Gate Control List, Long Format */ 818 struct sgcl_conf { 819 u8 aipv; 820 u8 res[2]; 821 u8 agtst; 822 u8 res1[4]; 823 union { 824 struct { 825 u8 res2[4]; 826 u8 acl_len; 827 u8 res3[3]; 828 }; 829 u8 cct[8]; /* Config change time */ 830 }; 831 }; 832 833 #define ENETC_CBDR_SGL_IOMEN BIT(0) 834 #define ENETC_CBDR_SGL_IPVEN BIT(3) 835 #define ENETC_CBDR_SGL_GTST BIT(4) 836 #define ENETC_CBDR_SGL_IPV_MASK 0xe 837 /* Stream Gate Control List Entry */ 838 struct sgce { 839 u32 interval; 840 u8 msdu[3]; 841 u8 multi; 842 }; 843 844 /* stream control list class 9 , cmd 1 data buffer */ 845 struct sgcl_data { 846 u32 btl; 847 u32 bth; 848 u32 ct; 849 u32 cte; 850 struct sgce sgcl[0]; 851 }; 852 853 #define ENETC_CBDR_FMI_MR BIT(0) 854 #define ENETC_CBDR_FMI_MREN BIT(1) 855 #define ENETC_CBDR_FMI_DOY BIT(2) 856 #define ENETC_CBDR_FMI_CM BIT(3) 857 #define ENETC_CBDR_FMI_CF BIT(4) 858 #define ENETC_CBDR_FMI_NDOR BIT(5) 859 #define ENETC_CBDR_FMI_OALEN BIT(6) 860 #define ENETC_CBDR_FMI_IRFPP_MASK GENMASK(4, 0) 861 862 /* class 10: command 0/1, Flow Meter Instance Set, short Format */ 863 struct fmi_conf { 864 __le32 cir; 865 __le32 cbs; 866 __le32 eir; 867 __le32 ebs; 868 u8 conf; 869 u8 res1; 870 u8 ir_fpp; 871 u8 res2[4]; 872 u8 en; 873 }; 874 875 struct enetc_cbd { 876 union{ 877 struct sfi_conf sfi_conf; 878 struct sgi_table sgi_table; 879 struct fmi_conf fmi_conf; 880 struct { 881 __le32 addr[2]; 882 union { 883 __le32 opt[4]; 884 struct tgs_gcl_conf gcl_conf; 885 struct streamid_conf sid_set; 886 struct sgcl_conf sgcl_conf; 887 }; 888 }; /* Long format */ 889 __le32 data[6]; 890 }; 891 __le16 index; 892 __le16 length; 893 u8 cmd; 894 u8 cls; 895 u8 _res; 896 u8 status_flags; 897 }; 898 899 #define ENETC_CLK 400000000ULL 900 static inline u32 enetc_cycles_to_usecs(u32 cycles) 901 { 902 return (u32)div_u64(cycles * 1000000ULL, ENETC_CLK); 903 } 904 905 static inline u32 enetc_usecs_to_cycles(u32 usecs) 906 { 907 return (u32)div_u64(usecs * ENETC_CLK, 1000000ULL); 908 } 909 910 /* port time gating control register */ 911 #define ENETC_QBV_PTGCR_OFFSET 0x11a00 912 #define ENETC_QBV_TGE BIT(31) 913 #define ENETC_QBV_TGPE BIT(30) 914 915 /* Port time gating capability register */ 916 #define ENETC_QBV_PTGCAPR_OFFSET 0x11a08 917 #define ENETC_QBV_MAX_GCL_LEN_MASK GENMASK(15, 0) 918 919 /* Port time specific departure */ 920 #define ENETC_PTCTSDR(n) (0x1210 + 4 * (n)) 921 #define ENETC_TSDE BIT(31) 922 923 /* PSFP setting */ 924 #define ENETC_PPSFPMR 0x11b00 925 #define ENETC_PPSFPMR_PSFPEN BIT(0) 926 #define ENETC_PPSFPMR_VS BIT(1) 927 #define ENETC_PPSFPMR_PVC BIT(2) 928 #define ENETC_PPSFPMR_PVZC BIT(3) 929