1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ 2 /* Copyright 2017-2019 NXP */ 3 4 #include <linux/bitops.h> 5 6 /* ENETC device IDs */ 7 #define ENETC_DEV_ID_PF 0xe100 8 #define ENETC_DEV_ID_VF 0xef00 9 #define ENETC_DEV_ID_PTP 0xee02 10 11 /* ENETC register block BAR */ 12 #define ENETC_BAR_REGS 0 13 14 /** SI regs, offset: 0h */ 15 #define ENETC_SIMR 0 16 #define ENETC_SIMR_EN BIT(31) 17 #define ENETC_SIMR_RSSE BIT(0) 18 #define ENETC_SICTR0 0x18 19 #define ENETC_SICTR1 0x1c 20 #define ENETC_SIPCAPR0 0x20 21 #define ENETC_SIPCAPR0_QBV BIT(4) 22 #define ENETC_SIPCAPR0_PSFP BIT(9) 23 #define ENETC_SIPCAPR0_RSS BIT(8) 24 #define ENETC_SIPCAPR1 0x24 25 #define ENETC_SITGTGR 0x30 26 #define ENETC_SIRBGCR 0x38 27 /* cache attribute registers for transactions initiated by ENETC */ 28 #define ENETC_SICAR0 0x40 29 #define ENETC_SICAR1 0x44 30 #define ENETC_SICAR2 0x48 31 /* rd snoop, no alloc 32 * wr snoop, no alloc, partial cache line update for BDs and full cache line 33 * update for data 34 */ 35 #define ENETC_SICAR_RD_COHERENT 0x2b2b0000 36 #define ENETC_SICAR_WR_COHERENT 0x00006727 37 #define ENETC_SICAR_MSI 0x00300030 /* rd/wr device, no snoop, no alloc */ 38 39 #define ENETC_SIPMAR0 0x80 40 #define ENETC_SIPMAR1 0x84 41 42 /* VF-PF Message passing */ 43 #define ENETC_DEFAULT_MSG_SIZE 1024 /* and max size */ 44 /* msg size encoding: default and max msg value of 1024B encoded as 0 */ 45 static inline u32 enetc_vsi_set_msize(u32 size) 46 { 47 return size < ENETC_DEFAULT_MSG_SIZE ? size >> 5 : 0; 48 } 49 50 #define ENETC_PSIMSGRR 0x204 51 #define ENETC_PSIMSGRR_MR_MASK GENMASK(2, 1) 52 #define ENETC_PSIMSGRR_MR(n) BIT((n) + 1) /* n = VSI index */ 53 #define ENETC_PSIVMSGRCVAR0(n) (0x210 + (n) * 0x8) /* n = VSI index */ 54 #define ENETC_PSIVMSGRCVAR1(n) (0x214 + (n) * 0x8) 55 56 #define ENETC_VSIMSGSR 0x204 /* RO */ 57 #define ENETC_VSIMSGSR_MB BIT(0) 58 #define ENETC_VSIMSGSR_MS BIT(1) 59 #define ENETC_VSIMSGSNDAR0 0x210 60 #define ENETC_VSIMSGSNDAR1 0x214 61 62 #define ENETC_SIMSGSR_SET_MC(val) ((val) << 16) 63 #define ENETC_SIMSGSR_GET_MC(val) ((val) >> 16) 64 65 /* SI statistics */ 66 #define ENETC_SIROCT 0x300 67 #define ENETC_SIRFRM 0x308 68 #define ENETC_SIRUCA 0x310 69 #define ENETC_SIRMCA 0x318 70 #define ENETC_SITOCT 0x320 71 #define ENETC_SITFRM 0x328 72 #define ENETC_SITUCA 0x330 73 #define ENETC_SITMCA 0x338 74 #define ENETC_RBDCR(n) (0x8180 + (n) * 0x200) 75 76 /* Control BDR regs */ 77 #define ENETC_SICBDRMR 0x800 78 #define ENETC_SICBDRSR 0x804 /* RO */ 79 #define ENETC_SICBDRBAR0 0x810 80 #define ENETC_SICBDRBAR1 0x814 81 #define ENETC_SICBDRPIR 0x818 82 #define ENETC_SICBDRCIR 0x81c 83 #define ENETC_SICBDRLENR 0x820 84 85 #define ENETC_SICAPR0 0x900 86 #define ENETC_SICAPR1 0x904 87 88 #define ENETC_PSIIER 0xa00 89 #define ENETC_PSIIER_MR_MASK GENMASK(2, 1) 90 #define ENETC_PSIIDR 0xa08 91 #define ENETC_SITXIDR 0xa18 92 #define ENETC_SIRXIDR 0xa28 93 #define ENETC_SIMSIVR 0xa30 94 95 #define ENETC_SIMSITRV(n) (0xB00 + (n) * 0x4) 96 #define ENETC_SIMSIRRV(n) (0xB80 + (n) * 0x4) 97 98 #define ENETC_SIUEFDCR 0xe28 99 100 #define ENETC_SIRFSCAPR 0x1200 101 #define ENETC_SIRFSCAPR_GET_NUM_RFS(val) ((val) & 0x7f) 102 #define ENETC_SIRSSCAPR 0x1600 103 #define ENETC_SIRSSCAPR_GET_NUM_RSS(val) (BIT((val) & 0xf) * 32) 104 105 /** SI BDR sub-blocks, n = 0..7 */ 106 enum enetc_bdr_type {TX, RX}; 107 #define ENETC_BDR_OFF(i) ((i) * 0x200) 108 #define ENETC_BDR(t, i, r) (0x8000 + (t) * 0x100 + ENETC_BDR_OFF(i) + (r)) 109 /* RX BDR reg offsets */ 110 #define ENETC_RBMR 0 111 #define ENETC_RBMR_BDS BIT(2) 112 #define ENETC_RBMR_VTE BIT(5) 113 #define ENETC_RBMR_EN BIT(31) 114 #define ENETC_RBSR 0x4 115 #define ENETC_RBBSR 0x8 116 #define ENETC_RBCIR 0xc 117 #define ENETC_RBBAR0 0x10 118 #define ENETC_RBBAR1 0x14 119 #define ENETC_RBPIR 0x18 120 #define ENETC_RBLENR 0x20 121 #define ENETC_RBIER 0xa0 122 #define ENETC_RBIER_RXTIE BIT(0) 123 #define ENETC_RBIDR 0xa4 124 #define ENETC_RBICIR0 0xa8 125 #define ENETC_RBICIR0_ICEN BIT(31) 126 127 /* TX BDR reg offsets */ 128 #define ENETC_TBMR 0 129 #define ENETC_TBSR_BUSY BIT(0) 130 #define ENETC_TBMR_VIH BIT(9) 131 #define ENETC_TBMR_PRIO_MASK GENMASK(2, 0) 132 #define ENETC_TBMR_SET_PRIO(val) ((val) & ENETC_TBMR_PRIO_MASK) 133 #define ENETC_TBMR_EN BIT(31) 134 #define ENETC_TBSR 0x4 135 #define ENETC_TBBAR0 0x10 136 #define ENETC_TBBAR1 0x14 137 #define ENETC_TBPIR 0x18 138 #define ENETC_TBCIR 0x1c 139 #define ENETC_TBCIR_IDX_MASK 0xffff 140 #define ENETC_TBLENR 0x20 141 #define ENETC_TBIER 0xa0 142 #define ENETC_TBIER_TXTIE BIT(0) 143 #define ENETC_TBIDR 0xa4 144 #define ENETC_TBICIR0 0xa8 145 #define ENETC_TBICIR0_ICEN BIT(31) 146 147 #define ENETC_RTBLENR_LEN(n) ((n) & ~0x7) 148 149 /* Port regs, offset: 1_0000h */ 150 #define ENETC_PORT_BASE 0x10000 151 #define ENETC_PMR 0x0000 152 #define ENETC_PMR_EN GENMASK(18, 16) 153 #define ENETC_PMR_PSPEED_MASK GENMASK(11, 8) 154 #define ENETC_PMR_PSPEED_10M 0 155 #define ENETC_PMR_PSPEED_100M BIT(8) 156 #define ENETC_PMR_PSPEED_1000M BIT(9) 157 #define ENETC_PMR_PSPEED_2500M BIT(10) 158 #define ENETC_PSR 0x0004 /* RO */ 159 #define ENETC_PSIPMR 0x0018 160 #define ENETC_PSIPMR_SET_UP(n) BIT(n) /* n = SI index */ 161 #define ENETC_PSIPMR_SET_MP(n) BIT((n) + 16) 162 #define ENETC_PSIPVMR 0x001c 163 #define ENETC_VLAN_PROMISC_MAP_ALL 0x7 164 #define ENETC_PSIPVMR_SET_VP(simap) ((simap) & 0x7) 165 #define ENETC_PSIPVMR_SET_VUTA(simap) (((simap) & 0x7) << 16) 166 #define ENETC_PSIPMAR0(n) (0x0100 + (n) * 0x8) /* n = SI index */ 167 #define ENETC_PSIPMAR1(n) (0x0104 + (n) * 0x8) 168 #define ENETC_PVCLCTR 0x0208 169 #define ENETC_VLAN_TYPE_C BIT(0) 170 #define ENETC_VLAN_TYPE_S BIT(1) 171 #define ENETC_PVCLCTR_OVTPIDL(bmp) ((bmp) & 0xff) /* VLAN_TYPE */ 172 #define ENETC_PSIVLANR(n) (0x0240 + (n) * 4) /* n = SI index */ 173 #define ENETC_PSIVLAN_EN BIT(31) 174 #define ENETC_PSIVLAN_SET_QOS(val) ((u32)(val) << 12) 175 #define ENETC_PTXMBAR 0x0608 176 #define ENETC_PCAPR0 0x0900 177 #define ENETC_PCAPR0_RXBDR(val) ((val) >> 24) 178 #define ENETC_PCAPR0_TXBDR(val) (((val) >> 16) & 0xff) 179 #define ENETC_PCAPR1 0x0904 180 #define ENETC_PSICFGR0(n) (0x0940 + (n) * 0xc) /* n = SI index */ 181 #define ENETC_PSICFGR0_SET_TXBDR(val) ((val) & 0xff) 182 #define ENETC_PSICFGR0_SET_RXBDR(val) (((val) & 0xff) << 16) 183 #define ENETC_PSICFGR0_VTE BIT(12) 184 #define ENETC_PSICFGR0_SIVIE BIT(14) 185 #define ENETC_PSICFGR0_ASE BIT(15) 186 #define ENETC_PSICFGR0_SIVC(bmp) (((bmp) & 0xff) << 24) /* VLAN_TYPE */ 187 188 #define ENETC_PTCCBSR0(n) (0x1110 + (n) * 8) /* n = 0 to 7*/ 189 #define ENETC_CBSE BIT(31) 190 #define ENETC_CBS_BW_MASK GENMASK(6, 0) 191 #define ENETC_PTCCBSR1(n) (0x1114 + (n) * 8) /* n = 0 to 7*/ 192 #define ENETC_RSSHASH_KEY_SIZE 40 193 #define ENETC_PRSSK(n) (0x1410 + (n) * 4) /* n = [0..9] */ 194 #define ENETC_PSIVLANFMR 0x1700 195 #define ENETC_PSIVLANFMR_VS BIT(0) 196 #define ENETC_PRFSMR 0x1800 197 #define ENETC_PRFSMR_RFSE BIT(31) 198 #define ENETC_PRFSCAPR 0x1804 199 #define ENETC_PRFSCAPR_GET_NUM_RFS(val) ((((val) & 0xf) + 1) * 16) 200 #define ENETC_PSIRFSCFGR(n) (0x1814 + (n) * 4) /* n = SI index */ 201 #define ENETC_PFPMR 0x1900 202 #define ENETC_PFPMR_PMACE BIT(1) 203 #define ENETC_PFPMR_MWLM BIT(0) 204 #define ENETC_EMDIO_BASE 0x1c00 205 #define ENETC_PSIUMHFR0(n, err) (((err) ? 0x1d08 : 0x1d00) + (n) * 0x10) 206 #define ENETC_PSIUMHFR1(n) (0x1d04 + (n) * 0x10) 207 #define ENETC_PSIMMHFR0(n, err) (((err) ? 0x1d00 : 0x1d08) + (n) * 0x10) 208 #define ENETC_PSIMMHFR1(n) (0x1d0c + (n) * 0x10) 209 #define ENETC_PSIVHFR0(n) (0x1e00 + (n) * 8) /* n = SI index */ 210 #define ENETC_PSIVHFR1(n) (0x1e04 + (n) * 8) /* n = SI index */ 211 #define ENETC_MMCSR 0x1f00 212 #define ENETC_MMCSR_ME BIT(16) 213 #define ENETC_PTCMSDUR(n) (0x2020 + (n) * 4) /* n = TC index [0..7] */ 214 215 #define ENETC_PM0_CMD_CFG 0x8008 216 #define ENETC_PM1_CMD_CFG 0x9008 217 #define ENETC_PM0_TX_EN BIT(0) 218 #define ENETC_PM0_RX_EN BIT(1) 219 #define ENETC_PM0_PROMISC BIT(4) 220 #define ENETC_PM0_CMD_XGLP BIT(10) 221 #define ENETC_PM0_CMD_TXP BIT(11) 222 #define ENETC_PM0_CMD_PHY_TX_EN BIT(15) 223 #define ENETC_PM0_CMD_SFD BIT(21) 224 #define ENETC_PM0_MAXFRM 0x8014 225 #define ENETC_SET_TX_MTU(val) ((val) << 16) 226 #define ENETC_SET_MAXFRM(val) ((val) & 0xffff) 227 #define ENETC_PM0_IF_MODE 0x8300 228 #define ENETC_PMO_IFM_RG BIT(2) 229 #define ENETC_PM0_IFM_RLP (BIT(5) | BIT(11)) 230 #define ENETC_PM0_IFM_RGAUTO (BIT(15) | ENETC_PMO_IFM_RG | BIT(1)) 231 #define ENETC_PM0_IFM_XGMII BIT(12) 232 #define ENETC_PSIDCAPR 0x1b08 233 #define ENETC_PSIDCAPR_MSK GENMASK(15, 0) 234 #define ENETC_PSFCAPR 0x1b18 235 #define ENETC_PSFCAPR_MSK GENMASK(15, 0) 236 #define ENETC_PSGCAPR 0x1b28 237 #define ENETC_PSGCAPR_GCL_MSK GENMASK(18, 16) 238 #define ENETC_PSGCAPR_SGIT_MSK GENMASK(15, 0) 239 #define ENETC_PFMCAPR 0x1b38 240 #define ENETC_PFMCAPR_MSK GENMASK(15, 0) 241 242 /* MAC counters */ 243 #define ENETC_PM0_REOCT 0x8100 244 #define ENETC_PM0_RALN 0x8110 245 #define ENETC_PM0_RXPF 0x8118 246 #define ENETC_PM0_RFRM 0x8120 247 #define ENETC_PM0_RFCS 0x8128 248 #define ENETC_PM0_RVLAN 0x8130 249 #define ENETC_PM0_RERR 0x8138 250 #define ENETC_PM0_RUCA 0x8140 251 #define ENETC_PM0_RMCA 0x8148 252 #define ENETC_PM0_RBCA 0x8150 253 #define ENETC_PM0_RDRP 0x8158 254 #define ENETC_PM0_RPKT 0x8160 255 #define ENETC_PM0_RUND 0x8168 256 #define ENETC_PM0_R64 0x8170 257 #define ENETC_PM0_R127 0x8178 258 #define ENETC_PM0_R255 0x8180 259 #define ENETC_PM0_R511 0x8188 260 #define ENETC_PM0_R1023 0x8190 261 #define ENETC_PM0_R1518 0x8198 262 #define ENETC_PM0_R1519X 0x81A0 263 #define ENETC_PM0_ROVR 0x81A8 264 #define ENETC_PM0_RJBR 0x81B0 265 #define ENETC_PM0_RFRG 0x81B8 266 #define ENETC_PM0_RCNP 0x81C0 267 #define ENETC_PM0_RDRNTP 0x81C8 268 #define ENETC_PM0_TEOCT 0x8200 269 #define ENETC_PM0_TOCT 0x8208 270 #define ENETC_PM0_TCRSE 0x8210 271 #define ENETC_PM0_TXPF 0x8218 272 #define ENETC_PM0_TFRM 0x8220 273 #define ENETC_PM0_TFCS 0x8228 274 #define ENETC_PM0_TVLAN 0x8230 275 #define ENETC_PM0_TERR 0x8238 276 #define ENETC_PM0_TUCA 0x8240 277 #define ENETC_PM0_TMCA 0x8248 278 #define ENETC_PM0_TBCA 0x8250 279 #define ENETC_PM0_TPKT 0x8260 280 #define ENETC_PM0_TUND 0x8268 281 #define ENETC_PM0_T127 0x8278 282 #define ENETC_PM0_T1023 0x8290 283 #define ENETC_PM0_T1518 0x8298 284 #define ENETC_PM0_TCNP 0x82C0 285 #define ENETC_PM0_TDFR 0x82D0 286 #define ENETC_PM0_TMCOL 0x82D8 287 #define ENETC_PM0_TSCOL 0x82E0 288 #define ENETC_PM0_TLCOL 0x82E8 289 #define ENETC_PM0_TECOL 0x82F0 290 291 /* Port counters */ 292 #define ENETC_PICDR(n) (0x0700 + (n) * 8) /* n = [0..3] */ 293 #define ENETC_PBFDSIR 0x0810 294 #define ENETC_PFDMSAPR 0x0814 295 #define ENETC_UFDMF 0x1680 296 #define ENETC_MFDMF 0x1684 297 #define ENETC_PUFDVFR 0x1780 298 #define ENETC_PMFDVFR 0x1784 299 #define ENETC_PBFDVFR 0x1788 300 301 /** Global regs, offset: 2_0000h */ 302 #define ENETC_GLOBAL_BASE 0x20000 303 #define ENETC_G_EIPBRR0 0x0bf8 304 #define ENETC_G_EIPBRR1 0x0bfc 305 #define ENETC_G_EPFBLPR(n) (0xd00 + 4 * (n)) 306 #define ENETC_G_EPFBLPR1_XGMII 0x80000000 307 308 /* PCI device info */ 309 struct enetc_hw { 310 /* SI registers, used by all PCI functions */ 311 void __iomem *reg; 312 /* Port registers, PF only */ 313 void __iomem *port; 314 /* IP global registers, PF only */ 315 void __iomem *global; 316 }; 317 318 /* general register accessors */ 319 #define enetc_rd_reg(reg) ioread32((reg)) 320 #define enetc_wr_reg(reg, val) iowrite32((val), (reg)) 321 #ifdef ioread64 322 #define enetc_rd_reg64(reg) ioread64((reg)) 323 #else 324 /* using this to read out stats on 32b systems */ 325 static inline u64 enetc_rd_reg64(void __iomem *reg) 326 { 327 u32 low, high, tmp; 328 329 do { 330 high = ioread32(reg + 4); 331 low = ioread32(reg); 332 tmp = ioread32(reg + 4); 333 } while (high != tmp); 334 335 return le64_to_cpu((__le64)high << 32 | low); 336 } 337 #endif 338 339 #define enetc_rd(hw, off) enetc_rd_reg((hw)->reg + (off)) 340 #define enetc_wr(hw, off, val) enetc_wr_reg((hw)->reg + (off), val) 341 #define enetc_rd64(hw, off) enetc_rd_reg64((hw)->reg + (off)) 342 /* port register accessors - PF only */ 343 #define enetc_port_rd(hw, off) enetc_rd_reg((hw)->port + (off)) 344 #define enetc_port_wr(hw, off, val) enetc_wr_reg((hw)->port + (off), val) 345 /* global register accessors - PF only */ 346 #define enetc_global_rd(hw, off) enetc_rd_reg((hw)->global + (off)) 347 #define enetc_global_wr(hw, off, val) enetc_wr_reg((hw)->global + (off), val) 348 /* BDR register accessors, see ENETC_BDR() */ 349 #define enetc_bdr_rd(hw, t, n, off) \ 350 enetc_rd(hw, ENETC_BDR(t, n, off)) 351 #define enetc_bdr_wr(hw, t, n, off, val) \ 352 enetc_wr(hw, ENETC_BDR(t, n, off), val) 353 #define enetc_txbdr_rd(hw, n, off) enetc_bdr_rd(hw, TX, n, off) 354 #define enetc_rxbdr_rd(hw, n, off) enetc_bdr_rd(hw, RX, n, off) 355 #define enetc_txbdr_wr(hw, n, off, val) \ 356 enetc_bdr_wr(hw, TX, n, off, val) 357 #define enetc_rxbdr_wr(hw, n, off, val) \ 358 enetc_bdr_wr(hw, RX, n, off, val) 359 360 /* Buffer Descriptors (BD) */ 361 union enetc_tx_bd { 362 struct { 363 __le64 addr; 364 __le16 buf_len; 365 __le16 frm_len; 366 union { 367 struct { 368 __le16 l3_csoff; 369 u8 l4_csoff; 370 u8 flags; 371 }; /* default layout */ 372 __le32 txstart; 373 __le32 lstatus; 374 }; 375 }; 376 struct { 377 __le32 tstamp; 378 __le16 tpid; 379 __le16 vid; 380 u8 reserved[6]; 381 u8 e_flags; 382 u8 flags; 383 } ext; /* Tx BD extension */ 384 struct { 385 __le32 tstamp; 386 u8 reserved[10]; 387 u8 status; 388 u8 flags; 389 } wb; /* writeback descriptor */ 390 }; 391 392 #define ENETC_TXBD_FLAGS_L4CS BIT(0) 393 #define ENETC_TXBD_FLAGS_TSE BIT(1) 394 #define ENETC_TXBD_FLAGS_W BIT(2) 395 #define ENETC_TXBD_FLAGS_CSUM BIT(3) 396 #define ENETC_TXBD_FLAGS_TXSTART BIT(4) 397 #define ENETC_TXBD_FLAGS_EX BIT(6) 398 #define ENETC_TXBD_FLAGS_F BIT(7) 399 #define ENETC_TXBD_TXSTART_MASK GENMASK(24, 0) 400 #define ENETC_TXBD_FLAGS_OFFSET 24 401 static inline void enetc_clear_tx_bd(union enetc_tx_bd *txbd) 402 { 403 memset(txbd, 0, sizeof(*txbd)); 404 } 405 406 /* L3 csum flags */ 407 #define ENETC_TXBD_L3_IPCS BIT(7) 408 #define ENETC_TXBD_L3_IPV6 BIT(15) 409 410 #define ENETC_TXBD_L3_START_MASK GENMASK(6, 0) 411 #define ENETC_TXBD_L3_SET_HSIZE(val) ((((val) >> 2) & 0x7f) << 8) 412 413 /* Extension flags */ 414 #define ENETC_TXBD_E_FLAGS_VLAN_INS BIT(0) 415 #define ENETC_TXBD_E_FLAGS_TWO_STEP_PTP BIT(2) 416 417 static inline __le16 enetc_txbd_l3_csoff(int start, int hdr_sz, u16 l3_flags) 418 { 419 return cpu_to_le16(l3_flags | ENETC_TXBD_L3_SET_HSIZE(hdr_sz) | 420 (start & ENETC_TXBD_L3_START_MASK)); 421 } 422 423 /* L4 csum flags */ 424 #define ENETC_TXBD_L4_UDP BIT(5) 425 #define ENETC_TXBD_L4_TCP BIT(6) 426 427 union enetc_rx_bd { 428 struct { 429 __le64 addr; 430 u8 reserved[8]; 431 } w; 432 struct { 433 __le16 inet_csum; 434 __le16 parse_summary; 435 __le32 rss_hash; 436 __le16 buf_len; 437 __le16 vlan_opt; 438 union { 439 struct { 440 __le16 flags; 441 __le16 error; 442 }; 443 __le32 lstatus; 444 }; 445 } r; 446 struct { 447 __le32 tstamp; 448 u8 reserved[12]; 449 } ext; 450 }; 451 452 #define ENETC_RXBD_LSTATUS_R BIT(30) 453 #define ENETC_RXBD_LSTATUS_F BIT(31) 454 #define ENETC_RXBD_ERR_MASK 0xff 455 #define ENETC_RXBD_LSTATUS(flags) ((flags) << 16) 456 #define ENETC_RXBD_FLAG_VLAN BIT(9) 457 #define ENETC_RXBD_FLAG_TSTMP BIT(10) 458 459 #define ENETC_MAC_ADDR_FILT_CNT 8 /* # of supported entries per port */ 460 #define EMETC_MAC_ADDR_FILT_RES 3 /* # of reserved entries at the beginning */ 461 #define ENETC_MAX_NUM_VFS 2 462 463 #define ENETC_CBD_FLAGS_SF BIT(7) /* short format */ 464 #define ENETC_CBD_STATUS_MASK 0xf 465 466 struct enetc_cmd_rfse { 467 u8 smac_h[6]; 468 u8 smac_m[6]; 469 u8 dmac_h[6]; 470 u8 dmac_m[6]; 471 u32 sip_h[4]; 472 u32 sip_m[4]; 473 u32 dip_h[4]; 474 u32 dip_m[4]; 475 u16 ethtype_h; 476 u16 ethtype_m; 477 u16 ethtype4_h; 478 u16 ethtype4_m; 479 u16 sport_h; 480 u16 sport_m; 481 u16 dport_h; 482 u16 dport_m; 483 u16 vlan_h; 484 u16 vlan_m; 485 u8 proto_h; 486 u8 proto_m; 487 u16 flags; 488 u16 result; 489 u16 mode; 490 }; 491 492 #define ENETC_RFSE_EN BIT(15) 493 #define ENETC_RFSE_MODE_BD 2 494 495 static inline void enetc_get_primary_mac_addr(struct enetc_hw *hw, u8 *addr) 496 { 497 *(u32 *)addr = __raw_readl(hw->reg + ENETC_SIPMAR0); 498 *(u16 *)(addr + 4) = __raw_readw(hw->reg + ENETC_SIPMAR1); 499 } 500 501 #define ENETC_SI_INT_IDX 0 502 /* base index for Rx/Tx interrupts */ 503 #define ENETC_BDR_INT_BASE_IDX 1 504 505 /* Messaging */ 506 507 /* Command completion status */ 508 enum enetc_msg_cmd_status { 509 ENETC_MSG_CMD_STATUS_OK, 510 ENETC_MSG_CMD_STATUS_FAIL 511 }; 512 513 /* VSI-PSI command message types */ 514 enum enetc_msg_cmd_type { 515 ENETC_MSG_CMD_MNG_MAC = 1, /* manage MAC address */ 516 ENETC_MSG_CMD_MNG_RX_MAC_FILTER,/* manage RX MAC table */ 517 ENETC_MSG_CMD_MNG_RX_VLAN_FILTER /* manage RX VLAN table */ 518 }; 519 520 /* VSI-PSI command action types */ 521 enum enetc_msg_cmd_action_type { 522 ENETC_MSG_CMD_MNG_ADD = 1, 523 ENETC_MSG_CMD_MNG_REMOVE 524 }; 525 526 /* PSI-VSI command header format */ 527 struct enetc_msg_cmd_header { 528 u16 type; /* command class type */ 529 u16 id; /* denotes the specific required action */ 530 }; 531 532 /* Common H/W utility functions */ 533 534 static inline void enetc_bdr_enable_rxvlan(struct enetc_hw *hw, int idx, 535 bool en) 536 { 537 u32 val = enetc_rxbdr_rd(hw, idx, ENETC_RBMR); 538 539 val = (val & ~ENETC_RBMR_VTE) | (en ? ENETC_RBMR_VTE : 0); 540 enetc_rxbdr_wr(hw, idx, ENETC_RBMR, val); 541 } 542 543 static inline void enetc_bdr_enable_txvlan(struct enetc_hw *hw, int idx, 544 bool en) 545 { 546 u32 val = enetc_txbdr_rd(hw, idx, ENETC_TBMR); 547 548 val = (val & ~ENETC_TBMR_VIH) | (en ? ENETC_TBMR_VIH : 0); 549 enetc_txbdr_wr(hw, idx, ENETC_TBMR, val); 550 } 551 552 static inline void enetc_set_bdr_prio(struct enetc_hw *hw, int bdr_idx, 553 int prio) 554 { 555 u32 val = enetc_txbdr_rd(hw, bdr_idx, ENETC_TBMR); 556 557 val &= ~ENETC_TBMR_PRIO_MASK; 558 val |= ENETC_TBMR_SET_PRIO(prio); 559 enetc_txbdr_wr(hw, bdr_idx, ENETC_TBMR, val); 560 } 561 562 enum bdcr_cmd_class { 563 BDCR_CMD_UNSPEC = 0, 564 BDCR_CMD_MAC_FILTER, 565 BDCR_CMD_VLAN_FILTER, 566 BDCR_CMD_RSS, 567 BDCR_CMD_RFS, 568 BDCR_CMD_PORT_GCL, 569 BDCR_CMD_RECV_CLASSIFIER, 570 BDCR_CMD_STREAM_IDENTIFY, 571 BDCR_CMD_STREAM_FILTER, 572 BDCR_CMD_STREAM_GCL, 573 __BDCR_CMD_MAX_LEN, 574 BDCR_CMD_MAX_LEN = __BDCR_CMD_MAX_LEN - 1, 575 }; 576 577 /* class 5, command 0 */ 578 struct tgs_gcl_conf { 579 u8 atc; /* init gate value */ 580 u8 res[7]; 581 struct { 582 u8 res1[4]; 583 __le16 acl_len; 584 u8 res2[2]; 585 }; 586 }; 587 588 /* gate control list entry */ 589 struct gce { 590 __le32 period; 591 u8 gate; 592 u8 res[3]; 593 }; 594 595 /* tgs_gcl_conf address point to this data space */ 596 struct tgs_gcl_data { 597 __le32 btl; 598 __le32 bth; 599 __le32 ct; 600 __le32 cte; 601 struct gce entry[]; 602 }; 603 604 /* class 7, command 0, Stream Identity Entry Configuration */ 605 struct streamid_conf { 606 __le32 stream_handle; /* init gate value */ 607 __le32 iports; 608 u8 id_type; 609 u8 oui[3]; 610 u8 res[3]; 611 u8 en; 612 }; 613 614 #define ENETC_CBDR_SID_VID_MASK 0xfff 615 #define ENETC_CBDR_SID_VIDM BIT(12) 616 #define ENETC_CBDR_SID_TG_MASK 0xc000 617 /* streamid_conf address point to this data space */ 618 struct streamid_data { 619 union { 620 u8 dmac[6]; 621 u8 smac[6]; 622 }; 623 u16 vid_vidm_tg; 624 }; 625 626 #define ENETC_CBDR_SFI_PRI_MASK 0x7 627 #define ENETC_CBDR_SFI_PRIM BIT(3) 628 #define ENETC_CBDR_SFI_BLOV BIT(4) 629 #define ENETC_CBDR_SFI_BLEN BIT(5) 630 #define ENETC_CBDR_SFI_MSDUEN BIT(6) 631 #define ENETC_CBDR_SFI_FMITEN BIT(7) 632 #define ENETC_CBDR_SFI_ENABLE BIT(7) 633 /* class 8, command 0, Stream Filter Instance, Short Format */ 634 struct sfi_conf { 635 __le32 stream_handle; 636 u8 multi; 637 u8 res[2]; 638 u8 sthm; 639 /* Max Service Data Unit or Flow Meter Instance Table index. 640 * Depending on the value of FLT this represents either Max 641 * Service Data Unit (max frame size) allowed by the filter 642 * entry or is an index into the Flow Meter Instance table 643 * index identifying the policer which will be used to police 644 * it. 645 */ 646 __le16 fm_inst_table_index; 647 __le16 msdu; 648 __le16 sg_inst_table_index; 649 u8 res1[2]; 650 __le32 input_ports; 651 u8 res2[3]; 652 u8 en; 653 }; 654 655 /* class 8, command 2 stream Filter Instance status query short format 656 * command no need structure define 657 * Stream Filter Instance Query Statistics Response data 658 */ 659 struct sfi_counter_data { 660 u32 matchl; 661 u32 matchh; 662 u32 msdu_dropl; 663 u32 msdu_droph; 664 u32 stream_gate_dropl; 665 u32 stream_gate_droph; 666 u32 flow_meter_dropl; 667 u32 flow_meter_droph; 668 }; 669 670 #define ENETC_CBDR_SGI_OIPV_MASK 0x7 671 #define ENETC_CBDR_SGI_OIPV_EN BIT(3) 672 #define ENETC_CBDR_SGI_CGTST BIT(6) 673 #define ENETC_CBDR_SGI_OGTST BIT(7) 674 #define ENETC_CBDR_SGI_CFG_CHG BIT(1) 675 #define ENETC_CBDR_SGI_CFG_PND BIT(2) 676 #define ENETC_CBDR_SGI_OEX BIT(4) 677 #define ENETC_CBDR_SGI_OEXEN BIT(5) 678 #define ENETC_CBDR_SGI_IRX BIT(6) 679 #define ENETC_CBDR_SGI_IRXEN BIT(7) 680 #define ENETC_CBDR_SGI_ACLLEN_MASK 0x3 681 #define ENETC_CBDR_SGI_OCLLEN_MASK 0xc 682 #define ENETC_CBDR_SGI_EN BIT(7) 683 /* class 9, command 0, Stream Gate Instance Table, Short Format 684 * class 9, command 2, Stream Gate Instance Table entry query write back 685 * Short Format 686 */ 687 struct sgi_table { 688 u8 res[8]; 689 u8 oipv; 690 u8 res0[2]; 691 u8 ocgtst; 692 u8 res1[7]; 693 u8 gset; 694 u8 oacl_len; 695 u8 res2[2]; 696 u8 en; 697 }; 698 699 #define ENETC_CBDR_SGI_AIPV_MASK 0x7 700 #define ENETC_CBDR_SGI_AIPV_EN BIT(3) 701 #define ENETC_CBDR_SGI_AGTST BIT(7) 702 703 /* class 9, command 1, Stream Gate Control List, Long Format */ 704 struct sgcl_conf { 705 u8 aipv; 706 u8 res[2]; 707 u8 agtst; 708 u8 res1[4]; 709 union { 710 struct { 711 u8 res2[4]; 712 u8 acl_len; 713 u8 res3[3]; 714 }; 715 u8 cct[8]; /* Config change time */ 716 }; 717 }; 718 719 #define ENETC_CBDR_SGL_IOMEN BIT(0) 720 #define ENETC_CBDR_SGL_IPVEN BIT(3) 721 #define ENETC_CBDR_SGL_GTST BIT(4) 722 #define ENETC_CBDR_SGL_IPV_MASK 0xe 723 /* Stream Gate Control List Entry */ 724 struct sgce { 725 u32 interval; 726 u8 msdu[3]; 727 u8 multi; 728 }; 729 730 /* stream control list class 9 , cmd 1 data buffer */ 731 struct sgcl_data { 732 u32 btl; 733 u32 bth; 734 u32 ct; 735 u32 cte; 736 struct sgce sgcl[0]; 737 }; 738 739 struct enetc_cbd { 740 union{ 741 struct sfi_conf sfi_conf; 742 struct sgi_table sgi_table; 743 struct { 744 __le32 addr[2]; 745 union { 746 __le32 opt[4]; 747 struct tgs_gcl_conf gcl_conf; 748 struct streamid_conf sid_set; 749 struct sgcl_conf sgcl_conf; 750 }; 751 }; /* Long format */ 752 __le32 data[6]; 753 }; 754 __le16 index; 755 __le16 length; 756 u8 cmd; 757 u8 cls; 758 u8 _res; 759 u8 status_flags; 760 }; 761 762 #define ENETC_CLK 400000000ULL 763 764 /* port time gating control register */ 765 #define ENETC_QBV_PTGCR_OFFSET 0x11a00 766 #define ENETC_QBV_TGE BIT(31) 767 #define ENETC_QBV_TGPE BIT(30) 768 769 /* Port time gating capability register */ 770 #define ENETC_QBV_PTGCAPR_OFFSET 0x11a08 771 #define ENETC_QBV_MAX_GCL_LEN_MASK GENMASK(15, 0) 772 773 /* Port time specific departure */ 774 #define ENETC_PTCTSDR(n) (0x1210 + 4 * (n)) 775 #define ENETC_TSDE BIT(31) 776 777 /* PSFP setting */ 778 #define ENETC_PPSFPMR 0x11b00 779 #define ENETC_PPSFPMR_PSFPEN BIT(0) 780 #define ENETC_PPSFPMR_VS BIT(1) 781 #define ENETC_PPSFPMR_PVC BIT(2) 782 #define ENETC_PPSFPMR_PVZC BIT(3) 783