1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ 2 /* Copyright 2017-2019 NXP */ 3 4 #include <linux/timer.h> 5 #include <linux/pci.h> 6 #include <linux/netdevice.h> 7 #include <linux/etherdevice.h> 8 #include <linux/dma-mapping.h> 9 #include <linux/skbuff.h> 10 #include <linux/ethtool.h> 11 #include <linux/if_vlan.h> 12 #include <linux/phylink.h> 13 #include <linux/dim.h> 14 15 #include "enetc_hw.h" 16 17 #define ENETC_MAC_MAXFRM_SIZE 9600 18 #define ENETC_MAX_MTU (ENETC_MAC_MAXFRM_SIZE - \ 19 (ETH_FCS_LEN + ETH_HLEN + VLAN_HLEN)) 20 21 #define ENETC_CBD_DATA_MEM_ALIGN 64 22 23 struct enetc_tx_swbd { 24 union { 25 struct sk_buff *skb; 26 struct xdp_frame *xdp_frame; 27 }; 28 dma_addr_t dma; 29 struct page *page; /* valid only if is_xdp_tx */ 30 u16 page_offset; /* valid only if is_xdp_tx */ 31 u16 len; 32 enum dma_data_direction dir; 33 u8 is_dma_page:1; 34 u8 check_wb:1; 35 u8 do_twostep_tstamp:1; 36 u8 is_eof:1; 37 u8 is_xdp_tx:1; 38 u8 is_xdp_redirect:1; 39 u8 qbv_en:1; 40 }; 41 42 #define ENETC_RX_MAXFRM_SIZE ENETC_MAC_MAXFRM_SIZE 43 #define ENETC_RXB_TRUESIZE 2048 /* PAGE_SIZE >> 1 */ 44 #define ENETC_RXB_PAD NET_SKB_PAD /* add extra space if needed */ 45 #define ENETC_RXB_DMA_SIZE \ 46 (SKB_WITH_OVERHEAD(ENETC_RXB_TRUESIZE) - ENETC_RXB_PAD) 47 #define ENETC_RXB_DMA_SIZE_XDP \ 48 (SKB_WITH_OVERHEAD(ENETC_RXB_TRUESIZE) - XDP_PACKET_HEADROOM) 49 50 struct enetc_rx_swbd { 51 dma_addr_t dma; 52 struct page *page; 53 u16 page_offset; 54 enum dma_data_direction dir; 55 u16 len; 56 }; 57 58 /* ENETC overhead: optional extension BD + 1 BD gap */ 59 #define ENETC_TXBDS_NEEDED(val) ((val) + 2) 60 /* max # of chained Tx BDs is 15, including head and extension BD */ 61 #define ENETC_MAX_SKB_FRAGS 13 62 #define ENETC_TXBDS_MAX_NEEDED ENETC_TXBDS_NEEDED(ENETC_MAX_SKB_FRAGS + 1) 63 64 struct enetc_ring_stats { 65 unsigned int packets; 66 unsigned int bytes; 67 unsigned int rx_alloc_errs; 68 unsigned int xdp_drops; 69 unsigned int xdp_tx; 70 unsigned int xdp_tx_drops; 71 unsigned int xdp_redirect; 72 unsigned int xdp_redirect_failures; 73 unsigned int xdp_redirect_sg; 74 unsigned int recycles; 75 unsigned int recycle_failures; 76 unsigned int win_drop; 77 }; 78 79 struct enetc_xdp_data { 80 struct xdp_rxq_info rxq; 81 struct bpf_prog *prog; 82 int xdp_tx_in_flight; 83 }; 84 85 #define ENETC_RX_RING_DEFAULT_SIZE 2048 86 #define ENETC_TX_RING_DEFAULT_SIZE 2048 87 #define ENETC_DEFAULT_TX_WORK (ENETC_TX_RING_DEFAULT_SIZE / 2) 88 89 struct enetc_bdr { 90 struct device *dev; /* for DMA mapping */ 91 struct net_device *ndev; 92 void *bd_base; /* points to Rx or Tx BD ring */ 93 union { 94 void __iomem *tpir; 95 void __iomem *rcir; 96 }; 97 u16 index; 98 u16 prio; 99 int bd_count; /* # of BDs */ 100 int next_to_use; 101 int next_to_clean; 102 union { 103 struct enetc_tx_swbd *tx_swbd; 104 struct enetc_rx_swbd *rx_swbd; 105 }; 106 union { 107 void __iomem *tcir; /* Tx */ 108 int next_to_alloc; /* Rx */ 109 }; 110 void __iomem *idr; /* Interrupt Detect Register pointer */ 111 112 int buffer_offset; 113 struct enetc_xdp_data xdp; 114 115 struct enetc_ring_stats stats; 116 117 dma_addr_t bd_dma_base; 118 u8 tsd_enable; /* Time specific departure */ 119 bool ext_en; /* enable h/w descriptor extensions */ 120 121 /* DMA buffer for TSO headers */ 122 char *tso_headers; 123 dma_addr_t tso_headers_dma; 124 } ____cacheline_aligned_in_smp; 125 126 static inline void enetc_bdr_idx_inc(struct enetc_bdr *bdr, int *i) 127 { 128 if (unlikely(++*i == bdr->bd_count)) 129 *i = 0; 130 } 131 132 static inline int enetc_bd_unused(struct enetc_bdr *bdr) 133 { 134 if (bdr->next_to_clean > bdr->next_to_use) 135 return bdr->next_to_clean - bdr->next_to_use - 1; 136 137 return bdr->bd_count + bdr->next_to_clean - bdr->next_to_use - 1; 138 } 139 140 static inline int enetc_swbd_unused(struct enetc_bdr *bdr) 141 { 142 if (bdr->next_to_clean > bdr->next_to_alloc) 143 return bdr->next_to_clean - bdr->next_to_alloc - 1; 144 145 return bdr->bd_count + bdr->next_to_clean - bdr->next_to_alloc - 1; 146 } 147 148 /* Control BD ring */ 149 #define ENETC_CBDR_DEFAULT_SIZE 64 150 struct enetc_cbdr { 151 void *bd_base; /* points to Rx or Tx BD ring */ 152 void __iomem *pir; 153 void __iomem *cir; 154 void __iomem *mr; /* mode register */ 155 156 int bd_count; /* # of BDs */ 157 int next_to_use; 158 int next_to_clean; 159 160 dma_addr_t bd_dma_base; 161 struct device *dma_dev; 162 }; 163 164 #define ENETC_TXBD(BDR, i) (&(((union enetc_tx_bd *)((BDR).bd_base))[i])) 165 166 static inline union enetc_rx_bd *enetc_rxbd(struct enetc_bdr *rx_ring, int i) 167 { 168 int hw_idx = i; 169 170 #ifdef CONFIG_FSL_ENETC_PTP_CLOCK 171 if (rx_ring->ext_en) 172 hw_idx = 2 * i; 173 #endif 174 return &(((union enetc_rx_bd *)rx_ring->bd_base)[hw_idx]); 175 } 176 177 static inline void enetc_rxbd_next(struct enetc_bdr *rx_ring, 178 union enetc_rx_bd **old_rxbd, int *old_index) 179 { 180 union enetc_rx_bd *new_rxbd = *old_rxbd; 181 int new_index = *old_index; 182 183 new_rxbd++; 184 185 #ifdef CONFIG_FSL_ENETC_PTP_CLOCK 186 if (rx_ring->ext_en) 187 new_rxbd++; 188 #endif 189 190 if (unlikely(++new_index == rx_ring->bd_count)) { 191 new_rxbd = rx_ring->bd_base; 192 new_index = 0; 193 } 194 195 *old_rxbd = new_rxbd; 196 *old_index = new_index; 197 } 198 199 static inline union enetc_rx_bd *enetc_rxbd_ext(union enetc_rx_bd *rxbd) 200 { 201 return ++rxbd; 202 } 203 204 struct enetc_msg_swbd { 205 void *vaddr; 206 dma_addr_t dma; 207 int size; 208 }; 209 210 #define ENETC_REV1 0x1 211 enum enetc_errata { 212 ENETC_ERR_VLAN_ISOL = BIT(0), 213 ENETC_ERR_UCMCSWP = BIT(1), 214 }; 215 216 #define ENETC_SI_F_QBV BIT(0) 217 #define ENETC_SI_F_PSFP BIT(1) 218 219 /* PCI IEP device data */ 220 struct enetc_si { 221 struct pci_dev *pdev; 222 struct enetc_hw hw; 223 enum enetc_errata errata; 224 225 struct net_device *ndev; /* back ref. */ 226 227 struct enetc_cbdr cbd_ring; 228 229 int num_rx_rings; /* how many rings are available in the SI */ 230 int num_tx_rings; 231 int num_fs_entries; 232 int num_rss; /* number of RSS buckets */ 233 unsigned short pad; 234 int hw_features; 235 }; 236 237 #define ENETC_SI_ALIGN 32 238 239 static inline void *enetc_si_priv(const struct enetc_si *si) 240 { 241 return (char *)si + ALIGN(sizeof(struct enetc_si), ENETC_SI_ALIGN); 242 } 243 244 static inline bool enetc_si_is_pf(struct enetc_si *si) 245 { 246 return !!(si->hw.port); 247 } 248 249 static inline int enetc_pf_to_port(struct pci_dev *pf_pdev) 250 { 251 switch (pf_pdev->devfn) { 252 case 0: 253 return 0; 254 case 1: 255 return 1; 256 case 2: 257 return 2; 258 case 6: 259 return 3; 260 default: 261 return -1; 262 } 263 } 264 265 #define ENETC_MAX_NUM_TXQS 8 266 #define ENETC_INT_NAME_MAX (IFNAMSIZ + 8) 267 268 struct enetc_int_vector { 269 void __iomem *rbier; 270 void __iomem *tbier_base; 271 void __iomem *ricr1; 272 unsigned long tx_rings_map; 273 int count_tx_rings; 274 u32 rx_ictt; 275 u16 comp_cnt; 276 bool rx_dim_en, rx_napi_work; 277 struct napi_struct napi ____cacheline_aligned_in_smp; 278 struct dim rx_dim ____cacheline_aligned_in_smp; 279 char name[ENETC_INT_NAME_MAX]; 280 281 struct enetc_bdr rx_ring; 282 struct enetc_bdr tx_ring[]; 283 } ____cacheline_aligned_in_smp; 284 285 struct enetc_cls_rule { 286 struct ethtool_rx_flow_spec fs; 287 int used; 288 }; 289 290 #define ENETC_MAX_BDR_INT 2 /* fixed to max # of available cpus */ 291 struct psfp_cap { 292 u32 max_streamid; 293 u32 max_psfp_filter; 294 u32 max_psfp_gate; 295 u32 max_psfp_gatelist; 296 u32 max_psfp_meter; 297 }; 298 299 #define ENETC_F_TX_TSTAMP_MASK 0xff 300 /* TODO: more hardware offloads */ 301 enum enetc_active_offloads { 302 /* 8 bits reserved for TX timestamp types (hwtstamp_tx_types) */ 303 ENETC_F_TX_TSTAMP = BIT(0), 304 ENETC_F_TX_ONESTEP_SYNC_TSTAMP = BIT(1), 305 306 ENETC_F_RX_TSTAMP = BIT(8), 307 ENETC_F_QBV = BIT(9), 308 ENETC_F_QCI = BIT(10), 309 }; 310 311 enum enetc_flags_bit { 312 ENETC_TX_ONESTEP_TSTAMP_IN_PROGRESS = 0, 313 }; 314 315 /* interrupt coalescing modes */ 316 enum enetc_ic_mode { 317 /* one interrupt per frame */ 318 ENETC_IC_NONE = 0, 319 /* activated when int coalescing time is set to a non-0 value */ 320 ENETC_IC_RX_MANUAL = BIT(0), 321 ENETC_IC_TX_MANUAL = BIT(1), 322 /* use dynamic interrupt moderation */ 323 ENETC_IC_RX_ADAPTIVE = BIT(2), 324 }; 325 326 #define ENETC_RXIC_PKTTHR min_t(u32, 256, ENETC_RX_RING_DEFAULT_SIZE / 2) 327 #define ENETC_TXIC_PKTTHR min_t(u32, 128, ENETC_TX_RING_DEFAULT_SIZE / 2) 328 #define ENETC_TXIC_TIMETHR enetc_usecs_to_cycles(600) 329 330 struct enetc_ndev_priv { 331 struct net_device *ndev; 332 struct device *dev; /* dma-mapping device */ 333 struct enetc_si *si; 334 335 int bdr_int_num; /* number of Rx/Tx ring interrupts */ 336 struct enetc_int_vector *int_vector[ENETC_MAX_BDR_INT]; 337 u16 num_rx_rings, num_tx_rings; 338 u16 rx_bd_count, tx_bd_count; 339 340 u16 msg_enable; 341 enum enetc_active_offloads active_offloads; 342 343 u32 speed; /* store speed for compare update pspeed */ 344 345 struct enetc_bdr **xdp_tx_ring; 346 struct enetc_bdr *tx_ring[16]; 347 struct enetc_bdr *rx_ring[16]; 348 349 struct enetc_cls_rule *cls_rules; 350 351 struct psfp_cap psfp_cap; 352 353 struct phylink *phylink; 354 int ic_mode; 355 u32 tx_ictt; 356 357 struct bpf_prog *xdp_prog; 358 359 unsigned long flags; 360 361 struct work_struct tx_onestep_tstamp; 362 struct sk_buff_head tx_skbs; 363 }; 364 365 /* Messaging */ 366 367 /* VF-PF set primary MAC address message format */ 368 struct enetc_msg_cmd_set_primary_mac { 369 struct enetc_msg_cmd_header header; 370 struct sockaddr mac; 371 }; 372 373 #define ENETC_CBD(R, i) (&(((struct enetc_cbd *)((R).bd_base))[i])) 374 375 #define ENETC_CBDR_TIMEOUT 1000 /* usecs */ 376 377 /* PTP driver exports */ 378 extern int enetc_phc_index; 379 380 /* SI common */ 381 int enetc_pci_probe(struct pci_dev *pdev, const char *name, int sizeof_priv); 382 void enetc_pci_remove(struct pci_dev *pdev); 383 int enetc_alloc_msix(struct enetc_ndev_priv *priv); 384 void enetc_free_msix(struct enetc_ndev_priv *priv); 385 void enetc_get_si_caps(struct enetc_si *si); 386 void enetc_init_si_rings_params(struct enetc_ndev_priv *priv); 387 int enetc_alloc_si_resources(struct enetc_ndev_priv *priv); 388 void enetc_free_si_resources(struct enetc_ndev_priv *priv); 389 int enetc_configure_si(struct enetc_ndev_priv *priv); 390 391 int enetc_open(struct net_device *ndev); 392 int enetc_close(struct net_device *ndev); 393 void enetc_start(struct net_device *ndev); 394 void enetc_stop(struct net_device *ndev); 395 netdev_tx_t enetc_xmit(struct sk_buff *skb, struct net_device *ndev); 396 struct net_device_stats *enetc_get_stats(struct net_device *ndev); 397 void enetc_set_features(struct net_device *ndev, netdev_features_t features); 398 int enetc_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd); 399 int enetc_setup_tc_mqprio(struct net_device *ndev, void *type_data); 400 int enetc_setup_bpf(struct net_device *dev, struct netdev_bpf *xdp); 401 int enetc_xdp_xmit(struct net_device *ndev, int num_frames, 402 struct xdp_frame **frames, u32 flags); 403 404 /* ethtool */ 405 void enetc_set_ethtool_ops(struct net_device *ndev); 406 407 /* control buffer descriptor ring (CBDR) */ 408 int enetc_setup_cbdr(struct device *dev, struct enetc_hw *hw, int bd_count, 409 struct enetc_cbdr *cbdr); 410 void enetc_teardown_cbdr(struct enetc_cbdr *cbdr); 411 int enetc_set_mac_flt_entry(struct enetc_si *si, int index, 412 char *mac_addr, int si_map); 413 int enetc_clear_mac_flt_entry(struct enetc_si *si, int index); 414 int enetc_set_fs_entry(struct enetc_si *si, struct enetc_cmd_rfse *rfse, 415 int index); 416 void enetc_set_rss_key(struct enetc_hw *hw, const u8 *bytes); 417 int enetc_get_rss_table(struct enetc_si *si, u32 *table, int count); 418 int enetc_set_rss_table(struct enetc_si *si, const u32 *table, int count); 419 int enetc_send_cmd(struct enetc_si *si, struct enetc_cbd *cbd); 420 421 static inline void *enetc_cbd_alloc_data_mem(struct enetc_si *si, 422 struct enetc_cbd *cbd, 423 int size, dma_addr_t *dma, 424 void **data_align) 425 { 426 struct enetc_cbdr *ring = &si->cbd_ring; 427 dma_addr_t dma_align; 428 void *data; 429 430 data = dma_alloc_coherent(ring->dma_dev, 431 size + ENETC_CBD_DATA_MEM_ALIGN, 432 dma, GFP_KERNEL); 433 if (!data) { 434 dev_err(ring->dma_dev, "CBD alloc data memory failed!\n"); 435 return NULL; 436 } 437 438 dma_align = ALIGN(*dma, ENETC_CBD_DATA_MEM_ALIGN); 439 *data_align = PTR_ALIGN(data, ENETC_CBD_DATA_MEM_ALIGN); 440 441 cbd->addr[0] = cpu_to_le32(lower_32_bits(dma_align)); 442 cbd->addr[1] = cpu_to_le32(upper_32_bits(dma_align)); 443 cbd->length = cpu_to_le16(size); 444 445 return data; 446 } 447 448 static inline void enetc_cbd_free_data_mem(struct enetc_si *si, int size, 449 void *data, dma_addr_t *dma) 450 { 451 struct enetc_cbdr *ring = &si->cbd_ring; 452 453 dma_free_coherent(ring->dma_dev, size + ENETC_CBD_DATA_MEM_ALIGN, 454 data, *dma); 455 } 456 457 void enetc_reset_ptcmsdur(struct enetc_hw *hw); 458 void enetc_set_ptcmsdur(struct enetc_hw *hw, u32 *queue_max_sdu); 459 460 #ifdef CONFIG_FSL_ENETC_QOS 461 int enetc_qos_query_caps(struct net_device *ndev, void *type_data); 462 int enetc_setup_tc_taprio(struct net_device *ndev, void *type_data); 463 void enetc_sched_speed_set(struct enetc_ndev_priv *priv, int speed); 464 int enetc_setup_tc_cbs(struct net_device *ndev, void *type_data); 465 int enetc_setup_tc_txtime(struct net_device *ndev, void *type_data); 466 int enetc_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 467 void *cb_priv); 468 int enetc_setup_tc_psfp(struct net_device *ndev, void *type_data); 469 int enetc_psfp_init(struct enetc_ndev_priv *priv); 470 int enetc_psfp_clean(struct enetc_ndev_priv *priv); 471 int enetc_set_psfp(struct net_device *ndev, bool en); 472 473 static inline void enetc_get_max_cap(struct enetc_ndev_priv *priv) 474 { 475 struct enetc_hw *hw = &priv->si->hw; 476 u32 reg; 477 478 reg = enetc_port_rd(hw, ENETC_PSIDCAPR); 479 priv->psfp_cap.max_streamid = reg & ENETC_PSIDCAPR_MSK; 480 /* Port stream filter capability */ 481 reg = enetc_port_rd(hw, ENETC_PSFCAPR); 482 priv->psfp_cap.max_psfp_filter = reg & ENETC_PSFCAPR_MSK; 483 /* Port stream gate capability */ 484 reg = enetc_port_rd(hw, ENETC_PSGCAPR); 485 priv->psfp_cap.max_psfp_gate = (reg & ENETC_PSGCAPR_SGIT_MSK); 486 priv->psfp_cap.max_psfp_gatelist = (reg & ENETC_PSGCAPR_GCL_MSK) >> 16; 487 /* Port flow meter capability */ 488 reg = enetc_port_rd(hw, ENETC_PFMCAPR); 489 priv->psfp_cap.max_psfp_meter = reg & ENETC_PFMCAPR_MSK; 490 } 491 492 static inline int enetc_psfp_enable(struct enetc_ndev_priv *priv) 493 { 494 struct enetc_hw *hw = &priv->si->hw; 495 int err; 496 497 enetc_get_max_cap(priv); 498 499 err = enetc_psfp_init(priv); 500 if (err) 501 return err; 502 503 enetc_wr(hw, ENETC_PPSFPMR, enetc_rd(hw, ENETC_PPSFPMR) | 504 ENETC_PPSFPMR_PSFPEN | ENETC_PPSFPMR_VS | 505 ENETC_PPSFPMR_PVC | ENETC_PPSFPMR_PVZC); 506 507 return 0; 508 } 509 510 static inline int enetc_psfp_disable(struct enetc_ndev_priv *priv) 511 { 512 struct enetc_hw *hw = &priv->si->hw; 513 int err; 514 515 err = enetc_psfp_clean(priv); 516 if (err) 517 return err; 518 519 enetc_wr(hw, ENETC_PPSFPMR, enetc_rd(hw, ENETC_PPSFPMR) & 520 ~ENETC_PPSFPMR_PSFPEN & ~ENETC_PPSFPMR_VS & 521 ~ENETC_PPSFPMR_PVC & ~ENETC_PPSFPMR_PVZC); 522 523 memset(&priv->psfp_cap, 0, sizeof(struct psfp_cap)); 524 525 return 0; 526 } 527 528 #else 529 #define enetc_qos_query_caps(ndev, type_data) -EOPNOTSUPP 530 #define enetc_setup_tc_taprio(ndev, type_data) -EOPNOTSUPP 531 #define enetc_sched_speed_set(priv, speed) (void)0 532 #define enetc_setup_tc_cbs(ndev, type_data) -EOPNOTSUPP 533 #define enetc_setup_tc_txtime(ndev, type_data) -EOPNOTSUPP 534 #define enetc_setup_tc_psfp(ndev, type_data) -EOPNOTSUPP 535 #define enetc_setup_tc_block_cb NULL 536 537 #define enetc_get_max_cap(p) \ 538 memset(&((p)->psfp_cap), 0, sizeof(struct psfp_cap)) 539 540 static inline int enetc_psfp_enable(struct enetc_ndev_priv *priv) 541 { 542 return 0; 543 } 544 545 static inline int enetc_psfp_disable(struct enetc_ndev_priv *priv) 546 { 547 return 0; 548 } 549 550 static inline int enetc_set_psfp(struct net_device *ndev, bool en) 551 { 552 return 0; 553 } 554 #endif 555