1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ 2 /* Copyright 2017-2019 NXP */ 3 4 #include <linux/timer.h> 5 #include <linux/pci.h> 6 #include <linux/netdevice.h> 7 #include <linux/etherdevice.h> 8 #include <linux/dma-mapping.h> 9 #include <linux/skbuff.h> 10 #include <linux/ethtool.h> 11 #include <linux/if_vlan.h> 12 #include <linux/phylink.h> 13 #include <linux/dim.h> 14 15 #include "enetc_hw.h" 16 17 #define ENETC_MAC_MAXFRM_SIZE 9600 18 #define ENETC_MAX_MTU (ENETC_MAC_MAXFRM_SIZE - \ 19 (ETH_FCS_LEN + ETH_HLEN + VLAN_HLEN)) 20 21 struct enetc_tx_swbd { 22 struct sk_buff *skb; 23 dma_addr_t dma; 24 u16 len; 25 u8 is_dma_page:1; 26 u8 check_wb:1; 27 u8 do_tstamp:1; 28 }; 29 30 #define ENETC_RX_MAXFRM_SIZE ENETC_MAC_MAXFRM_SIZE 31 #define ENETC_RXB_TRUESIZE 2048 /* PAGE_SIZE >> 1 */ 32 #define ENETC_RXB_PAD NET_SKB_PAD /* add extra space if needed */ 33 #define ENETC_RXB_DMA_SIZE \ 34 (SKB_WITH_OVERHEAD(ENETC_RXB_TRUESIZE) - ENETC_RXB_PAD) 35 36 struct enetc_rx_swbd { 37 dma_addr_t dma; 38 struct page *page; 39 u16 page_offset; 40 }; 41 42 struct enetc_ring_stats { 43 unsigned int packets; 44 unsigned int bytes; 45 unsigned int rx_alloc_errs; 46 }; 47 48 #define ENETC_RX_RING_DEFAULT_SIZE 512 49 #define ENETC_TX_RING_DEFAULT_SIZE 256 50 #define ENETC_DEFAULT_TX_WORK (ENETC_TX_RING_DEFAULT_SIZE / 2) 51 52 struct enetc_bdr { 53 struct device *dev; /* for DMA mapping */ 54 struct net_device *ndev; 55 void *bd_base; /* points to Rx or Tx BD ring */ 56 union { 57 void __iomem *tpir; 58 void __iomem *rcir; 59 }; 60 u16 index; 61 int bd_count; /* # of BDs */ 62 int next_to_use; 63 int next_to_clean; 64 union { 65 struct enetc_tx_swbd *tx_swbd; 66 struct enetc_rx_swbd *rx_swbd; 67 }; 68 union { 69 void __iomem *tcir; /* Tx */ 70 int next_to_alloc; /* Rx */ 71 }; 72 void __iomem *idr; /* Interrupt Detect Register pointer */ 73 74 struct enetc_ring_stats stats; 75 76 dma_addr_t bd_dma_base; 77 u8 tsd_enable; /* Time specific departure */ 78 bool ext_en; /* enable h/w descriptor extensions */ 79 } ____cacheline_aligned_in_smp; 80 81 static inline void enetc_bdr_idx_inc(struct enetc_bdr *bdr, int *i) 82 { 83 if (unlikely(++*i == bdr->bd_count)) 84 *i = 0; 85 } 86 87 static inline int enetc_bd_unused(struct enetc_bdr *bdr) 88 { 89 if (bdr->next_to_clean > bdr->next_to_use) 90 return bdr->next_to_clean - bdr->next_to_use - 1; 91 92 return bdr->bd_count + bdr->next_to_clean - bdr->next_to_use - 1; 93 } 94 95 /* Control BD ring */ 96 #define ENETC_CBDR_DEFAULT_SIZE 64 97 struct enetc_cbdr { 98 void *bd_base; /* points to Rx or Tx BD ring */ 99 void __iomem *pir; 100 void __iomem *cir; 101 102 int bd_count; /* # of BDs */ 103 int next_to_use; 104 int next_to_clean; 105 106 dma_addr_t bd_dma_base; 107 }; 108 109 #define ENETC_TXBD(BDR, i) (&(((union enetc_tx_bd *)((BDR).bd_base))[i])) 110 111 static inline union enetc_rx_bd *enetc_rxbd(struct enetc_bdr *rx_ring, int i) 112 { 113 int hw_idx = i; 114 115 #ifdef CONFIG_FSL_ENETC_PTP_CLOCK 116 if (rx_ring->ext_en) 117 hw_idx = 2 * i; 118 #endif 119 return &(((union enetc_rx_bd *)rx_ring->bd_base)[hw_idx]); 120 } 121 122 static inline union enetc_rx_bd *enetc_rxbd_next(struct enetc_bdr *rx_ring, 123 union enetc_rx_bd *rxbd, 124 int i) 125 { 126 rxbd++; 127 #ifdef CONFIG_FSL_ENETC_PTP_CLOCK 128 if (rx_ring->ext_en) 129 rxbd++; 130 #endif 131 if (unlikely(++i == rx_ring->bd_count)) 132 rxbd = rx_ring->bd_base; 133 134 return rxbd; 135 } 136 137 static inline union enetc_rx_bd *enetc_rxbd_ext(union enetc_rx_bd *rxbd) 138 { 139 return ++rxbd; 140 } 141 142 struct enetc_msg_swbd { 143 void *vaddr; 144 dma_addr_t dma; 145 int size; 146 }; 147 148 #define ENETC_REV1 0x1 149 enum enetc_errata { 150 ENETC_ERR_VLAN_ISOL = BIT(0), 151 ENETC_ERR_UCMCSWP = BIT(1), 152 }; 153 154 #define ENETC_SI_F_QBV BIT(0) 155 #define ENETC_SI_F_PSFP BIT(1) 156 157 /* PCI IEP device data */ 158 struct enetc_si { 159 struct pci_dev *pdev; 160 struct enetc_hw hw; 161 enum enetc_errata errata; 162 163 struct net_device *ndev; /* back ref. */ 164 165 struct enetc_cbdr cbd_ring; 166 167 int num_rx_rings; /* how many rings are available in the SI */ 168 int num_tx_rings; 169 int num_fs_entries; 170 int num_rss; /* number of RSS buckets */ 171 unsigned short pad; 172 int hw_features; 173 }; 174 175 #define ENETC_SI_ALIGN 32 176 177 static inline void *enetc_si_priv(const struct enetc_si *si) 178 { 179 return (char *)si + ALIGN(sizeof(struct enetc_si), ENETC_SI_ALIGN); 180 } 181 182 static inline bool enetc_si_is_pf(struct enetc_si *si) 183 { 184 return !!(si->hw.port); 185 } 186 187 #define ENETC_MAX_NUM_TXQS 8 188 #define ENETC_INT_NAME_MAX (IFNAMSIZ + 8) 189 190 struct enetc_int_vector { 191 void __iomem *rbier; 192 void __iomem *tbier_base; 193 void __iomem *ricr1; 194 unsigned long tx_rings_map; 195 int count_tx_rings; 196 u32 rx_ictt; 197 u16 comp_cnt; 198 bool rx_dim_en, rx_napi_work; 199 struct napi_struct napi ____cacheline_aligned_in_smp; 200 struct dim rx_dim ____cacheline_aligned_in_smp; 201 char name[ENETC_INT_NAME_MAX]; 202 203 struct enetc_bdr rx_ring; 204 struct enetc_bdr tx_ring[]; 205 } ____cacheline_aligned_in_smp; 206 207 struct enetc_cls_rule { 208 struct ethtool_rx_flow_spec fs; 209 int used; 210 }; 211 212 #define ENETC_MAX_BDR_INT 2 /* fixed to max # of available cpus */ 213 struct psfp_cap { 214 u32 max_streamid; 215 u32 max_psfp_filter; 216 u32 max_psfp_gate; 217 u32 max_psfp_gatelist; 218 u32 max_psfp_meter; 219 }; 220 221 /* TODO: more hardware offloads */ 222 enum enetc_active_offloads { 223 ENETC_F_RX_TSTAMP = BIT(0), 224 ENETC_F_TX_TSTAMP = BIT(1), 225 ENETC_F_QBV = BIT(2), 226 ENETC_F_QCI = BIT(3), 227 }; 228 229 /* interrupt coalescing modes */ 230 enum enetc_ic_mode { 231 /* one interrupt per frame */ 232 ENETC_IC_NONE = 0, 233 /* activated when int coalescing time is set to a non-0 value */ 234 ENETC_IC_RX_MANUAL = BIT(0), 235 ENETC_IC_TX_MANUAL = BIT(1), 236 /* use dynamic interrupt moderation */ 237 ENETC_IC_RX_ADAPTIVE = BIT(2), 238 }; 239 240 #define ENETC_RXIC_PKTTHR min_t(u32, 256, ENETC_RX_RING_DEFAULT_SIZE / 2) 241 #define ENETC_TXIC_PKTTHR min_t(u32, 128, ENETC_TX_RING_DEFAULT_SIZE / 2) 242 #define ENETC_TXIC_TIMETHR enetc_usecs_to_cycles(600) 243 244 struct enetc_ndev_priv { 245 struct net_device *ndev; 246 struct device *dev; /* dma-mapping device */ 247 struct enetc_si *si; 248 249 int bdr_int_num; /* number of Rx/Tx ring interrupts */ 250 struct enetc_int_vector *int_vector[ENETC_MAX_BDR_INT]; 251 u16 num_rx_rings, num_tx_rings; 252 u16 rx_bd_count, tx_bd_count; 253 254 u16 msg_enable; 255 int active_offloads; 256 257 u32 speed; /* store speed for compare update pspeed */ 258 259 struct enetc_bdr *tx_ring[16]; 260 struct enetc_bdr *rx_ring[16]; 261 262 struct enetc_cls_rule *cls_rules; 263 264 struct psfp_cap psfp_cap; 265 266 struct phylink *phylink; 267 int ic_mode; 268 u32 tx_ictt; 269 }; 270 271 /* Messaging */ 272 273 /* VF-PF set primary MAC address message format */ 274 struct enetc_msg_cmd_set_primary_mac { 275 struct enetc_msg_cmd_header header; 276 struct sockaddr mac; 277 }; 278 279 #define ENETC_CBD(R, i) (&(((struct enetc_cbd *)((R).bd_base))[i])) 280 281 #define ENETC_CBDR_TIMEOUT 1000 /* usecs */ 282 283 /* PTP driver exports */ 284 extern int enetc_phc_index; 285 286 /* SI common */ 287 int enetc_pci_probe(struct pci_dev *pdev, const char *name, int sizeof_priv); 288 void enetc_pci_remove(struct pci_dev *pdev); 289 int enetc_alloc_msix(struct enetc_ndev_priv *priv); 290 void enetc_free_msix(struct enetc_ndev_priv *priv); 291 void enetc_get_si_caps(struct enetc_si *si); 292 void enetc_init_si_rings_params(struct enetc_ndev_priv *priv); 293 int enetc_alloc_si_resources(struct enetc_ndev_priv *priv); 294 void enetc_free_si_resources(struct enetc_ndev_priv *priv); 295 int enetc_configure_si(struct enetc_ndev_priv *priv); 296 297 int enetc_open(struct net_device *ndev); 298 int enetc_close(struct net_device *ndev); 299 void enetc_start(struct net_device *ndev); 300 void enetc_stop(struct net_device *ndev); 301 netdev_tx_t enetc_xmit(struct sk_buff *skb, struct net_device *ndev); 302 struct net_device_stats *enetc_get_stats(struct net_device *ndev); 303 int enetc_set_features(struct net_device *ndev, 304 netdev_features_t features); 305 int enetc_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd); 306 int enetc_setup_tc(struct net_device *ndev, enum tc_setup_type type, 307 void *type_data); 308 309 /* ethtool */ 310 void enetc_set_ethtool_ops(struct net_device *ndev); 311 312 /* control buffer descriptor ring (CBDR) */ 313 int enetc_alloc_cbdr(struct device *dev, struct enetc_cbdr *cbdr); 314 void enetc_free_cbdr(struct device *dev, struct enetc_cbdr *cbdr); 315 void enetc_setup_cbdr(struct enetc_hw *hw, struct enetc_cbdr *cbdr); 316 void enetc_clear_cbdr(struct enetc_hw *hw); 317 int enetc_set_mac_flt_entry(struct enetc_si *si, int index, 318 char *mac_addr, int si_map); 319 int enetc_clear_mac_flt_entry(struct enetc_si *si, int index); 320 int enetc_set_fs_entry(struct enetc_si *si, struct enetc_cmd_rfse *rfse, 321 int index); 322 void enetc_set_rss_key(struct enetc_hw *hw, const u8 *bytes); 323 int enetc_get_rss_table(struct enetc_si *si, u32 *table, int count); 324 int enetc_set_rss_table(struct enetc_si *si, const u32 *table, int count); 325 int enetc_send_cmd(struct enetc_si *si, struct enetc_cbd *cbd); 326 327 #ifdef CONFIG_FSL_ENETC_QOS 328 int enetc_setup_tc_taprio(struct net_device *ndev, void *type_data); 329 void enetc_sched_speed_set(struct enetc_ndev_priv *priv, int speed); 330 int enetc_setup_tc_cbs(struct net_device *ndev, void *type_data); 331 int enetc_setup_tc_txtime(struct net_device *ndev, void *type_data); 332 int enetc_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 333 void *cb_priv); 334 int enetc_setup_tc_psfp(struct net_device *ndev, void *type_data); 335 int enetc_psfp_init(struct enetc_ndev_priv *priv); 336 int enetc_psfp_clean(struct enetc_ndev_priv *priv); 337 338 static inline void enetc_get_max_cap(struct enetc_ndev_priv *priv) 339 { 340 u32 reg; 341 342 reg = enetc_port_rd(&priv->si->hw, ENETC_PSIDCAPR); 343 priv->psfp_cap.max_streamid = reg & ENETC_PSIDCAPR_MSK; 344 /* Port stream filter capability */ 345 reg = enetc_port_rd(&priv->si->hw, ENETC_PSFCAPR); 346 priv->psfp_cap.max_psfp_filter = reg & ENETC_PSFCAPR_MSK; 347 /* Port stream gate capability */ 348 reg = enetc_port_rd(&priv->si->hw, ENETC_PSGCAPR); 349 priv->psfp_cap.max_psfp_gate = (reg & ENETC_PSGCAPR_SGIT_MSK); 350 priv->psfp_cap.max_psfp_gatelist = (reg & ENETC_PSGCAPR_GCL_MSK) >> 16; 351 /* Port flow meter capability */ 352 reg = enetc_port_rd(&priv->si->hw, ENETC_PFMCAPR); 353 priv->psfp_cap.max_psfp_meter = reg & ENETC_PFMCAPR_MSK; 354 } 355 356 static inline int enetc_psfp_enable(struct enetc_ndev_priv *priv) 357 { 358 struct enetc_hw *hw = &priv->si->hw; 359 int err; 360 361 enetc_get_max_cap(priv); 362 363 err = enetc_psfp_init(priv); 364 if (err) 365 return err; 366 367 enetc_wr(hw, ENETC_PPSFPMR, enetc_rd(hw, ENETC_PPSFPMR) | 368 ENETC_PPSFPMR_PSFPEN | ENETC_PPSFPMR_VS | 369 ENETC_PPSFPMR_PVC | ENETC_PPSFPMR_PVZC); 370 371 return 0; 372 } 373 374 static inline int enetc_psfp_disable(struct enetc_ndev_priv *priv) 375 { 376 struct enetc_hw *hw = &priv->si->hw; 377 int err; 378 379 err = enetc_psfp_clean(priv); 380 if (err) 381 return err; 382 383 enetc_wr(hw, ENETC_PPSFPMR, enetc_rd(hw, ENETC_PPSFPMR) & 384 ~ENETC_PPSFPMR_PSFPEN & ~ENETC_PPSFPMR_VS & 385 ~ENETC_PPSFPMR_PVC & ~ENETC_PPSFPMR_PVZC); 386 387 memset(&priv->psfp_cap, 0, sizeof(struct psfp_cap)); 388 389 return 0; 390 } 391 392 #else 393 #define enetc_setup_tc_taprio(ndev, type_data) -EOPNOTSUPP 394 #define enetc_sched_speed_set(priv, speed) (void)0 395 #define enetc_setup_tc_cbs(ndev, type_data) -EOPNOTSUPP 396 #define enetc_setup_tc_txtime(ndev, type_data) -EOPNOTSUPP 397 #define enetc_setup_tc_psfp(ndev, type_data) -EOPNOTSUPP 398 #define enetc_setup_tc_block_cb NULL 399 400 #define enetc_get_max_cap(p) \ 401 memset(&((p)->psfp_cap), 0, sizeof(struct psfp_cap)) 402 403 static inline int enetc_psfp_enable(struct enetc_ndev_priv *priv) 404 { 405 return 0; 406 } 407 408 static inline int enetc_psfp_disable(struct enetc_ndev_priv *priv) 409 { 410 return 0; 411 } 412 #endif 413