1d4fd0404SClaudiu Manoil /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
2d4fd0404SClaudiu Manoil /* Copyright 2017-2019 NXP */
3d4fd0404SClaudiu Manoil
4d4fd0404SClaudiu Manoil #include <linux/timer.h>
5d4fd0404SClaudiu Manoil #include <linux/pci.h>
6d4fd0404SClaudiu Manoil #include <linux/netdevice.h>
7d4fd0404SClaudiu Manoil #include <linux/etherdevice.h>
8d4fd0404SClaudiu Manoil #include <linux/dma-mapping.h>
9d4fd0404SClaudiu Manoil #include <linux/skbuff.h>
10d4fd0404SClaudiu Manoil #include <linux/ethtool.h>
11d4fd0404SClaudiu Manoil #include <linux/if_vlan.h>
1271b77a7aSClaudiu Manoil #include <linux/phylink.h>
13ae0e6a5dSClaudiu Manoil #include <linux/dim.h>
14*92272ec4SJakub Kicinski #include <net/xdp.h>
15d4fd0404SClaudiu Manoil
16d4fd0404SClaudiu Manoil #include "enetc_hw.h"
17d4fd0404SClaudiu Manoil
18d4fd0404SClaudiu Manoil #define ENETC_MAC_MAXFRM_SIZE 9600
19d4fd0404SClaudiu Manoil #define ENETC_MAX_MTU (ENETC_MAC_MAXFRM_SIZE - \
20d4fd0404SClaudiu Manoil (ETH_FCS_LEN + ETH_HLEN + VLAN_HLEN))
21d4fd0404SClaudiu Manoil
220cc11cdbSPo Liu #define ENETC_CBD_DATA_MEM_ALIGN 64
230cc11cdbSPo Liu
24d4fd0404SClaudiu Manoil struct enetc_tx_swbd {
259d2b68ccSVladimir Oltean union {
26d4fd0404SClaudiu Manoil struct sk_buff *skb;
279d2b68ccSVladimir Oltean struct xdp_frame *xdp_frame;
289d2b68ccSVladimir Oltean };
29d4fd0404SClaudiu Manoil dma_addr_t dma;
307ed2bc80SVladimir Oltean struct page *page; /* valid only if is_xdp_tx */
317ed2bc80SVladimir Oltean u16 page_offset; /* valid only if is_xdp_tx */
32d4fd0404SClaudiu Manoil u16 len;
337ed2bc80SVladimir Oltean enum dma_data_direction dir;
34d3982312SY.b. Lu u8 is_dma_page:1;
35d3982312SY.b. Lu u8 check_wb:1;
367294380cSYangbo Lu u8 do_twostep_tstamp:1;
37d504498dSVladimir Oltean u8 is_eof:1;
387ed2bc80SVladimir Oltean u8 is_xdp_tx:1;
399d2b68ccSVladimir Oltean u8 is_xdp_redirect:1;
40285e8dedSPo Liu u8 qbv_en:1;
41d4fd0404SClaudiu Manoil };
42d4fd0404SClaudiu Manoil
43d4fd0404SClaudiu Manoil #define ENETC_RX_MAXFRM_SIZE ENETC_MAC_MAXFRM_SIZE
44d4fd0404SClaudiu Manoil #define ENETC_RXB_TRUESIZE 2048 /* PAGE_SIZE >> 1 */
45d4fd0404SClaudiu Manoil #define ENETC_RXB_PAD NET_SKB_PAD /* add extra space if needed */
46d4fd0404SClaudiu Manoil #define ENETC_RXB_DMA_SIZE \
47d4fd0404SClaudiu Manoil (SKB_WITH_OVERHEAD(ENETC_RXB_TRUESIZE) - ENETC_RXB_PAD)
48d1b15102SVladimir Oltean #define ENETC_RXB_DMA_SIZE_XDP \
49d1b15102SVladimir Oltean (SKB_WITH_OVERHEAD(ENETC_RXB_TRUESIZE) - XDP_PACKET_HEADROOM)
50d4fd0404SClaudiu Manoil
51d4fd0404SClaudiu Manoil struct enetc_rx_swbd {
52d4fd0404SClaudiu Manoil dma_addr_t dma;
53d4fd0404SClaudiu Manoil struct page *page;
54d4fd0404SClaudiu Manoil u16 page_offset;
557ed2bc80SVladimir Oltean enum dma_data_direction dir;
567ed2bc80SVladimir Oltean u16 len;
57d4fd0404SClaudiu Manoil };
58d4fd0404SClaudiu Manoil
597ed2bc80SVladimir Oltean /* ENETC overhead: optional extension BD + 1 BD gap */
607ed2bc80SVladimir Oltean #define ENETC_TXBDS_NEEDED(val) ((val) + 2)
617ed2bc80SVladimir Oltean /* max # of chained Tx BDs is 15, including head and extension BD */
627ed2bc80SVladimir Oltean #define ENETC_MAX_SKB_FRAGS 13
637ed2bc80SVladimir Oltean #define ENETC_TXBDS_MAX_NEEDED ENETC_TXBDS_NEEDED(ENETC_MAX_SKB_FRAGS + 1)
647ed2bc80SVladimir Oltean
65d4fd0404SClaudiu Manoil struct enetc_ring_stats {
66d4fd0404SClaudiu Manoil unsigned int packets;
67d4fd0404SClaudiu Manoil unsigned int bytes;
68d4fd0404SClaudiu Manoil unsigned int rx_alloc_errs;
69d1b15102SVladimir Oltean unsigned int xdp_drops;
707ed2bc80SVladimir Oltean unsigned int xdp_tx;
717ed2bc80SVladimir Oltean unsigned int xdp_tx_drops;
729d2b68ccSVladimir Oltean unsigned int xdp_redirect;
739d2b68ccSVladimir Oltean unsigned int xdp_redirect_failures;
747ed2bc80SVladimir Oltean unsigned int recycles;
757ed2bc80SVladimir Oltean unsigned int recycle_failures;
76285e8dedSPo Liu unsigned int win_drop;
77d1b15102SVladimir Oltean };
78d1b15102SVladimir Oltean
79d1b15102SVladimir Oltean struct enetc_xdp_data {
80d1b15102SVladimir Oltean struct xdp_rxq_info rxq;
81d1b15102SVladimir Oltean struct bpf_prog *prog;
827ed2bc80SVladimir Oltean int xdp_tx_in_flight;
83d4fd0404SClaudiu Manoil };
84d4fd0404SClaudiu Manoil
85d6a2829eSVladimir Oltean #define ENETC_RX_RING_DEFAULT_SIZE 2048
86ee3e875fSVladimir Oltean #define ENETC_TX_RING_DEFAULT_SIZE 2048
8702293dd4SClaudiu Manoil #define ENETC_DEFAULT_TX_WORK (ENETC_TX_RING_DEFAULT_SIZE / 2)
88d4fd0404SClaudiu Manoil
89f3ce29e1SVladimir Oltean struct enetc_bdr_resource {
90f3ce29e1SVladimir Oltean /* Input arguments saved for teardown */
91f3ce29e1SVladimir Oltean struct device *dev; /* for DMA mapping */
92f3ce29e1SVladimir Oltean size_t bd_count;
93f3ce29e1SVladimir Oltean size_t bd_size;
94f3ce29e1SVladimir Oltean
95f3ce29e1SVladimir Oltean /* Resource proper */
96f3ce29e1SVladimir Oltean void *bd_base; /* points to Rx or Tx BD ring */
97f3ce29e1SVladimir Oltean dma_addr_t bd_dma_base;
98f3ce29e1SVladimir Oltean union {
99f3ce29e1SVladimir Oltean struct enetc_tx_swbd *tx_swbd;
100f3ce29e1SVladimir Oltean struct enetc_rx_swbd *rx_swbd;
101f3ce29e1SVladimir Oltean };
102f3ce29e1SVladimir Oltean char *tso_headers;
103f3ce29e1SVladimir Oltean dma_addr_t tso_headers_dma;
104f3ce29e1SVladimir Oltean };
105f3ce29e1SVladimir Oltean
106d4fd0404SClaudiu Manoil struct enetc_bdr {
107d4fd0404SClaudiu Manoil struct device *dev; /* for DMA mapping */
108d4fd0404SClaudiu Manoil struct net_device *ndev;
109d4fd0404SClaudiu Manoil void *bd_base; /* points to Rx or Tx BD ring */
110d4fd0404SClaudiu Manoil union {
111d4fd0404SClaudiu Manoil void __iomem *tpir;
112d4fd0404SClaudiu Manoil void __iomem *rcir;
113d4fd0404SClaudiu Manoil };
114d4fd0404SClaudiu Manoil u16 index;
115290b5fe0SVladimir Oltean u16 prio;
116d4fd0404SClaudiu Manoil int bd_count; /* # of BDs */
117d4fd0404SClaudiu Manoil int next_to_use;
118d4fd0404SClaudiu Manoil int next_to_clean;
119d4fd0404SClaudiu Manoil union {
120d4fd0404SClaudiu Manoil struct enetc_tx_swbd *tx_swbd;
121d4fd0404SClaudiu Manoil struct enetc_rx_swbd *rx_swbd;
122d4fd0404SClaudiu Manoil };
123d4fd0404SClaudiu Manoil union {
124d4fd0404SClaudiu Manoil void __iomem *tcir; /* Tx */
125d4fd0404SClaudiu Manoil int next_to_alloc; /* Rx */
126d4fd0404SClaudiu Manoil };
127d4fd0404SClaudiu Manoil void __iomem *idr; /* Interrupt Detect Register pointer */
128d4fd0404SClaudiu Manoil
129d1b15102SVladimir Oltean int buffer_offset;
130d1b15102SVladimir Oltean struct enetc_xdp_data xdp;
131d1b15102SVladimir Oltean
132d4fd0404SClaudiu Manoil struct enetc_ring_stats stats;
133d4fd0404SClaudiu Manoil
134d4fd0404SClaudiu Manoil dma_addr_t bd_dma_base;
1350d08c9ecSPo Liu u8 tsd_enable; /* Time specific departure */
136434cebabSClaudiu Manoil bool ext_en; /* enable h/w descriptor extensions */
137fb8629e2SIoana Ciornei
138fb8629e2SIoana Ciornei /* DMA buffer for TSO headers */
139fb8629e2SIoana Ciornei char *tso_headers;
140fb8629e2SIoana Ciornei dma_addr_t tso_headers_dma;
141d4fd0404SClaudiu Manoil } ____cacheline_aligned_in_smp;
142d4fd0404SClaudiu Manoil
enetc_bdr_idx_inc(struct enetc_bdr * bdr,int * i)143d4fd0404SClaudiu Manoil static inline void enetc_bdr_idx_inc(struct enetc_bdr *bdr, int *i)
144d4fd0404SClaudiu Manoil {
145d4fd0404SClaudiu Manoil if (unlikely(++*i == bdr->bd_count))
146d4fd0404SClaudiu Manoil *i = 0;
147d4fd0404SClaudiu Manoil }
148d4fd0404SClaudiu Manoil
enetc_bd_unused(struct enetc_bdr * bdr)149d4fd0404SClaudiu Manoil static inline int enetc_bd_unused(struct enetc_bdr *bdr)
150d4fd0404SClaudiu Manoil {
151d4fd0404SClaudiu Manoil if (bdr->next_to_clean > bdr->next_to_use)
152d4fd0404SClaudiu Manoil return bdr->next_to_clean - bdr->next_to_use - 1;
153d4fd0404SClaudiu Manoil
154d4fd0404SClaudiu Manoil return bdr->bd_count + bdr->next_to_clean - bdr->next_to_use - 1;
155d4fd0404SClaudiu Manoil }
156d4fd0404SClaudiu Manoil
enetc_swbd_unused(struct enetc_bdr * bdr)1577ed2bc80SVladimir Oltean static inline int enetc_swbd_unused(struct enetc_bdr *bdr)
1587ed2bc80SVladimir Oltean {
1597ed2bc80SVladimir Oltean if (bdr->next_to_clean > bdr->next_to_alloc)
1607ed2bc80SVladimir Oltean return bdr->next_to_clean - bdr->next_to_alloc - 1;
1617ed2bc80SVladimir Oltean
1627ed2bc80SVladimir Oltean return bdr->bd_count + bdr->next_to_clean - bdr->next_to_alloc - 1;
1637ed2bc80SVladimir Oltean }
1647ed2bc80SVladimir Oltean
165d4fd0404SClaudiu Manoil /* Control BD ring */
166d4fd0404SClaudiu Manoil #define ENETC_CBDR_DEFAULT_SIZE 64
167d4fd0404SClaudiu Manoil struct enetc_cbdr {
168d4fd0404SClaudiu Manoil void *bd_base; /* points to Rx or Tx BD ring */
169d4fd0404SClaudiu Manoil void __iomem *pir;
170d4fd0404SClaudiu Manoil void __iomem *cir;
17127f9025dSVladimir Oltean void __iomem *mr; /* mode register */
172d4fd0404SClaudiu Manoil
173d4fd0404SClaudiu Manoil int bd_count; /* # of BDs */
174d4fd0404SClaudiu Manoil int next_to_use;
175d4fd0404SClaudiu Manoil int next_to_clean;
176d4fd0404SClaudiu Manoil
177d4fd0404SClaudiu Manoil dma_addr_t bd_dma_base;
17801121ab7SVladimir Oltean struct device *dma_dev;
179d4fd0404SClaudiu Manoil };
180d4fd0404SClaudiu Manoil
181d4fd0404SClaudiu Manoil #define ENETC_TXBD(BDR, i) (&(((union enetc_tx_bd *)((BDR).bd_base))[i]))
182714239acSClaudiu Manoil
enetc_rxbd(struct enetc_bdr * rx_ring,int i)183714239acSClaudiu Manoil static inline union enetc_rx_bd *enetc_rxbd(struct enetc_bdr *rx_ring, int i)
184714239acSClaudiu Manoil {
185434cebabSClaudiu Manoil int hw_idx = i;
186434cebabSClaudiu Manoil
187434cebabSClaudiu Manoil #ifdef CONFIG_FSL_ENETC_PTP_CLOCK
188434cebabSClaudiu Manoil if (rx_ring->ext_en)
189434cebabSClaudiu Manoil hw_idx = 2 * i;
190434cebabSClaudiu Manoil #endif
191434cebabSClaudiu Manoil return &(((union enetc_rx_bd *)rx_ring->bd_base)[hw_idx]);
192714239acSClaudiu Manoil }
193714239acSClaudiu Manoil
enetc_rxbd_next(struct enetc_bdr * rx_ring,union enetc_rx_bd ** old_rxbd,int * old_index)194c027aa92SVladimir Oltean static inline void enetc_rxbd_next(struct enetc_bdr *rx_ring,
195c027aa92SVladimir Oltean union enetc_rx_bd **old_rxbd, int *old_index)
196714239acSClaudiu Manoil {
197c027aa92SVladimir Oltean union enetc_rx_bd *new_rxbd = *old_rxbd;
198c027aa92SVladimir Oltean int new_index = *old_index;
199c027aa92SVladimir Oltean
200c027aa92SVladimir Oltean new_rxbd++;
201c027aa92SVladimir Oltean
202434cebabSClaudiu Manoil #ifdef CONFIG_FSL_ENETC_PTP_CLOCK
203434cebabSClaudiu Manoil if (rx_ring->ext_en)
204c027aa92SVladimir Oltean new_rxbd++;
205434cebabSClaudiu Manoil #endif
206714239acSClaudiu Manoil
207c027aa92SVladimir Oltean if (unlikely(++new_index == rx_ring->bd_count)) {
208c027aa92SVladimir Oltean new_rxbd = rx_ring->bd_base;
209c027aa92SVladimir Oltean new_index = 0;
210c027aa92SVladimir Oltean }
211c027aa92SVladimir Oltean
212c027aa92SVladimir Oltean *old_rxbd = new_rxbd;
213c027aa92SVladimir Oltean *old_index = new_index;
214714239acSClaudiu Manoil }
215d4fd0404SClaudiu Manoil
enetc_rxbd_ext(union enetc_rx_bd * rxbd)216434cebabSClaudiu Manoil static inline union enetc_rx_bd *enetc_rxbd_ext(union enetc_rx_bd *rxbd)
217434cebabSClaudiu Manoil {
218434cebabSClaudiu Manoil return ++rxbd;
219434cebabSClaudiu Manoil }
220434cebabSClaudiu Manoil
221beb74ac8SClaudiu Manoil struct enetc_msg_swbd {
222beb74ac8SClaudiu Manoil void *vaddr;
223beb74ac8SClaudiu Manoil dma_addr_t dma;
224beb74ac8SClaudiu Manoil int size;
225beb74ac8SClaudiu Manoil };
226beb74ac8SClaudiu Manoil
227d4fd0404SClaudiu Manoil #define ENETC_REV1 0x1
228d4fd0404SClaudiu Manoil enum enetc_errata {
22982728b91SClaudiu Manoil ENETC_ERR_VLAN_ISOL = BIT(0),
23082728b91SClaudiu Manoil ENETC_ERR_UCMCSWP = BIT(1),
231d4fd0404SClaudiu Manoil };
232d4fd0404SClaudiu Manoil
23394557a9aSVladimir Oltean #define ENETC_SI_F_PSFP BIT(0)
23494557a9aSVladimir Oltean #define ENETC_SI_F_QBV BIT(1)
23594557a9aSVladimir Oltean #define ENETC_SI_F_QBU BIT(2)
2362e47cb41SPo Liu
237d4fd0404SClaudiu Manoil /* PCI IEP device data */
238d4fd0404SClaudiu Manoil struct enetc_si {
239d4fd0404SClaudiu Manoil struct pci_dev *pdev;
240d4fd0404SClaudiu Manoil struct enetc_hw hw;
241d4fd0404SClaudiu Manoil enum enetc_errata errata;
242d4fd0404SClaudiu Manoil
243d4fd0404SClaudiu Manoil struct net_device *ndev; /* back ref. */
244d4fd0404SClaudiu Manoil
245d4fd0404SClaudiu Manoil struct enetc_cbdr cbd_ring;
246d4fd0404SClaudiu Manoil
247d4fd0404SClaudiu Manoil int num_rx_rings; /* how many rings are available in the SI */
248d4fd0404SClaudiu Manoil int num_tx_rings;
249d382563fSClaudiu Manoil int num_fs_entries;
250d382563fSClaudiu Manoil int num_rss; /* number of RSS buckets */
251d4fd0404SClaudiu Manoil unsigned short pad;
2522e47cb41SPo Liu int hw_features;
253d4fd0404SClaudiu Manoil };
254d4fd0404SClaudiu Manoil
255d4fd0404SClaudiu Manoil #define ENETC_SI_ALIGN 32
256d4fd0404SClaudiu Manoil
enetc_si_priv(const struct enetc_si * si)257d4fd0404SClaudiu Manoil static inline void *enetc_si_priv(const struct enetc_si *si)
258d4fd0404SClaudiu Manoil {
259d4fd0404SClaudiu Manoil return (char *)si + ALIGN(sizeof(struct enetc_si), ENETC_SI_ALIGN);
260d4fd0404SClaudiu Manoil }
261d4fd0404SClaudiu Manoil
enetc_si_is_pf(struct enetc_si * si)262d4fd0404SClaudiu Manoil static inline bool enetc_si_is_pf(struct enetc_si *si)
263d4fd0404SClaudiu Manoil {
264d4fd0404SClaudiu Manoil return !!(si->hw.port);
265d4fd0404SClaudiu Manoil }
266d4fd0404SClaudiu Manoil
enetc_pf_to_port(struct pci_dev * pf_pdev)26787614b93SVladimir Oltean static inline int enetc_pf_to_port(struct pci_dev *pf_pdev)
26887614b93SVladimir Oltean {
26987614b93SVladimir Oltean switch (pf_pdev->devfn) {
27087614b93SVladimir Oltean case 0:
27187614b93SVladimir Oltean return 0;
27287614b93SVladimir Oltean case 1:
27387614b93SVladimir Oltean return 1;
27487614b93SVladimir Oltean case 2:
27587614b93SVladimir Oltean return 2;
27687614b93SVladimir Oltean case 6:
27787614b93SVladimir Oltean return 3;
27887614b93SVladimir Oltean default:
27987614b93SVladimir Oltean return -1;
28087614b93SVladimir Oltean }
28187614b93SVladimir Oltean }
28287614b93SVladimir Oltean
283d4fd0404SClaudiu Manoil #define ENETC_MAX_NUM_TXQS 8
284d4fd0404SClaudiu Manoil #define ENETC_INT_NAME_MAX (IFNAMSIZ + 8)
285d4fd0404SClaudiu Manoil
286d4fd0404SClaudiu Manoil struct enetc_int_vector {
287d4fd0404SClaudiu Manoil void __iomem *rbier;
288d4fd0404SClaudiu Manoil void __iomem *tbier_base;
28991571081SClaudiu Manoil void __iomem *ricr1;
290d4fd0404SClaudiu Manoil unsigned long tx_rings_map;
291d4fd0404SClaudiu Manoil int count_tx_rings;
29291571081SClaudiu Manoil u32 rx_ictt;
293ae0e6a5dSClaudiu Manoil u16 comp_cnt;
294ae0e6a5dSClaudiu Manoil bool rx_dim_en, rx_napi_work;
295ae0e6a5dSClaudiu Manoil struct napi_struct napi ____cacheline_aligned_in_smp;
296ae0e6a5dSClaudiu Manoil struct dim rx_dim ____cacheline_aligned_in_smp;
297d4fd0404SClaudiu Manoil char name[ENETC_INT_NAME_MAX];
298d4fd0404SClaudiu Manoil
299058d9cfaSClaudiu Manoil struct enetc_bdr rx_ring;
300cc5b48b5SGustavo A. R. Silva struct enetc_bdr tx_ring[];
301ae0e6a5dSClaudiu Manoil } ____cacheline_aligned_in_smp;
302d4fd0404SClaudiu Manoil
303d382563fSClaudiu Manoil struct enetc_cls_rule {
304d382563fSClaudiu Manoil struct ethtool_rx_flow_spec fs;
305d382563fSClaudiu Manoil int used;
306d382563fSClaudiu Manoil };
307d382563fSClaudiu Manoil
308d4fd0404SClaudiu Manoil #define ENETC_MAX_BDR_INT 2 /* fixed to max # of available cpus */
30979e49982SPo Liu struct psfp_cap {
31079e49982SPo Liu u32 max_streamid;
31179e49982SPo Liu u32 max_psfp_filter;
31279e49982SPo Liu u32 max_psfp_gate;
31379e49982SPo Liu u32 max_psfp_gatelist;
31479e49982SPo Liu u32 max_psfp_meter;
31579e49982SPo Liu };
316d4fd0404SClaudiu Manoil
317f768e751SYangbo Lu #define ENETC_F_TX_TSTAMP_MASK 0xff
318d3982312SY.b. Lu enum enetc_active_offloads {
319f768e751SYangbo Lu /* 8 bits reserved for TX timestamp types (hwtstamp_tx_types) */
320f768e751SYangbo Lu ENETC_F_TX_TSTAMP = BIT(0),
3217294380cSYangbo Lu ENETC_F_TX_ONESTEP_SYNC_TSTAMP = BIT(1),
322f768e751SYangbo Lu
323f768e751SYangbo Lu ENETC_F_RX_TSTAMP = BIT(8),
324f768e751SYangbo Lu ENETC_F_QBV = BIT(9),
325f768e751SYangbo Lu ENETC_F_QCI = BIT(10),
326c7b9e808SVladimir Oltean ENETC_F_QBU = BIT(11),
327d3982312SY.b. Lu };
328d3982312SY.b. Lu
3297294380cSYangbo Lu enum enetc_flags_bit {
3307294380cSYangbo Lu ENETC_TX_ONESTEP_TSTAMP_IN_PROGRESS = 0,
3317294380cSYangbo Lu };
3327294380cSYangbo Lu
33391571081SClaudiu Manoil /* interrupt coalescing modes */
33491571081SClaudiu Manoil enum enetc_ic_mode {
33591571081SClaudiu Manoil /* one interrupt per frame */
33691571081SClaudiu Manoil ENETC_IC_NONE = 0,
33791571081SClaudiu Manoil /* activated when int coalescing time is set to a non-0 value */
33891571081SClaudiu Manoil ENETC_IC_RX_MANUAL = BIT(0),
33991571081SClaudiu Manoil ENETC_IC_TX_MANUAL = BIT(1),
340ae0e6a5dSClaudiu Manoil /* use dynamic interrupt moderation */
341ae0e6a5dSClaudiu Manoil ENETC_IC_RX_ADAPTIVE = BIT(2),
34291571081SClaudiu Manoil };
34391571081SClaudiu Manoil
34491571081SClaudiu Manoil #define ENETC_RXIC_PKTTHR min_t(u32, 256, ENETC_RX_RING_DEFAULT_SIZE / 2)
34591571081SClaudiu Manoil #define ENETC_TXIC_PKTTHR min_t(u32, 128, ENETC_TX_RING_DEFAULT_SIZE / 2)
346ae0e6a5dSClaudiu Manoil #define ENETC_TXIC_TIMETHR enetc_usecs_to_cycles(600)
34791571081SClaudiu Manoil
348d4fd0404SClaudiu Manoil struct enetc_ndev_priv {
349d4fd0404SClaudiu Manoil struct net_device *ndev;
350d4fd0404SClaudiu Manoil struct device *dev; /* dma-mapping device */
351d4fd0404SClaudiu Manoil struct enetc_si *si;
352d4fd0404SClaudiu Manoil
353d4fd0404SClaudiu Manoil int bdr_int_num; /* number of Rx/Tx ring interrupts */
354d4fd0404SClaudiu Manoil struct enetc_int_vector *int_vector[ENETC_MAX_BDR_INT];
355d4fd0404SClaudiu Manoil u16 num_rx_rings, num_tx_rings;
356d4fd0404SClaudiu Manoil u16 rx_bd_count, tx_bd_count;
357d4fd0404SClaudiu Manoil
358d4fd0404SClaudiu Manoil u16 msg_enable;
35982714539SVladimir Oltean
36082714539SVladimir Oltean u8 preemptible_tcs;
36182714539SVladimir Oltean
3627f071a45SVladimir Oltean enum enetc_active_offloads active_offloads;
363d4fd0404SClaudiu Manoil
3642e47cb41SPo Liu u32 speed; /* store speed for compare update pspeed */
3652e47cb41SPo Liu
3667eab503bSVladimir Oltean struct enetc_bdr **xdp_tx_ring;
367d4fd0404SClaudiu Manoil struct enetc_bdr *tx_ring[16];
368d4fd0404SClaudiu Manoil struct enetc_bdr *rx_ring[16];
369f3ce29e1SVladimir Oltean const struct enetc_bdr_resource *tx_res;
370f3ce29e1SVladimir Oltean const struct enetc_bdr_resource *rx_res;
371d4fd0404SClaudiu Manoil
372d382563fSClaudiu Manoil struct enetc_cls_rule *cls_rules;
373d382563fSClaudiu Manoil
37479e49982SPo Liu struct psfp_cap psfp_cap;
37579e49982SPo Liu
376800db2d1SVladimir Oltean /* Minimum number of TX queues required by the network stack */
377800db2d1SVladimir Oltean unsigned int min_num_stack_tx_queues;
378800db2d1SVladimir Oltean
37971b77a7aSClaudiu Manoil struct phylink *phylink;
38091571081SClaudiu Manoil int ic_mode;
38191571081SClaudiu Manoil u32 tx_ictt;
382d1b15102SVladimir Oltean
383d1b15102SVladimir Oltean struct bpf_prog *xdp_prog;
3847294380cSYangbo Lu
3857294380cSYangbo Lu unsigned long flags;
3867294380cSYangbo Lu
3877294380cSYangbo Lu struct work_struct tx_onestep_tstamp;
3887294380cSYangbo Lu struct sk_buff_head tx_skbs;
389c7b9e808SVladimir Oltean
390c7b9e808SVladimir Oltean /* Serialize access to MAC Merge state between ethtool requests
391c7b9e808SVladimir Oltean * and link state updates
392c7b9e808SVladimir Oltean */
393c7b9e808SVladimir Oltean struct mutex mm_lock;
394d4fd0404SClaudiu Manoil };
395d4fd0404SClaudiu Manoil
396beb74ac8SClaudiu Manoil /* Messaging */
397beb74ac8SClaudiu Manoil
398beb74ac8SClaudiu Manoil /* VF-PF set primary MAC address message format */
399beb74ac8SClaudiu Manoil struct enetc_msg_cmd_set_primary_mac {
400beb74ac8SClaudiu Manoil struct enetc_msg_cmd_header header;
401beb74ac8SClaudiu Manoil struct sockaddr mac;
402beb74ac8SClaudiu Manoil };
403beb74ac8SClaudiu Manoil
404d4fd0404SClaudiu Manoil #define ENETC_CBD(R, i) (&(((struct enetc_cbd *)((R).bd_base))[i]))
405d4fd0404SClaudiu Manoil
406d4fd0404SClaudiu Manoil #define ENETC_CBDR_TIMEOUT 1000 /* usecs */
407d4fd0404SClaudiu Manoil
40841514737SY.b. Lu /* PTP driver exports */
40941514737SY.b. Lu extern int enetc_phc_index;
41041514737SY.b. Lu
411d4fd0404SClaudiu Manoil /* SI common */
41212717decSVladimir Oltean u32 enetc_port_mac_rd(struct enetc_si *si, u32 reg);
41312717decSVladimir Oltean void enetc_port_mac_wr(struct enetc_si *si, u32 reg, u32 val);
414d4fd0404SClaudiu Manoil int enetc_pci_probe(struct pci_dev *pdev, const char *name, int sizeof_priv);
415d4fd0404SClaudiu Manoil void enetc_pci_remove(struct pci_dev *pdev);
416d4fd0404SClaudiu Manoil int enetc_alloc_msix(struct enetc_ndev_priv *priv);
417d4fd0404SClaudiu Manoil void enetc_free_msix(struct enetc_ndev_priv *priv);
418d4fd0404SClaudiu Manoil void enetc_get_si_caps(struct enetc_si *si);
419d4fd0404SClaudiu Manoil void enetc_init_si_rings_params(struct enetc_ndev_priv *priv);
420d4fd0404SClaudiu Manoil int enetc_alloc_si_resources(struct enetc_ndev_priv *priv);
421d4fd0404SClaudiu Manoil void enetc_free_si_resources(struct enetc_ndev_priv *priv);
422c646d10dSVladimir Oltean int enetc_configure_si(struct enetc_ndev_priv *priv);
423d4fd0404SClaudiu Manoil
424d4fd0404SClaudiu Manoil int enetc_open(struct net_device *ndev);
425d4fd0404SClaudiu Manoil int enetc_close(struct net_device *ndev);
42691571081SClaudiu Manoil void enetc_start(struct net_device *ndev);
42791571081SClaudiu Manoil void enetc_stop(struct net_device *ndev);
428d4fd0404SClaudiu Manoil netdev_tx_t enetc_xmit(struct sk_buff *skb, struct net_device *ndev);
429d4fd0404SClaudiu Manoil struct net_device_stats *enetc_get_stats(struct net_device *ndev);
430fed38e64SVladimir Oltean void enetc_set_features(struct net_device *ndev, netdev_features_t features);
431d3982312SY.b. Lu int enetc_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd);
4325641c751SVladimir Oltean int enetc_setup_tc_mqprio(struct net_device *ndev, void *type_data);
4335353599aSVladimir Oltean void enetc_reset_tc_mqprio(struct net_device *ndev);
434766338c7SVladimir Oltean int enetc_setup_bpf(struct net_device *ndev, struct netdev_bpf *bpf);
4359d2b68ccSVladimir Oltean int enetc_xdp_xmit(struct net_device *ndev, int num_frames,
4369d2b68ccSVladimir Oltean struct xdp_frame **frames, u32 flags);
437cbe9e835SCamelia Groza
438d4fd0404SClaudiu Manoil /* ethtool */
439d4fd0404SClaudiu Manoil void enetc_set_ethtool_ops(struct net_device *ndev);
440c7b9e808SVladimir Oltean void enetc_mm_link_state_update(struct enetc_ndev_priv *priv, bool link);
44182714539SVladimir Oltean void enetc_mm_commit_preemptible_tcs(struct enetc_ndev_priv *priv);
442d4fd0404SClaudiu Manoil
443d4fd0404SClaudiu Manoil /* control buffer descriptor ring (CBDR) */
4445b4daa7fSVladimir Oltean int enetc_setup_cbdr(struct device *dev, struct enetc_hw *hw, int bd_count,
44524be14e3SVladimir Oltean struct enetc_cbdr *cbdr);
4460bfde022SVladimir Oltean void enetc_teardown_cbdr(struct enetc_cbdr *cbdr);
447d4fd0404SClaudiu Manoil int enetc_set_mac_flt_entry(struct enetc_si *si, int index,
448d4fd0404SClaudiu Manoil char *mac_addr, int si_map);
449d4fd0404SClaudiu Manoil int enetc_clear_mac_flt_entry(struct enetc_si *si, int index);
450d382563fSClaudiu Manoil int enetc_set_fs_entry(struct enetc_si *si, struct enetc_cmd_rfse *rfse,
451d382563fSClaudiu Manoil int index);
452d382563fSClaudiu Manoil void enetc_set_rss_key(struct enetc_hw *hw, const u8 *bytes);
453d382563fSClaudiu Manoil int enetc_get_rss_table(struct enetc_si *si, u32 *table, int count);
454d382563fSClaudiu Manoil int enetc_set_rss_table(struct enetc_si *si, const u32 *table, int count);
45534c6adf1SPo Liu int enetc_send_cmd(struct enetc_si *si, struct enetc_cbd *cbd);
45634c6adf1SPo Liu
enetc_cbd_alloc_data_mem(struct enetc_si * si,struct enetc_cbd * cbd,int size,dma_addr_t * dma,void ** data_align)4570cc11cdbSPo Liu static inline void *enetc_cbd_alloc_data_mem(struct enetc_si *si,
4580cc11cdbSPo Liu struct enetc_cbd *cbd,
4590cc11cdbSPo Liu int size, dma_addr_t *dma,
4600cc11cdbSPo Liu void **data_align)
4610cc11cdbSPo Liu {
4620cc11cdbSPo Liu struct enetc_cbdr *ring = &si->cbd_ring;
4630cc11cdbSPo Liu dma_addr_t dma_align;
4640cc11cdbSPo Liu void *data;
4650cc11cdbSPo Liu
4660cc11cdbSPo Liu data = dma_alloc_coherent(ring->dma_dev,
4670cc11cdbSPo Liu size + ENETC_CBD_DATA_MEM_ALIGN,
4680cc11cdbSPo Liu dma, GFP_KERNEL);
4690cc11cdbSPo Liu if (!data) {
4700cc11cdbSPo Liu dev_err(ring->dma_dev, "CBD alloc data memory failed!\n");
4710cc11cdbSPo Liu return NULL;
4720cc11cdbSPo Liu }
4730cc11cdbSPo Liu
4740cc11cdbSPo Liu dma_align = ALIGN(*dma, ENETC_CBD_DATA_MEM_ALIGN);
4750cc11cdbSPo Liu *data_align = PTR_ALIGN(data, ENETC_CBD_DATA_MEM_ALIGN);
4760cc11cdbSPo Liu
4770cc11cdbSPo Liu cbd->addr[0] = cpu_to_le32(lower_32_bits(dma_align));
4780cc11cdbSPo Liu cbd->addr[1] = cpu_to_le32(upper_32_bits(dma_align));
4790cc11cdbSPo Liu cbd->length = cpu_to_le16(size);
4800cc11cdbSPo Liu
4810cc11cdbSPo Liu return data;
4820cc11cdbSPo Liu }
4830cc11cdbSPo Liu
enetc_cbd_free_data_mem(struct enetc_si * si,int size,void * data,dma_addr_t * dma)4840cc11cdbSPo Liu static inline void enetc_cbd_free_data_mem(struct enetc_si *si, int size,
4850cc11cdbSPo Liu void *data, dma_addr_t *dma)
4860cc11cdbSPo Liu {
4870cc11cdbSPo Liu struct enetc_cbdr *ring = &si->cbd_ring;
4880cc11cdbSPo Liu
4890cc11cdbSPo Liu dma_free_coherent(ring->dma_dev, size + ENETC_CBD_DATA_MEM_ALIGN,
4900cc11cdbSPo Liu data, *dma);
4910cc11cdbSPo Liu }
4920cc11cdbSPo Liu
493dfc7175dSVladimir Oltean void enetc_reset_ptcmsdur(struct enetc_hw *hw);
494dfc7175dSVladimir Oltean void enetc_set_ptcmsdur(struct enetc_hw *hw, u32 *queue_max_sdu);
495dfc7175dSVladimir Oltean
49634c6adf1SPo Liu #ifdef CONFIG_FSL_ENETC_QOS
497dfc7175dSVladimir Oltean int enetc_qos_query_caps(struct net_device *ndev, void *type_data);
49834c6adf1SPo Liu int enetc_setup_tc_taprio(struct net_device *ndev, void *type_data);
49971b77a7aSClaudiu Manoil void enetc_sched_speed_set(struct enetc_ndev_priv *priv, int speed);
500c431047cSPo Liu int enetc_setup_tc_cbs(struct net_device *ndev, void *type_data);
5010d08c9ecSPo Liu int enetc_setup_tc_txtime(struct net_device *ndev, void *type_data);
502888ae5a3SPo Liu int enetc_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
503888ae5a3SPo Liu void *cb_priv);
504888ae5a3SPo Liu int enetc_setup_tc_psfp(struct net_device *ndev, void *type_data);
505888ae5a3SPo Liu int enetc_psfp_init(struct enetc_ndev_priv *priv);
506888ae5a3SPo Liu int enetc_psfp_clean(struct enetc_ndev_priv *priv);
507fed38e64SVladimir Oltean int enetc_set_psfp(struct net_device *ndev, bool en);
50879e49982SPo Liu
enetc_get_max_cap(struct enetc_ndev_priv * priv)50979e49982SPo Liu static inline void enetc_get_max_cap(struct enetc_ndev_priv *priv)
51079e49982SPo Liu {
511715bf261SVladimir Oltean struct enetc_hw *hw = &priv->si->hw;
51279e49982SPo Liu u32 reg;
51379e49982SPo Liu
514715bf261SVladimir Oltean reg = enetc_port_rd(hw, ENETC_PSIDCAPR);
51579e49982SPo Liu priv->psfp_cap.max_streamid = reg & ENETC_PSIDCAPR_MSK;
51679e49982SPo Liu /* Port stream filter capability */
517715bf261SVladimir Oltean reg = enetc_port_rd(hw, ENETC_PSFCAPR);
51879e49982SPo Liu priv->psfp_cap.max_psfp_filter = reg & ENETC_PSFCAPR_MSK;
51979e49982SPo Liu /* Port stream gate capability */
520715bf261SVladimir Oltean reg = enetc_port_rd(hw, ENETC_PSGCAPR);
52179e49982SPo Liu priv->psfp_cap.max_psfp_gate = (reg & ENETC_PSGCAPR_SGIT_MSK);
52279e49982SPo Liu priv->psfp_cap.max_psfp_gatelist = (reg & ENETC_PSGCAPR_GCL_MSK) >> 16;
52379e49982SPo Liu /* Port flow meter capability */
524715bf261SVladimir Oltean reg = enetc_port_rd(hw, ENETC_PFMCAPR);
52579e49982SPo Liu priv->psfp_cap.max_psfp_meter = reg & ENETC_PFMCAPR_MSK;
52679e49982SPo Liu }
52779e49982SPo Liu
enetc_psfp_enable(struct enetc_ndev_priv * priv)528888ae5a3SPo Liu static inline int enetc_psfp_enable(struct enetc_ndev_priv *priv)
52979e49982SPo Liu {
530888ae5a3SPo Liu struct enetc_hw *hw = &priv->si->hw;
531888ae5a3SPo Liu int err;
532888ae5a3SPo Liu
533888ae5a3SPo Liu enetc_get_max_cap(priv);
534888ae5a3SPo Liu
535888ae5a3SPo Liu err = enetc_psfp_init(priv);
536888ae5a3SPo Liu if (err)
537888ae5a3SPo Liu return err;
538888ae5a3SPo Liu
53979e49982SPo Liu enetc_wr(hw, ENETC_PPSFPMR, enetc_rd(hw, ENETC_PPSFPMR) |
54079e49982SPo Liu ENETC_PPSFPMR_PSFPEN | ENETC_PPSFPMR_VS |
54179e49982SPo Liu ENETC_PPSFPMR_PVC | ENETC_PPSFPMR_PVZC);
542888ae5a3SPo Liu
543888ae5a3SPo Liu return 0;
54479e49982SPo Liu }
54579e49982SPo Liu
enetc_psfp_disable(struct enetc_ndev_priv * priv)546888ae5a3SPo Liu static inline int enetc_psfp_disable(struct enetc_ndev_priv *priv)
54779e49982SPo Liu {
548888ae5a3SPo Liu struct enetc_hw *hw = &priv->si->hw;
549888ae5a3SPo Liu int err;
550888ae5a3SPo Liu
551888ae5a3SPo Liu err = enetc_psfp_clean(priv);
552888ae5a3SPo Liu if (err)
553888ae5a3SPo Liu return err;
554888ae5a3SPo Liu
55579e49982SPo Liu enetc_wr(hw, ENETC_PPSFPMR, enetc_rd(hw, ENETC_PPSFPMR) &
55679e49982SPo Liu ~ENETC_PPSFPMR_PSFPEN & ~ENETC_PPSFPMR_VS &
55779e49982SPo Liu ~ENETC_PPSFPMR_PVC & ~ENETC_PPSFPMR_PVZC);
558888ae5a3SPo Liu
559888ae5a3SPo Liu memset(&priv->psfp_cap, 0, sizeof(struct psfp_cap));
560888ae5a3SPo Liu
561888ae5a3SPo Liu return 0;
56279e49982SPo Liu }
563888ae5a3SPo Liu
56434c6adf1SPo Liu #else
565dfc7175dSVladimir Oltean #define enetc_qos_query_caps(ndev, type_data) -EOPNOTSUPP
56634c6adf1SPo Liu #define enetc_setup_tc_taprio(ndev, type_data) -EOPNOTSUPP
56771b77a7aSClaudiu Manoil #define enetc_sched_speed_set(priv, speed) (void)0
568c431047cSPo Liu #define enetc_setup_tc_cbs(ndev, type_data) -EOPNOTSUPP
5690d08c9ecSPo Liu #define enetc_setup_tc_txtime(ndev, type_data) -EOPNOTSUPP
570888ae5a3SPo Liu #define enetc_setup_tc_psfp(ndev, type_data) -EOPNOTSUPP
571888ae5a3SPo Liu #define enetc_setup_tc_block_cb NULL
572888ae5a3SPo Liu
57379e49982SPo Liu #define enetc_get_max_cap(p) \
57479e49982SPo Liu memset(&((p)->psfp_cap), 0, sizeof(struct psfp_cap))
57579e49982SPo Liu
enetc_psfp_enable(struct enetc_ndev_priv * priv)576888ae5a3SPo Liu static inline int enetc_psfp_enable(struct enetc_ndev_priv *priv)
577888ae5a3SPo Liu {
578888ae5a3SPo Liu return 0;
579888ae5a3SPo Liu }
580888ae5a3SPo Liu
enetc_psfp_disable(struct enetc_ndev_priv * priv)581888ae5a3SPo Liu static inline int enetc_psfp_disable(struct enetc_ndev_priv *priv)
582888ae5a3SPo Liu {
583888ae5a3SPo Liu return 0;
584888ae5a3SPo Liu }
585fed38e64SVladimir Oltean
enetc_set_psfp(struct net_device * ndev,bool en)586fed38e64SVladimir Oltean static inline int enetc_set_psfp(struct net_device *ndev, bool en)
587fed38e64SVladimir Oltean {
588fed38e64SVladimir Oltean return 0;
589fed38e64SVladimir Oltean }
59034c6adf1SPo Liu #endif
591