1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2 /* Copyright 2017-2019 NXP */ 3 4 #include "enetc.h" 5 #include <linux/tcp.h> 6 #include <linux/udp.h> 7 #include <linux/of_mdio.h> 8 #include <linux/vmalloc.h> 9 10 /* ENETC overhead: optional extension BD + 1 BD gap */ 11 #define ENETC_TXBDS_NEEDED(val) ((val) + 2) 12 /* max # of chained Tx BDs is 15, including head and extension BD */ 13 #define ENETC_MAX_SKB_FRAGS 13 14 #define ENETC_TXBDS_MAX_NEEDED ENETC_TXBDS_NEEDED(ENETC_MAX_SKB_FRAGS + 1) 15 16 static int enetc_map_tx_buffs(struct enetc_bdr *tx_ring, struct sk_buff *skb, 17 int active_offloads); 18 19 netdev_tx_t enetc_xmit(struct sk_buff *skb, struct net_device *ndev) 20 { 21 struct enetc_ndev_priv *priv = netdev_priv(ndev); 22 struct enetc_bdr *tx_ring; 23 int count; 24 25 tx_ring = priv->tx_ring[skb->queue_mapping]; 26 27 if (unlikely(skb_shinfo(skb)->nr_frags > ENETC_MAX_SKB_FRAGS)) 28 if (unlikely(skb_linearize(skb))) 29 goto drop_packet_err; 30 31 count = skb_shinfo(skb)->nr_frags + 1; /* fragments + head */ 32 if (enetc_bd_unused(tx_ring) < ENETC_TXBDS_NEEDED(count)) { 33 netif_stop_subqueue(ndev, tx_ring->index); 34 return NETDEV_TX_BUSY; 35 } 36 37 count = enetc_map_tx_buffs(tx_ring, skb, priv->active_offloads); 38 if (unlikely(!count)) 39 goto drop_packet_err; 40 41 if (enetc_bd_unused(tx_ring) < ENETC_TXBDS_MAX_NEEDED) 42 netif_stop_subqueue(ndev, tx_ring->index); 43 44 return NETDEV_TX_OK; 45 46 drop_packet_err: 47 dev_kfree_skb_any(skb); 48 return NETDEV_TX_OK; 49 } 50 51 static bool enetc_tx_csum(struct sk_buff *skb, union enetc_tx_bd *txbd) 52 { 53 int l3_start, l3_hsize; 54 u16 l3_flags, l4_flags; 55 56 if (skb->ip_summed != CHECKSUM_PARTIAL) 57 return false; 58 59 switch (skb->csum_offset) { 60 case offsetof(struct tcphdr, check): 61 l4_flags = ENETC_TXBD_L4_TCP; 62 break; 63 case offsetof(struct udphdr, check): 64 l4_flags = ENETC_TXBD_L4_UDP; 65 break; 66 default: 67 skb_checksum_help(skb); 68 return false; 69 } 70 71 l3_start = skb_network_offset(skb); 72 l3_hsize = skb_network_header_len(skb); 73 74 l3_flags = 0; 75 if (skb->protocol == htons(ETH_P_IPV6)) 76 l3_flags = ENETC_TXBD_L3_IPV6; 77 78 /* write BD fields */ 79 txbd->l3_csoff = enetc_txbd_l3_csoff(l3_start, l3_hsize, l3_flags); 80 txbd->l4_csoff = l4_flags; 81 82 return true; 83 } 84 85 static void enetc_unmap_tx_buff(struct enetc_bdr *tx_ring, 86 struct enetc_tx_swbd *tx_swbd) 87 { 88 if (tx_swbd->is_dma_page) 89 dma_unmap_page(tx_ring->dev, tx_swbd->dma, 90 tx_swbd->len, DMA_TO_DEVICE); 91 else 92 dma_unmap_single(tx_ring->dev, tx_swbd->dma, 93 tx_swbd->len, DMA_TO_DEVICE); 94 tx_swbd->dma = 0; 95 } 96 97 static void enetc_free_tx_skb(struct enetc_bdr *tx_ring, 98 struct enetc_tx_swbd *tx_swbd) 99 { 100 if (tx_swbd->dma) 101 enetc_unmap_tx_buff(tx_ring, tx_swbd); 102 103 if (tx_swbd->skb) { 104 dev_kfree_skb_any(tx_swbd->skb); 105 tx_swbd->skb = NULL; 106 } 107 } 108 109 static int enetc_map_tx_buffs(struct enetc_bdr *tx_ring, struct sk_buff *skb, 110 int active_offloads) 111 { 112 struct enetc_tx_swbd *tx_swbd; 113 skb_frag_t *frag; 114 int len = skb_headlen(skb); 115 union enetc_tx_bd temp_bd; 116 union enetc_tx_bd *txbd; 117 bool do_vlan, do_tstamp; 118 int i, count = 0; 119 unsigned int f; 120 dma_addr_t dma; 121 u8 flags = 0; 122 123 i = tx_ring->next_to_use; 124 txbd = ENETC_TXBD(*tx_ring, i); 125 prefetchw(txbd); 126 127 dma = dma_map_single(tx_ring->dev, skb->data, len, DMA_TO_DEVICE); 128 if (unlikely(dma_mapping_error(tx_ring->dev, dma))) 129 goto dma_err; 130 131 temp_bd.addr = cpu_to_le64(dma); 132 temp_bd.buf_len = cpu_to_le16(len); 133 temp_bd.lstatus = 0; 134 135 tx_swbd = &tx_ring->tx_swbd[i]; 136 tx_swbd->dma = dma; 137 tx_swbd->len = len; 138 tx_swbd->is_dma_page = 0; 139 count++; 140 141 do_vlan = skb_vlan_tag_present(skb); 142 do_tstamp = (active_offloads & ENETC_F_TX_TSTAMP) && 143 (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP); 144 tx_swbd->do_tstamp = do_tstamp; 145 tx_swbd->check_wb = tx_swbd->do_tstamp; 146 147 if (do_vlan || do_tstamp) 148 flags |= ENETC_TXBD_FLAGS_EX; 149 150 if (enetc_tx_csum(skb, &temp_bd)) 151 flags |= ENETC_TXBD_FLAGS_CSUM | ENETC_TXBD_FLAGS_L4CS; 152 else if (tx_ring->tsd_enable) 153 flags |= ENETC_TXBD_FLAGS_TSE | ENETC_TXBD_FLAGS_TXSTART; 154 155 /* first BD needs frm_len and offload flags set */ 156 temp_bd.frm_len = cpu_to_le16(skb->len); 157 temp_bd.flags = flags; 158 159 if (flags & ENETC_TXBD_FLAGS_TSE) { 160 u32 temp; 161 162 temp = (skb->skb_mstamp_ns >> 5 & ENETC_TXBD_TXSTART_MASK) 163 | (flags << ENETC_TXBD_FLAGS_OFFSET); 164 temp_bd.txstart = cpu_to_le32(temp); 165 } 166 167 if (flags & ENETC_TXBD_FLAGS_EX) { 168 u8 e_flags = 0; 169 *txbd = temp_bd; 170 enetc_clear_tx_bd(&temp_bd); 171 172 /* add extension BD for VLAN and/or timestamping */ 173 flags = 0; 174 tx_swbd++; 175 txbd++; 176 i++; 177 if (unlikely(i == tx_ring->bd_count)) { 178 i = 0; 179 tx_swbd = tx_ring->tx_swbd; 180 txbd = ENETC_TXBD(*tx_ring, 0); 181 } 182 prefetchw(txbd); 183 184 if (do_vlan) { 185 temp_bd.ext.vid = cpu_to_le16(skb_vlan_tag_get(skb)); 186 temp_bd.ext.tpid = 0; /* < C-TAG */ 187 e_flags |= ENETC_TXBD_E_FLAGS_VLAN_INS; 188 } 189 190 if (do_tstamp) { 191 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 192 e_flags |= ENETC_TXBD_E_FLAGS_TWO_STEP_PTP; 193 } 194 195 temp_bd.ext.e_flags = e_flags; 196 count++; 197 } 198 199 frag = &skb_shinfo(skb)->frags[0]; 200 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++, frag++) { 201 len = skb_frag_size(frag); 202 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, len, 203 DMA_TO_DEVICE); 204 if (dma_mapping_error(tx_ring->dev, dma)) 205 goto dma_err; 206 207 *txbd = temp_bd; 208 enetc_clear_tx_bd(&temp_bd); 209 210 flags = 0; 211 tx_swbd++; 212 txbd++; 213 i++; 214 if (unlikely(i == tx_ring->bd_count)) { 215 i = 0; 216 tx_swbd = tx_ring->tx_swbd; 217 txbd = ENETC_TXBD(*tx_ring, 0); 218 } 219 prefetchw(txbd); 220 221 temp_bd.addr = cpu_to_le64(dma); 222 temp_bd.buf_len = cpu_to_le16(len); 223 224 tx_swbd->dma = dma; 225 tx_swbd->len = len; 226 tx_swbd->is_dma_page = 1; 227 count++; 228 } 229 230 /* last BD needs 'F' bit set */ 231 flags |= ENETC_TXBD_FLAGS_F; 232 temp_bd.flags = flags; 233 *txbd = temp_bd; 234 235 tx_ring->tx_swbd[i].skb = skb; 236 237 enetc_bdr_idx_inc(tx_ring, &i); 238 tx_ring->next_to_use = i; 239 240 skb_tx_timestamp(skb); 241 242 /* let H/W know BD ring has been updated */ 243 enetc_wr_reg(tx_ring->tpir, i); /* includes wmb() */ 244 245 return count; 246 247 dma_err: 248 dev_err(tx_ring->dev, "DMA map error"); 249 250 do { 251 tx_swbd = &tx_ring->tx_swbd[i]; 252 enetc_free_tx_skb(tx_ring, tx_swbd); 253 if (i == 0) 254 i = tx_ring->bd_count; 255 i--; 256 } while (count--); 257 258 return 0; 259 } 260 261 static irqreturn_t enetc_msix(int irq, void *data) 262 { 263 struct enetc_int_vector *v = data; 264 int i; 265 266 /* disable interrupts */ 267 enetc_wr_reg(v->rbier, 0); 268 269 for_each_set_bit(i, &v->tx_rings_map, v->count_tx_rings) 270 enetc_wr_reg(v->tbier_base + ENETC_BDR_OFF(i), 0); 271 272 napi_schedule_irqoff(&v->napi); 273 274 return IRQ_HANDLED; 275 } 276 277 static bool enetc_clean_tx_ring(struct enetc_bdr *tx_ring, int napi_budget); 278 static int enetc_clean_rx_ring(struct enetc_bdr *rx_ring, 279 struct napi_struct *napi, int work_limit); 280 281 static int enetc_poll(struct napi_struct *napi, int budget) 282 { 283 struct enetc_int_vector 284 *v = container_of(napi, struct enetc_int_vector, napi); 285 bool complete = true; 286 int work_done; 287 int i; 288 289 for (i = 0; i < v->count_tx_rings; i++) 290 if (!enetc_clean_tx_ring(&v->tx_ring[i], budget)) 291 complete = false; 292 293 work_done = enetc_clean_rx_ring(&v->rx_ring, napi, budget); 294 if (work_done == budget) 295 complete = false; 296 297 if (!complete) 298 return budget; 299 300 napi_complete_done(napi, work_done); 301 302 /* enable interrupts */ 303 enetc_wr_reg(v->rbier, ENETC_RBIER_RXTIE); 304 305 for_each_set_bit(i, &v->tx_rings_map, v->count_tx_rings) 306 enetc_wr_reg(v->tbier_base + ENETC_BDR_OFF(i), 307 ENETC_TBIER_TXTIE); 308 309 return work_done; 310 } 311 312 static int enetc_bd_ready_count(struct enetc_bdr *tx_ring, int ci) 313 { 314 int pi = enetc_rd_reg(tx_ring->tcir) & ENETC_TBCIR_IDX_MASK; 315 316 return pi >= ci ? pi - ci : tx_ring->bd_count - ci + pi; 317 } 318 319 static void enetc_get_tx_tstamp(struct enetc_hw *hw, union enetc_tx_bd *txbd, 320 u64 *tstamp) 321 { 322 u32 lo, hi, tstamp_lo; 323 324 lo = enetc_rd(hw, ENETC_SICTR0); 325 hi = enetc_rd(hw, ENETC_SICTR1); 326 tstamp_lo = le32_to_cpu(txbd->wb.tstamp); 327 if (lo <= tstamp_lo) 328 hi -= 1; 329 *tstamp = (u64)hi << 32 | tstamp_lo; 330 } 331 332 static void enetc_tstamp_tx(struct sk_buff *skb, u64 tstamp) 333 { 334 struct skb_shared_hwtstamps shhwtstamps; 335 336 if (skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) { 337 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 338 shhwtstamps.hwtstamp = ns_to_ktime(tstamp); 339 skb_tstamp_tx(skb, &shhwtstamps); 340 } 341 } 342 343 static bool enetc_clean_tx_ring(struct enetc_bdr *tx_ring, int napi_budget) 344 { 345 struct net_device *ndev = tx_ring->ndev; 346 int tx_frm_cnt = 0, tx_byte_cnt = 0; 347 struct enetc_tx_swbd *tx_swbd; 348 int i, bds_to_clean; 349 bool do_tstamp; 350 u64 tstamp = 0; 351 352 i = tx_ring->next_to_clean; 353 tx_swbd = &tx_ring->tx_swbd[i]; 354 bds_to_clean = enetc_bd_ready_count(tx_ring, i); 355 356 do_tstamp = false; 357 358 while (bds_to_clean && tx_frm_cnt < ENETC_DEFAULT_TX_WORK) { 359 bool is_eof = !!tx_swbd->skb; 360 361 if (unlikely(tx_swbd->check_wb)) { 362 struct enetc_ndev_priv *priv = netdev_priv(ndev); 363 union enetc_tx_bd *txbd; 364 365 txbd = ENETC_TXBD(*tx_ring, i); 366 367 if (txbd->flags & ENETC_TXBD_FLAGS_W && 368 tx_swbd->do_tstamp) { 369 enetc_get_tx_tstamp(&priv->si->hw, txbd, 370 &tstamp); 371 do_tstamp = true; 372 } 373 } 374 375 if (likely(tx_swbd->dma)) 376 enetc_unmap_tx_buff(tx_ring, tx_swbd); 377 378 if (is_eof) { 379 if (unlikely(do_tstamp)) { 380 enetc_tstamp_tx(tx_swbd->skb, tstamp); 381 do_tstamp = false; 382 } 383 napi_consume_skb(tx_swbd->skb, napi_budget); 384 tx_swbd->skb = NULL; 385 } 386 387 tx_byte_cnt += tx_swbd->len; 388 389 bds_to_clean--; 390 tx_swbd++; 391 i++; 392 if (unlikely(i == tx_ring->bd_count)) { 393 i = 0; 394 tx_swbd = tx_ring->tx_swbd; 395 } 396 397 /* BD iteration loop end */ 398 if (is_eof) { 399 tx_frm_cnt++; 400 /* re-arm interrupt source */ 401 enetc_wr_reg(tx_ring->idr, BIT(tx_ring->index) | 402 BIT(16 + tx_ring->index)); 403 } 404 405 if (unlikely(!bds_to_clean)) 406 bds_to_clean = enetc_bd_ready_count(tx_ring, i); 407 } 408 409 tx_ring->next_to_clean = i; 410 tx_ring->stats.packets += tx_frm_cnt; 411 tx_ring->stats.bytes += tx_byte_cnt; 412 413 if (unlikely(tx_frm_cnt && netif_carrier_ok(ndev) && 414 __netif_subqueue_stopped(ndev, tx_ring->index) && 415 (enetc_bd_unused(tx_ring) >= ENETC_TXBDS_MAX_NEEDED))) { 416 netif_wake_subqueue(ndev, tx_ring->index); 417 } 418 419 return tx_frm_cnt != ENETC_DEFAULT_TX_WORK; 420 } 421 422 static bool enetc_new_page(struct enetc_bdr *rx_ring, 423 struct enetc_rx_swbd *rx_swbd) 424 { 425 struct page *page; 426 dma_addr_t addr; 427 428 page = dev_alloc_page(); 429 if (unlikely(!page)) 430 return false; 431 432 addr = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE); 433 if (unlikely(dma_mapping_error(rx_ring->dev, addr))) { 434 __free_page(page); 435 436 return false; 437 } 438 439 rx_swbd->dma = addr; 440 rx_swbd->page = page; 441 rx_swbd->page_offset = ENETC_RXB_PAD; 442 443 return true; 444 } 445 446 static int enetc_refill_rx_ring(struct enetc_bdr *rx_ring, const int buff_cnt) 447 { 448 struct enetc_rx_swbd *rx_swbd; 449 union enetc_rx_bd *rxbd; 450 int i, j; 451 452 i = rx_ring->next_to_use; 453 rx_swbd = &rx_ring->rx_swbd[i]; 454 rxbd = ENETC_RXBD(*rx_ring, i); 455 456 for (j = 0; j < buff_cnt; j++) { 457 /* try reuse page */ 458 if (unlikely(!rx_swbd->page)) { 459 if (unlikely(!enetc_new_page(rx_ring, rx_swbd))) { 460 rx_ring->stats.rx_alloc_errs++; 461 break; 462 } 463 } 464 465 /* update RxBD */ 466 rxbd->w.addr = cpu_to_le64(rx_swbd->dma + 467 rx_swbd->page_offset); 468 /* clear 'R" as well */ 469 rxbd->r.lstatus = 0; 470 471 rx_swbd++; 472 rxbd++; 473 i++; 474 if (unlikely(i == rx_ring->bd_count)) { 475 i = 0; 476 rx_swbd = rx_ring->rx_swbd; 477 rxbd = ENETC_RXBD(*rx_ring, 0); 478 } 479 } 480 481 if (likely(j)) { 482 rx_ring->next_to_alloc = i; /* keep track from page reuse */ 483 rx_ring->next_to_use = i; 484 /* update ENETC's consumer index */ 485 enetc_wr_reg(rx_ring->rcir, i); 486 } 487 488 return j; 489 } 490 491 #ifdef CONFIG_FSL_ENETC_HW_TIMESTAMPING 492 static void enetc_get_rx_tstamp(struct net_device *ndev, 493 union enetc_rx_bd *rxbd, 494 struct sk_buff *skb) 495 { 496 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb); 497 struct enetc_ndev_priv *priv = netdev_priv(ndev); 498 struct enetc_hw *hw = &priv->si->hw; 499 u32 lo, hi, tstamp_lo; 500 u64 tstamp; 501 502 if (le16_to_cpu(rxbd->r.flags) & ENETC_RXBD_FLAG_TSTMP) { 503 lo = enetc_rd(hw, ENETC_SICTR0); 504 hi = enetc_rd(hw, ENETC_SICTR1); 505 tstamp_lo = le32_to_cpu(rxbd->r.tstamp); 506 if (lo <= tstamp_lo) 507 hi -= 1; 508 509 tstamp = (u64)hi << 32 | tstamp_lo; 510 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 511 shhwtstamps->hwtstamp = ns_to_ktime(tstamp); 512 } 513 } 514 #endif 515 516 static void enetc_get_offloads(struct enetc_bdr *rx_ring, 517 union enetc_rx_bd *rxbd, struct sk_buff *skb) 518 { 519 #ifdef CONFIG_FSL_ENETC_HW_TIMESTAMPING 520 struct enetc_ndev_priv *priv = netdev_priv(rx_ring->ndev); 521 #endif 522 /* TODO: hashing */ 523 if (rx_ring->ndev->features & NETIF_F_RXCSUM) { 524 u16 inet_csum = le16_to_cpu(rxbd->r.inet_csum); 525 526 skb->csum = csum_unfold((__force __sum16)~htons(inet_csum)); 527 skb->ip_summed = CHECKSUM_COMPLETE; 528 } 529 530 /* copy VLAN to skb, if one is extracted, for now we assume it's a 531 * standard TPID, but HW also supports custom values 532 */ 533 if (le16_to_cpu(rxbd->r.flags) & ENETC_RXBD_FLAG_VLAN) 534 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 535 le16_to_cpu(rxbd->r.vlan_opt)); 536 #ifdef CONFIG_FSL_ENETC_HW_TIMESTAMPING 537 if (priv->active_offloads & ENETC_F_RX_TSTAMP) 538 enetc_get_rx_tstamp(rx_ring->ndev, rxbd, skb); 539 #endif 540 } 541 542 static void enetc_process_skb(struct enetc_bdr *rx_ring, 543 struct sk_buff *skb) 544 { 545 skb_record_rx_queue(skb, rx_ring->index); 546 skb->protocol = eth_type_trans(skb, rx_ring->ndev); 547 } 548 549 static bool enetc_page_reusable(struct page *page) 550 { 551 return (!page_is_pfmemalloc(page) && page_ref_count(page) == 1); 552 } 553 554 static void enetc_reuse_page(struct enetc_bdr *rx_ring, 555 struct enetc_rx_swbd *old) 556 { 557 struct enetc_rx_swbd *new; 558 559 new = &rx_ring->rx_swbd[rx_ring->next_to_alloc]; 560 561 /* next buf that may reuse a page */ 562 enetc_bdr_idx_inc(rx_ring, &rx_ring->next_to_alloc); 563 564 /* copy page reference */ 565 *new = *old; 566 } 567 568 static struct enetc_rx_swbd *enetc_get_rx_buff(struct enetc_bdr *rx_ring, 569 int i, u16 size) 570 { 571 struct enetc_rx_swbd *rx_swbd = &rx_ring->rx_swbd[i]; 572 573 dma_sync_single_range_for_cpu(rx_ring->dev, rx_swbd->dma, 574 rx_swbd->page_offset, 575 size, DMA_FROM_DEVICE); 576 return rx_swbd; 577 } 578 579 static void enetc_put_rx_buff(struct enetc_bdr *rx_ring, 580 struct enetc_rx_swbd *rx_swbd) 581 { 582 if (likely(enetc_page_reusable(rx_swbd->page))) { 583 rx_swbd->page_offset ^= ENETC_RXB_TRUESIZE; 584 page_ref_inc(rx_swbd->page); 585 586 enetc_reuse_page(rx_ring, rx_swbd); 587 588 /* sync for use by the device */ 589 dma_sync_single_range_for_device(rx_ring->dev, rx_swbd->dma, 590 rx_swbd->page_offset, 591 ENETC_RXB_DMA_SIZE, 592 DMA_FROM_DEVICE); 593 } else { 594 dma_unmap_page(rx_ring->dev, rx_swbd->dma, 595 PAGE_SIZE, DMA_FROM_DEVICE); 596 } 597 598 rx_swbd->page = NULL; 599 } 600 601 static struct sk_buff *enetc_map_rx_buff_to_skb(struct enetc_bdr *rx_ring, 602 int i, u16 size) 603 { 604 struct enetc_rx_swbd *rx_swbd = enetc_get_rx_buff(rx_ring, i, size); 605 struct sk_buff *skb; 606 void *ba; 607 608 ba = page_address(rx_swbd->page) + rx_swbd->page_offset; 609 skb = build_skb(ba - ENETC_RXB_PAD, ENETC_RXB_TRUESIZE); 610 if (unlikely(!skb)) { 611 rx_ring->stats.rx_alloc_errs++; 612 return NULL; 613 } 614 615 skb_reserve(skb, ENETC_RXB_PAD); 616 __skb_put(skb, size); 617 618 enetc_put_rx_buff(rx_ring, rx_swbd); 619 620 return skb; 621 } 622 623 static void enetc_add_rx_buff_to_skb(struct enetc_bdr *rx_ring, int i, 624 u16 size, struct sk_buff *skb) 625 { 626 struct enetc_rx_swbd *rx_swbd = enetc_get_rx_buff(rx_ring, i, size); 627 628 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_swbd->page, 629 rx_swbd->page_offset, size, ENETC_RXB_TRUESIZE); 630 631 enetc_put_rx_buff(rx_ring, rx_swbd); 632 } 633 634 #define ENETC_RXBD_BUNDLE 16 /* # of BDs to update at once */ 635 636 static int enetc_clean_rx_ring(struct enetc_bdr *rx_ring, 637 struct napi_struct *napi, int work_limit) 638 { 639 int rx_frm_cnt = 0, rx_byte_cnt = 0; 640 int cleaned_cnt, i; 641 642 cleaned_cnt = enetc_bd_unused(rx_ring); 643 /* next descriptor to process */ 644 i = rx_ring->next_to_clean; 645 646 while (likely(rx_frm_cnt < work_limit)) { 647 union enetc_rx_bd *rxbd; 648 struct sk_buff *skb; 649 u32 bd_status; 650 u16 size; 651 652 if (cleaned_cnt >= ENETC_RXBD_BUNDLE) { 653 int count = enetc_refill_rx_ring(rx_ring, cleaned_cnt); 654 655 cleaned_cnt -= count; 656 } 657 658 rxbd = ENETC_RXBD(*rx_ring, i); 659 bd_status = le32_to_cpu(rxbd->r.lstatus); 660 if (!bd_status) 661 break; 662 663 enetc_wr_reg(rx_ring->idr, BIT(rx_ring->index)); 664 dma_rmb(); /* for reading other rxbd fields */ 665 size = le16_to_cpu(rxbd->r.buf_len); 666 skb = enetc_map_rx_buff_to_skb(rx_ring, i, size); 667 if (!skb) 668 break; 669 670 enetc_get_offloads(rx_ring, rxbd, skb); 671 672 cleaned_cnt++; 673 rxbd++; 674 i++; 675 if (unlikely(i == rx_ring->bd_count)) { 676 i = 0; 677 rxbd = ENETC_RXBD(*rx_ring, 0); 678 } 679 680 if (unlikely(bd_status & 681 ENETC_RXBD_LSTATUS(ENETC_RXBD_ERR_MASK))) { 682 dev_kfree_skb(skb); 683 while (!(bd_status & ENETC_RXBD_LSTATUS_F)) { 684 dma_rmb(); 685 bd_status = le32_to_cpu(rxbd->r.lstatus); 686 rxbd++; 687 i++; 688 if (unlikely(i == rx_ring->bd_count)) { 689 i = 0; 690 rxbd = ENETC_RXBD(*rx_ring, 0); 691 } 692 } 693 694 rx_ring->ndev->stats.rx_dropped++; 695 rx_ring->ndev->stats.rx_errors++; 696 697 break; 698 } 699 700 /* not last BD in frame? */ 701 while (!(bd_status & ENETC_RXBD_LSTATUS_F)) { 702 bd_status = le32_to_cpu(rxbd->r.lstatus); 703 size = ENETC_RXB_DMA_SIZE; 704 705 if (bd_status & ENETC_RXBD_LSTATUS_F) { 706 dma_rmb(); 707 size = le16_to_cpu(rxbd->r.buf_len); 708 } 709 710 enetc_add_rx_buff_to_skb(rx_ring, i, size, skb); 711 712 cleaned_cnt++; 713 rxbd++; 714 i++; 715 if (unlikely(i == rx_ring->bd_count)) { 716 i = 0; 717 rxbd = ENETC_RXBD(*rx_ring, 0); 718 } 719 } 720 721 rx_byte_cnt += skb->len; 722 723 enetc_process_skb(rx_ring, skb); 724 725 napi_gro_receive(napi, skb); 726 727 rx_frm_cnt++; 728 } 729 730 rx_ring->next_to_clean = i; 731 732 rx_ring->stats.packets += rx_frm_cnt; 733 rx_ring->stats.bytes += rx_byte_cnt; 734 735 return rx_frm_cnt; 736 } 737 738 /* Probing and Init */ 739 #define ENETC_MAX_RFS_SIZE 64 740 void enetc_get_si_caps(struct enetc_si *si) 741 { 742 struct enetc_hw *hw = &si->hw; 743 u32 val; 744 745 /* find out how many of various resources we have to work with */ 746 val = enetc_rd(hw, ENETC_SICAPR0); 747 si->num_rx_rings = (val >> 16) & 0xff; 748 si->num_tx_rings = val & 0xff; 749 750 val = enetc_rd(hw, ENETC_SIRFSCAPR); 751 si->num_fs_entries = ENETC_SIRFSCAPR_GET_NUM_RFS(val); 752 si->num_fs_entries = min(si->num_fs_entries, ENETC_MAX_RFS_SIZE); 753 754 si->num_rss = 0; 755 val = enetc_rd(hw, ENETC_SIPCAPR0); 756 if (val & ENETC_SIPCAPR0_RSS) { 757 u32 rss; 758 759 rss = enetc_rd(hw, ENETC_SIRSSCAPR); 760 si->num_rss = ENETC_SIRSSCAPR_GET_NUM_RSS(rss); 761 } 762 763 if (val & ENETC_SIPCAPR0_QBV) 764 si->hw_features |= ENETC_SI_F_QBV; 765 } 766 767 static int enetc_dma_alloc_bdr(struct enetc_bdr *r, size_t bd_size) 768 { 769 r->bd_base = dma_alloc_coherent(r->dev, r->bd_count * bd_size, 770 &r->bd_dma_base, GFP_KERNEL); 771 if (!r->bd_base) 772 return -ENOMEM; 773 774 /* h/w requires 128B alignment */ 775 if (!IS_ALIGNED(r->bd_dma_base, 128)) { 776 dma_free_coherent(r->dev, r->bd_count * bd_size, r->bd_base, 777 r->bd_dma_base); 778 return -EINVAL; 779 } 780 781 return 0; 782 } 783 784 static int enetc_alloc_txbdr(struct enetc_bdr *txr) 785 { 786 int err; 787 788 txr->tx_swbd = vzalloc(txr->bd_count * sizeof(struct enetc_tx_swbd)); 789 if (!txr->tx_swbd) 790 return -ENOMEM; 791 792 err = enetc_dma_alloc_bdr(txr, sizeof(union enetc_tx_bd)); 793 if (err) { 794 vfree(txr->tx_swbd); 795 return err; 796 } 797 798 txr->next_to_clean = 0; 799 txr->next_to_use = 0; 800 801 return 0; 802 } 803 804 static void enetc_free_txbdr(struct enetc_bdr *txr) 805 { 806 int size, i; 807 808 for (i = 0; i < txr->bd_count; i++) 809 enetc_free_tx_skb(txr, &txr->tx_swbd[i]); 810 811 size = txr->bd_count * sizeof(union enetc_tx_bd); 812 813 dma_free_coherent(txr->dev, size, txr->bd_base, txr->bd_dma_base); 814 txr->bd_base = NULL; 815 816 vfree(txr->tx_swbd); 817 txr->tx_swbd = NULL; 818 } 819 820 static int enetc_alloc_tx_resources(struct enetc_ndev_priv *priv) 821 { 822 int i, err; 823 824 for (i = 0; i < priv->num_tx_rings; i++) { 825 err = enetc_alloc_txbdr(priv->tx_ring[i]); 826 827 if (err) 828 goto fail; 829 } 830 831 return 0; 832 833 fail: 834 while (i-- > 0) 835 enetc_free_txbdr(priv->tx_ring[i]); 836 837 return err; 838 } 839 840 static void enetc_free_tx_resources(struct enetc_ndev_priv *priv) 841 { 842 int i; 843 844 for (i = 0; i < priv->num_tx_rings; i++) 845 enetc_free_txbdr(priv->tx_ring[i]); 846 } 847 848 static int enetc_alloc_rxbdr(struct enetc_bdr *rxr) 849 { 850 int err; 851 852 rxr->rx_swbd = vzalloc(rxr->bd_count * sizeof(struct enetc_rx_swbd)); 853 if (!rxr->rx_swbd) 854 return -ENOMEM; 855 856 err = enetc_dma_alloc_bdr(rxr, sizeof(union enetc_rx_bd)); 857 if (err) { 858 vfree(rxr->rx_swbd); 859 return err; 860 } 861 862 rxr->next_to_clean = 0; 863 rxr->next_to_use = 0; 864 rxr->next_to_alloc = 0; 865 866 return 0; 867 } 868 869 static void enetc_free_rxbdr(struct enetc_bdr *rxr) 870 { 871 int size; 872 873 size = rxr->bd_count * sizeof(union enetc_rx_bd); 874 875 dma_free_coherent(rxr->dev, size, rxr->bd_base, rxr->bd_dma_base); 876 rxr->bd_base = NULL; 877 878 vfree(rxr->rx_swbd); 879 rxr->rx_swbd = NULL; 880 } 881 882 static int enetc_alloc_rx_resources(struct enetc_ndev_priv *priv) 883 { 884 int i, err; 885 886 for (i = 0; i < priv->num_rx_rings; i++) { 887 err = enetc_alloc_rxbdr(priv->rx_ring[i]); 888 889 if (err) 890 goto fail; 891 } 892 893 return 0; 894 895 fail: 896 while (i-- > 0) 897 enetc_free_rxbdr(priv->rx_ring[i]); 898 899 return err; 900 } 901 902 static void enetc_free_rx_resources(struct enetc_ndev_priv *priv) 903 { 904 int i; 905 906 for (i = 0; i < priv->num_rx_rings; i++) 907 enetc_free_rxbdr(priv->rx_ring[i]); 908 } 909 910 static void enetc_free_tx_ring(struct enetc_bdr *tx_ring) 911 { 912 int i; 913 914 if (!tx_ring->tx_swbd) 915 return; 916 917 for (i = 0; i < tx_ring->bd_count; i++) { 918 struct enetc_tx_swbd *tx_swbd = &tx_ring->tx_swbd[i]; 919 920 enetc_free_tx_skb(tx_ring, tx_swbd); 921 } 922 923 tx_ring->next_to_clean = 0; 924 tx_ring->next_to_use = 0; 925 } 926 927 static void enetc_free_rx_ring(struct enetc_bdr *rx_ring) 928 { 929 int i; 930 931 if (!rx_ring->rx_swbd) 932 return; 933 934 for (i = 0; i < rx_ring->bd_count; i++) { 935 struct enetc_rx_swbd *rx_swbd = &rx_ring->rx_swbd[i]; 936 937 if (!rx_swbd->page) 938 continue; 939 940 dma_unmap_page(rx_ring->dev, rx_swbd->dma, 941 PAGE_SIZE, DMA_FROM_DEVICE); 942 __free_page(rx_swbd->page); 943 rx_swbd->page = NULL; 944 } 945 946 rx_ring->next_to_clean = 0; 947 rx_ring->next_to_use = 0; 948 rx_ring->next_to_alloc = 0; 949 } 950 951 static void enetc_free_rxtx_rings(struct enetc_ndev_priv *priv) 952 { 953 int i; 954 955 for (i = 0; i < priv->num_rx_rings; i++) 956 enetc_free_rx_ring(priv->rx_ring[i]); 957 958 for (i = 0; i < priv->num_tx_rings; i++) 959 enetc_free_tx_ring(priv->tx_ring[i]); 960 } 961 962 static int enetc_alloc_cbdr(struct device *dev, struct enetc_cbdr *cbdr) 963 { 964 int size = cbdr->bd_count * sizeof(struct enetc_cbd); 965 966 cbdr->bd_base = dma_alloc_coherent(dev, size, &cbdr->bd_dma_base, 967 GFP_KERNEL); 968 if (!cbdr->bd_base) 969 return -ENOMEM; 970 971 /* h/w requires 128B alignment */ 972 if (!IS_ALIGNED(cbdr->bd_dma_base, 128)) { 973 dma_free_coherent(dev, size, cbdr->bd_base, cbdr->bd_dma_base); 974 return -EINVAL; 975 } 976 977 cbdr->next_to_clean = 0; 978 cbdr->next_to_use = 0; 979 980 return 0; 981 } 982 983 static void enetc_free_cbdr(struct device *dev, struct enetc_cbdr *cbdr) 984 { 985 int size = cbdr->bd_count * sizeof(struct enetc_cbd); 986 987 dma_free_coherent(dev, size, cbdr->bd_base, cbdr->bd_dma_base); 988 cbdr->bd_base = NULL; 989 } 990 991 static void enetc_setup_cbdr(struct enetc_hw *hw, struct enetc_cbdr *cbdr) 992 { 993 /* set CBDR cache attributes */ 994 enetc_wr(hw, ENETC_SICAR2, 995 ENETC_SICAR_RD_COHERENT | ENETC_SICAR_WR_COHERENT); 996 997 enetc_wr(hw, ENETC_SICBDRBAR0, lower_32_bits(cbdr->bd_dma_base)); 998 enetc_wr(hw, ENETC_SICBDRBAR1, upper_32_bits(cbdr->bd_dma_base)); 999 enetc_wr(hw, ENETC_SICBDRLENR, ENETC_RTBLENR_LEN(cbdr->bd_count)); 1000 1001 enetc_wr(hw, ENETC_SICBDRPIR, 0); 1002 enetc_wr(hw, ENETC_SICBDRCIR, 0); 1003 1004 /* enable ring */ 1005 enetc_wr(hw, ENETC_SICBDRMR, BIT(31)); 1006 1007 cbdr->pir = hw->reg + ENETC_SICBDRPIR; 1008 cbdr->cir = hw->reg + ENETC_SICBDRCIR; 1009 } 1010 1011 static void enetc_clear_cbdr(struct enetc_hw *hw) 1012 { 1013 enetc_wr(hw, ENETC_SICBDRMR, 0); 1014 } 1015 1016 static int enetc_setup_default_rss_table(struct enetc_si *si, int num_groups) 1017 { 1018 int *rss_table; 1019 int i; 1020 1021 rss_table = kmalloc_array(si->num_rss, sizeof(*rss_table), GFP_KERNEL); 1022 if (!rss_table) 1023 return -ENOMEM; 1024 1025 /* Set up RSS table defaults */ 1026 for (i = 0; i < si->num_rss; i++) 1027 rss_table[i] = i % num_groups; 1028 1029 enetc_set_rss_table(si, rss_table, si->num_rss); 1030 1031 kfree(rss_table); 1032 1033 return 0; 1034 } 1035 1036 static int enetc_configure_si(struct enetc_ndev_priv *priv) 1037 { 1038 struct enetc_si *si = priv->si; 1039 struct enetc_hw *hw = &si->hw; 1040 int err; 1041 1042 enetc_setup_cbdr(hw, &si->cbd_ring); 1043 /* set SI cache attributes */ 1044 enetc_wr(hw, ENETC_SICAR0, 1045 ENETC_SICAR_RD_COHERENT | ENETC_SICAR_WR_COHERENT); 1046 enetc_wr(hw, ENETC_SICAR1, ENETC_SICAR_MSI); 1047 /* enable SI */ 1048 enetc_wr(hw, ENETC_SIMR, ENETC_SIMR_EN); 1049 1050 if (si->num_rss) { 1051 err = enetc_setup_default_rss_table(si, priv->num_rx_rings); 1052 if (err) 1053 return err; 1054 } 1055 1056 return 0; 1057 } 1058 1059 void enetc_init_si_rings_params(struct enetc_ndev_priv *priv) 1060 { 1061 struct enetc_si *si = priv->si; 1062 int cpus = num_online_cpus(); 1063 1064 priv->tx_bd_count = ENETC_BDR_DEFAULT_SIZE; 1065 priv->rx_bd_count = ENETC_BDR_DEFAULT_SIZE; 1066 1067 /* Enable all available TX rings in order to configure as many 1068 * priorities as possible, when needed. 1069 * TODO: Make # of TX rings run-time configurable 1070 */ 1071 priv->num_rx_rings = min_t(int, cpus, si->num_rx_rings); 1072 priv->num_tx_rings = si->num_tx_rings; 1073 priv->bdr_int_num = cpus; 1074 1075 /* SI specific */ 1076 si->cbd_ring.bd_count = ENETC_CBDR_DEFAULT_SIZE; 1077 } 1078 1079 int enetc_alloc_si_resources(struct enetc_ndev_priv *priv) 1080 { 1081 struct enetc_si *si = priv->si; 1082 int err; 1083 1084 err = enetc_alloc_cbdr(priv->dev, &si->cbd_ring); 1085 if (err) 1086 return err; 1087 1088 priv->cls_rules = kcalloc(si->num_fs_entries, sizeof(*priv->cls_rules), 1089 GFP_KERNEL); 1090 if (!priv->cls_rules) { 1091 err = -ENOMEM; 1092 goto err_alloc_cls; 1093 } 1094 1095 err = enetc_configure_si(priv); 1096 if (err) 1097 goto err_config_si; 1098 1099 return 0; 1100 1101 err_config_si: 1102 kfree(priv->cls_rules); 1103 err_alloc_cls: 1104 enetc_clear_cbdr(&si->hw); 1105 enetc_free_cbdr(priv->dev, &si->cbd_ring); 1106 1107 return err; 1108 } 1109 1110 void enetc_free_si_resources(struct enetc_ndev_priv *priv) 1111 { 1112 struct enetc_si *si = priv->si; 1113 1114 enetc_clear_cbdr(&si->hw); 1115 enetc_free_cbdr(priv->dev, &si->cbd_ring); 1116 1117 kfree(priv->cls_rules); 1118 } 1119 1120 static void enetc_setup_txbdr(struct enetc_hw *hw, struct enetc_bdr *tx_ring) 1121 { 1122 int idx = tx_ring->index; 1123 u32 tbmr; 1124 1125 enetc_txbdr_wr(hw, idx, ENETC_TBBAR0, 1126 lower_32_bits(tx_ring->bd_dma_base)); 1127 1128 enetc_txbdr_wr(hw, idx, ENETC_TBBAR1, 1129 upper_32_bits(tx_ring->bd_dma_base)); 1130 1131 WARN_ON(!IS_ALIGNED(tx_ring->bd_count, 64)); /* multiple of 64 */ 1132 enetc_txbdr_wr(hw, idx, ENETC_TBLENR, 1133 ENETC_RTBLENR_LEN(tx_ring->bd_count)); 1134 1135 /* clearing PI/CI registers for Tx not supported, adjust sw indexes */ 1136 tx_ring->next_to_use = enetc_txbdr_rd(hw, idx, ENETC_TBPIR); 1137 tx_ring->next_to_clean = enetc_txbdr_rd(hw, idx, ENETC_TBCIR); 1138 1139 /* enable Tx ints by setting pkt thr to 1 */ 1140 enetc_txbdr_wr(hw, idx, ENETC_TBICIR0, ENETC_TBICIR0_ICEN | 0x1); 1141 1142 tbmr = ENETC_TBMR_EN; 1143 if (tx_ring->ndev->features & NETIF_F_HW_VLAN_CTAG_TX) 1144 tbmr |= ENETC_TBMR_VIH; 1145 1146 /* enable ring */ 1147 enetc_txbdr_wr(hw, idx, ENETC_TBMR, tbmr); 1148 1149 tx_ring->tpir = hw->reg + ENETC_BDR(TX, idx, ENETC_TBPIR); 1150 tx_ring->tcir = hw->reg + ENETC_BDR(TX, idx, ENETC_TBCIR); 1151 tx_ring->idr = hw->reg + ENETC_SITXIDR; 1152 } 1153 1154 static void enetc_setup_rxbdr(struct enetc_hw *hw, struct enetc_bdr *rx_ring) 1155 { 1156 int idx = rx_ring->index; 1157 u32 rbmr; 1158 1159 enetc_rxbdr_wr(hw, idx, ENETC_RBBAR0, 1160 lower_32_bits(rx_ring->bd_dma_base)); 1161 1162 enetc_rxbdr_wr(hw, idx, ENETC_RBBAR1, 1163 upper_32_bits(rx_ring->bd_dma_base)); 1164 1165 WARN_ON(!IS_ALIGNED(rx_ring->bd_count, 64)); /* multiple of 64 */ 1166 enetc_rxbdr_wr(hw, idx, ENETC_RBLENR, 1167 ENETC_RTBLENR_LEN(rx_ring->bd_count)); 1168 1169 enetc_rxbdr_wr(hw, idx, ENETC_RBBSR, ENETC_RXB_DMA_SIZE); 1170 1171 enetc_rxbdr_wr(hw, idx, ENETC_RBPIR, 0); 1172 1173 /* enable Rx ints by setting pkt thr to 1 */ 1174 enetc_rxbdr_wr(hw, idx, ENETC_RBICIR0, ENETC_RBICIR0_ICEN | 0x1); 1175 1176 rbmr = ENETC_RBMR_EN; 1177 #ifdef CONFIG_FSL_ENETC_HW_TIMESTAMPING 1178 rbmr |= ENETC_RBMR_BDS; 1179 #endif 1180 if (rx_ring->ndev->features & NETIF_F_HW_VLAN_CTAG_RX) 1181 rbmr |= ENETC_RBMR_VTE; 1182 1183 rx_ring->rcir = hw->reg + ENETC_BDR(RX, idx, ENETC_RBCIR); 1184 rx_ring->idr = hw->reg + ENETC_SIRXIDR; 1185 1186 enetc_refill_rx_ring(rx_ring, enetc_bd_unused(rx_ring)); 1187 1188 /* enable ring */ 1189 enetc_rxbdr_wr(hw, idx, ENETC_RBMR, rbmr); 1190 } 1191 1192 static void enetc_setup_bdrs(struct enetc_ndev_priv *priv) 1193 { 1194 int i; 1195 1196 for (i = 0; i < priv->num_tx_rings; i++) 1197 enetc_setup_txbdr(&priv->si->hw, priv->tx_ring[i]); 1198 1199 for (i = 0; i < priv->num_rx_rings; i++) 1200 enetc_setup_rxbdr(&priv->si->hw, priv->rx_ring[i]); 1201 } 1202 1203 static void enetc_clear_rxbdr(struct enetc_hw *hw, struct enetc_bdr *rx_ring) 1204 { 1205 int idx = rx_ring->index; 1206 1207 /* disable EN bit on ring */ 1208 enetc_rxbdr_wr(hw, idx, ENETC_RBMR, 0); 1209 } 1210 1211 static void enetc_clear_txbdr(struct enetc_hw *hw, struct enetc_bdr *tx_ring) 1212 { 1213 int delay = 8, timeout = 100; 1214 int idx = tx_ring->index; 1215 1216 /* disable EN bit on ring */ 1217 enetc_txbdr_wr(hw, idx, ENETC_TBMR, 0); 1218 1219 /* wait for busy to clear */ 1220 while (delay < timeout && 1221 enetc_txbdr_rd(hw, idx, ENETC_TBSR) & ENETC_TBSR_BUSY) { 1222 msleep(delay); 1223 delay *= 2; 1224 } 1225 1226 if (delay >= timeout) 1227 netdev_warn(tx_ring->ndev, "timeout for tx ring #%d clear\n", 1228 idx); 1229 } 1230 1231 static void enetc_clear_bdrs(struct enetc_ndev_priv *priv) 1232 { 1233 int i; 1234 1235 for (i = 0; i < priv->num_tx_rings; i++) 1236 enetc_clear_txbdr(&priv->si->hw, priv->tx_ring[i]); 1237 1238 for (i = 0; i < priv->num_rx_rings; i++) 1239 enetc_clear_rxbdr(&priv->si->hw, priv->rx_ring[i]); 1240 1241 udelay(1); 1242 } 1243 1244 static int enetc_setup_irqs(struct enetc_ndev_priv *priv) 1245 { 1246 struct pci_dev *pdev = priv->si->pdev; 1247 cpumask_t cpu_mask; 1248 int i, j, err; 1249 1250 for (i = 0; i < priv->bdr_int_num; i++) { 1251 int irq = pci_irq_vector(pdev, ENETC_BDR_INT_BASE_IDX + i); 1252 struct enetc_int_vector *v = priv->int_vector[i]; 1253 int entry = ENETC_BDR_INT_BASE_IDX + i; 1254 struct enetc_hw *hw = &priv->si->hw; 1255 1256 snprintf(v->name, sizeof(v->name), "%s-rxtx%d", 1257 priv->ndev->name, i); 1258 err = request_irq(irq, enetc_msix, 0, v->name, v); 1259 if (err) { 1260 dev_err(priv->dev, "request_irq() failed!\n"); 1261 goto irq_err; 1262 } 1263 1264 v->tbier_base = hw->reg + ENETC_BDR(TX, 0, ENETC_TBIER); 1265 v->rbier = hw->reg + ENETC_BDR(RX, i, ENETC_RBIER); 1266 1267 enetc_wr(hw, ENETC_SIMSIRRV(i), entry); 1268 1269 for (j = 0; j < v->count_tx_rings; j++) { 1270 int idx = v->tx_ring[j].index; 1271 1272 enetc_wr(hw, ENETC_SIMSITRV(idx), entry); 1273 } 1274 cpumask_clear(&cpu_mask); 1275 cpumask_set_cpu(i % num_online_cpus(), &cpu_mask); 1276 irq_set_affinity_hint(irq, &cpu_mask); 1277 } 1278 1279 return 0; 1280 1281 irq_err: 1282 while (i--) { 1283 int irq = pci_irq_vector(pdev, ENETC_BDR_INT_BASE_IDX + i); 1284 1285 irq_set_affinity_hint(irq, NULL); 1286 free_irq(irq, priv->int_vector[i]); 1287 } 1288 1289 return err; 1290 } 1291 1292 static void enetc_free_irqs(struct enetc_ndev_priv *priv) 1293 { 1294 struct pci_dev *pdev = priv->si->pdev; 1295 int i; 1296 1297 for (i = 0; i < priv->bdr_int_num; i++) { 1298 int irq = pci_irq_vector(pdev, ENETC_BDR_INT_BASE_IDX + i); 1299 1300 irq_set_affinity_hint(irq, NULL); 1301 free_irq(irq, priv->int_vector[i]); 1302 } 1303 } 1304 1305 static void enetc_enable_interrupts(struct enetc_ndev_priv *priv) 1306 { 1307 int i; 1308 1309 /* enable Tx & Rx event indication */ 1310 for (i = 0; i < priv->num_rx_rings; i++) { 1311 enetc_rxbdr_wr(&priv->si->hw, i, 1312 ENETC_RBIER, ENETC_RBIER_RXTIE); 1313 } 1314 1315 for (i = 0; i < priv->num_tx_rings; i++) { 1316 enetc_txbdr_wr(&priv->si->hw, i, 1317 ENETC_TBIER, ENETC_TBIER_TXTIE); 1318 } 1319 } 1320 1321 static void enetc_disable_interrupts(struct enetc_ndev_priv *priv) 1322 { 1323 int i; 1324 1325 for (i = 0; i < priv->num_tx_rings; i++) 1326 enetc_txbdr_wr(&priv->si->hw, i, ENETC_TBIER, 0); 1327 1328 for (i = 0; i < priv->num_rx_rings; i++) 1329 enetc_rxbdr_wr(&priv->si->hw, i, ENETC_RBIER, 0); 1330 } 1331 1332 static void adjust_link(struct net_device *ndev) 1333 { 1334 struct enetc_ndev_priv *priv = netdev_priv(ndev); 1335 struct phy_device *phydev = ndev->phydev; 1336 1337 if (priv->active_offloads & ENETC_F_QBV) 1338 enetc_sched_speed_set(ndev); 1339 1340 phy_print_status(phydev); 1341 } 1342 1343 static int enetc_phy_connect(struct net_device *ndev) 1344 { 1345 struct enetc_ndev_priv *priv = netdev_priv(ndev); 1346 struct phy_device *phydev; 1347 struct ethtool_eee edata; 1348 1349 if (!priv->phy_node) 1350 return 0; /* phy-less mode */ 1351 1352 phydev = of_phy_connect(ndev, priv->phy_node, &adjust_link, 1353 0, priv->if_mode); 1354 if (!phydev) { 1355 dev_err(&ndev->dev, "could not attach to PHY\n"); 1356 return -ENODEV; 1357 } 1358 1359 phy_attached_info(phydev); 1360 1361 /* disable EEE autoneg, until ENETC driver supports it */ 1362 memset(&edata, 0, sizeof(struct ethtool_eee)); 1363 phy_ethtool_set_eee(phydev, &edata); 1364 1365 return 0; 1366 } 1367 1368 int enetc_open(struct net_device *ndev) 1369 { 1370 struct enetc_ndev_priv *priv = netdev_priv(ndev); 1371 int i, err; 1372 1373 err = enetc_setup_irqs(priv); 1374 if (err) 1375 return err; 1376 1377 err = enetc_phy_connect(ndev); 1378 if (err) 1379 goto err_phy_connect; 1380 1381 err = enetc_alloc_tx_resources(priv); 1382 if (err) 1383 goto err_alloc_tx; 1384 1385 err = enetc_alloc_rx_resources(priv); 1386 if (err) 1387 goto err_alloc_rx; 1388 1389 enetc_setup_bdrs(priv); 1390 1391 err = netif_set_real_num_tx_queues(ndev, priv->num_tx_rings); 1392 if (err) 1393 goto err_set_queues; 1394 1395 err = netif_set_real_num_rx_queues(ndev, priv->num_rx_rings); 1396 if (err) 1397 goto err_set_queues; 1398 1399 for (i = 0; i < priv->bdr_int_num; i++) 1400 napi_enable(&priv->int_vector[i]->napi); 1401 1402 enetc_enable_interrupts(priv); 1403 1404 if (ndev->phydev) 1405 phy_start(ndev->phydev); 1406 else 1407 netif_carrier_on(ndev); 1408 1409 netif_tx_start_all_queues(ndev); 1410 1411 return 0; 1412 1413 err_set_queues: 1414 enetc_free_rx_resources(priv); 1415 err_alloc_rx: 1416 enetc_free_tx_resources(priv); 1417 err_alloc_tx: 1418 if (ndev->phydev) 1419 phy_disconnect(ndev->phydev); 1420 err_phy_connect: 1421 enetc_free_irqs(priv); 1422 1423 return err; 1424 } 1425 1426 int enetc_close(struct net_device *ndev) 1427 { 1428 struct enetc_ndev_priv *priv = netdev_priv(ndev); 1429 int i; 1430 1431 netif_tx_stop_all_queues(ndev); 1432 1433 if (ndev->phydev) { 1434 phy_stop(ndev->phydev); 1435 phy_disconnect(ndev->phydev); 1436 } else { 1437 netif_carrier_off(ndev); 1438 } 1439 1440 for (i = 0; i < priv->bdr_int_num; i++) { 1441 napi_synchronize(&priv->int_vector[i]->napi); 1442 napi_disable(&priv->int_vector[i]->napi); 1443 } 1444 1445 enetc_disable_interrupts(priv); 1446 enetc_clear_bdrs(priv); 1447 1448 enetc_free_rxtx_rings(priv); 1449 enetc_free_rx_resources(priv); 1450 enetc_free_tx_resources(priv); 1451 enetc_free_irqs(priv); 1452 1453 return 0; 1454 } 1455 1456 static int enetc_setup_tc_mqprio(struct net_device *ndev, void *type_data) 1457 { 1458 struct enetc_ndev_priv *priv = netdev_priv(ndev); 1459 struct tc_mqprio_qopt *mqprio = type_data; 1460 struct enetc_bdr *tx_ring; 1461 u8 num_tc; 1462 int i; 1463 1464 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS; 1465 num_tc = mqprio->num_tc; 1466 1467 if (!num_tc) { 1468 netdev_reset_tc(ndev); 1469 netif_set_real_num_tx_queues(ndev, priv->num_tx_rings); 1470 1471 /* Reset all ring priorities to 0 */ 1472 for (i = 0; i < priv->num_tx_rings; i++) { 1473 tx_ring = priv->tx_ring[i]; 1474 enetc_set_bdr_prio(&priv->si->hw, tx_ring->index, 0); 1475 } 1476 1477 return 0; 1478 } 1479 1480 /* Check if we have enough BD rings available to accommodate all TCs */ 1481 if (num_tc > priv->num_tx_rings) { 1482 netdev_err(ndev, "Max %d traffic classes supported\n", 1483 priv->num_tx_rings); 1484 return -EINVAL; 1485 } 1486 1487 /* For the moment, we use only one BD ring per TC. 1488 * 1489 * Configure num_tc BD rings with increasing priorities. 1490 */ 1491 for (i = 0; i < num_tc; i++) { 1492 tx_ring = priv->tx_ring[i]; 1493 enetc_set_bdr_prio(&priv->si->hw, tx_ring->index, i); 1494 } 1495 1496 /* Reset the number of netdev queues based on the TC count */ 1497 netif_set_real_num_tx_queues(ndev, num_tc); 1498 1499 netdev_set_num_tc(ndev, num_tc); 1500 1501 /* Each TC is associated with one netdev queue */ 1502 for (i = 0; i < num_tc; i++) 1503 netdev_set_tc_queue(ndev, i, 1, i); 1504 1505 return 0; 1506 } 1507 1508 int enetc_setup_tc(struct net_device *ndev, enum tc_setup_type type, 1509 void *type_data) 1510 { 1511 switch (type) { 1512 case TC_SETUP_QDISC_MQPRIO: 1513 return enetc_setup_tc_mqprio(ndev, type_data); 1514 case TC_SETUP_QDISC_TAPRIO: 1515 return enetc_setup_tc_taprio(ndev, type_data); 1516 case TC_SETUP_QDISC_CBS: 1517 return enetc_setup_tc_cbs(ndev, type_data); 1518 case TC_SETUP_QDISC_ETF: 1519 return enetc_setup_tc_txtime(ndev, type_data); 1520 default: 1521 return -EOPNOTSUPP; 1522 } 1523 } 1524 1525 struct net_device_stats *enetc_get_stats(struct net_device *ndev) 1526 { 1527 struct enetc_ndev_priv *priv = netdev_priv(ndev); 1528 struct net_device_stats *stats = &ndev->stats; 1529 unsigned long packets = 0, bytes = 0; 1530 int i; 1531 1532 for (i = 0; i < priv->num_rx_rings; i++) { 1533 packets += priv->rx_ring[i]->stats.packets; 1534 bytes += priv->rx_ring[i]->stats.bytes; 1535 } 1536 1537 stats->rx_packets = packets; 1538 stats->rx_bytes = bytes; 1539 bytes = 0; 1540 packets = 0; 1541 1542 for (i = 0; i < priv->num_tx_rings; i++) { 1543 packets += priv->tx_ring[i]->stats.packets; 1544 bytes += priv->tx_ring[i]->stats.bytes; 1545 } 1546 1547 stats->tx_packets = packets; 1548 stats->tx_bytes = bytes; 1549 1550 return stats; 1551 } 1552 1553 static int enetc_set_rss(struct net_device *ndev, int en) 1554 { 1555 struct enetc_ndev_priv *priv = netdev_priv(ndev); 1556 struct enetc_hw *hw = &priv->si->hw; 1557 u32 reg; 1558 1559 enetc_wr(hw, ENETC_SIRBGCR, priv->num_rx_rings); 1560 1561 reg = enetc_rd(hw, ENETC_SIMR); 1562 reg &= ~ENETC_SIMR_RSSE; 1563 reg |= (en) ? ENETC_SIMR_RSSE : 0; 1564 enetc_wr(hw, ENETC_SIMR, reg); 1565 1566 return 0; 1567 } 1568 1569 int enetc_set_features(struct net_device *ndev, 1570 netdev_features_t features) 1571 { 1572 netdev_features_t changed = ndev->features ^ features; 1573 1574 if (changed & NETIF_F_RXHASH) 1575 enetc_set_rss(ndev, !!(features & NETIF_F_RXHASH)); 1576 1577 return 0; 1578 } 1579 1580 #ifdef CONFIG_FSL_ENETC_HW_TIMESTAMPING 1581 static int enetc_hwtstamp_set(struct net_device *ndev, struct ifreq *ifr) 1582 { 1583 struct enetc_ndev_priv *priv = netdev_priv(ndev); 1584 struct hwtstamp_config config; 1585 1586 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 1587 return -EFAULT; 1588 1589 switch (config.tx_type) { 1590 case HWTSTAMP_TX_OFF: 1591 priv->active_offloads &= ~ENETC_F_TX_TSTAMP; 1592 break; 1593 case HWTSTAMP_TX_ON: 1594 priv->active_offloads |= ENETC_F_TX_TSTAMP; 1595 break; 1596 default: 1597 return -ERANGE; 1598 } 1599 1600 switch (config.rx_filter) { 1601 case HWTSTAMP_FILTER_NONE: 1602 priv->active_offloads &= ~ENETC_F_RX_TSTAMP; 1603 break; 1604 default: 1605 priv->active_offloads |= ENETC_F_RX_TSTAMP; 1606 config.rx_filter = HWTSTAMP_FILTER_ALL; 1607 } 1608 1609 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? 1610 -EFAULT : 0; 1611 } 1612 1613 static int enetc_hwtstamp_get(struct net_device *ndev, struct ifreq *ifr) 1614 { 1615 struct enetc_ndev_priv *priv = netdev_priv(ndev); 1616 struct hwtstamp_config config; 1617 1618 config.flags = 0; 1619 1620 if (priv->active_offloads & ENETC_F_TX_TSTAMP) 1621 config.tx_type = HWTSTAMP_TX_ON; 1622 else 1623 config.tx_type = HWTSTAMP_TX_OFF; 1624 1625 config.rx_filter = (priv->active_offloads & ENETC_F_RX_TSTAMP) ? 1626 HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE; 1627 1628 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? 1629 -EFAULT : 0; 1630 } 1631 #endif 1632 1633 int enetc_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) 1634 { 1635 #ifdef CONFIG_FSL_ENETC_HW_TIMESTAMPING 1636 if (cmd == SIOCSHWTSTAMP) 1637 return enetc_hwtstamp_set(ndev, rq); 1638 if (cmd == SIOCGHWTSTAMP) 1639 return enetc_hwtstamp_get(ndev, rq); 1640 #endif 1641 1642 if (!ndev->phydev) 1643 return -EOPNOTSUPP; 1644 return phy_mii_ioctl(ndev->phydev, rq, cmd); 1645 } 1646 1647 int enetc_alloc_msix(struct enetc_ndev_priv *priv) 1648 { 1649 struct pci_dev *pdev = priv->si->pdev; 1650 int size, v_tx_rings; 1651 int i, n, err, nvec; 1652 1653 nvec = ENETC_BDR_INT_BASE_IDX + priv->bdr_int_num; 1654 /* allocate MSIX for both messaging and Rx/Tx interrupts */ 1655 n = pci_alloc_irq_vectors(pdev, nvec, nvec, PCI_IRQ_MSIX); 1656 1657 if (n < 0) 1658 return n; 1659 1660 if (n != nvec) 1661 return -EPERM; 1662 1663 /* # of tx rings per int vector */ 1664 v_tx_rings = priv->num_tx_rings / priv->bdr_int_num; 1665 size = sizeof(struct enetc_int_vector) + 1666 sizeof(struct enetc_bdr) * v_tx_rings; 1667 1668 for (i = 0; i < priv->bdr_int_num; i++) { 1669 struct enetc_int_vector *v; 1670 struct enetc_bdr *bdr; 1671 int j; 1672 1673 v = kzalloc(size, GFP_KERNEL); 1674 if (!v) { 1675 err = -ENOMEM; 1676 goto fail; 1677 } 1678 1679 priv->int_vector[i] = v; 1680 1681 netif_napi_add(priv->ndev, &v->napi, enetc_poll, 1682 NAPI_POLL_WEIGHT); 1683 v->count_tx_rings = v_tx_rings; 1684 1685 for (j = 0; j < v_tx_rings; j++) { 1686 int idx; 1687 1688 /* default tx ring mapping policy */ 1689 if (priv->bdr_int_num == ENETC_MAX_BDR_INT) 1690 idx = 2 * j + i; /* 2 CPUs */ 1691 else 1692 idx = j + i * v_tx_rings; /* default */ 1693 1694 __set_bit(idx, &v->tx_rings_map); 1695 bdr = &v->tx_ring[j]; 1696 bdr->index = idx; 1697 bdr->ndev = priv->ndev; 1698 bdr->dev = priv->dev; 1699 bdr->bd_count = priv->tx_bd_count; 1700 priv->tx_ring[idx] = bdr; 1701 } 1702 1703 bdr = &v->rx_ring; 1704 bdr->index = i; 1705 bdr->ndev = priv->ndev; 1706 bdr->dev = priv->dev; 1707 bdr->bd_count = priv->rx_bd_count; 1708 priv->rx_ring[i] = bdr; 1709 } 1710 1711 return 0; 1712 1713 fail: 1714 while (i--) { 1715 netif_napi_del(&priv->int_vector[i]->napi); 1716 kfree(priv->int_vector[i]); 1717 } 1718 1719 pci_free_irq_vectors(pdev); 1720 1721 return err; 1722 } 1723 1724 void enetc_free_msix(struct enetc_ndev_priv *priv) 1725 { 1726 int i; 1727 1728 for (i = 0; i < priv->bdr_int_num; i++) { 1729 struct enetc_int_vector *v = priv->int_vector[i]; 1730 1731 netif_napi_del(&v->napi); 1732 } 1733 1734 for (i = 0; i < priv->num_rx_rings; i++) 1735 priv->rx_ring[i] = NULL; 1736 1737 for (i = 0; i < priv->num_tx_rings; i++) 1738 priv->tx_ring[i] = NULL; 1739 1740 for (i = 0; i < priv->bdr_int_num; i++) { 1741 kfree(priv->int_vector[i]); 1742 priv->int_vector[i] = NULL; 1743 } 1744 1745 /* disable all MSIX for this device */ 1746 pci_free_irq_vectors(priv->si->pdev); 1747 } 1748 1749 static void enetc_kfree_si(struct enetc_si *si) 1750 { 1751 char *p = (char *)si - si->pad; 1752 1753 kfree(p); 1754 } 1755 1756 static void enetc_detect_errata(struct enetc_si *si) 1757 { 1758 if (si->pdev->revision == ENETC_REV1) 1759 si->errata = ENETC_ERR_TXCSUM | ENETC_ERR_VLAN_ISOL | 1760 ENETC_ERR_UCMCSWP; 1761 } 1762 1763 int enetc_pci_probe(struct pci_dev *pdev, const char *name, int sizeof_priv) 1764 { 1765 struct enetc_si *si, *p; 1766 struct enetc_hw *hw; 1767 size_t alloc_size; 1768 int err, len; 1769 1770 pcie_flr(pdev); 1771 err = pci_enable_device_mem(pdev); 1772 if (err) { 1773 dev_err(&pdev->dev, "device enable failed\n"); 1774 return err; 1775 } 1776 1777 /* set up for high or low dma */ 1778 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 1779 if (err) { 1780 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 1781 if (err) { 1782 dev_err(&pdev->dev, 1783 "DMA configuration failed: 0x%x\n", err); 1784 goto err_dma; 1785 } 1786 } 1787 1788 err = pci_request_mem_regions(pdev, name); 1789 if (err) { 1790 dev_err(&pdev->dev, "pci_request_regions failed err=%d\n", err); 1791 goto err_pci_mem_reg; 1792 } 1793 1794 pci_set_master(pdev); 1795 1796 alloc_size = sizeof(struct enetc_si); 1797 if (sizeof_priv) { 1798 /* align priv to 32B */ 1799 alloc_size = ALIGN(alloc_size, ENETC_SI_ALIGN); 1800 alloc_size += sizeof_priv; 1801 } 1802 /* force 32B alignment for enetc_si */ 1803 alloc_size += ENETC_SI_ALIGN - 1; 1804 1805 p = kzalloc(alloc_size, GFP_KERNEL); 1806 if (!p) { 1807 err = -ENOMEM; 1808 goto err_alloc_si; 1809 } 1810 1811 si = PTR_ALIGN(p, ENETC_SI_ALIGN); 1812 si->pad = (char *)si - (char *)p; 1813 1814 pci_set_drvdata(pdev, si); 1815 si->pdev = pdev; 1816 hw = &si->hw; 1817 1818 len = pci_resource_len(pdev, ENETC_BAR_REGS); 1819 hw->reg = ioremap(pci_resource_start(pdev, ENETC_BAR_REGS), len); 1820 if (!hw->reg) { 1821 err = -ENXIO; 1822 dev_err(&pdev->dev, "ioremap() failed\n"); 1823 goto err_ioremap; 1824 } 1825 if (len > ENETC_PORT_BASE) 1826 hw->port = hw->reg + ENETC_PORT_BASE; 1827 if (len > ENETC_GLOBAL_BASE) 1828 hw->global = hw->reg + ENETC_GLOBAL_BASE; 1829 1830 enetc_detect_errata(si); 1831 1832 return 0; 1833 1834 err_ioremap: 1835 enetc_kfree_si(si); 1836 err_alloc_si: 1837 pci_release_mem_regions(pdev); 1838 err_pci_mem_reg: 1839 err_dma: 1840 pci_disable_device(pdev); 1841 1842 return err; 1843 } 1844 1845 void enetc_pci_remove(struct pci_dev *pdev) 1846 { 1847 struct enetc_si *si = pci_get_drvdata(pdev); 1848 struct enetc_hw *hw = &si->hw; 1849 1850 iounmap(hw->reg); 1851 enetc_kfree_si(si); 1852 pci_release_mem_regions(pdev); 1853 pci_disable_device(pdev); 1854 } 1855