1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2 /* Copyright 2017-2019 NXP */ 3 4 #include "enetc.h" 5 #include <linux/bpf_trace.h> 6 #include <linux/tcp.h> 7 #include <linux/udp.h> 8 #include <linux/vmalloc.h> 9 #include <linux/ptp_classify.h> 10 #include <net/ip6_checksum.h> 11 #include <net/pkt_sched.h> 12 #include <net/tso.h> 13 14 static int enetc_num_stack_tx_queues(struct enetc_ndev_priv *priv) 15 { 16 int num_tx_rings = priv->num_tx_rings; 17 int i; 18 19 for (i = 0; i < priv->num_rx_rings; i++) 20 if (priv->rx_ring[i]->xdp.prog) 21 return num_tx_rings - num_possible_cpus(); 22 23 return num_tx_rings; 24 } 25 26 static struct enetc_bdr *enetc_rx_ring_from_xdp_tx_ring(struct enetc_ndev_priv *priv, 27 struct enetc_bdr *tx_ring) 28 { 29 int index = &priv->tx_ring[tx_ring->index] - priv->xdp_tx_ring; 30 31 return priv->rx_ring[index]; 32 } 33 34 static struct sk_buff *enetc_tx_swbd_get_skb(struct enetc_tx_swbd *tx_swbd) 35 { 36 if (tx_swbd->is_xdp_tx || tx_swbd->is_xdp_redirect) 37 return NULL; 38 39 return tx_swbd->skb; 40 } 41 42 static struct xdp_frame * 43 enetc_tx_swbd_get_xdp_frame(struct enetc_tx_swbd *tx_swbd) 44 { 45 if (tx_swbd->is_xdp_redirect) 46 return tx_swbd->xdp_frame; 47 48 return NULL; 49 } 50 51 static void enetc_unmap_tx_buff(struct enetc_bdr *tx_ring, 52 struct enetc_tx_swbd *tx_swbd) 53 { 54 /* For XDP_TX, pages come from RX, whereas for the other contexts where 55 * we have is_dma_page_set, those come from skb_frag_dma_map. We need 56 * to match the DMA mapping length, so we need to differentiate those. 57 */ 58 if (tx_swbd->is_dma_page) 59 dma_unmap_page(tx_ring->dev, tx_swbd->dma, 60 tx_swbd->is_xdp_tx ? PAGE_SIZE : tx_swbd->len, 61 tx_swbd->dir); 62 else 63 dma_unmap_single(tx_ring->dev, tx_swbd->dma, 64 tx_swbd->len, tx_swbd->dir); 65 tx_swbd->dma = 0; 66 } 67 68 static void enetc_free_tx_frame(struct enetc_bdr *tx_ring, 69 struct enetc_tx_swbd *tx_swbd) 70 { 71 struct xdp_frame *xdp_frame = enetc_tx_swbd_get_xdp_frame(tx_swbd); 72 struct sk_buff *skb = enetc_tx_swbd_get_skb(tx_swbd); 73 74 if (tx_swbd->dma) 75 enetc_unmap_tx_buff(tx_ring, tx_swbd); 76 77 if (xdp_frame) { 78 xdp_return_frame(tx_swbd->xdp_frame); 79 tx_swbd->xdp_frame = NULL; 80 } else if (skb) { 81 dev_kfree_skb_any(skb); 82 tx_swbd->skb = NULL; 83 } 84 } 85 86 /* Let H/W know BD ring has been updated */ 87 static void enetc_update_tx_ring_tail(struct enetc_bdr *tx_ring) 88 { 89 /* includes wmb() */ 90 enetc_wr_reg_hot(tx_ring->tpir, tx_ring->next_to_use); 91 } 92 93 static int enetc_ptp_parse(struct sk_buff *skb, u8 *udp, 94 u8 *msgtype, u8 *twostep, 95 u16 *correction_offset, u16 *body_offset) 96 { 97 unsigned int ptp_class; 98 struct ptp_header *hdr; 99 unsigned int type; 100 u8 *base; 101 102 ptp_class = ptp_classify_raw(skb); 103 if (ptp_class == PTP_CLASS_NONE) 104 return -EINVAL; 105 106 hdr = ptp_parse_header(skb, ptp_class); 107 if (!hdr) 108 return -EINVAL; 109 110 type = ptp_class & PTP_CLASS_PMASK; 111 if (type == PTP_CLASS_IPV4 || type == PTP_CLASS_IPV6) 112 *udp = 1; 113 else 114 *udp = 0; 115 116 *msgtype = ptp_get_msgtype(hdr, ptp_class); 117 *twostep = hdr->flag_field[0] & 0x2; 118 119 base = skb_mac_header(skb); 120 *correction_offset = (u8 *)&hdr->correction - base; 121 *body_offset = (u8 *)hdr + sizeof(struct ptp_header) - base; 122 123 return 0; 124 } 125 126 static int enetc_map_tx_buffs(struct enetc_bdr *tx_ring, struct sk_buff *skb) 127 { 128 bool do_vlan, do_onestep_tstamp = false, do_twostep_tstamp = false; 129 struct enetc_ndev_priv *priv = netdev_priv(tx_ring->ndev); 130 struct enetc_hw *hw = &priv->si->hw; 131 struct enetc_tx_swbd *tx_swbd; 132 int len = skb_headlen(skb); 133 union enetc_tx_bd temp_bd; 134 u8 msgtype, twostep, udp; 135 union enetc_tx_bd *txbd; 136 u16 offset1, offset2; 137 int i, count = 0; 138 skb_frag_t *frag; 139 unsigned int f; 140 dma_addr_t dma; 141 u8 flags = 0; 142 143 i = tx_ring->next_to_use; 144 txbd = ENETC_TXBD(*tx_ring, i); 145 prefetchw(txbd); 146 147 dma = dma_map_single(tx_ring->dev, skb->data, len, DMA_TO_DEVICE); 148 if (unlikely(dma_mapping_error(tx_ring->dev, dma))) 149 goto dma_err; 150 151 temp_bd.addr = cpu_to_le64(dma); 152 temp_bd.buf_len = cpu_to_le16(len); 153 temp_bd.lstatus = 0; 154 155 tx_swbd = &tx_ring->tx_swbd[i]; 156 tx_swbd->dma = dma; 157 tx_swbd->len = len; 158 tx_swbd->is_dma_page = 0; 159 tx_swbd->dir = DMA_TO_DEVICE; 160 count++; 161 162 do_vlan = skb_vlan_tag_present(skb); 163 if (skb->cb[0] & ENETC_F_TX_ONESTEP_SYNC_TSTAMP) { 164 if (enetc_ptp_parse(skb, &udp, &msgtype, &twostep, &offset1, 165 &offset2) || 166 msgtype != PTP_MSGTYPE_SYNC || twostep) 167 WARN_ONCE(1, "Bad packet for one-step timestamping\n"); 168 else 169 do_onestep_tstamp = true; 170 } else if (skb->cb[0] & ENETC_F_TX_TSTAMP) { 171 do_twostep_tstamp = true; 172 } 173 174 tx_swbd->do_twostep_tstamp = do_twostep_tstamp; 175 tx_swbd->check_wb = tx_swbd->do_twostep_tstamp; 176 177 if (do_vlan || do_onestep_tstamp || do_twostep_tstamp) 178 flags |= ENETC_TXBD_FLAGS_EX; 179 180 if (tx_ring->tsd_enable) 181 flags |= ENETC_TXBD_FLAGS_TSE | ENETC_TXBD_FLAGS_TXSTART; 182 183 /* first BD needs frm_len and offload flags set */ 184 temp_bd.frm_len = cpu_to_le16(skb->len); 185 temp_bd.flags = flags; 186 187 if (flags & ENETC_TXBD_FLAGS_TSE) 188 temp_bd.txstart = enetc_txbd_set_tx_start(skb->skb_mstamp_ns, 189 flags); 190 191 if (flags & ENETC_TXBD_FLAGS_EX) { 192 u8 e_flags = 0; 193 *txbd = temp_bd; 194 enetc_clear_tx_bd(&temp_bd); 195 196 /* add extension BD for VLAN and/or timestamping */ 197 flags = 0; 198 tx_swbd++; 199 txbd++; 200 i++; 201 if (unlikely(i == tx_ring->bd_count)) { 202 i = 0; 203 tx_swbd = tx_ring->tx_swbd; 204 txbd = ENETC_TXBD(*tx_ring, 0); 205 } 206 prefetchw(txbd); 207 208 if (do_vlan) { 209 temp_bd.ext.vid = cpu_to_le16(skb_vlan_tag_get(skb)); 210 temp_bd.ext.tpid = 0; /* < C-TAG */ 211 e_flags |= ENETC_TXBD_E_FLAGS_VLAN_INS; 212 } 213 214 if (do_onestep_tstamp) { 215 u32 lo, hi, val; 216 u64 sec, nsec; 217 u8 *data; 218 219 lo = enetc_rd_hot(hw, ENETC_SICTR0); 220 hi = enetc_rd_hot(hw, ENETC_SICTR1); 221 sec = (u64)hi << 32 | lo; 222 nsec = do_div(sec, 1000000000); 223 224 /* Configure extension BD */ 225 temp_bd.ext.tstamp = cpu_to_le32(lo & 0x3fffffff); 226 e_flags |= ENETC_TXBD_E_FLAGS_ONE_STEP_PTP; 227 228 /* Update originTimestamp field of Sync packet 229 * - 48 bits seconds field 230 * - 32 bits nanseconds field 231 */ 232 data = skb_mac_header(skb); 233 *(__be16 *)(data + offset2) = 234 htons((sec >> 32) & 0xffff); 235 *(__be32 *)(data + offset2 + 2) = 236 htonl(sec & 0xffffffff); 237 *(__be32 *)(data + offset2 + 6) = htonl(nsec); 238 239 /* Configure single-step register */ 240 val = ENETC_PM0_SINGLE_STEP_EN; 241 val |= ENETC_SET_SINGLE_STEP_OFFSET(offset1); 242 if (udp) 243 val |= ENETC_PM0_SINGLE_STEP_CH; 244 245 enetc_port_wr(hw, ENETC_PM0_SINGLE_STEP, val); 246 enetc_port_wr(hw, ENETC_PM1_SINGLE_STEP, val); 247 } else if (do_twostep_tstamp) { 248 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 249 e_flags |= ENETC_TXBD_E_FLAGS_TWO_STEP_PTP; 250 } 251 252 temp_bd.ext.e_flags = e_flags; 253 count++; 254 } 255 256 frag = &skb_shinfo(skb)->frags[0]; 257 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++, frag++) { 258 len = skb_frag_size(frag); 259 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, len, 260 DMA_TO_DEVICE); 261 if (dma_mapping_error(tx_ring->dev, dma)) 262 goto dma_err; 263 264 *txbd = temp_bd; 265 enetc_clear_tx_bd(&temp_bd); 266 267 flags = 0; 268 tx_swbd++; 269 txbd++; 270 i++; 271 if (unlikely(i == tx_ring->bd_count)) { 272 i = 0; 273 tx_swbd = tx_ring->tx_swbd; 274 txbd = ENETC_TXBD(*tx_ring, 0); 275 } 276 prefetchw(txbd); 277 278 temp_bd.addr = cpu_to_le64(dma); 279 temp_bd.buf_len = cpu_to_le16(len); 280 281 tx_swbd->dma = dma; 282 tx_swbd->len = len; 283 tx_swbd->is_dma_page = 1; 284 tx_swbd->dir = DMA_TO_DEVICE; 285 count++; 286 } 287 288 /* last BD needs 'F' bit set */ 289 flags |= ENETC_TXBD_FLAGS_F; 290 temp_bd.flags = flags; 291 *txbd = temp_bd; 292 293 tx_ring->tx_swbd[i].is_eof = true; 294 tx_ring->tx_swbd[i].skb = skb; 295 296 enetc_bdr_idx_inc(tx_ring, &i); 297 tx_ring->next_to_use = i; 298 299 skb_tx_timestamp(skb); 300 301 enetc_update_tx_ring_tail(tx_ring); 302 303 return count; 304 305 dma_err: 306 dev_err(tx_ring->dev, "DMA map error"); 307 308 do { 309 tx_swbd = &tx_ring->tx_swbd[i]; 310 enetc_free_tx_frame(tx_ring, tx_swbd); 311 if (i == 0) 312 i = tx_ring->bd_count; 313 i--; 314 } while (count--); 315 316 return 0; 317 } 318 319 static void enetc_map_tx_tso_hdr(struct enetc_bdr *tx_ring, struct sk_buff *skb, 320 struct enetc_tx_swbd *tx_swbd, 321 union enetc_tx_bd *txbd, int *i, int hdr_len, 322 int data_len) 323 { 324 union enetc_tx_bd txbd_tmp; 325 u8 flags = 0, e_flags = 0; 326 dma_addr_t addr; 327 328 enetc_clear_tx_bd(&txbd_tmp); 329 addr = tx_ring->tso_headers_dma + *i * TSO_HEADER_SIZE; 330 331 if (skb_vlan_tag_present(skb)) 332 flags |= ENETC_TXBD_FLAGS_EX; 333 334 txbd_tmp.addr = cpu_to_le64(addr); 335 txbd_tmp.buf_len = cpu_to_le16(hdr_len); 336 337 /* first BD needs frm_len and offload flags set */ 338 txbd_tmp.frm_len = cpu_to_le16(hdr_len + data_len); 339 txbd_tmp.flags = flags; 340 341 /* For the TSO header we do not set the dma address since we do not 342 * want it unmapped when we do cleanup. We still set len so that we 343 * count the bytes sent. 344 */ 345 tx_swbd->len = hdr_len; 346 tx_swbd->do_twostep_tstamp = false; 347 tx_swbd->check_wb = false; 348 349 /* Actually write the header in the BD */ 350 *txbd = txbd_tmp; 351 352 /* Add extension BD for VLAN */ 353 if (flags & ENETC_TXBD_FLAGS_EX) { 354 /* Get the next BD */ 355 enetc_bdr_idx_inc(tx_ring, i); 356 txbd = ENETC_TXBD(*tx_ring, *i); 357 tx_swbd = &tx_ring->tx_swbd[*i]; 358 prefetchw(txbd); 359 360 /* Setup the VLAN fields */ 361 enetc_clear_tx_bd(&txbd_tmp); 362 txbd_tmp.ext.vid = cpu_to_le16(skb_vlan_tag_get(skb)); 363 txbd_tmp.ext.tpid = 0; /* < C-TAG */ 364 e_flags |= ENETC_TXBD_E_FLAGS_VLAN_INS; 365 366 /* Write the BD */ 367 txbd_tmp.ext.e_flags = e_flags; 368 *txbd = txbd_tmp; 369 } 370 } 371 372 static int enetc_map_tx_tso_data(struct enetc_bdr *tx_ring, struct sk_buff *skb, 373 struct enetc_tx_swbd *tx_swbd, 374 union enetc_tx_bd *txbd, char *data, 375 int size, bool last_bd) 376 { 377 union enetc_tx_bd txbd_tmp; 378 dma_addr_t addr; 379 u8 flags = 0; 380 381 enetc_clear_tx_bd(&txbd_tmp); 382 383 addr = dma_map_single(tx_ring->dev, data, size, DMA_TO_DEVICE); 384 if (unlikely(dma_mapping_error(tx_ring->dev, addr))) { 385 netdev_err(tx_ring->ndev, "DMA map error\n"); 386 return -ENOMEM; 387 } 388 389 if (last_bd) { 390 flags |= ENETC_TXBD_FLAGS_F; 391 tx_swbd->is_eof = 1; 392 } 393 394 txbd_tmp.addr = cpu_to_le64(addr); 395 txbd_tmp.buf_len = cpu_to_le16(size); 396 txbd_tmp.flags = flags; 397 398 tx_swbd->dma = addr; 399 tx_swbd->len = size; 400 tx_swbd->dir = DMA_TO_DEVICE; 401 402 *txbd = txbd_tmp; 403 404 return 0; 405 } 406 407 static __wsum enetc_tso_hdr_csum(struct tso_t *tso, struct sk_buff *skb, 408 char *hdr, int hdr_len, int *l4_hdr_len) 409 { 410 char *l4_hdr = hdr + skb_transport_offset(skb); 411 int mac_hdr_len = skb_network_offset(skb); 412 413 if (tso->tlen != sizeof(struct udphdr)) { 414 struct tcphdr *tcph = (struct tcphdr *)(l4_hdr); 415 416 tcph->check = 0; 417 } else { 418 struct udphdr *udph = (struct udphdr *)(l4_hdr); 419 420 udph->check = 0; 421 } 422 423 /* Compute the IP checksum. This is necessary since tso_build_hdr() 424 * already incremented the IP ID field. 425 */ 426 if (!tso->ipv6) { 427 struct iphdr *iph = (void *)(hdr + mac_hdr_len); 428 429 iph->check = 0; 430 iph->check = ip_fast_csum((unsigned char *)iph, iph->ihl); 431 } 432 433 /* Compute the checksum over the L4 header. */ 434 *l4_hdr_len = hdr_len - skb_transport_offset(skb); 435 return csum_partial(l4_hdr, *l4_hdr_len, 0); 436 } 437 438 static void enetc_tso_complete_csum(struct enetc_bdr *tx_ring, struct tso_t *tso, 439 struct sk_buff *skb, char *hdr, int len, 440 __wsum sum) 441 { 442 char *l4_hdr = hdr + skb_transport_offset(skb); 443 __sum16 csum_final; 444 445 /* Complete the L4 checksum by appending the pseudo-header to the 446 * already computed checksum. 447 */ 448 if (!tso->ipv6) 449 csum_final = csum_tcpudp_magic(ip_hdr(skb)->saddr, 450 ip_hdr(skb)->daddr, 451 len, ip_hdr(skb)->protocol, sum); 452 else 453 csum_final = csum_ipv6_magic(&ipv6_hdr(skb)->saddr, 454 &ipv6_hdr(skb)->daddr, 455 len, ipv6_hdr(skb)->nexthdr, sum); 456 457 if (tso->tlen != sizeof(struct udphdr)) { 458 struct tcphdr *tcph = (struct tcphdr *)(l4_hdr); 459 460 tcph->check = csum_final; 461 } else { 462 struct udphdr *udph = (struct udphdr *)(l4_hdr); 463 464 udph->check = csum_final; 465 } 466 } 467 468 static int enetc_map_tx_tso_buffs(struct enetc_bdr *tx_ring, struct sk_buff *skb) 469 { 470 int hdr_len, total_len, data_len; 471 struct enetc_tx_swbd *tx_swbd; 472 union enetc_tx_bd *txbd; 473 struct tso_t tso; 474 __wsum csum, csum2; 475 int count = 0, pos; 476 int err, i, bd_data_num; 477 478 /* Initialize the TSO handler, and prepare the first payload */ 479 hdr_len = tso_start(skb, &tso); 480 total_len = skb->len - hdr_len; 481 i = tx_ring->next_to_use; 482 483 while (total_len > 0) { 484 char *hdr; 485 486 /* Get the BD */ 487 txbd = ENETC_TXBD(*tx_ring, i); 488 tx_swbd = &tx_ring->tx_swbd[i]; 489 prefetchw(txbd); 490 491 /* Determine the length of this packet */ 492 data_len = min_t(int, skb_shinfo(skb)->gso_size, total_len); 493 total_len -= data_len; 494 495 /* prepare packet headers: MAC + IP + TCP */ 496 hdr = tx_ring->tso_headers + i * TSO_HEADER_SIZE; 497 tso_build_hdr(skb, hdr, &tso, data_len, total_len == 0); 498 499 /* compute the csum over the L4 header */ 500 csum = enetc_tso_hdr_csum(&tso, skb, hdr, hdr_len, &pos); 501 enetc_map_tx_tso_hdr(tx_ring, skb, tx_swbd, txbd, &i, hdr_len, data_len); 502 bd_data_num = 0; 503 count++; 504 505 while (data_len > 0) { 506 int size; 507 508 size = min_t(int, tso.size, data_len); 509 510 /* Advance the index in the BDR */ 511 enetc_bdr_idx_inc(tx_ring, &i); 512 txbd = ENETC_TXBD(*tx_ring, i); 513 tx_swbd = &tx_ring->tx_swbd[i]; 514 prefetchw(txbd); 515 516 /* Compute the checksum over this segment of data and 517 * add it to the csum already computed (over the L4 518 * header and possible other data segments). 519 */ 520 csum2 = csum_partial(tso.data, size, 0); 521 csum = csum_block_add(csum, csum2, pos); 522 pos += size; 523 524 err = enetc_map_tx_tso_data(tx_ring, skb, tx_swbd, txbd, 525 tso.data, size, 526 size == data_len); 527 if (err) 528 goto err_map_data; 529 530 data_len -= size; 531 count++; 532 bd_data_num++; 533 tso_build_data(skb, &tso, size); 534 535 if (unlikely(bd_data_num >= ENETC_MAX_SKB_FRAGS && data_len)) 536 goto err_chained_bd; 537 } 538 539 enetc_tso_complete_csum(tx_ring, &tso, skb, hdr, pos, csum); 540 541 if (total_len == 0) 542 tx_swbd->skb = skb; 543 544 /* Go to the next BD */ 545 enetc_bdr_idx_inc(tx_ring, &i); 546 } 547 548 tx_ring->next_to_use = i; 549 enetc_update_tx_ring_tail(tx_ring); 550 551 return count; 552 553 err_map_data: 554 dev_err(tx_ring->dev, "DMA map error"); 555 556 err_chained_bd: 557 do { 558 tx_swbd = &tx_ring->tx_swbd[i]; 559 enetc_free_tx_frame(tx_ring, tx_swbd); 560 if (i == 0) 561 i = tx_ring->bd_count; 562 i--; 563 } while (count--); 564 565 return 0; 566 } 567 568 static netdev_tx_t enetc_start_xmit(struct sk_buff *skb, 569 struct net_device *ndev) 570 { 571 struct enetc_ndev_priv *priv = netdev_priv(ndev); 572 struct enetc_bdr *tx_ring; 573 int count, err; 574 575 /* Queue one-step Sync packet if already locked */ 576 if (skb->cb[0] & ENETC_F_TX_ONESTEP_SYNC_TSTAMP) { 577 if (test_and_set_bit_lock(ENETC_TX_ONESTEP_TSTAMP_IN_PROGRESS, 578 &priv->flags)) { 579 skb_queue_tail(&priv->tx_skbs, skb); 580 return NETDEV_TX_OK; 581 } 582 } 583 584 tx_ring = priv->tx_ring[skb->queue_mapping]; 585 586 if (skb_is_gso(skb)) { 587 if (enetc_bd_unused(tx_ring) < tso_count_descs(skb)) { 588 netif_stop_subqueue(ndev, tx_ring->index); 589 return NETDEV_TX_BUSY; 590 } 591 592 enetc_lock_mdio(); 593 count = enetc_map_tx_tso_buffs(tx_ring, skb); 594 enetc_unlock_mdio(); 595 } else { 596 if (unlikely(skb_shinfo(skb)->nr_frags > ENETC_MAX_SKB_FRAGS)) 597 if (unlikely(skb_linearize(skb))) 598 goto drop_packet_err; 599 600 count = skb_shinfo(skb)->nr_frags + 1; /* fragments + head */ 601 if (enetc_bd_unused(tx_ring) < ENETC_TXBDS_NEEDED(count)) { 602 netif_stop_subqueue(ndev, tx_ring->index); 603 return NETDEV_TX_BUSY; 604 } 605 606 if (skb->ip_summed == CHECKSUM_PARTIAL) { 607 err = skb_checksum_help(skb); 608 if (err) 609 goto drop_packet_err; 610 } 611 enetc_lock_mdio(); 612 count = enetc_map_tx_buffs(tx_ring, skb); 613 enetc_unlock_mdio(); 614 } 615 616 if (unlikely(!count)) 617 goto drop_packet_err; 618 619 if (enetc_bd_unused(tx_ring) < ENETC_TXBDS_MAX_NEEDED) 620 netif_stop_subqueue(ndev, tx_ring->index); 621 622 return NETDEV_TX_OK; 623 624 drop_packet_err: 625 dev_kfree_skb_any(skb); 626 return NETDEV_TX_OK; 627 } 628 629 netdev_tx_t enetc_xmit(struct sk_buff *skb, struct net_device *ndev) 630 { 631 struct enetc_ndev_priv *priv = netdev_priv(ndev); 632 u8 udp, msgtype, twostep; 633 u16 offset1, offset2; 634 635 /* Mark tx timestamp type on skb->cb[0] if requires */ 636 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 637 (priv->active_offloads & ENETC_F_TX_TSTAMP_MASK)) { 638 skb->cb[0] = priv->active_offloads & ENETC_F_TX_TSTAMP_MASK; 639 } else { 640 skb->cb[0] = 0; 641 } 642 643 /* Fall back to two-step timestamp if not one-step Sync packet */ 644 if (skb->cb[0] & ENETC_F_TX_ONESTEP_SYNC_TSTAMP) { 645 if (enetc_ptp_parse(skb, &udp, &msgtype, &twostep, 646 &offset1, &offset2) || 647 msgtype != PTP_MSGTYPE_SYNC || twostep != 0) 648 skb->cb[0] = ENETC_F_TX_TSTAMP; 649 } 650 651 return enetc_start_xmit(skb, ndev); 652 } 653 654 static irqreturn_t enetc_msix(int irq, void *data) 655 { 656 struct enetc_int_vector *v = data; 657 int i; 658 659 enetc_lock_mdio(); 660 661 /* disable interrupts */ 662 enetc_wr_reg_hot(v->rbier, 0); 663 enetc_wr_reg_hot(v->ricr1, v->rx_ictt); 664 665 for_each_set_bit(i, &v->tx_rings_map, ENETC_MAX_NUM_TXQS) 666 enetc_wr_reg_hot(v->tbier_base + ENETC_BDR_OFF(i), 0); 667 668 enetc_unlock_mdio(); 669 670 napi_schedule(&v->napi); 671 672 return IRQ_HANDLED; 673 } 674 675 static void enetc_rx_dim_work(struct work_struct *w) 676 { 677 struct dim *dim = container_of(w, struct dim, work); 678 struct dim_cq_moder moder = 679 net_dim_get_rx_moderation(dim->mode, dim->profile_ix); 680 struct enetc_int_vector *v = 681 container_of(dim, struct enetc_int_vector, rx_dim); 682 683 v->rx_ictt = enetc_usecs_to_cycles(moder.usec); 684 dim->state = DIM_START_MEASURE; 685 } 686 687 static void enetc_rx_net_dim(struct enetc_int_vector *v) 688 { 689 struct dim_sample dim_sample = {}; 690 691 v->comp_cnt++; 692 693 if (!v->rx_napi_work) 694 return; 695 696 dim_update_sample(v->comp_cnt, 697 v->rx_ring.stats.packets, 698 v->rx_ring.stats.bytes, 699 &dim_sample); 700 net_dim(&v->rx_dim, dim_sample); 701 } 702 703 static int enetc_bd_ready_count(struct enetc_bdr *tx_ring, int ci) 704 { 705 int pi = enetc_rd_reg_hot(tx_ring->tcir) & ENETC_TBCIR_IDX_MASK; 706 707 return pi >= ci ? pi - ci : tx_ring->bd_count - ci + pi; 708 } 709 710 static bool enetc_page_reusable(struct page *page) 711 { 712 return (!page_is_pfmemalloc(page) && page_ref_count(page) == 1); 713 } 714 715 static void enetc_reuse_page(struct enetc_bdr *rx_ring, 716 struct enetc_rx_swbd *old) 717 { 718 struct enetc_rx_swbd *new; 719 720 new = &rx_ring->rx_swbd[rx_ring->next_to_alloc]; 721 722 /* next buf that may reuse a page */ 723 enetc_bdr_idx_inc(rx_ring, &rx_ring->next_to_alloc); 724 725 /* copy page reference */ 726 *new = *old; 727 } 728 729 static void enetc_get_tx_tstamp(struct enetc_hw *hw, union enetc_tx_bd *txbd, 730 u64 *tstamp) 731 { 732 u32 lo, hi, tstamp_lo; 733 734 lo = enetc_rd_hot(hw, ENETC_SICTR0); 735 hi = enetc_rd_hot(hw, ENETC_SICTR1); 736 tstamp_lo = le32_to_cpu(txbd->wb.tstamp); 737 if (lo <= tstamp_lo) 738 hi -= 1; 739 *tstamp = (u64)hi << 32 | tstamp_lo; 740 } 741 742 static void enetc_tstamp_tx(struct sk_buff *skb, u64 tstamp) 743 { 744 struct skb_shared_hwtstamps shhwtstamps; 745 746 if (skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) { 747 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 748 shhwtstamps.hwtstamp = ns_to_ktime(tstamp); 749 skb_txtime_consumed(skb); 750 skb_tstamp_tx(skb, &shhwtstamps); 751 } 752 } 753 754 static void enetc_recycle_xdp_tx_buff(struct enetc_bdr *tx_ring, 755 struct enetc_tx_swbd *tx_swbd) 756 { 757 struct enetc_ndev_priv *priv = netdev_priv(tx_ring->ndev); 758 struct enetc_rx_swbd rx_swbd = { 759 .dma = tx_swbd->dma, 760 .page = tx_swbd->page, 761 .page_offset = tx_swbd->page_offset, 762 .dir = tx_swbd->dir, 763 .len = tx_swbd->len, 764 }; 765 struct enetc_bdr *rx_ring; 766 767 rx_ring = enetc_rx_ring_from_xdp_tx_ring(priv, tx_ring); 768 769 if (likely(enetc_swbd_unused(rx_ring))) { 770 enetc_reuse_page(rx_ring, &rx_swbd); 771 772 /* sync for use by the device */ 773 dma_sync_single_range_for_device(rx_ring->dev, rx_swbd.dma, 774 rx_swbd.page_offset, 775 ENETC_RXB_DMA_SIZE_XDP, 776 rx_swbd.dir); 777 778 rx_ring->stats.recycles++; 779 } else { 780 /* RX ring is already full, we need to unmap and free the 781 * page, since there's nothing useful we can do with it. 782 */ 783 rx_ring->stats.recycle_failures++; 784 785 dma_unmap_page(rx_ring->dev, rx_swbd.dma, PAGE_SIZE, 786 rx_swbd.dir); 787 __free_page(rx_swbd.page); 788 } 789 790 rx_ring->xdp.xdp_tx_in_flight--; 791 } 792 793 static bool enetc_clean_tx_ring(struct enetc_bdr *tx_ring, int napi_budget) 794 { 795 struct net_device *ndev = tx_ring->ndev; 796 struct enetc_ndev_priv *priv = netdev_priv(ndev); 797 int tx_frm_cnt = 0, tx_byte_cnt = 0; 798 struct enetc_tx_swbd *tx_swbd; 799 int i, bds_to_clean; 800 bool do_twostep_tstamp; 801 u64 tstamp = 0; 802 803 i = tx_ring->next_to_clean; 804 tx_swbd = &tx_ring->tx_swbd[i]; 805 806 bds_to_clean = enetc_bd_ready_count(tx_ring, i); 807 808 do_twostep_tstamp = false; 809 810 while (bds_to_clean && tx_frm_cnt < ENETC_DEFAULT_TX_WORK) { 811 struct xdp_frame *xdp_frame = enetc_tx_swbd_get_xdp_frame(tx_swbd); 812 struct sk_buff *skb = enetc_tx_swbd_get_skb(tx_swbd); 813 bool is_eof = tx_swbd->is_eof; 814 815 if (unlikely(tx_swbd->check_wb)) { 816 union enetc_tx_bd *txbd = ENETC_TXBD(*tx_ring, i); 817 818 if (txbd->flags & ENETC_TXBD_FLAGS_W && 819 tx_swbd->do_twostep_tstamp) { 820 enetc_get_tx_tstamp(&priv->si->hw, txbd, 821 &tstamp); 822 do_twostep_tstamp = true; 823 } 824 } 825 826 if (tx_swbd->is_xdp_tx) 827 enetc_recycle_xdp_tx_buff(tx_ring, tx_swbd); 828 else if (likely(tx_swbd->dma)) 829 enetc_unmap_tx_buff(tx_ring, tx_swbd); 830 831 if (xdp_frame) { 832 xdp_return_frame(xdp_frame); 833 } else if (skb) { 834 if (unlikely(skb->cb[0] & ENETC_F_TX_ONESTEP_SYNC_TSTAMP)) { 835 /* Start work to release lock for next one-step 836 * timestamping packet. And send one skb in 837 * tx_skbs queue if has. 838 */ 839 schedule_work(&priv->tx_onestep_tstamp); 840 } else if (unlikely(do_twostep_tstamp)) { 841 enetc_tstamp_tx(skb, tstamp); 842 do_twostep_tstamp = false; 843 } 844 napi_consume_skb(skb, napi_budget); 845 } 846 847 tx_byte_cnt += tx_swbd->len; 848 /* Scrub the swbd here so we don't have to do that 849 * when we reuse it during xmit 850 */ 851 memset(tx_swbd, 0, sizeof(*tx_swbd)); 852 853 bds_to_clean--; 854 tx_swbd++; 855 i++; 856 if (unlikely(i == tx_ring->bd_count)) { 857 i = 0; 858 tx_swbd = tx_ring->tx_swbd; 859 } 860 861 /* BD iteration loop end */ 862 if (is_eof) { 863 tx_frm_cnt++; 864 /* re-arm interrupt source */ 865 enetc_wr_reg_hot(tx_ring->idr, BIT(tx_ring->index) | 866 BIT(16 + tx_ring->index)); 867 } 868 869 if (unlikely(!bds_to_clean)) 870 bds_to_clean = enetc_bd_ready_count(tx_ring, i); 871 } 872 873 tx_ring->next_to_clean = i; 874 tx_ring->stats.packets += tx_frm_cnt; 875 tx_ring->stats.bytes += tx_byte_cnt; 876 877 if (unlikely(tx_frm_cnt && netif_carrier_ok(ndev) && 878 __netif_subqueue_stopped(ndev, tx_ring->index) && 879 (enetc_bd_unused(tx_ring) >= ENETC_TXBDS_MAX_NEEDED))) { 880 netif_wake_subqueue(ndev, tx_ring->index); 881 } 882 883 return tx_frm_cnt != ENETC_DEFAULT_TX_WORK; 884 } 885 886 static bool enetc_new_page(struct enetc_bdr *rx_ring, 887 struct enetc_rx_swbd *rx_swbd) 888 { 889 bool xdp = !!(rx_ring->xdp.prog); 890 struct page *page; 891 dma_addr_t addr; 892 893 page = dev_alloc_page(); 894 if (unlikely(!page)) 895 return false; 896 897 /* For XDP_TX, we forgo dma_unmap -> dma_map */ 898 rx_swbd->dir = xdp ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE; 899 900 addr = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, rx_swbd->dir); 901 if (unlikely(dma_mapping_error(rx_ring->dev, addr))) { 902 __free_page(page); 903 904 return false; 905 } 906 907 rx_swbd->dma = addr; 908 rx_swbd->page = page; 909 rx_swbd->page_offset = rx_ring->buffer_offset; 910 911 return true; 912 } 913 914 static int enetc_refill_rx_ring(struct enetc_bdr *rx_ring, const int buff_cnt) 915 { 916 struct enetc_rx_swbd *rx_swbd; 917 union enetc_rx_bd *rxbd; 918 int i, j; 919 920 i = rx_ring->next_to_use; 921 rx_swbd = &rx_ring->rx_swbd[i]; 922 rxbd = enetc_rxbd(rx_ring, i); 923 924 for (j = 0; j < buff_cnt; j++) { 925 /* try reuse page */ 926 if (unlikely(!rx_swbd->page)) { 927 if (unlikely(!enetc_new_page(rx_ring, rx_swbd))) { 928 rx_ring->stats.rx_alloc_errs++; 929 break; 930 } 931 } 932 933 /* update RxBD */ 934 rxbd->w.addr = cpu_to_le64(rx_swbd->dma + 935 rx_swbd->page_offset); 936 /* clear 'R" as well */ 937 rxbd->r.lstatus = 0; 938 939 enetc_rxbd_next(rx_ring, &rxbd, &i); 940 rx_swbd = &rx_ring->rx_swbd[i]; 941 } 942 943 if (likely(j)) { 944 rx_ring->next_to_alloc = i; /* keep track from page reuse */ 945 rx_ring->next_to_use = i; 946 947 /* update ENETC's consumer index */ 948 enetc_wr_reg_hot(rx_ring->rcir, rx_ring->next_to_use); 949 } 950 951 return j; 952 } 953 954 #ifdef CONFIG_FSL_ENETC_PTP_CLOCK 955 static void enetc_get_rx_tstamp(struct net_device *ndev, 956 union enetc_rx_bd *rxbd, 957 struct sk_buff *skb) 958 { 959 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb); 960 struct enetc_ndev_priv *priv = netdev_priv(ndev); 961 struct enetc_hw *hw = &priv->si->hw; 962 u32 lo, hi, tstamp_lo; 963 u64 tstamp; 964 965 if (le16_to_cpu(rxbd->r.flags) & ENETC_RXBD_FLAG_TSTMP) { 966 lo = enetc_rd_reg_hot(hw->reg + ENETC_SICTR0); 967 hi = enetc_rd_reg_hot(hw->reg + ENETC_SICTR1); 968 rxbd = enetc_rxbd_ext(rxbd); 969 tstamp_lo = le32_to_cpu(rxbd->ext.tstamp); 970 if (lo <= tstamp_lo) 971 hi -= 1; 972 973 tstamp = (u64)hi << 32 | tstamp_lo; 974 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 975 shhwtstamps->hwtstamp = ns_to_ktime(tstamp); 976 } 977 } 978 #endif 979 980 static void enetc_get_offloads(struct enetc_bdr *rx_ring, 981 union enetc_rx_bd *rxbd, struct sk_buff *skb) 982 { 983 struct enetc_ndev_priv *priv = netdev_priv(rx_ring->ndev); 984 985 /* TODO: hashing */ 986 if (rx_ring->ndev->features & NETIF_F_RXCSUM) { 987 u16 inet_csum = le16_to_cpu(rxbd->r.inet_csum); 988 989 skb->csum = csum_unfold((__force __sum16)~htons(inet_csum)); 990 skb->ip_summed = CHECKSUM_COMPLETE; 991 } 992 993 if (le16_to_cpu(rxbd->r.flags) & ENETC_RXBD_FLAG_VLAN) { 994 __be16 tpid = 0; 995 996 switch (le16_to_cpu(rxbd->r.flags) & ENETC_RXBD_FLAG_TPID) { 997 case 0: 998 tpid = htons(ETH_P_8021Q); 999 break; 1000 case 1: 1001 tpid = htons(ETH_P_8021AD); 1002 break; 1003 case 2: 1004 tpid = htons(enetc_port_rd(&priv->si->hw, 1005 ENETC_PCVLANR1)); 1006 break; 1007 case 3: 1008 tpid = htons(enetc_port_rd(&priv->si->hw, 1009 ENETC_PCVLANR2)); 1010 break; 1011 default: 1012 break; 1013 } 1014 1015 __vlan_hwaccel_put_tag(skb, tpid, le16_to_cpu(rxbd->r.vlan_opt)); 1016 } 1017 1018 #ifdef CONFIG_FSL_ENETC_PTP_CLOCK 1019 if (priv->active_offloads & ENETC_F_RX_TSTAMP) 1020 enetc_get_rx_tstamp(rx_ring->ndev, rxbd, skb); 1021 #endif 1022 } 1023 1024 /* This gets called during the non-XDP NAPI poll cycle as well as on XDP_PASS, 1025 * so it needs to work with both DMA_FROM_DEVICE as well as DMA_BIDIRECTIONAL 1026 * mapped buffers. 1027 */ 1028 static struct enetc_rx_swbd *enetc_get_rx_buff(struct enetc_bdr *rx_ring, 1029 int i, u16 size) 1030 { 1031 struct enetc_rx_swbd *rx_swbd = &rx_ring->rx_swbd[i]; 1032 1033 dma_sync_single_range_for_cpu(rx_ring->dev, rx_swbd->dma, 1034 rx_swbd->page_offset, 1035 size, rx_swbd->dir); 1036 return rx_swbd; 1037 } 1038 1039 /* Reuse the current page without performing half-page buffer flipping */ 1040 static void enetc_put_rx_buff(struct enetc_bdr *rx_ring, 1041 struct enetc_rx_swbd *rx_swbd) 1042 { 1043 size_t buffer_size = ENETC_RXB_TRUESIZE - rx_ring->buffer_offset; 1044 1045 enetc_reuse_page(rx_ring, rx_swbd); 1046 1047 dma_sync_single_range_for_device(rx_ring->dev, rx_swbd->dma, 1048 rx_swbd->page_offset, 1049 buffer_size, rx_swbd->dir); 1050 1051 rx_swbd->page = NULL; 1052 } 1053 1054 /* Reuse the current page by performing half-page buffer flipping */ 1055 static void enetc_flip_rx_buff(struct enetc_bdr *rx_ring, 1056 struct enetc_rx_swbd *rx_swbd) 1057 { 1058 if (likely(enetc_page_reusable(rx_swbd->page))) { 1059 rx_swbd->page_offset ^= ENETC_RXB_TRUESIZE; 1060 page_ref_inc(rx_swbd->page); 1061 1062 enetc_put_rx_buff(rx_ring, rx_swbd); 1063 } else { 1064 dma_unmap_page(rx_ring->dev, rx_swbd->dma, PAGE_SIZE, 1065 rx_swbd->dir); 1066 rx_swbd->page = NULL; 1067 } 1068 } 1069 1070 static struct sk_buff *enetc_map_rx_buff_to_skb(struct enetc_bdr *rx_ring, 1071 int i, u16 size) 1072 { 1073 struct enetc_rx_swbd *rx_swbd = enetc_get_rx_buff(rx_ring, i, size); 1074 struct sk_buff *skb; 1075 void *ba; 1076 1077 ba = page_address(rx_swbd->page) + rx_swbd->page_offset; 1078 skb = build_skb(ba - rx_ring->buffer_offset, ENETC_RXB_TRUESIZE); 1079 if (unlikely(!skb)) { 1080 rx_ring->stats.rx_alloc_errs++; 1081 return NULL; 1082 } 1083 1084 skb_reserve(skb, rx_ring->buffer_offset); 1085 __skb_put(skb, size); 1086 1087 enetc_flip_rx_buff(rx_ring, rx_swbd); 1088 1089 return skb; 1090 } 1091 1092 static void enetc_add_rx_buff_to_skb(struct enetc_bdr *rx_ring, int i, 1093 u16 size, struct sk_buff *skb) 1094 { 1095 struct enetc_rx_swbd *rx_swbd = enetc_get_rx_buff(rx_ring, i, size); 1096 1097 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_swbd->page, 1098 rx_swbd->page_offset, size, ENETC_RXB_TRUESIZE); 1099 1100 enetc_flip_rx_buff(rx_ring, rx_swbd); 1101 } 1102 1103 static bool enetc_check_bd_errors_and_consume(struct enetc_bdr *rx_ring, 1104 u32 bd_status, 1105 union enetc_rx_bd **rxbd, int *i) 1106 { 1107 if (likely(!(bd_status & ENETC_RXBD_LSTATUS(ENETC_RXBD_ERR_MASK)))) 1108 return false; 1109 1110 enetc_put_rx_buff(rx_ring, &rx_ring->rx_swbd[*i]); 1111 enetc_rxbd_next(rx_ring, rxbd, i); 1112 1113 while (!(bd_status & ENETC_RXBD_LSTATUS_F)) { 1114 dma_rmb(); 1115 bd_status = le32_to_cpu((*rxbd)->r.lstatus); 1116 1117 enetc_put_rx_buff(rx_ring, &rx_ring->rx_swbd[*i]); 1118 enetc_rxbd_next(rx_ring, rxbd, i); 1119 } 1120 1121 rx_ring->ndev->stats.rx_dropped++; 1122 rx_ring->ndev->stats.rx_errors++; 1123 1124 return true; 1125 } 1126 1127 static struct sk_buff *enetc_build_skb(struct enetc_bdr *rx_ring, 1128 u32 bd_status, union enetc_rx_bd **rxbd, 1129 int *i, int *cleaned_cnt, int buffer_size) 1130 { 1131 struct sk_buff *skb; 1132 u16 size; 1133 1134 size = le16_to_cpu((*rxbd)->r.buf_len); 1135 skb = enetc_map_rx_buff_to_skb(rx_ring, *i, size); 1136 if (!skb) 1137 return NULL; 1138 1139 enetc_get_offloads(rx_ring, *rxbd, skb); 1140 1141 (*cleaned_cnt)++; 1142 1143 enetc_rxbd_next(rx_ring, rxbd, i); 1144 1145 /* not last BD in frame? */ 1146 while (!(bd_status & ENETC_RXBD_LSTATUS_F)) { 1147 bd_status = le32_to_cpu((*rxbd)->r.lstatus); 1148 size = buffer_size; 1149 1150 if (bd_status & ENETC_RXBD_LSTATUS_F) { 1151 dma_rmb(); 1152 size = le16_to_cpu((*rxbd)->r.buf_len); 1153 } 1154 1155 enetc_add_rx_buff_to_skb(rx_ring, *i, size, skb); 1156 1157 (*cleaned_cnt)++; 1158 1159 enetc_rxbd_next(rx_ring, rxbd, i); 1160 } 1161 1162 skb_record_rx_queue(skb, rx_ring->index); 1163 skb->protocol = eth_type_trans(skb, rx_ring->ndev); 1164 1165 return skb; 1166 } 1167 1168 #define ENETC_RXBD_BUNDLE 16 /* # of BDs to update at once */ 1169 1170 static int enetc_clean_rx_ring(struct enetc_bdr *rx_ring, 1171 struct napi_struct *napi, int work_limit) 1172 { 1173 int rx_frm_cnt = 0, rx_byte_cnt = 0; 1174 int cleaned_cnt, i; 1175 1176 cleaned_cnt = enetc_bd_unused(rx_ring); 1177 /* next descriptor to process */ 1178 i = rx_ring->next_to_clean; 1179 1180 while (likely(rx_frm_cnt < work_limit)) { 1181 union enetc_rx_bd *rxbd; 1182 struct sk_buff *skb; 1183 u32 bd_status; 1184 1185 if (cleaned_cnt >= ENETC_RXBD_BUNDLE) 1186 cleaned_cnt -= enetc_refill_rx_ring(rx_ring, 1187 cleaned_cnt); 1188 1189 rxbd = enetc_rxbd(rx_ring, i); 1190 bd_status = le32_to_cpu(rxbd->r.lstatus); 1191 if (!bd_status) 1192 break; 1193 1194 enetc_wr_reg_hot(rx_ring->idr, BIT(rx_ring->index)); 1195 dma_rmb(); /* for reading other rxbd fields */ 1196 1197 if (enetc_check_bd_errors_and_consume(rx_ring, bd_status, 1198 &rxbd, &i)) 1199 break; 1200 1201 skb = enetc_build_skb(rx_ring, bd_status, &rxbd, &i, 1202 &cleaned_cnt, ENETC_RXB_DMA_SIZE); 1203 if (!skb) 1204 break; 1205 1206 rx_byte_cnt += skb->len; 1207 rx_frm_cnt++; 1208 1209 napi_gro_receive(napi, skb); 1210 } 1211 1212 rx_ring->next_to_clean = i; 1213 1214 rx_ring->stats.packets += rx_frm_cnt; 1215 rx_ring->stats.bytes += rx_byte_cnt; 1216 1217 return rx_frm_cnt; 1218 } 1219 1220 static void enetc_xdp_map_tx_buff(struct enetc_bdr *tx_ring, int i, 1221 struct enetc_tx_swbd *tx_swbd, 1222 int frm_len) 1223 { 1224 union enetc_tx_bd *txbd = ENETC_TXBD(*tx_ring, i); 1225 1226 prefetchw(txbd); 1227 1228 enetc_clear_tx_bd(txbd); 1229 txbd->addr = cpu_to_le64(tx_swbd->dma + tx_swbd->page_offset); 1230 txbd->buf_len = cpu_to_le16(tx_swbd->len); 1231 txbd->frm_len = cpu_to_le16(frm_len); 1232 1233 memcpy(&tx_ring->tx_swbd[i], tx_swbd, sizeof(*tx_swbd)); 1234 } 1235 1236 /* Puts in the TX ring one XDP frame, mapped as an array of TX software buffer 1237 * descriptors. 1238 */ 1239 static bool enetc_xdp_tx(struct enetc_bdr *tx_ring, 1240 struct enetc_tx_swbd *xdp_tx_arr, int num_tx_swbd) 1241 { 1242 struct enetc_tx_swbd *tmp_tx_swbd = xdp_tx_arr; 1243 int i, k, frm_len = tmp_tx_swbd->len; 1244 1245 if (unlikely(enetc_bd_unused(tx_ring) < ENETC_TXBDS_NEEDED(num_tx_swbd))) 1246 return false; 1247 1248 while (unlikely(!tmp_tx_swbd->is_eof)) { 1249 tmp_tx_swbd++; 1250 frm_len += tmp_tx_swbd->len; 1251 } 1252 1253 i = tx_ring->next_to_use; 1254 1255 for (k = 0; k < num_tx_swbd; k++) { 1256 struct enetc_tx_swbd *xdp_tx_swbd = &xdp_tx_arr[k]; 1257 1258 enetc_xdp_map_tx_buff(tx_ring, i, xdp_tx_swbd, frm_len); 1259 1260 /* last BD needs 'F' bit set */ 1261 if (xdp_tx_swbd->is_eof) { 1262 union enetc_tx_bd *txbd = ENETC_TXBD(*tx_ring, i); 1263 1264 txbd->flags = ENETC_TXBD_FLAGS_F; 1265 } 1266 1267 enetc_bdr_idx_inc(tx_ring, &i); 1268 } 1269 1270 tx_ring->next_to_use = i; 1271 1272 return true; 1273 } 1274 1275 static int enetc_xdp_frame_to_xdp_tx_swbd(struct enetc_bdr *tx_ring, 1276 struct enetc_tx_swbd *xdp_tx_arr, 1277 struct xdp_frame *xdp_frame) 1278 { 1279 struct enetc_tx_swbd *xdp_tx_swbd = &xdp_tx_arr[0]; 1280 struct skb_shared_info *shinfo; 1281 void *data = xdp_frame->data; 1282 int len = xdp_frame->len; 1283 skb_frag_t *frag; 1284 dma_addr_t dma; 1285 unsigned int f; 1286 int n = 0; 1287 1288 dma = dma_map_single(tx_ring->dev, data, len, DMA_TO_DEVICE); 1289 if (unlikely(dma_mapping_error(tx_ring->dev, dma))) { 1290 netdev_err(tx_ring->ndev, "DMA map error\n"); 1291 return -1; 1292 } 1293 1294 xdp_tx_swbd->dma = dma; 1295 xdp_tx_swbd->dir = DMA_TO_DEVICE; 1296 xdp_tx_swbd->len = len; 1297 xdp_tx_swbd->is_xdp_redirect = true; 1298 xdp_tx_swbd->is_eof = false; 1299 xdp_tx_swbd->xdp_frame = NULL; 1300 1301 n++; 1302 xdp_tx_swbd = &xdp_tx_arr[n]; 1303 1304 shinfo = xdp_get_shared_info_from_frame(xdp_frame); 1305 1306 for (f = 0, frag = &shinfo->frags[0]; f < shinfo->nr_frags; 1307 f++, frag++) { 1308 data = skb_frag_address(frag); 1309 len = skb_frag_size(frag); 1310 1311 dma = dma_map_single(tx_ring->dev, data, len, DMA_TO_DEVICE); 1312 if (unlikely(dma_mapping_error(tx_ring->dev, dma))) { 1313 /* Undo the DMA mapping for all fragments */ 1314 while (--n >= 0) 1315 enetc_unmap_tx_buff(tx_ring, &xdp_tx_arr[n]); 1316 1317 netdev_err(tx_ring->ndev, "DMA map error\n"); 1318 return -1; 1319 } 1320 1321 xdp_tx_swbd->dma = dma; 1322 xdp_tx_swbd->dir = DMA_TO_DEVICE; 1323 xdp_tx_swbd->len = len; 1324 xdp_tx_swbd->is_xdp_redirect = true; 1325 xdp_tx_swbd->is_eof = false; 1326 xdp_tx_swbd->xdp_frame = NULL; 1327 1328 n++; 1329 xdp_tx_swbd = &xdp_tx_arr[n]; 1330 } 1331 1332 xdp_tx_arr[n - 1].is_eof = true; 1333 xdp_tx_arr[n - 1].xdp_frame = xdp_frame; 1334 1335 return n; 1336 } 1337 1338 int enetc_xdp_xmit(struct net_device *ndev, int num_frames, 1339 struct xdp_frame **frames, u32 flags) 1340 { 1341 struct enetc_tx_swbd xdp_redirect_arr[ENETC_MAX_SKB_FRAGS] = {0}; 1342 struct enetc_ndev_priv *priv = netdev_priv(ndev); 1343 struct enetc_bdr *tx_ring; 1344 int xdp_tx_bd_cnt, i, k; 1345 int xdp_tx_frm_cnt = 0; 1346 1347 enetc_lock_mdio(); 1348 1349 tx_ring = priv->xdp_tx_ring[smp_processor_id()]; 1350 1351 prefetchw(ENETC_TXBD(*tx_ring, tx_ring->next_to_use)); 1352 1353 for (k = 0; k < num_frames; k++) { 1354 xdp_tx_bd_cnt = enetc_xdp_frame_to_xdp_tx_swbd(tx_ring, 1355 xdp_redirect_arr, 1356 frames[k]); 1357 if (unlikely(xdp_tx_bd_cnt < 0)) 1358 break; 1359 1360 if (unlikely(!enetc_xdp_tx(tx_ring, xdp_redirect_arr, 1361 xdp_tx_bd_cnt))) { 1362 for (i = 0; i < xdp_tx_bd_cnt; i++) 1363 enetc_unmap_tx_buff(tx_ring, 1364 &xdp_redirect_arr[i]); 1365 tx_ring->stats.xdp_tx_drops++; 1366 break; 1367 } 1368 1369 xdp_tx_frm_cnt++; 1370 } 1371 1372 if (unlikely((flags & XDP_XMIT_FLUSH) || k != xdp_tx_frm_cnt)) 1373 enetc_update_tx_ring_tail(tx_ring); 1374 1375 tx_ring->stats.xdp_tx += xdp_tx_frm_cnt; 1376 1377 enetc_unlock_mdio(); 1378 1379 return xdp_tx_frm_cnt; 1380 } 1381 1382 static void enetc_map_rx_buff_to_xdp(struct enetc_bdr *rx_ring, int i, 1383 struct xdp_buff *xdp_buff, u16 size) 1384 { 1385 struct enetc_rx_swbd *rx_swbd = enetc_get_rx_buff(rx_ring, i, size); 1386 void *hard_start = page_address(rx_swbd->page) + rx_swbd->page_offset; 1387 struct skb_shared_info *shinfo; 1388 1389 /* To be used for XDP_TX */ 1390 rx_swbd->len = size; 1391 1392 xdp_prepare_buff(xdp_buff, hard_start - rx_ring->buffer_offset, 1393 rx_ring->buffer_offset, size, false); 1394 1395 shinfo = xdp_get_shared_info_from_buff(xdp_buff); 1396 shinfo->nr_frags = 0; 1397 } 1398 1399 static void enetc_add_rx_buff_to_xdp(struct enetc_bdr *rx_ring, int i, 1400 u16 size, struct xdp_buff *xdp_buff) 1401 { 1402 struct skb_shared_info *shinfo = xdp_get_shared_info_from_buff(xdp_buff); 1403 struct enetc_rx_swbd *rx_swbd = enetc_get_rx_buff(rx_ring, i, size); 1404 skb_frag_t *frag = &shinfo->frags[shinfo->nr_frags]; 1405 1406 /* To be used for XDP_TX */ 1407 rx_swbd->len = size; 1408 1409 skb_frag_off_set(frag, rx_swbd->page_offset); 1410 skb_frag_size_set(frag, size); 1411 __skb_frag_set_page(frag, rx_swbd->page); 1412 1413 shinfo->nr_frags++; 1414 } 1415 1416 static void enetc_build_xdp_buff(struct enetc_bdr *rx_ring, u32 bd_status, 1417 union enetc_rx_bd **rxbd, int *i, 1418 int *cleaned_cnt, struct xdp_buff *xdp_buff) 1419 { 1420 u16 size = le16_to_cpu((*rxbd)->r.buf_len); 1421 1422 xdp_init_buff(xdp_buff, ENETC_RXB_TRUESIZE, &rx_ring->xdp.rxq); 1423 1424 enetc_map_rx_buff_to_xdp(rx_ring, *i, xdp_buff, size); 1425 (*cleaned_cnt)++; 1426 enetc_rxbd_next(rx_ring, rxbd, i); 1427 1428 /* not last BD in frame? */ 1429 while (!(bd_status & ENETC_RXBD_LSTATUS_F)) { 1430 bd_status = le32_to_cpu((*rxbd)->r.lstatus); 1431 size = ENETC_RXB_DMA_SIZE_XDP; 1432 1433 if (bd_status & ENETC_RXBD_LSTATUS_F) { 1434 dma_rmb(); 1435 size = le16_to_cpu((*rxbd)->r.buf_len); 1436 } 1437 1438 enetc_add_rx_buff_to_xdp(rx_ring, *i, size, xdp_buff); 1439 (*cleaned_cnt)++; 1440 enetc_rxbd_next(rx_ring, rxbd, i); 1441 } 1442 } 1443 1444 /* Convert RX buffer descriptors to TX buffer descriptors. These will be 1445 * recycled back into the RX ring in enetc_clean_tx_ring. 1446 */ 1447 static int enetc_rx_swbd_to_xdp_tx_swbd(struct enetc_tx_swbd *xdp_tx_arr, 1448 struct enetc_bdr *rx_ring, 1449 int rx_ring_first, int rx_ring_last) 1450 { 1451 int n = 0; 1452 1453 for (; rx_ring_first != rx_ring_last; 1454 n++, enetc_bdr_idx_inc(rx_ring, &rx_ring_first)) { 1455 struct enetc_rx_swbd *rx_swbd = &rx_ring->rx_swbd[rx_ring_first]; 1456 struct enetc_tx_swbd *tx_swbd = &xdp_tx_arr[n]; 1457 1458 /* No need to dma_map, we already have DMA_BIDIRECTIONAL */ 1459 tx_swbd->dma = rx_swbd->dma; 1460 tx_swbd->dir = rx_swbd->dir; 1461 tx_swbd->page = rx_swbd->page; 1462 tx_swbd->page_offset = rx_swbd->page_offset; 1463 tx_swbd->len = rx_swbd->len; 1464 tx_swbd->is_dma_page = true; 1465 tx_swbd->is_xdp_tx = true; 1466 tx_swbd->is_eof = false; 1467 } 1468 1469 /* We rely on caller providing an rx_ring_last > rx_ring_first */ 1470 xdp_tx_arr[n - 1].is_eof = true; 1471 1472 return n; 1473 } 1474 1475 static void enetc_xdp_drop(struct enetc_bdr *rx_ring, int rx_ring_first, 1476 int rx_ring_last) 1477 { 1478 while (rx_ring_first != rx_ring_last) { 1479 enetc_put_rx_buff(rx_ring, 1480 &rx_ring->rx_swbd[rx_ring_first]); 1481 enetc_bdr_idx_inc(rx_ring, &rx_ring_first); 1482 } 1483 rx_ring->stats.xdp_drops++; 1484 } 1485 1486 static void enetc_xdp_free(struct enetc_bdr *rx_ring, int rx_ring_first, 1487 int rx_ring_last) 1488 { 1489 while (rx_ring_first != rx_ring_last) { 1490 struct enetc_rx_swbd *rx_swbd = &rx_ring->rx_swbd[rx_ring_first]; 1491 1492 if (rx_swbd->page) { 1493 dma_unmap_page(rx_ring->dev, rx_swbd->dma, PAGE_SIZE, 1494 rx_swbd->dir); 1495 __free_page(rx_swbd->page); 1496 rx_swbd->page = NULL; 1497 } 1498 enetc_bdr_idx_inc(rx_ring, &rx_ring_first); 1499 } 1500 rx_ring->stats.xdp_redirect_failures++; 1501 } 1502 1503 static int enetc_clean_rx_ring_xdp(struct enetc_bdr *rx_ring, 1504 struct napi_struct *napi, int work_limit, 1505 struct bpf_prog *prog) 1506 { 1507 int xdp_tx_bd_cnt, xdp_tx_frm_cnt = 0, xdp_redirect_frm_cnt = 0; 1508 struct enetc_tx_swbd xdp_tx_arr[ENETC_MAX_SKB_FRAGS] = {0}; 1509 struct enetc_ndev_priv *priv = netdev_priv(rx_ring->ndev); 1510 int rx_frm_cnt = 0, rx_byte_cnt = 0; 1511 struct enetc_bdr *tx_ring; 1512 int cleaned_cnt, i; 1513 u32 xdp_act; 1514 1515 cleaned_cnt = enetc_bd_unused(rx_ring); 1516 /* next descriptor to process */ 1517 i = rx_ring->next_to_clean; 1518 1519 while (likely(rx_frm_cnt < work_limit)) { 1520 union enetc_rx_bd *rxbd, *orig_rxbd; 1521 int orig_i, orig_cleaned_cnt; 1522 struct xdp_buff xdp_buff; 1523 struct sk_buff *skb; 1524 int tmp_orig_i, err; 1525 u32 bd_status; 1526 1527 rxbd = enetc_rxbd(rx_ring, i); 1528 bd_status = le32_to_cpu(rxbd->r.lstatus); 1529 if (!bd_status) 1530 break; 1531 1532 enetc_wr_reg_hot(rx_ring->idr, BIT(rx_ring->index)); 1533 dma_rmb(); /* for reading other rxbd fields */ 1534 1535 if (enetc_check_bd_errors_and_consume(rx_ring, bd_status, 1536 &rxbd, &i)) 1537 break; 1538 1539 orig_rxbd = rxbd; 1540 orig_cleaned_cnt = cleaned_cnt; 1541 orig_i = i; 1542 1543 enetc_build_xdp_buff(rx_ring, bd_status, &rxbd, &i, 1544 &cleaned_cnt, &xdp_buff); 1545 1546 xdp_act = bpf_prog_run_xdp(prog, &xdp_buff); 1547 1548 switch (xdp_act) { 1549 default: 1550 bpf_warn_invalid_xdp_action(rx_ring->ndev, prog, xdp_act); 1551 fallthrough; 1552 case XDP_ABORTED: 1553 trace_xdp_exception(rx_ring->ndev, prog, xdp_act); 1554 fallthrough; 1555 case XDP_DROP: 1556 enetc_xdp_drop(rx_ring, orig_i, i); 1557 break; 1558 case XDP_PASS: 1559 rxbd = orig_rxbd; 1560 cleaned_cnt = orig_cleaned_cnt; 1561 i = orig_i; 1562 1563 skb = enetc_build_skb(rx_ring, bd_status, &rxbd, 1564 &i, &cleaned_cnt, 1565 ENETC_RXB_DMA_SIZE_XDP); 1566 if (unlikely(!skb)) 1567 goto out; 1568 1569 napi_gro_receive(napi, skb); 1570 break; 1571 case XDP_TX: 1572 tx_ring = priv->xdp_tx_ring[rx_ring->index]; 1573 xdp_tx_bd_cnt = enetc_rx_swbd_to_xdp_tx_swbd(xdp_tx_arr, 1574 rx_ring, 1575 orig_i, i); 1576 1577 if (!enetc_xdp_tx(tx_ring, xdp_tx_arr, xdp_tx_bd_cnt)) { 1578 enetc_xdp_drop(rx_ring, orig_i, i); 1579 tx_ring->stats.xdp_tx_drops++; 1580 } else { 1581 tx_ring->stats.xdp_tx += xdp_tx_bd_cnt; 1582 rx_ring->xdp.xdp_tx_in_flight += xdp_tx_bd_cnt; 1583 xdp_tx_frm_cnt++; 1584 /* The XDP_TX enqueue was successful, so we 1585 * need to scrub the RX software BDs because 1586 * the ownership of the buffers no longer 1587 * belongs to the RX ring, and we must prevent 1588 * enetc_refill_rx_ring() from reusing 1589 * rx_swbd->page. 1590 */ 1591 while (orig_i != i) { 1592 rx_ring->rx_swbd[orig_i].page = NULL; 1593 enetc_bdr_idx_inc(rx_ring, &orig_i); 1594 } 1595 } 1596 break; 1597 case XDP_REDIRECT: 1598 /* xdp_return_frame does not support S/G in the sense 1599 * that it leaks the fragments (__xdp_return should not 1600 * call page_frag_free only for the initial buffer). 1601 * Until XDP_REDIRECT gains support for S/G let's keep 1602 * the code structure in place, but dead. We drop the 1603 * S/G frames ourselves to avoid memory leaks which 1604 * would otherwise leave the kernel OOM. 1605 */ 1606 if (unlikely(cleaned_cnt - orig_cleaned_cnt != 1)) { 1607 enetc_xdp_drop(rx_ring, orig_i, i); 1608 rx_ring->stats.xdp_redirect_sg++; 1609 break; 1610 } 1611 1612 tmp_orig_i = orig_i; 1613 1614 while (orig_i != i) { 1615 enetc_flip_rx_buff(rx_ring, 1616 &rx_ring->rx_swbd[orig_i]); 1617 enetc_bdr_idx_inc(rx_ring, &orig_i); 1618 } 1619 1620 err = xdp_do_redirect(rx_ring->ndev, &xdp_buff, prog); 1621 if (unlikely(err)) { 1622 enetc_xdp_free(rx_ring, tmp_orig_i, i); 1623 } else { 1624 xdp_redirect_frm_cnt++; 1625 rx_ring->stats.xdp_redirect++; 1626 } 1627 } 1628 1629 rx_frm_cnt++; 1630 } 1631 1632 out: 1633 rx_ring->next_to_clean = i; 1634 1635 rx_ring->stats.packets += rx_frm_cnt; 1636 rx_ring->stats.bytes += rx_byte_cnt; 1637 1638 if (xdp_redirect_frm_cnt) 1639 xdp_do_flush_map(); 1640 1641 if (xdp_tx_frm_cnt) 1642 enetc_update_tx_ring_tail(tx_ring); 1643 1644 if (cleaned_cnt > rx_ring->xdp.xdp_tx_in_flight) 1645 enetc_refill_rx_ring(rx_ring, enetc_bd_unused(rx_ring) - 1646 rx_ring->xdp.xdp_tx_in_flight); 1647 1648 return rx_frm_cnt; 1649 } 1650 1651 static int enetc_poll(struct napi_struct *napi, int budget) 1652 { 1653 struct enetc_int_vector 1654 *v = container_of(napi, struct enetc_int_vector, napi); 1655 struct enetc_bdr *rx_ring = &v->rx_ring; 1656 struct bpf_prog *prog; 1657 bool complete = true; 1658 int work_done; 1659 int i; 1660 1661 enetc_lock_mdio(); 1662 1663 for (i = 0; i < v->count_tx_rings; i++) 1664 if (!enetc_clean_tx_ring(&v->tx_ring[i], budget)) 1665 complete = false; 1666 1667 prog = rx_ring->xdp.prog; 1668 if (prog) 1669 work_done = enetc_clean_rx_ring_xdp(rx_ring, napi, budget, prog); 1670 else 1671 work_done = enetc_clean_rx_ring(rx_ring, napi, budget); 1672 if (work_done == budget) 1673 complete = false; 1674 if (work_done) 1675 v->rx_napi_work = true; 1676 1677 if (!complete) { 1678 enetc_unlock_mdio(); 1679 return budget; 1680 } 1681 1682 napi_complete_done(napi, work_done); 1683 1684 if (likely(v->rx_dim_en)) 1685 enetc_rx_net_dim(v); 1686 1687 v->rx_napi_work = false; 1688 1689 /* enable interrupts */ 1690 enetc_wr_reg_hot(v->rbier, ENETC_RBIER_RXTIE); 1691 1692 for_each_set_bit(i, &v->tx_rings_map, ENETC_MAX_NUM_TXQS) 1693 enetc_wr_reg_hot(v->tbier_base + ENETC_BDR_OFF(i), 1694 ENETC_TBIER_TXTIE); 1695 1696 enetc_unlock_mdio(); 1697 1698 return work_done; 1699 } 1700 1701 /* Probing and Init */ 1702 #define ENETC_MAX_RFS_SIZE 64 1703 void enetc_get_si_caps(struct enetc_si *si) 1704 { 1705 struct enetc_hw *hw = &si->hw; 1706 u32 val; 1707 1708 /* find out how many of various resources we have to work with */ 1709 val = enetc_rd(hw, ENETC_SICAPR0); 1710 si->num_rx_rings = (val >> 16) & 0xff; 1711 si->num_tx_rings = val & 0xff; 1712 1713 val = enetc_rd(hw, ENETC_SIRFSCAPR); 1714 si->num_fs_entries = ENETC_SIRFSCAPR_GET_NUM_RFS(val); 1715 si->num_fs_entries = min(si->num_fs_entries, ENETC_MAX_RFS_SIZE); 1716 1717 si->num_rss = 0; 1718 val = enetc_rd(hw, ENETC_SIPCAPR0); 1719 if (val & ENETC_SIPCAPR0_RSS) { 1720 u32 rss; 1721 1722 rss = enetc_rd(hw, ENETC_SIRSSCAPR); 1723 si->num_rss = ENETC_SIRSSCAPR_GET_NUM_RSS(rss); 1724 } 1725 1726 if (val & ENETC_SIPCAPR0_QBV) 1727 si->hw_features |= ENETC_SI_F_QBV; 1728 1729 if (val & ENETC_SIPCAPR0_PSFP) 1730 si->hw_features |= ENETC_SI_F_PSFP; 1731 } 1732 1733 static int enetc_dma_alloc_bdr(struct enetc_bdr *r, size_t bd_size) 1734 { 1735 r->bd_base = dma_alloc_coherent(r->dev, r->bd_count * bd_size, 1736 &r->bd_dma_base, GFP_KERNEL); 1737 if (!r->bd_base) 1738 return -ENOMEM; 1739 1740 /* h/w requires 128B alignment */ 1741 if (!IS_ALIGNED(r->bd_dma_base, 128)) { 1742 dma_free_coherent(r->dev, r->bd_count * bd_size, r->bd_base, 1743 r->bd_dma_base); 1744 return -EINVAL; 1745 } 1746 1747 return 0; 1748 } 1749 1750 static int enetc_alloc_txbdr(struct enetc_bdr *txr) 1751 { 1752 int err; 1753 1754 txr->tx_swbd = vzalloc(txr->bd_count * sizeof(struct enetc_tx_swbd)); 1755 if (!txr->tx_swbd) 1756 return -ENOMEM; 1757 1758 err = enetc_dma_alloc_bdr(txr, sizeof(union enetc_tx_bd)); 1759 if (err) 1760 goto err_alloc_bdr; 1761 1762 txr->tso_headers = dma_alloc_coherent(txr->dev, 1763 txr->bd_count * TSO_HEADER_SIZE, 1764 &txr->tso_headers_dma, 1765 GFP_KERNEL); 1766 if (!txr->tso_headers) { 1767 err = -ENOMEM; 1768 goto err_alloc_tso; 1769 } 1770 1771 txr->next_to_clean = 0; 1772 txr->next_to_use = 0; 1773 1774 return 0; 1775 1776 err_alloc_tso: 1777 dma_free_coherent(txr->dev, txr->bd_count * sizeof(union enetc_tx_bd), 1778 txr->bd_base, txr->bd_dma_base); 1779 txr->bd_base = NULL; 1780 err_alloc_bdr: 1781 vfree(txr->tx_swbd); 1782 txr->tx_swbd = NULL; 1783 1784 return err; 1785 } 1786 1787 static void enetc_free_txbdr(struct enetc_bdr *txr) 1788 { 1789 int size, i; 1790 1791 for (i = 0; i < txr->bd_count; i++) 1792 enetc_free_tx_frame(txr, &txr->tx_swbd[i]); 1793 1794 size = txr->bd_count * sizeof(union enetc_tx_bd); 1795 1796 dma_free_coherent(txr->dev, txr->bd_count * TSO_HEADER_SIZE, 1797 txr->tso_headers, txr->tso_headers_dma); 1798 txr->tso_headers = NULL; 1799 1800 dma_free_coherent(txr->dev, size, txr->bd_base, txr->bd_dma_base); 1801 txr->bd_base = NULL; 1802 1803 vfree(txr->tx_swbd); 1804 txr->tx_swbd = NULL; 1805 } 1806 1807 static int enetc_alloc_tx_resources(struct enetc_ndev_priv *priv) 1808 { 1809 int i, err; 1810 1811 for (i = 0; i < priv->num_tx_rings; i++) { 1812 err = enetc_alloc_txbdr(priv->tx_ring[i]); 1813 1814 if (err) 1815 goto fail; 1816 } 1817 1818 return 0; 1819 1820 fail: 1821 while (i-- > 0) 1822 enetc_free_txbdr(priv->tx_ring[i]); 1823 1824 return err; 1825 } 1826 1827 static void enetc_free_tx_resources(struct enetc_ndev_priv *priv) 1828 { 1829 int i; 1830 1831 for (i = 0; i < priv->num_tx_rings; i++) 1832 enetc_free_txbdr(priv->tx_ring[i]); 1833 } 1834 1835 static int enetc_alloc_rxbdr(struct enetc_bdr *rxr, bool extended) 1836 { 1837 size_t size = sizeof(union enetc_rx_bd); 1838 int err; 1839 1840 rxr->rx_swbd = vzalloc(rxr->bd_count * sizeof(struct enetc_rx_swbd)); 1841 if (!rxr->rx_swbd) 1842 return -ENOMEM; 1843 1844 if (extended) 1845 size *= 2; 1846 1847 err = enetc_dma_alloc_bdr(rxr, size); 1848 if (err) { 1849 vfree(rxr->rx_swbd); 1850 return err; 1851 } 1852 1853 rxr->next_to_clean = 0; 1854 rxr->next_to_use = 0; 1855 rxr->next_to_alloc = 0; 1856 rxr->ext_en = extended; 1857 1858 return 0; 1859 } 1860 1861 static void enetc_free_rxbdr(struct enetc_bdr *rxr) 1862 { 1863 int size; 1864 1865 size = rxr->bd_count * sizeof(union enetc_rx_bd); 1866 1867 dma_free_coherent(rxr->dev, size, rxr->bd_base, rxr->bd_dma_base); 1868 rxr->bd_base = NULL; 1869 1870 vfree(rxr->rx_swbd); 1871 rxr->rx_swbd = NULL; 1872 } 1873 1874 static int enetc_alloc_rx_resources(struct enetc_ndev_priv *priv) 1875 { 1876 bool extended = !!(priv->active_offloads & ENETC_F_RX_TSTAMP); 1877 int i, err; 1878 1879 for (i = 0; i < priv->num_rx_rings; i++) { 1880 err = enetc_alloc_rxbdr(priv->rx_ring[i], extended); 1881 1882 if (err) 1883 goto fail; 1884 } 1885 1886 return 0; 1887 1888 fail: 1889 while (i-- > 0) 1890 enetc_free_rxbdr(priv->rx_ring[i]); 1891 1892 return err; 1893 } 1894 1895 static void enetc_free_rx_resources(struct enetc_ndev_priv *priv) 1896 { 1897 int i; 1898 1899 for (i = 0; i < priv->num_rx_rings; i++) 1900 enetc_free_rxbdr(priv->rx_ring[i]); 1901 } 1902 1903 static void enetc_free_tx_ring(struct enetc_bdr *tx_ring) 1904 { 1905 int i; 1906 1907 if (!tx_ring->tx_swbd) 1908 return; 1909 1910 for (i = 0; i < tx_ring->bd_count; i++) { 1911 struct enetc_tx_swbd *tx_swbd = &tx_ring->tx_swbd[i]; 1912 1913 enetc_free_tx_frame(tx_ring, tx_swbd); 1914 } 1915 1916 tx_ring->next_to_clean = 0; 1917 tx_ring->next_to_use = 0; 1918 } 1919 1920 static void enetc_free_rx_ring(struct enetc_bdr *rx_ring) 1921 { 1922 int i; 1923 1924 if (!rx_ring->rx_swbd) 1925 return; 1926 1927 for (i = 0; i < rx_ring->bd_count; i++) { 1928 struct enetc_rx_swbd *rx_swbd = &rx_ring->rx_swbd[i]; 1929 1930 if (!rx_swbd->page) 1931 continue; 1932 1933 dma_unmap_page(rx_ring->dev, rx_swbd->dma, PAGE_SIZE, 1934 rx_swbd->dir); 1935 __free_page(rx_swbd->page); 1936 rx_swbd->page = NULL; 1937 } 1938 1939 rx_ring->next_to_clean = 0; 1940 rx_ring->next_to_use = 0; 1941 rx_ring->next_to_alloc = 0; 1942 } 1943 1944 static void enetc_free_rxtx_rings(struct enetc_ndev_priv *priv) 1945 { 1946 int i; 1947 1948 for (i = 0; i < priv->num_rx_rings; i++) 1949 enetc_free_rx_ring(priv->rx_ring[i]); 1950 1951 for (i = 0; i < priv->num_tx_rings; i++) 1952 enetc_free_tx_ring(priv->tx_ring[i]); 1953 } 1954 1955 static int enetc_setup_default_rss_table(struct enetc_si *si, int num_groups) 1956 { 1957 int *rss_table; 1958 int i; 1959 1960 rss_table = kmalloc_array(si->num_rss, sizeof(*rss_table), GFP_KERNEL); 1961 if (!rss_table) 1962 return -ENOMEM; 1963 1964 /* Set up RSS table defaults */ 1965 for (i = 0; i < si->num_rss; i++) 1966 rss_table[i] = i % num_groups; 1967 1968 enetc_set_rss_table(si, rss_table, si->num_rss); 1969 1970 kfree(rss_table); 1971 1972 return 0; 1973 } 1974 1975 int enetc_configure_si(struct enetc_ndev_priv *priv) 1976 { 1977 struct enetc_si *si = priv->si; 1978 struct enetc_hw *hw = &si->hw; 1979 int err; 1980 1981 /* set SI cache attributes */ 1982 enetc_wr(hw, ENETC_SICAR0, 1983 ENETC_SICAR_RD_COHERENT | ENETC_SICAR_WR_COHERENT); 1984 enetc_wr(hw, ENETC_SICAR1, ENETC_SICAR_MSI); 1985 /* enable SI */ 1986 enetc_wr(hw, ENETC_SIMR, ENETC_SIMR_EN); 1987 1988 if (si->num_rss) { 1989 err = enetc_setup_default_rss_table(si, priv->num_rx_rings); 1990 if (err) 1991 return err; 1992 } 1993 1994 return 0; 1995 } 1996 1997 void enetc_init_si_rings_params(struct enetc_ndev_priv *priv) 1998 { 1999 struct enetc_si *si = priv->si; 2000 int cpus = num_online_cpus(); 2001 2002 priv->tx_bd_count = ENETC_TX_RING_DEFAULT_SIZE; 2003 priv->rx_bd_count = ENETC_RX_RING_DEFAULT_SIZE; 2004 2005 /* Enable all available TX rings in order to configure as many 2006 * priorities as possible, when needed. 2007 * TODO: Make # of TX rings run-time configurable 2008 */ 2009 priv->num_rx_rings = min_t(int, cpus, si->num_rx_rings); 2010 priv->num_tx_rings = si->num_tx_rings; 2011 priv->bdr_int_num = cpus; 2012 priv->ic_mode = ENETC_IC_RX_ADAPTIVE | ENETC_IC_TX_MANUAL; 2013 priv->tx_ictt = ENETC_TXIC_TIMETHR; 2014 } 2015 2016 int enetc_alloc_si_resources(struct enetc_ndev_priv *priv) 2017 { 2018 struct enetc_si *si = priv->si; 2019 2020 priv->cls_rules = kcalloc(si->num_fs_entries, sizeof(*priv->cls_rules), 2021 GFP_KERNEL); 2022 if (!priv->cls_rules) 2023 return -ENOMEM; 2024 2025 return 0; 2026 } 2027 2028 void enetc_free_si_resources(struct enetc_ndev_priv *priv) 2029 { 2030 kfree(priv->cls_rules); 2031 } 2032 2033 static void enetc_setup_txbdr(struct enetc_hw *hw, struct enetc_bdr *tx_ring) 2034 { 2035 int idx = tx_ring->index; 2036 u32 tbmr; 2037 2038 enetc_txbdr_wr(hw, idx, ENETC_TBBAR0, 2039 lower_32_bits(tx_ring->bd_dma_base)); 2040 2041 enetc_txbdr_wr(hw, idx, ENETC_TBBAR1, 2042 upper_32_bits(tx_ring->bd_dma_base)); 2043 2044 WARN_ON(!IS_ALIGNED(tx_ring->bd_count, 64)); /* multiple of 64 */ 2045 enetc_txbdr_wr(hw, idx, ENETC_TBLENR, 2046 ENETC_RTBLENR_LEN(tx_ring->bd_count)); 2047 2048 /* clearing PI/CI registers for Tx not supported, adjust sw indexes */ 2049 tx_ring->next_to_use = enetc_txbdr_rd(hw, idx, ENETC_TBPIR); 2050 tx_ring->next_to_clean = enetc_txbdr_rd(hw, idx, ENETC_TBCIR); 2051 2052 /* enable Tx ints by setting pkt thr to 1 */ 2053 enetc_txbdr_wr(hw, idx, ENETC_TBICR0, ENETC_TBICR0_ICEN | 0x1); 2054 2055 tbmr = ENETC_TBMR_EN; 2056 if (tx_ring->ndev->features & NETIF_F_HW_VLAN_CTAG_TX) 2057 tbmr |= ENETC_TBMR_VIH; 2058 2059 /* enable ring */ 2060 enetc_txbdr_wr(hw, idx, ENETC_TBMR, tbmr); 2061 2062 tx_ring->tpir = hw->reg + ENETC_BDR(TX, idx, ENETC_TBPIR); 2063 tx_ring->tcir = hw->reg + ENETC_BDR(TX, idx, ENETC_TBCIR); 2064 tx_ring->idr = hw->reg + ENETC_SITXIDR; 2065 } 2066 2067 static void enetc_setup_rxbdr(struct enetc_hw *hw, struct enetc_bdr *rx_ring) 2068 { 2069 int idx = rx_ring->index; 2070 u32 rbmr; 2071 2072 enetc_rxbdr_wr(hw, idx, ENETC_RBBAR0, 2073 lower_32_bits(rx_ring->bd_dma_base)); 2074 2075 enetc_rxbdr_wr(hw, idx, ENETC_RBBAR1, 2076 upper_32_bits(rx_ring->bd_dma_base)); 2077 2078 WARN_ON(!IS_ALIGNED(rx_ring->bd_count, 64)); /* multiple of 64 */ 2079 enetc_rxbdr_wr(hw, idx, ENETC_RBLENR, 2080 ENETC_RTBLENR_LEN(rx_ring->bd_count)); 2081 2082 if (rx_ring->xdp.prog) 2083 enetc_rxbdr_wr(hw, idx, ENETC_RBBSR, ENETC_RXB_DMA_SIZE_XDP); 2084 else 2085 enetc_rxbdr_wr(hw, idx, ENETC_RBBSR, ENETC_RXB_DMA_SIZE); 2086 2087 enetc_rxbdr_wr(hw, idx, ENETC_RBPIR, 0); 2088 2089 /* enable Rx ints by setting pkt thr to 1 */ 2090 enetc_rxbdr_wr(hw, idx, ENETC_RBICR0, ENETC_RBICR0_ICEN | 0x1); 2091 2092 rbmr = ENETC_RBMR_EN; 2093 2094 if (rx_ring->ext_en) 2095 rbmr |= ENETC_RBMR_BDS; 2096 2097 if (rx_ring->ndev->features & NETIF_F_HW_VLAN_CTAG_RX) 2098 rbmr |= ENETC_RBMR_VTE; 2099 2100 rx_ring->rcir = hw->reg + ENETC_BDR(RX, idx, ENETC_RBCIR); 2101 rx_ring->idr = hw->reg + ENETC_SIRXIDR; 2102 2103 enetc_lock_mdio(); 2104 enetc_refill_rx_ring(rx_ring, enetc_bd_unused(rx_ring)); 2105 enetc_unlock_mdio(); 2106 2107 /* enable ring */ 2108 enetc_rxbdr_wr(hw, idx, ENETC_RBMR, rbmr); 2109 } 2110 2111 static void enetc_setup_bdrs(struct enetc_ndev_priv *priv) 2112 { 2113 int i; 2114 2115 for (i = 0; i < priv->num_tx_rings; i++) 2116 enetc_setup_txbdr(&priv->si->hw, priv->tx_ring[i]); 2117 2118 for (i = 0; i < priv->num_rx_rings; i++) 2119 enetc_setup_rxbdr(&priv->si->hw, priv->rx_ring[i]); 2120 } 2121 2122 static void enetc_clear_rxbdr(struct enetc_hw *hw, struct enetc_bdr *rx_ring) 2123 { 2124 int idx = rx_ring->index; 2125 2126 /* disable EN bit on ring */ 2127 enetc_rxbdr_wr(hw, idx, ENETC_RBMR, 0); 2128 } 2129 2130 static void enetc_clear_txbdr(struct enetc_hw *hw, struct enetc_bdr *tx_ring) 2131 { 2132 int delay = 8, timeout = 100; 2133 int idx = tx_ring->index; 2134 2135 /* disable EN bit on ring */ 2136 enetc_txbdr_wr(hw, idx, ENETC_TBMR, 0); 2137 2138 /* wait for busy to clear */ 2139 while (delay < timeout && 2140 enetc_txbdr_rd(hw, idx, ENETC_TBSR) & ENETC_TBSR_BUSY) { 2141 msleep(delay); 2142 delay *= 2; 2143 } 2144 2145 if (delay >= timeout) 2146 netdev_warn(tx_ring->ndev, "timeout for tx ring #%d clear\n", 2147 idx); 2148 } 2149 2150 static void enetc_clear_bdrs(struct enetc_ndev_priv *priv) 2151 { 2152 int i; 2153 2154 for (i = 0; i < priv->num_tx_rings; i++) 2155 enetc_clear_txbdr(&priv->si->hw, priv->tx_ring[i]); 2156 2157 for (i = 0; i < priv->num_rx_rings; i++) 2158 enetc_clear_rxbdr(&priv->si->hw, priv->rx_ring[i]); 2159 2160 udelay(1); 2161 } 2162 2163 static int enetc_setup_irqs(struct enetc_ndev_priv *priv) 2164 { 2165 struct pci_dev *pdev = priv->si->pdev; 2166 int i, j, err; 2167 2168 for (i = 0; i < priv->bdr_int_num; i++) { 2169 int irq = pci_irq_vector(pdev, ENETC_BDR_INT_BASE_IDX + i); 2170 struct enetc_int_vector *v = priv->int_vector[i]; 2171 int entry = ENETC_BDR_INT_BASE_IDX + i; 2172 struct enetc_hw *hw = &priv->si->hw; 2173 2174 snprintf(v->name, sizeof(v->name), "%s-rxtx%d", 2175 priv->ndev->name, i); 2176 err = request_irq(irq, enetc_msix, 0, v->name, v); 2177 if (err) { 2178 dev_err(priv->dev, "request_irq() failed!\n"); 2179 goto irq_err; 2180 } 2181 disable_irq(irq); 2182 2183 v->tbier_base = hw->reg + ENETC_BDR(TX, 0, ENETC_TBIER); 2184 v->rbier = hw->reg + ENETC_BDR(RX, i, ENETC_RBIER); 2185 v->ricr1 = hw->reg + ENETC_BDR(RX, i, ENETC_RBICR1); 2186 2187 enetc_wr(hw, ENETC_SIMSIRRV(i), entry); 2188 2189 for (j = 0; j < v->count_tx_rings; j++) { 2190 int idx = v->tx_ring[j].index; 2191 2192 enetc_wr(hw, ENETC_SIMSITRV(idx), entry); 2193 } 2194 irq_set_affinity_hint(irq, get_cpu_mask(i % num_online_cpus())); 2195 } 2196 2197 return 0; 2198 2199 irq_err: 2200 while (i--) { 2201 int irq = pci_irq_vector(pdev, ENETC_BDR_INT_BASE_IDX + i); 2202 2203 irq_set_affinity_hint(irq, NULL); 2204 free_irq(irq, priv->int_vector[i]); 2205 } 2206 2207 return err; 2208 } 2209 2210 static void enetc_free_irqs(struct enetc_ndev_priv *priv) 2211 { 2212 struct pci_dev *pdev = priv->si->pdev; 2213 int i; 2214 2215 for (i = 0; i < priv->bdr_int_num; i++) { 2216 int irq = pci_irq_vector(pdev, ENETC_BDR_INT_BASE_IDX + i); 2217 2218 irq_set_affinity_hint(irq, NULL); 2219 free_irq(irq, priv->int_vector[i]); 2220 } 2221 } 2222 2223 static void enetc_setup_interrupts(struct enetc_ndev_priv *priv) 2224 { 2225 struct enetc_hw *hw = &priv->si->hw; 2226 u32 icpt, ictt; 2227 int i; 2228 2229 /* enable Tx & Rx event indication */ 2230 if (priv->ic_mode & 2231 (ENETC_IC_RX_MANUAL | ENETC_IC_RX_ADAPTIVE)) { 2232 icpt = ENETC_RBICR0_SET_ICPT(ENETC_RXIC_PKTTHR); 2233 /* init to non-0 minimum, will be adjusted later */ 2234 ictt = 0x1; 2235 } else { 2236 icpt = 0x1; /* enable Rx ints by setting pkt thr to 1 */ 2237 ictt = 0; 2238 } 2239 2240 for (i = 0; i < priv->num_rx_rings; i++) { 2241 enetc_rxbdr_wr(hw, i, ENETC_RBICR1, ictt); 2242 enetc_rxbdr_wr(hw, i, ENETC_RBICR0, ENETC_RBICR0_ICEN | icpt); 2243 enetc_rxbdr_wr(hw, i, ENETC_RBIER, ENETC_RBIER_RXTIE); 2244 } 2245 2246 if (priv->ic_mode & ENETC_IC_TX_MANUAL) 2247 icpt = ENETC_TBICR0_SET_ICPT(ENETC_TXIC_PKTTHR); 2248 else 2249 icpt = 0x1; /* enable Tx ints by setting pkt thr to 1 */ 2250 2251 for (i = 0; i < priv->num_tx_rings; i++) { 2252 enetc_txbdr_wr(hw, i, ENETC_TBICR1, priv->tx_ictt); 2253 enetc_txbdr_wr(hw, i, ENETC_TBICR0, ENETC_TBICR0_ICEN | icpt); 2254 enetc_txbdr_wr(hw, i, ENETC_TBIER, ENETC_TBIER_TXTIE); 2255 } 2256 } 2257 2258 static void enetc_clear_interrupts(struct enetc_ndev_priv *priv) 2259 { 2260 int i; 2261 2262 for (i = 0; i < priv->num_tx_rings; i++) 2263 enetc_txbdr_wr(&priv->si->hw, i, ENETC_TBIER, 0); 2264 2265 for (i = 0; i < priv->num_rx_rings; i++) 2266 enetc_rxbdr_wr(&priv->si->hw, i, ENETC_RBIER, 0); 2267 } 2268 2269 static int enetc_phylink_connect(struct net_device *ndev) 2270 { 2271 struct enetc_ndev_priv *priv = netdev_priv(ndev); 2272 struct ethtool_eee edata; 2273 int err; 2274 2275 if (!priv->phylink) 2276 return 0; /* phy-less mode */ 2277 2278 err = phylink_of_phy_connect(priv->phylink, priv->dev->of_node, 0); 2279 if (err) { 2280 dev_err(&ndev->dev, "could not attach to PHY\n"); 2281 return err; 2282 } 2283 2284 /* disable EEE autoneg, until ENETC driver supports it */ 2285 memset(&edata, 0, sizeof(struct ethtool_eee)); 2286 phylink_ethtool_set_eee(priv->phylink, &edata); 2287 2288 return 0; 2289 } 2290 2291 static void enetc_tx_onestep_tstamp(struct work_struct *work) 2292 { 2293 struct enetc_ndev_priv *priv; 2294 struct sk_buff *skb; 2295 2296 priv = container_of(work, struct enetc_ndev_priv, tx_onestep_tstamp); 2297 2298 netif_tx_lock(priv->ndev); 2299 2300 clear_bit_unlock(ENETC_TX_ONESTEP_TSTAMP_IN_PROGRESS, &priv->flags); 2301 skb = skb_dequeue(&priv->tx_skbs); 2302 if (skb) 2303 enetc_start_xmit(skb, priv->ndev); 2304 2305 netif_tx_unlock(priv->ndev); 2306 } 2307 2308 static void enetc_tx_onestep_tstamp_init(struct enetc_ndev_priv *priv) 2309 { 2310 INIT_WORK(&priv->tx_onestep_tstamp, enetc_tx_onestep_tstamp); 2311 skb_queue_head_init(&priv->tx_skbs); 2312 } 2313 2314 void enetc_start(struct net_device *ndev) 2315 { 2316 struct enetc_ndev_priv *priv = netdev_priv(ndev); 2317 int i; 2318 2319 enetc_setup_interrupts(priv); 2320 2321 for (i = 0; i < priv->bdr_int_num; i++) { 2322 int irq = pci_irq_vector(priv->si->pdev, 2323 ENETC_BDR_INT_BASE_IDX + i); 2324 2325 napi_enable(&priv->int_vector[i]->napi); 2326 enable_irq(irq); 2327 } 2328 2329 if (priv->phylink) 2330 phylink_start(priv->phylink); 2331 else 2332 netif_carrier_on(ndev); 2333 2334 netif_tx_start_all_queues(ndev); 2335 } 2336 2337 int enetc_open(struct net_device *ndev) 2338 { 2339 struct enetc_ndev_priv *priv = netdev_priv(ndev); 2340 int num_stack_tx_queues; 2341 int err; 2342 2343 err = enetc_setup_irqs(priv); 2344 if (err) 2345 return err; 2346 2347 err = enetc_phylink_connect(ndev); 2348 if (err) 2349 goto err_phy_connect; 2350 2351 err = enetc_alloc_tx_resources(priv); 2352 if (err) 2353 goto err_alloc_tx; 2354 2355 err = enetc_alloc_rx_resources(priv); 2356 if (err) 2357 goto err_alloc_rx; 2358 2359 num_stack_tx_queues = enetc_num_stack_tx_queues(priv); 2360 2361 err = netif_set_real_num_tx_queues(ndev, num_stack_tx_queues); 2362 if (err) 2363 goto err_set_queues; 2364 2365 err = netif_set_real_num_rx_queues(ndev, priv->num_rx_rings); 2366 if (err) 2367 goto err_set_queues; 2368 2369 enetc_tx_onestep_tstamp_init(priv); 2370 enetc_setup_bdrs(priv); 2371 enetc_start(ndev); 2372 2373 return 0; 2374 2375 err_set_queues: 2376 enetc_free_rx_resources(priv); 2377 err_alloc_rx: 2378 enetc_free_tx_resources(priv); 2379 err_alloc_tx: 2380 if (priv->phylink) 2381 phylink_disconnect_phy(priv->phylink); 2382 err_phy_connect: 2383 enetc_free_irqs(priv); 2384 2385 return err; 2386 } 2387 2388 void enetc_stop(struct net_device *ndev) 2389 { 2390 struct enetc_ndev_priv *priv = netdev_priv(ndev); 2391 int i; 2392 2393 netif_tx_stop_all_queues(ndev); 2394 2395 for (i = 0; i < priv->bdr_int_num; i++) { 2396 int irq = pci_irq_vector(priv->si->pdev, 2397 ENETC_BDR_INT_BASE_IDX + i); 2398 2399 disable_irq(irq); 2400 napi_synchronize(&priv->int_vector[i]->napi); 2401 napi_disable(&priv->int_vector[i]->napi); 2402 } 2403 2404 if (priv->phylink) 2405 phylink_stop(priv->phylink); 2406 else 2407 netif_carrier_off(ndev); 2408 2409 enetc_clear_interrupts(priv); 2410 } 2411 2412 int enetc_close(struct net_device *ndev) 2413 { 2414 struct enetc_ndev_priv *priv = netdev_priv(ndev); 2415 2416 enetc_stop(ndev); 2417 enetc_clear_bdrs(priv); 2418 2419 if (priv->phylink) 2420 phylink_disconnect_phy(priv->phylink); 2421 enetc_free_rxtx_rings(priv); 2422 enetc_free_rx_resources(priv); 2423 enetc_free_tx_resources(priv); 2424 enetc_free_irqs(priv); 2425 2426 return 0; 2427 } 2428 2429 static int enetc_setup_tc_mqprio(struct net_device *ndev, void *type_data) 2430 { 2431 struct enetc_ndev_priv *priv = netdev_priv(ndev); 2432 struct tc_mqprio_qopt *mqprio = type_data; 2433 struct enetc_bdr *tx_ring; 2434 int num_stack_tx_queues; 2435 u8 num_tc; 2436 int i; 2437 2438 num_stack_tx_queues = enetc_num_stack_tx_queues(priv); 2439 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS; 2440 num_tc = mqprio->num_tc; 2441 2442 if (!num_tc) { 2443 netdev_reset_tc(ndev); 2444 netif_set_real_num_tx_queues(ndev, num_stack_tx_queues); 2445 2446 /* Reset all ring priorities to 0 */ 2447 for (i = 0; i < priv->num_tx_rings; i++) { 2448 tx_ring = priv->tx_ring[i]; 2449 enetc_set_bdr_prio(&priv->si->hw, tx_ring->index, 0); 2450 } 2451 2452 return 0; 2453 } 2454 2455 /* Check if we have enough BD rings available to accommodate all TCs */ 2456 if (num_tc > num_stack_tx_queues) { 2457 netdev_err(ndev, "Max %d traffic classes supported\n", 2458 priv->num_tx_rings); 2459 return -EINVAL; 2460 } 2461 2462 /* For the moment, we use only one BD ring per TC. 2463 * 2464 * Configure num_tc BD rings with increasing priorities. 2465 */ 2466 for (i = 0; i < num_tc; i++) { 2467 tx_ring = priv->tx_ring[i]; 2468 enetc_set_bdr_prio(&priv->si->hw, tx_ring->index, i); 2469 } 2470 2471 /* Reset the number of netdev queues based on the TC count */ 2472 netif_set_real_num_tx_queues(ndev, num_tc); 2473 2474 netdev_set_num_tc(ndev, num_tc); 2475 2476 /* Each TC is associated with one netdev queue */ 2477 for (i = 0; i < num_tc; i++) 2478 netdev_set_tc_queue(ndev, i, 1, i); 2479 2480 return 0; 2481 } 2482 2483 int enetc_setup_tc(struct net_device *ndev, enum tc_setup_type type, 2484 void *type_data) 2485 { 2486 switch (type) { 2487 case TC_SETUP_QDISC_MQPRIO: 2488 return enetc_setup_tc_mqprio(ndev, type_data); 2489 case TC_SETUP_QDISC_TAPRIO: 2490 return enetc_setup_tc_taprio(ndev, type_data); 2491 case TC_SETUP_QDISC_CBS: 2492 return enetc_setup_tc_cbs(ndev, type_data); 2493 case TC_SETUP_QDISC_ETF: 2494 return enetc_setup_tc_txtime(ndev, type_data); 2495 case TC_SETUP_BLOCK: 2496 return enetc_setup_tc_psfp(ndev, type_data); 2497 default: 2498 return -EOPNOTSUPP; 2499 } 2500 } 2501 2502 static int enetc_setup_xdp_prog(struct net_device *dev, struct bpf_prog *prog, 2503 struct netlink_ext_ack *extack) 2504 { 2505 struct enetc_ndev_priv *priv = netdev_priv(dev); 2506 struct bpf_prog *old_prog; 2507 bool is_up; 2508 int i; 2509 2510 /* The buffer layout is changing, so we need to drain the old 2511 * RX buffers and seed new ones. 2512 */ 2513 is_up = netif_running(dev); 2514 if (is_up) 2515 dev_close(dev); 2516 2517 old_prog = xchg(&priv->xdp_prog, prog); 2518 if (old_prog) 2519 bpf_prog_put(old_prog); 2520 2521 for (i = 0; i < priv->num_rx_rings; i++) { 2522 struct enetc_bdr *rx_ring = priv->rx_ring[i]; 2523 2524 rx_ring->xdp.prog = prog; 2525 2526 if (prog) 2527 rx_ring->buffer_offset = XDP_PACKET_HEADROOM; 2528 else 2529 rx_ring->buffer_offset = ENETC_RXB_PAD; 2530 } 2531 2532 if (is_up) 2533 return dev_open(dev, extack); 2534 2535 return 0; 2536 } 2537 2538 int enetc_setup_bpf(struct net_device *dev, struct netdev_bpf *xdp) 2539 { 2540 switch (xdp->command) { 2541 case XDP_SETUP_PROG: 2542 return enetc_setup_xdp_prog(dev, xdp->prog, xdp->extack); 2543 default: 2544 return -EINVAL; 2545 } 2546 2547 return 0; 2548 } 2549 2550 struct net_device_stats *enetc_get_stats(struct net_device *ndev) 2551 { 2552 struct enetc_ndev_priv *priv = netdev_priv(ndev); 2553 struct net_device_stats *stats = &ndev->stats; 2554 unsigned long packets = 0, bytes = 0; 2555 int i; 2556 2557 for (i = 0; i < priv->num_rx_rings; i++) { 2558 packets += priv->rx_ring[i]->stats.packets; 2559 bytes += priv->rx_ring[i]->stats.bytes; 2560 } 2561 2562 stats->rx_packets = packets; 2563 stats->rx_bytes = bytes; 2564 bytes = 0; 2565 packets = 0; 2566 2567 for (i = 0; i < priv->num_tx_rings; i++) { 2568 packets += priv->tx_ring[i]->stats.packets; 2569 bytes += priv->tx_ring[i]->stats.bytes; 2570 } 2571 2572 stats->tx_packets = packets; 2573 stats->tx_bytes = bytes; 2574 2575 return stats; 2576 } 2577 2578 static int enetc_set_rss(struct net_device *ndev, int en) 2579 { 2580 struct enetc_ndev_priv *priv = netdev_priv(ndev); 2581 struct enetc_hw *hw = &priv->si->hw; 2582 u32 reg; 2583 2584 enetc_wr(hw, ENETC_SIRBGCR, priv->num_rx_rings); 2585 2586 reg = enetc_rd(hw, ENETC_SIMR); 2587 reg &= ~ENETC_SIMR_RSSE; 2588 reg |= (en) ? ENETC_SIMR_RSSE : 0; 2589 enetc_wr(hw, ENETC_SIMR, reg); 2590 2591 return 0; 2592 } 2593 2594 static int enetc_set_psfp(struct net_device *ndev, int en) 2595 { 2596 struct enetc_ndev_priv *priv = netdev_priv(ndev); 2597 int err; 2598 2599 if (en) { 2600 err = enetc_psfp_enable(priv); 2601 if (err) 2602 return err; 2603 2604 priv->active_offloads |= ENETC_F_QCI; 2605 return 0; 2606 } 2607 2608 err = enetc_psfp_disable(priv); 2609 if (err) 2610 return err; 2611 2612 priv->active_offloads &= ~ENETC_F_QCI; 2613 2614 return 0; 2615 } 2616 2617 static void enetc_enable_rxvlan(struct net_device *ndev, bool en) 2618 { 2619 struct enetc_ndev_priv *priv = netdev_priv(ndev); 2620 int i; 2621 2622 for (i = 0; i < priv->num_rx_rings; i++) 2623 enetc_bdr_enable_rxvlan(&priv->si->hw, i, en); 2624 } 2625 2626 static void enetc_enable_txvlan(struct net_device *ndev, bool en) 2627 { 2628 struct enetc_ndev_priv *priv = netdev_priv(ndev); 2629 int i; 2630 2631 for (i = 0; i < priv->num_tx_rings; i++) 2632 enetc_bdr_enable_txvlan(&priv->si->hw, i, en); 2633 } 2634 2635 int enetc_set_features(struct net_device *ndev, 2636 netdev_features_t features) 2637 { 2638 netdev_features_t changed = ndev->features ^ features; 2639 int err = 0; 2640 2641 if (changed & NETIF_F_RXHASH) 2642 enetc_set_rss(ndev, !!(features & NETIF_F_RXHASH)); 2643 2644 if (changed & NETIF_F_HW_VLAN_CTAG_RX) 2645 enetc_enable_rxvlan(ndev, 2646 !!(features & NETIF_F_HW_VLAN_CTAG_RX)); 2647 2648 if (changed & NETIF_F_HW_VLAN_CTAG_TX) 2649 enetc_enable_txvlan(ndev, 2650 !!(features & NETIF_F_HW_VLAN_CTAG_TX)); 2651 2652 if (changed & NETIF_F_HW_TC) 2653 err = enetc_set_psfp(ndev, !!(features & NETIF_F_HW_TC)); 2654 2655 return err; 2656 } 2657 2658 #ifdef CONFIG_FSL_ENETC_PTP_CLOCK 2659 static int enetc_hwtstamp_set(struct net_device *ndev, struct ifreq *ifr) 2660 { 2661 struct enetc_ndev_priv *priv = netdev_priv(ndev); 2662 struct hwtstamp_config config; 2663 int ao; 2664 2665 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 2666 return -EFAULT; 2667 2668 switch (config.tx_type) { 2669 case HWTSTAMP_TX_OFF: 2670 priv->active_offloads &= ~ENETC_F_TX_TSTAMP_MASK; 2671 break; 2672 case HWTSTAMP_TX_ON: 2673 priv->active_offloads &= ~ENETC_F_TX_TSTAMP_MASK; 2674 priv->active_offloads |= ENETC_F_TX_TSTAMP; 2675 break; 2676 case HWTSTAMP_TX_ONESTEP_SYNC: 2677 priv->active_offloads &= ~ENETC_F_TX_TSTAMP_MASK; 2678 priv->active_offloads |= ENETC_F_TX_ONESTEP_SYNC_TSTAMP; 2679 break; 2680 default: 2681 return -ERANGE; 2682 } 2683 2684 ao = priv->active_offloads; 2685 switch (config.rx_filter) { 2686 case HWTSTAMP_FILTER_NONE: 2687 priv->active_offloads &= ~ENETC_F_RX_TSTAMP; 2688 break; 2689 default: 2690 priv->active_offloads |= ENETC_F_RX_TSTAMP; 2691 config.rx_filter = HWTSTAMP_FILTER_ALL; 2692 } 2693 2694 if (netif_running(ndev) && ao != priv->active_offloads) { 2695 enetc_close(ndev); 2696 enetc_open(ndev); 2697 } 2698 2699 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? 2700 -EFAULT : 0; 2701 } 2702 2703 static int enetc_hwtstamp_get(struct net_device *ndev, struct ifreq *ifr) 2704 { 2705 struct enetc_ndev_priv *priv = netdev_priv(ndev); 2706 struct hwtstamp_config config; 2707 2708 config.flags = 0; 2709 2710 if (priv->active_offloads & ENETC_F_TX_ONESTEP_SYNC_TSTAMP) 2711 config.tx_type = HWTSTAMP_TX_ONESTEP_SYNC; 2712 else if (priv->active_offloads & ENETC_F_TX_TSTAMP) 2713 config.tx_type = HWTSTAMP_TX_ON; 2714 else 2715 config.tx_type = HWTSTAMP_TX_OFF; 2716 2717 config.rx_filter = (priv->active_offloads & ENETC_F_RX_TSTAMP) ? 2718 HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE; 2719 2720 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? 2721 -EFAULT : 0; 2722 } 2723 #endif 2724 2725 int enetc_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) 2726 { 2727 struct enetc_ndev_priv *priv = netdev_priv(ndev); 2728 #ifdef CONFIG_FSL_ENETC_PTP_CLOCK 2729 if (cmd == SIOCSHWTSTAMP) 2730 return enetc_hwtstamp_set(ndev, rq); 2731 if (cmd == SIOCGHWTSTAMP) 2732 return enetc_hwtstamp_get(ndev, rq); 2733 #endif 2734 2735 if (!priv->phylink) 2736 return -EOPNOTSUPP; 2737 2738 return phylink_mii_ioctl(priv->phylink, rq, cmd); 2739 } 2740 2741 int enetc_alloc_msix(struct enetc_ndev_priv *priv) 2742 { 2743 struct pci_dev *pdev = priv->si->pdev; 2744 int first_xdp_tx_ring; 2745 int i, n, err, nvec; 2746 int v_tx_rings; 2747 2748 nvec = ENETC_BDR_INT_BASE_IDX + priv->bdr_int_num; 2749 /* allocate MSIX for both messaging and Rx/Tx interrupts */ 2750 n = pci_alloc_irq_vectors(pdev, nvec, nvec, PCI_IRQ_MSIX); 2751 2752 if (n < 0) 2753 return n; 2754 2755 if (n != nvec) 2756 return -EPERM; 2757 2758 /* # of tx rings per int vector */ 2759 v_tx_rings = priv->num_tx_rings / priv->bdr_int_num; 2760 2761 for (i = 0; i < priv->bdr_int_num; i++) { 2762 struct enetc_int_vector *v; 2763 struct enetc_bdr *bdr; 2764 int j; 2765 2766 v = kzalloc(struct_size(v, tx_ring, v_tx_rings), GFP_KERNEL); 2767 if (!v) { 2768 err = -ENOMEM; 2769 goto fail; 2770 } 2771 2772 priv->int_vector[i] = v; 2773 2774 bdr = &v->rx_ring; 2775 bdr->index = i; 2776 bdr->ndev = priv->ndev; 2777 bdr->dev = priv->dev; 2778 bdr->bd_count = priv->rx_bd_count; 2779 bdr->buffer_offset = ENETC_RXB_PAD; 2780 priv->rx_ring[i] = bdr; 2781 2782 err = xdp_rxq_info_reg(&bdr->xdp.rxq, priv->ndev, i, 0); 2783 if (err) { 2784 kfree(v); 2785 goto fail; 2786 } 2787 2788 err = xdp_rxq_info_reg_mem_model(&bdr->xdp.rxq, 2789 MEM_TYPE_PAGE_SHARED, NULL); 2790 if (err) { 2791 xdp_rxq_info_unreg(&bdr->xdp.rxq); 2792 kfree(v); 2793 goto fail; 2794 } 2795 2796 /* init defaults for adaptive IC */ 2797 if (priv->ic_mode & ENETC_IC_RX_ADAPTIVE) { 2798 v->rx_ictt = 0x1; 2799 v->rx_dim_en = true; 2800 } 2801 INIT_WORK(&v->rx_dim.work, enetc_rx_dim_work); 2802 netif_napi_add(priv->ndev, &v->napi, enetc_poll, 2803 NAPI_POLL_WEIGHT); 2804 v->count_tx_rings = v_tx_rings; 2805 2806 for (j = 0; j < v_tx_rings; j++) { 2807 int idx; 2808 2809 /* default tx ring mapping policy */ 2810 idx = priv->bdr_int_num * j + i; 2811 __set_bit(idx, &v->tx_rings_map); 2812 bdr = &v->tx_ring[j]; 2813 bdr->index = idx; 2814 bdr->ndev = priv->ndev; 2815 bdr->dev = priv->dev; 2816 bdr->bd_count = priv->tx_bd_count; 2817 priv->tx_ring[idx] = bdr; 2818 } 2819 } 2820 2821 first_xdp_tx_ring = priv->num_tx_rings - num_possible_cpus(); 2822 priv->xdp_tx_ring = &priv->tx_ring[first_xdp_tx_ring]; 2823 2824 return 0; 2825 2826 fail: 2827 while (i--) { 2828 struct enetc_int_vector *v = priv->int_vector[i]; 2829 struct enetc_bdr *rx_ring = &v->rx_ring; 2830 2831 xdp_rxq_info_unreg_mem_model(&rx_ring->xdp.rxq); 2832 xdp_rxq_info_unreg(&rx_ring->xdp.rxq); 2833 netif_napi_del(&v->napi); 2834 cancel_work_sync(&v->rx_dim.work); 2835 kfree(v); 2836 } 2837 2838 pci_free_irq_vectors(pdev); 2839 2840 return err; 2841 } 2842 2843 void enetc_free_msix(struct enetc_ndev_priv *priv) 2844 { 2845 int i; 2846 2847 for (i = 0; i < priv->bdr_int_num; i++) { 2848 struct enetc_int_vector *v = priv->int_vector[i]; 2849 struct enetc_bdr *rx_ring = &v->rx_ring; 2850 2851 xdp_rxq_info_unreg_mem_model(&rx_ring->xdp.rxq); 2852 xdp_rxq_info_unreg(&rx_ring->xdp.rxq); 2853 netif_napi_del(&v->napi); 2854 cancel_work_sync(&v->rx_dim.work); 2855 } 2856 2857 for (i = 0; i < priv->num_rx_rings; i++) 2858 priv->rx_ring[i] = NULL; 2859 2860 for (i = 0; i < priv->num_tx_rings; i++) 2861 priv->tx_ring[i] = NULL; 2862 2863 for (i = 0; i < priv->bdr_int_num; i++) { 2864 kfree(priv->int_vector[i]); 2865 priv->int_vector[i] = NULL; 2866 } 2867 2868 /* disable all MSIX for this device */ 2869 pci_free_irq_vectors(priv->si->pdev); 2870 } 2871 2872 static void enetc_kfree_si(struct enetc_si *si) 2873 { 2874 char *p = (char *)si - si->pad; 2875 2876 kfree(p); 2877 } 2878 2879 static void enetc_detect_errata(struct enetc_si *si) 2880 { 2881 if (si->pdev->revision == ENETC_REV1) 2882 si->errata = ENETC_ERR_VLAN_ISOL | ENETC_ERR_UCMCSWP; 2883 } 2884 2885 int enetc_pci_probe(struct pci_dev *pdev, const char *name, int sizeof_priv) 2886 { 2887 struct enetc_si *si, *p; 2888 struct enetc_hw *hw; 2889 size_t alloc_size; 2890 int err, len; 2891 2892 pcie_flr(pdev); 2893 err = pci_enable_device_mem(pdev); 2894 if (err) 2895 return dev_err_probe(&pdev->dev, err, "device enable failed\n"); 2896 2897 /* set up for high or low dma */ 2898 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2899 if (err) { 2900 dev_err(&pdev->dev, "DMA configuration failed: 0x%x\n", err); 2901 goto err_dma; 2902 } 2903 2904 err = pci_request_mem_regions(pdev, name); 2905 if (err) { 2906 dev_err(&pdev->dev, "pci_request_regions failed err=%d\n", err); 2907 goto err_pci_mem_reg; 2908 } 2909 2910 pci_set_master(pdev); 2911 2912 alloc_size = sizeof(struct enetc_si); 2913 if (sizeof_priv) { 2914 /* align priv to 32B */ 2915 alloc_size = ALIGN(alloc_size, ENETC_SI_ALIGN); 2916 alloc_size += sizeof_priv; 2917 } 2918 /* force 32B alignment for enetc_si */ 2919 alloc_size += ENETC_SI_ALIGN - 1; 2920 2921 p = kzalloc(alloc_size, GFP_KERNEL); 2922 if (!p) { 2923 err = -ENOMEM; 2924 goto err_alloc_si; 2925 } 2926 2927 si = PTR_ALIGN(p, ENETC_SI_ALIGN); 2928 si->pad = (char *)si - (char *)p; 2929 2930 pci_set_drvdata(pdev, si); 2931 si->pdev = pdev; 2932 hw = &si->hw; 2933 2934 len = pci_resource_len(pdev, ENETC_BAR_REGS); 2935 hw->reg = ioremap(pci_resource_start(pdev, ENETC_BAR_REGS), len); 2936 if (!hw->reg) { 2937 err = -ENXIO; 2938 dev_err(&pdev->dev, "ioremap() failed\n"); 2939 goto err_ioremap; 2940 } 2941 if (len > ENETC_PORT_BASE) 2942 hw->port = hw->reg + ENETC_PORT_BASE; 2943 if (len > ENETC_GLOBAL_BASE) 2944 hw->global = hw->reg + ENETC_GLOBAL_BASE; 2945 2946 enetc_detect_errata(si); 2947 2948 return 0; 2949 2950 err_ioremap: 2951 enetc_kfree_si(si); 2952 err_alloc_si: 2953 pci_release_mem_regions(pdev); 2954 err_pci_mem_reg: 2955 err_dma: 2956 pci_disable_device(pdev); 2957 2958 return err; 2959 } 2960 2961 void enetc_pci_remove(struct pci_dev *pdev) 2962 { 2963 struct enetc_si *si = pci_get_drvdata(pdev); 2964 struct enetc_hw *hw = &si->hw; 2965 2966 iounmap(hw->reg); 2967 enetc_kfree_si(si); 2968 pci_release_mem_regions(pdev); 2969 pci_disable_device(pdev); 2970 } 2971