1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2 /* Copyright 2017-2019 NXP */ 3 4 #include "enetc.h" 5 #include <linux/bpf_trace.h> 6 #include <linux/tcp.h> 7 #include <linux/udp.h> 8 #include <linux/vmalloc.h> 9 #include <linux/ptp_classify.h> 10 #include <net/ip6_checksum.h> 11 #include <net/pkt_sched.h> 12 #include <net/tso.h> 13 14 u32 enetc_port_mac_rd(struct enetc_si *si, u32 reg) 15 { 16 return enetc_port_rd(&si->hw, reg); 17 } 18 EXPORT_SYMBOL_GPL(enetc_port_mac_rd); 19 20 void enetc_port_mac_wr(struct enetc_si *si, u32 reg, u32 val) 21 { 22 enetc_port_wr(&si->hw, reg, val); 23 if (si->hw_features & ENETC_SI_F_QBU) 24 enetc_port_wr(&si->hw, reg + ENETC_PMAC_OFFSET, val); 25 } 26 EXPORT_SYMBOL_GPL(enetc_port_mac_wr); 27 28 static void enetc_change_preemptible_tcs(struct enetc_ndev_priv *priv, 29 u8 preemptible_tcs) 30 { 31 priv->preemptible_tcs = preemptible_tcs; 32 enetc_mm_commit_preemptible_tcs(priv); 33 } 34 35 static int enetc_num_stack_tx_queues(struct enetc_ndev_priv *priv) 36 { 37 int num_tx_rings = priv->num_tx_rings; 38 39 if (priv->xdp_prog) 40 return num_tx_rings - num_possible_cpus(); 41 42 return num_tx_rings; 43 } 44 45 static struct enetc_bdr *enetc_rx_ring_from_xdp_tx_ring(struct enetc_ndev_priv *priv, 46 struct enetc_bdr *tx_ring) 47 { 48 int index = &priv->tx_ring[tx_ring->index] - priv->xdp_tx_ring; 49 50 return priv->rx_ring[index]; 51 } 52 53 static struct sk_buff *enetc_tx_swbd_get_skb(struct enetc_tx_swbd *tx_swbd) 54 { 55 if (tx_swbd->is_xdp_tx || tx_swbd->is_xdp_redirect) 56 return NULL; 57 58 return tx_swbd->skb; 59 } 60 61 static struct xdp_frame * 62 enetc_tx_swbd_get_xdp_frame(struct enetc_tx_swbd *tx_swbd) 63 { 64 if (tx_swbd->is_xdp_redirect) 65 return tx_swbd->xdp_frame; 66 67 return NULL; 68 } 69 70 static void enetc_unmap_tx_buff(struct enetc_bdr *tx_ring, 71 struct enetc_tx_swbd *tx_swbd) 72 { 73 /* For XDP_TX, pages come from RX, whereas for the other contexts where 74 * we have is_dma_page_set, those come from skb_frag_dma_map. We need 75 * to match the DMA mapping length, so we need to differentiate those. 76 */ 77 if (tx_swbd->is_dma_page) 78 dma_unmap_page(tx_ring->dev, tx_swbd->dma, 79 tx_swbd->is_xdp_tx ? PAGE_SIZE : tx_swbd->len, 80 tx_swbd->dir); 81 else 82 dma_unmap_single(tx_ring->dev, tx_swbd->dma, 83 tx_swbd->len, tx_swbd->dir); 84 tx_swbd->dma = 0; 85 } 86 87 static void enetc_free_tx_frame(struct enetc_bdr *tx_ring, 88 struct enetc_tx_swbd *tx_swbd) 89 { 90 struct xdp_frame *xdp_frame = enetc_tx_swbd_get_xdp_frame(tx_swbd); 91 struct sk_buff *skb = enetc_tx_swbd_get_skb(tx_swbd); 92 93 if (tx_swbd->dma) 94 enetc_unmap_tx_buff(tx_ring, tx_swbd); 95 96 if (xdp_frame) { 97 xdp_return_frame(tx_swbd->xdp_frame); 98 tx_swbd->xdp_frame = NULL; 99 } else if (skb) { 100 dev_kfree_skb_any(skb); 101 tx_swbd->skb = NULL; 102 } 103 } 104 105 /* Let H/W know BD ring has been updated */ 106 static void enetc_update_tx_ring_tail(struct enetc_bdr *tx_ring) 107 { 108 /* includes wmb() */ 109 enetc_wr_reg_hot(tx_ring->tpir, tx_ring->next_to_use); 110 } 111 112 static int enetc_ptp_parse(struct sk_buff *skb, u8 *udp, 113 u8 *msgtype, u8 *twostep, 114 u16 *correction_offset, u16 *body_offset) 115 { 116 unsigned int ptp_class; 117 struct ptp_header *hdr; 118 unsigned int type; 119 u8 *base; 120 121 ptp_class = ptp_classify_raw(skb); 122 if (ptp_class == PTP_CLASS_NONE) 123 return -EINVAL; 124 125 hdr = ptp_parse_header(skb, ptp_class); 126 if (!hdr) 127 return -EINVAL; 128 129 type = ptp_class & PTP_CLASS_PMASK; 130 if (type == PTP_CLASS_IPV4 || type == PTP_CLASS_IPV6) 131 *udp = 1; 132 else 133 *udp = 0; 134 135 *msgtype = ptp_get_msgtype(hdr, ptp_class); 136 *twostep = hdr->flag_field[0] & 0x2; 137 138 base = skb_mac_header(skb); 139 *correction_offset = (u8 *)&hdr->correction - base; 140 *body_offset = (u8 *)hdr + sizeof(struct ptp_header) - base; 141 142 return 0; 143 } 144 145 static int enetc_map_tx_buffs(struct enetc_bdr *tx_ring, struct sk_buff *skb) 146 { 147 bool do_vlan, do_onestep_tstamp = false, do_twostep_tstamp = false; 148 struct enetc_ndev_priv *priv = netdev_priv(tx_ring->ndev); 149 struct enetc_hw *hw = &priv->si->hw; 150 struct enetc_tx_swbd *tx_swbd; 151 int len = skb_headlen(skb); 152 union enetc_tx_bd temp_bd; 153 u8 msgtype, twostep, udp; 154 union enetc_tx_bd *txbd; 155 u16 offset1, offset2; 156 int i, count = 0; 157 skb_frag_t *frag; 158 unsigned int f; 159 dma_addr_t dma; 160 u8 flags = 0; 161 162 i = tx_ring->next_to_use; 163 txbd = ENETC_TXBD(*tx_ring, i); 164 prefetchw(txbd); 165 166 dma = dma_map_single(tx_ring->dev, skb->data, len, DMA_TO_DEVICE); 167 if (unlikely(dma_mapping_error(tx_ring->dev, dma))) 168 goto dma_err; 169 170 temp_bd.addr = cpu_to_le64(dma); 171 temp_bd.buf_len = cpu_to_le16(len); 172 temp_bd.lstatus = 0; 173 174 tx_swbd = &tx_ring->tx_swbd[i]; 175 tx_swbd->dma = dma; 176 tx_swbd->len = len; 177 tx_swbd->is_dma_page = 0; 178 tx_swbd->dir = DMA_TO_DEVICE; 179 count++; 180 181 do_vlan = skb_vlan_tag_present(skb); 182 if (skb->cb[0] & ENETC_F_TX_ONESTEP_SYNC_TSTAMP) { 183 if (enetc_ptp_parse(skb, &udp, &msgtype, &twostep, &offset1, 184 &offset2) || 185 msgtype != PTP_MSGTYPE_SYNC || twostep) 186 WARN_ONCE(1, "Bad packet for one-step timestamping\n"); 187 else 188 do_onestep_tstamp = true; 189 } else if (skb->cb[0] & ENETC_F_TX_TSTAMP) { 190 do_twostep_tstamp = true; 191 } 192 193 tx_swbd->do_twostep_tstamp = do_twostep_tstamp; 194 tx_swbd->qbv_en = !!(priv->active_offloads & ENETC_F_QBV); 195 tx_swbd->check_wb = tx_swbd->do_twostep_tstamp || tx_swbd->qbv_en; 196 197 if (do_vlan || do_onestep_tstamp || do_twostep_tstamp) 198 flags |= ENETC_TXBD_FLAGS_EX; 199 200 if (tx_ring->tsd_enable) 201 flags |= ENETC_TXBD_FLAGS_TSE | ENETC_TXBD_FLAGS_TXSTART; 202 203 /* first BD needs frm_len and offload flags set */ 204 temp_bd.frm_len = cpu_to_le16(skb->len); 205 temp_bd.flags = flags; 206 207 if (flags & ENETC_TXBD_FLAGS_TSE) 208 temp_bd.txstart = enetc_txbd_set_tx_start(skb->skb_mstamp_ns, 209 flags); 210 211 if (flags & ENETC_TXBD_FLAGS_EX) { 212 u8 e_flags = 0; 213 *txbd = temp_bd; 214 enetc_clear_tx_bd(&temp_bd); 215 216 /* add extension BD for VLAN and/or timestamping */ 217 flags = 0; 218 tx_swbd++; 219 txbd++; 220 i++; 221 if (unlikely(i == tx_ring->bd_count)) { 222 i = 0; 223 tx_swbd = tx_ring->tx_swbd; 224 txbd = ENETC_TXBD(*tx_ring, 0); 225 } 226 prefetchw(txbd); 227 228 if (do_vlan) { 229 temp_bd.ext.vid = cpu_to_le16(skb_vlan_tag_get(skb)); 230 temp_bd.ext.tpid = 0; /* < C-TAG */ 231 e_flags |= ENETC_TXBD_E_FLAGS_VLAN_INS; 232 } 233 234 if (do_onestep_tstamp) { 235 u32 lo, hi, val; 236 u64 sec, nsec; 237 u8 *data; 238 239 lo = enetc_rd_hot(hw, ENETC_SICTR0); 240 hi = enetc_rd_hot(hw, ENETC_SICTR1); 241 sec = (u64)hi << 32 | lo; 242 nsec = do_div(sec, 1000000000); 243 244 /* Configure extension BD */ 245 temp_bd.ext.tstamp = cpu_to_le32(lo & 0x3fffffff); 246 e_flags |= ENETC_TXBD_E_FLAGS_ONE_STEP_PTP; 247 248 /* Update originTimestamp field of Sync packet 249 * - 48 bits seconds field 250 * - 32 bits nanseconds field 251 */ 252 data = skb_mac_header(skb); 253 *(__be16 *)(data + offset2) = 254 htons((sec >> 32) & 0xffff); 255 *(__be32 *)(data + offset2 + 2) = 256 htonl(sec & 0xffffffff); 257 *(__be32 *)(data + offset2 + 6) = htonl(nsec); 258 259 /* Configure single-step register */ 260 val = ENETC_PM0_SINGLE_STEP_EN; 261 val |= ENETC_SET_SINGLE_STEP_OFFSET(offset1); 262 if (udp) 263 val |= ENETC_PM0_SINGLE_STEP_CH; 264 265 enetc_port_mac_wr(priv->si, ENETC_PM0_SINGLE_STEP, 266 val); 267 } else if (do_twostep_tstamp) { 268 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 269 e_flags |= ENETC_TXBD_E_FLAGS_TWO_STEP_PTP; 270 } 271 272 temp_bd.ext.e_flags = e_flags; 273 count++; 274 } 275 276 frag = &skb_shinfo(skb)->frags[0]; 277 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++, frag++) { 278 len = skb_frag_size(frag); 279 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, len, 280 DMA_TO_DEVICE); 281 if (dma_mapping_error(tx_ring->dev, dma)) 282 goto dma_err; 283 284 *txbd = temp_bd; 285 enetc_clear_tx_bd(&temp_bd); 286 287 flags = 0; 288 tx_swbd++; 289 txbd++; 290 i++; 291 if (unlikely(i == tx_ring->bd_count)) { 292 i = 0; 293 tx_swbd = tx_ring->tx_swbd; 294 txbd = ENETC_TXBD(*tx_ring, 0); 295 } 296 prefetchw(txbd); 297 298 temp_bd.addr = cpu_to_le64(dma); 299 temp_bd.buf_len = cpu_to_le16(len); 300 301 tx_swbd->dma = dma; 302 tx_swbd->len = len; 303 tx_swbd->is_dma_page = 1; 304 tx_swbd->dir = DMA_TO_DEVICE; 305 count++; 306 } 307 308 /* last BD needs 'F' bit set */ 309 flags |= ENETC_TXBD_FLAGS_F; 310 temp_bd.flags = flags; 311 *txbd = temp_bd; 312 313 tx_ring->tx_swbd[i].is_eof = true; 314 tx_ring->tx_swbd[i].skb = skb; 315 316 enetc_bdr_idx_inc(tx_ring, &i); 317 tx_ring->next_to_use = i; 318 319 skb_tx_timestamp(skb); 320 321 enetc_update_tx_ring_tail(tx_ring); 322 323 return count; 324 325 dma_err: 326 dev_err(tx_ring->dev, "DMA map error"); 327 328 do { 329 tx_swbd = &tx_ring->tx_swbd[i]; 330 enetc_free_tx_frame(tx_ring, tx_swbd); 331 if (i == 0) 332 i = tx_ring->bd_count; 333 i--; 334 } while (count--); 335 336 return 0; 337 } 338 339 static void enetc_map_tx_tso_hdr(struct enetc_bdr *tx_ring, struct sk_buff *skb, 340 struct enetc_tx_swbd *tx_swbd, 341 union enetc_tx_bd *txbd, int *i, int hdr_len, 342 int data_len) 343 { 344 union enetc_tx_bd txbd_tmp; 345 u8 flags = 0, e_flags = 0; 346 dma_addr_t addr; 347 348 enetc_clear_tx_bd(&txbd_tmp); 349 addr = tx_ring->tso_headers_dma + *i * TSO_HEADER_SIZE; 350 351 if (skb_vlan_tag_present(skb)) 352 flags |= ENETC_TXBD_FLAGS_EX; 353 354 txbd_tmp.addr = cpu_to_le64(addr); 355 txbd_tmp.buf_len = cpu_to_le16(hdr_len); 356 357 /* first BD needs frm_len and offload flags set */ 358 txbd_tmp.frm_len = cpu_to_le16(hdr_len + data_len); 359 txbd_tmp.flags = flags; 360 361 /* For the TSO header we do not set the dma address since we do not 362 * want it unmapped when we do cleanup. We still set len so that we 363 * count the bytes sent. 364 */ 365 tx_swbd->len = hdr_len; 366 tx_swbd->do_twostep_tstamp = false; 367 tx_swbd->check_wb = false; 368 369 /* Actually write the header in the BD */ 370 *txbd = txbd_tmp; 371 372 /* Add extension BD for VLAN */ 373 if (flags & ENETC_TXBD_FLAGS_EX) { 374 /* Get the next BD */ 375 enetc_bdr_idx_inc(tx_ring, i); 376 txbd = ENETC_TXBD(*tx_ring, *i); 377 tx_swbd = &tx_ring->tx_swbd[*i]; 378 prefetchw(txbd); 379 380 /* Setup the VLAN fields */ 381 enetc_clear_tx_bd(&txbd_tmp); 382 txbd_tmp.ext.vid = cpu_to_le16(skb_vlan_tag_get(skb)); 383 txbd_tmp.ext.tpid = 0; /* < C-TAG */ 384 e_flags |= ENETC_TXBD_E_FLAGS_VLAN_INS; 385 386 /* Write the BD */ 387 txbd_tmp.ext.e_flags = e_flags; 388 *txbd = txbd_tmp; 389 } 390 } 391 392 static int enetc_map_tx_tso_data(struct enetc_bdr *tx_ring, struct sk_buff *skb, 393 struct enetc_tx_swbd *tx_swbd, 394 union enetc_tx_bd *txbd, char *data, 395 int size, bool last_bd) 396 { 397 union enetc_tx_bd txbd_tmp; 398 dma_addr_t addr; 399 u8 flags = 0; 400 401 enetc_clear_tx_bd(&txbd_tmp); 402 403 addr = dma_map_single(tx_ring->dev, data, size, DMA_TO_DEVICE); 404 if (unlikely(dma_mapping_error(tx_ring->dev, addr))) { 405 netdev_err(tx_ring->ndev, "DMA map error\n"); 406 return -ENOMEM; 407 } 408 409 if (last_bd) { 410 flags |= ENETC_TXBD_FLAGS_F; 411 tx_swbd->is_eof = 1; 412 } 413 414 txbd_tmp.addr = cpu_to_le64(addr); 415 txbd_tmp.buf_len = cpu_to_le16(size); 416 txbd_tmp.flags = flags; 417 418 tx_swbd->dma = addr; 419 tx_swbd->len = size; 420 tx_swbd->dir = DMA_TO_DEVICE; 421 422 *txbd = txbd_tmp; 423 424 return 0; 425 } 426 427 static __wsum enetc_tso_hdr_csum(struct tso_t *tso, struct sk_buff *skb, 428 char *hdr, int hdr_len, int *l4_hdr_len) 429 { 430 char *l4_hdr = hdr + skb_transport_offset(skb); 431 int mac_hdr_len = skb_network_offset(skb); 432 433 if (tso->tlen != sizeof(struct udphdr)) { 434 struct tcphdr *tcph = (struct tcphdr *)(l4_hdr); 435 436 tcph->check = 0; 437 } else { 438 struct udphdr *udph = (struct udphdr *)(l4_hdr); 439 440 udph->check = 0; 441 } 442 443 /* Compute the IP checksum. This is necessary since tso_build_hdr() 444 * already incremented the IP ID field. 445 */ 446 if (!tso->ipv6) { 447 struct iphdr *iph = (void *)(hdr + mac_hdr_len); 448 449 iph->check = 0; 450 iph->check = ip_fast_csum((unsigned char *)iph, iph->ihl); 451 } 452 453 /* Compute the checksum over the L4 header. */ 454 *l4_hdr_len = hdr_len - skb_transport_offset(skb); 455 return csum_partial(l4_hdr, *l4_hdr_len, 0); 456 } 457 458 static void enetc_tso_complete_csum(struct enetc_bdr *tx_ring, struct tso_t *tso, 459 struct sk_buff *skb, char *hdr, int len, 460 __wsum sum) 461 { 462 char *l4_hdr = hdr + skb_transport_offset(skb); 463 __sum16 csum_final; 464 465 /* Complete the L4 checksum by appending the pseudo-header to the 466 * already computed checksum. 467 */ 468 if (!tso->ipv6) 469 csum_final = csum_tcpudp_magic(ip_hdr(skb)->saddr, 470 ip_hdr(skb)->daddr, 471 len, ip_hdr(skb)->protocol, sum); 472 else 473 csum_final = csum_ipv6_magic(&ipv6_hdr(skb)->saddr, 474 &ipv6_hdr(skb)->daddr, 475 len, ipv6_hdr(skb)->nexthdr, sum); 476 477 if (tso->tlen != sizeof(struct udphdr)) { 478 struct tcphdr *tcph = (struct tcphdr *)(l4_hdr); 479 480 tcph->check = csum_final; 481 } else { 482 struct udphdr *udph = (struct udphdr *)(l4_hdr); 483 484 udph->check = csum_final; 485 } 486 } 487 488 static int enetc_map_tx_tso_buffs(struct enetc_bdr *tx_ring, struct sk_buff *skb) 489 { 490 int hdr_len, total_len, data_len; 491 struct enetc_tx_swbd *tx_swbd; 492 union enetc_tx_bd *txbd; 493 struct tso_t tso; 494 __wsum csum, csum2; 495 int count = 0, pos; 496 int err, i, bd_data_num; 497 498 /* Initialize the TSO handler, and prepare the first payload */ 499 hdr_len = tso_start(skb, &tso); 500 total_len = skb->len - hdr_len; 501 i = tx_ring->next_to_use; 502 503 while (total_len > 0) { 504 char *hdr; 505 506 /* Get the BD */ 507 txbd = ENETC_TXBD(*tx_ring, i); 508 tx_swbd = &tx_ring->tx_swbd[i]; 509 prefetchw(txbd); 510 511 /* Determine the length of this packet */ 512 data_len = min_t(int, skb_shinfo(skb)->gso_size, total_len); 513 total_len -= data_len; 514 515 /* prepare packet headers: MAC + IP + TCP */ 516 hdr = tx_ring->tso_headers + i * TSO_HEADER_SIZE; 517 tso_build_hdr(skb, hdr, &tso, data_len, total_len == 0); 518 519 /* compute the csum over the L4 header */ 520 csum = enetc_tso_hdr_csum(&tso, skb, hdr, hdr_len, &pos); 521 enetc_map_tx_tso_hdr(tx_ring, skb, tx_swbd, txbd, &i, hdr_len, data_len); 522 bd_data_num = 0; 523 count++; 524 525 while (data_len > 0) { 526 int size; 527 528 size = min_t(int, tso.size, data_len); 529 530 /* Advance the index in the BDR */ 531 enetc_bdr_idx_inc(tx_ring, &i); 532 txbd = ENETC_TXBD(*tx_ring, i); 533 tx_swbd = &tx_ring->tx_swbd[i]; 534 prefetchw(txbd); 535 536 /* Compute the checksum over this segment of data and 537 * add it to the csum already computed (over the L4 538 * header and possible other data segments). 539 */ 540 csum2 = csum_partial(tso.data, size, 0); 541 csum = csum_block_add(csum, csum2, pos); 542 pos += size; 543 544 err = enetc_map_tx_tso_data(tx_ring, skb, tx_swbd, txbd, 545 tso.data, size, 546 size == data_len); 547 if (err) 548 goto err_map_data; 549 550 data_len -= size; 551 count++; 552 bd_data_num++; 553 tso_build_data(skb, &tso, size); 554 555 if (unlikely(bd_data_num >= ENETC_MAX_SKB_FRAGS && data_len)) 556 goto err_chained_bd; 557 } 558 559 enetc_tso_complete_csum(tx_ring, &tso, skb, hdr, pos, csum); 560 561 if (total_len == 0) 562 tx_swbd->skb = skb; 563 564 /* Go to the next BD */ 565 enetc_bdr_idx_inc(tx_ring, &i); 566 } 567 568 tx_ring->next_to_use = i; 569 enetc_update_tx_ring_tail(tx_ring); 570 571 return count; 572 573 err_map_data: 574 dev_err(tx_ring->dev, "DMA map error"); 575 576 err_chained_bd: 577 do { 578 tx_swbd = &tx_ring->tx_swbd[i]; 579 enetc_free_tx_frame(tx_ring, tx_swbd); 580 if (i == 0) 581 i = tx_ring->bd_count; 582 i--; 583 } while (count--); 584 585 return 0; 586 } 587 588 static netdev_tx_t enetc_start_xmit(struct sk_buff *skb, 589 struct net_device *ndev) 590 { 591 struct enetc_ndev_priv *priv = netdev_priv(ndev); 592 struct enetc_bdr *tx_ring; 593 int count, err; 594 595 /* Queue one-step Sync packet if already locked */ 596 if (skb->cb[0] & ENETC_F_TX_ONESTEP_SYNC_TSTAMP) { 597 if (test_and_set_bit_lock(ENETC_TX_ONESTEP_TSTAMP_IN_PROGRESS, 598 &priv->flags)) { 599 skb_queue_tail(&priv->tx_skbs, skb); 600 return NETDEV_TX_OK; 601 } 602 } 603 604 tx_ring = priv->tx_ring[skb->queue_mapping]; 605 606 if (skb_is_gso(skb)) { 607 if (enetc_bd_unused(tx_ring) < tso_count_descs(skb)) { 608 netif_stop_subqueue(ndev, tx_ring->index); 609 return NETDEV_TX_BUSY; 610 } 611 612 enetc_lock_mdio(); 613 count = enetc_map_tx_tso_buffs(tx_ring, skb); 614 enetc_unlock_mdio(); 615 } else { 616 if (unlikely(skb_shinfo(skb)->nr_frags > ENETC_MAX_SKB_FRAGS)) 617 if (unlikely(skb_linearize(skb))) 618 goto drop_packet_err; 619 620 count = skb_shinfo(skb)->nr_frags + 1; /* fragments + head */ 621 if (enetc_bd_unused(tx_ring) < ENETC_TXBDS_NEEDED(count)) { 622 netif_stop_subqueue(ndev, tx_ring->index); 623 return NETDEV_TX_BUSY; 624 } 625 626 if (skb->ip_summed == CHECKSUM_PARTIAL) { 627 err = skb_checksum_help(skb); 628 if (err) 629 goto drop_packet_err; 630 } 631 enetc_lock_mdio(); 632 count = enetc_map_tx_buffs(tx_ring, skb); 633 enetc_unlock_mdio(); 634 } 635 636 if (unlikely(!count)) 637 goto drop_packet_err; 638 639 if (enetc_bd_unused(tx_ring) < ENETC_TXBDS_MAX_NEEDED) 640 netif_stop_subqueue(ndev, tx_ring->index); 641 642 return NETDEV_TX_OK; 643 644 drop_packet_err: 645 dev_kfree_skb_any(skb); 646 return NETDEV_TX_OK; 647 } 648 649 netdev_tx_t enetc_xmit(struct sk_buff *skb, struct net_device *ndev) 650 { 651 struct enetc_ndev_priv *priv = netdev_priv(ndev); 652 u8 udp, msgtype, twostep; 653 u16 offset1, offset2; 654 655 /* Mark tx timestamp type on skb->cb[0] if requires */ 656 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 657 (priv->active_offloads & ENETC_F_TX_TSTAMP_MASK)) { 658 skb->cb[0] = priv->active_offloads & ENETC_F_TX_TSTAMP_MASK; 659 } else { 660 skb->cb[0] = 0; 661 } 662 663 /* Fall back to two-step timestamp if not one-step Sync packet */ 664 if (skb->cb[0] & ENETC_F_TX_ONESTEP_SYNC_TSTAMP) { 665 if (enetc_ptp_parse(skb, &udp, &msgtype, &twostep, 666 &offset1, &offset2) || 667 msgtype != PTP_MSGTYPE_SYNC || twostep != 0) 668 skb->cb[0] = ENETC_F_TX_TSTAMP; 669 } 670 671 return enetc_start_xmit(skb, ndev); 672 } 673 EXPORT_SYMBOL_GPL(enetc_xmit); 674 675 static irqreturn_t enetc_msix(int irq, void *data) 676 { 677 struct enetc_int_vector *v = data; 678 int i; 679 680 enetc_lock_mdio(); 681 682 /* disable interrupts */ 683 enetc_wr_reg_hot(v->rbier, 0); 684 enetc_wr_reg_hot(v->ricr1, v->rx_ictt); 685 686 for_each_set_bit(i, &v->tx_rings_map, ENETC_MAX_NUM_TXQS) 687 enetc_wr_reg_hot(v->tbier_base + ENETC_BDR_OFF(i), 0); 688 689 enetc_unlock_mdio(); 690 691 napi_schedule(&v->napi); 692 693 return IRQ_HANDLED; 694 } 695 696 static void enetc_rx_dim_work(struct work_struct *w) 697 { 698 struct dim *dim = container_of(w, struct dim, work); 699 struct dim_cq_moder moder = 700 net_dim_get_rx_moderation(dim->mode, dim->profile_ix); 701 struct enetc_int_vector *v = 702 container_of(dim, struct enetc_int_vector, rx_dim); 703 704 v->rx_ictt = enetc_usecs_to_cycles(moder.usec); 705 dim->state = DIM_START_MEASURE; 706 } 707 708 static void enetc_rx_net_dim(struct enetc_int_vector *v) 709 { 710 struct dim_sample dim_sample = {}; 711 712 v->comp_cnt++; 713 714 if (!v->rx_napi_work) 715 return; 716 717 dim_update_sample(v->comp_cnt, 718 v->rx_ring.stats.packets, 719 v->rx_ring.stats.bytes, 720 &dim_sample); 721 net_dim(&v->rx_dim, dim_sample); 722 } 723 724 static int enetc_bd_ready_count(struct enetc_bdr *tx_ring, int ci) 725 { 726 int pi = enetc_rd_reg_hot(tx_ring->tcir) & ENETC_TBCIR_IDX_MASK; 727 728 return pi >= ci ? pi - ci : tx_ring->bd_count - ci + pi; 729 } 730 731 static bool enetc_page_reusable(struct page *page) 732 { 733 return (!page_is_pfmemalloc(page) && page_ref_count(page) == 1); 734 } 735 736 static void enetc_reuse_page(struct enetc_bdr *rx_ring, 737 struct enetc_rx_swbd *old) 738 { 739 struct enetc_rx_swbd *new; 740 741 new = &rx_ring->rx_swbd[rx_ring->next_to_alloc]; 742 743 /* next buf that may reuse a page */ 744 enetc_bdr_idx_inc(rx_ring, &rx_ring->next_to_alloc); 745 746 /* copy page reference */ 747 *new = *old; 748 } 749 750 static void enetc_get_tx_tstamp(struct enetc_hw *hw, union enetc_tx_bd *txbd, 751 u64 *tstamp) 752 { 753 u32 lo, hi, tstamp_lo; 754 755 lo = enetc_rd_hot(hw, ENETC_SICTR0); 756 hi = enetc_rd_hot(hw, ENETC_SICTR1); 757 tstamp_lo = le32_to_cpu(txbd->wb.tstamp); 758 if (lo <= tstamp_lo) 759 hi -= 1; 760 *tstamp = (u64)hi << 32 | tstamp_lo; 761 } 762 763 static void enetc_tstamp_tx(struct sk_buff *skb, u64 tstamp) 764 { 765 struct skb_shared_hwtstamps shhwtstamps; 766 767 if (skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) { 768 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 769 shhwtstamps.hwtstamp = ns_to_ktime(tstamp); 770 skb_txtime_consumed(skb); 771 skb_tstamp_tx(skb, &shhwtstamps); 772 } 773 } 774 775 static void enetc_recycle_xdp_tx_buff(struct enetc_bdr *tx_ring, 776 struct enetc_tx_swbd *tx_swbd) 777 { 778 struct enetc_ndev_priv *priv = netdev_priv(tx_ring->ndev); 779 struct enetc_rx_swbd rx_swbd = { 780 .dma = tx_swbd->dma, 781 .page = tx_swbd->page, 782 .page_offset = tx_swbd->page_offset, 783 .dir = tx_swbd->dir, 784 .len = tx_swbd->len, 785 }; 786 struct enetc_bdr *rx_ring; 787 788 rx_ring = enetc_rx_ring_from_xdp_tx_ring(priv, tx_ring); 789 790 if (likely(enetc_swbd_unused(rx_ring))) { 791 enetc_reuse_page(rx_ring, &rx_swbd); 792 793 /* sync for use by the device */ 794 dma_sync_single_range_for_device(rx_ring->dev, rx_swbd.dma, 795 rx_swbd.page_offset, 796 ENETC_RXB_DMA_SIZE_XDP, 797 rx_swbd.dir); 798 799 rx_ring->stats.recycles++; 800 } else { 801 /* RX ring is already full, we need to unmap and free the 802 * page, since there's nothing useful we can do with it. 803 */ 804 rx_ring->stats.recycle_failures++; 805 806 dma_unmap_page(rx_ring->dev, rx_swbd.dma, PAGE_SIZE, 807 rx_swbd.dir); 808 __free_page(rx_swbd.page); 809 } 810 811 rx_ring->xdp.xdp_tx_in_flight--; 812 } 813 814 static bool enetc_clean_tx_ring(struct enetc_bdr *tx_ring, int napi_budget) 815 { 816 int tx_frm_cnt = 0, tx_byte_cnt = 0, tx_win_drop = 0; 817 struct net_device *ndev = tx_ring->ndev; 818 struct enetc_ndev_priv *priv = netdev_priv(ndev); 819 struct enetc_tx_swbd *tx_swbd; 820 int i, bds_to_clean; 821 bool do_twostep_tstamp; 822 u64 tstamp = 0; 823 824 i = tx_ring->next_to_clean; 825 tx_swbd = &tx_ring->tx_swbd[i]; 826 827 bds_to_clean = enetc_bd_ready_count(tx_ring, i); 828 829 do_twostep_tstamp = false; 830 831 while (bds_to_clean && tx_frm_cnt < ENETC_DEFAULT_TX_WORK) { 832 struct xdp_frame *xdp_frame = enetc_tx_swbd_get_xdp_frame(tx_swbd); 833 struct sk_buff *skb = enetc_tx_swbd_get_skb(tx_swbd); 834 bool is_eof = tx_swbd->is_eof; 835 836 if (unlikely(tx_swbd->check_wb)) { 837 union enetc_tx_bd *txbd = ENETC_TXBD(*tx_ring, i); 838 839 if (txbd->flags & ENETC_TXBD_FLAGS_W && 840 tx_swbd->do_twostep_tstamp) { 841 enetc_get_tx_tstamp(&priv->si->hw, txbd, 842 &tstamp); 843 do_twostep_tstamp = true; 844 } 845 846 if (tx_swbd->qbv_en && 847 txbd->wb.status & ENETC_TXBD_STATS_WIN) 848 tx_win_drop++; 849 } 850 851 if (tx_swbd->is_xdp_tx) 852 enetc_recycle_xdp_tx_buff(tx_ring, tx_swbd); 853 else if (likely(tx_swbd->dma)) 854 enetc_unmap_tx_buff(tx_ring, tx_swbd); 855 856 if (xdp_frame) { 857 xdp_return_frame(xdp_frame); 858 } else if (skb) { 859 if (unlikely(skb->cb[0] & ENETC_F_TX_ONESTEP_SYNC_TSTAMP)) { 860 /* Start work to release lock for next one-step 861 * timestamping packet. And send one skb in 862 * tx_skbs queue if has. 863 */ 864 schedule_work(&priv->tx_onestep_tstamp); 865 } else if (unlikely(do_twostep_tstamp)) { 866 enetc_tstamp_tx(skb, tstamp); 867 do_twostep_tstamp = false; 868 } 869 napi_consume_skb(skb, napi_budget); 870 } 871 872 tx_byte_cnt += tx_swbd->len; 873 /* Scrub the swbd here so we don't have to do that 874 * when we reuse it during xmit 875 */ 876 memset(tx_swbd, 0, sizeof(*tx_swbd)); 877 878 bds_to_clean--; 879 tx_swbd++; 880 i++; 881 if (unlikely(i == tx_ring->bd_count)) { 882 i = 0; 883 tx_swbd = tx_ring->tx_swbd; 884 } 885 886 /* BD iteration loop end */ 887 if (is_eof) { 888 tx_frm_cnt++; 889 /* re-arm interrupt source */ 890 enetc_wr_reg_hot(tx_ring->idr, BIT(tx_ring->index) | 891 BIT(16 + tx_ring->index)); 892 } 893 894 if (unlikely(!bds_to_clean)) 895 bds_to_clean = enetc_bd_ready_count(tx_ring, i); 896 } 897 898 tx_ring->next_to_clean = i; 899 tx_ring->stats.packets += tx_frm_cnt; 900 tx_ring->stats.bytes += tx_byte_cnt; 901 tx_ring->stats.win_drop += tx_win_drop; 902 903 if (unlikely(tx_frm_cnt && netif_carrier_ok(ndev) && 904 __netif_subqueue_stopped(ndev, tx_ring->index) && 905 !test_bit(ENETC_TX_DOWN, &priv->flags) && 906 (enetc_bd_unused(tx_ring) >= ENETC_TXBDS_MAX_NEEDED))) { 907 netif_wake_subqueue(ndev, tx_ring->index); 908 } 909 910 return tx_frm_cnt != ENETC_DEFAULT_TX_WORK; 911 } 912 913 static bool enetc_new_page(struct enetc_bdr *rx_ring, 914 struct enetc_rx_swbd *rx_swbd) 915 { 916 bool xdp = !!(rx_ring->xdp.prog); 917 struct page *page; 918 dma_addr_t addr; 919 920 page = dev_alloc_page(); 921 if (unlikely(!page)) 922 return false; 923 924 /* For XDP_TX, we forgo dma_unmap -> dma_map */ 925 rx_swbd->dir = xdp ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE; 926 927 addr = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, rx_swbd->dir); 928 if (unlikely(dma_mapping_error(rx_ring->dev, addr))) { 929 __free_page(page); 930 931 return false; 932 } 933 934 rx_swbd->dma = addr; 935 rx_swbd->page = page; 936 rx_swbd->page_offset = rx_ring->buffer_offset; 937 938 return true; 939 } 940 941 static int enetc_refill_rx_ring(struct enetc_bdr *rx_ring, const int buff_cnt) 942 { 943 struct enetc_rx_swbd *rx_swbd; 944 union enetc_rx_bd *rxbd; 945 int i, j; 946 947 i = rx_ring->next_to_use; 948 rx_swbd = &rx_ring->rx_swbd[i]; 949 rxbd = enetc_rxbd(rx_ring, i); 950 951 for (j = 0; j < buff_cnt; j++) { 952 /* try reuse page */ 953 if (unlikely(!rx_swbd->page)) { 954 if (unlikely(!enetc_new_page(rx_ring, rx_swbd))) { 955 rx_ring->stats.rx_alloc_errs++; 956 break; 957 } 958 } 959 960 /* update RxBD */ 961 rxbd->w.addr = cpu_to_le64(rx_swbd->dma + 962 rx_swbd->page_offset); 963 /* clear 'R" as well */ 964 rxbd->r.lstatus = 0; 965 966 enetc_rxbd_next(rx_ring, &rxbd, &i); 967 rx_swbd = &rx_ring->rx_swbd[i]; 968 } 969 970 if (likely(j)) { 971 rx_ring->next_to_alloc = i; /* keep track from page reuse */ 972 rx_ring->next_to_use = i; 973 974 /* update ENETC's consumer index */ 975 enetc_wr_reg_hot(rx_ring->rcir, rx_ring->next_to_use); 976 } 977 978 return j; 979 } 980 981 #ifdef CONFIG_FSL_ENETC_PTP_CLOCK 982 static void enetc_get_rx_tstamp(struct net_device *ndev, 983 union enetc_rx_bd *rxbd, 984 struct sk_buff *skb) 985 { 986 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb); 987 struct enetc_ndev_priv *priv = netdev_priv(ndev); 988 struct enetc_hw *hw = &priv->si->hw; 989 u32 lo, hi, tstamp_lo; 990 u64 tstamp; 991 992 if (le16_to_cpu(rxbd->r.flags) & ENETC_RXBD_FLAG_TSTMP) { 993 lo = enetc_rd_reg_hot(hw->reg + ENETC_SICTR0); 994 hi = enetc_rd_reg_hot(hw->reg + ENETC_SICTR1); 995 rxbd = enetc_rxbd_ext(rxbd); 996 tstamp_lo = le32_to_cpu(rxbd->ext.tstamp); 997 if (lo <= tstamp_lo) 998 hi -= 1; 999 1000 tstamp = (u64)hi << 32 | tstamp_lo; 1001 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 1002 shhwtstamps->hwtstamp = ns_to_ktime(tstamp); 1003 } 1004 } 1005 #endif 1006 1007 static void enetc_get_offloads(struct enetc_bdr *rx_ring, 1008 union enetc_rx_bd *rxbd, struct sk_buff *skb) 1009 { 1010 struct enetc_ndev_priv *priv = netdev_priv(rx_ring->ndev); 1011 1012 /* TODO: hashing */ 1013 if (rx_ring->ndev->features & NETIF_F_RXCSUM) { 1014 u16 inet_csum = le16_to_cpu(rxbd->r.inet_csum); 1015 1016 skb->csum = csum_unfold((__force __sum16)~htons(inet_csum)); 1017 skb->ip_summed = CHECKSUM_COMPLETE; 1018 } 1019 1020 if (le16_to_cpu(rxbd->r.flags) & ENETC_RXBD_FLAG_VLAN) { 1021 __be16 tpid = 0; 1022 1023 switch (le16_to_cpu(rxbd->r.flags) & ENETC_RXBD_FLAG_TPID) { 1024 case 0: 1025 tpid = htons(ETH_P_8021Q); 1026 break; 1027 case 1: 1028 tpid = htons(ETH_P_8021AD); 1029 break; 1030 case 2: 1031 tpid = htons(enetc_port_rd(&priv->si->hw, 1032 ENETC_PCVLANR1)); 1033 break; 1034 case 3: 1035 tpid = htons(enetc_port_rd(&priv->si->hw, 1036 ENETC_PCVLANR2)); 1037 break; 1038 default: 1039 break; 1040 } 1041 1042 __vlan_hwaccel_put_tag(skb, tpid, le16_to_cpu(rxbd->r.vlan_opt)); 1043 } 1044 1045 #ifdef CONFIG_FSL_ENETC_PTP_CLOCK 1046 if (priv->active_offloads & ENETC_F_RX_TSTAMP) 1047 enetc_get_rx_tstamp(rx_ring->ndev, rxbd, skb); 1048 #endif 1049 } 1050 1051 /* This gets called during the non-XDP NAPI poll cycle as well as on XDP_PASS, 1052 * so it needs to work with both DMA_FROM_DEVICE as well as DMA_BIDIRECTIONAL 1053 * mapped buffers. 1054 */ 1055 static struct enetc_rx_swbd *enetc_get_rx_buff(struct enetc_bdr *rx_ring, 1056 int i, u16 size) 1057 { 1058 struct enetc_rx_swbd *rx_swbd = &rx_ring->rx_swbd[i]; 1059 1060 dma_sync_single_range_for_cpu(rx_ring->dev, rx_swbd->dma, 1061 rx_swbd->page_offset, 1062 size, rx_swbd->dir); 1063 return rx_swbd; 1064 } 1065 1066 /* Reuse the current page without performing half-page buffer flipping */ 1067 static void enetc_put_rx_buff(struct enetc_bdr *rx_ring, 1068 struct enetc_rx_swbd *rx_swbd) 1069 { 1070 size_t buffer_size = ENETC_RXB_TRUESIZE - rx_ring->buffer_offset; 1071 1072 enetc_reuse_page(rx_ring, rx_swbd); 1073 1074 dma_sync_single_range_for_device(rx_ring->dev, rx_swbd->dma, 1075 rx_swbd->page_offset, 1076 buffer_size, rx_swbd->dir); 1077 1078 rx_swbd->page = NULL; 1079 } 1080 1081 /* Reuse the current page by performing half-page buffer flipping */ 1082 static void enetc_flip_rx_buff(struct enetc_bdr *rx_ring, 1083 struct enetc_rx_swbd *rx_swbd) 1084 { 1085 if (likely(enetc_page_reusable(rx_swbd->page))) { 1086 rx_swbd->page_offset ^= ENETC_RXB_TRUESIZE; 1087 page_ref_inc(rx_swbd->page); 1088 1089 enetc_put_rx_buff(rx_ring, rx_swbd); 1090 } else { 1091 dma_unmap_page(rx_ring->dev, rx_swbd->dma, PAGE_SIZE, 1092 rx_swbd->dir); 1093 rx_swbd->page = NULL; 1094 } 1095 } 1096 1097 static struct sk_buff *enetc_map_rx_buff_to_skb(struct enetc_bdr *rx_ring, 1098 int i, u16 size) 1099 { 1100 struct enetc_rx_swbd *rx_swbd = enetc_get_rx_buff(rx_ring, i, size); 1101 struct sk_buff *skb; 1102 void *ba; 1103 1104 ba = page_address(rx_swbd->page) + rx_swbd->page_offset; 1105 skb = build_skb(ba - rx_ring->buffer_offset, ENETC_RXB_TRUESIZE); 1106 if (unlikely(!skb)) { 1107 rx_ring->stats.rx_alloc_errs++; 1108 return NULL; 1109 } 1110 1111 skb_reserve(skb, rx_ring->buffer_offset); 1112 __skb_put(skb, size); 1113 1114 enetc_flip_rx_buff(rx_ring, rx_swbd); 1115 1116 return skb; 1117 } 1118 1119 static void enetc_add_rx_buff_to_skb(struct enetc_bdr *rx_ring, int i, 1120 u16 size, struct sk_buff *skb) 1121 { 1122 struct enetc_rx_swbd *rx_swbd = enetc_get_rx_buff(rx_ring, i, size); 1123 1124 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_swbd->page, 1125 rx_swbd->page_offset, size, ENETC_RXB_TRUESIZE); 1126 1127 enetc_flip_rx_buff(rx_ring, rx_swbd); 1128 } 1129 1130 static bool enetc_check_bd_errors_and_consume(struct enetc_bdr *rx_ring, 1131 u32 bd_status, 1132 union enetc_rx_bd **rxbd, int *i) 1133 { 1134 if (likely(!(bd_status & ENETC_RXBD_LSTATUS(ENETC_RXBD_ERR_MASK)))) 1135 return false; 1136 1137 enetc_put_rx_buff(rx_ring, &rx_ring->rx_swbd[*i]); 1138 enetc_rxbd_next(rx_ring, rxbd, i); 1139 1140 while (!(bd_status & ENETC_RXBD_LSTATUS_F)) { 1141 dma_rmb(); 1142 bd_status = le32_to_cpu((*rxbd)->r.lstatus); 1143 1144 enetc_put_rx_buff(rx_ring, &rx_ring->rx_swbd[*i]); 1145 enetc_rxbd_next(rx_ring, rxbd, i); 1146 } 1147 1148 rx_ring->ndev->stats.rx_dropped++; 1149 rx_ring->ndev->stats.rx_errors++; 1150 1151 return true; 1152 } 1153 1154 static struct sk_buff *enetc_build_skb(struct enetc_bdr *rx_ring, 1155 u32 bd_status, union enetc_rx_bd **rxbd, 1156 int *i, int *cleaned_cnt, int buffer_size) 1157 { 1158 struct sk_buff *skb; 1159 u16 size; 1160 1161 size = le16_to_cpu((*rxbd)->r.buf_len); 1162 skb = enetc_map_rx_buff_to_skb(rx_ring, *i, size); 1163 if (!skb) 1164 return NULL; 1165 1166 enetc_get_offloads(rx_ring, *rxbd, skb); 1167 1168 (*cleaned_cnt)++; 1169 1170 enetc_rxbd_next(rx_ring, rxbd, i); 1171 1172 /* not last BD in frame? */ 1173 while (!(bd_status & ENETC_RXBD_LSTATUS_F)) { 1174 bd_status = le32_to_cpu((*rxbd)->r.lstatus); 1175 size = buffer_size; 1176 1177 if (bd_status & ENETC_RXBD_LSTATUS_F) { 1178 dma_rmb(); 1179 size = le16_to_cpu((*rxbd)->r.buf_len); 1180 } 1181 1182 enetc_add_rx_buff_to_skb(rx_ring, *i, size, skb); 1183 1184 (*cleaned_cnt)++; 1185 1186 enetc_rxbd_next(rx_ring, rxbd, i); 1187 } 1188 1189 skb_record_rx_queue(skb, rx_ring->index); 1190 skb->protocol = eth_type_trans(skb, rx_ring->ndev); 1191 1192 return skb; 1193 } 1194 1195 #define ENETC_RXBD_BUNDLE 16 /* # of BDs to update at once */ 1196 1197 static int enetc_clean_rx_ring(struct enetc_bdr *rx_ring, 1198 struct napi_struct *napi, int work_limit) 1199 { 1200 int rx_frm_cnt = 0, rx_byte_cnt = 0; 1201 int cleaned_cnt, i; 1202 1203 cleaned_cnt = enetc_bd_unused(rx_ring); 1204 /* next descriptor to process */ 1205 i = rx_ring->next_to_clean; 1206 1207 while (likely(rx_frm_cnt < work_limit)) { 1208 union enetc_rx_bd *rxbd; 1209 struct sk_buff *skb; 1210 u32 bd_status; 1211 1212 if (cleaned_cnt >= ENETC_RXBD_BUNDLE) 1213 cleaned_cnt -= enetc_refill_rx_ring(rx_ring, 1214 cleaned_cnt); 1215 1216 rxbd = enetc_rxbd(rx_ring, i); 1217 bd_status = le32_to_cpu(rxbd->r.lstatus); 1218 if (!bd_status) 1219 break; 1220 1221 enetc_wr_reg_hot(rx_ring->idr, BIT(rx_ring->index)); 1222 dma_rmb(); /* for reading other rxbd fields */ 1223 1224 if (enetc_check_bd_errors_and_consume(rx_ring, bd_status, 1225 &rxbd, &i)) 1226 break; 1227 1228 skb = enetc_build_skb(rx_ring, bd_status, &rxbd, &i, 1229 &cleaned_cnt, ENETC_RXB_DMA_SIZE); 1230 if (!skb) 1231 break; 1232 1233 /* When set, the outer VLAN header is extracted and reported 1234 * in the receive buffer descriptor. So rx_byte_cnt should 1235 * add the length of the extracted VLAN header. 1236 */ 1237 if (bd_status & ENETC_RXBD_FLAG_VLAN) 1238 rx_byte_cnt += VLAN_HLEN; 1239 rx_byte_cnt += skb->len + ETH_HLEN; 1240 rx_frm_cnt++; 1241 1242 napi_gro_receive(napi, skb); 1243 } 1244 1245 rx_ring->next_to_clean = i; 1246 1247 rx_ring->stats.packets += rx_frm_cnt; 1248 rx_ring->stats.bytes += rx_byte_cnt; 1249 1250 return rx_frm_cnt; 1251 } 1252 1253 static void enetc_xdp_map_tx_buff(struct enetc_bdr *tx_ring, int i, 1254 struct enetc_tx_swbd *tx_swbd, 1255 int frm_len) 1256 { 1257 union enetc_tx_bd *txbd = ENETC_TXBD(*tx_ring, i); 1258 1259 prefetchw(txbd); 1260 1261 enetc_clear_tx_bd(txbd); 1262 txbd->addr = cpu_to_le64(tx_swbd->dma + tx_swbd->page_offset); 1263 txbd->buf_len = cpu_to_le16(tx_swbd->len); 1264 txbd->frm_len = cpu_to_le16(frm_len); 1265 1266 memcpy(&tx_ring->tx_swbd[i], tx_swbd, sizeof(*tx_swbd)); 1267 } 1268 1269 /* Puts in the TX ring one XDP frame, mapped as an array of TX software buffer 1270 * descriptors. 1271 */ 1272 static bool enetc_xdp_tx(struct enetc_bdr *tx_ring, 1273 struct enetc_tx_swbd *xdp_tx_arr, int num_tx_swbd) 1274 { 1275 struct enetc_tx_swbd *tmp_tx_swbd = xdp_tx_arr; 1276 int i, k, frm_len = tmp_tx_swbd->len; 1277 1278 if (unlikely(enetc_bd_unused(tx_ring) < ENETC_TXBDS_NEEDED(num_tx_swbd))) 1279 return false; 1280 1281 while (unlikely(!tmp_tx_swbd->is_eof)) { 1282 tmp_tx_swbd++; 1283 frm_len += tmp_tx_swbd->len; 1284 } 1285 1286 i = tx_ring->next_to_use; 1287 1288 for (k = 0; k < num_tx_swbd; k++) { 1289 struct enetc_tx_swbd *xdp_tx_swbd = &xdp_tx_arr[k]; 1290 1291 enetc_xdp_map_tx_buff(tx_ring, i, xdp_tx_swbd, frm_len); 1292 1293 /* last BD needs 'F' bit set */ 1294 if (xdp_tx_swbd->is_eof) { 1295 union enetc_tx_bd *txbd = ENETC_TXBD(*tx_ring, i); 1296 1297 txbd->flags = ENETC_TXBD_FLAGS_F; 1298 } 1299 1300 enetc_bdr_idx_inc(tx_ring, &i); 1301 } 1302 1303 tx_ring->next_to_use = i; 1304 1305 return true; 1306 } 1307 1308 static int enetc_xdp_frame_to_xdp_tx_swbd(struct enetc_bdr *tx_ring, 1309 struct enetc_tx_swbd *xdp_tx_arr, 1310 struct xdp_frame *xdp_frame) 1311 { 1312 struct enetc_tx_swbd *xdp_tx_swbd = &xdp_tx_arr[0]; 1313 struct skb_shared_info *shinfo; 1314 void *data = xdp_frame->data; 1315 int len = xdp_frame->len; 1316 skb_frag_t *frag; 1317 dma_addr_t dma; 1318 unsigned int f; 1319 int n = 0; 1320 1321 dma = dma_map_single(tx_ring->dev, data, len, DMA_TO_DEVICE); 1322 if (unlikely(dma_mapping_error(tx_ring->dev, dma))) { 1323 netdev_err(tx_ring->ndev, "DMA map error\n"); 1324 return -1; 1325 } 1326 1327 xdp_tx_swbd->dma = dma; 1328 xdp_tx_swbd->dir = DMA_TO_DEVICE; 1329 xdp_tx_swbd->len = len; 1330 xdp_tx_swbd->is_xdp_redirect = true; 1331 xdp_tx_swbd->is_eof = false; 1332 xdp_tx_swbd->xdp_frame = NULL; 1333 1334 n++; 1335 1336 if (!xdp_frame_has_frags(xdp_frame)) 1337 goto out; 1338 1339 xdp_tx_swbd = &xdp_tx_arr[n]; 1340 1341 shinfo = xdp_get_shared_info_from_frame(xdp_frame); 1342 1343 for (f = 0, frag = &shinfo->frags[0]; f < shinfo->nr_frags; 1344 f++, frag++) { 1345 data = skb_frag_address(frag); 1346 len = skb_frag_size(frag); 1347 1348 dma = dma_map_single(tx_ring->dev, data, len, DMA_TO_DEVICE); 1349 if (unlikely(dma_mapping_error(tx_ring->dev, dma))) { 1350 /* Undo the DMA mapping for all fragments */ 1351 while (--n >= 0) 1352 enetc_unmap_tx_buff(tx_ring, &xdp_tx_arr[n]); 1353 1354 netdev_err(tx_ring->ndev, "DMA map error\n"); 1355 return -1; 1356 } 1357 1358 xdp_tx_swbd->dma = dma; 1359 xdp_tx_swbd->dir = DMA_TO_DEVICE; 1360 xdp_tx_swbd->len = len; 1361 xdp_tx_swbd->is_xdp_redirect = true; 1362 xdp_tx_swbd->is_eof = false; 1363 xdp_tx_swbd->xdp_frame = NULL; 1364 1365 n++; 1366 xdp_tx_swbd = &xdp_tx_arr[n]; 1367 } 1368 out: 1369 xdp_tx_arr[n - 1].is_eof = true; 1370 xdp_tx_arr[n - 1].xdp_frame = xdp_frame; 1371 1372 return n; 1373 } 1374 1375 int enetc_xdp_xmit(struct net_device *ndev, int num_frames, 1376 struct xdp_frame **frames, u32 flags) 1377 { 1378 struct enetc_tx_swbd xdp_redirect_arr[ENETC_MAX_SKB_FRAGS] = {0}; 1379 struct enetc_ndev_priv *priv = netdev_priv(ndev); 1380 struct enetc_bdr *tx_ring; 1381 int xdp_tx_bd_cnt, i, k; 1382 int xdp_tx_frm_cnt = 0; 1383 1384 if (unlikely(test_bit(ENETC_TX_DOWN, &priv->flags))) 1385 return -ENETDOWN; 1386 1387 enetc_lock_mdio(); 1388 1389 tx_ring = priv->xdp_tx_ring[smp_processor_id()]; 1390 1391 prefetchw(ENETC_TXBD(*tx_ring, tx_ring->next_to_use)); 1392 1393 for (k = 0; k < num_frames; k++) { 1394 xdp_tx_bd_cnt = enetc_xdp_frame_to_xdp_tx_swbd(tx_ring, 1395 xdp_redirect_arr, 1396 frames[k]); 1397 if (unlikely(xdp_tx_bd_cnt < 0)) 1398 break; 1399 1400 if (unlikely(!enetc_xdp_tx(tx_ring, xdp_redirect_arr, 1401 xdp_tx_bd_cnt))) { 1402 for (i = 0; i < xdp_tx_bd_cnt; i++) 1403 enetc_unmap_tx_buff(tx_ring, 1404 &xdp_redirect_arr[i]); 1405 tx_ring->stats.xdp_tx_drops++; 1406 break; 1407 } 1408 1409 xdp_tx_frm_cnt++; 1410 } 1411 1412 if (unlikely((flags & XDP_XMIT_FLUSH) || k != xdp_tx_frm_cnt)) 1413 enetc_update_tx_ring_tail(tx_ring); 1414 1415 tx_ring->stats.xdp_tx += xdp_tx_frm_cnt; 1416 1417 enetc_unlock_mdio(); 1418 1419 return xdp_tx_frm_cnt; 1420 } 1421 EXPORT_SYMBOL_GPL(enetc_xdp_xmit); 1422 1423 static void enetc_map_rx_buff_to_xdp(struct enetc_bdr *rx_ring, int i, 1424 struct xdp_buff *xdp_buff, u16 size) 1425 { 1426 struct enetc_rx_swbd *rx_swbd = enetc_get_rx_buff(rx_ring, i, size); 1427 void *hard_start = page_address(rx_swbd->page) + rx_swbd->page_offset; 1428 1429 /* To be used for XDP_TX */ 1430 rx_swbd->len = size; 1431 1432 xdp_prepare_buff(xdp_buff, hard_start - rx_ring->buffer_offset, 1433 rx_ring->buffer_offset, size, false); 1434 } 1435 1436 static void enetc_add_rx_buff_to_xdp(struct enetc_bdr *rx_ring, int i, 1437 u16 size, struct xdp_buff *xdp_buff) 1438 { 1439 struct skb_shared_info *shinfo = xdp_get_shared_info_from_buff(xdp_buff); 1440 struct enetc_rx_swbd *rx_swbd = enetc_get_rx_buff(rx_ring, i, size); 1441 skb_frag_t *frag; 1442 1443 /* To be used for XDP_TX */ 1444 rx_swbd->len = size; 1445 1446 if (!xdp_buff_has_frags(xdp_buff)) { 1447 xdp_buff_set_frags_flag(xdp_buff); 1448 shinfo->xdp_frags_size = size; 1449 shinfo->nr_frags = 0; 1450 } else { 1451 shinfo->xdp_frags_size += size; 1452 } 1453 1454 if (page_is_pfmemalloc(rx_swbd->page)) 1455 xdp_buff_set_frag_pfmemalloc(xdp_buff); 1456 1457 frag = &shinfo->frags[shinfo->nr_frags]; 1458 skb_frag_fill_page_desc(frag, rx_swbd->page, rx_swbd->page_offset, 1459 size); 1460 1461 shinfo->nr_frags++; 1462 } 1463 1464 static void enetc_build_xdp_buff(struct enetc_bdr *rx_ring, u32 bd_status, 1465 union enetc_rx_bd **rxbd, int *i, 1466 int *cleaned_cnt, struct xdp_buff *xdp_buff) 1467 { 1468 u16 size = le16_to_cpu((*rxbd)->r.buf_len); 1469 1470 xdp_init_buff(xdp_buff, ENETC_RXB_TRUESIZE, &rx_ring->xdp.rxq); 1471 1472 enetc_map_rx_buff_to_xdp(rx_ring, *i, xdp_buff, size); 1473 (*cleaned_cnt)++; 1474 enetc_rxbd_next(rx_ring, rxbd, i); 1475 1476 /* not last BD in frame? */ 1477 while (!(bd_status & ENETC_RXBD_LSTATUS_F)) { 1478 bd_status = le32_to_cpu((*rxbd)->r.lstatus); 1479 size = ENETC_RXB_DMA_SIZE_XDP; 1480 1481 if (bd_status & ENETC_RXBD_LSTATUS_F) { 1482 dma_rmb(); 1483 size = le16_to_cpu((*rxbd)->r.buf_len); 1484 } 1485 1486 enetc_add_rx_buff_to_xdp(rx_ring, *i, size, xdp_buff); 1487 (*cleaned_cnt)++; 1488 enetc_rxbd_next(rx_ring, rxbd, i); 1489 } 1490 } 1491 1492 /* Convert RX buffer descriptors to TX buffer descriptors. These will be 1493 * recycled back into the RX ring in enetc_clean_tx_ring. 1494 */ 1495 static int enetc_rx_swbd_to_xdp_tx_swbd(struct enetc_tx_swbd *xdp_tx_arr, 1496 struct enetc_bdr *rx_ring, 1497 int rx_ring_first, int rx_ring_last) 1498 { 1499 int n = 0; 1500 1501 for (; rx_ring_first != rx_ring_last; 1502 n++, enetc_bdr_idx_inc(rx_ring, &rx_ring_first)) { 1503 struct enetc_rx_swbd *rx_swbd = &rx_ring->rx_swbd[rx_ring_first]; 1504 struct enetc_tx_swbd *tx_swbd = &xdp_tx_arr[n]; 1505 1506 /* No need to dma_map, we already have DMA_BIDIRECTIONAL */ 1507 tx_swbd->dma = rx_swbd->dma; 1508 tx_swbd->dir = rx_swbd->dir; 1509 tx_swbd->page = rx_swbd->page; 1510 tx_swbd->page_offset = rx_swbd->page_offset; 1511 tx_swbd->len = rx_swbd->len; 1512 tx_swbd->is_dma_page = true; 1513 tx_swbd->is_xdp_tx = true; 1514 tx_swbd->is_eof = false; 1515 } 1516 1517 /* We rely on caller providing an rx_ring_last > rx_ring_first */ 1518 xdp_tx_arr[n - 1].is_eof = true; 1519 1520 return n; 1521 } 1522 1523 static void enetc_xdp_drop(struct enetc_bdr *rx_ring, int rx_ring_first, 1524 int rx_ring_last) 1525 { 1526 while (rx_ring_first != rx_ring_last) { 1527 enetc_put_rx_buff(rx_ring, 1528 &rx_ring->rx_swbd[rx_ring_first]); 1529 enetc_bdr_idx_inc(rx_ring, &rx_ring_first); 1530 } 1531 } 1532 1533 static int enetc_clean_rx_ring_xdp(struct enetc_bdr *rx_ring, 1534 struct napi_struct *napi, int work_limit, 1535 struct bpf_prog *prog) 1536 { 1537 int xdp_tx_bd_cnt, xdp_tx_frm_cnt = 0, xdp_redirect_frm_cnt = 0; 1538 struct enetc_tx_swbd xdp_tx_arr[ENETC_MAX_SKB_FRAGS] = {0}; 1539 struct enetc_ndev_priv *priv = netdev_priv(rx_ring->ndev); 1540 int rx_frm_cnt = 0, rx_byte_cnt = 0; 1541 struct enetc_bdr *tx_ring; 1542 int cleaned_cnt, i; 1543 u32 xdp_act; 1544 1545 cleaned_cnt = enetc_bd_unused(rx_ring); 1546 /* next descriptor to process */ 1547 i = rx_ring->next_to_clean; 1548 1549 while (likely(rx_frm_cnt < work_limit)) { 1550 union enetc_rx_bd *rxbd, *orig_rxbd; 1551 int orig_i, orig_cleaned_cnt; 1552 struct xdp_buff xdp_buff; 1553 struct sk_buff *skb; 1554 u32 bd_status; 1555 int err; 1556 1557 rxbd = enetc_rxbd(rx_ring, i); 1558 bd_status = le32_to_cpu(rxbd->r.lstatus); 1559 if (!bd_status) 1560 break; 1561 1562 enetc_wr_reg_hot(rx_ring->idr, BIT(rx_ring->index)); 1563 dma_rmb(); /* for reading other rxbd fields */ 1564 1565 if (enetc_check_bd_errors_and_consume(rx_ring, bd_status, 1566 &rxbd, &i)) 1567 break; 1568 1569 orig_rxbd = rxbd; 1570 orig_cleaned_cnt = cleaned_cnt; 1571 orig_i = i; 1572 1573 enetc_build_xdp_buff(rx_ring, bd_status, &rxbd, &i, 1574 &cleaned_cnt, &xdp_buff); 1575 1576 /* When set, the outer VLAN header is extracted and reported 1577 * in the receive buffer descriptor. So rx_byte_cnt should 1578 * add the length of the extracted VLAN header. 1579 */ 1580 if (bd_status & ENETC_RXBD_FLAG_VLAN) 1581 rx_byte_cnt += VLAN_HLEN; 1582 rx_byte_cnt += xdp_get_buff_len(&xdp_buff); 1583 1584 xdp_act = bpf_prog_run_xdp(prog, &xdp_buff); 1585 1586 switch (xdp_act) { 1587 default: 1588 bpf_warn_invalid_xdp_action(rx_ring->ndev, prog, xdp_act); 1589 fallthrough; 1590 case XDP_ABORTED: 1591 trace_xdp_exception(rx_ring->ndev, prog, xdp_act); 1592 fallthrough; 1593 case XDP_DROP: 1594 enetc_xdp_drop(rx_ring, orig_i, i); 1595 rx_ring->stats.xdp_drops++; 1596 break; 1597 case XDP_PASS: 1598 rxbd = orig_rxbd; 1599 cleaned_cnt = orig_cleaned_cnt; 1600 i = orig_i; 1601 1602 skb = enetc_build_skb(rx_ring, bd_status, &rxbd, 1603 &i, &cleaned_cnt, 1604 ENETC_RXB_DMA_SIZE_XDP); 1605 if (unlikely(!skb)) 1606 goto out; 1607 1608 napi_gro_receive(napi, skb); 1609 break; 1610 case XDP_TX: 1611 tx_ring = priv->xdp_tx_ring[rx_ring->index]; 1612 if (unlikely(test_bit(ENETC_TX_DOWN, &priv->flags))) { 1613 enetc_xdp_drop(rx_ring, orig_i, i); 1614 tx_ring->stats.xdp_tx_drops++; 1615 break; 1616 } 1617 1618 xdp_tx_bd_cnt = enetc_rx_swbd_to_xdp_tx_swbd(xdp_tx_arr, 1619 rx_ring, 1620 orig_i, i); 1621 1622 if (!enetc_xdp_tx(tx_ring, xdp_tx_arr, xdp_tx_bd_cnt)) { 1623 enetc_xdp_drop(rx_ring, orig_i, i); 1624 tx_ring->stats.xdp_tx_drops++; 1625 } else { 1626 tx_ring->stats.xdp_tx += xdp_tx_bd_cnt; 1627 rx_ring->xdp.xdp_tx_in_flight += xdp_tx_bd_cnt; 1628 xdp_tx_frm_cnt++; 1629 /* The XDP_TX enqueue was successful, so we 1630 * need to scrub the RX software BDs because 1631 * the ownership of the buffers no longer 1632 * belongs to the RX ring, and we must prevent 1633 * enetc_refill_rx_ring() from reusing 1634 * rx_swbd->page. 1635 */ 1636 while (orig_i != i) { 1637 rx_ring->rx_swbd[orig_i].page = NULL; 1638 enetc_bdr_idx_inc(rx_ring, &orig_i); 1639 } 1640 } 1641 break; 1642 case XDP_REDIRECT: 1643 err = xdp_do_redirect(rx_ring->ndev, &xdp_buff, prog); 1644 if (unlikely(err)) { 1645 enetc_xdp_drop(rx_ring, orig_i, i); 1646 rx_ring->stats.xdp_redirect_failures++; 1647 } else { 1648 while (orig_i != i) { 1649 enetc_flip_rx_buff(rx_ring, 1650 &rx_ring->rx_swbd[orig_i]); 1651 enetc_bdr_idx_inc(rx_ring, &orig_i); 1652 } 1653 xdp_redirect_frm_cnt++; 1654 rx_ring->stats.xdp_redirect++; 1655 } 1656 } 1657 1658 rx_frm_cnt++; 1659 } 1660 1661 out: 1662 rx_ring->next_to_clean = i; 1663 1664 rx_ring->stats.packets += rx_frm_cnt; 1665 rx_ring->stats.bytes += rx_byte_cnt; 1666 1667 if (xdp_redirect_frm_cnt) 1668 xdp_do_flush_map(); 1669 1670 if (xdp_tx_frm_cnt) 1671 enetc_update_tx_ring_tail(tx_ring); 1672 1673 if (cleaned_cnt > rx_ring->xdp.xdp_tx_in_flight) 1674 enetc_refill_rx_ring(rx_ring, enetc_bd_unused(rx_ring) - 1675 rx_ring->xdp.xdp_tx_in_flight); 1676 1677 return rx_frm_cnt; 1678 } 1679 1680 static int enetc_poll(struct napi_struct *napi, int budget) 1681 { 1682 struct enetc_int_vector 1683 *v = container_of(napi, struct enetc_int_vector, napi); 1684 struct enetc_bdr *rx_ring = &v->rx_ring; 1685 struct bpf_prog *prog; 1686 bool complete = true; 1687 int work_done; 1688 int i; 1689 1690 enetc_lock_mdio(); 1691 1692 for (i = 0; i < v->count_tx_rings; i++) 1693 if (!enetc_clean_tx_ring(&v->tx_ring[i], budget)) 1694 complete = false; 1695 1696 prog = rx_ring->xdp.prog; 1697 if (prog) 1698 work_done = enetc_clean_rx_ring_xdp(rx_ring, napi, budget, prog); 1699 else 1700 work_done = enetc_clean_rx_ring(rx_ring, napi, budget); 1701 if (work_done == budget) 1702 complete = false; 1703 if (work_done) 1704 v->rx_napi_work = true; 1705 1706 if (!complete) { 1707 enetc_unlock_mdio(); 1708 return budget; 1709 } 1710 1711 napi_complete_done(napi, work_done); 1712 1713 if (likely(v->rx_dim_en)) 1714 enetc_rx_net_dim(v); 1715 1716 v->rx_napi_work = false; 1717 1718 /* enable interrupts */ 1719 enetc_wr_reg_hot(v->rbier, ENETC_RBIER_RXTIE); 1720 1721 for_each_set_bit(i, &v->tx_rings_map, ENETC_MAX_NUM_TXQS) 1722 enetc_wr_reg_hot(v->tbier_base + ENETC_BDR_OFF(i), 1723 ENETC_TBIER_TXTIE); 1724 1725 enetc_unlock_mdio(); 1726 1727 return work_done; 1728 } 1729 1730 /* Probing and Init */ 1731 #define ENETC_MAX_RFS_SIZE 64 1732 void enetc_get_si_caps(struct enetc_si *si) 1733 { 1734 struct enetc_hw *hw = &si->hw; 1735 u32 val; 1736 1737 /* find out how many of various resources we have to work with */ 1738 val = enetc_rd(hw, ENETC_SICAPR0); 1739 si->num_rx_rings = (val >> 16) & 0xff; 1740 si->num_tx_rings = val & 0xff; 1741 1742 val = enetc_rd(hw, ENETC_SIRFSCAPR); 1743 si->num_fs_entries = ENETC_SIRFSCAPR_GET_NUM_RFS(val); 1744 si->num_fs_entries = min(si->num_fs_entries, ENETC_MAX_RFS_SIZE); 1745 1746 si->num_rss = 0; 1747 val = enetc_rd(hw, ENETC_SIPCAPR0); 1748 if (val & ENETC_SIPCAPR0_RSS) { 1749 u32 rss; 1750 1751 rss = enetc_rd(hw, ENETC_SIRSSCAPR); 1752 si->num_rss = ENETC_SIRSSCAPR_GET_NUM_RSS(rss); 1753 } 1754 1755 if (val & ENETC_SIPCAPR0_QBV) 1756 si->hw_features |= ENETC_SI_F_QBV; 1757 1758 if (val & ENETC_SIPCAPR0_QBU) 1759 si->hw_features |= ENETC_SI_F_QBU; 1760 1761 if (val & ENETC_SIPCAPR0_PSFP) 1762 si->hw_features |= ENETC_SI_F_PSFP; 1763 } 1764 EXPORT_SYMBOL_GPL(enetc_get_si_caps); 1765 1766 static int enetc_dma_alloc_bdr(struct enetc_bdr_resource *res) 1767 { 1768 size_t bd_base_size = res->bd_count * res->bd_size; 1769 1770 res->bd_base = dma_alloc_coherent(res->dev, bd_base_size, 1771 &res->bd_dma_base, GFP_KERNEL); 1772 if (!res->bd_base) 1773 return -ENOMEM; 1774 1775 /* h/w requires 128B alignment */ 1776 if (!IS_ALIGNED(res->bd_dma_base, 128)) { 1777 dma_free_coherent(res->dev, bd_base_size, res->bd_base, 1778 res->bd_dma_base); 1779 return -EINVAL; 1780 } 1781 1782 return 0; 1783 } 1784 1785 static void enetc_dma_free_bdr(const struct enetc_bdr_resource *res) 1786 { 1787 size_t bd_base_size = res->bd_count * res->bd_size; 1788 1789 dma_free_coherent(res->dev, bd_base_size, res->bd_base, 1790 res->bd_dma_base); 1791 } 1792 1793 static int enetc_alloc_tx_resource(struct enetc_bdr_resource *res, 1794 struct device *dev, size_t bd_count) 1795 { 1796 int err; 1797 1798 res->dev = dev; 1799 res->bd_count = bd_count; 1800 res->bd_size = sizeof(union enetc_tx_bd); 1801 1802 res->tx_swbd = vcalloc(bd_count, sizeof(*res->tx_swbd)); 1803 if (!res->tx_swbd) 1804 return -ENOMEM; 1805 1806 err = enetc_dma_alloc_bdr(res); 1807 if (err) 1808 goto err_alloc_bdr; 1809 1810 res->tso_headers = dma_alloc_coherent(dev, bd_count * TSO_HEADER_SIZE, 1811 &res->tso_headers_dma, 1812 GFP_KERNEL); 1813 if (!res->tso_headers) { 1814 err = -ENOMEM; 1815 goto err_alloc_tso; 1816 } 1817 1818 return 0; 1819 1820 err_alloc_tso: 1821 enetc_dma_free_bdr(res); 1822 err_alloc_bdr: 1823 vfree(res->tx_swbd); 1824 res->tx_swbd = NULL; 1825 1826 return err; 1827 } 1828 1829 static void enetc_free_tx_resource(const struct enetc_bdr_resource *res) 1830 { 1831 dma_free_coherent(res->dev, res->bd_count * TSO_HEADER_SIZE, 1832 res->tso_headers, res->tso_headers_dma); 1833 enetc_dma_free_bdr(res); 1834 vfree(res->tx_swbd); 1835 } 1836 1837 static struct enetc_bdr_resource * 1838 enetc_alloc_tx_resources(struct enetc_ndev_priv *priv) 1839 { 1840 struct enetc_bdr_resource *tx_res; 1841 int i, err; 1842 1843 tx_res = kcalloc(priv->num_tx_rings, sizeof(*tx_res), GFP_KERNEL); 1844 if (!tx_res) 1845 return ERR_PTR(-ENOMEM); 1846 1847 for (i = 0; i < priv->num_tx_rings; i++) { 1848 struct enetc_bdr *tx_ring = priv->tx_ring[i]; 1849 1850 err = enetc_alloc_tx_resource(&tx_res[i], tx_ring->dev, 1851 tx_ring->bd_count); 1852 if (err) 1853 goto fail; 1854 } 1855 1856 return tx_res; 1857 1858 fail: 1859 while (i-- > 0) 1860 enetc_free_tx_resource(&tx_res[i]); 1861 1862 kfree(tx_res); 1863 1864 return ERR_PTR(err); 1865 } 1866 1867 static void enetc_free_tx_resources(const struct enetc_bdr_resource *tx_res, 1868 size_t num_resources) 1869 { 1870 size_t i; 1871 1872 for (i = 0; i < num_resources; i++) 1873 enetc_free_tx_resource(&tx_res[i]); 1874 1875 kfree(tx_res); 1876 } 1877 1878 static int enetc_alloc_rx_resource(struct enetc_bdr_resource *res, 1879 struct device *dev, size_t bd_count, 1880 bool extended) 1881 { 1882 int err; 1883 1884 res->dev = dev; 1885 res->bd_count = bd_count; 1886 res->bd_size = sizeof(union enetc_rx_bd); 1887 if (extended) 1888 res->bd_size *= 2; 1889 1890 res->rx_swbd = vcalloc(bd_count, sizeof(struct enetc_rx_swbd)); 1891 if (!res->rx_swbd) 1892 return -ENOMEM; 1893 1894 err = enetc_dma_alloc_bdr(res); 1895 if (err) { 1896 vfree(res->rx_swbd); 1897 return err; 1898 } 1899 1900 return 0; 1901 } 1902 1903 static void enetc_free_rx_resource(const struct enetc_bdr_resource *res) 1904 { 1905 enetc_dma_free_bdr(res); 1906 vfree(res->rx_swbd); 1907 } 1908 1909 static struct enetc_bdr_resource * 1910 enetc_alloc_rx_resources(struct enetc_ndev_priv *priv, bool extended) 1911 { 1912 struct enetc_bdr_resource *rx_res; 1913 int i, err; 1914 1915 rx_res = kcalloc(priv->num_rx_rings, sizeof(*rx_res), GFP_KERNEL); 1916 if (!rx_res) 1917 return ERR_PTR(-ENOMEM); 1918 1919 for (i = 0; i < priv->num_rx_rings; i++) { 1920 struct enetc_bdr *rx_ring = priv->rx_ring[i]; 1921 1922 err = enetc_alloc_rx_resource(&rx_res[i], rx_ring->dev, 1923 rx_ring->bd_count, extended); 1924 if (err) 1925 goto fail; 1926 } 1927 1928 return rx_res; 1929 1930 fail: 1931 while (i-- > 0) 1932 enetc_free_rx_resource(&rx_res[i]); 1933 1934 kfree(rx_res); 1935 1936 return ERR_PTR(err); 1937 } 1938 1939 static void enetc_free_rx_resources(const struct enetc_bdr_resource *rx_res, 1940 size_t num_resources) 1941 { 1942 size_t i; 1943 1944 for (i = 0; i < num_resources; i++) 1945 enetc_free_rx_resource(&rx_res[i]); 1946 1947 kfree(rx_res); 1948 } 1949 1950 static void enetc_assign_tx_resource(struct enetc_bdr *tx_ring, 1951 const struct enetc_bdr_resource *res) 1952 { 1953 tx_ring->bd_base = res ? res->bd_base : NULL; 1954 tx_ring->bd_dma_base = res ? res->bd_dma_base : 0; 1955 tx_ring->tx_swbd = res ? res->tx_swbd : NULL; 1956 tx_ring->tso_headers = res ? res->tso_headers : NULL; 1957 tx_ring->tso_headers_dma = res ? res->tso_headers_dma : 0; 1958 } 1959 1960 static void enetc_assign_rx_resource(struct enetc_bdr *rx_ring, 1961 const struct enetc_bdr_resource *res) 1962 { 1963 rx_ring->bd_base = res ? res->bd_base : NULL; 1964 rx_ring->bd_dma_base = res ? res->bd_dma_base : 0; 1965 rx_ring->rx_swbd = res ? res->rx_swbd : NULL; 1966 } 1967 1968 static void enetc_assign_tx_resources(struct enetc_ndev_priv *priv, 1969 const struct enetc_bdr_resource *res) 1970 { 1971 int i; 1972 1973 if (priv->tx_res) 1974 enetc_free_tx_resources(priv->tx_res, priv->num_tx_rings); 1975 1976 for (i = 0; i < priv->num_tx_rings; i++) { 1977 enetc_assign_tx_resource(priv->tx_ring[i], 1978 res ? &res[i] : NULL); 1979 } 1980 1981 priv->tx_res = res; 1982 } 1983 1984 static void enetc_assign_rx_resources(struct enetc_ndev_priv *priv, 1985 const struct enetc_bdr_resource *res) 1986 { 1987 int i; 1988 1989 if (priv->rx_res) 1990 enetc_free_rx_resources(priv->rx_res, priv->num_rx_rings); 1991 1992 for (i = 0; i < priv->num_rx_rings; i++) { 1993 enetc_assign_rx_resource(priv->rx_ring[i], 1994 res ? &res[i] : NULL); 1995 } 1996 1997 priv->rx_res = res; 1998 } 1999 2000 static void enetc_free_tx_ring(struct enetc_bdr *tx_ring) 2001 { 2002 int i; 2003 2004 for (i = 0; i < tx_ring->bd_count; i++) { 2005 struct enetc_tx_swbd *tx_swbd = &tx_ring->tx_swbd[i]; 2006 2007 enetc_free_tx_frame(tx_ring, tx_swbd); 2008 } 2009 } 2010 2011 static void enetc_free_rx_ring(struct enetc_bdr *rx_ring) 2012 { 2013 int i; 2014 2015 for (i = 0; i < rx_ring->bd_count; i++) { 2016 struct enetc_rx_swbd *rx_swbd = &rx_ring->rx_swbd[i]; 2017 2018 if (!rx_swbd->page) 2019 continue; 2020 2021 dma_unmap_page(rx_ring->dev, rx_swbd->dma, PAGE_SIZE, 2022 rx_swbd->dir); 2023 __free_page(rx_swbd->page); 2024 rx_swbd->page = NULL; 2025 } 2026 } 2027 2028 static void enetc_free_rxtx_rings(struct enetc_ndev_priv *priv) 2029 { 2030 int i; 2031 2032 for (i = 0; i < priv->num_rx_rings; i++) 2033 enetc_free_rx_ring(priv->rx_ring[i]); 2034 2035 for (i = 0; i < priv->num_tx_rings; i++) 2036 enetc_free_tx_ring(priv->tx_ring[i]); 2037 } 2038 2039 static int enetc_setup_default_rss_table(struct enetc_si *si, int num_groups) 2040 { 2041 int *rss_table; 2042 int i; 2043 2044 rss_table = kmalloc_array(si->num_rss, sizeof(*rss_table), GFP_KERNEL); 2045 if (!rss_table) 2046 return -ENOMEM; 2047 2048 /* Set up RSS table defaults */ 2049 for (i = 0; i < si->num_rss; i++) 2050 rss_table[i] = i % num_groups; 2051 2052 enetc_set_rss_table(si, rss_table, si->num_rss); 2053 2054 kfree(rss_table); 2055 2056 return 0; 2057 } 2058 2059 int enetc_configure_si(struct enetc_ndev_priv *priv) 2060 { 2061 struct enetc_si *si = priv->si; 2062 struct enetc_hw *hw = &si->hw; 2063 int err; 2064 2065 /* set SI cache attributes */ 2066 enetc_wr(hw, ENETC_SICAR0, 2067 ENETC_SICAR_RD_COHERENT | ENETC_SICAR_WR_COHERENT); 2068 enetc_wr(hw, ENETC_SICAR1, ENETC_SICAR_MSI); 2069 /* enable SI */ 2070 enetc_wr(hw, ENETC_SIMR, ENETC_SIMR_EN); 2071 2072 if (si->num_rss) { 2073 err = enetc_setup_default_rss_table(si, priv->num_rx_rings); 2074 if (err) 2075 return err; 2076 } 2077 2078 return 0; 2079 } 2080 EXPORT_SYMBOL_GPL(enetc_configure_si); 2081 2082 void enetc_init_si_rings_params(struct enetc_ndev_priv *priv) 2083 { 2084 struct enetc_si *si = priv->si; 2085 int cpus = num_online_cpus(); 2086 2087 priv->tx_bd_count = ENETC_TX_RING_DEFAULT_SIZE; 2088 priv->rx_bd_count = ENETC_RX_RING_DEFAULT_SIZE; 2089 2090 /* Enable all available TX rings in order to configure as many 2091 * priorities as possible, when needed. 2092 * TODO: Make # of TX rings run-time configurable 2093 */ 2094 priv->num_rx_rings = min_t(int, cpus, si->num_rx_rings); 2095 priv->num_tx_rings = si->num_tx_rings; 2096 priv->bdr_int_num = cpus; 2097 priv->ic_mode = ENETC_IC_RX_ADAPTIVE | ENETC_IC_TX_MANUAL; 2098 priv->tx_ictt = ENETC_TXIC_TIMETHR; 2099 } 2100 EXPORT_SYMBOL_GPL(enetc_init_si_rings_params); 2101 2102 int enetc_alloc_si_resources(struct enetc_ndev_priv *priv) 2103 { 2104 struct enetc_si *si = priv->si; 2105 2106 priv->cls_rules = kcalloc(si->num_fs_entries, sizeof(*priv->cls_rules), 2107 GFP_KERNEL); 2108 if (!priv->cls_rules) 2109 return -ENOMEM; 2110 2111 return 0; 2112 } 2113 EXPORT_SYMBOL_GPL(enetc_alloc_si_resources); 2114 2115 void enetc_free_si_resources(struct enetc_ndev_priv *priv) 2116 { 2117 kfree(priv->cls_rules); 2118 } 2119 EXPORT_SYMBOL_GPL(enetc_free_si_resources); 2120 2121 static void enetc_setup_txbdr(struct enetc_hw *hw, struct enetc_bdr *tx_ring) 2122 { 2123 int idx = tx_ring->index; 2124 u32 tbmr; 2125 2126 enetc_txbdr_wr(hw, idx, ENETC_TBBAR0, 2127 lower_32_bits(tx_ring->bd_dma_base)); 2128 2129 enetc_txbdr_wr(hw, idx, ENETC_TBBAR1, 2130 upper_32_bits(tx_ring->bd_dma_base)); 2131 2132 WARN_ON(!IS_ALIGNED(tx_ring->bd_count, 64)); /* multiple of 64 */ 2133 enetc_txbdr_wr(hw, idx, ENETC_TBLENR, 2134 ENETC_RTBLENR_LEN(tx_ring->bd_count)); 2135 2136 /* clearing PI/CI registers for Tx not supported, adjust sw indexes */ 2137 tx_ring->next_to_use = enetc_txbdr_rd(hw, idx, ENETC_TBPIR); 2138 tx_ring->next_to_clean = enetc_txbdr_rd(hw, idx, ENETC_TBCIR); 2139 2140 /* enable Tx ints by setting pkt thr to 1 */ 2141 enetc_txbdr_wr(hw, idx, ENETC_TBICR0, ENETC_TBICR0_ICEN | 0x1); 2142 2143 tbmr = ENETC_TBMR_SET_PRIO(tx_ring->prio); 2144 if (tx_ring->ndev->features & NETIF_F_HW_VLAN_CTAG_TX) 2145 tbmr |= ENETC_TBMR_VIH; 2146 2147 /* enable ring */ 2148 enetc_txbdr_wr(hw, idx, ENETC_TBMR, tbmr); 2149 2150 tx_ring->tpir = hw->reg + ENETC_BDR(TX, idx, ENETC_TBPIR); 2151 tx_ring->tcir = hw->reg + ENETC_BDR(TX, idx, ENETC_TBCIR); 2152 tx_ring->idr = hw->reg + ENETC_SITXIDR; 2153 } 2154 2155 static void enetc_setup_rxbdr(struct enetc_hw *hw, struct enetc_bdr *rx_ring, 2156 bool extended) 2157 { 2158 int idx = rx_ring->index; 2159 u32 rbmr = 0; 2160 2161 enetc_rxbdr_wr(hw, idx, ENETC_RBBAR0, 2162 lower_32_bits(rx_ring->bd_dma_base)); 2163 2164 enetc_rxbdr_wr(hw, idx, ENETC_RBBAR1, 2165 upper_32_bits(rx_ring->bd_dma_base)); 2166 2167 WARN_ON(!IS_ALIGNED(rx_ring->bd_count, 64)); /* multiple of 64 */ 2168 enetc_rxbdr_wr(hw, idx, ENETC_RBLENR, 2169 ENETC_RTBLENR_LEN(rx_ring->bd_count)); 2170 2171 if (rx_ring->xdp.prog) 2172 enetc_rxbdr_wr(hw, idx, ENETC_RBBSR, ENETC_RXB_DMA_SIZE_XDP); 2173 else 2174 enetc_rxbdr_wr(hw, idx, ENETC_RBBSR, ENETC_RXB_DMA_SIZE); 2175 2176 /* Also prepare the consumer index in case page allocation never 2177 * succeeds. In that case, hardware will never advance producer index 2178 * to match consumer index, and will drop all frames. 2179 */ 2180 enetc_rxbdr_wr(hw, idx, ENETC_RBPIR, 0); 2181 enetc_rxbdr_wr(hw, idx, ENETC_RBCIR, 1); 2182 2183 /* enable Rx ints by setting pkt thr to 1 */ 2184 enetc_rxbdr_wr(hw, idx, ENETC_RBICR0, ENETC_RBICR0_ICEN | 0x1); 2185 2186 rx_ring->ext_en = extended; 2187 if (rx_ring->ext_en) 2188 rbmr |= ENETC_RBMR_BDS; 2189 2190 if (rx_ring->ndev->features & NETIF_F_HW_VLAN_CTAG_RX) 2191 rbmr |= ENETC_RBMR_VTE; 2192 2193 rx_ring->rcir = hw->reg + ENETC_BDR(RX, idx, ENETC_RBCIR); 2194 rx_ring->idr = hw->reg + ENETC_SIRXIDR; 2195 2196 rx_ring->next_to_clean = 0; 2197 rx_ring->next_to_use = 0; 2198 rx_ring->next_to_alloc = 0; 2199 2200 enetc_lock_mdio(); 2201 enetc_refill_rx_ring(rx_ring, enetc_bd_unused(rx_ring)); 2202 enetc_unlock_mdio(); 2203 2204 enetc_rxbdr_wr(hw, idx, ENETC_RBMR, rbmr); 2205 } 2206 2207 static void enetc_setup_bdrs(struct enetc_ndev_priv *priv, bool extended) 2208 { 2209 struct enetc_hw *hw = &priv->si->hw; 2210 int i; 2211 2212 for (i = 0; i < priv->num_tx_rings; i++) 2213 enetc_setup_txbdr(hw, priv->tx_ring[i]); 2214 2215 for (i = 0; i < priv->num_rx_rings; i++) 2216 enetc_setup_rxbdr(hw, priv->rx_ring[i], extended); 2217 } 2218 2219 static void enetc_enable_txbdr(struct enetc_hw *hw, struct enetc_bdr *tx_ring) 2220 { 2221 int idx = tx_ring->index; 2222 u32 tbmr; 2223 2224 tbmr = enetc_txbdr_rd(hw, idx, ENETC_TBMR); 2225 tbmr |= ENETC_TBMR_EN; 2226 enetc_txbdr_wr(hw, idx, ENETC_TBMR, tbmr); 2227 } 2228 2229 static void enetc_enable_rxbdr(struct enetc_hw *hw, struct enetc_bdr *rx_ring) 2230 { 2231 int idx = rx_ring->index; 2232 u32 rbmr; 2233 2234 rbmr = enetc_rxbdr_rd(hw, idx, ENETC_RBMR); 2235 rbmr |= ENETC_RBMR_EN; 2236 enetc_rxbdr_wr(hw, idx, ENETC_RBMR, rbmr); 2237 } 2238 2239 static void enetc_enable_bdrs(struct enetc_ndev_priv *priv) 2240 { 2241 struct enetc_hw *hw = &priv->si->hw; 2242 int i; 2243 2244 for (i = 0; i < priv->num_tx_rings; i++) 2245 enetc_enable_txbdr(hw, priv->tx_ring[i]); 2246 2247 for (i = 0; i < priv->num_rx_rings; i++) 2248 enetc_enable_rxbdr(hw, priv->rx_ring[i]); 2249 } 2250 2251 static void enetc_disable_rxbdr(struct enetc_hw *hw, struct enetc_bdr *rx_ring) 2252 { 2253 int idx = rx_ring->index; 2254 2255 /* disable EN bit on ring */ 2256 enetc_rxbdr_wr(hw, idx, ENETC_RBMR, 0); 2257 } 2258 2259 static void enetc_disable_txbdr(struct enetc_hw *hw, struct enetc_bdr *rx_ring) 2260 { 2261 int idx = rx_ring->index; 2262 2263 /* disable EN bit on ring */ 2264 enetc_txbdr_wr(hw, idx, ENETC_TBMR, 0); 2265 } 2266 2267 static void enetc_disable_bdrs(struct enetc_ndev_priv *priv) 2268 { 2269 struct enetc_hw *hw = &priv->si->hw; 2270 int i; 2271 2272 for (i = 0; i < priv->num_tx_rings; i++) 2273 enetc_disable_txbdr(hw, priv->tx_ring[i]); 2274 2275 for (i = 0; i < priv->num_rx_rings; i++) 2276 enetc_disable_rxbdr(hw, priv->rx_ring[i]); 2277 } 2278 2279 static void enetc_wait_txbdr(struct enetc_hw *hw, struct enetc_bdr *tx_ring) 2280 { 2281 int delay = 8, timeout = 100; 2282 int idx = tx_ring->index; 2283 2284 /* wait for busy to clear */ 2285 while (delay < timeout && 2286 enetc_txbdr_rd(hw, idx, ENETC_TBSR) & ENETC_TBSR_BUSY) { 2287 msleep(delay); 2288 delay *= 2; 2289 } 2290 2291 if (delay >= timeout) 2292 netdev_warn(tx_ring->ndev, "timeout for tx ring #%d clear\n", 2293 idx); 2294 } 2295 2296 static void enetc_wait_bdrs(struct enetc_ndev_priv *priv) 2297 { 2298 struct enetc_hw *hw = &priv->si->hw; 2299 int i; 2300 2301 for (i = 0; i < priv->num_tx_rings; i++) 2302 enetc_wait_txbdr(hw, priv->tx_ring[i]); 2303 } 2304 2305 static int enetc_setup_irqs(struct enetc_ndev_priv *priv) 2306 { 2307 struct pci_dev *pdev = priv->si->pdev; 2308 struct enetc_hw *hw = &priv->si->hw; 2309 int i, j, err; 2310 2311 for (i = 0; i < priv->bdr_int_num; i++) { 2312 int irq = pci_irq_vector(pdev, ENETC_BDR_INT_BASE_IDX + i); 2313 struct enetc_int_vector *v = priv->int_vector[i]; 2314 int entry = ENETC_BDR_INT_BASE_IDX + i; 2315 2316 snprintf(v->name, sizeof(v->name), "%s-rxtx%d", 2317 priv->ndev->name, i); 2318 err = request_irq(irq, enetc_msix, IRQF_NO_AUTOEN, v->name, v); 2319 if (err) { 2320 dev_err(priv->dev, "request_irq() failed!\n"); 2321 goto irq_err; 2322 } 2323 2324 v->tbier_base = hw->reg + ENETC_BDR(TX, 0, ENETC_TBIER); 2325 v->rbier = hw->reg + ENETC_BDR(RX, i, ENETC_RBIER); 2326 v->ricr1 = hw->reg + ENETC_BDR(RX, i, ENETC_RBICR1); 2327 2328 enetc_wr(hw, ENETC_SIMSIRRV(i), entry); 2329 2330 for (j = 0; j < v->count_tx_rings; j++) { 2331 int idx = v->tx_ring[j].index; 2332 2333 enetc_wr(hw, ENETC_SIMSITRV(idx), entry); 2334 } 2335 irq_set_affinity_hint(irq, get_cpu_mask(i % num_online_cpus())); 2336 } 2337 2338 return 0; 2339 2340 irq_err: 2341 while (i--) { 2342 int irq = pci_irq_vector(pdev, ENETC_BDR_INT_BASE_IDX + i); 2343 2344 irq_set_affinity_hint(irq, NULL); 2345 free_irq(irq, priv->int_vector[i]); 2346 } 2347 2348 return err; 2349 } 2350 2351 static void enetc_free_irqs(struct enetc_ndev_priv *priv) 2352 { 2353 struct pci_dev *pdev = priv->si->pdev; 2354 int i; 2355 2356 for (i = 0; i < priv->bdr_int_num; i++) { 2357 int irq = pci_irq_vector(pdev, ENETC_BDR_INT_BASE_IDX + i); 2358 2359 irq_set_affinity_hint(irq, NULL); 2360 free_irq(irq, priv->int_vector[i]); 2361 } 2362 } 2363 2364 static void enetc_setup_interrupts(struct enetc_ndev_priv *priv) 2365 { 2366 struct enetc_hw *hw = &priv->si->hw; 2367 u32 icpt, ictt; 2368 int i; 2369 2370 /* enable Tx & Rx event indication */ 2371 if (priv->ic_mode & 2372 (ENETC_IC_RX_MANUAL | ENETC_IC_RX_ADAPTIVE)) { 2373 icpt = ENETC_RBICR0_SET_ICPT(ENETC_RXIC_PKTTHR); 2374 /* init to non-0 minimum, will be adjusted later */ 2375 ictt = 0x1; 2376 } else { 2377 icpt = 0x1; /* enable Rx ints by setting pkt thr to 1 */ 2378 ictt = 0; 2379 } 2380 2381 for (i = 0; i < priv->num_rx_rings; i++) { 2382 enetc_rxbdr_wr(hw, i, ENETC_RBICR1, ictt); 2383 enetc_rxbdr_wr(hw, i, ENETC_RBICR0, ENETC_RBICR0_ICEN | icpt); 2384 enetc_rxbdr_wr(hw, i, ENETC_RBIER, ENETC_RBIER_RXTIE); 2385 } 2386 2387 if (priv->ic_mode & ENETC_IC_TX_MANUAL) 2388 icpt = ENETC_TBICR0_SET_ICPT(ENETC_TXIC_PKTTHR); 2389 else 2390 icpt = 0x1; /* enable Tx ints by setting pkt thr to 1 */ 2391 2392 for (i = 0; i < priv->num_tx_rings; i++) { 2393 enetc_txbdr_wr(hw, i, ENETC_TBICR1, priv->tx_ictt); 2394 enetc_txbdr_wr(hw, i, ENETC_TBICR0, ENETC_TBICR0_ICEN | icpt); 2395 enetc_txbdr_wr(hw, i, ENETC_TBIER, ENETC_TBIER_TXTIE); 2396 } 2397 } 2398 2399 static void enetc_clear_interrupts(struct enetc_ndev_priv *priv) 2400 { 2401 struct enetc_hw *hw = &priv->si->hw; 2402 int i; 2403 2404 for (i = 0; i < priv->num_tx_rings; i++) 2405 enetc_txbdr_wr(hw, i, ENETC_TBIER, 0); 2406 2407 for (i = 0; i < priv->num_rx_rings; i++) 2408 enetc_rxbdr_wr(hw, i, ENETC_RBIER, 0); 2409 } 2410 2411 static int enetc_phylink_connect(struct net_device *ndev) 2412 { 2413 struct enetc_ndev_priv *priv = netdev_priv(ndev); 2414 struct ethtool_eee edata; 2415 int err; 2416 2417 if (!priv->phylink) { 2418 /* phy-less mode */ 2419 netif_carrier_on(ndev); 2420 return 0; 2421 } 2422 2423 err = phylink_of_phy_connect(priv->phylink, priv->dev->of_node, 0); 2424 if (err) { 2425 dev_err(&ndev->dev, "could not attach to PHY\n"); 2426 return err; 2427 } 2428 2429 /* disable EEE autoneg, until ENETC driver supports it */ 2430 memset(&edata, 0, sizeof(struct ethtool_eee)); 2431 phylink_ethtool_set_eee(priv->phylink, &edata); 2432 2433 phylink_start(priv->phylink); 2434 2435 return 0; 2436 } 2437 2438 static void enetc_tx_onestep_tstamp(struct work_struct *work) 2439 { 2440 struct enetc_ndev_priv *priv; 2441 struct sk_buff *skb; 2442 2443 priv = container_of(work, struct enetc_ndev_priv, tx_onestep_tstamp); 2444 2445 netif_tx_lock_bh(priv->ndev); 2446 2447 clear_bit_unlock(ENETC_TX_ONESTEP_TSTAMP_IN_PROGRESS, &priv->flags); 2448 skb = skb_dequeue(&priv->tx_skbs); 2449 if (skb) 2450 enetc_start_xmit(skb, priv->ndev); 2451 2452 netif_tx_unlock_bh(priv->ndev); 2453 } 2454 2455 static void enetc_tx_onestep_tstamp_init(struct enetc_ndev_priv *priv) 2456 { 2457 INIT_WORK(&priv->tx_onestep_tstamp, enetc_tx_onestep_tstamp); 2458 skb_queue_head_init(&priv->tx_skbs); 2459 } 2460 2461 void enetc_start(struct net_device *ndev) 2462 { 2463 struct enetc_ndev_priv *priv = netdev_priv(ndev); 2464 int i; 2465 2466 enetc_setup_interrupts(priv); 2467 2468 for (i = 0; i < priv->bdr_int_num; i++) { 2469 int irq = pci_irq_vector(priv->si->pdev, 2470 ENETC_BDR_INT_BASE_IDX + i); 2471 2472 napi_enable(&priv->int_vector[i]->napi); 2473 enable_irq(irq); 2474 } 2475 2476 enetc_enable_bdrs(priv); 2477 2478 netif_tx_start_all_queues(ndev); 2479 2480 clear_bit(ENETC_TX_DOWN, &priv->flags); 2481 } 2482 EXPORT_SYMBOL_GPL(enetc_start); 2483 2484 int enetc_open(struct net_device *ndev) 2485 { 2486 struct enetc_ndev_priv *priv = netdev_priv(ndev); 2487 struct enetc_bdr_resource *tx_res, *rx_res; 2488 bool extended; 2489 int err; 2490 2491 extended = !!(priv->active_offloads & ENETC_F_RX_TSTAMP); 2492 2493 err = enetc_setup_irqs(priv); 2494 if (err) 2495 return err; 2496 2497 err = enetc_phylink_connect(ndev); 2498 if (err) 2499 goto err_phy_connect; 2500 2501 tx_res = enetc_alloc_tx_resources(priv); 2502 if (IS_ERR(tx_res)) { 2503 err = PTR_ERR(tx_res); 2504 goto err_alloc_tx; 2505 } 2506 2507 rx_res = enetc_alloc_rx_resources(priv, extended); 2508 if (IS_ERR(rx_res)) { 2509 err = PTR_ERR(rx_res); 2510 goto err_alloc_rx; 2511 } 2512 2513 enetc_tx_onestep_tstamp_init(priv); 2514 enetc_assign_tx_resources(priv, tx_res); 2515 enetc_assign_rx_resources(priv, rx_res); 2516 enetc_setup_bdrs(priv, extended); 2517 enetc_start(ndev); 2518 2519 return 0; 2520 2521 err_alloc_rx: 2522 enetc_free_tx_resources(tx_res, priv->num_tx_rings); 2523 err_alloc_tx: 2524 if (priv->phylink) 2525 phylink_disconnect_phy(priv->phylink); 2526 err_phy_connect: 2527 enetc_free_irqs(priv); 2528 2529 return err; 2530 } 2531 EXPORT_SYMBOL_GPL(enetc_open); 2532 2533 void enetc_stop(struct net_device *ndev) 2534 { 2535 struct enetc_ndev_priv *priv = netdev_priv(ndev); 2536 int i; 2537 2538 set_bit(ENETC_TX_DOWN, &priv->flags); 2539 2540 netif_tx_stop_all_queues(ndev); 2541 2542 enetc_disable_bdrs(priv); 2543 2544 for (i = 0; i < priv->bdr_int_num; i++) { 2545 int irq = pci_irq_vector(priv->si->pdev, 2546 ENETC_BDR_INT_BASE_IDX + i); 2547 2548 disable_irq(irq); 2549 napi_synchronize(&priv->int_vector[i]->napi); 2550 napi_disable(&priv->int_vector[i]->napi); 2551 } 2552 2553 enetc_wait_bdrs(priv); 2554 2555 enetc_clear_interrupts(priv); 2556 } 2557 EXPORT_SYMBOL_GPL(enetc_stop); 2558 2559 int enetc_close(struct net_device *ndev) 2560 { 2561 struct enetc_ndev_priv *priv = netdev_priv(ndev); 2562 2563 enetc_stop(ndev); 2564 2565 if (priv->phylink) { 2566 phylink_stop(priv->phylink); 2567 phylink_disconnect_phy(priv->phylink); 2568 } else { 2569 netif_carrier_off(ndev); 2570 } 2571 2572 enetc_free_rxtx_rings(priv); 2573 2574 /* Avoids dangling pointers and also frees old resources */ 2575 enetc_assign_rx_resources(priv, NULL); 2576 enetc_assign_tx_resources(priv, NULL); 2577 2578 enetc_free_irqs(priv); 2579 2580 return 0; 2581 } 2582 EXPORT_SYMBOL_GPL(enetc_close); 2583 2584 static int enetc_reconfigure(struct enetc_ndev_priv *priv, bool extended, 2585 int (*cb)(struct enetc_ndev_priv *priv, void *ctx), 2586 void *ctx) 2587 { 2588 struct enetc_bdr_resource *tx_res, *rx_res; 2589 int err; 2590 2591 ASSERT_RTNL(); 2592 2593 /* If the interface is down, run the callback right away, 2594 * without reconfiguration. 2595 */ 2596 if (!netif_running(priv->ndev)) { 2597 if (cb) { 2598 err = cb(priv, ctx); 2599 if (err) 2600 return err; 2601 } 2602 2603 return 0; 2604 } 2605 2606 tx_res = enetc_alloc_tx_resources(priv); 2607 if (IS_ERR(tx_res)) { 2608 err = PTR_ERR(tx_res); 2609 goto out; 2610 } 2611 2612 rx_res = enetc_alloc_rx_resources(priv, extended); 2613 if (IS_ERR(rx_res)) { 2614 err = PTR_ERR(rx_res); 2615 goto out_free_tx_res; 2616 } 2617 2618 enetc_stop(priv->ndev); 2619 enetc_free_rxtx_rings(priv); 2620 2621 /* Interface is down, run optional callback now */ 2622 if (cb) { 2623 err = cb(priv, ctx); 2624 if (err) 2625 goto out_restart; 2626 } 2627 2628 enetc_assign_tx_resources(priv, tx_res); 2629 enetc_assign_rx_resources(priv, rx_res); 2630 enetc_setup_bdrs(priv, extended); 2631 enetc_start(priv->ndev); 2632 2633 return 0; 2634 2635 out_restart: 2636 enetc_setup_bdrs(priv, extended); 2637 enetc_start(priv->ndev); 2638 enetc_free_rx_resources(rx_res, priv->num_rx_rings); 2639 out_free_tx_res: 2640 enetc_free_tx_resources(tx_res, priv->num_tx_rings); 2641 out: 2642 return err; 2643 } 2644 2645 static void enetc_debug_tx_ring_prios(struct enetc_ndev_priv *priv) 2646 { 2647 int i; 2648 2649 for (i = 0; i < priv->num_tx_rings; i++) 2650 netdev_dbg(priv->ndev, "TX ring %d prio %d\n", i, 2651 priv->tx_ring[i]->prio); 2652 } 2653 2654 void enetc_reset_tc_mqprio(struct net_device *ndev) 2655 { 2656 struct enetc_ndev_priv *priv = netdev_priv(ndev); 2657 struct enetc_hw *hw = &priv->si->hw; 2658 struct enetc_bdr *tx_ring; 2659 int num_stack_tx_queues; 2660 int i; 2661 2662 num_stack_tx_queues = enetc_num_stack_tx_queues(priv); 2663 2664 netdev_reset_tc(ndev); 2665 netif_set_real_num_tx_queues(ndev, num_stack_tx_queues); 2666 priv->min_num_stack_tx_queues = num_possible_cpus(); 2667 2668 /* Reset all ring priorities to 0 */ 2669 for (i = 0; i < priv->num_tx_rings; i++) { 2670 tx_ring = priv->tx_ring[i]; 2671 tx_ring->prio = 0; 2672 enetc_set_bdr_prio(hw, tx_ring->index, tx_ring->prio); 2673 } 2674 2675 enetc_debug_tx_ring_prios(priv); 2676 2677 enetc_change_preemptible_tcs(priv, 0); 2678 } 2679 EXPORT_SYMBOL_GPL(enetc_reset_tc_mqprio); 2680 2681 int enetc_setup_tc_mqprio(struct net_device *ndev, void *type_data) 2682 { 2683 struct tc_mqprio_qopt_offload *mqprio = type_data; 2684 struct enetc_ndev_priv *priv = netdev_priv(ndev); 2685 struct tc_mqprio_qopt *qopt = &mqprio->qopt; 2686 struct enetc_hw *hw = &priv->si->hw; 2687 int num_stack_tx_queues = 0; 2688 struct enetc_bdr *tx_ring; 2689 u8 num_tc = qopt->num_tc; 2690 int offset, count; 2691 int err, tc, q; 2692 2693 if (!num_tc) { 2694 enetc_reset_tc_mqprio(ndev); 2695 return 0; 2696 } 2697 2698 err = netdev_set_num_tc(ndev, num_tc); 2699 if (err) 2700 return err; 2701 2702 for (tc = 0; tc < num_tc; tc++) { 2703 offset = qopt->offset[tc]; 2704 count = qopt->count[tc]; 2705 num_stack_tx_queues += count; 2706 2707 err = netdev_set_tc_queue(ndev, tc, count, offset); 2708 if (err) 2709 goto err_reset_tc; 2710 2711 for (q = offset; q < offset + count; q++) { 2712 tx_ring = priv->tx_ring[q]; 2713 /* The prio_tc_map is skb_tx_hash()'s way of selecting 2714 * between TX queues based on skb->priority. As such, 2715 * there's nothing to offload based on it. 2716 * Make the mqprio "traffic class" be the priority of 2717 * this ring group, and leave the Tx IPV to traffic 2718 * class mapping as its default mapping value of 1:1. 2719 */ 2720 tx_ring->prio = tc; 2721 enetc_set_bdr_prio(hw, tx_ring->index, tx_ring->prio); 2722 } 2723 } 2724 2725 err = netif_set_real_num_tx_queues(ndev, num_stack_tx_queues); 2726 if (err) 2727 goto err_reset_tc; 2728 2729 priv->min_num_stack_tx_queues = num_stack_tx_queues; 2730 2731 enetc_debug_tx_ring_prios(priv); 2732 2733 enetc_change_preemptible_tcs(priv, mqprio->preemptible_tcs); 2734 2735 return 0; 2736 2737 err_reset_tc: 2738 enetc_reset_tc_mqprio(ndev); 2739 return err; 2740 } 2741 EXPORT_SYMBOL_GPL(enetc_setup_tc_mqprio); 2742 2743 static int enetc_reconfigure_xdp_cb(struct enetc_ndev_priv *priv, void *ctx) 2744 { 2745 struct bpf_prog *old_prog, *prog = ctx; 2746 int num_stack_tx_queues; 2747 int err, i; 2748 2749 old_prog = xchg(&priv->xdp_prog, prog); 2750 2751 num_stack_tx_queues = enetc_num_stack_tx_queues(priv); 2752 err = netif_set_real_num_tx_queues(priv->ndev, num_stack_tx_queues); 2753 if (err) { 2754 xchg(&priv->xdp_prog, old_prog); 2755 return err; 2756 } 2757 2758 if (old_prog) 2759 bpf_prog_put(old_prog); 2760 2761 for (i = 0; i < priv->num_rx_rings; i++) { 2762 struct enetc_bdr *rx_ring = priv->rx_ring[i]; 2763 2764 rx_ring->xdp.prog = prog; 2765 2766 if (prog) 2767 rx_ring->buffer_offset = XDP_PACKET_HEADROOM; 2768 else 2769 rx_ring->buffer_offset = ENETC_RXB_PAD; 2770 } 2771 2772 return 0; 2773 } 2774 2775 static int enetc_setup_xdp_prog(struct net_device *ndev, struct bpf_prog *prog, 2776 struct netlink_ext_ack *extack) 2777 { 2778 int num_xdp_tx_queues = prog ? num_possible_cpus() : 0; 2779 struct enetc_ndev_priv *priv = netdev_priv(ndev); 2780 bool extended; 2781 2782 if (priv->min_num_stack_tx_queues + num_xdp_tx_queues > 2783 priv->num_tx_rings) { 2784 NL_SET_ERR_MSG_FMT_MOD(extack, 2785 "Reserving %d XDP TXQs leaves under %d for stack (total %d)", 2786 num_xdp_tx_queues, 2787 priv->min_num_stack_tx_queues, 2788 priv->num_tx_rings); 2789 return -EBUSY; 2790 } 2791 2792 extended = !!(priv->active_offloads & ENETC_F_RX_TSTAMP); 2793 2794 /* The buffer layout is changing, so we need to drain the old 2795 * RX buffers and seed new ones. 2796 */ 2797 return enetc_reconfigure(priv, extended, enetc_reconfigure_xdp_cb, prog); 2798 } 2799 2800 int enetc_setup_bpf(struct net_device *ndev, struct netdev_bpf *bpf) 2801 { 2802 switch (bpf->command) { 2803 case XDP_SETUP_PROG: 2804 return enetc_setup_xdp_prog(ndev, bpf->prog, bpf->extack); 2805 default: 2806 return -EINVAL; 2807 } 2808 2809 return 0; 2810 } 2811 EXPORT_SYMBOL_GPL(enetc_setup_bpf); 2812 2813 struct net_device_stats *enetc_get_stats(struct net_device *ndev) 2814 { 2815 struct enetc_ndev_priv *priv = netdev_priv(ndev); 2816 struct net_device_stats *stats = &ndev->stats; 2817 unsigned long packets = 0, bytes = 0; 2818 unsigned long tx_dropped = 0; 2819 int i; 2820 2821 for (i = 0; i < priv->num_rx_rings; i++) { 2822 packets += priv->rx_ring[i]->stats.packets; 2823 bytes += priv->rx_ring[i]->stats.bytes; 2824 } 2825 2826 stats->rx_packets = packets; 2827 stats->rx_bytes = bytes; 2828 bytes = 0; 2829 packets = 0; 2830 2831 for (i = 0; i < priv->num_tx_rings; i++) { 2832 packets += priv->tx_ring[i]->stats.packets; 2833 bytes += priv->tx_ring[i]->stats.bytes; 2834 tx_dropped += priv->tx_ring[i]->stats.win_drop; 2835 } 2836 2837 stats->tx_packets = packets; 2838 stats->tx_bytes = bytes; 2839 stats->tx_dropped = tx_dropped; 2840 2841 return stats; 2842 } 2843 EXPORT_SYMBOL_GPL(enetc_get_stats); 2844 2845 static int enetc_set_rss(struct net_device *ndev, int en) 2846 { 2847 struct enetc_ndev_priv *priv = netdev_priv(ndev); 2848 struct enetc_hw *hw = &priv->si->hw; 2849 u32 reg; 2850 2851 enetc_wr(hw, ENETC_SIRBGCR, priv->num_rx_rings); 2852 2853 reg = enetc_rd(hw, ENETC_SIMR); 2854 reg &= ~ENETC_SIMR_RSSE; 2855 reg |= (en) ? ENETC_SIMR_RSSE : 0; 2856 enetc_wr(hw, ENETC_SIMR, reg); 2857 2858 return 0; 2859 } 2860 2861 static void enetc_enable_rxvlan(struct net_device *ndev, bool en) 2862 { 2863 struct enetc_ndev_priv *priv = netdev_priv(ndev); 2864 struct enetc_hw *hw = &priv->si->hw; 2865 int i; 2866 2867 for (i = 0; i < priv->num_rx_rings; i++) 2868 enetc_bdr_enable_rxvlan(hw, i, en); 2869 } 2870 2871 static void enetc_enable_txvlan(struct net_device *ndev, bool en) 2872 { 2873 struct enetc_ndev_priv *priv = netdev_priv(ndev); 2874 struct enetc_hw *hw = &priv->si->hw; 2875 int i; 2876 2877 for (i = 0; i < priv->num_tx_rings; i++) 2878 enetc_bdr_enable_txvlan(hw, i, en); 2879 } 2880 2881 void enetc_set_features(struct net_device *ndev, netdev_features_t features) 2882 { 2883 netdev_features_t changed = ndev->features ^ features; 2884 2885 if (changed & NETIF_F_RXHASH) 2886 enetc_set_rss(ndev, !!(features & NETIF_F_RXHASH)); 2887 2888 if (changed & NETIF_F_HW_VLAN_CTAG_RX) 2889 enetc_enable_rxvlan(ndev, 2890 !!(features & NETIF_F_HW_VLAN_CTAG_RX)); 2891 2892 if (changed & NETIF_F_HW_VLAN_CTAG_TX) 2893 enetc_enable_txvlan(ndev, 2894 !!(features & NETIF_F_HW_VLAN_CTAG_TX)); 2895 } 2896 EXPORT_SYMBOL_GPL(enetc_set_features); 2897 2898 #ifdef CONFIG_FSL_ENETC_PTP_CLOCK 2899 static int enetc_hwtstamp_set(struct net_device *ndev, struct ifreq *ifr) 2900 { 2901 struct enetc_ndev_priv *priv = netdev_priv(ndev); 2902 int err, new_offloads = priv->active_offloads; 2903 struct hwtstamp_config config; 2904 2905 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 2906 return -EFAULT; 2907 2908 switch (config.tx_type) { 2909 case HWTSTAMP_TX_OFF: 2910 new_offloads &= ~ENETC_F_TX_TSTAMP_MASK; 2911 break; 2912 case HWTSTAMP_TX_ON: 2913 new_offloads &= ~ENETC_F_TX_TSTAMP_MASK; 2914 new_offloads |= ENETC_F_TX_TSTAMP; 2915 break; 2916 case HWTSTAMP_TX_ONESTEP_SYNC: 2917 new_offloads &= ~ENETC_F_TX_TSTAMP_MASK; 2918 new_offloads |= ENETC_F_TX_ONESTEP_SYNC_TSTAMP; 2919 break; 2920 default: 2921 return -ERANGE; 2922 } 2923 2924 switch (config.rx_filter) { 2925 case HWTSTAMP_FILTER_NONE: 2926 new_offloads &= ~ENETC_F_RX_TSTAMP; 2927 break; 2928 default: 2929 new_offloads |= ENETC_F_RX_TSTAMP; 2930 config.rx_filter = HWTSTAMP_FILTER_ALL; 2931 } 2932 2933 if ((new_offloads ^ priv->active_offloads) & ENETC_F_RX_TSTAMP) { 2934 bool extended = !!(new_offloads & ENETC_F_RX_TSTAMP); 2935 2936 err = enetc_reconfigure(priv, extended, NULL, NULL); 2937 if (err) 2938 return err; 2939 } 2940 2941 priv->active_offloads = new_offloads; 2942 2943 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? 2944 -EFAULT : 0; 2945 } 2946 2947 static int enetc_hwtstamp_get(struct net_device *ndev, struct ifreq *ifr) 2948 { 2949 struct enetc_ndev_priv *priv = netdev_priv(ndev); 2950 struct hwtstamp_config config; 2951 2952 config.flags = 0; 2953 2954 if (priv->active_offloads & ENETC_F_TX_ONESTEP_SYNC_TSTAMP) 2955 config.tx_type = HWTSTAMP_TX_ONESTEP_SYNC; 2956 else if (priv->active_offloads & ENETC_F_TX_TSTAMP) 2957 config.tx_type = HWTSTAMP_TX_ON; 2958 else 2959 config.tx_type = HWTSTAMP_TX_OFF; 2960 2961 config.rx_filter = (priv->active_offloads & ENETC_F_RX_TSTAMP) ? 2962 HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE; 2963 2964 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? 2965 -EFAULT : 0; 2966 } 2967 #endif 2968 2969 int enetc_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) 2970 { 2971 struct enetc_ndev_priv *priv = netdev_priv(ndev); 2972 #ifdef CONFIG_FSL_ENETC_PTP_CLOCK 2973 if (cmd == SIOCSHWTSTAMP) 2974 return enetc_hwtstamp_set(ndev, rq); 2975 if (cmd == SIOCGHWTSTAMP) 2976 return enetc_hwtstamp_get(ndev, rq); 2977 #endif 2978 2979 if (!priv->phylink) 2980 return -EOPNOTSUPP; 2981 2982 return phylink_mii_ioctl(priv->phylink, rq, cmd); 2983 } 2984 EXPORT_SYMBOL_GPL(enetc_ioctl); 2985 2986 int enetc_alloc_msix(struct enetc_ndev_priv *priv) 2987 { 2988 struct pci_dev *pdev = priv->si->pdev; 2989 int num_stack_tx_queues; 2990 int first_xdp_tx_ring; 2991 int i, n, err, nvec; 2992 int v_tx_rings; 2993 2994 nvec = ENETC_BDR_INT_BASE_IDX + priv->bdr_int_num; 2995 /* allocate MSIX for both messaging and Rx/Tx interrupts */ 2996 n = pci_alloc_irq_vectors(pdev, nvec, nvec, PCI_IRQ_MSIX); 2997 2998 if (n < 0) 2999 return n; 3000 3001 if (n != nvec) 3002 return -EPERM; 3003 3004 /* # of tx rings per int vector */ 3005 v_tx_rings = priv->num_tx_rings / priv->bdr_int_num; 3006 3007 for (i = 0; i < priv->bdr_int_num; i++) { 3008 struct enetc_int_vector *v; 3009 struct enetc_bdr *bdr; 3010 int j; 3011 3012 v = kzalloc(struct_size(v, tx_ring, v_tx_rings), GFP_KERNEL); 3013 if (!v) { 3014 err = -ENOMEM; 3015 goto fail; 3016 } 3017 3018 priv->int_vector[i] = v; 3019 3020 bdr = &v->rx_ring; 3021 bdr->index = i; 3022 bdr->ndev = priv->ndev; 3023 bdr->dev = priv->dev; 3024 bdr->bd_count = priv->rx_bd_count; 3025 bdr->buffer_offset = ENETC_RXB_PAD; 3026 priv->rx_ring[i] = bdr; 3027 3028 err = xdp_rxq_info_reg(&bdr->xdp.rxq, priv->ndev, i, 0); 3029 if (err) { 3030 kfree(v); 3031 goto fail; 3032 } 3033 3034 err = xdp_rxq_info_reg_mem_model(&bdr->xdp.rxq, 3035 MEM_TYPE_PAGE_SHARED, NULL); 3036 if (err) { 3037 xdp_rxq_info_unreg(&bdr->xdp.rxq); 3038 kfree(v); 3039 goto fail; 3040 } 3041 3042 /* init defaults for adaptive IC */ 3043 if (priv->ic_mode & ENETC_IC_RX_ADAPTIVE) { 3044 v->rx_ictt = 0x1; 3045 v->rx_dim_en = true; 3046 } 3047 INIT_WORK(&v->rx_dim.work, enetc_rx_dim_work); 3048 netif_napi_add(priv->ndev, &v->napi, enetc_poll); 3049 v->count_tx_rings = v_tx_rings; 3050 3051 for (j = 0; j < v_tx_rings; j++) { 3052 int idx; 3053 3054 /* default tx ring mapping policy */ 3055 idx = priv->bdr_int_num * j + i; 3056 __set_bit(idx, &v->tx_rings_map); 3057 bdr = &v->tx_ring[j]; 3058 bdr->index = idx; 3059 bdr->ndev = priv->ndev; 3060 bdr->dev = priv->dev; 3061 bdr->bd_count = priv->tx_bd_count; 3062 priv->tx_ring[idx] = bdr; 3063 } 3064 } 3065 3066 num_stack_tx_queues = enetc_num_stack_tx_queues(priv); 3067 3068 err = netif_set_real_num_tx_queues(priv->ndev, num_stack_tx_queues); 3069 if (err) 3070 goto fail; 3071 3072 err = netif_set_real_num_rx_queues(priv->ndev, priv->num_rx_rings); 3073 if (err) 3074 goto fail; 3075 3076 priv->min_num_stack_tx_queues = num_possible_cpus(); 3077 first_xdp_tx_ring = priv->num_tx_rings - num_possible_cpus(); 3078 priv->xdp_tx_ring = &priv->tx_ring[first_xdp_tx_ring]; 3079 3080 return 0; 3081 3082 fail: 3083 while (i--) { 3084 struct enetc_int_vector *v = priv->int_vector[i]; 3085 struct enetc_bdr *rx_ring = &v->rx_ring; 3086 3087 xdp_rxq_info_unreg_mem_model(&rx_ring->xdp.rxq); 3088 xdp_rxq_info_unreg(&rx_ring->xdp.rxq); 3089 netif_napi_del(&v->napi); 3090 cancel_work_sync(&v->rx_dim.work); 3091 kfree(v); 3092 } 3093 3094 pci_free_irq_vectors(pdev); 3095 3096 return err; 3097 } 3098 EXPORT_SYMBOL_GPL(enetc_alloc_msix); 3099 3100 void enetc_free_msix(struct enetc_ndev_priv *priv) 3101 { 3102 int i; 3103 3104 for (i = 0; i < priv->bdr_int_num; i++) { 3105 struct enetc_int_vector *v = priv->int_vector[i]; 3106 struct enetc_bdr *rx_ring = &v->rx_ring; 3107 3108 xdp_rxq_info_unreg_mem_model(&rx_ring->xdp.rxq); 3109 xdp_rxq_info_unreg(&rx_ring->xdp.rxq); 3110 netif_napi_del(&v->napi); 3111 cancel_work_sync(&v->rx_dim.work); 3112 } 3113 3114 for (i = 0; i < priv->num_rx_rings; i++) 3115 priv->rx_ring[i] = NULL; 3116 3117 for (i = 0; i < priv->num_tx_rings; i++) 3118 priv->tx_ring[i] = NULL; 3119 3120 for (i = 0; i < priv->bdr_int_num; i++) { 3121 kfree(priv->int_vector[i]); 3122 priv->int_vector[i] = NULL; 3123 } 3124 3125 /* disable all MSIX for this device */ 3126 pci_free_irq_vectors(priv->si->pdev); 3127 } 3128 EXPORT_SYMBOL_GPL(enetc_free_msix); 3129 3130 static void enetc_kfree_si(struct enetc_si *si) 3131 { 3132 char *p = (char *)si - si->pad; 3133 3134 kfree(p); 3135 } 3136 3137 static void enetc_detect_errata(struct enetc_si *si) 3138 { 3139 if (si->pdev->revision == ENETC_REV1) 3140 si->errata = ENETC_ERR_VLAN_ISOL | ENETC_ERR_UCMCSWP; 3141 } 3142 3143 int enetc_pci_probe(struct pci_dev *pdev, const char *name, int sizeof_priv) 3144 { 3145 struct enetc_si *si, *p; 3146 struct enetc_hw *hw; 3147 size_t alloc_size; 3148 int err, len; 3149 3150 pcie_flr(pdev); 3151 err = pci_enable_device_mem(pdev); 3152 if (err) 3153 return dev_err_probe(&pdev->dev, err, "device enable failed\n"); 3154 3155 /* set up for high or low dma */ 3156 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 3157 if (err) { 3158 dev_err(&pdev->dev, "DMA configuration failed: 0x%x\n", err); 3159 goto err_dma; 3160 } 3161 3162 err = pci_request_mem_regions(pdev, name); 3163 if (err) { 3164 dev_err(&pdev->dev, "pci_request_regions failed err=%d\n", err); 3165 goto err_pci_mem_reg; 3166 } 3167 3168 pci_set_master(pdev); 3169 3170 alloc_size = sizeof(struct enetc_si); 3171 if (sizeof_priv) { 3172 /* align priv to 32B */ 3173 alloc_size = ALIGN(alloc_size, ENETC_SI_ALIGN); 3174 alloc_size += sizeof_priv; 3175 } 3176 /* force 32B alignment for enetc_si */ 3177 alloc_size += ENETC_SI_ALIGN - 1; 3178 3179 p = kzalloc(alloc_size, GFP_KERNEL); 3180 if (!p) { 3181 err = -ENOMEM; 3182 goto err_alloc_si; 3183 } 3184 3185 si = PTR_ALIGN(p, ENETC_SI_ALIGN); 3186 si->pad = (char *)si - (char *)p; 3187 3188 pci_set_drvdata(pdev, si); 3189 si->pdev = pdev; 3190 hw = &si->hw; 3191 3192 len = pci_resource_len(pdev, ENETC_BAR_REGS); 3193 hw->reg = ioremap(pci_resource_start(pdev, ENETC_BAR_REGS), len); 3194 if (!hw->reg) { 3195 err = -ENXIO; 3196 dev_err(&pdev->dev, "ioremap() failed\n"); 3197 goto err_ioremap; 3198 } 3199 if (len > ENETC_PORT_BASE) 3200 hw->port = hw->reg + ENETC_PORT_BASE; 3201 if (len > ENETC_GLOBAL_BASE) 3202 hw->global = hw->reg + ENETC_GLOBAL_BASE; 3203 3204 enetc_detect_errata(si); 3205 3206 return 0; 3207 3208 err_ioremap: 3209 enetc_kfree_si(si); 3210 err_alloc_si: 3211 pci_release_mem_regions(pdev); 3212 err_pci_mem_reg: 3213 err_dma: 3214 pci_disable_device(pdev); 3215 3216 return err; 3217 } 3218 EXPORT_SYMBOL_GPL(enetc_pci_probe); 3219 3220 void enetc_pci_remove(struct pci_dev *pdev) 3221 { 3222 struct enetc_si *si = pci_get_drvdata(pdev); 3223 struct enetc_hw *hw = &si->hw; 3224 3225 iounmap(hw->reg); 3226 enetc_kfree_si(si); 3227 pci_release_mem_regions(pdev); 3228 pci_disable_device(pdev); 3229 } 3230 EXPORT_SYMBOL_GPL(enetc_pci_remove); 3231 3232 MODULE_LICENSE("Dual BSD/GPL"); 3233