1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright 2014-2016 Freescale Semiconductor Inc.
4  * Copyright 2017-2021 NXP
5  *
6  */
7 
8 #ifndef __FSL_DPSW_CMD_H
9 #define __FSL_DPSW_CMD_H
10 
11 #include "dpsw.h"
12 
13 /* DPSW Version */
14 #define DPSW_VER_MAJOR		8
15 #define DPSW_VER_MINOR		9
16 
17 #define DPSW_CMD_BASE_VERSION	1
18 #define DPSW_CMD_VERSION_2	2
19 #define DPSW_CMD_ID_OFFSET	4
20 
21 #define DPSW_CMD_ID(id)	(((id) << DPSW_CMD_ID_OFFSET) | DPSW_CMD_BASE_VERSION)
22 #define DPSW_CMD_V2(id) (((id) << DPSW_CMD_ID_OFFSET) | DPSW_CMD_VERSION_2)
23 
24 /* Command IDs */
25 #define DPSW_CMDID_CLOSE                    DPSW_CMD_ID(0x800)
26 #define DPSW_CMDID_OPEN                     DPSW_CMD_ID(0x802)
27 
28 #define DPSW_CMDID_GET_API_VERSION          DPSW_CMD_ID(0xa02)
29 
30 #define DPSW_CMDID_ENABLE                   DPSW_CMD_ID(0x002)
31 #define DPSW_CMDID_DISABLE                  DPSW_CMD_ID(0x003)
32 #define DPSW_CMDID_GET_ATTR                 DPSW_CMD_V2(0x004)
33 #define DPSW_CMDID_RESET                    DPSW_CMD_ID(0x005)
34 
35 #define DPSW_CMDID_SET_IRQ_ENABLE           DPSW_CMD_ID(0x012)
36 
37 #define DPSW_CMDID_SET_IRQ_MASK             DPSW_CMD_ID(0x014)
38 
39 #define DPSW_CMDID_GET_IRQ_STATUS           DPSW_CMD_ID(0x016)
40 #define DPSW_CMDID_CLEAR_IRQ_STATUS         DPSW_CMD_ID(0x017)
41 
42 #define DPSW_CMDID_IF_SET_TCI               DPSW_CMD_ID(0x030)
43 #define DPSW_CMDID_IF_SET_STP               DPSW_CMD_ID(0x031)
44 
45 #define DPSW_CMDID_IF_GET_COUNTER           DPSW_CMD_V2(0x034)
46 
47 #define DPSW_CMDID_IF_ENABLE                DPSW_CMD_ID(0x03D)
48 #define DPSW_CMDID_IF_DISABLE               DPSW_CMD_ID(0x03E)
49 
50 #define DPSW_CMDID_IF_GET_ATTR              DPSW_CMD_ID(0x042)
51 
52 #define DPSW_CMDID_IF_SET_MAX_FRAME_LENGTH  DPSW_CMD_ID(0x044)
53 
54 #define DPSW_CMDID_IF_GET_LINK_STATE        DPSW_CMD_ID(0x046)
55 
56 #define DPSW_CMDID_IF_GET_TCI               DPSW_CMD_ID(0x04A)
57 
58 #define DPSW_CMDID_IF_SET_LINK_CFG          DPSW_CMD_ID(0x04C)
59 
60 #define DPSW_CMDID_VLAN_ADD                 DPSW_CMD_ID(0x060)
61 #define DPSW_CMDID_VLAN_ADD_IF              DPSW_CMD_V2(0x061)
62 #define DPSW_CMDID_VLAN_ADD_IF_UNTAGGED     DPSW_CMD_ID(0x062)
63 
64 #define DPSW_CMDID_VLAN_REMOVE_IF           DPSW_CMD_ID(0x064)
65 #define DPSW_CMDID_VLAN_REMOVE_IF_UNTAGGED  DPSW_CMD_ID(0x065)
66 #define DPSW_CMDID_VLAN_REMOVE_IF_FLOODING  DPSW_CMD_ID(0x066)
67 #define DPSW_CMDID_VLAN_REMOVE              DPSW_CMD_ID(0x067)
68 
69 #define DPSW_CMDID_FDB_ADD                  DPSW_CMD_ID(0x082)
70 #define DPSW_CMDID_FDB_REMOVE               DPSW_CMD_ID(0x083)
71 #define DPSW_CMDID_FDB_ADD_UNICAST          DPSW_CMD_ID(0x084)
72 #define DPSW_CMDID_FDB_REMOVE_UNICAST       DPSW_CMD_ID(0x085)
73 #define DPSW_CMDID_FDB_ADD_MULTICAST        DPSW_CMD_ID(0x086)
74 #define DPSW_CMDID_FDB_REMOVE_MULTICAST     DPSW_CMD_ID(0x087)
75 #define DPSW_CMDID_FDB_DUMP                 DPSW_CMD_ID(0x08A)
76 
77 #define DPSW_CMDID_ACL_ADD                  DPSW_CMD_ID(0x090)
78 #define DPSW_CMDID_ACL_REMOVE               DPSW_CMD_ID(0x091)
79 #define DPSW_CMDID_ACL_ADD_ENTRY            DPSW_CMD_ID(0x092)
80 #define DPSW_CMDID_ACL_REMOVE_ENTRY         DPSW_CMD_ID(0x093)
81 #define DPSW_CMDID_ACL_ADD_IF               DPSW_CMD_ID(0x094)
82 #define DPSW_CMDID_ACL_REMOVE_IF            DPSW_CMD_ID(0x095)
83 
84 #define DPSW_CMDID_IF_GET_PORT_MAC_ADDR     DPSW_CMD_ID(0x0A7)
85 
86 #define DPSW_CMDID_CTRL_IF_GET_ATTR         DPSW_CMD_ID(0x0A0)
87 #define DPSW_CMDID_CTRL_IF_SET_POOLS        DPSW_CMD_ID(0x0A1)
88 #define DPSW_CMDID_CTRL_IF_ENABLE           DPSW_CMD_ID(0x0A2)
89 #define DPSW_CMDID_CTRL_IF_DISABLE          DPSW_CMD_ID(0x0A3)
90 #define DPSW_CMDID_CTRL_IF_SET_QUEUE        DPSW_CMD_ID(0x0A6)
91 
92 #define DPSW_CMDID_SET_EGRESS_FLOOD         DPSW_CMD_ID(0x0AC)
93 #define DPSW_CMDID_IF_SET_LEARNING_MODE     DPSW_CMD_ID(0x0AD)
94 
95 /* Macros for accessing command fields smaller than 1byte */
96 #define DPSW_MASK(field)        \
97 	GENMASK(DPSW_##field##_SHIFT + DPSW_##field##_SIZE - 1, \
98 		DPSW_##field##_SHIFT)
99 #define dpsw_set_field(var, field, val) \
100 	((var) |= (((val) << DPSW_##field##_SHIFT) & DPSW_MASK(field)))
101 #define dpsw_get_field(var, field)      \
102 	(((var) & DPSW_MASK(field)) >> DPSW_##field##_SHIFT)
103 #define dpsw_get_bit(var, bit) \
104 	(((var)  >> (bit)) & GENMASK(0, 0))
105 
106 #pragma pack(push, 1)
107 struct dpsw_cmd_open {
108 	__le32 dpsw_id;
109 };
110 
111 #define DPSW_COMPONENT_TYPE_SHIFT	0
112 #define DPSW_COMPONENT_TYPE_SIZE	4
113 
114 struct dpsw_cmd_create {
115 	/* cmd word 0 */
116 	__le16 num_ifs;
117 	u8 max_fdbs;
118 	u8 max_meters_per_if;
119 	/* from LSB: only the first 4 bits */
120 	u8 component_type;
121 	u8 pad[3];
122 	/* cmd word 1 */
123 	__le16 max_vlans;
124 	__le16 max_fdb_entries;
125 	__le16 fdb_aging_time;
126 	__le16 max_fdb_mc_groups;
127 	/* cmd word 2 */
128 	__le64 options;
129 };
130 
131 struct dpsw_cmd_destroy {
132 	__le32 dpsw_id;
133 };
134 
135 #define DPSW_ENABLE_SHIFT 0
136 #define DPSW_ENABLE_SIZE  1
137 
138 struct dpsw_rsp_is_enabled {
139 	/* from LSB: enable:1 */
140 	u8 enabled;
141 };
142 
143 struct dpsw_cmd_set_irq_enable {
144 	u8 enable_state;
145 	u8 pad[3];
146 	u8 irq_index;
147 };
148 
149 struct dpsw_cmd_get_irq_enable {
150 	__le32 pad;
151 	u8 irq_index;
152 };
153 
154 struct dpsw_rsp_get_irq_enable {
155 	u8 enable_state;
156 };
157 
158 struct dpsw_cmd_set_irq_mask {
159 	__le32 mask;
160 	u8 irq_index;
161 };
162 
163 struct dpsw_cmd_get_irq_mask {
164 	__le32 pad;
165 	u8 irq_index;
166 };
167 
168 struct dpsw_rsp_get_irq_mask {
169 	__le32 mask;
170 };
171 
172 struct dpsw_cmd_get_irq_status {
173 	__le32 status;
174 	u8 irq_index;
175 };
176 
177 struct dpsw_rsp_get_irq_status {
178 	__le32 status;
179 };
180 
181 struct dpsw_cmd_clear_irq_status {
182 	__le32 status;
183 	u8 irq_index;
184 };
185 
186 #define DPSW_COMPONENT_TYPE_SHIFT	0
187 #define DPSW_COMPONENT_TYPE_SIZE	4
188 
189 #define DPSW_FLOODING_CFG_SHIFT		0
190 #define DPSW_FLOODING_CFG_SIZE		4
191 
192 #define DPSW_BROADCAST_CFG_SHIFT	4
193 #define DPSW_BROADCAST_CFG_SIZE		4
194 
195 struct dpsw_rsp_get_attr {
196 	/* cmd word 0 */
197 	__le16 num_ifs;
198 	u8 max_fdbs;
199 	u8 num_fdbs;
200 	__le16 max_vlans;
201 	__le16 num_vlans;
202 	/* cmd word 1 */
203 	__le16 max_fdb_entries;
204 	__le16 fdb_aging_time;
205 	__le32 dpsw_id;
206 	/* cmd word 2 */
207 	__le16 mem_size;
208 	__le16 max_fdb_mc_groups;
209 	u8 max_meters_per_if;
210 	/* from LSB only the first 4 bits */
211 	u8 component_type;
212 	/* [0:3] - flooding configuration
213 	 * [4:7] - broadcast configuration
214 	 */
215 	u8 repl_cfg;
216 	u8 pad;
217 	/* cmd word 3 */
218 	__le64 options;
219 };
220 
221 #define DPSW_VLAN_ID_SHIFT	0
222 #define DPSW_VLAN_ID_SIZE	12
223 #define DPSW_DEI_SHIFT		12
224 #define DPSW_DEI_SIZE		1
225 #define DPSW_PCP_SHIFT		13
226 #define DPSW_PCP_SIZE		3
227 
228 struct dpsw_cmd_if_set_tci {
229 	__le16 if_id;
230 	/* from LSB: VLAN_ID:12 DEI:1 PCP:3 */
231 	__le16 conf;
232 };
233 
234 struct dpsw_cmd_if_get_tci {
235 	__le16 if_id;
236 };
237 
238 struct dpsw_rsp_if_get_tci {
239 	__le16 pad;
240 	__le16 vlan_id;
241 	u8 dei;
242 	u8 pcp;
243 };
244 
245 #define DPSW_STATE_SHIFT	0
246 #define DPSW_STATE_SIZE		4
247 
248 struct dpsw_cmd_if_set_stp {
249 	__le16 if_id;
250 	__le16 vlan_id;
251 	/* only the first LSB 4 bits */
252 	u8 state;
253 };
254 
255 #define DPSW_COUNTER_TYPE_SHIFT		0
256 #define DPSW_COUNTER_TYPE_SIZE		5
257 
258 struct dpsw_cmd_if_get_counter {
259 	__le16 if_id;
260 	/* from LSB: type:5 */
261 	u8 type;
262 };
263 
264 struct dpsw_rsp_if_get_counter {
265 	__le64 pad;
266 	__le64 counter;
267 };
268 
269 struct dpsw_cmd_if {
270 	__le16 if_id;
271 };
272 
273 #define DPSW_ADMIT_UNTAGGED_SHIFT	0
274 #define DPSW_ADMIT_UNTAGGED_SIZE	4
275 #define DPSW_ENABLED_SHIFT		5
276 #define DPSW_ENABLED_SIZE		1
277 #define DPSW_ACCEPT_ALL_VLAN_SHIFT	6
278 #define DPSW_ACCEPT_ALL_VLAN_SIZE	1
279 
280 struct dpsw_rsp_if_get_attr {
281 	/* cmd word 0 */
282 	/* from LSB: admit_untagged:4 enabled:1 accept_all_vlan:1 */
283 	u8 conf;
284 	u8 pad1;
285 	u8 num_tcs;
286 	u8 pad2;
287 	__le16 qdid;
288 	/* cmd word 1 */
289 	__le32 options;
290 	__le32 pad3;
291 	/* cmd word 2 */
292 	__le32 rate;
293 };
294 
295 struct dpsw_cmd_if_set_max_frame_length {
296 	__le16 if_id;
297 	__le16 frame_length;
298 };
299 
300 struct dpsw_cmd_if_set_link_cfg {
301 	/* cmd word 0 */
302 	__le16 if_id;
303 	u8 pad[6];
304 	/* cmd word 1 */
305 	__le32 rate;
306 	__le32 pad1;
307 	/* cmd word 2 */
308 	__le64 options;
309 };
310 
311 struct dpsw_cmd_if_get_link_state {
312 	__le16 if_id;
313 };
314 
315 #define DPSW_UP_SHIFT	0
316 #define DPSW_UP_SIZE	1
317 
318 struct dpsw_rsp_if_get_link_state {
319 	/* cmd word 0 */
320 	__le32 pad0;
321 	u8 up;
322 	u8 pad1[3];
323 	/* cmd word 1 */
324 	__le32 rate;
325 	__le32 pad2;
326 	/* cmd word 2 */
327 	__le64 options;
328 };
329 
330 struct dpsw_vlan_add {
331 	__le16 fdb_id;
332 	__le16 vlan_id;
333 };
334 
335 struct dpsw_cmd_vlan_add_if {
336 	/* cmd word 0 */
337 	__le16 options;
338 	__le16 vlan_id;
339 	__le16 fdb_id;
340 	__le16 pad0;
341 	/* cmd word 1-4 */
342 	__le64 if_id;
343 };
344 
345 struct dpsw_cmd_vlan_manage_if {
346 	/* cmd word 0 */
347 	__le16 pad0;
348 	__le16 vlan_id;
349 	__le32 pad1;
350 	/* cmd word 1-4 */
351 	__le64 if_id;
352 };
353 
354 struct dpsw_cmd_vlan_remove {
355 	__le16 pad;
356 	__le16 vlan_id;
357 };
358 
359 struct dpsw_cmd_fdb_add {
360 	__le32 pad;
361 	__le16 fdb_ageing_time;
362 	__le16 num_fdb_entries;
363 };
364 
365 struct dpsw_rsp_fdb_add {
366 	__le16 fdb_id;
367 };
368 
369 struct dpsw_cmd_fdb_remove {
370 	__le16 fdb_id;
371 };
372 
373 #define DPSW_ENTRY_TYPE_SHIFT	0
374 #define DPSW_ENTRY_TYPE_SIZE	4
375 
376 struct dpsw_cmd_fdb_unicast_op {
377 	/* cmd word 0 */
378 	__le16 fdb_id;
379 	u8 mac_addr[6];
380 	/* cmd word 1 */
381 	__le16 if_egress;
382 	/* only the first 4 bits from LSB */
383 	u8 type;
384 };
385 
386 struct dpsw_cmd_fdb_multicast_op {
387 	/* cmd word 0 */
388 	__le16 fdb_id;
389 	__le16 num_ifs;
390 	/* only the first 4 bits from LSB */
391 	u8 type;
392 	u8 pad[3];
393 	/* cmd word 1 */
394 	u8 mac_addr[6];
395 	__le16 pad2;
396 	/* cmd word 2-5 */
397 	__le64 if_id;
398 };
399 
400 struct dpsw_cmd_fdb_dump {
401 	__le16 fdb_id;
402 	__le16 pad0;
403 	__le32 pad1;
404 	__le64 iova_addr;
405 	__le32 iova_size;
406 };
407 
408 struct dpsw_rsp_fdb_dump {
409 	__le16 num_entries;
410 };
411 
412 struct dpsw_rsp_ctrl_if_get_attr {
413 	__le64 pad;
414 	__le32 rx_fqid;
415 	__le32 rx_err_fqid;
416 	__le32 tx_err_conf_fqid;
417 };
418 
419 #define DPSW_BACKUP_POOL(val, order)	(((val) & 0x1) << (order))
420 struct dpsw_cmd_ctrl_if_set_pools {
421 	u8 num_dpbp;
422 	u8 backup_pool_mask;
423 	__le16 pad;
424 	__le32 dpbp_id[DPSW_MAX_DPBP];
425 	__le16 buffer_size[DPSW_MAX_DPBP];
426 };
427 
428 #define DPSW_DEST_TYPE_SHIFT	0
429 #define DPSW_DEST_TYPE_SIZE	4
430 
431 struct dpsw_cmd_ctrl_if_set_queue {
432 	__le32 dest_id;
433 	u8 dest_priority;
434 	u8 pad;
435 	/* from LSB: dest_type:4 */
436 	u8 dest_type;
437 	u8 qtype;
438 	__le64 user_ctx;
439 	__le32 options;
440 };
441 
442 struct dpsw_rsp_get_api_version {
443 	__le16 version_major;
444 	__le16 version_minor;
445 };
446 
447 struct dpsw_rsp_if_get_mac_addr {
448 	__le16 pad;
449 	u8 mac_addr[6];
450 };
451 
452 struct dpsw_cmd_set_egress_flood {
453 	__le16 fdb_id;
454 	u8 flood_type;
455 	u8 pad[5];
456 	__le64 if_id;
457 };
458 
459 #define DPSW_LEARNING_MODE_SHIFT	0
460 #define DPSW_LEARNING_MODE_SIZE		4
461 
462 struct dpsw_cmd_if_set_learning_mode {
463 	__le16 if_id;
464 	/* only the first 4 bits from LSB */
465 	u8 mode;
466 };
467 
468 struct dpsw_cmd_acl_add {
469 	__le16 pad;
470 	__le16 max_entries;
471 };
472 
473 struct dpsw_rsp_acl_add {
474 	__le16 acl_id;
475 };
476 
477 struct dpsw_cmd_acl_remove {
478 	__le16 acl_id;
479 };
480 
481 struct dpsw_cmd_acl_if {
482 	__le16 acl_id;
483 	__le16 num_ifs;
484 	__le32 pad;
485 	__le64 if_id;
486 };
487 
488 struct dpsw_prep_acl_entry {
489 	u8 match_l2_dest_mac[6];
490 	__le16 match_l2_tpid;
491 
492 	u8 match_l2_source_mac[6];
493 	__le16 match_l2_vlan_id;
494 
495 	__le32 match_l3_dest_ip;
496 	__le32 match_l3_source_ip;
497 
498 	__le16 match_l4_dest_port;
499 	__le16 match_l4_source_port;
500 	__le16 match_l2_ether_type;
501 	u8 match_l2_pcp_dei;
502 	u8 match_l3_dscp;
503 
504 	u8 mask_l2_dest_mac[6];
505 	__le16 mask_l2_tpid;
506 
507 	u8 mask_l2_source_mac[6];
508 	__le16 mask_l2_vlan_id;
509 
510 	__le32 mask_l3_dest_ip;
511 	__le32 mask_l3_source_ip;
512 
513 	__le16 mask_l4_dest_port;
514 	__le16 mask_l4_source_port;
515 	__le16 mask_l2_ether_type;
516 	u8 mask_l2_pcp_dei;
517 	u8 mask_l3_dscp;
518 
519 	u8 match_l3_protocol;
520 	u8 mask_l3_protocol;
521 };
522 
523 #define DPSW_RESULT_ACTION_SHIFT	0
524 #define DPSW_RESULT_ACTION_SIZE		4
525 
526 struct dpsw_cmd_acl_entry {
527 	__le16 acl_id;
528 	__le16 result_if_id;
529 	__le32 precedence;
530 	/* from LSB only the first 4 bits */
531 	u8 result_action;
532 	u8 pad[7];
533 	__le64 pad2[4];
534 	__le64 key_iova;
535 };
536 #pragma pack(pop)
537 #endif /* __FSL_DPSW_CMD_H */
538