1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * DPAA2 Ethernet Switch declarations 4 * 5 * Copyright 2014-2016 Freescale Semiconductor Inc. 6 * Copyright 2017-2021 NXP 7 * 8 */ 9 10 #ifndef __ETHSW_H 11 #define __ETHSW_H 12 13 #include <linux/netdevice.h> 14 #include <linux/etherdevice.h> 15 #include <linux/rtnetlink.h> 16 #include <linux/if_vlan.h> 17 #include <uapi/linux/if_bridge.h> 18 #include <net/switchdev.h> 19 #include <linux/if_bridge.h> 20 #include <linux/fsl/mc.h> 21 #include <soc/fsl/dpaa2-io.h> 22 23 #include "dpsw.h" 24 25 /* Number of IRQs supported */ 26 #define DPSW_IRQ_NUM 2 27 28 /* Port is member of VLAN */ 29 #define ETHSW_VLAN_MEMBER 1 30 /* VLAN to be treated as untagged on egress */ 31 #define ETHSW_VLAN_UNTAGGED 2 32 /* Untagged frames will be assigned to this VLAN */ 33 #define ETHSW_VLAN_PVID 4 34 /* VLAN configured on the switch */ 35 #define ETHSW_VLAN_GLOBAL 8 36 37 /* Maximum Frame Length supported by HW (currently 10k) */ 38 #define DPAA2_MFL (10 * 1024) 39 #define ETHSW_MAX_FRAME_LENGTH (DPAA2_MFL - VLAN_ETH_HLEN - ETH_FCS_LEN) 40 #define ETHSW_L2_MAX_FRM(mtu) ((mtu) + VLAN_ETH_HLEN + ETH_FCS_LEN) 41 42 #define ETHSW_FEATURE_MAC_ADDR BIT(0) 43 44 /* Number of receive queues (one RX and one TX_CONF) */ 45 #define DPAA2_SWITCH_RX_NUM_FQS 2 46 47 /* Hardware requires alignment for ingress/egress buffer addresses */ 48 #define DPAA2_SWITCH_RX_BUF_RAW_SIZE PAGE_SIZE 49 #define DPAA2_SWITCH_RX_BUF_TAILROOM \ 50 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) 51 #define DPAA2_SWITCH_RX_BUF_SIZE \ 52 (DPAA2_SWITCH_RX_BUF_RAW_SIZE - DPAA2_SWITCH_RX_BUF_TAILROOM) 53 54 #define DPAA2_SWITCH_STORE_SIZE 16 55 56 /* Buffer management */ 57 #define BUFS_PER_CMD 7 58 #define DPAA2_ETHSW_NUM_BUFS (1024 * BUFS_PER_CMD) 59 #define DPAA2_ETHSW_REFILL_THRESH (DPAA2_ETHSW_NUM_BUFS * 5 / 6) 60 61 /* Number of times to retry DPIO portal operations while waiting 62 * for portal to finish executing current command and become 63 * available. We want to avoid being stuck in a while loop in case 64 * hardware becomes unresponsive, but not give up too easily if 65 * the portal really is busy for valid reasons 66 */ 67 #define DPAA2_SWITCH_SWP_BUSY_RETRIES 1000 68 69 /* Hardware annotation buffer size */ 70 #define DPAA2_SWITCH_HWA_SIZE 64 71 /* Software annotation buffer size */ 72 #define DPAA2_SWITCH_SWA_SIZE 64 73 74 #define DPAA2_SWITCH_TX_BUF_ALIGN 64 75 76 #define DPAA2_SWITCH_TX_DATA_OFFSET \ 77 (DPAA2_SWITCH_HWA_SIZE + DPAA2_SWITCH_SWA_SIZE) 78 79 #define DPAA2_SWITCH_NEEDED_HEADROOM \ 80 (DPAA2_SWITCH_TX_DATA_OFFSET + DPAA2_SWITCH_TX_BUF_ALIGN) 81 82 extern const struct ethtool_ops dpaa2_switch_port_ethtool_ops; 83 84 struct ethsw_core; 85 86 struct dpaa2_switch_fq { 87 struct ethsw_core *ethsw; 88 enum dpsw_queue_type type; 89 struct dpaa2_io_store *store; 90 struct dpaa2_io_notification_ctx nctx; 91 struct napi_struct napi; 92 u32 fqid; 93 }; 94 95 struct dpaa2_switch_fdb { 96 struct net_device *bridge_dev; 97 u16 fdb_id; 98 bool in_use; 99 }; 100 101 /* Per port private data */ 102 struct ethsw_port_priv { 103 struct net_device *netdev; 104 u16 idx; 105 struct ethsw_core *ethsw_data; 106 u8 link_state; 107 u8 stp_state; 108 109 u8 vlans[VLAN_VID_MASK + 1]; 110 u16 pvid; 111 u16 tx_qdid; 112 113 struct dpaa2_switch_fdb *fdb; 114 bool bcast_flood; 115 bool ucast_flood; 116 }; 117 118 /* Switch data */ 119 struct ethsw_core { 120 struct device *dev; 121 struct fsl_mc_io *mc_io; 122 u16 dpsw_handle; 123 struct dpsw_attr sw_attr; 124 u16 major, minor; 125 unsigned long features; 126 int dev_id; 127 struct ethsw_port_priv **ports; 128 struct iommu_domain *iommu_domain; 129 130 u8 vlans[VLAN_VID_MASK + 1]; 131 132 struct workqueue_struct *workqueue; 133 134 struct dpaa2_switch_fq fq[DPAA2_SWITCH_RX_NUM_FQS]; 135 struct fsl_mc_device *dpbp_dev; 136 int buf_count; 137 u16 bpid; 138 int napi_users; 139 140 struct dpaa2_switch_fdb *fdbs; 141 }; 142 143 static inline bool dpaa2_switch_supports_cpu_traffic(struct ethsw_core *ethsw) 144 { 145 if (ethsw->sw_attr.options & DPSW_OPT_CTRL_IF_DIS) { 146 dev_err(ethsw->dev, "Control Interface is disabled, cannot probe\n"); 147 return false; 148 } 149 150 if (ethsw->sw_attr.flooding_cfg != DPSW_FLOODING_PER_FDB) { 151 dev_err(ethsw->dev, "Flooding domain is not per FDB, cannot probe\n"); 152 return false; 153 } 154 155 if (ethsw->sw_attr.broadcast_cfg != DPSW_BROADCAST_PER_FDB) { 156 dev_err(ethsw->dev, "Broadcast domain is not per FDB, cannot probe\n"); 157 return false; 158 } 159 160 if (ethsw->sw_attr.max_fdbs < ethsw->sw_attr.num_ifs) { 161 dev_err(ethsw->dev, "The number of FDBs is lower than the number of ports, cannot probe\n"); 162 return false; 163 } 164 165 return true; 166 } 167 168 bool dpaa2_switch_port_dev_check(const struct net_device *netdev); 169 170 int dpaa2_switch_port_vlans_add(struct net_device *netdev, 171 const struct switchdev_obj_port_vlan *vlan); 172 173 int dpaa2_switch_port_vlans_del(struct net_device *netdev, 174 const struct switchdev_obj_port_vlan *vlan); 175 176 typedef int dpaa2_switch_fdb_cb_t(struct ethsw_port_priv *port_priv, 177 struct fdb_dump_entry *fdb_entry, 178 void *data); 179 #endif /* __ETHSW_H */ 180