1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ 2 /* Copyright 2014-2016 Freescale Semiconductor Inc. 3 * Copyright 2016-2022 NXP 4 */ 5 6 #ifndef __DPAA2_ETH_H 7 #define __DPAA2_ETH_H 8 9 #include <linux/dcbnl.h> 10 #include <linux/netdevice.h> 11 #include <linux/if_vlan.h> 12 #include <linux/fsl/mc.h> 13 #include <linux/net_tstamp.h> 14 #include <net/devlink.h> 15 16 #include <soc/fsl/dpaa2-io.h> 17 #include <soc/fsl/dpaa2-fd.h> 18 #include "dpni.h" 19 #include "dpni-cmd.h" 20 21 #include "dpaa2-eth-trace.h" 22 #include "dpaa2-eth-debugfs.h" 23 #include "dpaa2-mac.h" 24 25 #define DPAA2_WRIOP_VERSION(x, y, z) ((x) << 10 | (y) << 5 | (z) << 0) 26 27 #define DPAA2_ETH_STORE_SIZE 16 28 29 /* Maximum number of scatter-gather entries in an ingress frame, 30 * considering the maximum receive frame size is 64K 31 */ 32 #define DPAA2_ETH_MAX_SG_ENTRIES ((64 * 1024) / DPAA2_ETH_RX_BUF_SIZE) 33 34 /* Maximum acceptable MTU value. It is in direct relation with the hardware 35 * enforced Max Frame Length (currently 10k). 36 */ 37 #define DPAA2_ETH_MFL (10 * 1024) 38 #define DPAA2_ETH_MAX_MTU (DPAA2_ETH_MFL - VLAN_ETH_HLEN) 39 /* Convert L3 MTU to L2 MFL */ 40 #define DPAA2_ETH_L2_MAX_FRM(mtu) ((mtu) + VLAN_ETH_HLEN) 41 42 /* Set the taildrop threshold (in bytes) to allow the enqueue of a large 43 * enough number of jumbo frames in the Rx queues (length of the current 44 * frame is not taken into account when making the taildrop decision) 45 */ 46 #define DPAA2_ETH_FQ_TAILDROP_THRESH (1024 * 1024) 47 48 /* Maximum burst size value for Tx shaping */ 49 #define DPAA2_ETH_MAX_BURST_SIZE 0xF7FF 50 51 /* Maximum number of Tx confirmation frames to be processed 52 * in a single NAPI call 53 */ 54 #define DPAA2_ETH_TXCONF_PER_NAPI 256 55 56 /* Maximum number of Tx frames to be processed in a single NAPI 57 * call when AF_XDP is running. Bind it to DPAA2_ETH_TXCONF_PER_NAPI 58 * to maximize the throughput. 59 */ 60 #define DPAA2_ETH_TX_ZC_PER_NAPI DPAA2_ETH_TXCONF_PER_NAPI 61 62 /* Buffer qouta per channel. We want to keep in check number of ingress frames 63 * in flight: for small sized frames, congestion group taildrop may kick in 64 * first; for large sizes, Rx FQ taildrop threshold will ensure only a 65 * reasonable number of frames will be pending at any given time. 66 * Ingress frame drop due to buffer pool depletion should be a corner case only 67 */ 68 #define DPAA2_ETH_NUM_BUFS 1280 69 #define DPAA2_ETH_REFILL_THRESH \ 70 (DPAA2_ETH_NUM_BUFS - DPAA2_ETH_BUFS_PER_CMD) 71 72 /* Congestion group taildrop threshold: number of frames allowed to accumulate 73 * at any moment in a group of Rx queues belonging to the same traffic class. 74 * Choose value such that we don't risk depleting the buffer pool before the 75 * taildrop kicks in 76 */ 77 #define DPAA2_ETH_CG_TAILDROP_THRESH(priv) \ 78 (1024 * dpaa2_eth_queue_count(priv) / dpaa2_eth_tc_count(priv)) 79 80 /* Congestion group notification threshold: when this many frames accumulate 81 * on the Rx queues belonging to the same TC, the MAC is instructed to send 82 * PFC frames for that TC. 83 * When number of pending frames drops below exit threshold transmission of 84 * PFC frames is stopped. 85 */ 86 #define DPAA2_ETH_CN_THRESH_ENTRY(priv) \ 87 (DPAA2_ETH_CG_TAILDROP_THRESH(priv) / 2) 88 #define DPAA2_ETH_CN_THRESH_EXIT(priv) \ 89 (DPAA2_ETH_CN_THRESH_ENTRY(priv) * 3 / 4) 90 91 /* Maximum number of buffers that can be acquired/released through a single 92 * QBMan command 93 */ 94 #define DPAA2_ETH_BUFS_PER_CMD 7 95 96 /* Hardware requires alignment for ingress/egress buffer addresses */ 97 #define DPAA2_ETH_TX_BUF_ALIGN 64 98 99 #define DPAA2_ETH_RX_BUF_RAW_SIZE PAGE_SIZE 100 #define DPAA2_ETH_RX_BUF_TAILROOM \ 101 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) 102 #define DPAA2_ETH_RX_BUF_SIZE \ 103 (DPAA2_ETH_RX_BUF_RAW_SIZE - DPAA2_ETH_RX_BUF_TAILROOM) 104 105 /* Hardware annotation area in RX/TX buffers */ 106 #define DPAA2_ETH_RX_HWA_SIZE 64 107 #define DPAA2_ETH_TX_HWA_SIZE 128 108 109 /* PTP nominal frequency 1GHz */ 110 #define DPAA2_PTP_CLK_PERIOD_NS 1 111 112 /* Due to a limitation in WRIOP 1.0.0, the RX buffer data must be aligned 113 * to 256B. For newer revisions, the requirement is only for 64B alignment 114 */ 115 #define DPAA2_ETH_RX_BUF_ALIGN_REV1 256 116 #define DPAA2_ETH_RX_BUF_ALIGN 64 117 118 /* The firmware allows assigning multiple buffer pools to a single DPNI - 119 * maximum 8 DPBP objects. By default, only the first DPBP (idx 0) is used for 120 * all queues. Thus, when enabling AF_XDP we must accommodate up to 9 DPBPs 121 * object: the default and 8 other distinct buffer pools, one for each queue. 122 */ 123 #define DPAA2_ETH_DEFAULT_BP_IDX 0 124 #define DPAA2_ETH_MAX_BPS 9 125 126 /* We are accommodating a skb backpointer and some S/G info 127 * in the frame's software annotation. The hardware 128 * options are either 0 or 64, so we choose the latter. 129 */ 130 #define DPAA2_ETH_SWA_SIZE 64 131 132 /* We store different information in the software annotation area of a Tx frame 133 * based on what type of frame it is 134 */ 135 enum dpaa2_eth_swa_type { 136 DPAA2_ETH_SWA_SINGLE, 137 DPAA2_ETH_SWA_SG, 138 DPAA2_ETH_SWA_XDP, 139 DPAA2_ETH_SWA_XSK, 140 DPAA2_ETH_SWA_SW_TSO, 141 }; 142 143 /* Must keep this struct smaller than DPAA2_ETH_SWA_SIZE */ 144 struct dpaa2_eth_swa { 145 enum dpaa2_eth_swa_type type; 146 union { 147 struct { 148 struct sk_buff *skb; 149 int sgt_size; 150 } single; 151 struct { 152 struct sk_buff *skb; 153 struct scatterlist *scl; 154 int num_sg; 155 int sgt_size; 156 } sg; 157 struct { 158 int dma_size; 159 struct xdp_frame *xdpf; 160 } xdp; 161 struct { 162 struct xdp_buff *xdp_buff; 163 int sgt_size; 164 } xsk; 165 struct { 166 struct sk_buff *skb; 167 int num_sg; 168 int sgt_size; 169 int is_last_fd; 170 } tso; 171 }; 172 }; 173 174 /* Annotation valid bits in FD FRC */ 175 #define DPAA2_FD_FRC_FASV 0x8000 176 #define DPAA2_FD_FRC_FAEADV 0x4000 177 #define DPAA2_FD_FRC_FAPRV 0x2000 178 #define DPAA2_FD_FRC_FAIADV 0x1000 179 #define DPAA2_FD_FRC_FASWOV 0x0800 180 #define DPAA2_FD_FRC_FAICFDV 0x0400 181 182 /* Error bits in FD CTRL */ 183 #define DPAA2_FD_RX_ERR_MASK (FD_CTRL_SBE | FD_CTRL_FAERR) 184 #define DPAA2_FD_TX_ERR_MASK (FD_CTRL_UFD | \ 185 FD_CTRL_SBE | \ 186 FD_CTRL_FSE | \ 187 FD_CTRL_FAERR) 188 189 /* Annotation bits in FD CTRL */ 190 #define DPAA2_FD_CTRL_ASAL 0x00020000 /* ASAL = 128B */ 191 192 /* Frame annotation status */ 193 struct dpaa2_fas { 194 u8 reserved; 195 u8 ppid; 196 __le16 ifpid; 197 __le32 status; 198 }; 199 200 /* Frame annotation status word is located in the first 8 bytes 201 * of the buffer's hardware annoatation area 202 */ 203 #define DPAA2_FAS_OFFSET 0 204 #define DPAA2_FAS_SIZE (sizeof(struct dpaa2_fas)) 205 206 /* Timestamp is located in the next 8 bytes of the buffer's 207 * hardware annotation area 208 */ 209 #define DPAA2_TS_OFFSET 0x8 210 211 /* Frame annotation parse results */ 212 struct dpaa2_fapr { 213 /* 64-bit word 1 */ 214 __le32 faf_lo; 215 __le16 faf_ext; 216 __le16 nxt_hdr; 217 /* 64-bit word 2 */ 218 __le64 faf_hi; 219 /* 64-bit word 3 */ 220 u8 last_ethertype_offset; 221 u8 vlan_tci_offset_n; 222 u8 vlan_tci_offset_1; 223 u8 llc_snap_offset; 224 u8 eth_offset; 225 u8 ip1_pid_offset; 226 u8 shim_offset_2; 227 u8 shim_offset_1; 228 /* 64-bit word 4 */ 229 u8 l5_offset; 230 u8 l4_offset; 231 u8 gre_offset; 232 u8 l3_offset_n; 233 u8 l3_offset_1; 234 u8 mpls_offset_n; 235 u8 mpls_offset_1; 236 u8 pppoe_offset; 237 /* 64-bit word 5 */ 238 __le16 running_sum; 239 __le16 gross_running_sum; 240 u8 ipv6_frag_offset; 241 u8 nxt_hdr_offset; 242 u8 routing_hdr_offset_2; 243 u8 routing_hdr_offset_1; 244 /* 64-bit word 6 */ 245 u8 reserved[5]; /* Soft-parsing context */ 246 u8 ip_proto_offset_n; 247 u8 nxt_hdr_frag_offset; 248 u8 parse_error_code; 249 }; 250 251 #define DPAA2_FAPR_OFFSET 0x10 252 #define DPAA2_FAPR_SIZE sizeof((struct dpaa2_fapr)) 253 254 /* Frame annotation egress action descriptor */ 255 #define DPAA2_FAEAD_OFFSET 0x58 256 257 struct dpaa2_faead { 258 __le32 conf_fqid; 259 __le32 ctrl; 260 }; 261 262 #define DPAA2_FAEAD_A2V 0x20000000 263 #define DPAA2_FAEAD_A4V 0x08000000 264 #define DPAA2_FAEAD_UPDV 0x00001000 265 #define DPAA2_FAEAD_EBDDV 0x00002000 266 #define DPAA2_FAEAD_UPD 0x00000010 267 268 struct ptp_tstamp { 269 u16 sec_msb; 270 u32 sec_lsb; 271 u32 nsec; 272 }; 273 274 static inline void ns_to_ptp_tstamp(struct ptp_tstamp *tstamp, u64 ns) 275 { 276 u64 sec, nsec; 277 278 sec = ns; 279 nsec = do_div(sec, 1000000000); 280 281 tstamp->sec_lsb = sec & 0xFFFFFFFF; 282 tstamp->sec_msb = (sec >> 32) & 0xFFFF; 283 tstamp->nsec = nsec; 284 } 285 286 /* Accessors for the hardware annotation fields that we use */ 287 static inline void *dpaa2_get_hwa(void *buf_addr, bool swa) 288 { 289 return buf_addr + (swa ? DPAA2_ETH_SWA_SIZE : 0); 290 } 291 292 static inline struct dpaa2_fas *dpaa2_get_fas(void *buf_addr, bool swa) 293 { 294 return dpaa2_get_hwa(buf_addr, swa) + DPAA2_FAS_OFFSET; 295 } 296 297 static inline __le64 *dpaa2_get_ts(void *buf_addr, bool swa) 298 { 299 return dpaa2_get_hwa(buf_addr, swa) + DPAA2_TS_OFFSET; 300 } 301 302 static inline struct dpaa2_fapr *dpaa2_get_fapr(void *buf_addr, bool swa) 303 { 304 return dpaa2_get_hwa(buf_addr, swa) + DPAA2_FAPR_OFFSET; 305 } 306 307 static inline struct dpaa2_faead *dpaa2_get_faead(void *buf_addr, bool swa) 308 { 309 return dpaa2_get_hwa(buf_addr, swa) + DPAA2_FAEAD_OFFSET; 310 } 311 312 /* Error and status bits in the frame annotation status word */ 313 /* Debug frame, otherwise supposed to be discarded */ 314 #define DPAA2_FAS_DISC 0x80000000 315 /* MACSEC frame */ 316 #define DPAA2_FAS_MS 0x40000000 317 #define DPAA2_FAS_PTP 0x08000000 318 /* Ethernet multicast frame */ 319 #define DPAA2_FAS_MC 0x04000000 320 /* Ethernet broadcast frame */ 321 #define DPAA2_FAS_BC 0x02000000 322 #define DPAA2_FAS_KSE 0x00040000 323 #define DPAA2_FAS_EOFHE 0x00020000 324 #define DPAA2_FAS_MNLE 0x00010000 325 #define DPAA2_FAS_TIDE 0x00008000 326 #define DPAA2_FAS_PIEE 0x00004000 327 /* Frame length error */ 328 #define DPAA2_FAS_FLE 0x00002000 329 /* Frame physical error */ 330 #define DPAA2_FAS_FPE 0x00001000 331 #define DPAA2_FAS_PTE 0x00000080 332 #define DPAA2_FAS_ISP 0x00000040 333 #define DPAA2_FAS_PHE 0x00000020 334 #define DPAA2_FAS_BLE 0x00000010 335 /* L3 csum validation performed */ 336 #define DPAA2_FAS_L3CV 0x00000008 337 /* L3 csum error */ 338 #define DPAA2_FAS_L3CE 0x00000004 339 /* L4 csum validation performed */ 340 #define DPAA2_FAS_L4CV 0x00000002 341 /* L4 csum error */ 342 #define DPAA2_FAS_L4CE 0x00000001 343 /* Possible errors on the ingress path */ 344 #define DPAA2_FAS_RX_ERR_MASK (DPAA2_FAS_KSE | \ 345 DPAA2_FAS_EOFHE | \ 346 DPAA2_FAS_MNLE | \ 347 DPAA2_FAS_TIDE | \ 348 DPAA2_FAS_PIEE | \ 349 DPAA2_FAS_FLE | \ 350 DPAA2_FAS_FPE | \ 351 DPAA2_FAS_PTE | \ 352 DPAA2_FAS_ISP | \ 353 DPAA2_FAS_PHE | \ 354 DPAA2_FAS_BLE | \ 355 DPAA2_FAS_L3CE | \ 356 DPAA2_FAS_L4CE) 357 358 /* Time in milliseconds between link state updates */ 359 #define DPAA2_ETH_LINK_STATE_REFRESH 1000 360 361 /* Number of times to retry a frame enqueue before giving up. 362 * Value determined empirically, in order to minimize the number 363 * of frames dropped on Tx 364 */ 365 #define DPAA2_ETH_ENQUEUE_RETRIES 10 366 367 /* Number of times to retry DPIO portal operations while waiting 368 * for portal to finish executing current command and become 369 * available. We want to avoid being stuck in a while loop in case 370 * hardware becomes unresponsive, but not give up too easily if 371 * the portal really is busy for valid reasons 372 */ 373 #define DPAA2_ETH_SWP_BUSY_RETRIES 1000 374 375 /* Driver statistics, other than those in struct rtnl_link_stats64. 376 * These are usually collected per-CPU and aggregated by ethtool. 377 */ 378 struct dpaa2_eth_drv_stats { 379 __u64 tx_conf_frames; 380 __u64 tx_conf_bytes; 381 __u64 tx_sg_frames; 382 __u64 tx_sg_bytes; 383 __u64 tx_tso_frames; 384 __u64 tx_tso_bytes; 385 __u64 rx_sg_frames; 386 __u64 rx_sg_bytes; 387 /* Linear skbs sent as a S/G FD due to insufficient headroom */ 388 __u64 tx_converted_sg_frames; 389 __u64 tx_converted_sg_bytes; 390 /* Enqueues retried due to portal busy */ 391 __u64 tx_portal_busy; 392 }; 393 394 /* Per-FQ statistics */ 395 struct dpaa2_eth_fq_stats { 396 /* Number of frames received on this queue */ 397 __u64 frames; 398 }; 399 400 /* Per-channel statistics */ 401 struct dpaa2_eth_ch_stats { 402 /* Volatile dequeues retried due to portal busy */ 403 __u64 dequeue_portal_busy; 404 /* Pull errors */ 405 __u64 pull_err; 406 /* Number of CDANs; useful to estimate avg NAPI len */ 407 __u64 cdan; 408 /* XDP counters */ 409 __u64 xdp_drop; 410 __u64 xdp_tx; 411 __u64 xdp_tx_err; 412 __u64 xdp_redirect; 413 /* Must be last, does not show up in ethtool stats */ 414 __u64 frames; 415 __u64 frames_per_cdan; 416 __u64 bytes_per_cdan; 417 }; 418 419 #define DPAA2_ETH_CH_STATS 7 420 421 /* Maximum number of queues associated with a DPNI */ 422 #define DPAA2_ETH_MAX_TCS 8 423 #define DPAA2_ETH_MAX_RX_QUEUES_PER_TC 16 424 #define DPAA2_ETH_MAX_RX_QUEUES \ 425 (DPAA2_ETH_MAX_RX_QUEUES_PER_TC * DPAA2_ETH_MAX_TCS) 426 #define DPAA2_ETH_MAX_TX_QUEUES 16 427 #define DPAA2_ETH_MAX_RX_ERR_QUEUES 1 428 #define DPAA2_ETH_MAX_QUEUES (DPAA2_ETH_MAX_RX_QUEUES + \ 429 DPAA2_ETH_MAX_TX_QUEUES + \ 430 DPAA2_ETH_MAX_RX_ERR_QUEUES) 431 #define DPAA2_ETH_MAX_NETDEV_QUEUES \ 432 (DPAA2_ETH_MAX_TX_QUEUES * DPAA2_ETH_MAX_TCS) 433 434 #define DPAA2_ETH_MAX_DPCONS 16 435 436 enum dpaa2_eth_fq_type { 437 DPAA2_RX_FQ = 0, 438 DPAA2_TX_CONF_FQ, 439 DPAA2_RX_ERR_FQ 440 }; 441 442 struct dpaa2_eth_priv; 443 struct dpaa2_eth_channel; 444 struct dpaa2_eth_fq; 445 446 struct dpaa2_eth_xdp_fds { 447 struct dpaa2_fd fds[DEV_MAP_BULK_SIZE]; 448 ssize_t num; 449 }; 450 451 typedef void dpaa2_eth_consume_cb_t(struct dpaa2_eth_priv *priv, 452 struct dpaa2_eth_channel *ch, 453 const struct dpaa2_fd *fd, 454 struct dpaa2_eth_fq *fq); 455 456 struct dpaa2_eth_fq { 457 u32 fqid; 458 u32 tx_qdbin; 459 u32 tx_fqid[DPAA2_ETH_MAX_TCS]; 460 u16 flowid; 461 u8 tc; 462 int target_cpu; 463 u32 dq_frames; 464 u32 dq_bytes; 465 struct dpaa2_eth_channel *channel; 466 enum dpaa2_eth_fq_type type; 467 468 dpaa2_eth_consume_cb_t *consume; 469 struct dpaa2_eth_fq_stats stats; 470 471 struct dpaa2_eth_xdp_fds xdp_redirect_fds; 472 struct dpaa2_eth_xdp_fds xdp_tx_fds; 473 }; 474 475 struct dpaa2_eth_ch_xdp { 476 struct bpf_prog *prog; 477 unsigned int res; 478 }; 479 480 struct dpaa2_eth_bp { 481 struct fsl_mc_device *dev; 482 int bpid; 483 }; 484 485 struct dpaa2_eth_channel { 486 struct dpaa2_io_notification_ctx nctx; 487 struct fsl_mc_device *dpcon; 488 int dpcon_id; 489 int ch_id; 490 struct napi_struct napi; 491 struct dpaa2_io *dpio; 492 struct dpaa2_io_store *store; 493 struct dpaa2_eth_priv *priv; 494 int buf_count; 495 struct dpaa2_eth_ch_stats stats; 496 struct dpaa2_eth_ch_xdp xdp; 497 struct xdp_rxq_info xdp_rxq; 498 struct list_head *rx_list; 499 500 /* Buffers to be recycled back in the buffer pool */ 501 u64 recycled_bufs[DPAA2_ETH_BUFS_PER_CMD]; 502 int recycled_bufs_cnt; 503 504 bool xsk_zc; 505 int xsk_tx_pkts_sent; 506 struct xsk_buff_pool *xsk_pool; 507 struct dpaa2_eth_bp *bp; 508 }; 509 510 struct dpaa2_eth_dist_fields { 511 u64 rxnfc_field; 512 enum net_prot cls_prot; 513 int cls_field; 514 int size; 515 u64 id; 516 }; 517 518 struct dpaa2_eth_cls_rule { 519 struct ethtool_rx_flow_spec fs; 520 u8 in_use; 521 }; 522 523 #define DPAA2_ETH_SGT_CACHE_SIZE 256 524 struct dpaa2_eth_sgt_cache { 525 void *buf[DPAA2_ETH_SGT_CACHE_SIZE]; 526 u16 count; 527 }; 528 529 struct dpaa2_eth_trap_item { 530 void *trap_ctx; 531 }; 532 533 struct dpaa2_eth_trap_data { 534 struct dpaa2_eth_trap_item *trap_items_arr; 535 struct dpaa2_eth_priv *priv; 536 }; 537 538 #define DPAA2_ETH_SG_ENTRIES_MAX (PAGE_SIZE / sizeof(struct scatterlist)) 539 540 #define DPAA2_ETH_DEFAULT_COPYBREAK 512 541 542 #define DPAA2_ETH_ENQUEUE_MAX_FDS 256 543 struct dpaa2_eth_fds { 544 struct dpaa2_fd array[DPAA2_ETH_ENQUEUE_MAX_FDS]; 545 }; 546 547 /* Driver private data */ 548 struct dpaa2_eth_priv { 549 struct net_device *net_dev; 550 551 u8 num_fqs; 552 struct dpaa2_eth_fq fq[DPAA2_ETH_MAX_QUEUES]; 553 int (*enqueue)(struct dpaa2_eth_priv *priv, 554 struct dpaa2_eth_fq *fq, 555 struct dpaa2_fd *fd, u8 prio, 556 u32 num_frames, 557 int *frames_enqueued); 558 559 u8 num_channels; 560 struct dpaa2_eth_channel *channel[DPAA2_ETH_MAX_DPCONS]; 561 struct dpaa2_eth_sgt_cache __percpu *sgt_cache; 562 unsigned long features; 563 struct dpni_attr dpni_attrs; 564 u16 dpni_ver_major; 565 u16 dpni_ver_minor; 566 u16 tx_data_offset; 567 void __iomem *onestep_reg_base; 568 u8 ptp_correction_off; 569 void (*dpaa2_set_onestep_params_cb)(struct dpaa2_eth_priv *priv, 570 u32 offset, u8 udp); 571 u16 rx_buf_size; 572 struct iommu_domain *iommu_domain; 573 574 enum hwtstamp_tx_types tx_tstamp_type; /* Tx timestamping type */ 575 bool rx_tstamp; /* Rx timestamping enabled */ 576 577 /* Buffer pool management */ 578 struct dpaa2_eth_bp *bp[DPAA2_ETH_MAX_BPS]; 579 int num_bps; 580 581 u16 tx_qdid; 582 struct fsl_mc_io *mc_io; 583 /* Cores which have an affine DPIO/DPCON. 584 * This is the cpu set on which Rx and Tx conf frames are processed 585 */ 586 struct cpumask dpio_cpumask; 587 588 /* Standard statistics */ 589 struct rtnl_link_stats64 __percpu *percpu_stats; 590 /* Extra stats, in addition to the ones known by the kernel */ 591 struct dpaa2_eth_drv_stats __percpu *percpu_extras; 592 593 u16 mc_token; 594 u8 rx_fqtd_enabled; 595 u8 rx_cgtd_enabled; 596 597 struct dpni_link_state link_state; 598 bool do_link_poll; 599 struct task_struct *poll_thread; 600 601 /* enabled ethtool hashing bits */ 602 u64 rx_hash_fields; 603 u64 rx_cls_fields; 604 struct dpaa2_eth_cls_rule *cls_rules; 605 u8 rx_cls_enabled; 606 u8 vlan_cls_enabled; 607 u8 pfc_enabled; 608 #ifdef CONFIG_FSL_DPAA2_ETH_DCB 609 u8 dcbx_mode; 610 struct ieee_pfc pfc; 611 #endif 612 struct bpf_prog *xdp_prog; 613 #ifdef CONFIG_DEBUG_FS 614 struct dpaa2_debugfs dbg; 615 #endif 616 617 struct dpaa2_mac *mac; 618 /* Serializes changes to priv->mac */ 619 struct mutex mac_lock; 620 struct workqueue_struct *dpaa2_ptp_wq; 621 struct work_struct tx_onestep_tstamp; 622 struct sk_buff_head tx_skbs; 623 /* The one-step timestamping configuration on hardware 624 * registers could only be done when no one-step 625 * timestamping frames are in flight. So we use a mutex 626 * lock here to make sure the lock is released by last 627 * one-step timestamping packet through TX confirmation 628 * queue before transmit current packet. 629 */ 630 struct mutex onestep_tstamp_lock; 631 struct devlink *devlink; 632 struct dpaa2_eth_trap_data *trap_data; 633 struct devlink_port devlink_port; 634 635 u32 rx_copybreak; 636 637 struct dpaa2_eth_fds __percpu *fd; 638 }; 639 640 struct dpaa2_eth_devlink_priv { 641 struct dpaa2_eth_priv *dpaa2_priv; 642 }; 643 644 #define TX_TSTAMP 0x1 645 #define TX_TSTAMP_ONESTEP_SYNC 0x2 646 647 #define DPAA2_RXH_SUPPORTED (RXH_L2DA | RXH_VLAN | RXH_L3_PROTO \ 648 | RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 \ 649 | RXH_L4_B_2_3) 650 651 /* default Rx hash options, set during probing */ 652 #define DPAA2_RXH_DEFAULT (RXH_L3_PROTO | RXH_IP_SRC | RXH_IP_DST | \ 653 RXH_L4_B_0_1 | RXH_L4_B_2_3) 654 655 #define dpaa2_eth_hash_enabled(priv) \ 656 ((priv)->dpni_attrs.num_queues > 1) 657 658 /* Required by struct dpni_rx_tc_dist_cfg::key_cfg_iova */ 659 #define DPAA2_CLASSIFIER_DMA_SIZE 256 660 661 extern const struct ethtool_ops dpaa2_ethtool_ops; 662 extern int dpaa2_phc_index; 663 extern struct ptp_qoriq *dpaa2_ptp; 664 665 static inline int dpaa2_eth_cmp_dpni_ver(struct dpaa2_eth_priv *priv, 666 u16 ver_major, u16 ver_minor) 667 { 668 if (priv->dpni_ver_major == ver_major) 669 return priv->dpni_ver_minor - ver_minor; 670 return priv->dpni_ver_major - ver_major; 671 } 672 673 /* Minimum firmware version that supports a more flexible API 674 * for configuring the Rx flow hash key 675 */ 676 #define DPNI_RX_DIST_KEY_VER_MAJOR 7 677 #define DPNI_RX_DIST_KEY_VER_MINOR 5 678 679 #define dpaa2_eth_has_legacy_dist(priv) \ 680 (dpaa2_eth_cmp_dpni_ver((priv), DPNI_RX_DIST_KEY_VER_MAJOR, \ 681 DPNI_RX_DIST_KEY_VER_MINOR) < 0) 682 683 #define dpaa2_eth_fs_enabled(priv) \ 684 (!((priv)->dpni_attrs.options & DPNI_OPT_NO_FS)) 685 686 #define dpaa2_eth_fs_mask_enabled(priv) \ 687 ((priv)->dpni_attrs.options & DPNI_OPT_HAS_KEY_MASKING) 688 689 #define dpaa2_eth_fs_count(priv) \ 690 ((priv)->dpni_attrs.fs_entries) 691 692 #define dpaa2_eth_tc_count(priv) \ 693 ((priv)->dpni_attrs.num_tcs) 694 695 /* We have exactly one {Rx, Tx conf} queue per channel */ 696 #define dpaa2_eth_queue_count(priv) \ 697 ((priv)->num_channels) 698 699 enum dpaa2_eth_rx_dist { 700 DPAA2_ETH_RX_DIST_HASH, 701 DPAA2_ETH_RX_DIST_CLS 702 }; 703 704 /* Unique IDs for the supported Rx classification header fields */ 705 #define DPAA2_ETH_DIST_ETHDST BIT(0) 706 #define DPAA2_ETH_DIST_ETHSRC BIT(1) 707 #define DPAA2_ETH_DIST_ETHTYPE BIT(2) 708 #define DPAA2_ETH_DIST_VLAN BIT(3) 709 #define DPAA2_ETH_DIST_IPSRC BIT(4) 710 #define DPAA2_ETH_DIST_IPDST BIT(5) 711 #define DPAA2_ETH_DIST_IPPROTO BIT(6) 712 #define DPAA2_ETH_DIST_L4SRC BIT(7) 713 #define DPAA2_ETH_DIST_L4DST BIT(8) 714 #define DPAA2_ETH_DIST_ALL (~0ULL) 715 716 #define DPNI_PTP_ONESTEP_VER_MAJOR 8 717 #define DPNI_PTP_ONESTEP_VER_MINOR 2 718 #define DPAA2_ETH_FEATURE_ONESTEP_CFG_DIRECT BIT(0) 719 #define DPAA2_PTP_SINGLE_STEP_ENABLE BIT(31) 720 #define DPAA2_PTP_SINGLE_STEP_CH BIT(7) 721 #define DPAA2_PTP_SINGLE_CORRECTION_OFF(v) ((v) << 8) 722 723 #define DPNI_PAUSE_VER_MAJOR 7 724 #define DPNI_PAUSE_VER_MINOR 13 725 #define dpaa2_eth_has_pause_support(priv) \ 726 (dpaa2_eth_cmp_dpni_ver((priv), DPNI_PAUSE_VER_MAJOR, \ 727 DPNI_PAUSE_VER_MINOR) >= 0) 728 729 static inline bool dpaa2_eth_tx_pause_enabled(u64 link_options) 730 { 731 return !!(link_options & DPNI_LINK_OPT_PAUSE) ^ 732 !!(link_options & DPNI_LINK_OPT_ASYM_PAUSE); 733 } 734 735 static inline bool dpaa2_eth_rx_pause_enabled(u64 link_options) 736 { 737 return !!(link_options & DPNI_LINK_OPT_PAUSE); 738 } 739 740 static inline unsigned int dpaa2_eth_needed_headroom(struct sk_buff *skb) 741 { 742 unsigned int headroom = DPAA2_ETH_SWA_SIZE; 743 744 /* If we don't have an skb (e.g. XDP buffer), we only need space for 745 * the software annotation area 746 */ 747 if (!skb) 748 return headroom; 749 750 /* For non-linear skbs we have no headroom requirement, as we build a 751 * SG frame with a newly allocated SGT buffer 752 */ 753 if (skb_is_nonlinear(skb)) 754 return 0; 755 756 /* If we have Tx timestamping, need 128B hardware annotation */ 757 if (skb->cb[0]) 758 headroom += DPAA2_ETH_TX_HWA_SIZE; 759 760 return headroom; 761 } 762 763 /* Extra headroom space requested to hardware, in order to make sure there's 764 * no realloc'ing in forwarding scenarios 765 */ 766 static inline unsigned int dpaa2_eth_rx_head_room(struct dpaa2_eth_priv *priv) 767 { 768 return priv->tx_data_offset - DPAA2_ETH_RX_HWA_SIZE; 769 } 770 771 static inline bool dpaa2_eth_is_type_phy(struct dpaa2_eth_priv *priv) 772 { 773 lockdep_assert_held(&priv->mac_lock); 774 775 return dpaa2_mac_is_type_phy(priv->mac); 776 } 777 778 static inline bool dpaa2_eth_has_mac(struct dpaa2_eth_priv *priv) 779 { 780 lockdep_assert_held(&priv->mac_lock); 781 782 return priv->mac ? true : false; 783 } 784 785 int dpaa2_eth_set_hash(struct net_device *net_dev, u64 flags); 786 int dpaa2_eth_set_cls(struct net_device *net_dev, u64 key); 787 int dpaa2_eth_cls_key_size(u64 key); 788 int dpaa2_eth_cls_fld_off(int prot, int field); 789 void dpaa2_eth_cls_trim_rule(void *key_mem, u64 fields); 790 791 void dpaa2_eth_set_rx_taildrop(struct dpaa2_eth_priv *priv, 792 bool tx_pause, bool pfc); 793 794 extern const struct dcbnl_rtnl_ops dpaa2_eth_dcbnl_ops; 795 796 int dpaa2_eth_dl_alloc(struct dpaa2_eth_priv *priv); 797 void dpaa2_eth_dl_free(struct dpaa2_eth_priv *priv); 798 799 void dpaa2_eth_dl_register(struct dpaa2_eth_priv *priv); 800 void dpaa2_eth_dl_unregister(struct dpaa2_eth_priv *priv); 801 802 int dpaa2_eth_dl_port_add(struct dpaa2_eth_priv *priv); 803 void dpaa2_eth_dl_port_del(struct dpaa2_eth_priv *priv); 804 805 int dpaa2_eth_dl_traps_register(struct dpaa2_eth_priv *priv); 806 void dpaa2_eth_dl_traps_unregister(struct dpaa2_eth_priv *priv); 807 808 struct dpaa2_eth_trap_item *dpaa2_eth_dl_get_trap(struct dpaa2_eth_priv *priv, 809 struct dpaa2_fapr *fapr); 810 811 struct dpaa2_eth_bp *dpaa2_eth_allocate_dpbp(struct dpaa2_eth_priv *priv); 812 void dpaa2_eth_free_dpbp(struct dpaa2_eth_priv *priv, struct dpaa2_eth_bp *bp); 813 814 struct sk_buff *dpaa2_eth_alloc_skb(struct dpaa2_eth_priv *priv, 815 struct dpaa2_eth_channel *ch, 816 const struct dpaa2_fd *fd, u32 fd_length, 817 void *fd_vaddr); 818 819 void dpaa2_eth_receive_skb(struct dpaa2_eth_priv *priv, 820 struct dpaa2_eth_channel *ch, 821 const struct dpaa2_fd *fd, void *vaddr, 822 struct dpaa2_eth_fq *fq, 823 struct rtnl_link_stats64 *percpu_stats, 824 struct sk_buff *skb); 825 826 void dpaa2_eth_rx(struct dpaa2_eth_priv *priv, 827 struct dpaa2_eth_channel *ch, 828 const struct dpaa2_fd *fd, 829 struct dpaa2_eth_fq *fq); 830 831 struct dpaa2_eth_bp *dpaa2_eth_allocate_dpbp(struct dpaa2_eth_priv *priv); 832 void dpaa2_eth_free_dpbp(struct dpaa2_eth_priv *priv, 833 struct dpaa2_eth_bp *bp); 834 835 void *dpaa2_iova_to_virt(struct iommu_domain *domain, dma_addr_t iova_addr); 836 void dpaa2_eth_recycle_buf(struct dpaa2_eth_priv *priv, 837 struct dpaa2_eth_channel *ch, 838 dma_addr_t addr); 839 840 void dpaa2_eth_xdp_enqueue(struct dpaa2_eth_priv *priv, 841 struct dpaa2_eth_channel *ch, 842 struct dpaa2_fd *fd, 843 void *buf_start, u16 queue_id); 844 845 int dpaa2_xsk_wakeup(struct net_device *dev, u32 qid, u32 flags); 846 int dpaa2_xsk_setup_pool(struct net_device *dev, struct xsk_buff_pool *pool, u16 qid); 847 848 void dpaa2_eth_free_tx_fd(struct dpaa2_eth_priv *priv, 849 struct dpaa2_eth_channel *ch, 850 struct dpaa2_eth_fq *fq, 851 const struct dpaa2_fd *fd, bool in_napi); 852 bool dpaa2_xsk_tx(struct dpaa2_eth_priv *priv, 853 struct dpaa2_eth_channel *ch); 854 855 /* SGT (Scatter-Gather Table) cache management */ 856 void *dpaa2_eth_sgt_get(struct dpaa2_eth_priv *priv); 857 858 void dpaa2_eth_sgt_recycle(struct dpaa2_eth_priv *priv, void *sgt_buf); 859 860 #endif /* __DPAA2_H */ 861