1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ 2 /* Copyright 2014-2016 Freescale Semiconductor Inc. 3 * Copyright 2016 NXP 4 */ 5 6 #ifndef __DPAA2_ETH_H 7 #define __DPAA2_ETH_H 8 9 #include <linux/netdevice.h> 10 #include <linux/if_vlan.h> 11 #include <linux/fsl/mc.h> 12 13 #include <soc/fsl/dpaa2-io.h> 14 #include <soc/fsl/dpaa2-fd.h> 15 #include "dpni.h" 16 #include "dpni-cmd.h" 17 18 #include "dpaa2-eth-trace.h" 19 #include "dpaa2-eth-debugfs.h" 20 21 #define DPAA2_WRIOP_VERSION(x, y, z) ((x) << 10 | (y) << 5 | (z) << 0) 22 23 #define DPAA2_ETH_STORE_SIZE 16 24 25 /* Maximum number of scatter-gather entries in an ingress frame, 26 * considering the maximum receive frame size is 64K 27 */ 28 #define DPAA2_ETH_MAX_SG_ENTRIES ((64 * 1024) / DPAA2_ETH_RX_BUF_SIZE) 29 30 /* Maximum acceptable MTU value. It is in direct relation with the hardware 31 * enforced Max Frame Length (currently 10k). 32 */ 33 #define DPAA2_ETH_MFL (10 * 1024) 34 #define DPAA2_ETH_MAX_MTU (DPAA2_ETH_MFL - VLAN_ETH_HLEN) 35 /* Convert L3 MTU to L2 MFL */ 36 #define DPAA2_ETH_L2_MAX_FRM(mtu) ((mtu) + VLAN_ETH_HLEN) 37 38 /* Set the taildrop threshold (in bytes) to allow the enqueue of several jumbo 39 * frames in the Rx queues (length of the current frame is not 40 * taken into account when making the taildrop decision) 41 */ 42 #define DPAA2_ETH_TAILDROP_THRESH (64 * 1024) 43 44 /* Maximum number of Tx confirmation frames to be processed 45 * in a single NAPI call 46 */ 47 #define DPAA2_ETH_TXCONF_PER_NAPI 256 48 49 /* Buffer quota per queue. Must be large enough such that for minimum sized 50 * frames taildrop kicks in before the bpool gets depleted, so we compute 51 * how many 64B frames fit inside the taildrop threshold and add a margin 52 * to accommodate the buffer refill delay. 53 */ 54 #define DPAA2_ETH_MAX_FRAMES_PER_QUEUE (DPAA2_ETH_TAILDROP_THRESH / 64) 55 #define DPAA2_ETH_NUM_BUFS (DPAA2_ETH_MAX_FRAMES_PER_QUEUE + 256) 56 #define DPAA2_ETH_REFILL_THRESH DPAA2_ETH_MAX_FRAMES_PER_QUEUE 57 58 /* Maximum number of buffers that can be acquired/released through a single 59 * QBMan command 60 */ 61 #define DPAA2_ETH_BUFS_PER_CMD 7 62 63 /* Hardware requires alignment for ingress/egress buffer addresses */ 64 #define DPAA2_ETH_TX_BUF_ALIGN 64 65 66 #define DPAA2_ETH_RX_BUF_SIZE 2048 67 #define DPAA2_ETH_SKB_SIZE \ 68 (DPAA2_ETH_RX_BUF_SIZE + SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 69 70 /* Hardware annotation area in RX/TX buffers */ 71 #define DPAA2_ETH_RX_HWA_SIZE 64 72 #define DPAA2_ETH_TX_HWA_SIZE 128 73 74 /* PTP nominal frequency 1GHz */ 75 #define DPAA2_PTP_CLK_PERIOD_NS 1 76 77 /* Due to a limitation in WRIOP 1.0.0, the RX buffer data must be aligned 78 * to 256B. For newer revisions, the requirement is only for 64B alignment 79 */ 80 #define DPAA2_ETH_RX_BUF_ALIGN_REV1 256 81 #define DPAA2_ETH_RX_BUF_ALIGN 64 82 83 /* We are accommodating a skb backpointer and some S/G info 84 * in the frame's software annotation. The hardware 85 * options are either 0 or 64, so we choose the latter. 86 */ 87 #define DPAA2_ETH_SWA_SIZE 64 88 89 /* Must keep this struct smaller than DPAA2_ETH_SWA_SIZE */ 90 struct dpaa2_eth_swa { 91 struct sk_buff *skb; 92 struct scatterlist *scl; 93 int num_sg; 94 int sgt_size; 95 }; 96 97 /* Annotation valid bits in FD FRC */ 98 #define DPAA2_FD_FRC_FASV 0x8000 99 #define DPAA2_FD_FRC_FAEADV 0x4000 100 #define DPAA2_FD_FRC_FAPRV 0x2000 101 #define DPAA2_FD_FRC_FAIADV 0x1000 102 #define DPAA2_FD_FRC_FASWOV 0x0800 103 #define DPAA2_FD_FRC_FAICFDV 0x0400 104 105 /* Error bits in FD CTRL */ 106 #define DPAA2_FD_RX_ERR_MASK (FD_CTRL_SBE | FD_CTRL_FAERR) 107 #define DPAA2_FD_TX_ERR_MASK (FD_CTRL_UFD | \ 108 FD_CTRL_SBE | \ 109 FD_CTRL_FSE | \ 110 FD_CTRL_FAERR) 111 112 /* Annotation bits in FD CTRL */ 113 #define DPAA2_FD_CTRL_ASAL 0x00020000 /* ASAL = 128B */ 114 115 /* Frame annotation status */ 116 struct dpaa2_fas { 117 u8 reserved; 118 u8 ppid; 119 __le16 ifpid; 120 __le32 status; 121 }; 122 123 /* Frame annotation status word is located in the first 8 bytes 124 * of the buffer's hardware annoatation area 125 */ 126 #define DPAA2_FAS_OFFSET 0 127 #define DPAA2_FAS_SIZE (sizeof(struct dpaa2_fas)) 128 129 /* Timestamp is located in the next 8 bytes of the buffer's 130 * hardware annotation area 131 */ 132 #define DPAA2_TS_OFFSET 0x8 133 134 /* Frame annotation egress action descriptor */ 135 #define DPAA2_FAEAD_OFFSET 0x58 136 137 struct dpaa2_faead { 138 __le32 conf_fqid; 139 __le32 ctrl; 140 }; 141 142 #define DPAA2_FAEAD_A2V 0x20000000 143 #define DPAA2_FAEAD_A4V 0x08000000 144 #define DPAA2_FAEAD_UPDV 0x00001000 145 #define DPAA2_FAEAD_EBDDV 0x00002000 146 #define DPAA2_FAEAD_UPD 0x00000010 147 148 /* Accessors for the hardware annotation fields that we use */ 149 static inline void *dpaa2_get_hwa(void *buf_addr, bool swa) 150 { 151 return buf_addr + (swa ? DPAA2_ETH_SWA_SIZE : 0); 152 } 153 154 static inline struct dpaa2_fas *dpaa2_get_fas(void *buf_addr, bool swa) 155 { 156 return dpaa2_get_hwa(buf_addr, swa) + DPAA2_FAS_OFFSET; 157 } 158 159 static inline __le64 *dpaa2_get_ts(void *buf_addr, bool swa) 160 { 161 return dpaa2_get_hwa(buf_addr, swa) + DPAA2_TS_OFFSET; 162 } 163 164 static inline struct dpaa2_faead *dpaa2_get_faead(void *buf_addr, bool swa) 165 { 166 return dpaa2_get_hwa(buf_addr, swa) + DPAA2_FAEAD_OFFSET; 167 } 168 169 /* Error and status bits in the frame annotation status word */ 170 /* Debug frame, otherwise supposed to be discarded */ 171 #define DPAA2_FAS_DISC 0x80000000 172 /* MACSEC frame */ 173 #define DPAA2_FAS_MS 0x40000000 174 #define DPAA2_FAS_PTP 0x08000000 175 /* Ethernet multicast frame */ 176 #define DPAA2_FAS_MC 0x04000000 177 /* Ethernet broadcast frame */ 178 #define DPAA2_FAS_BC 0x02000000 179 #define DPAA2_FAS_KSE 0x00040000 180 #define DPAA2_FAS_EOFHE 0x00020000 181 #define DPAA2_FAS_MNLE 0x00010000 182 #define DPAA2_FAS_TIDE 0x00008000 183 #define DPAA2_FAS_PIEE 0x00004000 184 /* Frame length error */ 185 #define DPAA2_FAS_FLE 0x00002000 186 /* Frame physical error */ 187 #define DPAA2_FAS_FPE 0x00001000 188 #define DPAA2_FAS_PTE 0x00000080 189 #define DPAA2_FAS_ISP 0x00000040 190 #define DPAA2_FAS_PHE 0x00000020 191 #define DPAA2_FAS_BLE 0x00000010 192 /* L3 csum validation performed */ 193 #define DPAA2_FAS_L3CV 0x00000008 194 /* L3 csum error */ 195 #define DPAA2_FAS_L3CE 0x00000004 196 /* L4 csum validation performed */ 197 #define DPAA2_FAS_L4CV 0x00000002 198 /* L4 csum error */ 199 #define DPAA2_FAS_L4CE 0x00000001 200 /* Possible errors on the ingress path */ 201 #define DPAA2_FAS_RX_ERR_MASK (DPAA2_FAS_KSE | \ 202 DPAA2_FAS_EOFHE | \ 203 DPAA2_FAS_MNLE | \ 204 DPAA2_FAS_TIDE | \ 205 DPAA2_FAS_PIEE | \ 206 DPAA2_FAS_FLE | \ 207 DPAA2_FAS_FPE | \ 208 DPAA2_FAS_PTE | \ 209 DPAA2_FAS_ISP | \ 210 DPAA2_FAS_PHE | \ 211 DPAA2_FAS_BLE | \ 212 DPAA2_FAS_L3CE | \ 213 DPAA2_FAS_L4CE) 214 215 /* Time in milliseconds between link state updates */ 216 #define DPAA2_ETH_LINK_STATE_REFRESH 1000 217 218 /* Number of times to retry a frame enqueue before giving up. 219 * Value determined empirically, in order to minimize the number 220 * of frames dropped on Tx 221 */ 222 #define DPAA2_ETH_ENQUEUE_RETRIES 10 223 224 /* Driver statistics, other than those in struct rtnl_link_stats64. 225 * These are usually collected per-CPU and aggregated by ethtool. 226 */ 227 struct dpaa2_eth_drv_stats { 228 __u64 tx_conf_frames; 229 __u64 tx_conf_bytes; 230 __u64 tx_sg_frames; 231 __u64 tx_sg_bytes; 232 __u64 tx_reallocs; 233 __u64 rx_sg_frames; 234 __u64 rx_sg_bytes; 235 /* Enqueues retried due to portal busy */ 236 __u64 tx_portal_busy; 237 }; 238 239 /* Per-FQ statistics */ 240 struct dpaa2_eth_fq_stats { 241 /* Number of frames received on this queue */ 242 __u64 frames; 243 }; 244 245 /* Per-channel statistics */ 246 struct dpaa2_eth_ch_stats { 247 /* Volatile dequeues retried due to portal busy */ 248 __u64 dequeue_portal_busy; 249 /* Pull errors */ 250 __u64 pull_err; 251 /* Number of CDANs; useful to estimate avg NAPI len */ 252 __u64 cdan; 253 /* XDP counters */ 254 __u64 xdp_drop; 255 __u64 xdp_tx; 256 __u64 xdp_tx_err; 257 }; 258 259 /* Maximum number of queues associated with a DPNI */ 260 #define DPAA2_ETH_MAX_RX_QUEUES 16 261 #define DPAA2_ETH_MAX_TX_QUEUES 16 262 #define DPAA2_ETH_MAX_QUEUES (DPAA2_ETH_MAX_RX_QUEUES + \ 263 DPAA2_ETH_MAX_TX_QUEUES) 264 265 #define DPAA2_ETH_MAX_DPCONS 16 266 267 enum dpaa2_eth_fq_type { 268 DPAA2_RX_FQ = 0, 269 DPAA2_TX_CONF_FQ, 270 }; 271 272 struct dpaa2_eth_priv; 273 274 struct dpaa2_eth_fq { 275 u32 fqid; 276 u32 tx_qdbin; 277 u16 flowid; 278 int target_cpu; 279 u32 dq_frames; 280 u32 dq_bytes; 281 struct dpaa2_eth_channel *channel; 282 enum dpaa2_eth_fq_type type; 283 284 void (*consume)(struct dpaa2_eth_priv *priv, 285 struct dpaa2_eth_channel *ch, 286 const struct dpaa2_fd *fd, 287 struct dpaa2_eth_fq *fq); 288 struct dpaa2_eth_fq_stats stats; 289 }; 290 291 struct dpaa2_eth_ch_xdp { 292 struct bpf_prog *prog; 293 u64 drop_bufs[DPAA2_ETH_BUFS_PER_CMD]; 294 int drop_cnt; 295 }; 296 297 struct dpaa2_eth_channel { 298 struct dpaa2_io_notification_ctx nctx; 299 struct fsl_mc_device *dpcon; 300 int dpcon_id; 301 int ch_id; 302 struct napi_struct napi; 303 struct dpaa2_io *dpio; 304 struct dpaa2_io_store *store; 305 struct dpaa2_eth_priv *priv; 306 int buf_count; 307 struct dpaa2_eth_ch_stats stats; 308 struct dpaa2_eth_ch_xdp xdp; 309 }; 310 311 struct dpaa2_eth_dist_fields { 312 u64 rxnfc_field; 313 enum net_prot cls_prot; 314 int cls_field; 315 int size; 316 }; 317 318 struct dpaa2_eth_cls_rule { 319 struct ethtool_rx_flow_spec fs; 320 u8 in_use; 321 }; 322 323 /* Driver private data */ 324 struct dpaa2_eth_priv { 325 struct net_device *net_dev; 326 327 u8 num_fqs; 328 struct dpaa2_eth_fq fq[DPAA2_ETH_MAX_QUEUES]; 329 330 u8 num_channels; 331 struct dpaa2_eth_channel *channel[DPAA2_ETH_MAX_DPCONS]; 332 333 struct dpni_attr dpni_attrs; 334 u16 dpni_ver_major; 335 u16 dpni_ver_minor; 336 u16 tx_data_offset; 337 338 struct fsl_mc_device *dpbp_dev; 339 u16 bpid; 340 struct iommu_domain *iommu_domain; 341 342 bool tx_tstamp; /* Tx timestamping enabled */ 343 bool rx_tstamp; /* Rx timestamping enabled */ 344 345 u16 tx_qdid; 346 u16 rx_buf_align; 347 struct fsl_mc_io *mc_io; 348 /* Cores which have an affine DPIO/DPCON. 349 * This is the cpu set on which Rx and Tx conf frames are processed 350 */ 351 struct cpumask dpio_cpumask; 352 353 /* Standard statistics */ 354 struct rtnl_link_stats64 __percpu *percpu_stats; 355 /* Extra stats, in addition to the ones known by the kernel */ 356 struct dpaa2_eth_drv_stats __percpu *percpu_extras; 357 358 u16 mc_token; 359 360 struct dpni_link_state link_state; 361 bool do_link_poll; 362 struct task_struct *poll_thread; 363 364 /* enabled ethtool hashing bits */ 365 u64 rx_hash_fields; 366 struct dpaa2_eth_cls_rule *cls_rules; 367 u8 rx_cls_enabled; 368 struct bpf_prog *xdp_prog; 369 #ifdef CONFIG_DEBUG_FS 370 struct dpaa2_debugfs dbg; 371 #endif 372 }; 373 374 #define DPAA2_RXH_SUPPORTED (RXH_L2DA | RXH_VLAN | RXH_L3_PROTO \ 375 | RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 \ 376 | RXH_L4_B_2_3) 377 378 /* default Rx hash options, set during probing */ 379 #define DPAA2_RXH_DEFAULT (RXH_L3_PROTO | RXH_IP_SRC | RXH_IP_DST | \ 380 RXH_L4_B_0_1 | RXH_L4_B_2_3) 381 382 #define dpaa2_eth_hash_enabled(priv) \ 383 ((priv)->dpni_attrs.num_queues > 1) 384 385 /* Required by struct dpni_rx_tc_dist_cfg::key_cfg_iova */ 386 #define DPAA2_CLASSIFIER_DMA_SIZE 256 387 388 extern const struct ethtool_ops dpaa2_ethtool_ops; 389 extern int dpaa2_phc_index; 390 391 static inline int dpaa2_eth_cmp_dpni_ver(struct dpaa2_eth_priv *priv, 392 u16 ver_major, u16 ver_minor) 393 { 394 if (priv->dpni_ver_major == ver_major) 395 return priv->dpni_ver_minor - ver_minor; 396 return priv->dpni_ver_major - ver_major; 397 } 398 399 /* Minimum firmware version that supports a more flexible API 400 * for configuring the Rx flow hash key 401 */ 402 #define DPNI_RX_DIST_KEY_VER_MAJOR 7 403 #define DPNI_RX_DIST_KEY_VER_MINOR 5 404 405 #define dpaa2_eth_has_legacy_dist(priv) \ 406 (dpaa2_eth_cmp_dpni_ver((priv), DPNI_RX_DIST_KEY_VER_MAJOR, \ 407 DPNI_RX_DIST_KEY_VER_MINOR) < 0) 408 409 #define dpaa2_eth_fs_count(priv) \ 410 ((priv)->dpni_attrs.fs_entries) 411 412 /* We have exactly one {Rx, Tx conf} queue per channel */ 413 #define dpaa2_eth_queue_count(priv) \ 414 ((priv)->num_channels) 415 416 enum dpaa2_eth_rx_dist { 417 DPAA2_ETH_RX_DIST_HASH, 418 DPAA2_ETH_RX_DIST_CLS 419 }; 420 421 /* Hardware only sees DPAA2_ETH_RX_BUF_SIZE, but the skb built around 422 * the buffer also needs space for its shared info struct, and we need 423 * to allocate enough to accommodate hardware alignment restrictions 424 */ 425 static inline unsigned int dpaa2_eth_buf_raw_size(struct dpaa2_eth_priv *priv) 426 { 427 return DPAA2_ETH_SKB_SIZE + priv->rx_buf_align; 428 } 429 430 static inline 431 unsigned int dpaa2_eth_needed_headroom(struct dpaa2_eth_priv *priv, 432 struct sk_buff *skb) 433 { 434 unsigned int headroom = DPAA2_ETH_SWA_SIZE; 435 436 /* For non-linear skbs we have no headroom requirement, as we build a 437 * SG frame with a newly allocated SGT buffer 438 */ 439 if (skb_is_nonlinear(skb)) 440 return 0; 441 442 /* If we have Tx timestamping, need 128B hardware annotation */ 443 if (priv->tx_tstamp && skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) 444 headroom += DPAA2_ETH_TX_HWA_SIZE; 445 446 return headroom; 447 } 448 449 /* Extra headroom space requested to hardware, in order to make sure there's 450 * no realloc'ing in forwarding scenarios 451 */ 452 static inline unsigned int dpaa2_eth_rx_head_room(struct dpaa2_eth_priv *priv) 453 { 454 return priv->tx_data_offset + DPAA2_ETH_TX_BUF_ALIGN - 455 DPAA2_ETH_RX_HWA_SIZE; 456 } 457 458 int dpaa2_eth_set_hash(struct net_device *net_dev, u64 flags); 459 int dpaa2_eth_cls_key_size(void); 460 int dpaa2_eth_cls_fld_off(int prot, int field); 461 462 #endif /* __DPAA2_H */ 463