1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ 2 /* Copyright 2014-2016 Freescale Semiconductor Inc. 3 * Copyright 2016-2020 NXP 4 */ 5 6 #ifndef __DPAA2_ETH_H 7 #define __DPAA2_ETH_H 8 9 #include <linux/dcbnl.h> 10 #include <linux/netdevice.h> 11 #include <linux/if_vlan.h> 12 #include <linux/fsl/mc.h> 13 14 #include <soc/fsl/dpaa2-io.h> 15 #include <soc/fsl/dpaa2-fd.h> 16 #include "dpni.h" 17 #include "dpni-cmd.h" 18 19 #include "dpaa2-eth-trace.h" 20 #include "dpaa2-eth-debugfs.h" 21 #include "dpaa2-mac.h" 22 23 #define DPAA2_WRIOP_VERSION(x, y, z) ((x) << 10 | (y) << 5 | (z) << 0) 24 25 #define DPAA2_ETH_STORE_SIZE 16 26 27 /* Maximum number of scatter-gather entries in an ingress frame, 28 * considering the maximum receive frame size is 64K 29 */ 30 #define DPAA2_ETH_MAX_SG_ENTRIES ((64 * 1024) / DPAA2_ETH_RX_BUF_SIZE) 31 32 /* Maximum acceptable MTU value. It is in direct relation with the hardware 33 * enforced Max Frame Length (currently 10k). 34 */ 35 #define DPAA2_ETH_MFL (10 * 1024) 36 #define DPAA2_ETH_MAX_MTU (DPAA2_ETH_MFL - VLAN_ETH_HLEN) 37 /* Convert L3 MTU to L2 MFL */ 38 #define DPAA2_ETH_L2_MAX_FRM(mtu) ((mtu) + VLAN_ETH_HLEN) 39 40 /* Set the taildrop threshold (in bytes) to allow the enqueue of a large 41 * enough number of jumbo frames in the Rx queues (length of the current 42 * frame is not taken into account when making the taildrop decision) 43 */ 44 #define DPAA2_ETH_FQ_TAILDROP_THRESH (1024 * 1024) 45 46 /* Maximum burst size value for Tx shaping */ 47 #define DPAA2_ETH_MAX_BURST_SIZE 0xF7FF 48 49 /* Maximum number of Tx confirmation frames to be processed 50 * in a single NAPI call 51 */ 52 #define DPAA2_ETH_TXCONF_PER_NAPI 256 53 54 /* Buffer qouta per channel. We want to keep in check number of ingress frames 55 * in flight: for small sized frames, congestion group taildrop may kick in 56 * first; for large sizes, Rx FQ taildrop threshold will ensure only a 57 * reasonable number of frames will be pending at any given time. 58 * Ingress frame drop due to buffer pool depletion should be a corner case only 59 */ 60 #define DPAA2_ETH_NUM_BUFS 1280 61 #define DPAA2_ETH_REFILL_THRESH \ 62 (DPAA2_ETH_NUM_BUFS - DPAA2_ETH_BUFS_PER_CMD) 63 64 /* Congestion group taildrop threshold: number of frames allowed to accumulate 65 * at any moment in a group of Rx queues belonging to the same traffic class. 66 * Choose value such that we don't risk depleting the buffer pool before the 67 * taildrop kicks in 68 */ 69 #define DPAA2_ETH_CG_TAILDROP_THRESH(priv) \ 70 (1024 * dpaa2_eth_queue_count(priv) / dpaa2_eth_tc_count(priv)) 71 72 /* Congestion group notification threshold: when this many frames accumulate 73 * on the Rx queues belonging to the same TC, the MAC is instructed to send 74 * PFC frames for that TC. 75 * When number of pending frames drops below exit threshold transmission of 76 * PFC frames is stopped. 77 */ 78 #define DPAA2_ETH_CN_THRESH_ENTRY(priv) \ 79 (DPAA2_ETH_CG_TAILDROP_THRESH(priv) / 2) 80 #define DPAA2_ETH_CN_THRESH_EXIT(priv) \ 81 (DPAA2_ETH_CN_THRESH_ENTRY(priv) * 3 / 4) 82 83 /* Maximum number of buffers that can be acquired/released through a single 84 * QBMan command 85 */ 86 #define DPAA2_ETH_BUFS_PER_CMD 7 87 88 /* Hardware requires alignment for ingress/egress buffer addresses */ 89 #define DPAA2_ETH_TX_BUF_ALIGN 64 90 91 #define DPAA2_ETH_RX_BUF_RAW_SIZE PAGE_SIZE 92 #define DPAA2_ETH_RX_BUF_TAILROOM \ 93 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) 94 #define DPAA2_ETH_RX_BUF_SIZE \ 95 (DPAA2_ETH_RX_BUF_RAW_SIZE - DPAA2_ETH_RX_BUF_TAILROOM) 96 97 /* Hardware annotation area in RX/TX buffers */ 98 #define DPAA2_ETH_RX_HWA_SIZE 64 99 #define DPAA2_ETH_TX_HWA_SIZE 128 100 101 /* PTP nominal frequency 1GHz */ 102 #define DPAA2_PTP_CLK_PERIOD_NS 1 103 104 /* Due to a limitation in WRIOP 1.0.0, the RX buffer data must be aligned 105 * to 256B. For newer revisions, the requirement is only for 64B alignment 106 */ 107 #define DPAA2_ETH_RX_BUF_ALIGN_REV1 256 108 #define DPAA2_ETH_RX_BUF_ALIGN 64 109 110 /* We are accommodating a skb backpointer and some S/G info 111 * in the frame's software annotation. The hardware 112 * options are either 0 or 64, so we choose the latter. 113 */ 114 #define DPAA2_ETH_SWA_SIZE 64 115 116 /* We store different information in the software annotation area of a Tx frame 117 * based on what type of frame it is 118 */ 119 enum dpaa2_eth_swa_type { 120 DPAA2_ETH_SWA_SINGLE, 121 DPAA2_ETH_SWA_SG, 122 DPAA2_ETH_SWA_XDP, 123 }; 124 125 /* Must keep this struct smaller than DPAA2_ETH_SWA_SIZE */ 126 struct dpaa2_eth_swa { 127 enum dpaa2_eth_swa_type type; 128 union { 129 struct { 130 struct sk_buff *skb; 131 int sgt_size; 132 } single; 133 struct { 134 struct sk_buff *skb; 135 struct scatterlist *scl; 136 int num_sg; 137 int sgt_size; 138 } sg; 139 struct { 140 int dma_size; 141 struct xdp_frame *xdpf; 142 } xdp; 143 }; 144 }; 145 146 /* Annotation valid bits in FD FRC */ 147 #define DPAA2_FD_FRC_FASV 0x8000 148 #define DPAA2_FD_FRC_FAEADV 0x4000 149 #define DPAA2_FD_FRC_FAPRV 0x2000 150 #define DPAA2_FD_FRC_FAIADV 0x1000 151 #define DPAA2_FD_FRC_FASWOV 0x0800 152 #define DPAA2_FD_FRC_FAICFDV 0x0400 153 154 /* Error bits in FD CTRL */ 155 #define DPAA2_FD_RX_ERR_MASK (FD_CTRL_SBE | FD_CTRL_FAERR) 156 #define DPAA2_FD_TX_ERR_MASK (FD_CTRL_UFD | \ 157 FD_CTRL_SBE | \ 158 FD_CTRL_FSE | \ 159 FD_CTRL_FAERR) 160 161 /* Annotation bits in FD CTRL */ 162 #define DPAA2_FD_CTRL_ASAL 0x00020000 /* ASAL = 128B */ 163 164 /* Frame annotation status */ 165 struct dpaa2_fas { 166 u8 reserved; 167 u8 ppid; 168 __le16 ifpid; 169 __le32 status; 170 }; 171 172 /* Frame annotation status word is located in the first 8 bytes 173 * of the buffer's hardware annoatation area 174 */ 175 #define DPAA2_FAS_OFFSET 0 176 #define DPAA2_FAS_SIZE (sizeof(struct dpaa2_fas)) 177 178 /* Timestamp is located in the next 8 bytes of the buffer's 179 * hardware annotation area 180 */ 181 #define DPAA2_TS_OFFSET 0x8 182 183 /* Frame annotation egress action descriptor */ 184 #define DPAA2_FAEAD_OFFSET 0x58 185 186 struct dpaa2_faead { 187 __le32 conf_fqid; 188 __le32 ctrl; 189 }; 190 191 #define DPAA2_FAEAD_A2V 0x20000000 192 #define DPAA2_FAEAD_A4V 0x08000000 193 #define DPAA2_FAEAD_UPDV 0x00001000 194 #define DPAA2_FAEAD_EBDDV 0x00002000 195 #define DPAA2_FAEAD_UPD 0x00000010 196 197 /* Accessors for the hardware annotation fields that we use */ 198 static inline void *dpaa2_get_hwa(void *buf_addr, bool swa) 199 { 200 return buf_addr + (swa ? DPAA2_ETH_SWA_SIZE : 0); 201 } 202 203 static inline struct dpaa2_fas *dpaa2_get_fas(void *buf_addr, bool swa) 204 { 205 return dpaa2_get_hwa(buf_addr, swa) + DPAA2_FAS_OFFSET; 206 } 207 208 static inline __le64 *dpaa2_get_ts(void *buf_addr, bool swa) 209 { 210 return dpaa2_get_hwa(buf_addr, swa) + DPAA2_TS_OFFSET; 211 } 212 213 static inline struct dpaa2_faead *dpaa2_get_faead(void *buf_addr, bool swa) 214 { 215 return dpaa2_get_hwa(buf_addr, swa) + DPAA2_FAEAD_OFFSET; 216 } 217 218 /* Error and status bits in the frame annotation status word */ 219 /* Debug frame, otherwise supposed to be discarded */ 220 #define DPAA2_FAS_DISC 0x80000000 221 /* MACSEC frame */ 222 #define DPAA2_FAS_MS 0x40000000 223 #define DPAA2_FAS_PTP 0x08000000 224 /* Ethernet multicast frame */ 225 #define DPAA2_FAS_MC 0x04000000 226 /* Ethernet broadcast frame */ 227 #define DPAA2_FAS_BC 0x02000000 228 #define DPAA2_FAS_KSE 0x00040000 229 #define DPAA2_FAS_EOFHE 0x00020000 230 #define DPAA2_FAS_MNLE 0x00010000 231 #define DPAA2_FAS_TIDE 0x00008000 232 #define DPAA2_FAS_PIEE 0x00004000 233 /* Frame length error */ 234 #define DPAA2_FAS_FLE 0x00002000 235 /* Frame physical error */ 236 #define DPAA2_FAS_FPE 0x00001000 237 #define DPAA2_FAS_PTE 0x00000080 238 #define DPAA2_FAS_ISP 0x00000040 239 #define DPAA2_FAS_PHE 0x00000020 240 #define DPAA2_FAS_BLE 0x00000010 241 /* L3 csum validation performed */ 242 #define DPAA2_FAS_L3CV 0x00000008 243 /* L3 csum error */ 244 #define DPAA2_FAS_L3CE 0x00000004 245 /* L4 csum validation performed */ 246 #define DPAA2_FAS_L4CV 0x00000002 247 /* L4 csum error */ 248 #define DPAA2_FAS_L4CE 0x00000001 249 /* Possible errors on the ingress path */ 250 #define DPAA2_FAS_RX_ERR_MASK (DPAA2_FAS_KSE | \ 251 DPAA2_FAS_EOFHE | \ 252 DPAA2_FAS_MNLE | \ 253 DPAA2_FAS_TIDE | \ 254 DPAA2_FAS_PIEE | \ 255 DPAA2_FAS_FLE | \ 256 DPAA2_FAS_FPE | \ 257 DPAA2_FAS_PTE | \ 258 DPAA2_FAS_ISP | \ 259 DPAA2_FAS_PHE | \ 260 DPAA2_FAS_BLE | \ 261 DPAA2_FAS_L3CE | \ 262 DPAA2_FAS_L4CE) 263 264 /* Time in milliseconds between link state updates */ 265 #define DPAA2_ETH_LINK_STATE_REFRESH 1000 266 267 /* Number of times to retry a frame enqueue before giving up. 268 * Value determined empirically, in order to minimize the number 269 * of frames dropped on Tx 270 */ 271 #define DPAA2_ETH_ENQUEUE_RETRIES 10 272 273 /* Number of times to retry DPIO portal operations while waiting 274 * for portal to finish executing current command and become 275 * available. We want to avoid being stuck in a while loop in case 276 * hardware becomes unresponsive, but not give up too easily if 277 * the portal really is busy for valid reasons 278 */ 279 #define DPAA2_ETH_SWP_BUSY_RETRIES 1000 280 281 /* Driver statistics, other than those in struct rtnl_link_stats64. 282 * These are usually collected per-CPU and aggregated by ethtool. 283 */ 284 struct dpaa2_eth_drv_stats { 285 __u64 tx_conf_frames; 286 __u64 tx_conf_bytes; 287 __u64 tx_sg_frames; 288 __u64 tx_sg_bytes; 289 __u64 rx_sg_frames; 290 __u64 rx_sg_bytes; 291 /* Linear skbs sent as a S/G FD due to insufficient headroom */ 292 __u64 tx_converted_sg_frames; 293 __u64 tx_converted_sg_bytes; 294 /* Enqueues retried due to portal busy */ 295 __u64 tx_portal_busy; 296 }; 297 298 /* Per-FQ statistics */ 299 struct dpaa2_eth_fq_stats { 300 /* Number of frames received on this queue */ 301 __u64 frames; 302 }; 303 304 /* Per-channel statistics */ 305 struct dpaa2_eth_ch_stats { 306 /* Volatile dequeues retried due to portal busy */ 307 __u64 dequeue_portal_busy; 308 /* Pull errors */ 309 __u64 pull_err; 310 /* Number of CDANs; useful to estimate avg NAPI len */ 311 __u64 cdan; 312 /* XDP counters */ 313 __u64 xdp_drop; 314 __u64 xdp_tx; 315 __u64 xdp_tx_err; 316 __u64 xdp_redirect; 317 /* Must be last, does not show up in ethtool stats */ 318 __u64 frames; 319 }; 320 321 /* Maximum number of queues associated with a DPNI */ 322 #define DPAA2_ETH_MAX_TCS 8 323 #define DPAA2_ETH_MAX_RX_QUEUES_PER_TC 16 324 #define DPAA2_ETH_MAX_RX_QUEUES \ 325 (DPAA2_ETH_MAX_RX_QUEUES_PER_TC * DPAA2_ETH_MAX_TCS) 326 #define DPAA2_ETH_MAX_TX_QUEUES 16 327 #define DPAA2_ETH_MAX_QUEUES (DPAA2_ETH_MAX_RX_QUEUES + \ 328 DPAA2_ETH_MAX_TX_QUEUES) 329 #define DPAA2_ETH_MAX_NETDEV_QUEUES \ 330 (DPAA2_ETH_MAX_TX_QUEUES * DPAA2_ETH_MAX_TCS) 331 332 #define DPAA2_ETH_MAX_DPCONS 16 333 334 enum dpaa2_eth_fq_type { 335 DPAA2_RX_FQ = 0, 336 DPAA2_TX_CONF_FQ, 337 }; 338 339 struct dpaa2_eth_priv; 340 341 struct dpaa2_eth_xdp_fds { 342 struct dpaa2_fd fds[DEV_MAP_BULK_SIZE]; 343 ssize_t num; 344 }; 345 346 struct dpaa2_eth_fq { 347 u32 fqid; 348 u32 tx_qdbin; 349 u32 tx_fqid[DPAA2_ETH_MAX_TCS]; 350 u16 flowid; 351 u8 tc; 352 int target_cpu; 353 u32 dq_frames; 354 u32 dq_bytes; 355 struct dpaa2_eth_channel *channel; 356 enum dpaa2_eth_fq_type type; 357 358 void (*consume)(struct dpaa2_eth_priv *priv, 359 struct dpaa2_eth_channel *ch, 360 const struct dpaa2_fd *fd, 361 struct dpaa2_eth_fq *fq); 362 struct dpaa2_eth_fq_stats stats; 363 364 struct dpaa2_eth_xdp_fds xdp_redirect_fds; 365 struct dpaa2_eth_xdp_fds xdp_tx_fds; 366 }; 367 368 struct dpaa2_eth_ch_xdp { 369 struct bpf_prog *prog; 370 u64 drop_bufs[DPAA2_ETH_BUFS_PER_CMD]; 371 int drop_cnt; 372 unsigned int res; 373 }; 374 375 struct dpaa2_eth_channel { 376 struct dpaa2_io_notification_ctx nctx; 377 struct fsl_mc_device *dpcon; 378 int dpcon_id; 379 int ch_id; 380 struct napi_struct napi; 381 struct dpaa2_io *dpio; 382 struct dpaa2_io_store *store; 383 struct dpaa2_eth_priv *priv; 384 int buf_count; 385 struct dpaa2_eth_ch_stats stats; 386 struct dpaa2_eth_ch_xdp xdp; 387 struct xdp_rxq_info xdp_rxq; 388 struct list_head *rx_list; 389 }; 390 391 struct dpaa2_eth_dist_fields { 392 u64 rxnfc_field; 393 enum net_prot cls_prot; 394 int cls_field; 395 int size; 396 u64 id; 397 }; 398 399 struct dpaa2_eth_cls_rule { 400 struct ethtool_rx_flow_spec fs; 401 u8 in_use; 402 }; 403 404 #define DPAA2_ETH_SGT_CACHE_SIZE 256 405 struct dpaa2_eth_sgt_cache { 406 void *buf[DPAA2_ETH_SGT_CACHE_SIZE]; 407 u16 count; 408 }; 409 410 /* Driver private data */ 411 struct dpaa2_eth_priv { 412 struct net_device *net_dev; 413 414 u8 num_fqs; 415 struct dpaa2_eth_fq fq[DPAA2_ETH_MAX_QUEUES]; 416 int (*enqueue)(struct dpaa2_eth_priv *priv, 417 struct dpaa2_eth_fq *fq, 418 struct dpaa2_fd *fd, u8 prio, 419 u32 num_frames, 420 int *frames_enqueued); 421 422 u8 num_channels; 423 struct dpaa2_eth_channel *channel[DPAA2_ETH_MAX_DPCONS]; 424 struct dpaa2_eth_sgt_cache __percpu *sgt_cache; 425 426 struct dpni_attr dpni_attrs; 427 u16 dpni_ver_major; 428 u16 dpni_ver_minor; 429 u16 tx_data_offset; 430 431 struct fsl_mc_device *dpbp_dev; 432 u16 rx_buf_size; 433 u16 bpid; 434 struct iommu_domain *iommu_domain; 435 436 bool tx_tstamp; /* Tx timestamping enabled */ 437 bool rx_tstamp; /* Rx timestamping enabled */ 438 439 u16 tx_qdid; 440 struct fsl_mc_io *mc_io; 441 /* Cores which have an affine DPIO/DPCON. 442 * This is the cpu set on which Rx and Tx conf frames are processed 443 */ 444 struct cpumask dpio_cpumask; 445 446 /* Standard statistics */ 447 struct rtnl_link_stats64 __percpu *percpu_stats; 448 /* Extra stats, in addition to the ones known by the kernel */ 449 struct dpaa2_eth_drv_stats __percpu *percpu_extras; 450 451 u16 mc_token; 452 u8 rx_fqtd_enabled; 453 u8 rx_cgtd_enabled; 454 455 struct dpni_link_state link_state; 456 bool do_link_poll; 457 struct task_struct *poll_thread; 458 459 /* enabled ethtool hashing bits */ 460 u64 rx_hash_fields; 461 u64 rx_cls_fields; 462 struct dpaa2_eth_cls_rule *cls_rules; 463 u8 rx_cls_enabled; 464 u8 vlan_cls_enabled; 465 u8 pfc_enabled; 466 #ifdef CONFIG_FSL_DPAA2_ETH_DCB 467 u8 dcbx_mode; 468 struct ieee_pfc pfc; 469 #endif 470 struct bpf_prog *xdp_prog; 471 #ifdef CONFIG_DEBUG_FS 472 struct dpaa2_debugfs dbg; 473 #endif 474 475 struct dpaa2_mac *mac; 476 }; 477 478 #define DPAA2_RXH_SUPPORTED (RXH_L2DA | RXH_VLAN | RXH_L3_PROTO \ 479 | RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 \ 480 | RXH_L4_B_2_3) 481 482 /* default Rx hash options, set during probing */ 483 #define DPAA2_RXH_DEFAULT (RXH_L3_PROTO | RXH_IP_SRC | RXH_IP_DST | \ 484 RXH_L4_B_0_1 | RXH_L4_B_2_3) 485 486 #define dpaa2_eth_hash_enabled(priv) \ 487 ((priv)->dpni_attrs.num_queues > 1) 488 489 /* Required by struct dpni_rx_tc_dist_cfg::key_cfg_iova */ 490 #define DPAA2_CLASSIFIER_DMA_SIZE 256 491 492 extern const struct ethtool_ops dpaa2_ethtool_ops; 493 extern int dpaa2_phc_index; 494 495 static inline int dpaa2_eth_cmp_dpni_ver(struct dpaa2_eth_priv *priv, 496 u16 ver_major, u16 ver_minor) 497 { 498 if (priv->dpni_ver_major == ver_major) 499 return priv->dpni_ver_minor - ver_minor; 500 return priv->dpni_ver_major - ver_major; 501 } 502 503 /* Minimum firmware version that supports a more flexible API 504 * for configuring the Rx flow hash key 505 */ 506 #define DPNI_RX_DIST_KEY_VER_MAJOR 7 507 #define DPNI_RX_DIST_KEY_VER_MINOR 5 508 509 #define dpaa2_eth_has_legacy_dist(priv) \ 510 (dpaa2_eth_cmp_dpni_ver((priv), DPNI_RX_DIST_KEY_VER_MAJOR, \ 511 DPNI_RX_DIST_KEY_VER_MINOR) < 0) 512 513 #define dpaa2_eth_fs_enabled(priv) \ 514 (!((priv)->dpni_attrs.options & DPNI_OPT_NO_FS)) 515 516 #define dpaa2_eth_fs_mask_enabled(priv) \ 517 ((priv)->dpni_attrs.options & DPNI_OPT_HAS_KEY_MASKING) 518 519 #define dpaa2_eth_fs_count(priv) \ 520 ((priv)->dpni_attrs.fs_entries) 521 522 #define dpaa2_eth_tc_count(priv) \ 523 ((priv)->dpni_attrs.num_tcs) 524 525 /* We have exactly one {Rx, Tx conf} queue per channel */ 526 #define dpaa2_eth_queue_count(priv) \ 527 ((priv)->num_channels) 528 529 enum dpaa2_eth_rx_dist { 530 DPAA2_ETH_RX_DIST_HASH, 531 DPAA2_ETH_RX_DIST_CLS 532 }; 533 534 /* Unique IDs for the supported Rx classification header fields */ 535 #define DPAA2_ETH_DIST_ETHDST BIT(0) 536 #define DPAA2_ETH_DIST_ETHSRC BIT(1) 537 #define DPAA2_ETH_DIST_ETHTYPE BIT(2) 538 #define DPAA2_ETH_DIST_VLAN BIT(3) 539 #define DPAA2_ETH_DIST_IPSRC BIT(4) 540 #define DPAA2_ETH_DIST_IPDST BIT(5) 541 #define DPAA2_ETH_DIST_IPPROTO BIT(6) 542 #define DPAA2_ETH_DIST_L4SRC BIT(7) 543 #define DPAA2_ETH_DIST_L4DST BIT(8) 544 #define DPAA2_ETH_DIST_ALL (~0ULL) 545 546 #define DPNI_PAUSE_VER_MAJOR 7 547 #define DPNI_PAUSE_VER_MINOR 13 548 #define dpaa2_eth_has_pause_support(priv) \ 549 (dpaa2_eth_cmp_dpni_ver((priv), DPNI_PAUSE_VER_MAJOR, \ 550 DPNI_PAUSE_VER_MINOR) >= 0) 551 552 static inline bool dpaa2_eth_tx_pause_enabled(u64 link_options) 553 { 554 return !!(link_options & DPNI_LINK_OPT_PAUSE) ^ 555 !!(link_options & DPNI_LINK_OPT_ASYM_PAUSE); 556 } 557 558 static inline bool dpaa2_eth_rx_pause_enabled(u64 link_options) 559 { 560 return !!(link_options & DPNI_LINK_OPT_PAUSE); 561 } 562 563 static inline 564 unsigned int dpaa2_eth_needed_headroom(struct dpaa2_eth_priv *priv, 565 struct sk_buff *skb) 566 { 567 unsigned int headroom = DPAA2_ETH_SWA_SIZE; 568 569 /* If we don't have an skb (e.g. XDP buffer), we only need space for 570 * the software annotation area 571 */ 572 if (!skb) 573 return headroom; 574 575 /* For non-linear skbs we have no headroom requirement, as we build a 576 * SG frame with a newly allocated SGT buffer 577 */ 578 if (skb_is_nonlinear(skb)) 579 return 0; 580 581 /* If we have Tx timestamping, need 128B hardware annotation */ 582 if (priv->tx_tstamp && skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) 583 headroom += DPAA2_ETH_TX_HWA_SIZE; 584 585 return headroom; 586 } 587 588 /* Extra headroom space requested to hardware, in order to make sure there's 589 * no realloc'ing in forwarding scenarios 590 */ 591 static inline unsigned int dpaa2_eth_rx_head_room(struct dpaa2_eth_priv *priv) 592 { 593 return priv->tx_data_offset - DPAA2_ETH_RX_HWA_SIZE; 594 } 595 596 int dpaa2_eth_set_hash(struct net_device *net_dev, u64 flags); 597 int dpaa2_eth_set_cls(struct net_device *net_dev, u64 key); 598 int dpaa2_eth_cls_key_size(u64 key); 599 int dpaa2_eth_cls_fld_off(int prot, int field); 600 void dpaa2_eth_cls_trim_rule(void *key_mem, u64 fields); 601 602 void dpaa2_eth_set_rx_taildrop(struct dpaa2_eth_priv *priv, 603 bool tx_pause, bool pfc); 604 605 extern const struct dcbnl_rtnl_ops dpaa2_eth_dcbnl_ops; 606 607 #endif /* __DPAA2_H */ 608