1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ 2 /* Copyright 2014-2016 Freescale Semiconductor Inc. 3 * Copyright 2016-2020 NXP 4 */ 5 6 #ifndef __DPAA2_ETH_H 7 #define __DPAA2_ETH_H 8 9 #include <linux/dcbnl.h> 10 #include <linux/netdevice.h> 11 #include <linux/if_vlan.h> 12 #include <linux/fsl/mc.h> 13 14 #include <soc/fsl/dpaa2-io.h> 15 #include <soc/fsl/dpaa2-fd.h> 16 #include "dpni.h" 17 #include "dpni-cmd.h" 18 19 #include "dpaa2-eth-trace.h" 20 #include "dpaa2-eth-debugfs.h" 21 #include "dpaa2-mac.h" 22 23 #define DPAA2_WRIOP_VERSION(x, y, z) ((x) << 10 | (y) << 5 | (z) << 0) 24 25 #define DPAA2_ETH_STORE_SIZE 16 26 27 /* Maximum number of scatter-gather entries in an ingress frame, 28 * considering the maximum receive frame size is 64K 29 */ 30 #define DPAA2_ETH_MAX_SG_ENTRIES ((64 * 1024) / DPAA2_ETH_RX_BUF_SIZE) 31 32 /* Maximum acceptable MTU value. It is in direct relation with the hardware 33 * enforced Max Frame Length (currently 10k). 34 */ 35 #define DPAA2_ETH_MFL (10 * 1024) 36 #define DPAA2_ETH_MAX_MTU (DPAA2_ETH_MFL - VLAN_ETH_HLEN) 37 /* Convert L3 MTU to L2 MFL */ 38 #define DPAA2_ETH_L2_MAX_FRM(mtu) ((mtu) + VLAN_ETH_HLEN) 39 40 /* Set the taildrop threshold (in bytes) to allow the enqueue of a large 41 * enough number of jumbo frames in the Rx queues (length of the current 42 * frame is not taken into account when making the taildrop decision) 43 */ 44 #define DPAA2_ETH_FQ_TAILDROP_THRESH (1024 * 1024) 45 46 /* Maximum number of Tx confirmation frames to be processed 47 * in a single NAPI call 48 */ 49 #define DPAA2_ETH_TXCONF_PER_NAPI 256 50 51 /* Buffer qouta per channel. We want to keep in check number of ingress frames 52 * in flight: for small sized frames, congestion group taildrop may kick in 53 * first; for large sizes, Rx FQ taildrop threshold will ensure only a 54 * reasonable number of frames will be pending at any given time. 55 * Ingress frame drop due to buffer pool depletion should be a corner case only 56 */ 57 #define DPAA2_ETH_NUM_BUFS 1280 58 #define DPAA2_ETH_REFILL_THRESH \ 59 (DPAA2_ETH_NUM_BUFS - DPAA2_ETH_BUFS_PER_CMD) 60 61 /* Congestion group taildrop threshold: number of frames allowed to accumulate 62 * at any moment in a group of Rx queues belonging to the same traffic class. 63 * Choose value such that we don't risk depleting the buffer pool before the 64 * taildrop kicks in 65 */ 66 #define DPAA2_ETH_CG_TAILDROP_THRESH(priv) \ 67 (1024 * dpaa2_eth_queue_count(priv) / dpaa2_eth_tc_count(priv)) 68 69 /* Congestion group notification threshold: when this many frames accumulate 70 * on the Rx queues belonging to the same TC, the MAC is instructed to send 71 * PFC frames for that TC. 72 * When number of pending frames drops below exit threshold transmission of 73 * PFC frames is stopped. 74 */ 75 #define DPAA2_ETH_CN_THRESH_ENTRY(priv) \ 76 (DPAA2_ETH_CG_TAILDROP_THRESH(priv) / 2) 77 #define DPAA2_ETH_CN_THRESH_EXIT(priv) \ 78 (DPAA2_ETH_CN_THRESH_ENTRY(priv) * 3 / 4) 79 80 /* Maximum number of buffers that can be acquired/released through a single 81 * QBMan command 82 */ 83 #define DPAA2_ETH_BUFS_PER_CMD 7 84 85 /* Hardware requires alignment for ingress/egress buffer addresses */ 86 #define DPAA2_ETH_TX_BUF_ALIGN 64 87 88 #define DPAA2_ETH_RX_BUF_RAW_SIZE PAGE_SIZE 89 #define DPAA2_ETH_RX_BUF_TAILROOM \ 90 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) 91 #define DPAA2_ETH_RX_BUF_SIZE \ 92 (DPAA2_ETH_RX_BUF_RAW_SIZE - DPAA2_ETH_RX_BUF_TAILROOM) 93 94 /* Hardware annotation area in RX/TX buffers */ 95 #define DPAA2_ETH_RX_HWA_SIZE 64 96 #define DPAA2_ETH_TX_HWA_SIZE 128 97 98 /* PTP nominal frequency 1GHz */ 99 #define DPAA2_PTP_CLK_PERIOD_NS 1 100 101 /* Due to a limitation in WRIOP 1.0.0, the RX buffer data must be aligned 102 * to 256B. For newer revisions, the requirement is only for 64B alignment 103 */ 104 #define DPAA2_ETH_RX_BUF_ALIGN_REV1 256 105 #define DPAA2_ETH_RX_BUF_ALIGN 64 106 107 /* We are accommodating a skb backpointer and some S/G info 108 * in the frame's software annotation. The hardware 109 * options are either 0 or 64, so we choose the latter. 110 */ 111 #define DPAA2_ETH_SWA_SIZE 64 112 113 /* We store different information in the software annotation area of a Tx frame 114 * based on what type of frame it is 115 */ 116 enum dpaa2_eth_swa_type { 117 DPAA2_ETH_SWA_SINGLE, 118 DPAA2_ETH_SWA_SG, 119 DPAA2_ETH_SWA_XDP, 120 }; 121 122 /* Must keep this struct smaller than DPAA2_ETH_SWA_SIZE */ 123 struct dpaa2_eth_swa { 124 enum dpaa2_eth_swa_type type; 125 union { 126 struct { 127 struct sk_buff *skb; 128 } single; 129 struct { 130 struct sk_buff *skb; 131 struct scatterlist *scl; 132 int num_sg; 133 int sgt_size; 134 } sg; 135 struct { 136 int dma_size; 137 struct xdp_frame *xdpf; 138 } xdp; 139 }; 140 }; 141 142 /* Annotation valid bits in FD FRC */ 143 #define DPAA2_FD_FRC_FASV 0x8000 144 #define DPAA2_FD_FRC_FAEADV 0x4000 145 #define DPAA2_FD_FRC_FAPRV 0x2000 146 #define DPAA2_FD_FRC_FAIADV 0x1000 147 #define DPAA2_FD_FRC_FASWOV 0x0800 148 #define DPAA2_FD_FRC_FAICFDV 0x0400 149 150 /* Error bits in FD CTRL */ 151 #define DPAA2_FD_RX_ERR_MASK (FD_CTRL_SBE | FD_CTRL_FAERR) 152 #define DPAA2_FD_TX_ERR_MASK (FD_CTRL_UFD | \ 153 FD_CTRL_SBE | \ 154 FD_CTRL_FSE | \ 155 FD_CTRL_FAERR) 156 157 /* Annotation bits in FD CTRL */ 158 #define DPAA2_FD_CTRL_ASAL 0x00020000 /* ASAL = 128B */ 159 160 /* Frame annotation status */ 161 struct dpaa2_fas { 162 u8 reserved; 163 u8 ppid; 164 __le16 ifpid; 165 __le32 status; 166 }; 167 168 /* Frame annotation status word is located in the first 8 bytes 169 * of the buffer's hardware annoatation area 170 */ 171 #define DPAA2_FAS_OFFSET 0 172 #define DPAA2_FAS_SIZE (sizeof(struct dpaa2_fas)) 173 174 /* Timestamp is located in the next 8 bytes of the buffer's 175 * hardware annotation area 176 */ 177 #define DPAA2_TS_OFFSET 0x8 178 179 /* Frame annotation egress action descriptor */ 180 #define DPAA2_FAEAD_OFFSET 0x58 181 182 struct dpaa2_faead { 183 __le32 conf_fqid; 184 __le32 ctrl; 185 }; 186 187 #define DPAA2_FAEAD_A2V 0x20000000 188 #define DPAA2_FAEAD_A4V 0x08000000 189 #define DPAA2_FAEAD_UPDV 0x00001000 190 #define DPAA2_FAEAD_EBDDV 0x00002000 191 #define DPAA2_FAEAD_UPD 0x00000010 192 193 /* Accessors for the hardware annotation fields that we use */ 194 static inline void *dpaa2_get_hwa(void *buf_addr, bool swa) 195 { 196 return buf_addr + (swa ? DPAA2_ETH_SWA_SIZE : 0); 197 } 198 199 static inline struct dpaa2_fas *dpaa2_get_fas(void *buf_addr, bool swa) 200 { 201 return dpaa2_get_hwa(buf_addr, swa) + DPAA2_FAS_OFFSET; 202 } 203 204 static inline __le64 *dpaa2_get_ts(void *buf_addr, bool swa) 205 { 206 return dpaa2_get_hwa(buf_addr, swa) + DPAA2_TS_OFFSET; 207 } 208 209 static inline struct dpaa2_faead *dpaa2_get_faead(void *buf_addr, bool swa) 210 { 211 return dpaa2_get_hwa(buf_addr, swa) + DPAA2_FAEAD_OFFSET; 212 } 213 214 /* Error and status bits in the frame annotation status word */ 215 /* Debug frame, otherwise supposed to be discarded */ 216 #define DPAA2_FAS_DISC 0x80000000 217 /* MACSEC frame */ 218 #define DPAA2_FAS_MS 0x40000000 219 #define DPAA2_FAS_PTP 0x08000000 220 /* Ethernet multicast frame */ 221 #define DPAA2_FAS_MC 0x04000000 222 /* Ethernet broadcast frame */ 223 #define DPAA2_FAS_BC 0x02000000 224 #define DPAA2_FAS_KSE 0x00040000 225 #define DPAA2_FAS_EOFHE 0x00020000 226 #define DPAA2_FAS_MNLE 0x00010000 227 #define DPAA2_FAS_TIDE 0x00008000 228 #define DPAA2_FAS_PIEE 0x00004000 229 /* Frame length error */ 230 #define DPAA2_FAS_FLE 0x00002000 231 /* Frame physical error */ 232 #define DPAA2_FAS_FPE 0x00001000 233 #define DPAA2_FAS_PTE 0x00000080 234 #define DPAA2_FAS_ISP 0x00000040 235 #define DPAA2_FAS_PHE 0x00000020 236 #define DPAA2_FAS_BLE 0x00000010 237 /* L3 csum validation performed */ 238 #define DPAA2_FAS_L3CV 0x00000008 239 /* L3 csum error */ 240 #define DPAA2_FAS_L3CE 0x00000004 241 /* L4 csum validation performed */ 242 #define DPAA2_FAS_L4CV 0x00000002 243 /* L4 csum error */ 244 #define DPAA2_FAS_L4CE 0x00000001 245 /* Possible errors on the ingress path */ 246 #define DPAA2_FAS_RX_ERR_MASK (DPAA2_FAS_KSE | \ 247 DPAA2_FAS_EOFHE | \ 248 DPAA2_FAS_MNLE | \ 249 DPAA2_FAS_TIDE | \ 250 DPAA2_FAS_PIEE | \ 251 DPAA2_FAS_FLE | \ 252 DPAA2_FAS_FPE | \ 253 DPAA2_FAS_PTE | \ 254 DPAA2_FAS_ISP | \ 255 DPAA2_FAS_PHE | \ 256 DPAA2_FAS_BLE | \ 257 DPAA2_FAS_L3CE | \ 258 DPAA2_FAS_L4CE) 259 260 /* Time in milliseconds between link state updates */ 261 #define DPAA2_ETH_LINK_STATE_REFRESH 1000 262 263 /* Number of times to retry a frame enqueue before giving up. 264 * Value determined empirically, in order to minimize the number 265 * of frames dropped on Tx 266 */ 267 #define DPAA2_ETH_ENQUEUE_RETRIES 10 268 269 /* Number of times to retry DPIO portal operations while waiting 270 * for portal to finish executing current command and become 271 * available. We want to avoid being stuck in a while loop in case 272 * hardware becomes unresponsive, but not give up too easily if 273 * the portal really is busy for valid reasons 274 */ 275 #define DPAA2_ETH_SWP_BUSY_RETRIES 1000 276 277 /* Driver statistics, other than those in struct rtnl_link_stats64. 278 * These are usually collected per-CPU and aggregated by ethtool. 279 */ 280 struct dpaa2_eth_drv_stats { 281 __u64 tx_conf_frames; 282 __u64 tx_conf_bytes; 283 __u64 tx_sg_frames; 284 __u64 tx_sg_bytes; 285 __u64 tx_reallocs; 286 __u64 rx_sg_frames; 287 __u64 rx_sg_bytes; 288 /* Enqueues retried due to portal busy */ 289 __u64 tx_portal_busy; 290 }; 291 292 /* Per-FQ statistics */ 293 struct dpaa2_eth_fq_stats { 294 /* Number of frames received on this queue */ 295 __u64 frames; 296 }; 297 298 /* Per-channel statistics */ 299 struct dpaa2_eth_ch_stats { 300 /* Volatile dequeues retried due to portal busy */ 301 __u64 dequeue_portal_busy; 302 /* Pull errors */ 303 __u64 pull_err; 304 /* Number of CDANs; useful to estimate avg NAPI len */ 305 __u64 cdan; 306 /* XDP counters */ 307 __u64 xdp_drop; 308 __u64 xdp_tx; 309 __u64 xdp_tx_err; 310 __u64 xdp_redirect; 311 /* Must be last, does not show up in ethtool stats */ 312 __u64 frames; 313 }; 314 315 /* Maximum number of queues associated with a DPNI */ 316 #define DPAA2_ETH_MAX_TCS 8 317 #define DPAA2_ETH_MAX_RX_QUEUES_PER_TC 16 318 #define DPAA2_ETH_MAX_RX_QUEUES \ 319 (DPAA2_ETH_MAX_RX_QUEUES_PER_TC * DPAA2_ETH_MAX_TCS) 320 #define DPAA2_ETH_MAX_TX_QUEUES 16 321 #define DPAA2_ETH_MAX_QUEUES (DPAA2_ETH_MAX_RX_QUEUES + \ 322 DPAA2_ETH_MAX_TX_QUEUES) 323 #define DPAA2_ETH_MAX_NETDEV_QUEUES \ 324 (DPAA2_ETH_MAX_TX_QUEUES * DPAA2_ETH_MAX_TCS) 325 326 #define DPAA2_ETH_MAX_DPCONS 16 327 328 enum dpaa2_eth_fq_type { 329 DPAA2_RX_FQ = 0, 330 DPAA2_TX_CONF_FQ, 331 }; 332 333 struct dpaa2_eth_priv; 334 335 struct dpaa2_eth_xdp_fds { 336 struct dpaa2_fd fds[DEV_MAP_BULK_SIZE]; 337 ssize_t num; 338 }; 339 340 struct dpaa2_eth_fq { 341 u32 fqid; 342 u32 tx_qdbin; 343 u32 tx_fqid[DPAA2_ETH_MAX_TCS]; 344 u16 flowid; 345 u8 tc; 346 int target_cpu; 347 u32 dq_frames; 348 u32 dq_bytes; 349 struct dpaa2_eth_channel *channel; 350 enum dpaa2_eth_fq_type type; 351 352 void (*consume)(struct dpaa2_eth_priv *priv, 353 struct dpaa2_eth_channel *ch, 354 const struct dpaa2_fd *fd, 355 struct dpaa2_eth_fq *fq); 356 struct dpaa2_eth_fq_stats stats; 357 358 struct dpaa2_eth_xdp_fds xdp_redirect_fds; 359 struct dpaa2_eth_xdp_fds xdp_tx_fds; 360 }; 361 362 struct dpaa2_eth_ch_xdp { 363 struct bpf_prog *prog; 364 u64 drop_bufs[DPAA2_ETH_BUFS_PER_CMD]; 365 int drop_cnt; 366 unsigned int res; 367 }; 368 369 struct dpaa2_eth_channel { 370 struct dpaa2_io_notification_ctx nctx; 371 struct fsl_mc_device *dpcon; 372 int dpcon_id; 373 int ch_id; 374 struct napi_struct napi; 375 struct dpaa2_io *dpio; 376 struct dpaa2_io_store *store; 377 struct dpaa2_eth_priv *priv; 378 int buf_count; 379 struct dpaa2_eth_ch_stats stats; 380 struct dpaa2_eth_ch_xdp xdp; 381 struct xdp_rxq_info xdp_rxq; 382 struct list_head *rx_list; 383 }; 384 385 struct dpaa2_eth_dist_fields { 386 u64 rxnfc_field; 387 enum net_prot cls_prot; 388 int cls_field; 389 int size; 390 u64 id; 391 }; 392 393 struct dpaa2_eth_cls_rule { 394 struct ethtool_rx_flow_spec fs; 395 u8 in_use; 396 }; 397 398 /* Driver private data */ 399 struct dpaa2_eth_priv { 400 struct net_device *net_dev; 401 402 u8 num_fqs; 403 struct dpaa2_eth_fq fq[DPAA2_ETH_MAX_QUEUES]; 404 int (*enqueue)(struct dpaa2_eth_priv *priv, 405 struct dpaa2_eth_fq *fq, 406 struct dpaa2_fd *fd, u8 prio, 407 u32 num_frames, 408 int *frames_enqueued); 409 410 u8 num_channels; 411 struct dpaa2_eth_channel *channel[DPAA2_ETH_MAX_DPCONS]; 412 413 struct dpni_attr dpni_attrs; 414 u16 dpni_ver_major; 415 u16 dpni_ver_minor; 416 u16 tx_data_offset; 417 418 struct fsl_mc_device *dpbp_dev; 419 u16 rx_buf_size; 420 u16 bpid; 421 struct iommu_domain *iommu_domain; 422 423 bool tx_tstamp; /* Tx timestamping enabled */ 424 bool rx_tstamp; /* Rx timestamping enabled */ 425 426 u16 tx_qdid; 427 struct fsl_mc_io *mc_io; 428 /* Cores which have an affine DPIO/DPCON. 429 * This is the cpu set on which Rx and Tx conf frames are processed 430 */ 431 struct cpumask dpio_cpumask; 432 433 /* Standard statistics */ 434 struct rtnl_link_stats64 __percpu *percpu_stats; 435 /* Extra stats, in addition to the ones known by the kernel */ 436 struct dpaa2_eth_drv_stats __percpu *percpu_extras; 437 438 u16 mc_token; 439 u8 rx_fqtd_enabled; 440 u8 rx_cgtd_enabled; 441 442 struct dpni_link_state link_state; 443 bool do_link_poll; 444 struct task_struct *poll_thread; 445 446 /* enabled ethtool hashing bits */ 447 u64 rx_hash_fields; 448 u64 rx_cls_fields; 449 struct dpaa2_eth_cls_rule *cls_rules; 450 u8 rx_cls_enabled; 451 u8 vlan_cls_enabled; 452 u8 pfc_enabled; 453 #ifdef CONFIG_FSL_DPAA2_ETH_DCB 454 u8 dcbx_mode; 455 struct ieee_pfc pfc; 456 #endif 457 struct bpf_prog *xdp_prog; 458 #ifdef CONFIG_DEBUG_FS 459 struct dpaa2_debugfs dbg; 460 #endif 461 462 struct dpaa2_mac *mac; 463 }; 464 465 #define DPAA2_RXH_SUPPORTED (RXH_L2DA | RXH_VLAN | RXH_L3_PROTO \ 466 | RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 \ 467 | RXH_L4_B_2_3) 468 469 /* default Rx hash options, set during probing */ 470 #define DPAA2_RXH_DEFAULT (RXH_L3_PROTO | RXH_IP_SRC | RXH_IP_DST | \ 471 RXH_L4_B_0_1 | RXH_L4_B_2_3) 472 473 #define dpaa2_eth_hash_enabled(priv) \ 474 ((priv)->dpni_attrs.num_queues > 1) 475 476 /* Required by struct dpni_rx_tc_dist_cfg::key_cfg_iova */ 477 #define DPAA2_CLASSIFIER_DMA_SIZE 256 478 479 extern const struct ethtool_ops dpaa2_ethtool_ops; 480 extern int dpaa2_phc_index; 481 482 static inline int dpaa2_eth_cmp_dpni_ver(struct dpaa2_eth_priv *priv, 483 u16 ver_major, u16 ver_minor) 484 { 485 if (priv->dpni_ver_major == ver_major) 486 return priv->dpni_ver_minor - ver_minor; 487 return priv->dpni_ver_major - ver_major; 488 } 489 490 /* Minimum firmware version that supports a more flexible API 491 * for configuring the Rx flow hash key 492 */ 493 #define DPNI_RX_DIST_KEY_VER_MAJOR 7 494 #define DPNI_RX_DIST_KEY_VER_MINOR 5 495 496 #define dpaa2_eth_has_legacy_dist(priv) \ 497 (dpaa2_eth_cmp_dpni_ver((priv), DPNI_RX_DIST_KEY_VER_MAJOR, \ 498 DPNI_RX_DIST_KEY_VER_MINOR) < 0) 499 500 #define dpaa2_eth_fs_enabled(priv) \ 501 (!((priv)->dpni_attrs.options & DPNI_OPT_NO_FS)) 502 503 #define dpaa2_eth_fs_mask_enabled(priv) \ 504 ((priv)->dpni_attrs.options & DPNI_OPT_HAS_KEY_MASKING) 505 506 #define dpaa2_eth_fs_count(priv) \ 507 ((priv)->dpni_attrs.fs_entries) 508 509 #define dpaa2_eth_tc_count(priv) \ 510 ((priv)->dpni_attrs.num_tcs) 511 512 /* We have exactly one {Rx, Tx conf} queue per channel */ 513 #define dpaa2_eth_queue_count(priv) \ 514 ((priv)->num_channels) 515 516 enum dpaa2_eth_rx_dist { 517 DPAA2_ETH_RX_DIST_HASH, 518 DPAA2_ETH_RX_DIST_CLS 519 }; 520 521 /* Unique IDs for the supported Rx classification header fields */ 522 #define DPAA2_ETH_DIST_ETHDST BIT(0) 523 #define DPAA2_ETH_DIST_ETHSRC BIT(1) 524 #define DPAA2_ETH_DIST_ETHTYPE BIT(2) 525 #define DPAA2_ETH_DIST_VLAN BIT(3) 526 #define DPAA2_ETH_DIST_IPSRC BIT(4) 527 #define DPAA2_ETH_DIST_IPDST BIT(5) 528 #define DPAA2_ETH_DIST_IPPROTO BIT(6) 529 #define DPAA2_ETH_DIST_L4SRC BIT(7) 530 #define DPAA2_ETH_DIST_L4DST BIT(8) 531 #define DPAA2_ETH_DIST_ALL (~0ULL) 532 533 #define DPNI_PAUSE_VER_MAJOR 7 534 #define DPNI_PAUSE_VER_MINOR 13 535 #define dpaa2_eth_has_pause_support(priv) \ 536 (dpaa2_eth_cmp_dpni_ver((priv), DPNI_PAUSE_VER_MAJOR, \ 537 DPNI_PAUSE_VER_MINOR) >= 0) 538 539 static inline bool dpaa2_eth_tx_pause_enabled(u64 link_options) 540 { 541 return !!(link_options & DPNI_LINK_OPT_PAUSE) ^ 542 !!(link_options & DPNI_LINK_OPT_ASYM_PAUSE); 543 } 544 545 static inline bool dpaa2_eth_rx_pause_enabled(u64 link_options) 546 { 547 return !!(link_options & DPNI_LINK_OPT_PAUSE); 548 } 549 550 static inline 551 unsigned int dpaa2_eth_needed_headroom(struct dpaa2_eth_priv *priv, 552 struct sk_buff *skb) 553 { 554 unsigned int headroom = DPAA2_ETH_SWA_SIZE; 555 556 /* If we don't have an skb (e.g. XDP buffer), we only need space for 557 * the software annotation area 558 */ 559 if (!skb) 560 return headroom; 561 562 /* For non-linear skbs we have no headroom requirement, as we build a 563 * SG frame with a newly allocated SGT buffer 564 */ 565 if (skb_is_nonlinear(skb)) 566 return 0; 567 568 /* If we have Tx timestamping, need 128B hardware annotation */ 569 if (priv->tx_tstamp && skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) 570 headroom += DPAA2_ETH_TX_HWA_SIZE; 571 572 return headroom; 573 } 574 575 /* Extra headroom space requested to hardware, in order to make sure there's 576 * no realloc'ing in forwarding scenarios 577 */ 578 static inline unsigned int dpaa2_eth_rx_head_room(struct dpaa2_eth_priv *priv) 579 { 580 return priv->tx_data_offset - DPAA2_ETH_RX_HWA_SIZE; 581 } 582 583 int dpaa2_eth_set_hash(struct net_device *net_dev, u64 flags); 584 int dpaa2_eth_set_cls(struct net_device *net_dev, u64 key); 585 int dpaa2_eth_cls_key_size(u64 key); 586 int dpaa2_eth_cls_fld_off(int prot, int field); 587 void dpaa2_eth_cls_trim_rule(void *key_mem, u64 fields); 588 589 void dpaa2_eth_set_rx_taildrop(struct dpaa2_eth_priv *priv, 590 bool tx_pause, bool pfc); 591 592 extern const struct dcbnl_rtnl_ops dpaa2_eth_dcbnl_ops; 593 594 #endif /* __DPAA2_H */ 595