1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2 /* Copyright 2014-2016 Freescale Semiconductor Inc.
3  * Copyright 2016-2022 NXP
4  */
5 #include <linux/init.h>
6 #include <linux/module.h>
7 #include <linux/platform_device.h>
8 #include <linux/etherdevice.h>
9 #include <linux/of_net.h>
10 #include <linux/interrupt.h>
11 #include <linux/kthread.h>
12 #include <linux/iommu.h>
13 #include <linux/fsl/mc.h>
14 #include <linux/bpf.h>
15 #include <linux/bpf_trace.h>
16 #include <linux/fsl/ptp_qoriq.h>
17 #include <linux/ptp_classify.h>
18 #include <net/pkt_cls.h>
19 #include <net/sock.h>
20 #include <net/tso.h>
21 #include <net/xdp_sock_drv.h>
22 
23 #include "dpaa2-eth.h"
24 
25 /* CREATE_TRACE_POINTS only needs to be defined once. Other dpa files
26  * using trace events only need to #include <trace/events/sched.h>
27  */
28 #define CREATE_TRACE_POINTS
29 #include "dpaa2-eth-trace.h"
30 
31 MODULE_LICENSE("Dual BSD/GPL");
32 MODULE_AUTHOR("Freescale Semiconductor, Inc");
33 MODULE_DESCRIPTION("Freescale DPAA2 Ethernet Driver");
34 
35 struct ptp_qoriq *dpaa2_ptp;
36 EXPORT_SYMBOL(dpaa2_ptp);
37 
38 static void dpaa2_eth_detect_features(struct dpaa2_eth_priv *priv)
39 {
40 	priv->features = 0;
41 
42 	if (dpaa2_eth_cmp_dpni_ver(priv, DPNI_PTP_ONESTEP_VER_MAJOR,
43 				   DPNI_PTP_ONESTEP_VER_MINOR) >= 0)
44 		priv->features |= DPAA2_ETH_FEATURE_ONESTEP_CFG_DIRECT;
45 }
46 
47 static void dpaa2_update_ptp_onestep_indirect(struct dpaa2_eth_priv *priv,
48 					      u32 offset, u8 udp)
49 {
50 	struct dpni_single_step_cfg cfg;
51 
52 	cfg.en = 1;
53 	cfg.ch_update = udp;
54 	cfg.offset = offset;
55 	cfg.peer_delay = 0;
56 
57 	if (dpni_set_single_step_cfg(priv->mc_io, 0, priv->mc_token, &cfg))
58 		WARN_ONCE(1, "Failed to set single step register");
59 }
60 
61 static void dpaa2_update_ptp_onestep_direct(struct dpaa2_eth_priv *priv,
62 					    u32 offset, u8 udp)
63 {
64 	u32 val = 0;
65 
66 	val = DPAA2_PTP_SINGLE_STEP_ENABLE |
67 	       DPAA2_PTP_SINGLE_CORRECTION_OFF(offset);
68 
69 	if (udp)
70 		val |= DPAA2_PTP_SINGLE_STEP_CH;
71 
72 	if (priv->onestep_reg_base)
73 		writel(val, priv->onestep_reg_base);
74 }
75 
76 static void dpaa2_ptp_onestep_reg_update_method(struct dpaa2_eth_priv *priv)
77 {
78 	struct device *dev = priv->net_dev->dev.parent;
79 	struct dpni_single_step_cfg ptp_cfg;
80 
81 	priv->dpaa2_set_onestep_params_cb = dpaa2_update_ptp_onestep_indirect;
82 
83 	if (!(priv->features & DPAA2_ETH_FEATURE_ONESTEP_CFG_DIRECT))
84 		return;
85 
86 	if (dpni_get_single_step_cfg(priv->mc_io, 0,
87 				     priv->mc_token, &ptp_cfg)) {
88 		dev_err(dev, "dpni_get_single_step_cfg cannot retrieve onestep reg, falling back to indirect update\n");
89 		return;
90 	}
91 
92 	if (!ptp_cfg.ptp_onestep_reg_base) {
93 		dev_err(dev, "1588 onestep reg not available, falling back to indirect update\n");
94 		return;
95 	}
96 
97 	priv->onestep_reg_base = ioremap(ptp_cfg.ptp_onestep_reg_base,
98 					 sizeof(u32));
99 	if (!priv->onestep_reg_base) {
100 		dev_err(dev, "1588 onestep reg cannot be mapped, falling back to indirect update\n");
101 		return;
102 	}
103 
104 	priv->dpaa2_set_onestep_params_cb = dpaa2_update_ptp_onestep_direct;
105 }
106 
107 void *dpaa2_iova_to_virt(struct iommu_domain *domain,
108 			 dma_addr_t iova_addr)
109 {
110 	phys_addr_t phys_addr;
111 
112 	phys_addr = domain ? iommu_iova_to_phys(domain, iova_addr) : iova_addr;
113 
114 	return phys_to_virt(phys_addr);
115 }
116 
117 static void dpaa2_eth_validate_rx_csum(struct dpaa2_eth_priv *priv,
118 				       u32 fd_status,
119 				       struct sk_buff *skb)
120 {
121 	skb_checksum_none_assert(skb);
122 
123 	/* HW checksum validation is disabled, nothing to do here */
124 	if (!(priv->net_dev->features & NETIF_F_RXCSUM))
125 		return;
126 
127 	/* Read checksum validation bits */
128 	if (!((fd_status & DPAA2_FAS_L3CV) &&
129 	      (fd_status & DPAA2_FAS_L4CV)))
130 		return;
131 
132 	/* Inform the stack there's no need to compute L3/L4 csum anymore */
133 	skb->ip_summed = CHECKSUM_UNNECESSARY;
134 }
135 
136 /* Free a received FD.
137  * Not to be used for Tx conf FDs or on any other paths.
138  */
139 static void dpaa2_eth_free_rx_fd(struct dpaa2_eth_priv *priv,
140 				 const struct dpaa2_fd *fd,
141 				 void *vaddr)
142 {
143 	struct device *dev = priv->net_dev->dev.parent;
144 	dma_addr_t addr = dpaa2_fd_get_addr(fd);
145 	u8 fd_format = dpaa2_fd_get_format(fd);
146 	struct dpaa2_sg_entry *sgt;
147 	void *sg_vaddr;
148 	int i;
149 
150 	/* If single buffer frame, just free the data buffer */
151 	if (fd_format == dpaa2_fd_single)
152 		goto free_buf;
153 	else if (fd_format != dpaa2_fd_sg)
154 		/* We don't support any other format */
155 		return;
156 
157 	/* For S/G frames, we first need to free all SG entries
158 	 * except the first one, which was taken care of already
159 	 */
160 	sgt = vaddr + dpaa2_fd_get_offset(fd);
161 	for (i = 1; i < DPAA2_ETH_MAX_SG_ENTRIES; i++) {
162 		addr = dpaa2_sg_get_addr(&sgt[i]);
163 		sg_vaddr = dpaa2_iova_to_virt(priv->iommu_domain, addr);
164 		dma_unmap_page(dev, addr, priv->rx_buf_size,
165 			       DMA_BIDIRECTIONAL);
166 
167 		free_pages((unsigned long)sg_vaddr, 0);
168 		if (dpaa2_sg_is_final(&sgt[i]))
169 			break;
170 	}
171 
172 free_buf:
173 	free_pages((unsigned long)vaddr, 0);
174 }
175 
176 /* Build a linear skb based on a single-buffer frame descriptor */
177 static struct sk_buff *dpaa2_eth_build_linear_skb(struct dpaa2_eth_channel *ch,
178 						  const struct dpaa2_fd *fd,
179 						  void *fd_vaddr)
180 {
181 	struct sk_buff *skb = NULL;
182 	u16 fd_offset = dpaa2_fd_get_offset(fd);
183 	u32 fd_length = dpaa2_fd_get_len(fd);
184 
185 	ch->buf_count--;
186 
187 	skb = build_skb(fd_vaddr, DPAA2_ETH_RX_BUF_RAW_SIZE);
188 	if (unlikely(!skb))
189 		return NULL;
190 
191 	skb_reserve(skb, fd_offset);
192 	skb_put(skb, fd_length);
193 
194 	return skb;
195 }
196 
197 /* Build a non linear (fragmented) skb based on a S/G table */
198 static struct sk_buff *dpaa2_eth_build_frag_skb(struct dpaa2_eth_priv *priv,
199 						struct dpaa2_eth_channel *ch,
200 						struct dpaa2_sg_entry *sgt)
201 {
202 	struct sk_buff *skb = NULL;
203 	struct device *dev = priv->net_dev->dev.parent;
204 	void *sg_vaddr;
205 	dma_addr_t sg_addr;
206 	u16 sg_offset;
207 	u32 sg_length;
208 	struct page *page, *head_page;
209 	int page_offset;
210 	int i;
211 
212 	for (i = 0; i < DPAA2_ETH_MAX_SG_ENTRIES; i++) {
213 		struct dpaa2_sg_entry *sge = &sgt[i];
214 
215 		/* NOTE: We only support SG entries in dpaa2_sg_single format,
216 		 * but this is the only format we may receive from HW anyway
217 		 */
218 
219 		/* Get the address and length from the S/G entry */
220 		sg_addr = dpaa2_sg_get_addr(sge);
221 		sg_vaddr = dpaa2_iova_to_virt(priv->iommu_domain, sg_addr);
222 		dma_unmap_page(dev, sg_addr, priv->rx_buf_size,
223 			       DMA_BIDIRECTIONAL);
224 
225 		sg_length = dpaa2_sg_get_len(sge);
226 
227 		if (i == 0) {
228 			/* We build the skb around the first data buffer */
229 			skb = build_skb(sg_vaddr, DPAA2_ETH_RX_BUF_RAW_SIZE);
230 			if (unlikely(!skb)) {
231 				/* Free the first SG entry now, since we already
232 				 * unmapped it and obtained the virtual address
233 				 */
234 				free_pages((unsigned long)sg_vaddr, 0);
235 
236 				/* We still need to subtract the buffers used
237 				 * by this FD from our software counter
238 				 */
239 				while (!dpaa2_sg_is_final(&sgt[i]) &&
240 				       i < DPAA2_ETH_MAX_SG_ENTRIES)
241 					i++;
242 				break;
243 			}
244 
245 			sg_offset = dpaa2_sg_get_offset(sge);
246 			skb_reserve(skb, sg_offset);
247 			skb_put(skb, sg_length);
248 		} else {
249 			/* Rest of the data buffers are stored as skb frags */
250 			page = virt_to_page(sg_vaddr);
251 			head_page = virt_to_head_page(sg_vaddr);
252 
253 			/* Offset in page (which may be compound).
254 			 * Data in subsequent SG entries is stored from the
255 			 * beginning of the buffer, so we don't need to add the
256 			 * sg_offset.
257 			 */
258 			page_offset = ((unsigned long)sg_vaddr &
259 				(PAGE_SIZE - 1)) +
260 				(page_address(page) - page_address(head_page));
261 
262 			skb_add_rx_frag(skb, i - 1, head_page, page_offset,
263 					sg_length, priv->rx_buf_size);
264 		}
265 
266 		if (dpaa2_sg_is_final(sge))
267 			break;
268 	}
269 
270 	WARN_ONCE(i == DPAA2_ETH_MAX_SG_ENTRIES, "Final bit not set in SGT");
271 
272 	/* Count all data buffers + SG table buffer */
273 	ch->buf_count -= i + 2;
274 
275 	return skb;
276 }
277 
278 /* Free buffers acquired from the buffer pool or which were meant to
279  * be released in the pool
280  */
281 static void dpaa2_eth_free_bufs(struct dpaa2_eth_priv *priv, u64 *buf_array,
282 				int count, bool xsk_zc)
283 {
284 	struct device *dev = priv->net_dev->dev.parent;
285 	struct dpaa2_eth_swa *swa;
286 	struct xdp_buff *xdp_buff;
287 	void *vaddr;
288 	int i;
289 
290 	for (i = 0; i < count; i++) {
291 		vaddr = dpaa2_iova_to_virt(priv->iommu_domain, buf_array[i]);
292 
293 		if (!xsk_zc) {
294 			dma_unmap_page(dev, buf_array[i], priv->rx_buf_size,
295 				       DMA_BIDIRECTIONAL);
296 			free_pages((unsigned long)vaddr, 0);
297 		} else {
298 			swa = (struct dpaa2_eth_swa *)
299 				(vaddr + DPAA2_ETH_RX_HWA_SIZE);
300 			xdp_buff = swa->xsk.xdp_buff;
301 			xsk_buff_free(xdp_buff);
302 		}
303 	}
304 }
305 
306 void dpaa2_eth_recycle_buf(struct dpaa2_eth_priv *priv,
307 			   struct dpaa2_eth_channel *ch,
308 			   dma_addr_t addr)
309 {
310 	int retries = 0;
311 	int err;
312 
313 	ch->recycled_bufs[ch->recycled_bufs_cnt++] = addr;
314 	if (ch->recycled_bufs_cnt < DPAA2_ETH_BUFS_PER_CMD)
315 		return;
316 
317 	while ((err = dpaa2_io_service_release(ch->dpio, ch->bp->bpid,
318 					       ch->recycled_bufs,
319 					       ch->recycled_bufs_cnt)) == -EBUSY) {
320 		if (retries++ >= DPAA2_ETH_SWP_BUSY_RETRIES)
321 			break;
322 		cpu_relax();
323 	}
324 
325 	if (err) {
326 		dpaa2_eth_free_bufs(priv, ch->recycled_bufs,
327 				    ch->recycled_bufs_cnt, ch->xsk_zc);
328 		ch->buf_count -= ch->recycled_bufs_cnt;
329 	}
330 
331 	ch->recycled_bufs_cnt = 0;
332 }
333 
334 static int dpaa2_eth_xdp_flush(struct dpaa2_eth_priv *priv,
335 			       struct dpaa2_eth_fq *fq,
336 			       struct dpaa2_eth_xdp_fds *xdp_fds)
337 {
338 	int total_enqueued = 0, retries = 0, enqueued;
339 	struct dpaa2_eth_drv_stats *percpu_extras;
340 	int num_fds, err, max_retries;
341 	struct dpaa2_fd *fds;
342 
343 	percpu_extras = this_cpu_ptr(priv->percpu_extras);
344 
345 	/* try to enqueue all the FDs until the max number of retries is hit */
346 	fds = xdp_fds->fds;
347 	num_fds = xdp_fds->num;
348 	max_retries = num_fds * DPAA2_ETH_ENQUEUE_RETRIES;
349 	while (total_enqueued < num_fds && retries < max_retries) {
350 		err = priv->enqueue(priv, fq, &fds[total_enqueued],
351 				    0, num_fds - total_enqueued, &enqueued);
352 		if (err == -EBUSY) {
353 			percpu_extras->tx_portal_busy += ++retries;
354 			continue;
355 		}
356 		total_enqueued += enqueued;
357 	}
358 	xdp_fds->num = 0;
359 
360 	return total_enqueued;
361 }
362 
363 static void dpaa2_eth_xdp_tx_flush(struct dpaa2_eth_priv *priv,
364 				   struct dpaa2_eth_channel *ch,
365 				   struct dpaa2_eth_fq *fq)
366 {
367 	struct rtnl_link_stats64 *percpu_stats;
368 	struct dpaa2_fd *fds;
369 	int enqueued, i;
370 
371 	percpu_stats = this_cpu_ptr(priv->percpu_stats);
372 
373 	// enqueue the array of XDP_TX frames
374 	enqueued = dpaa2_eth_xdp_flush(priv, fq, &fq->xdp_tx_fds);
375 
376 	/* update statistics */
377 	percpu_stats->tx_packets += enqueued;
378 	fds = fq->xdp_tx_fds.fds;
379 	for (i = 0; i < enqueued; i++) {
380 		percpu_stats->tx_bytes += dpaa2_fd_get_len(&fds[i]);
381 		ch->stats.xdp_tx++;
382 	}
383 	for (i = enqueued; i < fq->xdp_tx_fds.num; i++) {
384 		dpaa2_eth_recycle_buf(priv, ch, dpaa2_fd_get_addr(&fds[i]));
385 		percpu_stats->tx_errors++;
386 		ch->stats.xdp_tx_err++;
387 	}
388 	fq->xdp_tx_fds.num = 0;
389 }
390 
391 void dpaa2_eth_xdp_enqueue(struct dpaa2_eth_priv *priv,
392 			   struct dpaa2_eth_channel *ch,
393 			   struct dpaa2_fd *fd,
394 			   void *buf_start, u16 queue_id)
395 {
396 	struct dpaa2_faead *faead;
397 	struct dpaa2_fd *dest_fd;
398 	struct dpaa2_eth_fq *fq;
399 	u32 ctrl, frc;
400 
401 	/* Mark the egress frame hardware annotation area as valid */
402 	frc = dpaa2_fd_get_frc(fd);
403 	dpaa2_fd_set_frc(fd, frc | DPAA2_FD_FRC_FAEADV);
404 	dpaa2_fd_set_ctrl(fd, DPAA2_FD_CTRL_ASAL);
405 
406 	/* Instruct hardware to release the FD buffer directly into
407 	 * the buffer pool once transmission is completed, instead of
408 	 * sending a Tx confirmation frame to us
409 	 */
410 	ctrl = DPAA2_FAEAD_A4V | DPAA2_FAEAD_A2V | DPAA2_FAEAD_EBDDV;
411 	faead = dpaa2_get_faead(buf_start, false);
412 	faead->ctrl = cpu_to_le32(ctrl);
413 	faead->conf_fqid = 0;
414 
415 	fq = &priv->fq[queue_id];
416 	dest_fd = &fq->xdp_tx_fds.fds[fq->xdp_tx_fds.num++];
417 	memcpy(dest_fd, fd, sizeof(*dest_fd));
418 
419 	if (fq->xdp_tx_fds.num < DEV_MAP_BULK_SIZE)
420 		return;
421 
422 	dpaa2_eth_xdp_tx_flush(priv, ch, fq);
423 }
424 
425 static u32 dpaa2_eth_run_xdp(struct dpaa2_eth_priv *priv,
426 			     struct dpaa2_eth_channel *ch,
427 			     struct dpaa2_eth_fq *rx_fq,
428 			     struct dpaa2_fd *fd, void *vaddr)
429 {
430 	dma_addr_t addr = dpaa2_fd_get_addr(fd);
431 	struct bpf_prog *xdp_prog;
432 	struct xdp_buff xdp;
433 	u32 xdp_act = XDP_PASS;
434 	int err, offset;
435 
436 	xdp_prog = READ_ONCE(ch->xdp.prog);
437 	if (!xdp_prog)
438 		goto out;
439 
440 	offset = dpaa2_fd_get_offset(fd) - XDP_PACKET_HEADROOM;
441 	xdp_init_buff(&xdp, DPAA2_ETH_RX_BUF_RAW_SIZE - offset, &ch->xdp_rxq);
442 	xdp_prepare_buff(&xdp, vaddr + offset, XDP_PACKET_HEADROOM,
443 			 dpaa2_fd_get_len(fd), false);
444 
445 	xdp_act = bpf_prog_run_xdp(xdp_prog, &xdp);
446 
447 	/* xdp.data pointer may have changed */
448 	dpaa2_fd_set_offset(fd, xdp.data - vaddr);
449 	dpaa2_fd_set_len(fd, xdp.data_end - xdp.data);
450 
451 	switch (xdp_act) {
452 	case XDP_PASS:
453 		break;
454 	case XDP_TX:
455 		dpaa2_eth_xdp_enqueue(priv, ch, fd, vaddr, rx_fq->flowid);
456 		break;
457 	default:
458 		bpf_warn_invalid_xdp_action(priv->net_dev, xdp_prog, xdp_act);
459 		fallthrough;
460 	case XDP_ABORTED:
461 		trace_xdp_exception(priv->net_dev, xdp_prog, xdp_act);
462 		fallthrough;
463 	case XDP_DROP:
464 		dpaa2_eth_recycle_buf(priv, ch, addr);
465 		ch->stats.xdp_drop++;
466 		break;
467 	case XDP_REDIRECT:
468 		dma_unmap_page(priv->net_dev->dev.parent, addr,
469 			       priv->rx_buf_size, DMA_BIDIRECTIONAL);
470 		ch->buf_count--;
471 
472 		/* Allow redirect use of full headroom */
473 		xdp.data_hard_start = vaddr;
474 		xdp.frame_sz = DPAA2_ETH_RX_BUF_RAW_SIZE;
475 
476 		err = xdp_do_redirect(priv->net_dev, &xdp, xdp_prog);
477 		if (unlikely(err)) {
478 			addr = dma_map_page(priv->net_dev->dev.parent,
479 					    virt_to_page(vaddr), 0,
480 					    priv->rx_buf_size, DMA_BIDIRECTIONAL);
481 			if (unlikely(dma_mapping_error(priv->net_dev->dev.parent, addr))) {
482 				free_pages((unsigned long)vaddr, 0);
483 			} else {
484 				ch->buf_count++;
485 				dpaa2_eth_recycle_buf(priv, ch, addr);
486 			}
487 			ch->stats.xdp_drop++;
488 		} else {
489 			ch->stats.xdp_redirect++;
490 		}
491 		break;
492 	}
493 
494 	ch->xdp.res |= xdp_act;
495 out:
496 	return xdp_act;
497 }
498 
499 struct sk_buff *dpaa2_eth_alloc_skb(struct dpaa2_eth_priv *priv,
500 				    struct dpaa2_eth_channel *ch,
501 				    const struct dpaa2_fd *fd, u32 fd_length,
502 				    void *fd_vaddr)
503 {
504 	u16 fd_offset = dpaa2_fd_get_offset(fd);
505 	struct sk_buff *skb = NULL;
506 	unsigned int skb_len;
507 
508 	skb_len = fd_length + dpaa2_eth_needed_headroom(NULL);
509 
510 	skb = napi_alloc_skb(&ch->napi, skb_len);
511 	if (!skb)
512 		return NULL;
513 
514 	skb_reserve(skb, dpaa2_eth_needed_headroom(NULL));
515 	skb_put(skb, fd_length);
516 
517 	memcpy(skb->data, fd_vaddr + fd_offset, fd_length);
518 
519 	dpaa2_eth_recycle_buf(priv, ch, dpaa2_fd_get_addr(fd));
520 
521 	return skb;
522 }
523 
524 static struct sk_buff *dpaa2_eth_copybreak(struct dpaa2_eth_channel *ch,
525 					   const struct dpaa2_fd *fd,
526 					   void *fd_vaddr)
527 {
528 	struct dpaa2_eth_priv *priv = ch->priv;
529 	u32 fd_length = dpaa2_fd_get_len(fd);
530 
531 	if (fd_length > priv->rx_copybreak)
532 		return NULL;
533 
534 	return dpaa2_eth_alloc_skb(priv, ch, fd, fd_length, fd_vaddr);
535 }
536 
537 void dpaa2_eth_receive_skb(struct dpaa2_eth_priv *priv,
538 			   struct dpaa2_eth_channel *ch,
539 			   const struct dpaa2_fd *fd, void *vaddr,
540 			   struct dpaa2_eth_fq *fq,
541 			   struct rtnl_link_stats64 *percpu_stats,
542 			   struct sk_buff *skb)
543 {
544 	struct dpaa2_fas *fas;
545 	u32 status = 0;
546 
547 	fas = dpaa2_get_fas(vaddr, false);
548 	prefetch(fas);
549 	prefetch(skb->data);
550 
551 	/* Get the timestamp value */
552 	if (priv->rx_tstamp) {
553 		struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
554 		__le64 *ts = dpaa2_get_ts(vaddr, false);
555 		u64 ns;
556 
557 		memset(shhwtstamps, 0, sizeof(*shhwtstamps));
558 
559 		ns = DPAA2_PTP_CLK_PERIOD_NS * le64_to_cpup(ts);
560 		shhwtstamps->hwtstamp = ns_to_ktime(ns);
561 	}
562 
563 	/* Check if we need to validate the L4 csum */
564 	if (likely(dpaa2_fd_get_frc(fd) & DPAA2_FD_FRC_FASV)) {
565 		status = le32_to_cpu(fas->status);
566 		dpaa2_eth_validate_rx_csum(priv, status, skb);
567 	}
568 
569 	skb->protocol = eth_type_trans(skb, priv->net_dev);
570 	skb_record_rx_queue(skb, fq->flowid);
571 
572 	percpu_stats->rx_packets++;
573 	percpu_stats->rx_bytes += dpaa2_fd_get_len(fd);
574 	ch->stats.bytes_per_cdan += dpaa2_fd_get_len(fd);
575 
576 	list_add_tail(&skb->list, ch->rx_list);
577 }
578 
579 /* Main Rx frame processing routine */
580 void dpaa2_eth_rx(struct dpaa2_eth_priv *priv,
581 		  struct dpaa2_eth_channel *ch,
582 		  const struct dpaa2_fd *fd,
583 		  struct dpaa2_eth_fq *fq)
584 {
585 	dma_addr_t addr = dpaa2_fd_get_addr(fd);
586 	u8 fd_format = dpaa2_fd_get_format(fd);
587 	void *vaddr;
588 	struct sk_buff *skb;
589 	struct rtnl_link_stats64 *percpu_stats;
590 	struct dpaa2_eth_drv_stats *percpu_extras;
591 	struct device *dev = priv->net_dev->dev.parent;
592 	void *buf_data;
593 	u32 xdp_act;
594 
595 	/* Tracing point */
596 	trace_dpaa2_rx_fd(priv->net_dev, fd);
597 
598 	vaddr = dpaa2_iova_to_virt(priv->iommu_domain, addr);
599 	dma_sync_single_for_cpu(dev, addr, priv->rx_buf_size,
600 				DMA_BIDIRECTIONAL);
601 
602 	buf_data = vaddr + dpaa2_fd_get_offset(fd);
603 	prefetch(buf_data);
604 
605 	percpu_stats = this_cpu_ptr(priv->percpu_stats);
606 	percpu_extras = this_cpu_ptr(priv->percpu_extras);
607 
608 	if (fd_format == dpaa2_fd_single) {
609 		xdp_act = dpaa2_eth_run_xdp(priv, ch, fq, (struct dpaa2_fd *)fd, vaddr);
610 		if (xdp_act != XDP_PASS) {
611 			percpu_stats->rx_packets++;
612 			percpu_stats->rx_bytes += dpaa2_fd_get_len(fd);
613 			return;
614 		}
615 
616 		skb = dpaa2_eth_copybreak(ch, fd, vaddr);
617 		if (!skb) {
618 			dma_unmap_page(dev, addr, priv->rx_buf_size,
619 				       DMA_BIDIRECTIONAL);
620 			skb = dpaa2_eth_build_linear_skb(ch, fd, vaddr);
621 		}
622 	} else if (fd_format == dpaa2_fd_sg) {
623 		WARN_ON(priv->xdp_prog);
624 
625 		dma_unmap_page(dev, addr, priv->rx_buf_size,
626 			       DMA_BIDIRECTIONAL);
627 		skb = dpaa2_eth_build_frag_skb(priv, ch, buf_data);
628 		free_pages((unsigned long)vaddr, 0);
629 		percpu_extras->rx_sg_frames++;
630 		percpu_extras->rx_sg_bytes += dpaa2_fd_get_len(fd);
631 	} else {
632 		/* We don't support any other format */
633 		goto err_frame_format;
634 	}
635 
636 	if (unlikely(!skb))
637 		goto err_build_skb;
638 
639 	dpaa2_eth_receive_skb(priv, ch, fd, vaddr, fq, percpu_stats, skb);
640 	return;
641 
642 err_build_skb:
643 	dpaa2_eth_free_rx_fd(priv, fd, vaddr);
644 err_frame_format:
645 	percpu_stats->rx_dropped++;
646 }
647 
648 /* Processing of Rx frames received on the error FQ
649  * We check and print the error bits and then free the frame
650  */
651 static void dpaa2_eth_rx_err(struct dpaa2_eth_priv *priv,
652 			     struct dpaa2_eth_channel *ch,
653 			     const struct dpaa2_fd *fd,
654 			     struct dpaa2_eth_fq *fq __always_unused)
655 {
656 	struct device *dev = priv->net_dev->dev.parent;
657 	dma_addr_t addr = dpaa2_fd_get_addr(fd);
658 	u8 fd_format = dpaa2_fd_get_format(fd);
659 	struct rtnl_link_stats64 *percpu_stats;
660 	struct dpaa2_eth_trap_item *trap_item;
661 	struct dpaa2_fapr *fapr;
662 	struct sk_buff *skb;
663 	void *buf_data;
664 	void *vaddr;
665 
666 	vaddr = dpaa2_iova_to_virt(priv->iommu_domain, addr);
667 	dma_sync_single_for_cpu(dev, addr, priv->rx_buf_size,
668 				DMA_BIDIRECTIONAL);
669 
670 	buf_data = vaddr + dpaa2_fd_get_offset(fd);
671 
672 	if (fd_format == dpaa2_fd_single) {
673 		dma_unmap_page(dev, addr, priv->rx_buf_size,
674 			       DMA_BIDIRECTIONAL);
675 		skb = dpaa2_eth_build_linear_skb(ch, fd, vaddr);
676 	} else if (fd_format == dpaa2_fd_sg) {
677 		dma_unmap_page(dev, addr, priv->rx_buf_size,
678 			       DMA_BIDIRECTIONAL);
679 		skb = dpaa2_eth_build_frag_skb(priv, ch, buf_data);
680 		free_pages((unsigned long)vaddr, 0);
681 	} else {
682 		/* We don't support any other format */
683 		dpaa2_eth_free_rx_fd(priv, fd, vaddr);
684 		goto err_frame_format;
685 	}
686 
687 	fapr = dpaa2_get_fapr(vaddr, false);
688 	trap_item = dpaa2_eth_dl_get_trap(priv, fapr);
689 	if (trap_item)
690 		devlink_trap_report(priv->devlink, skb, trap_item->trap_ctx,
691 				    &priv->devlink_port, NULL);
692 	consume_skb(skb);
693 
694 err_frame_format:
695 	percpu_stats = this_cpu_ptr(priv->percpu_stats);
696 	percpu_stats->rx_errors++;
697 	ch->buf_count--;
698 }
699 
700 /* Consume all frames pull-dequeued into the store. This is the simplest way to
701  * make sure we don't accidentally issue another volatile dequeue which would
702  * overwrite (leak) frames already in the store.
703  *
704  * Observance of NAPI budget is not our concern, leaving that to the caller.
705  */
706 static int dpaa2_eth_consume_frames(struct dpaa2_eth_channel *ch,
707 				    struct dpaa2_eth_fq **src)
708 {
709 	struct dpaa2_eth_priv *priv = ch->priv;
710 	struct dpaa2_eth_fq *fq = NULL;
711 	struct dpaa2_dq *dq;
712 	const struct dpaa2_fd *fd;
713 	int cleaned = 0, retries = 0;
714 	int is_last;
715 
716 	do {
717 		dq = dpaa2_io_store_next(ch->store, &is_last);
718 		if (unlikely(!dq)) {
719 			/* If we're here, we *must* have placed a
720 			 * volatile dequeue comnmand, so keep reading through
721 			 * the store until we get some sort of valid response
722 			 * token (either a valid frame or an "empty dequeue")
723 			 */
724 			if (retries++ >= DPAA2_ETH_SWP_BUSY_RETRIES) {
725 				netdev_err_once(priv->net_dev,
726 						"Unable to read a valid dequeue response\n");
727 				return -ETIMEDOUT;
728 			}
729 			continue;
730 		}
731 
732 		fd = dpaa2_dq_fd(dq);
733 		fq = (struct dpaa2_eth_fq *)(uintptr_t)dpaa2_dq_fqd_ctx(dq);
734 
735 		fq->consume(priv, ch, fd, fq);
736 		cleaned++;
737 		retries = 0;
738 	} while (!is_last);
739 
740 	if (!cleaned)
741 		return 0;
742 
743 	fq->stats.frames += cleaned;
744 	ch->stats.frames += cleaned;
745 	ch->stats.frames_per_cdan += cleaned;
746 
747 	/* A dequeue operation only pulls frames from a single queue
748 	 * into the store. Return the frame queue as an out param.
749 	 */
750 	if (src)
751 		*src = fq;
752 
753 	return cleaned;
754 }
755 
756 static int dpaa2_eth_ptp_parse(struct sk_buff *skb,
757 			       u8 *msgtype, u8 *twostep, u8 *udp,
758 			       u16 *correction_offset,
759 			       u16 *origintimestamp_offset)
760 {
761 	unsigned int ptp_class;
762 	struct ptp_header *hdr;
763 	unsigned int type;
764 	u8 *base;
765 
766 	ptp_class = ptp_classify_raw(skb);
767 	if (ptp_class == PTP_CLASS_NONE)
768 		return -EINVAL;
769 
770 	hdr = ptp_parse_header(skb, ptp_class);
771 	if (!hdr)
772 		return -EINVAL;
773 
774 	*msgtype = ptp_get_msgtype(hdr, ptp_class);
775 	*twostep = hdr->flag_field[0] & 0x2;
776 
777 	type = ptp_class & PTP_CLASS_PMASK;
778 	if (type == PTP_CLASS_IPV4 ||
779 	    type == PTP_CLASS_IPV6)
780 		*udp = 1;
781 	else
782 		*udp = 0;
783 
784 	base = skb_mac_header(skb);
785 	*correction_offset = (u8 *)&hdr->correction - base;
786 	*origintimestamp_offset = (u8 *)hdr + sizeof(struct ptp_header) - base;
787 
788 	return 0;
789 }
790 
791 /* Configure the egress frame annotation for timestamp update */
792 static void dpaa2_eth_enable_tx_tstamp(struct dpaa2_eth_priv *priv,
793 				       struct dpaa2_fd *fd,
794 				       void *buf_start,
795 				       struct sk_buff *skb)
796 {
797 	struct ptp_tstamp origin_timestamp;
798 	u8 msgtype, twostep, udp;
799 	struct dpaa2_faead *faead;
800 	struct dpaa2_fas *fas;
801 	struct timespec64 ts;
802 	u16 offset1, offset2;
803 	u32 ctrl, frc;
804 	__le64 *ns;
805 	u8 *data;
806 
807 	/* Mark the egress frame annotation area as valid */
808 	frc = dpaa2_fd_get_frc(fd);
809 	dpaa2_fd_set_frc(fd, frc | DPAA2_FD_FRC_FAEADV);
810 
811 	/* Set hardware annotation size */
812 	ctrl = dpaa2_fd_get_ctrl(fd);
813 	dpaa2_fd_set_ctrl(fd, ctrl | DPAA2_FD_CTRL_ASAL);
814 
815 	/* enable UPD (update prepanded data) bit in FAEAD field of
816 	 * hardware frame annotation area
817 	 */
818 	ctrl = DPAA2_FAEAD_A2V | DPAA2_FAEAD_UPDV | DPAA2_FAEAD_UPD;
819 	faead = dpaa2_get_faead(buf_start, true);
820 	faead->ctrl = cpu_to_le32(ctrl);
821 
822 	if (skb->cb[0] == TX_TSTAMP_ONESTEP_SYNC) {
823 		if (dpaa2_eth_ptp_parse(skb, &msgtype, &twostep, &udp,
824 					&offset1, &offset2) ||
825 		    msgtype != PTP_MSGTYPE_SYNC || twostep) {
826 			WARN_ONCE(1, "Bad packet for one-step timestamping\n");
827 			return;
828 		}
829 
830 		/* Mark the frame annotation status as valid */
831 		frc = dpaa2_fd_get_frc(fd);
832 		dpaa2_fd_set_frc(fd, frc | DPAA2_FD_FRC_FASV);
833 
834 		/* Mark the PTP flag for one step timestamping */
835 		fas = dpaa2_get_fas(buf_start, true);
836 		fas->status = cpu_to_le32(DPAA2_FAS_PTP);
837 
838 		dpaa2_ptp->caps.gettime64(&dpaa2_ptp->caps, &ts);
839 		ns = dpaa2_get_ts(buf_start, true);
840 		*ns = cpu_to_le64(timespec64_to_ns(&ts) /
841 				  DPAA2_PTP_CLK_PERIOD_NS);
842 
843 		/* Update current time to PTP message originTimestamp field */
844 		ns_to_ptp_tstamp(&origin_timestamp, le64_to_cpup(ns));
845 		data = skb_mac_header(skb);
846 		*(__be16 *)(data + offset2) = htons(origin_timestamp.sec_msb);
847 		*(__be32 *)(data + offset2 + 2) =
848 			htonl(origin_timestamp.sec_lsb);
849 		*(__be32 *)(data + offset2 + 6) = htonl(origin_timestamp.nsec);
850 
851 		if (priv->ptp_correction_off == offset1)
852 			return;
853 
854 		priv->dpaa2_set_onestep_params_cb(priv, offset1, udp);
855 		priv->ptp_correction_off = offset1;
856 
857 	}
858 }
859 
860 void *dpaa2_eth_sgt_get(struct dpaa2_eth_priv *priv)
861 {
862 	struct dpaa2_eth_sgt_cache *sgt_cache;
863 	void *sgt_buf = NULL;
864 	int sgt_buf_size;
865 
866 	sgt_cache = this_cpu_ptr(priv->sgt_cache);
867 	sgt_buf_size = priv->tx_data_offset +
868 		DPAA2_ETH_SG_ENTRIES_MAX * sizeof(struct dpaa2_sg_entry);
869 
870 	if (sgt_cache->count == 0)
871 		sgt_buf = napi_alloc_frag_align(sgt_buf_size, DPAA2_ETH_TX_BUF_ALIGN);
872 	else
873 		sgt_buf = sgt_cache->buf[--sgt_cache->count];
874 	if (!sgt_buf)
875 		return NULL;
876 
877 	memset(sgt_buf, 0, sgt_buf_size);
878 
879 	return sgt_buf;
880 }
881 
882 void dpaa2_eth_sgt_recycle(struct dpaa2_eth_priv *priv, void *sgt_buf)
883 {
884 	struct dpaa2_eth_sgt_cache *sgt_cache;
885 
886 	sgt_cache = this_cpu_ptr(priv->sgt_cache);
887 	if (sgt_cache->count >= DPAA2_ETH_SGT_CACHE_SIZE)
888 		skb_free_frag(sgt_buf);
889 	else
890 		sgt_cache->buf[sgt_cache->count++] = sgt_buf;
891 }
892 
893 /* Create a frame descriptor based on a fragmented skb */
894 static int dpaa2_eth_build_sg_fd(struct dpaa2_eth_priv *priv,
895 				 struct sk_buff *skb,
896 				 struct dpaa2_fd *fd,
897 				 void **swa_addr)
898 {
899 	struct device *dev = priv->net_dev->dev.parent;
900 	void *sgt_buf = NULL;
901 	dma_addr_t addr;
902 	int nr_frags = skb_shinfo(skb)->nr_frags;
903 	struct dpaa2_sg_entry *sgt;
904 	int i, err;
905 	int sgt_buf_size;
906 	struct scatterlist *scl, *crt_scl;
907 	int num_sg;
908 	int num_dma_bufs;
909 	struct dpaa2_eth_swa *swa;
910 
911 	/* Create and map scatterlist.
912 	 * We don't advertise NETIF_F_FRAGLIST, so skb_to_sgvec() will not have
913 	 * to go beyond nr_frags+1.
914 	 * Note: We don't support chained scatterlists
915 	 */
916 	if (unlikely(PAGE_SIZE / sizeof(struct scatterlist) < nr_frags + 1))
917 		return -EINVAL;
918 
919 	scl = kmalloc_array(nr_frags + 1, sizeof(struct scatterlist), GFP_ATOMIC);
920 	if (unlikely(!scl))
921 		return -ENOMEM;
922 
923 	sg_init_table(scl, nr_frags + 1);
924 	num_sg = skb_to_sgvec(skb, scl, 0, skb->len);
925 	if (unlikely(num_sg < 0)) {
926 		err = -ENOMEM;
927 		goto dma_map_sg_failed;
928 	}
929 	num_dma_bufs = dma_map_sg(dev, scl, num_sg, DMA_BIDIRECTIONAL);
930 	if (unlikely(!num_dma_bufs)) {
931 		err = -ENOMEM;
932 		goto dma_map_sg_failed;
933 	}
934 
935 	/* Prepare the HW SGT structure */
936 	sgt_buf_size = priv->tx_data_offset +
937 		       sizeof(struct dpaa2_sg_entry) *  num_dma_bufs;
938 	sgt_buf = dpaa2_eth_sgt_get(priv);
939 	if (unlikely(!sgt_buf)) {
940 		err = -ENOMEM;
941 		goto sgt_buf_alloc_failed;
942 	}
943 
944 	sgt = (struct dpaa2_sg_entry *)(sgt_buf + priv->tx_data_offset);
945 
946 	/* Fill in the HW SGT structure.
947 	 *
948 	 * sgt_buf is zeroed out, so the following fields are implicit
949 	 * in all sgt entries:
950 	 *   - offset is 0
951 	 *   - format is 'dpaa2_sg_single'
952 	 */
953 	for_each_sg(scl, crt_scl, num_dma_bufs, i) {
954 		dpaa2_sg_set_addr(&sgt[i], sg_dma_address(crt_scl));
955 		dpaa2_sg_set_len(&sgt[i], sg_dma_len(crt_scl));
956 	}
957 	dpaa2_sg_set_final(&sgt[i - 1], true);
958 
959 	/* Store the skb backpointer in the SGT buffer.
960 	 * Fit the scatterlist and the number of buffers alongside the
961 	 * skb backpointer in the software annotation area. We'll need
962 	 * all of them on Tx Conf.
963 	 */
964 	*swa_addr = (void *)sgt_buf;
965 	swa = (struct dpaa2_eth_swa *)sgt_buf;
966 	swa->type = DPAA2_ETH_SWA_SG;
967 	swa->sg.skb = skb;
968 	swa->sg.scl = scl;
969 	swa->sg.num_sg = num_sg;
970 	swa->sg.sgt_size = sgt_buf_size;
971 
972 	/* Separately map the SGT buffer */
973 	addr = dma_map_single(dev, sgt_buf, sgt_buf_size, DMA_BIDIRECTIONAL);
974 	if (unlikely(dma_mapping_error(dev, addr))) {
975 		err = -ENOMEM;
976 		goto dma_map_single_failed;
977 	}
978 	memset(fd, 0, sizeof(struct dpaa2_fd));
979 	dpaa2_fd_set_offset(fd, priv->tx_data_offset);
980 	dpaa2_fd_set_format(fd, dpaa2_fd_sg);
981 	dpaa2_fd_set_addr(fd, addr);
982 	dpaa2_fd_set_len(fd, skb->len);
983 	dpaa2_fd_set_ctrl(fd, FD_CTRL_PTA);
984 
985 	return 0;
986 
987 dma_map_single_failed:
988 	dpaa2_eth_sgt_recycle(priv, sgt_buf);
989 sgt_buf_alloc_failed:
990 	dma_unmap_sg(dev, scl, num_sg, DMA_BIDIRECTIONAL);
991 dma_map_sg_failed:
992 	kfree(scl);
993 	return err;
994 }
995 
996 /* Create a SG frame descriptor based on a linear skb.
997  *
998  * This function is used on the Tx path when the skb headroom is not large
999  * enough for the HW requirements, thus instead of realloc-ing the skb we
1000  * create a SG frame descriptor with only one entry.
1001  */
1002 static int dpaa2_eth_build_sg_fd_single_buf(struct dpaa2_eth_priv *priv,
1003 					    struct sk_buff *skb,
1004 					    struct dpaa2_fd *fd,
1005 					    void **swa_addr)
1006 {
1007 	struct device *dev = priv->net_dev->dev.parent;
1008 	struct dpaa2_sg_entry *sgt;
1009 	struct dpaa2_eth_swa *swa;
1010 	dma_addr_t addr, sgt_addr;
1011 	void *sgt_buf = NULL;
1012 	int sgt_buf_size;
1013 	int err;
1014 
1015 	/* Prepare the HW SGT structure */
1016 	sgt_buf_size = priv->tx_data_offset + sizeof(struct dpaa2_sg_entry);
1017 	sgt_buf = dpaa2_eth_sgt_get(priv);
1018 	if (unlikely(!sgt_buf))
1019 		return -ENOMEM;
1020 	sgt = (struct dpaa2_sg_entry *)(sgt_buf + priv->tx_data_offset);
1021 
1022 	addr = dma_map_single(dev, skb->data, skb->len, DMA_BIDIRECTIONAL);
1023 	if (unlikely(dma_mapping_error(dev, addr))) {
1024 		err = -ENOMEM;
1025 		goto data_map_failed;
1026 	}
1027 
1028 	/* Fill in the HW SGT structure */
1029 	dpaa2_sg_set_addr(sgt, addr);
1030 	dpaa2_sg_set_len(sgt, skb->len);
1031 	dpaa2_sg_set_final(sgt, true);
1032 
1033 	/* Store the skb backpointer in the SGT buffer */
1034 	*swa_addr = (void *)sgt_buf;
1035 	swa = (struct dpaa2_eth_swa *)sgt_buf;
1036 	swa->type = DPAA2_ETH_SWA_SINGLE;
1037 	swa->single.skb = skb;
1038 	swa->single.sgt_size = sgt_buf_size;
1039 
1040 	/* Separately map the SGT buffer */
1041 	sgt_addr = dma_map_single(dev, sgt_buf, sgt_buf_size, DMA_BIDIRECTIONAL);
1042 	if (unlikely(dma_mapping_error(dev, sgt_addr))) {
1043 		err = -ENOMEM;
1044 		goto sgt_map_failed;
1045 	}
1046 
1047 	memset(fd, 0, sizeof(struct dpaa2_fd));
1048 	dpaa2_fd_set_offset(fd, priv->tx_data_offset);
1049 	dpaa2_fd_set_format(fd, dpaa2_fd_sg);
1050 	dpaa2_fd_set_addr(fd, sgt_addr);
1051 	dpaa2_fd_set_len(fd, skb->len);
1052 	dpaa2_fd_set_ctrl(fd, FD_CTRL_PTA);
1053 
1054 	return 0;
1055 
1056 sgt_map_failed:
1057 	dma_unmap_single(dev, addr, skb->len, DMA_BIDIRECTIONAL);
1058 data_map_failed:
1059 	dpaa2_eth_sgt_recycle(priv, sgt_buf);
1060 
1061 	return err;
1062 }
1063 
1064 /* Create a frame descriptor based on a linear skb */
1065 static int dpaa2_eth_build_single_fd(struct dpaa2_eth_priv *priv,
1066 				     struct sk_buff *skb,
1067 				     struct dpaa2_fd *fd,
1068 				     void **swa_addr)
1069 {
1070 	struct device *dev = priv->net_dev->dev.parent;
1071 	u8 *buffer_start, *aligned_start;
1072 	struct dpaa2_eth_swa *swa;
1073 	dma_addr_t addr;
1074 
1075 	buffer_start = skb->data - dpaa2_eth_needed_headroom(skb);
1076 
1077 	/* If there's enough room to align the FD address, do it.
1078 	 * It will help hardware optimize accesses.
1079 	 */
1080 	aligned_start = PTR_ALIGN(buffer_start - DPAA2_ETH_TX_BUF_ALIGN,
1081 				  DPAA2_ETH_TX_BUF_ALIGN);
1082 	if (aligned_start >= skb->head)
1083 		buffer_start = aligned_start;
1084 
1085 	/* Store a backpointer to the skb at the beginning of the buffer
1086 	 * (in the private data area) such that we can release it
1087 	 * on Tx confirm
1088 	 */
1089 	*swa_addr = (void *)buffer_start;
1090 	swa = (struct dpaa2_eth_swa *)buffer_start;
1091 	swa->type = DPAA2_ETH_SWA_SINGLE;
1092 	swa->single.skb = skb;
1093 
1094 	addr = dma_map_single(dev, buffer_start,
1095 			      skb_tail_pointer(skb) - buffer_start,
1096 			      DMA_BIDIRECTIONAL);
1097 	if (unlikely(dma_mapping_error(dev, addr)))
1098 		return -ENOMEM;
1099 
1100 	memset(fd, 0, sizeof(struct dpaa2_fd));
1101 	dpaa2_fd_set_addr(fd, addr);
1102 	dpaa2_fd_set_offset(fd, (u16)(skb->data - buffer_start));
1103 	dpaa2_fd_set_len(fd, skb->len);
1104 	dpaa2_fd_set_format(fd, dpaa2_fd_single);
1105 	dpaa2_fd_set_ctrl(fd, FD_CTRL_PTA);
1106 
1107 	return 0;
1108 }
1109 
1110 /* FD freeing routine on the Tx path
1111  *
1112  * DMA-unmap and free FD and possibly SGT buffer allocated on Tx. The skb
1113  * back-pointed to is also freed.
1114  * This can be called either from dpaa2_eth_tx_conf() or on the error path of
1115  * dpaa2_eth_tx().
1116  */
1117 void dpaa2_eth_free_tx_fd(struct dpaa2_eth_priv *priv,
1118 			  struct dpaa2_eth_channel *ch,
1119 			  struct dpaa2_eth_fq *fq,
1120 			  const struct dpaa2_fd *fd, bool in_napi)
1121 {
1122 	struct device *dev = priv->net_dev->dev.parent;
1123 	dma_addr_t fd_addr, sg_addr;
1124 	struct sk_buff *skb = NULL;
1125 	unsigned char *buffer_start;
1126 	struct dpaa2_eth_swa *swa;
1127 	u8 fd_format = dpaa2_fd_get_format(fd);
1128 	u32 fd_len = dpaa2_fd_get_len(fd);
1129 	struct dpaa2_sg_entry *sgt;
1130 	int should_free_skb = 1;
1131 	void *tso_hdr;
1132 	int i;
1133 
1134 	fd_addr = dpaa2_fd_get_addr(fd);
1135 	buffer_start = dpaa2_iova_to_virt(priv->iommu_domain, fd_addr);
1136 	swa = (struct dpaa2_eth_swa *)buffer_start;
1137 
1138 	if (fd_format == dpaa2_fd_single) {
1139 		if (swa->type == DPAA2_ETH_SWA_SINGLE) {
1140 			skb = swa->single.skb;
1141 			/* Accessing the skb buffer is safe before dma unmap,
1142 			 * because we didn't map the actual skb shell.
1143 			 */
1144 			dma_unmap_single(dev, fd_addr,
1145 					 skb_tail_pointer(skb) - buffer_start,
1146 					 DMA_BIDIRECTIONAL);
1147 		} else {
1148 			WARN_ONCE(swa->type != DPAA2_ETH_SWA_XDP, "Wrong SWA type");
1149 			dma_unmap_single(dev, fd_addr, swa->xdp.dma_size,
1150 					 DMA_BIDIRECTIONAL);
1151 		}
1152 	} else if (fd_format == dpaa2_fd_sg) {
1153 		if (swa->type == DPAA2_ETH_SWA_SG) {
1154 			skb = swa->sg.skb;
1155 
1156 			/* Unmap the scatterlist */
1157 			dma_unmap_sg(dev, swa->sg.scl, swa->sg.num_sg,
1158 				     DMA_BIDIRECTIONAL);
1159 			kfree(swa->sg.scl);
1160 
1161 			/* Unmap the SGT buffer */
1162 			dma_unmap_single(dev, fd_addr, swa->sg.sgt_size,
1163 					 DMA_BIDIRECTIONAL);
1164 		} else if (swa->type == DPAA2_ETH_SWA_SW_TSO) {
1165 			skb = swa->tso.skb;
1166 
1167 			sgt = (struct dpaa2_sg_entry *)(buffer_start +
1168 							priv->tx_data_offset);
1169 
1170 			/* Unmap the SGT buffer */
1171 			dma_unmap_single(dev, fd_addr, swa->tso.sgt_size,
1172 					 DMA_BIDIRECTIONAL);
1173 
1174 			/* Unmap and free the header */
1175 			tso_hdr = dpaa2_iova_to_virt(priv->iommu_domain, dpaa2_sg_get_addr(sgt));
1176 			dma_unmap_single(dev, dpaa2_sg_get_addr(sgt), TSO_HEADER_SIZE,
1177 					 DMA_TO_DEVICE);
1178 			kfree(tso_hdr);
1179 
1180 			/* Unmap the other SG entries for the data */
1181 			for (i = 1; i < swa->tso.num_sg; i++)
1182 				dma_unmap_single(dev, dpaa2_sg_get_addr(&sgt[i]),
1183 						 dpaa2_sg_get_len(&sgt[i]), DMA_TO_DEVICE);
1184 
1185 			if (!swa->tso.is_last_fd)
1186 				should_free_skb = 0;
1187 		} else if (swa->type == DPAA2_ETH_SWA_XSK) {
1188 			/* Unmap the SGT Buffer */
1189 			dma_unmap_single(dev, fd_addr, swa->xsk.sgt_size,
1190 					 DMA_BIDIRECTIONAL);
1191 		} else {
1192 			skb = swa->single.skb;
1193 
1194 			/* Unmap the SGT Buffer */
1195 			dma_unmap_single(dev, fd_addr, swa->single.sgt_size,
1196 					 DMA_BIDIRECTIONAL);
1197 
1198 			sgt = (struct dpaa2_sg_entry *)(buffer_start +
1199 							priv->tx_data_offset);
1200 			sg_addr = dpaa2_sg_get_addr(sgt);
1201 			dma_unmap_single(dev, sg_addr, skb->len, DMA_BIDIRECTIONAL);
1202 		}
1203 	} else {
1204 		netdev_dbg(priv->net_dev, "Invalid FD format\n");
1205 		return;
1206 	}
1207 
1208 	if (swa->type == DPAA2_ETH_SWA_XSK) {
1209 		ch->xsk_tx_pkts_sent++;
1210 		dpaa2_eth_sgt_recycle(priv, buffer_start);
1211 		return;
1212 	}
1213 
1214 	if (swa->type != DPAA2_ETH_SWA_XDP && in_napi) {
1215 		fq->dq_frames++;
1216 		fq->dq_bytes += fd_len;
1217 	}
1218 
1219 	if (swa->type == DPAA2_ETH_SWA_XDP) {
1220 		xdp_return_frame(swa->xdp.xdpf);
1221 		return;
1222 	}
1223 
1224 	/* Get the timestamp value */
1225 	if (swa->type != DPAA2_ETH_SWA_SW_TSO) {
1226 		if (skb->cb[0] == TX_TSTAMP) {
1227 			struct skb_shared_hwtstamps shhwtstamps;
1228 			__le64 *ts = dpaa2_get_ts(buffer_start, true);
1229 			u64 ns;
1230 
1231 			memset(&shhwtstamps, 0, sizeof(shhwtstamps));
1232 
1233 			ns = DPAA2_PTP_CLK_PERIOD_NS * le64_to_cpup(ts);
1234 			shhwtstamps.hwtstamp = ns_to_ktime(ns);
1235 			skb_tstamp_tx(skb, &shhwtstamps);
1236 		} else if (skb->cb[0] == TX_TSTAMP_ONESTEP_SYNC) {
1237 			mutex_unlock(&priv->onestep_tstamp_lock);
1238 		}
1239 	}
1240 
1241 	/* Free SGT buffer allocated on tx */
1242 	if (fd_format != dpaa2_fd_single)
1243 		dpaa2_eth_sgt_recycle(priv, buffer_start);
1244 
1245 	/* Move on with skb release. If we are just confirming multiple FDs
1246 	 * from the same TSO skb then only the last one will need to free the
1247 	 * skb.
1248 	 */
1249 	if (should_free_skb)
1250 		napi_consume_skb(skb, in_napi);
1251 }
1252 
1253 static int dpaa2_eth_build_gso_fd(struct dpaa2_eth_priv *priv,
1254 				  struct sk_buff *skb, struct dpaa2_fd *fd,
1255 				  int *num_fds, u32 *total_fds_len)
1256 {
1257 	struct device *dev = priv->net_dev->dev.parent;
1258 	int hdr_len, total_len, data_left, fd_len;
1259 	int num_sge, err, i, sgt_buf_size;
1260 	struct dpaa2_fd *fd_start = fd;
1261 	struct dpaa2_sg_entry *sgt;
1262 	struct dpaa2_eth_swa *swa;
1263 	dma_addr_t sgt_addr, addr;
1264 	dma_addr_t tso_hdr_dma;
1265 	unsigned int index = 0;
1266 	struct tso_t tso;
1267 	char *tso_hdr;
1268 	void *sgt_buf;
1269 
1270 	/* Initialize the TSO handler, and prepare the first payload */
1271 	hdr_len = tso_start(skb, &tso);
1272 	*total_fds_len = 0;
1273 
1274 	total_len = skb->len - hdr_len;
1275 	while (total_len > 0) {
1276 		/* Prepare the HW SGT structure for this frame */
1277 		sgt_buf = dpaa2_eth_sgt_get(priv);
1278 		if (unlikely(!sgt_buf)) {
1279 			netdev_err(priv->net_dev, "dpaa2_eth_sgt_get() failed\n");
1280 			err = -ENOMEM;
1281 			goto err_sgt_get;
1282 		}
1283 		sgt = (struct dpaa2_sg_entry *)(sgt_buf + priv->tx_data_offset);
1284 
1285 		/* Determine the data length of this frame */
1286 		data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
1287 		total_len -= data_left;
1288 		fd_len = data_left + hdr_len;
1289 
1290 		/* Prepare packet headers: MAC + IP + TCP */
1291 		tso_hdr = kmalloc(TSO_HEADER_SIZE, GFP_ATOMIC);
1292 		if (!tso_hdr) {
1293 			err =  -ENOMEM;
1294 			goto err_alloc_tso_hdr;
1295 		}
1296 
1297 		tso_build_hdr(skb, tso_hdr, &tso, data_left, total_len == 0);
1298 		tso_hdr_dma = dma_map_single(dev, tso_hdr, TSO_HEADER_SIZE, DMA_TO_DEVICE);
1299 		if (dma_mapping_error(dev, tso_hdr_dma)) {
1300 			netdev_err(priv->net_dev, "dma_map_single(tso_hdr) failed\n");
1301 			err = -ENOMEM;
1302 			goto err_map_tso_hdr;
1303 		}
1304 
1305 		/* Setup the SG entry for the header */
1306 		dpaa2_sg_set_addr(sgt, tso_hdr_dma);
1307 		dpaa2_sg_set_len(sgt, hdr_len);
1308 		dpaa2_sg_set_final(sgt, data_left <= 0);
1309 
1310 		/* Compose the SG entries for each fragment of data */
1311 		num_sge = 1;
1312 		while (data_left > 0) {
1313 			int size;
1314 
1315 			/* Move to the next SG entry */
1316 			sgt++;
1317 			size = min_t(int, tso.size, data_left);
1318 
1319 			addr = dma_map_single(dev, tso.data, size, DMA_TO_DEVICE);
1320 			if (dma_mapping_error(dev, addr)) {
1321 				netdev_err(priv->net_dev, "dma_map_single(tso.data) failed\n");
1322 				err = -ENOMEM;
1323 				goto err_map_data;
1324 			}
1325 			dpaa2_sg_set_addr(sgt, addr);
1326 			dpaa2_sg_set_len(sgt, size);
1327 			dpaa2_sg_set_final(sgt, size == data_left);
1328 
1329 			num_sge++;
1330 
1331 			/* Build the data for the __next__ fragment */
1332 			data_left -= size;
1333 			tso_build_data(skb, &tso, size);
1334 		}
1335 
1336 		/* Store the skb backpointer in the SGT buffer */
1337 		sgt_buf_size = priv->tx_data_offset + num_sge * sizeof(struct dpaa2_sg_entry);
1338 		swa = (struct dpaa2_eth_swa *)sgt_buf;
1339 		swa->type = DPAA2_ETH_SWA_SW_TSO;
1340 		swa->tso.skb = skb;
1341 		swa->tso.num_sg = num_sge;
1342 		swa->tso.sgt_size = sgt_buf_size;
1343 		swa->tso.is_last_fd = total_len == 0 ? 1 : 0;
1344 
1345 		/* Separately map the SGT buffer */
1346 		sgt_addr = dma_map_single(dev, sgt_buf, sgt_buf_size, DMA_BIDIRECTIONAL);
1347 		if (unlikely(dma_mapping_error(dev, sgt_addr))) {
1348 			netdev_err(priv->net_dev, "dma_map_single(sgt_buf) failed\n");
1349 			err = -ENOMEM;
1350 			goto err_map_sgt;
1351 		}
1352 
1353 		/* Setup the frame descriptor */
1354 		memset(fd, 0, sizeof(struct dpaa2_fd));
1355 		dpaa2_fd_set_offset(fd, priv->tx_data_offset);
1356 		dpaa2_fd_set_format(fd, dpaa2_fd_sg);
1357 		dpaa2_fd_set_addr(fd, sgt_addr);
1358 		dpaa2_fd_set_len(fd, fd_len);
1359 		dpaa2_fd_set_ctrl(fd, FD_CTRL_PTA);
1360 
1361 		*total_fds_len += fd_len;
1362 		/* Advance to the next frame descriptor */
1363 		fd++;
1364 		index++;
1365 	}
1366 
1367 	*num_fds = index;
1368 
1369 	return 0;
1370 
1371 err_map_sgt:
1372 err_map_data:
1373 	/* Unmap all the data S/G entries for the current FD */
1374 	sgt = (struct dpaa2_sg_entry *)(sgt_buf + priv->tx_data_offset);
1375 	for (i = 1; i < num_sge; i++)
1376 		dma_unmap_single(dev, dpaa2_sg_get_addr(&sgt[i]),
1377 				 dpaa2_sg_get_len(&sgt[i]), DMA_TO_DEVICE);
1378 
1379 	/* Unmap the header entry */
1380 	dma_unmap_single(dev, tso_hdr_dma, TSO_HEADER_SIZE, DMA_TO_DEVICE);
1381 err_map_tso_hdr:
1382 	kfree(tso_hdr);
1383 err_alloc_tso_hdr:
1384 	dpaa2_eth_sgt_recycle(priv, sgt_buf);
1385 err_sgt_get:
1386 	/* Free all the other FDs that were already fully created */
1387 	for (i = 0; i < index; i++)
1388 		dpaa2_eth_free_tx_fd(priv, NULL, NULL, &fd_start[i], false);
1389 
1390 	return err;
1391 }
1392 
1393 static netdev_tx_t __dpaa2_eth_tx(struct sk_buff *skb,
1394 				  struct net_device *net_dev)
1395 {
1396 	struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
1397 	int total_enqueued = 0, retries = 0, enqueued;
1398 	struct dpaa2_eth_drv_stats *percpu_extras;
1399 	struct rtnl_link_stats64 *percpu_stats;
1400 	unsigned int needed_headroom;
1401 	int num_fds = 1, max_retries;
1402 	struct dpaa2_eth_fq *fq;
1403 	struct netdev_queue *nq;
1404 	struct dpaa2_fd *fd;
1405 	u16 queue_mapping;
1406 	void *swa = NULL;
1407 	u8 prio = 0;
1408 	int err, i;
1409 	u32 fd_len;
1410 
1411 	percpu_stats = this_cpu_ptr(priv->percpu_stats);
1412 	percpu_extras = this_cpu_ptr(priv->percpu_extras);
1413 	fd = (this_cpu_ptr(priv->fd))->array;
1414 
1415 	needed_headroom = dpaa2_eth_needed_headroom(skb);
1416 
1417 	/* We'll be holding a back-reference to the skb until Tx Confirmation;
1418 	 * we don't want that overwritten by a concurrent Tx with a cloned skb.
1419 	 */
1420 	skb = skb_unshare(skb, GFP_ATOMIC);
1421 	if (unlikely(!skb)) {
1422 		/* skb_unshare() has already freed the skb */
1423 		percpu_stats->tx_dropped++;
1424 		return NETDEV_TX_OK;
1425 	}
1426 
1427 	/* Setup the FD fields */
1428 
1429 	if (skb_is_gso(skb)) {
1430 		err = dpaa2_eth_build_gso_fd(priv, skb, fd, &num_fds, &fd_len);
1431 		percpu_extras->tx_sg_frames += num_fds;
1432 		percpu_extras->tx_sg_bytes += fd_len;
1433 		percpu_extras->tx_tso_frames += num_fds;
1434 		percpu_extras->tx_tso_bytes += fd_len;
1435 	} else if (skb_is_nonlinear(skb)) {
1436 		err = dpaa2_eth_build_sg_fd(priv, skb, fd, &swa);
1437 		percpu_extras->tx_sg_frames++;
1438 		percpu_extras->tx_sg_bytes += skb->len;
1439 		fd_len = dpaa2_fd_get_len(fd);
1440 	} else if (skb_headroom(skb) < needed_headroom) {
1441 		err = dpaa2_eth_build_sg_fd_single_buf(priv, skb, fd, &swa);
1442 		percpu_extras->tx_sg_frames++;
1443 		percpu_extras->tx_sg_bytes += skb->len;
1444 		percpu_extras->tx_converted_sg_frames++;
1445 		percpu_extras->tx_converted_sg_bytes += skb->len;
1446 		fd_len = dpaa2_fd_get_len(fd);
1447 	} else {
1448 		err = dpaa2_eth_build_single_fd(priv, skb, fd, &swa);
1449 		fd_len = dpaa2_fd_get_len(fd);
1450 	}
1451 
1452 	if (unlikely(err)) {
1453 		percpu_stats->tx_dropped++;
1454 		goto err_build_fd;
1455 	}
1456 
1457 	if (swa && skb->cb[0])
1458 		dpaa2_eth_enable_tx_tstamp(priv, fd, swa, skb);
1459 
1460 	/* Tracing point */
1461 	for (i = 0; i < num_fds; i++)
1462 		trace_dpaa2_tx_fd(net_dev, &fd[i]);
1463 
1464 	/* TxConf FQ selection relies on queue id from the stack.
1465 	 * In case of a forwarded frame from another DPNI interface, we choose
1466 	 * a queue affined to the same core that processed the Rx frame
1467 	 */
1468 	queue_mapping = skb_get_queue_mapping(skb);
1469 
1470 	if (net_dev->num_tc) {
1471 		prio = netdev_txq_to_tc(net_dev, queue_mapping);
1472 		/* Hardware interprets priority level 0 as being the highest,
1473 		 * so we need to do a reverse mapping to the netdev tc index
1474 		 */
1475 		prio = net_dev->num_tc - prio - 1;
1476 		/* We have only one FQ array entry for all Tx hardware queues
1477 		 * with the same flow id (but different priority levels)
1478 		 */
1479 		queue_mapping %= dpaa2_eth_queue_count(priv);
1480 	}
1481 	fq = &priv->fq[queue_mapping];
1482 	nq = netdev_get_tx_queue(net_dev, queue_mapping);
1483 	netdev_tx_sent_queue(nq, fd_len);
1484 
1485 	/* Everything that happens after this enqueues might race with
1486 	 * the Tx confirmation callback for this frame
1487 	 */
1488 	max_retries = num_fds * DPAA2_ETH_ENQUEUE_RETRIES;
1489 	while (total_enqueued < num_fds && retries < max_retries) {
1490 		err = priv->enqueue(priv, fq, &fd[total_enqueued],
1491 				    prio, num_fds - total_enqueued, &enqueued);
1492 		if (err == -EBUSY) {
1493 			retries++;
1494 			continue;
1495 		}
1496 
1497 		total_enqueued += enqueued;
1498 	}
1499 	percpu_extras->tx_portal_busy += retries;
1500 
1501 	if (unlikely(err < 0)) {
1502 		percpu_stats->tx_errors++;
1503 		/* Clean up everything, including freeing the skb */
1504 		dpaa2_eth_free_tx_fd(priv, NULL, fq, fd, false);
1505 		netdev_tx_completed_queue(nq, 1, fd_len);
1506 	} else {
1507 		percpu_stats->tx_packets += total_enqueued;
1508 		percpu_stats->tx_bytes += fd_len;
1509 	}
1510 
1511 	return NETDEV_TX_OK;
1512 
1513 err_build_fd:
1514 	dev_kfree_skb(skb);
1515 
1516 	return NETDEV_TX_OK;
1517 }
1518 
1519 static void dpaa2_eth_tx_onestep_tstamp(struct work_struct *work)
1520 {
1521 	struct dpaa2_eth_priv *priv = container_of(work, struct dpaa2_eth_priv,
1522 						   tx_onestep_tstamp);
1523 	struct sk_buff *skb;
1524 
1525 	while (true) {
1526 		skb = skb_dequeue(&priv->tx_skbs);
1527 		if (!skb)
1528 			return;
1529 
1530 		/* Lock just before TX one-step timestamping packet,
1531 		 * and release the lock in dpaa2_eth_free_tx_fd when
1532 		 * confirm the packet has been sent on hardware, or
1533 		 * when clean up during transmit failure.
1534 		 */
1535 		mutex_lock(&priv->onestep_tstamp_lock);
1536 		__dpaa2_eth_tx(skb, priv->net_dev);
1537 	}
1538 }
1539 
1540 static netdev_tx_t dpaa2_eth_tx(struct sk_buff *skb, struct net_device *net_dev)
1541 {
1542 	struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
1543 	u8 msgtype, twostep, udp;
1544 	u16 offset1, offset2;
1545 
1546 	/* Utilize skb->cb[0] for timestamping request per skb */
1547 	skb->cb[0] = 0;
1548 
1549 	if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && dpaa2_ptp) {
1550 		if (priv->tx_tstamp_type == HWTSTAMP_TX_ON)
1551 			skb->cb[0] = TX_TSTAMP;
1552 		else if (priv->tx_tstamp_type == HWTSTAMP_TX_ONESTEP_SYNC)
1553 			skb->cb[0] = TX_TSTAMP_ONESTEP_SYNC;
1554 	}
1555 
1556 	/* TX for one-step timestamping PTP Sync packet */
1557 	if (skb->cb[0] == TX_TSTAMP_ONESTEP_SYNC) {
1558 		if (!dpaa2_eth_ptp_parse(skb, &msgtype, &twostep, &udp,
1559 					 &offset1, &offset2))
1560 			if (msgtype == PTP_MSGTYPE_SYNC && twostep == 0) {
1561 				skb_queue_tail(&priv->tx_skbs, skb);
1562 				queue_work(priv->dpaa2_ptp_wq,
1563 					   &priv->tx_onestep_tstamp);
1564 				return NETDEV_TX_OK;
1565 			}
1566 		/* Use two-step timestamping if not one-step timestamping
1567 		 * PTP Sync packet
1568 		 */
1569 		skb->cb[0] = TX_TSTAMP;
1570 	}
1571 
1572 	/* TX for other packets */
1573 	return __dpaa2_eth_tx(skb, net_dev);
1574 }
1575 
1576 /* Tx confirmation frame processing routine */
1577 static void dpaa2_eth_tx_conf(struct dpaa2_eth_priv *priv,
1578 			      struct dpaa2_eth_channel *ch,
1579 			      const struct dpaa2_fd *fd,
1580 			      struct dpaa2_eth_fq *fq)
1581 {
1582 	struct rtnl_link_stats64 *percpu_stats;
1583 	struct dpaa2_eth_drv_stats *percpu_extras;
1584 	u32 fd_len = dpaa2_fd_get_len(fd);
1585 	u32 fd_errors;
1586 
1587 	/* Tracing point */
1588 	trace_dpaa2_tx_conf_fd(priv->net_dev, fd);
1589 
1590 	percpu_extras = this_cpu_ptr(priv->percpu_extras);
1591 	percpu_extras->tx_conf_frames++;
1592 	percpu_extras->tx_conf_bytes += fd_len;
1593 	ch->stats.bytes_per_cdan += fd_len;
1594 
1595 	/* Check frame errors in the FD field */
1596 	fd_errors = dpaa2_fd_get_ctrl(fd) & DPAA2_FD_TX_ERR_MASK;
1597 	dpaa2_eth_free_tx_fd(priv, ch, fq, fd, true);
1598 
1599 	if (likely(!fd_errors))
1600 		return;
1601 
1602 	if (net_ratelimit())
1603 		netdev_dbg(priv->net_dev, "TX frame FD error: 0x%08x\n",
1604 			   fd_errors);
1605 
1606 	percpu_stats = this_cpu_ptr(priv->percpu_stats);
1607 	/* Tx-conf logically pertains to the egress path. */
1608 	percpu_stats->tx_errors++;
1609 }
1610 
1611 static int dpaa2_eth_set_rx_vlan_filtering(struct dpaa2_eth_priv *priv,
1612 					   bool enable)
1613 {
1614 	int err;
1615 
1616 	err = dpni_enable_vlan_filter(priv->mc_io, 0, priv->mc_token, enable);
1617 
1618 	if (err) {
1619 		netdev_err(priv->net_dev,
1620 			   "dpni_enable_vlan_filter failed\n");
1621 		return err;
1622 	}
1623 
1624 	return 0;
1625 }
1626 
1627 static int dpaa2_eth_set_rx_csum(struct dpaa2_eth_priv *priv, bool enable)
1628 {
1629 	int err;
1630 
1631 	err = dpni_set_offload(priv->mc_io, 0, priv->mc_token,
1632 			       DPNI_OFF_RX_L3_CSUM, enable);
1633 	if (err) {
1634 		netdev_err(priv->net_dev,
1635 			   "dpni_set_offload(RX_L3_CSUM) failed\n");
1636 		return err;
1637 	}
1638 
1639 	err = dpni_set_offload(priv->mc_io, 0, priv->mc_token,
1640 			       DPNI_OFF_RX_L4_CSUM, enable);
1641 	if (err) {
1642 		netdev_err(priv->net_dev,
1643 			   "dpni_set_offload(RX_L4_CSUM) failed\n");
1644 		return err;
1645 	}
1646 
1647 	return 0;
1648 }
1649 
1650 static int dpaa2_eth_set_tx_csum(struct dpaa2_eth_priv *priv, bool enable)
1651 {
1652 	int err;
1653 
1654 	err = dpni_set_offload(priv->mc_io, 0, priv->mc_token,
1655 			       DPNI_OFF_TX_L3_CSUM, enable);
1656 	if (err) {
1657 		netdev_err(priv->net_dev, "dpni_set_offload(TX_L3_CSUM) failed\n");
1658 		return err;
1659 	}
1660 
1661 	err = dpni_set_offload(priv->mc_io, 0, priv->mc_token,
1662 			       DPNI_OFF_TX_L4_CSUM, enable);
1663 	if (err) {
1664 		netdev_err(priv->net_dev, "dpni_set_offload(TX_L4_CSUM) failed\n");
1665 		return err;
1666 	}
1667 
1668 	return 0;
1669 }
1670 
1671 /* Perform a single release command to add buffers
1672  * to the specified buffer pool
1673  */
1674 static int dpaa2_eth_add_bufs(struct dpaa2_eth_priv *priv,
1675 			      struct dpaa2_eth_channel *ch)
1676 {
1677 	struct xdp_buff *xdp_buffs[DPAA2_ETH_BUFS_PER_CMD];
1678 	struct device *dev = priv->net_dev->dev.parent;
1679 	u64 buf_array[DPAA2_ETH_BUFS_PER_CMD];
1680 	struct dpaa2_eth_swa *swa;
1681 	struct page *page;
1682 	dma_addr_t addr;
1683 	int retries = 0;
1684 	int i = 0, err;
1685 	u32 batch;
1686 
1687 	/* Allocate buffers visible to WRIOP */
1688 	if (!ch->xsk_zc) {
1689 		for (i = 0; i < DPAA2_ETH_BUFS_PER_CMD; i++) {
1690 			/* Also allocate skb shared info and alignment padding.
1691 			 * There is one page for each Rx buffer. WRIOP sees
1692 			 * the entire page except for a tailroom reserved for
1693 			 * skb shared info
1694 			 */
1695 			page = dev_alloc_pages(0);
1696 			if (!page)
1697 				goto err_alloc;
1698 
1699 			addr = dma_map_page(dev, page, 0, priv->rx_buf_size,
1700 					    DMA_BIDIRECTIONAL);
1701 			if (unlikely(dma_mapping_error(dev, addr)))
1702 				goto err_map;
1703 
1704 			buf_array[i] = addr;
1705 
1706 			/* tracing point */
1707 			trace_dpaa2_eth_buf_seed(priv->net_dev,
1708 						 page_address(page),
1709 						 DPAA2_ETH_RX_BUF_RAW_SIZE,
1710 						 addr, priv->rx_buf_size,
1711 						 ch->bp->bpid);
1712 		}
1713 	} else if (xsk_buff_can_alloc(ch->xsk_pool, DPAA2_ETH_BUFS_PER_CMD)) {
1714 		/* Allocate XSK buffers for AF_XDP fast path in batches
1715 		 * of DPAA2_ETH_BUFS_PER_CMD. Bail out if the UMEM cannot
1716 		 * provide enough buffers at the moment
1717 		 */
1718 		batch = xsk_buff_alloc_batch(ch->xsk_pool, xdp_buffs,
1719 					     DPAA2_ETH_BUFS_PER_CMD);
1720 		if (!batch)
1721 			goto err_alloc;
1722 
1723 		for (i = 0; i < batch; i++) {
1724 			swa = (struct dpaa2_eth_swa *)(xdp_buffs[i]->data_hard_start +
1725 						       DPAA2_ETH_RX_HWA_SIZE);
1726 			swa->xsk.xdp_buff = xdp_buffs[i];
1727 
1728 			addr = xsk_buff_xdp_get_frame_dma(xdp_buffs[i]);
1729 			if (unlikely(dma_mapping_error(dev, addr)))
1730 				goto err_map;
1731 
1732 			buf_array[i] = addr;
1733 
1734 			trace_dpaa2_xsk_buf_seed(priv->net_dev,
1735 						 xdp_buffs[i]->data_hard_start,
1736 						 DPAA2_ETH_RX_BUF_RAW_SIZE,
1737 						 addr, priv->rx_buf_size,
1738 						 ch->bp->bpid);
1739 		}
1740 	}
1741 
1742 release_bufs:
1743 	/* In case the portal is busy, retry until successful */
1744 	while ((err = dpaa2_io_service_release(ch->dpio, ch->bp->bpid,
1745 					       buf_array, i)) == -EBUSY) {
1746 		if (retries++ >= DPAA2_ETH_SWP_BUSY_RETRIES)
1747 			break;
1748 		cpu_relax();
1749 	}
1750 
1751 	/* If release command failed, clean up and bail out;
1752 	 * not much else we can do about it
1753 	 */
1754 	if (err) {
1755 		dpaa2_eth_free_bufs(priv, buf_array, i, ch->xsk_zc);
1756 		return 0;
1757 	}
1758 
1759 	return i;
1760 
1761 err_map:
1762 	if (!ch->xsk_zc) {
1763 		__free_pages(page, 0);
1764 	} else {
1765 		for (; i < batch; i++)
1766 			xsk_buff_free(xdp_buffs[i]);
1767 	}
1768 err_alloc:
1769 	/* If we managed to allocate at least some buffers,
1770 	 * release them to hardware
1771 	 */
1772 	if (i)
1773 		goto release_bufs;
1774 
1775 	return 0;
1776 }
1777 
1778 static int dpaa2_eth_seed_pool(struct dpaa2_eth_priv *priv,
1779 			       struct dpaa2_eth_channel *ch)
1780 {
1781 	int i;
1782 	int new_count;
1783 
1784 	for (i = 0; i < DPAA2_ETH_NUM_BUFS; i += DPAA2_ETH_BUFS_PER_CMD) {
1785 		new_count = dpaa2_eth_add_bufs(priv, ch);
1786 		ch->buf_count += new_count;
1787 
1788 		if (new_count < DPAA2_ETH_BUFS_PER_CMD)
1789 			return -ENOMEM;
1790 	}
1791 
1792 	return 0;
1793 }
1794 
1795 static void dpaa2_eth_seed_pools(struct dpaa2_eth_priv *priv)
1796 {
1797 	struct net_device *net_dev = priv->net_dev;
1798 	struct dpaa2_eth_channel *channel;
1799 	int i, err = 0;
1800 
1801 	for (i = 0; i < priv->num_channels; i++) {
1802 		channel = priv->channel[i];
1803 
1804 		err = dpaa2_eth_seed_pool(priv, channel);
1805 
1806 		/* Not much to do; the buffer pool, though not filled up,
1807 		 * may still contain some buffers which would enable us
1808 		 * to limp on.
1809 		 */
1810 		if (err)
1811 			netdev_err(net_dev, "Buffer seeding failed for DPBP %d (bpid=%d)\n",
1812 				   channel->bp->dev->obj_desc.id,
1813 				   channel->bp->bpid);
1814 	}
1815 }
1816 
1817 /*
1818  * Drain the specified number of buffers from one of the DPNI's private buffer
1819  * pools.
1820  * @count must not exceeed DPAA2_ETH_BUFS_PER_CMD
1821  */
1822 static void dpaa2_eth_drain_bufs(struct dpaa2_eth_priv *priv, int bpid,
1823 				 int count)
1824 {
1825 	u64 buf_array[DPAA2_ETH_BUFS_PER_CMD];
1826 	bool xsk_zc = false;
1827 	int retries = 0;
1828 	int i, ret;
1829 
1830 	for (i = 0; i < priv->num_channels; i++)
1831 		if (priv->channel[i]->bp->bpid == bpid)
1832 			xsk_zc = priv->channel[i]->xsk_zc;
1833 
1834 	do {
1835 		ret = dpaa2_io_service_acquire(NULL, bpid, buf_array, count);
1836 		if (ret < 0) {
1837 			if (ret == -EBUSY &&
1838 			    retries++ < DPAA2_ETH_SWP_BUSY_RETRIES)
1839 				continue;
1840 			netdev_err(priv->net_dev, "dpaa2_io_service_acquire() failed\n");
1841 			return;
1842 		}
1843 		dpaa2_eth_free_bufs(priv, buf_array, ret, xsk_zc);
1844 		retries = 0;
1845 	} while (ret);
1846 }
1847 
1848 static void dpaa2_eth_drain_pool(struct dpaa2_eth_priv *priv, int bpid)
1849 {
1850 	int i;
1851 
1852 	/* Drain the buffer pool */
1853 	dpaa2_eth_drain_bufs(priv, bpid, DPAA2_ETH_BUFS_PER_CMD);
1854 	dpaa2_eth_drain_bufs(priv, bpid, 1);
1855 
1856 	/* Setup to zero the buffer count of all channels which were
1857 	 * using this buffer pool.
1858 	 */
1859 	for (i = 0; i < priv->num_channels; i++)
1860 		if (priv->channel[i]->bp->bpid == bpid)
1861 			priv->channel[i]->buf_count = 0;
1862 }
1863 
1864 static void dpaa2_eth_drain_pools(struct dpaa2_eth_priv *priv)
1865 {
1866 	int i;
1867 
1868 	for (i = 0; i < priv->num_bps; i++)
1869 		dpaa2_eth_drain_pool(priv, priv->bp[i]->bpid);
1870 }
1871 
1872 /* Function is called from softirq context only, so we don't need to guard
1873  * the access to percpu count
1874  */
1875 static int dpaa2_eth_refill_pool(struct dpaa2_eth_priv *priv,
1876 				 struct dpaa2_eth_channel *ch)
1877 {
1878 	int new_count;
1879 
1880 	if (likely(ch->buf_count >= DPAA2_ETH_REFILL_THRESH))
1881 		return 0;
1882 
1883 	do {
1884 		new_count = dpaa2_eth_add_bufs(priv, ch);
1885 		if (unlikely(!new_count)) {
1886 			/* Out of memory; abort for now, we'll try later on */
1887 			break;
1888 		}
1889 		ch->buf_count += new_count;
1890 	} while (ch->buf_count < DPAA2_ETH_NUM_BUFS);
1891 
1892 	if (unlikely(ch->buf_count < DPAA2_ETH_NUM_BUFS))
1893 		return -ENOMEM;
1894 
1895 	return 0;
1896 }
1897 
1898 static void dpaa2_eth_sgt_cache_drain(struct dpaa2_eth_priv *priv)
1899 {
1900 	struct dpaa2_eth_sgt_cache *sgt_cache;
1901 	u16 count;
1902 	int k, i;
1903 
1904 	for_each_possible_cpu(k) {
1905 		sgt_cache = per_cpu_ptr(priv->sgt_cache, k);
1906 		count = sgt_cache->count;
1907 
1908 		for (i = 0; i < count; i++)
1909 			skb_free_frag(sgt_cache->buf[i]);
1910 		sgt_cache->count = 0;
1911 	}
1912 }
1913 
1914 static int dpaa2_eth_pull_channel(struct dpaa2_eth_channel *ch)
1915 {
1916 	int err;
1917 	int dequeues = -1;
1918 
1919 	/* Retry while portal is busy */
1920 	do {
1921 		err = dpaa2_io_service_pull_channel(ch->dpio, ch->ch_id,
1922 						    ch->store);
1923 		dequeues++;
1924 		cpu_relax();
1925 	} while (err == -EBUSY && dequeues < DPAA2_ETH_SWP_BUSY_RETRIES);
1926 
1927 	ch->stats.dequeue_portal_busy += dequeues;
1928 	if (unlikely(err))
1929 		ch->stats.pull_err++;
1930 
1931 	return err;
1932 }
1933 
1934 /* NAPI poll routine
1935  *
1936  * Frames are dequeued from the QMan channel associated with this NAPI context.
1937  * Rx, Tx confirmation and (if configured) Rx error frames all count
1938  * towards the NAPI budget.
1939  */
1940 static int dpaa2_eth_poll(struct napi_struct *napi, int budget)
1941 {
1942 	struct dpaa2_eth_channel *ch;
1943 	struct dpaa2_eth_priv *priv;
1944 	int rx_cleaned = 0, txconf_cleaned = 0;
1945 	struct dpaa2_eth_fq *fq, *txc_fq = NULL;
1946 	struct netdev_queue *nq;
1947 	int store_cleaned, work_done;
1948 	bool work_done_zc = false;
1949 	struct list_head rx_list;
1950 	int retries = 0;
1951 	u16 flowid;
1952 	int err;
1953 
1954 	ch = container_of(napi, struct dpaa2_eth_channel, napi);
1955 	ch->xdp.res = 0;
1956 	priv = ch->priv;
1957 
1958 	INIT_LIST_HEAD(&rx_list);
1959 	ch->rx_list = &rx_list;
1960 
1961 	if (ch->xsk_zc) {
1962 		work_done_zc = dpaa2_xsk_tx(priv, ch);
1963 		/* If we reached the XSK Tx per NAPI threshold, we're done */
1964 		if (work_done_zc) {
1965 			work_done = budget;
1966 			goto out;
1967 		}
1968 	}
1969 
1970 	do {
1971 		err = dpaa2_eth_pull_channel(ch);
1972 		if (unlikely(err))
1973 			break;
1974 
1975 		/* Refill pool if appropriate */
1976 		dpaa2_eth_refill_pool(priv, ch);
1977 
1978 		store_cleaned = dpaa2_eth_consume_frames(ch, &fq);
1979 		if (store_cleaned <= 0)
1980 			break;
1981 		if (fq->type == DPAA2_RX_FQ) {
1982 			rx_cleaned += store_cleaned;
1983 			flowid = fq->flowid;
1984 		} else {
1985 			txconf_cleaned += store_cleaned;
1986 			/* We have a single Tx conf FQ on this channel */
1987 			txc_fq = fq;
1988 		}
1989 
1990 		/* If we either consumed the whole NAPI budget with Rx frames
1991 		 * or we reached the Tx confirmations threshold, we're done.
1992 		 */
1993 		if (rx_cleaned >= budget ||
1994 		    txconf_cleaned >= DPAA2_ETH_TXCONF_PER_NAPI) {
1995 			work_done = budget;
1996 			if (ch->xdp.res & XDP_REDIRECT)
1997 				xdp_do_flush();
1998 			goto out;
1999 		}
2000 	} while (store_cleaned);
2001 
2002 	if (ch->xdp.res & XDP_REDIRECT)
2003 		xdp_do_flush();
2004 
2005 	/* Update NET DIM with the values for this CDAN */
2006 	dpaa2_io_update_net_dim(ch->dpio, ch->stats.frames_per_cdan,
2007 				ch->stats.bytes_per_cdan);
2008 	ch->stats.frames_per_cdan = 0;
2009 	ch->stats.bytes_per_cdan = 0;
2010 
2011 	/* We didn't consume the entire budget, so finish napi and
2012 	 * re-enable data availability notifications
2013 	 */
2014 	napi_complete_done(napi, rx_cleaned);
2015 	do {
2016 		err = dpaa2_io_service_rearm(ch->dpio, &ch->nctx);
2017 		cpu_relax();
2018 	} while (err == -EBUSY && retries++ < DPAA2_ETH_SWP_BUSY_RETRIES);
2019 	WARN_ONCE(err, "CDAN notifications rearm failed on core %d",
2020 		  ch->nctx.desired_cpu);
2021 
2022 	work_done = max(rx_cleaned, 1);
2023 
2024 out:
2025 	netif_receive_skb_list(ch->rx_list);
2026 
2027 	if (ch->xsk_tx_pkts_sent) {
2028 		xsk_tx_completed(ch->xsk_pool, ch->xsk_tx_pkts_sent);
2029 		ch->xsk_tx_pkts_sent = 0;
2030 	}
2031 
2032 	if (txc_fq && txc_fq->dq_frames) {
2033 		nq = netdev_get_tx_queue(priv->net_dev, txc_fq->flowid);
2034 		netdev_tx_completed_queue(nq, txc_fq->dq_frames,
2035 					  txc_fq->dq_bytes);
2036 		txc_fq->dq_frames = 0;
2037 		txc_fq->dq_bytes = 0;
2038 	}
2039 
2040 	if (rx_cleaned && ch->xdp.res & XDP_TX)
2041 		dpaa2_eth_xdp_tx_flush(priv, ch, &priv->fq[flowid]);
2042 
2043 	return work_done;
2044 }
2045 
2046 static void dpaa2_eth_enable_ch_napi(struct dpaa2_eth_priv *priv)
2047 {
2048 	struct dpaa2_eth_channel *ch;
2049 	int i;
2050 
2051 	for (i = 0; i < priv->num_channels; i++) {
2052 		ch = priv->channel[i];
2053 		napi_enable(&ch->napi);
2054 	}
2055 }
2056 
2057 static void dpaa2_eth_disable_ch_napi(struct dpaa2_eth_priv *priv)
2058 {
2059 	struct dpaa2_eth_channel *ch;
2060 	int i;
2061 
2062 	for (i = 0; i < priv->num_channels; i++) {
2063 		ch = priv->channel[i];
2064 		napi_disable(&ch->napi);
2065 	}
2066 }
2067 
2068 void dpaa2_eth_set_rx_taildrop(struct dpaa2_eth_priv *priv,
2069 			       bool tx_pause, bool pfc)
2070 {
2071 	struct dpni_taildrop td = {0};
2072 	struct dpaa2_eth_fq *fq;
2073 	int i, err;
2074 
2075 	/* FQ taildrop: threshold is in bytes, per frame queue. Enabled if
2076 	 * flow control is disabled (as it might interfere with either the
2077 	 * buffer pool depletion trigger for pause frames or with the group
2078 	 * congestion trigger for PFC frames)
2079 	 */
2080 	td.enable = !tx_pause;
2081 	if (priv->rx_fqtd_enabled == td.enable)
2082 		goto set_cgtd;
2083 
2084 	td.threshold = DPAA2_ETH_FQ_TAILDROP_THRESH;
2085 	td.units = DPNI_CONGESTION_UNIT_BYTES;
2086 
2087 	for (i = 0; i < priv->num_fqs; i++) {
2088 		fq = &priv->fq[i];
2089 		if (fq->type != DPAA2_RX_FQ)
2090 			continue;
2091 		err = dpni_set_taildrop(priv->mc_io, 0, priv->mc_token,
2092 					DPNI_CP_QUEUE, DPNI_QUEUE_RX,
2093 					fq->tc, fq->flowid, &td);
2094 		if (err) {
2095 			netdev_err(priv->net_dev,
2096 				   "dpni_set_taildrop(FQ) failed\n");
2097 			return;
2098 		}
2099 	}
2100 
2101 	priv->rx_fqtd_enabled = td.enable;
2102 
2103 set_cgtd:
2104 	/* Congestion group taildrop: threshold is in frames, per group
2105 	 * of FQs belonging to the same traffic class
2106 	 * Enabled if general Tx pause disabled or if PFCs are enabled
2107 	 * (congestion group threhsold for PFC generation is lower than the
2108 	 * CG taildrop threshold, so it won't interfere with it; we also
2109 	 * want frames in non-PFC enabled traffic classes to be kept in check)
2110 	 */
2111 	td.enable = !tx_pause || pfc;
2112 	if (priv->rx_cgtd_enabled == td.enable)
2113 		return;
2114 
2115 	td.threshold = DPAA2_ETH_CG_TAILDROP_THRESH(priv);
2116 	td.units = DPNI_CONGESTION_UNIT_FRAMES;
2117 	for (i = 0; i < dpaa2_eth_tc_count(priv); i++) {
2118 		err = dpni_set_taildrop(priv->mc_io, 0, priv->mc_token,
2119 					DPNI_CP_GROUP, DPNI_QUEUE_RX,
2120 					i, 0, &td);
2121 		if (err) {
2122 			netdev_err(priv->net_dev,
2123 				   "dpni_set_taildrop(CG) failed\n");
2124 			return;
2125 		}
2126 	}
2127 
2128 	priv->rx_cgtd_enabled = td.enable;
2129 }
2130 
2131 static int dpaa2_eth_link_state_update(struct dpaa2_eth_priv *priv)
2132 {
2133 	struct dpni_link_state state = {0};
2134 	bool tx_pause;
2135 	int err;
2136 
2137 	err = dpni_get_link_state(priv->mc_io, 0, priv->mc_token, &state);
2138 	if (unlikely(err)) {
2139 		netdev_err(priv->net_dev,
2140 			   "dpni_get_link_state() failed\n");
2141 		return err;
2142 	}
2143 
2144 	/* If Tx pause frame settings have changed, we need to update
2145 	 * Rx FQ taildrop configuration as well. We configure taildrop
2146 	 * only when pause frame generation is disabled.
2147 	 */
2148 	tx_pause = dpaa2_eth_tx_pause_enabled(state.options);
2149 	dpaa2_eth_set_rx_taildrop(priv, tx_pause, priv->pfc_enabled);
2150 
2151 	/* When we manage the MAC/PHY using phylink there is no need
2152 	 * to manually update the netif_carrier.
2153 	 * We can avoid locking because we are called from the "link changed"
2154 	 * IRQ handler, which is the same as the "endpoint changed" IRQ handler
2155 	 * (the writer to priv->mac), so we cannot race with it.
2156 	 */
2157 	if (dpaa2_mac_is_type_phy(priv->mac))
2158 		goto out;
2159 
2160 	/* Chech link state; speed / duplex changes are not treated yet */
2161 	if (priv->link_state.up == state.up)
2162 		goto out;
2163 
2164 	if (state.up) {
2165 		netif_carrier_on(priv->net_dev);
2166 		netif_tx_start_all_queues(priv->net_dev);
2167 	} else {
2168 		netif_tx_stop_all_queues(priv->net_dev);
2169 		netif_carrier_off(priv->net_dev);
2170 	}
2171 
2172 	netdev_info(priv->net_dev, "Link Event: state %s\n",
2173 		    state.up ? "up" : "down");
2174 
2175 out:
2176 	priv->link_state = state;
2177 
2178 	return 0;
2179 }
2180 
2181 static int dpaa2_eth_open(struct net_device *net_dev)
2182 {
2183 	struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
2184 	int err;
2185 
2186 	dpaa2_eth_seed_pools(priv);
2187 
2188 	mutex_lock(&priv->mac_lock);
2189 
2190 	if (!dpaa2_eth_is_type_phy(priv)) {
2191 		/* We'll only start the txqs when the link is actually ready;
2192 		 * make sure we don't race against the link up notification,
2193 		 * which may come immediately after dpni_enable();
2194 		 */
2195 		netif_tx_stop_all_queues(net_dev);
2196 
2197 		/* Also, explicitly set carrier off, otherwise
2198 		 * netif_carrier_ok() will return true and cause 'ip link show'
2199 		 * to report the LOWER_UP flag, even though the link
2200 		 * notification wasn't even received.
2201 		 */
2202 		netif_carrier_off(net_dev);
2203 	}
2204 	dpaa2_eth_enable_ch_napi(priv);
2205 
2206 	err = dpni_enable(priv->mc_io, 0, priv->mc_token);
2207 	if (err < 0) {
2208 		mutex_unlock(&priv->mac_lock);
2209 		netdev_err(net_dev, "dpni_enable() failed\n");
2210 		goto enable_err;
2211 	}
2212 
2213 	if (dpaa2_eth_is_type_phy(priv))
2214 		dpaa2_mac_start(priv->mac);
2215 
2216 	mutex_unlock(&priv->mac_lock);
2217 
2218 	return 0;
2219 
2220 enable_err:
2221 	dpaa2_eth_disable_ch_napi(priv);
2222 	dpaa2_eth_drain_pools(priv);
2223 	return err;
2224 }
2225 
2226 /* Total number of in-flight frames on ingress queues */
2227 static u32 dpaa2_eth_ingress_fq_count(struct dpaa2_eth_priv *priv)
2228 {
2229 	struct dpaa2_eth_fq *fq;
2230 	u32 fcnt = 0, bcnt = 0, total = 0;
2231 	int i, err;
2232 
2233 	for (i = 0; i < priv->num_fqs; i++) {
2234 		fq = &priv->fq[i];
2235 		err = dpaa2_io_query_fq_count(NULL, fq->fqid, &fcnt, &bcnt);
2236 		if (err) {
2237 			netdev_warn(priv->net_dev, "query_fq_count failed");
2238 			break;
2239 		}
2240 		total += fcnt;
2241 	}
2242 
2243 	return total;
2244 }
2245 
2246 static void dpaa2_eth_wait_for_ingress_fq_empty(struct dpaa2_eth_priv *priv)
2247 {
2248 	int retries = 10;
2249 	u32 pending;
2250 
2251 	do {
2252 		pending = dpaa2_eth_ingress_fq_count(priv);
2253 		if (pending)
2254 			msleep(100);
2255 	} while (pending && --retries);
2256 }
2257 
2258 #define DPNI_TX_PENDING_VER_MAJOR	7
2259 #define DPNI_TX_PENDING_VER_MINOR	13
2260 static void dpaa2_eth_wait_for_egress_fq_empty(struct dpaa2_eth_priv *priv)
2261 {
2262 	union dpni_statistics stats;
2263 	int retries = 10;
2264 	int err;
2265 
2266 	if (dpaa2_eth_cmp_dpni_ver(priv, DPNI_TX_PENDING_VER_MAJOR,
2267 				   DPNI_TX_PENDING_VER_MINOR) < 0)
2268 		goto out;
2269 
2270 	do {
2271 		err = dpni_get_statistics(priv->mc_io, 0, priv->mc_token, 6,
2272 					  &stats);
2273 		if (err)
2274 			goto out;
2275 		if (stats.page_6.tx_pending_frames == 0)
2276 			return;
2277 	} while (--retries);
2278 
2279 out:
2280 	msleep(500);
2281 }
2282 
2283 static int dpaa2_eth_stop(struct net_device *net_dev)
2284 {
2285 	struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
2286 	int dpni_enabled = 0;
2287 	int retries = 10;
2288 
2289 	mutex_lock(&priv->mac_lock);
2290 
2291 	if (dpaa2_eth_is_type_phy(priv)) {
2292 		dpaa2_mac_stop(priv->mac);
2293 	} else {
2294 		netif_tx_stop_all_queues(net_dev);
2295 		netif_carrier_off(net_dev);
2296 	}
2297 
2298 	mutex_unlock(&priv->mac_lock);
2299 
2300 	/* On dpni_disable(), the MC firmware will:
2301 	 * - stop MAC Rx and wait for all Rx frames to be enqueued to software
2302 	 * - cut off WRIOP dequeues from egress FQs and wait until transmission
2303 	 * of all in flight Tx frames is finished (and corresponding Tx conf
2304 	 * frames are enqueued back to software)
2305 	 *
2306 	 * Before calling dpni_disable(), we wait for all Tx frames to arrive
2307 	 * on WRIOP. After it finishes, wait until all remaining frames on Rx
2308 	 * and Tx conf queues are consumed on NAPI poll.
2309 	 */
2310 	dpaa2_eth_wait_for_egress_fq_empty(priv);
2311 
2312 	do {
2313 		dpni_disable(priv->mc_io, 0, priv->mc_token);
2314 		dpni_is_enabled(priv->mc_io, 0, priv->mc_token, &dpni_enabled);
2315 		if (dpni_enabled)
2316 			/* Allow the hardware some slack */
2317 			msleep(100);
2318 	} while (dpni_enabled && --retries);
2319 	if (!retries) {
2320 		netdev_warn(net_dev, "Retry count exceeded disabling DPNI\n");
2321 		/* Must go on and disable NAPI nonetheless, so we don't crash at
2322 		 * the next "ifconfig up"
2323 		 */
2324 	}
2325 
2326 	dpaa2_eth_wait_for_ingress_fq_empty(priv);
2327 	dpaa2_eth_disable_ch_napi(priv);
2328 
2329 	/* Empty the buffer pool */
2330 	dpaa2_eth_drain_pools(priv);
2331 
2332 	/* Empty the Scatter-Gather Buffer cache */
2333 	dpaa2_eth_sgt_cache_drain(priv);
2334 
2335 	return 0;
2336 }
2337 
2338 static int dpaa2_eth_set_addr(struct net_device *net_dev, void *addr)
2339 {
2340 	struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
2341 	struct device *dev = net_dev->dev.parent;
2342 	int err;
2343 
2344 	err = eth_mac_addr(net_dev, addr);
2345 	if (err < 0) {
2346 		dev_err(dev, "eth_mac_addr() failed (%d)\n", err);
2347 		return err;
2348 	}
2349 
2350 	err = dpni_set_primary_mac_addr(priv->mc_io, 0, priv->mc_token,
2351 					net_dev->dev_addr);
2352 	if (err) {
2353 		dev_err(dev, "dpni_set_primary_mac_addr() failed (%d)\n", err);
2354 		return err;
2355 	}
2356 
2357 	return 0;
2358 }
2359 
2360 /** Fill in counters maintained by the GPP driver. These may be different from
2361  * the hardware counters obtained by ethtool.
2362  */
2363 static void dpaa2_eth_get_stats(struct net_device *net_dev,
2364 				struct rtnl_link_stats64 *stats)
2365 {
2366 	struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
2367 	struct rtnl_link_stats64 *percpu_stats;
2368 	u64 *cpustats;
2369 	u64 *netstats = (u64 *)stats;
2370 	int i, j;
2371 	int num = sizeof(struct rtnl_link_stats64) / sizeof(u64);
2372 
2373 	for_each_possible_cpu(i) {
2374 		percpu_stats = per_cpu_ptr(priv->percpu_stats, i);
2375 		cpustats = (u64 *)percpu_stats;
2376 		for (j = 0; j < num; j++)
2377 			netstats[j] += cpustats[j];
2378 	}
2379 }
2380 
2381 /* Copy mac unicast addresses from @net_dev to @priv.
2382  * Its sole purpose is to make dpaa2_eth_set_rx_mode() more readable.
2383  */
2384 static void dpaa2_eth_add_uc_hw_addr(const struct net_device *net_dev,
2385 				     struct dpaa2_eth_priv *priv)
2386 {
2387 	struct netdev_hw_addr *ha;
2388 	int err;
2389 
2390 	netdev_for_each_uc_addr(ha, net_dev) {
2391 		err = dpni_add_mac_addr(priv->mc_io, 0, priv->mc_token,
2392 					ha->addr);
2393 		if (err)
2394 			netdev_warn(priv->net_dev,
2395 				    "Could not add ucast MAC %pM to the filtering table (err %d)\n",
2396 				    ha->addr, err);
2397 	}
2398 }
2399 
2400 /* Copy mac multicast addresses from @net_dev to @priv
2401  * Its sole purpose is to make dpaa2_eth_set_rx_mode() more readable.
2402  */
2403 static void dpaa2_eth_add_mc_hw_addr(const struct net_device *net_dev,
2404 				     struct dpaa2_eth_priv *priv)
2405 {
2406 	struct netdev_hw_addr *ha;
2407 	int err;
2408 
2409 	netdev_for_each_mc_addr(ha, net_dev) {
2410 		err = dpni_add_mac_addr(priv->mc_io, 0, priv->mc_token,
2411 					ha->addr);
2412 		if (err)
2413 			netdev_warn(priv->net_dev,
2414 				    "Could not add mcast MAC %pM to the filtering table (err %d)\n",
2415 				    ha->addr, err);
2416 	}
2417 }
2418 
2419 static int dpaa2_eth_rx_add_vid(struct net_device *net_dev,
2420 				__be16 vlan_proto, u16 vid)
2421 {
2422 	struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
2423 	int err;
2424 
2425 	err = dpni_add_vlan_id(priv->mc_io, 0, priv->mc_token,
2426 			       vid, 0, 0, 0);
2427 
2428 	if (err) {
2429 		netdev_warn(priv->net_dev,
2430 			    "Could not add the vlan id %u\n",
2431 			    vid);
2432 		return err;
2433 	}
2434 
2435 	return 0;
2436 }
2437 
2438 static int dpaa2_eth_rx_kill_vid(struct net_device *net_dev,
2439 				 __be16 vlan_proto, u16 vid)
2440 {
2441 	struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
2442 	int err;
2443 
2444 	err = dpni_remove_vlan_id(priv->mc_io, 0, priv->mc_token, vid);
2445 
2446 	if (err) {
2447 		netdev_warn(priv->net_dev,
2448 			    "Could not remove the vlan id %u\n",
2449 			    vid);
2450 		return err;
2451 	}
2452 
2453 	return 0;
2454 }
2455 
2456 static void dpaa2_eth_set_rx_mode(struct net_device *net_dev)
2457 {
2458 	struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
2459 	int uc_count = netdev_uc_count(net_dev);
2460 	int mc_count = netdev_mc_count(net_dev);
2461 	u8 max_mac = priv->dpni_attrs.mac_filter_entries;
2462 	u32 options = priv->dpni_attrs.options;
2463 	u16 mc_token = priv->mc_token;
2464 	struct fsl_mc_io *mc_io = priv->mc_io;
2465 	int err;
2466 
2467 	/* Basic sanity checks; these probably indicate a misconfiguration */
2468 	if (options & DPNI_OPT_NO_MAC_FILTER && max_mac != 0)
2469 		netdev_info(net_dev,
2470 			    "mac_filter_entries=%d, DPNI_OPT_NO_MAC_FILTER option must be disabled\n",
2471 			    max_mac);
2472 
2473 	/* Force promiscuous if the uc or mc counts exceed our capabilities. */
2474 	if (uc_count > max_mac) {
2475 		netdev_info(net_dev,
2476 			    "Unicast addr count reached %d, max allowed is %d; forcing promisc\n",
2477 			    uc_count, max_mac);
2478 		goto force_promisc;
2479 	}
2480 	if (mc_count + uc_count > max_mac) {
2481 		netdev_info(net_dev,
2482 			    "Unicast + multicast addr count reached %d, max allowed is %d; forcing promisc\n",
2483 			    uc_count + mc_count, max_mac);
2484 		goto force_mc_promisc;
2485 	}
2486 
2487 	/* Adjust promisc settings due to flag combinations */
2488 	if (net_dev->flags & IFF_PROMISC)
2489 		goto force_promisc;
2490 	if (net_dev->flags & IFF_ALLMULTI) {
2491 		/* First, rebuild unicast filtering table. This should be done
2492 		 * in promisc mode, in order to avoid frame loss while we
2493 		 * progressively add entries to the table.
2494 		 * We don't know whether we had been in promisc already, and
2495 		 * making an MC call to find out is expensive; so set uc promisc
2496 		 * nonetheless.
2497 		 */
2498 		err = dpni_set_unicast_promisc(mc_io, 0, mc_token, 1);
2499 		if (err)
2500 			netdev_warn(net_dev, "Can't set uc promisc\n");
2501 
2502 		/* Actual uc table reconstruction. */
2503 		err = dpni_clear_mac_filters(mc_io, 0, mc_token, 1, 0);
2504 		if (err)
2505 			netdev_warn(net_dev, "Can't clear uc filters\n");
2506 		dpaa2_eth_add_uc_hw_addr(net_dev, priv);
2507 
2508 		/* Finally, clear uc promisc and set mc promisc as requested. */
2509 		err = dpni_set_unicast_promisc(mc_io, 0, mc_token, 0);
2510 		if (err)
2511 			netdev_warn(net_dev, "Can't clear uc promisc\n");
2512 		goto force_mc_promisc;
2513 	}
2514 
2515 	/* Neither unicast, nor multicast promisc will be on... eventually.
2516 	 * For now, rebuild mac filtering tables while forcing both of them on.
2517 	 */
2518 	err = dpni_set_unicast_promisc(mc_io, 0, mc_token, 1);
2519 	if (err)
2520 		netdev_warn(net_dev, "Can't set uc promisc (%d)\n", err);
2521 	err = dpni_set_multicast_promisc(mc_io, 0, mc_token, 1);
2522 	if (err)
2523 		netdev_warn(net_dev, "Can't set mc promisc (%d)\n", err);
2524 
2525 	/* Actual mac filtering tables reconstruction */
2526 	err = dpni_clear_mac_filters(mc_io, 0, mc_token, 1, 1);
2527 	if (err)
2528 		netdev_warn(net_dev, "Can't clear mac filters\n");
2529 	dpaa2_eth_add_mc_hw_addr(net_dev, priv);
2530 	dpaa2_eth_add_uc_hw_addr(net_dev, priv);
2531 
2532 	/* Now we can clear both ucast and mcast promisc, without risking
2533 	 * to drop legitimate frames anymore.
2534 	 */
2535 	err = dpni_set_unicast_promisc(mc_io, 0, mc_token, 0);
2536 	if (err)
2537 		netdev_warn(net_dev, "Can't clear ucast promisc\n");
2538 	err = dpni_set_multicast_promisc(mc_io, 0, mc_token, 0);
2539 	if (err)
2540 		netdev_warn(net_dev, "Can't clear mcast promisc\n");
2541 
2542 	return;
2543 
2544 force_promisc:
2545 	err = dpni_set_unicast_promisc(mc_io, 0, mc_token, 1);
2546 	if (err)
2547 		netdev_warn(net_dev, "Can't set ucast promisc\n");
2548 force_mc_promisc:
2549 	err = dpni_set_multicast_promisc(mc_io, 0, mc_token, 1);
2550 	if (err)
2551 		netdev_warn(net_dev, "Can't set mcast promisc\n");
2552 }
2553 
2554 static int dpaa2_eth_set_features(struct net_device *net_dev,
2555 				  netdev_features_t features)
2556 {
2557 	struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
2558 	netdev_features_t changed = features ^ net_dev->features;
2559 	bool enable;
2560 	int err;
2561 
2562 	if (changed & NETIF_F_HW_VLAN_CTAG_FILTER) {
2563 		enable = !!(features & NETIF_F_HW_VLAN_CTAG_FILTER);
2564 		err = dpaa2_eth_set_rx_vlan_filtering(priv, enable);
2565 		if (err)
2566 			return err;
2567 	}
2568 
2569 	if (changed & NETIF_F_RXCSUM) {
2570 		enable = !!(features & NETIF_F_RXCSUM);
2571 		err = dpaa2_eth_set_rx_csum(priv, enable);
2572 		if (err)
2573 			return err;
2574 	}
2575 
2576 	if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)) {
2577 		enable = !!(features & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM));
2578 		err = dpaa2_eth_set_tx_csum(priv, enable);
2579 		if (err)
2580 			return err;
2581 	}
2582 
2583 	return 0;
2584 }
2585 
2586 static int dpaa2_eth_ts_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2587 {
2588 	struct dpaa2_eth_priv *priv = netdev_priv(dev);
2589 	struct hwtstamp_config config;
2590 
2591 	if (!dpaa2_ptp)
2592 		return -EINVAL;
2593 
2594 	if (copy_from_user(&config, rq->ifr_data, sizeof(config)))
2595 		return -EFAULT;
2596 
2597 	switch (config.tx_type) {
2598 	case HWTSTAMP_TX_OFF:
2599 	case HWTSTAMP_TX_ON:
2600 	case HWTSTAMP_TX_ONESTEP_SYNC:
2601 		priv->tx_tstamp_type = config.tx_type;
2602 		break;
2603 	default:
2604 		return -ERANGE;
2605 	}
2606 
2607 	if (config.rx_filter == HWTSTAMP_FILTER_NONE) {
2608 		priv->rx_tstamp = false;
2609 	} else {
2610 		priv->rx_tstamp = true;
2611 		/* TS is set for all frame types, not only those requested */
2612 		config.rx_filter = HWTSTAMP_FILTER_ALL;
2613 	}
2614 
2615 	if (priv->tx_tstamp_type == HWTSTAMP_TX_ONESTEP_SYNC)
2616 		dpaa2_ptp_onestep_reg_update_method(priv);
2617 
2618 	return copy_to_user(rq->ifr_data, &config, sizeof(config)) ?
2619 			-EFAULT : 0;
2620 }
2621 
2622 static int dpaa2_eth_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2623 {
2624 	struct dpaa2_eth_priv *priv = netdev_priv(dev);
2625 	int err;
2626 
2627 	if (cmd == SIOCSHWTSTAMP)
2628 		return dpaa2_eth_ts_ioctl(dev, rq, cmd);
2629 
2630 	mutex_lock(&priv->mac_lock);
2631 
2632 	if (dpaa2_eth_is_type_phy(priv)) {
2633 		err = phylink_mii_ioctl(priv->mac->phylink, rq, cmd);
2634 		mutex_unlock(&priv->mac_lock);
2635 		return err;
2636 	}
2637 
2638 	mutex_unlock(&priv->mac_lock);
2639 
2640 	return -EOPNOTSUPP;
2641 }
2642 
2643 static bool xdp_mtu_valid(struct dpaa2_eth_priv *priv, int mtu)
2644 {
2645 	int mfl, linear_mfl;
2646 
2647 	mfl = DPAA2_ETH_L2_MAX_FRM(mtu);
2648 	linear_mfl = priv->rx_buf_size - DPAA2_ETH_RX_HWA_SIZE -
2649 		     dpaa2_eth_rx_head_room(priv) - XDP_PACKET_HEADROOM;
2650 
2651 	if (mfl > linear_mfl) {
2652 		netdev_warn(priv->net_dev, "Maximum MTU for XDP is %d\n",
2653 			    linear_mfl - VLAN_ETH_HLEN);
2654 		return false;
2655 	}
2656 
2657 	return true;
2658 }
2659 
2660 static int dpaa2_eth_set_rx_mfl(struct dpaa2_eth_priv *priv, int mtu, bool has_xdp)
2661 {
2662 	int mfl, err;
2663 
2664 	/* We enforce a maximum Rx frame length based on MTU only if we have
2665 	 * an XDP program attached (in order to avoid Rx S/G frames).
2666 	 * Otherwise, we accept all incoming frames as long as they are not
2667 	 * larger than maximum size supported in hardware
2668 	 */
2669 	if (has_xdp)
2670 		mfl = DPAA2_ETH_L2_MAX_FRM(mtu);
2671 	else
2672 		mfl = DPAA2_ETH_MFL;
2673 
2674 	err = dpni_set_max_frame_length(priv->mc_io, 0, priv->mc_token, mfl);
2675 	if (err) {
2676 		netdev_err(priv->net_dev, "dpni_set_max_frame_length failed\n");
2677 		return err;
2678 	}
2679 
2680 	return 0;
2681 }
2682 
2683 static int dpaa2_eth_change_mtu(struct net_device *dev, int new_mtu)
2684 {
2685 	struct dpaa2_eth_priv *priv = netdev_priv(dev);
2686 	int err;
2687 
2688 	if (!priv->xdp_prog)
2689 		goto out;
2690 
2691 	if (!xdp_mtu_valid(priv, new_mtu))
2692 		return -EINVAL;
2693 
2694 	err = dpaa2_eth_set_rx_mfl(priv, new_mtu, true);
2695 	if (err)
2696 		return err;
2697 
2698 out:
2699 	dev->mtu = new_mtu;
2700 	return 0;
2701 }
2702 
2703 static int dpaa2_eth_update_rx_buffer_headroom(struct dpaa2_eth_priv *priv, bool has_xdp)
2704 {
2705 	struct dpni_buffer_layout buf_layout = {0};
2706 	int err;
2707 
2708 	err = dpni_get_buffer_layout(priv->mc_io, 0, priv->mc_token,
2709 				     DPNI_QUEUE_RX, &buf_layout);
2710 	if (err) {
2711 		netdev_err(priv->net_dev, "dpni_get_buffer_layout failed\n");
2712 		return err;
2713 	}
2714 
2715 	/* Reserve extra headroom for XDP header size changes */
2716 	buf_layout.data_head_room = dpaa2_eth_rx_head_room(priv) +
2717 				    (has_xdp ? XDP_PACKET_HEADROOM : 0);
2718 	buf_layout.options = DPNI_BUF_LAYOUT_OPT_DATA_HEAD_ROOM;
2719 	err = dpni_set_buffer_layout(priv->mc_io, 0, priv->mc_token,
2720 				     DPNI_QUEUE_RX, &buf_layout);
2721 	if (err) {
2722 		netdev_err(priv->net_dev, "dpni_set_buffer_layout failed\n");
2723 		return err;
2724 	}
2725 
2726 	return 0;
2727 }
2728 
2729 static int dpaa2_eth_setup_xdp(struct net_device *dev, struct bpf_prog *prog)
2730 {
2731 	struct dpaa2_eth_priv *priv = netdev_priv(dev);
2732 	struct dpaa2_eth_channel *ch;
2733 	struct bpf_prog *old;
2734 	bool up, need_update;
2735 	int i, err;
2736 
2737 	if (prog && !xdp_mtu_valid(priv, dev->mtu))
2738 		return -EINVAL;
2739 
2740 	if (prog)
2741 		bpf_prog_add(prog, priv->num_channels);
2742 
2743 	up = netif_running(dev);
2744 	need_update = (!!priv->xdp_prog != !!prog);
2745 
2746 	if (up)
2747 		dev_close(dev);
2748 
2749 	/* While in xdp mode, enforce a maximum Rx frame size based on MTU.
2750 	 * Also, when switching between xdp/non-xdp modes we need to reconfigure
2751 	 * our Rx buffer layout. Buffer pool was drained on dpaa2_eth_stop,
2752 	 * so we are sure no old format buffers will be used from now on.
2753 	 */
2754 	if (need_update) {
2755 		err = dpaa2_eth_set_rx_mfl(priv, dev->mtu, !!prog);
2756 		if (err)
2757 			goto out_err;
2758 		err = dpaa2_eth_update_rx_buffer_headroom(priv, !!prog);
2759 		if (err)
2760 			goto out_err;
2761 	}
2762 
2763 	old = xchg(&priv->xdp_prog, prog);
2764 	if (old)
2765 		bpf_prog_put(old);
2766 
2767 	for (i = 0; i < priv->num_channels; i++) {
2768 		ch = priv->channel[i];
2769 		old = xchg(&ch->xdp.prog, prog);
2770 		if (old)
2771 			bpf_prog_put(old);
2772 	}
2773 
2774 	if (up) {
2775 		err = dev_open(dev, NULL);
2776 		if (err)
2777 			return err;
2778 	}
2779 
2780 	return 0;
2781 
2782 out_err:
2783 	if (prog)
2784 		bpf_prog_sub(prog, priv->num_channels);
2785 	if (up)
2786 		dev_open(dev, NULL);
2787 
2788 	return err;
2789 }
2790 
2791 static int dpaa2_eth_xdp(struct net_device *dev, struct netdev_bpf *xdp)
2792 {
2793 	switch (xdp->command) {
2794 	case XDP_SETUP_PROG:
2795 		return dpaa2_eth_setup_xdp(dev, xdp->prog);
2796 	case XDP_SETUP_XSK_POOL:
2797 		return dpaa2_xsk_setup_pool(dev, xdp->xsk.pool, xdp->xsk.queue_id);
2798 	default:
2799 		return -EINVAL;
2800 	}
2801 
2802 	return 0;
2803 }
2804 
2805 static int dpaa2_eth_xdp_create_fd(struct net_device *net_dev,
2806 				   struct xdp_frame *xdpf,
2807 				   struct dpaa2_fd *fd)
2808 {
2809 	struct device *dev = net_dev->dev.parent;
2810 	unsigned int needed_headroom;
2811 	struct dpaa2_eth_swa *swa;
2812 	void *buffer_start, *aligned_start;
2813 	dma_addr_t addr;
2814 
2815 	/* We require a minimum headroom to be able to transmit the frame.
2816 	 * Otherwise return an error and let the original net_device handle it
2817 	 */
2818 	needed_headroom = dpaa2_eth_needed_headroom(NULL);
2819 	if (xdpf->headroom < needed_headroom)
2820 		return -EINVAL;
2821 
2822 	/* Setup the FD fields */
2823 	memset(fd, 0, sizeof(*fd));
2824 
2825 	/* Align FD address, if possible */
2826 	buffer_start = xdpf->data - needed_headroom;
2827 	aligned_start = PTR_ALIGN(buffer_start - DPAA2_ETH_TX_BUF_ALIGN,
2828 				  DPAA2_ETH_TX_BUF_ALIGN);
2829 	if (aligned_start >= xdpf->data - xdpf->headroom)
2830 		buffer_start = aligned_start;
2831 
2832 	swa = (struct dpaa2_eth_swa *)buffer_start;
2833 	/* fill in necessary fields here */
2834 	swa->type = DPAA2_ETH_SWA_XDP;
2835 	swa->xdp.dma_size = xdpf->data + xdpf->len - buffer_start;
2836 	swa->xdp.xdpf = xdpf;
2837 
2838 	addr = dma_map_single(dev, buffer_start,
2839 			      swa->xdp.dma_size,
2840 			      DMA_BIDIRECTIONAL);
2841 	if (unlikely(dma_mapping_error(dev, addr)))
2842 		return -ENOMEM;
2843 
2844 	dpaa2_fd_set_addr(fd, addr);
2845 	dpaa2_fd_set_offset(fd, xdpf->data - buffer_start);
2846 	dpaa2_fd_set_len(fd, xdpf->len);
2847 	dpaa2_fd_set_format(fd, dpaa2_fd_single);
2848 	dpaa2_fd_set_ctrl(fd, FD_CTRL_PTA);
2849 
2850 	return 0;
2851 }
2852 
2853 static int dpaa2_eth_xdp_xmit(struct net_device *net_dev, int n,
2854 			      struct xdp_frame **frames, u32 flags)
2855 {
2856 	struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
2857 	struct dpaa2_eth_xdp_fds *xdp_redirect_fds;
2858 	struct rtnl_link_stats64 *percpu_stats;
2859 	struct dpaa2_eth_fq *fq;
2860 	struct dpaa2_fd *fds;
2861 	int enqueued, i, err;
2862 
2863 	if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
2864 		return -EINVAL;
2865 
2866 	if (!netif_running(net_dev))
2867 		return -ENETDOWN;
2868 
2869 	fq = &priv->fq[smp_processor_id()];
2870 	xdp_redirect_fds = &fq->xdp_redirect_fds;
2871 	fds = xdp_redirect_fds->fds;
2872 
2873 	percpu_stats = this_cpu_ptr(priv->percpu_stats);
2874 
2875 	/* create a FD for each xdp_frame in the list received */
2876 	for (i = 0; i < n; i++) {
2877 		err = dpaa2_eth_xdp_create_fd(net_dev, frames[i], &fds[i]);
2878 		if (err)
2879 			break;
2880 	}
2881 	xdp_redirect_fds->num = i;
2882 
2883 	/* enqueue all the frame descriptors */
2884 	enqueued = dpaa2_eth_xdp_flush(priv, fq, xdp_redirect_fds);
2885 
2886 	/* update statistics */
2887 	percpu_stats->tx_packets += enqueued;
2888 	for (i = 0; i < enqueued; i++)
2889 		percpu_stats->tx_bytes += dpaa2_fd_get_len(&fds[i]);
2890 
2891 	return enqueued;
2892 }
2893 
2894 static int update_xps(struct dpaa2_eth_priv *priv)
2895 {
2896 	struct net_device *net_dev = priv->net_dev;
2897 	struct cpumask xps_mask;
2898 	struct dpaa2_eth_fq *fq;
2899 	int i, num_queues, netdev_queues;
2900 	int err = 0;
2901 
2902 	num_queues = dpaa2_eth_queue_count(priv);
2903 	netdev_queues = (net_dev->num_tc ? : 1) * num_queues;
2904 
2905 	/* The first <num_queues> entries in priv->fq array are Tx/Tx conf
2906 	 * queues, so only process those
2907 	 */
2908 	for (i = 0; i < netdev_queues; i++) {
2909 		fq = &priv->fq[i % num_queues];
2910 
2911 		cpumask_clear(&xps_mask);
2912 		cpumask_set_cpu(fq->target_cpu, &xps_mask);
2913 
2914 		err = netif_set_xps_queue(net_dev, &xps_mask, i);
2915 		if (err) {
2916 			netdev_warn_once(net_dev, "Error setting XPS queue\n");
2917 			break;
2918 		}
2919 	}
2920 
2921 	return err;
2922 }
2923 
2924 static int dpaa2_eth_setup_mqprio(struct net_device *net_dev,
2925 				  struct tc_mqprio_qopt *mqprio)
2926 {
2927 	struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
2928 	u8 num_tc, num_queues;
2929 	int i;
2930 
2931 	mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
2932 	num_queues = dpaa2_eth_queue_count(priv);
2933 	num_tc = mqprio->num_tc;
2934 
2935 	if (num_tc == net_dev->num_tc)
2936 		return 0;
2937 
2938 	if (num_tc  > dpaa2_eth_tc_count(priv)) {
2939 		netdev_err(net_dev, "Max %d traffic classes supported\n",
2940 			   dpaa2_eth_tc_count(priv));
2941 		return -EOPNOTSUPP;
2942 	}
2943 
2944 	if (!num_tc) {
2945 		netdev_reset_tc(net_dev);
2946 		netif_set_real_num_tx_queues(net_dev, num_queues);
2947 		goto out;
2948 	}
2949 
2950 	netdev_set_num_tc(net_dev, num_tc);
2951 	netif_set_real_num_tx_queues(net_dev, num_tc * num_queues);
2952 
2953 	for (i = 0; i < num_tc; i++)
2954 		netdev_set_tc_queue(net_dev, i, num_queues, i * num_queues);
2955 
2956 out:
2957 	update_xps(priv);
2958 
2959 	return 0;
2960 }
2961 
2962 #define bps_to_mbits(rate) (div_u64((rate), 1000000) * 8)
2963 
2964 static int dpaa2_eth_setup_tbf(struct net_device *net_dev, struct tc_tbf_qopt_offload *p)
2965 {
2966 	struct tc_tbf_qopt_offload_replace_params *cfg = &p->replace_params;
2967 	struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
2968 	struct dpni_tx_shaping_cfg tx_cr_shaper = { 0 };
2969 	struct dpni_tx_shaping_cfg tx_er_shaper = { 0 };
2970 	int err;
2971 
2972 	if (p->command == TC_TBF_STATS)
2973 		return -EOPNOTSUPP;
2974 
2975 	/* Only per port Tx shaping */
2976 	if (p->parent != TC_H_ROOT)
2977 		return -EOPNOTSUPP;
2978 
2979 	if (p->command == TC_TBF_REPLACE) {
2980 		if (cfg->max_size > DPAA2_ETH_MAX_BURST_SIZE) {
2981 			netdev_err(net_dev, "burst size cannot be greater than %d\n",
2982 				   DPAA2_ETH_MAX_BURST_SIZE);
2983 			return -EINVAL;
2984 		}
2985 
2986 		tx_cr_shaper.max_burst_size = cfg->max_size;
2987 		/* The TBF interface is in bytes/s, whereas DPAA2 expects the
2988 		 * rate in Mbits/s
2989 		 */
2990 		tx_cr_shaper.rate_limit = bps_to_mbits(cfg->rate.rate_bytes_ps);
2991 	}
2992 
2993 	err = dpni_set_tx_shaping(priv->mc_io, 0, priv->mc_token, &tx_cr_shaper,
2994 				  &tx_er_shaper, 0);
2995 	if (err) {
2996 		netdev_err(net_dev, "dpni_set_tx_shaping() = %d\n", err);
2997 		return err;
2998 	}
2999 
3000 	return 0;
3001 }
3002 
3003 static int dpaa2_eth_setup_tc(struct net_device *net_dev,
3004 			      enum tc_setup_type type, void *type_data)
3005 {
3006 	switch (type) {
3007 	case TC_SETUP_QDISC_MQPRIO:
3008 		return dpaa2_eth_setup_mqprio(net_dev, type_data);
3009 	case TC_SETUP_QDISC_TBF:
3010 		return dpaa2_eth_setup_tbf(net_dev, type_data);
3011 	default:
3012 		return -EOPNOTSUPP;
3013 	}
3014 }
3015 
3016 static const struct net_device_ops dpaa2_eth_ops = {
3017 	.ndo_open = dpaa2_eth_open,
3018 	.ndo_start_xmit = dpaa2_eth_tx,
3019 	.ndo_stop = dpaa2_eth_stop,
3020 	.ndo_set_mac_address = dpaa2_eth_set_addr,
3021 	.ndo_get_stats64 = dpaa2_eth_get_stats,
3022 	.ndo_set_rx_mode = dpaa2_eth_set_rx_mode,
3023 	.ndo_set_features = dpaa2_eth_set_features,
3024 	.ndo_eth_ioctl = dpaa2_eth_ioctl,
3025 	.ndo_change_mtu = dpaa2_eth_change_mtu,
3026 	.ndo_bpf = dpaa2_eth_xdp,
3027 	.ndo_xdp_xmit = dpaa2_eth_xdp_xmit,
3028 	.ndo_xsk_wakeup = dpaa2_xsk_wakeup,
3029 	.ndo_setup_tc = dpaa2_eth_setup_tc,
3030 	.ndo_vlan_rx_add_vid = dpaa2_eth_rx_add_vid,
3031 	.ndo_vlan_rx_kill_vid = dpaa2_eth_rx_kill_vid
3032 };
3033 
3034 static void dpaa2_eth_cdan_cb(struct dpaa2_io_notification_ctx *ctx)
3035 {
3036 	struct dpaa2_eth_channel *ch;
3037 
3038 	ch = container_of(ctx, struct dpaa2_eth_channel, nctx);
3039 
3040 	/* Update NAPI statistics */
3041 	ch->stats.cdan++;
3042 
3043 	/* NAPI can also be scheduled from the AF_XDP Tx path. Mark a missed
3044 	 * so that it can be rescheduled again.
3045 	 */
3046 	if (!napi_if_scheduled_mark_missed(&ch->napi))
3047 		napi_schedule(&ch->napi);
3048 }
3049 
3050 /* Allocate and configure a DPCON object */
3051 static struct fsl_mc_device *dpaa2_eth_setup_dpcon(struct dpaa2_eth_priv *priv)
3052 {
3053 	struct fsl_mc_device *dpcon;
3054 	struct device *dev = priv->net_dev->dev.parent;
3055 	int err;
3056 
3057 	err = fsl_mc_object_allocate(to_fsl_mc_device(dev),
3058 				     FSL_MC_POOL_DPCON, &dpcon);
3059 	if (err) {
3060 		if (err == -ENXIO) {
3061 			dev_dbg(dev, "Waiting for DPCON\n");
3062 			err = -EPROBE_DEFER;
3063 		} else {
3064 			dev_info(dev, "Not enough DPCONs, will go on as-is\n");
3065 		}
3066 		return ERR_PTR(err);
3067 	}
3068 
3069 	err = dpcon_open(priv->mc_io, 0, dpcon->obj_desc.id, &dpcon->mc_handle);
3070 	if (err) {
3071 		dev_err(dev, "dpcon_open() failed\n");
3072 		goto free;
3073 	}
3074 
3075 	err = dpcon_reset(priv->mc_io, 0, dpcon->mc_handle);
3076 	if (err) {
3077 		dev_err(dev, "dpcon_reset() failed\n");
3078 		goto close;
3079 	}
3080 
3081 	err = dpcon_enable(priv->mc_io, 0, dpcon->mc_handle);
3082 	if (err) {
3083 		dev_err(dev, "dpcon_enable() failed\n");
3084 		goto close;
3085 	}
3086 
3087 	return dpcon;
3088 
3089 close:
3090 	dpcon_close(priv->mc_io, 0, dpcon->mc_handle);
3091 free:
3092 	fsl_mc_object_free(dpcon);
3093 
3094 	return ERR_PTR(err);
3095 }
3096 
3097 static void dpaa2_eth_free_dpcon(struct dpaa2_eth_priv *priv,
3098 				 struct fsl_mc_device *dpcon)
3099 {
3100 	dpcon_disable(priv->mc_io, 0, dpcon->mc_handle);
3101 	dpcon_close(priv->mc_io, 0, dpcon->mc_handle);
3102 	fsl_mc_object_free(dpcon);
3103 }
3104 
3105 static struct dpaa2_eth_channel *dpaa2_eth_alloc_channel(struct dpaa2_eth_priv *priv)
3106 {
3107 	struct dpaa2_eth_channel *channel;
3108 	struct dpcon_attr attr;
3109 	struct device *dev = priv->net_dev->dev.parent;
3110 	int err;
3111 
3112 	channel = kzalloc(sizeof(*channel), GFP_KERNEL);
3113 	if (!channel)
3114 		return NULL;
3115 
3116 	channel->dpcon = dpaa2_eth_setup_dpcon(priv);
3117 	if (IS_ERR(channel->dpcon)) {
3118 		err = PTR_ERR(channel->dpcon);
3119 		goto err_setup;
3120 	}
3121 
3122 	err = dpcon_get_attributes(priv->mc_io, 0, channel->dpcon->mc_handle,
3123 				   &attr);
3124 	if (err) {
3125 		dev_err(dev, "dpcon_get_attributes() failed\n");
3126 		goto err_get_attr;
3127 	}
3128 
3129 	channel->dpcon_id = attr.id;
3130 	channel->ch_id = attr.qbman_ch_id;
3131 	channel->priv = priv;
3132 
3133 	return channel;
3134 
3135 err_get_attr:
3136 	dpaa2_eth_free_dpcon(priv, channel->dpcon);
3137 err_setup:
3138 	kfree(channel);
3139 	return ERR_PTR(err);
3140 }
3141 
3142 static void dpaa2_eth_free_channel(struct dpaa2_eth_priv *priv,
3143 				   struct dpaa2_eth_channel *channel)
3144 {
3145 	dpaa2_eth_free_dpcon(priv, channel->dpcon);
3146 	kfree(channel);
3147 }
3148 
3149 /* DPIO setup: allocate and configure QBMan channels, setup core affinity
3150  * and register data availability notifications
3151  */
3152 static int dpaa2_eth_setup_dpio(struct dpaa2_eth_priv *priv)
3153 {
3154 	struct dpaa2_io_notification_ctx *nctx;
3155 	struct dpaa2_eth_channel *channel;
3156 	struct dpcon_notification_cfg dpcon_notif_cfg;
3157 	struct device *dev = priv->net_dev->dev.parent;
3158 	int i, err;
3159 
3160 	/* We want the ability to spread ingress traffic (RX, TX conf) to as
3161 	 * many cores as possible, so we need one channel for each core
3162 	 * (unless there's fewer queues than cores, in which case the extra
3163 	 * channels would be wasted).
3164 	 * Allocate one channel per core and register it to the core's
3165 	 * affine DPIO. If not enough channels are available for all cores
3166 	 * or if some cores don't have an affine DPIO, there will be no
3167 	 * ingress frame processing on those cores.
3168 	 */
3169 	cpumask_clear(&priv->dpio_cpumask);
3170 	for_each_online_cpu(i) {
3171 		/* Try to allocate a channel */
3172 		channel = dpaa2_eth_alloc_channel(priv);
3173 		if (IS_ERR_OR_NULL(channel)) {
3174 			err = PTR_ERR_OR_ZERO(channel);
3175 			if (err == -EPROBE_DEFER)
3176 				dev_dbg(dev, "waiting for affine channel\n");
3177 			else
3178 				dev_info(dev,
3179 					 "No affine channel for cpu %d and above\n", i);
3180 			goto err_alloc_ch;
3181 		}
3182 
3183 		priv->channel[priv->num_channels] = channel;
3184 
3185 		nctx = &channel->nctx;
3186 		nctx->is_cdan = 1;
3187 		nctx->cb = dpaa2_eth_cdan_cb;
3188 		nctx->id = channel->ch_id;
3189 		nctx->desired_cpu = i;
3190 
3191 		/* Register the new context */
3192 		channel->dpio = dpaa2_io_service_select(i);
3193 		err = dpaa2_io_service_register(channel->dpio, nctx, dev);
3194 		if (err) {
3195 			dev_dbg(dev, "No affine DPIO for cpu %d\n", i);
3196 			/* If no affine DPIO for this core, there's probably
3197 			 * none available for next cores either. Signal we want
3198 			 * to retry later, in case the DPIO devices weren't
3199 			 * probed yet.
3200 			 */
3201 			err = -EPROBE_DEFER;
3202 			goto err_service_reg;
3203 		}
3204 
3205 		/* Register DPCON notification with MC */
3206 		dpcon_notif_cfg.dpio_id = nctx->dpio_id;
3207 		dpcon_notif_cfg.priority = 0;
3208 		dpcon_notif_cfg.user_ctx = nctx->qman64;
3209 		err = dpcon_set_notification(priv->mc_io, 0,
3210 					     channel->dpcon->mc_handle,
3211 					     &dpcon_notif_cfg);
3212 		if (err) {
3213 			dev_err(dev, "dpcon_set_notification failed()\n");
3214 			goto err_set_cdan;
3215 		}
3216 
3217 		/* If we managed to allocate a channel and also found an affine
3218 		 * DPIO for this core, add it to the final mask
3219 		 */
3220 		cpumask_set_cpu(i, &priv->dpio_cpumask);
3221 		priv->num_channels++;
3222 
3223 		/* Stop if we already have enough channels to accommodate all
3224 		 * RX and TX conf queues
3225 		 */
3226 		if (priv->num_channels == priv->dpni_attrs.num_queues)
3227 			break;
3228 	}
3229 
3230 	return 0;
3231 
3232 err_set_cdan:
3233 	dpaa2_io_service_deregister(channel->dpio, nctx, dev);
3234 err_service_reg:
3235 	dpaa2_eth_free_channel(priv, channel);
3236 err_alloc_ch:
3237 	if (err == -EPROBE_DEFER) {
3238 		for (i = 0; i < priv->num_channels; i++) {
3239 			channel = priv->channel[i];
3240 			nctx = &channel->nctx;
3241 			dpaa2_io_service_deregister(channel->dpio, nctx, dev);
3242 			dpaa2_eth_free_channel(priv, channel);
3243 		}
3244 		priv->num_channels = 0;
3245 		return err;
3246 	}
3247 
3248 	if (cpumask_empty(&priv->dpio_cpumask)) {
3249 		dev_err(dev, "No cpu with an affine DPIO/DPCON\n");
3250 		return -ENODEV;
3251 	}
3252 
3253 	dev_info(dev, "Cores %*pbl available for processing ingress traffic\n",
3254 		 cpumask_pr_args(&priv->dpio_cpumask));
3255 
3256 	return 0;
3257 }
3258 
3259 static void dpaa2_eth_free_dpio(struct dpaa2_eth_priv *priv)
3260 {
3261 	struct device *dev = priv->net_dev->dev.parent;
3262 	struct dpaa2_eth_channel *ch;
3263 	int i;
3264 
3265 	/* deregister CDAN notifications and free channels */
3266 	for (i = 0; i < priv->num_channels; i++) {
3267 		ch = priv->channel[i];
3268 		dpaa2_io_service_deregister(ch->dpio, &ch->nctx, dev);
3269 		dpaa2_eth_free_channel(priv, ch);
3270 	}
3271 }
3272 
3273 static struct dpaa2_eth_channel *dpaa2_eth_get_affine_channel(struct dpaa2_eth_priv *priv,
3274 							      int cpu)
3275 {
3276 	struct device *dev = priv->net_dev->dev.parent;
3277 	int i;
3278 
3279 	for (i = 0; i < priv->num_channels; i++)
3280 		if (priv->channel[i]->nctx.desired_cpu == cpu)
3281 			return priv->channel[i];
3282 
3283 	/* We should never get here. Issue a warning and return
3284 	 * the first channel, because it's still better than nothing
3285 	 */
3286 	dev_warn(dev, "No affine channel found for cpu %d\n", cpu);
3287 
3288 	return priv->channel[0];
3289 }
3290 
3291 static void dpaa2_eth_set_fq_affinity(struct dpaa2_eth_priv *priv)
3292 {
3293 	struct device *dev = priv->net_dev->dev.parent;
3294 	struct dpaa2_eth_fq *fq;
3295 	int rx_cpu, txc_cpu;
3296 	int i;
3297 
3298 	/* For each FQ, pick one channel/CPU to deliver frames to.
3299 	 * This may well change at runtime, either through irqbalance or
3300 	 * through direct user intervention.
3301 	 */
3302 	rx_cpu = txc_cpu = cpumask_first(&priv->dpio_cpumask);
3303 
3304 	for (i = 0; i < priv->num_fqs; i++) {
3305 		fq = &priv->fq[i];
3306 		switch (fq->type) {
3307 		case DPAA2_RX_FQ:
3308 		case DPAA2_RX_ERR_FQ:
3309 			fq->target_cpu = rx_cpu;
3310 			rx_cpu = cpumask_next(rx_cpu, &priv->dpio_cpumask);
3311 			if (rx_cpu >= nr_cpu_ids)
3312 				rx_cpu = cpumask_first(&priv->dpio_cpumask);
3313 			break;
3314 		case DPAA2_TX_CONF_FQ:
3315 			fq->target_cpu = txc_cpu;
3316 			txc_cpu = cpumask_next(txc_cpu, &priv->dpio_cpumask);
3317 			if (txc_cpu >= nr_cpu_ids)
3318 				txc_cpu = cpumask_first(&priv->dpio_cpumask);
3319 			break;
3320 		default:
3321 			dev_err(dev, "Unknown FQ type: %d\n", fq->type);
3322 		}
3323 		fq->channel = dpaa2_eth_get_affine_channel(priv, fq->target_cpu);
3324 	}
3325 
3326 	update_xps(priv);
3327 }
3328 
3329 static void dpaa2_eth_setup_fqs(struct dpaa2_eth_priv *priv)
3330 {
3331 	int i, j;
3332 
3333 	/* We have one TxConf FQ per Tx flow.
3334 	 * The number of Tx and Rx queues is the same.
3335 	 * Tx queues come first in the fq array.
3336 	 */
3337 	for (i = 0; i < dpaa2_eth_queue_count(priv); i++) {
3338 		priv->fq[priv->num_fqs].type = DPAA2_TX_CONF_FQ;
3339 		priv->fq[priv->num_fqs].consume = dpaa2_eth_tx_conf;
3340 		priv->fq[priv->num_fqs++].flowid = (u16)i;
3341 	}
3342 
3343 	for (j = 0; j < dpaa2_eth_tc_count(priv); j++) {
3344 		for (i = 0; i < dpaa2_eth_queue_count(priv); i++) {
3345 			priv->fq[priv->num_fqs].type = DPAA2_RX_FQ;
3346 			priv->fq[priv->num_fqs].consume = dpaa2_eth_rx;
3347 			priv->fq[priv->num_fqs].tc = (u8)j;
3348 			priv->fq[priv->num_fqs++].flowid = (u16)i;
3349 		}
3350 	}
3351 
3352 	/* We have exactly one Rx error queue per DPNI */
3353 	priv->fq[priv->num_fqs].type = DPAA2_RX_ERR_FQ;
3354 	priv->fq[priv->num_fqs++].consume = dpaa2_eth_rx_err;
3355 
3356 	/* For each FQ, decide on which core to process incoming frames */
3357 	dpaa2_eth_set_fq_affinity(priv);
3358 }
3359 
3360 /* Allocate and configure a buffer pool */
3361 struct dpaa2_eth_bp *dpaa2_eth_allocate_dpbp(struct dpaa2_eth_priv *priv)
3362 {
3363 	struct device *dev = priv->net_dev->dev.parent;
3364 	struct fsl_mc_device *dpbp_dev;
3365 	struct dpbp_attr dpbp_attrs;
3366 	struct dpaa2_eth_bp *bp;
3367 	int err;
3368 
3369 	err = fsl_mc_object_allocate(to_fsl_mc_device(dev), FSL_MC_POOL_DPBP,
3370 				     &dpbp_dev);
3371 	if (err) {
3372 		if (err == -ENXIO)
3373 			err = -EPROBE_DEFER;
3374 		else
3375 			dev_err(dev, "DPBP device allocation failed\n");
3376 		return ERR_PTR(err);
3377 	}
3378 
3379 	bp = kzalloc(sizeof(*bp), GFP_KERNEL);
3380 	if (!bp) {
3381 		err = -ENOMEM;
3382 		goto err_alloc;
3383 	}
3384 
3385 	err = dpbp_open(priv->mc_io, 0, dpbp_dev->obj_desc.id,
3386 			&dpbp_dev->mc_handle);
3387 	if (err) {
3388 		dev_err(dev, "dpbp_open() failed\n");
3389 		goto err_open;
3390 	}
3391 
3392 	err = dpbp_reset(priv->mc_io, 0, dpbp_dev->mc_handle);
3393 	if (err) {
3394 		dev_err(dev, "dpbp_reset() failed\n");
3395 		goto err_reset;
3396 	}
3397 
3398 	err = dpbp_enable(priv->mc_io, 0, dpbp_dev->mc_handle);
3399 	if (err) {
3400 		dev_err(dev, "dpbp_enable() failed\n");
3401 		goto err_enable;
3402 	}
3403 
3404 	err = dpbp_get_attributes(priv->mc_io, 0, dpbp_dev->mc_handle,
3405 				  &dpbp_attrs);
3406 	if (err) {
3407 		dev_err(dev, "dpbp_get_attributes() failed\n");
3408 		goto err_get_attr;
3409 	}
3410 
3411 	bp->dev = dpbp_dev;
3412 	bp->bpid = dpbp_attrs.bpid;
3413 
3414 	return bp;
3415 
3416 err_get_attr:
3417 	dpbp_disable(priv->mc_io, 0, dpbp_dev->mc_handle);
3418 err_enable:
3419 err_reset:
3420 	dpbp_close(priv->mc_io, 0, dpbp_dev->mc_handle);
3421 err_open:
3422 	kfree(bp);
3423 err_alloc:
3424 	fsl_mc_object_free(dpbp_dev);
3425 
3426 	return ERR_PTR(err);
3427 }
3428 
3429 static int dpaa2_eth_setup_default_dpbp(struct dpaa2_eth_priv *priv)
3430 {
3431 	struct dpaa2_eth_bp *bp;
3432 	int i;
3433 
3434 	bp = dpaa2_eth_allocate_dpbp(priv);
3435 	if (IS_ERR(bp))
3436 		return PTR_ERR(bp);
3437 
3438 	priv->bp[DPAA2_ETH_DEFAULT_BP_IDX] = bp;
3439 	priv->num_bps++;
3440 
3441 	for (i = 0; i < priv->num_channels; i++)
3442 		priv->channel[i]->bp = bp;
3443 
3444 	return 0;
3445 }
3446 
3447 void dpaa2_eth_free_dpbp(struct dpaa2_eth_priv *priv, struct dpaa2_eth_bp *bp)
3448 {
3449 	int idx_bp;
3450 
3451 	/* Find the index at which this BP is stored */
3452 	for (idx_bp = 0; idx_bp < priv->num_bps; idx_bp++)
3453 		if (priv->bp[idx_bp] == bp)
3454 			break;
3455 
3456 	/* Drain the pool and disable the associated MC object */
3457 	dpaa2_eth_drain_pool(priv, bp->bpid);
3458 	dpbp_disable(priv->mc_io, 0, bp->dev->mc_handle);
3459 	dpbp_close(priv->mc_io, 0, bp->dev->mc_handle);
3460 	fsl_mc_object_free(bp->dev);
3461 	kfree(bp);
3462 
3463 	/* Move the last in use DPBP over in this position */
3464 	priv->bp[idx_bp] = priv->bp[priv->num_bps - 1];
3465 	priv->num_bps--;
3466 }
3467 
3468 static void dpaa2_eth_free_dpbps(struct dpaa2_eth_priv *priv)
3469 {
3470 	int i;
3471 
3472 	for (i = 0; i < priv->num_bps; i++)
3473 		dpaa2_eth_free_dpbp(priv, priv->bp[i]);
3474 }
3475 
3476 static int dpaa2_eth_set_buffer_layout(struct dpaa2_eth_priv *priv)
3477 {
3478 	struct device *dev = priv->net_dev->dev.parent;
3479 	struct dpni_buffer_layout buf_layout = {0};
3480 	u16 rx_buf_align;
3481 	int err;
3482 
3483 	/* We need to check for WRIOP version 1.0.0, but depending on the MC
3484 	 * version, this number is not always provided correctly on rev1.
3485 	 * We need to check for both alternatives in this situation.
3486 	 */
3487 	if (priv->dpni_attrs.wriop_version == DPAA2_WRIOP_VERSION(0, 0, 0) ||
3488 	    priv->dpni_attrs.wriop_version == DPAA2_WRIOP_VERSION(1, 0, 0))
3489 		rx_buf_align = DPAA2_ETH_RX_BUF_ALIGN_REV1;
3490 	else
3491 		rx_buf_align = DPAA2_ETH_RX_BUF_ALIGN;
3492 
3493 	/* We need to ensure that the buffer size seen by WRIOP is a multiple
3494 	 * of 64 or 256 bytes depending on the WRIOP version.
3495 	 */
3496 	priv->rx_buf_size = ALIGN_DOWN(DPAA2_ETH_RX_BUF_SIZE, rx_buf_align);
3497 
3498 	/* tx buffer */
3499 	buf_layout.private_data_size = DPAA2_ETH_SWA_SIZE;
3500 	buf_layout.pass_timestamp = true;
3501 	buf_layout.pass_frame_status = true;
3502 	buf_layout.options = DPNI_BUF_LAYOUT_OPT_PRIVATE_DATA_SIZE |
3503 			     DPNI_BUF_LAYOUT_OPT_TIMESTAMP |
3504 			     DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
3505 	err = dpni_set_buffer_layout(priv->mc_io, 0, priv->mc_token,
3506 				     DPNI_QUEUE_TX, &buf_layout);
3507 	if (err) {
3508 		dev_err(dev, "dpni_set_buffer_layout(TX) failed\n");
3509 		return err;
3510 	}
3511 
3512 	/* tx-confirm buffer */
3513 	buf_layout.options = DPNI_BUF_LAYOUT_OPT_TIMESTAMP |
3514 			     DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
3515 	err = dpni_set_buffer_layout(priv->mc_io, 0, priv->mc_token,
3516 				     DPNI_QUEUE_TX_CONFIRM, &buf_layout);
3517 	if (err) {
3518 		dev_err(dev, "dpni_set_buffer_layout(TX_CONF) failed\n");
3519 		return err;
3520 	}
3521 
3522 	/* Now that we've set our tx buffer layout, retrieve the minimum
3523 	 * required tx data offset.
3524 	 */
3525 	err = dpni_get_tx_data_offset(priv->mc_io, 0, priv->mc_token,
3526 				      &priv->tx_data_offset);
3527 	if (err) {
3528 		dev_err(dev, "dpni_get_tx_data_offset() failed\n");
3529 		return err;
3530 	}
3531 
3532 	if ((priv->tx_data_offset % 64) != 0)
3533 		dev_warn(dev, "Tx data offset (%d) not a multiple of 64B\n",
3534 			 priv->tx_data_offset);
3535 
3536 	/* rx buffer */
3537 	buf_layout.pass_frame_status = true;
3538 	buf_layout.pass_parser_result = true;
3539 	buf_layout.data_align = rx_buf_align;
3540 	buf_layout.data_head_room = dpaa2_eth_rx_head_room(priv);
3541 	buf_layout.private_data_size = 0;
3542 	buf_layout.options = DPNI_BUF_LAYOUT_OPT_PARSER_RESULT |
3543 			     DPNI_BUF_LAYOUT_OPT_FRAME_STATUS |
3544 			     DPNI_BUF_LAYOUT_OPT_DATA_ALIGN |
3545 			     DPNI_BUF_LAYOUT_OPT_DATA_HEAD_ROOM |
3546 			     DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
3547 	err = dpni_set_buffer_layout(priv->mc_io, 0, priv->mc_token,
3548 				     DPNI_QUEUE_RX, &buf_layout);
3549 	if (err) {
3550 		dev_err(dev, "dpni_set_buffer_layout(RX) failed\n");
3551 		return err;
3552 	}
3553 
3554 	return 0;
3555 }
3556 
3557 #define DPNI_ENQUEUE_FQID_VER_MAJOR	7
3558 #define DPNI_ENQUEUE_FQID_VER_MINOR	9
3559 
3560 static inline int dpaa2_eth_enqueue_qd(struct dpaa2_eth_priv *priv,
3561 				       struct dpaa2_eth_fq *fq,
3562 				       struct dpaa2_fd *fd, u8 prio,
3563 				       u32 num_frames __always_unused,
3564 				       int *frames_enqueued)
3565 {
3566 	int err;
3567 
3568 	err = dpaa2_io_service_enqueue_qd(fq->channel->dpio,
3569 					  priv->tx_qdid, prio,
3570 					  fq->tx_qdbin, fd);
3571 	if (!err && frames_enqueued)
3572 		*frames_enqueued = 1;
3573 	return err;
3574 }
3575 
3576 static inline int dpaa2_eth_enqueue_fq_multiple(struct dpaa2_eth_priv *priv,
3577 						struct dpaa2_eth_fq *fq,
3578 						struct dpaa2_fd *fd,
3579 						u8 prio, u32 num_frames,
3580 						int *frames_enqueued)
3581 {
3582 	int err;
3583 
3584 	err = dpaa2_io_service_enqueue_multiple_fq(fq->channel->dpio,
3585 						   fq->tx_fqid[prio],
3586 						   fd, num_frames);
3587 
3588 	if (err == 0)
3589 		return -EBUSY;
3590 
3591 	if (frames_enqueued)
3592 		*frames_enqueued = err;
3593 	return 0;
3594 }
3595 
3596 static void dpaa2_eth_set_enqueue_mode(struct dpaa2_eth_priv *priv)
3597 {
3598 	if (dpaa2_eth_cmp_dpni_ver(priv, DPNI_ENQUEUE_FQID_VER_MAJOR,
3599 				   DPNI_ENQUEUE_FQID_VER_MINOR) < 0)
3600 		priv->enqueue = dpaa2_eth_enqueue_qd;
3601 	else
3602 		priv->enqueue = dpaa2_eth_enqueue_fq_multiple;
3603 }
3604 
3605 static int dpaa2_eth_set_pause(struct dpaa2_eth_priv *priv)
3606 {
3607 	struct device *dev = priv->net_dev->dev.parent;
3608 	struct dpni_link_cfg link_cfg = {0};
3609 	int err;
3610 
3611 	/* Get the default link options so we don't override other flags */
3612 	err = dpni_get_link_cfg(priv->mc_io, 0, priv->mc_token, &link_cfg);
3613 	if (err) {
3614 		dev_err(dev, "dpni_get_link_cfg() failed\n");
3615 		return err;
3616 	}
3617 
3618 	/* By default, enable both Rx and Tx pause frames */
3619 	link_cfg.options |= DPNI_LINK_OPT_PAUSE;
3620 	link_cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE;
3621 	err = dpni_set_link_cfg(priv->mc_io, 0, priv->mc_token, &link_cfg);
3622 	if (err) {
3623 		dev_err(dev, "dpni_set_link_cfg() failed\n");
3624 		return err;
3625 	}
3626 
3627 	priv->link_state.options = link_cfg.options;
3628 
3629 	return 0;
3630 }
3631 
3632 static void dpaa2_eth_update_tx_fqids(struct dpaa2_eth_priv *priv)
3633 {
3634 	struct dpni_queue_id qid = {0};
3635 	struct dpaa2_eth_fq *fq;
3636 	struct dpni_queue queue;
3637 	int i, j, err;
3638 
3639 	/* We only use Tx FQIDs for FQID-based enqueue, so check
3640 	 * if DPNI version supports it before updating FQIDs
3641 	 */
3642 	if (dpaa2_eth_cmp_dpni_ver(priv, DPNI_ENQUEUE_FQID_VER_MAJOR,
3643 				   DPNI_ENQUEUE_FQID_VER_MINOR) < 0)
3644 		return;
3645 
3646 	for (i = 0; i < priv->num_fqs; i++) {
3647 		fq = &priv->fq[i];
3648 		if (fq->type != DPAA2_TX_CONF_FQ)
3649 			continue;
3650 		for (j = 0; j < dpaa2_eth_tc_count(priv); j++) {
3651 			err = dpni_get_queue(priv->mc_io, 0, priv->mc_token,
3652 					     DPNI_QUEUE_TX, j, fq->flowid,
3653 					     &queue, &qid);
3654 			if (err)
3655 				goto out_err;
3656 
3657 			fq->tx_fqid[j] = qid.fqid;
3658 			if (fq->tx_fqid[j] == 0)
3659 				goto out_err;
3660 		}
3661 	}
3662 
3663 	priv->enqueue = dpaa2_eth_enqueue_fq_multiple;
3664 
3665 	return;
3666 
3667 out_err:
3668 	netdev_info(priv->net_dev,
3669 		    "Error reading Tx FQID, fallback to QDID-based enqueue\n");
3670 	priv->enqueue = dpaa2_eth_enqueue_qd;
3671 }
3672 
3673 /* Configure ingress classification based on VLAN PCP */
3674 static int dpaa2_eth_set_vlan_qos(struct dpaa2_eth_priv *priv)
3675 {
3676 	struct device *dev = priv->net_dev->dev.parent;
3677 	struct dpkg_profile_cfg kg_cfg = {0};
3678 	struct dpni_qos_tbl_cfg qos_cfg = {0};
3679 	struct dpni_rule_cfg key_params;
3680 	void *dma_mem, *key, *mask;
3681 	u8 key_size = 2;	/* VLAN TCI field */
3682 	int i, pcp, err;
3683 
3684 	/* VLAN-based classification only makes sense if we have multiple
3685 	 * traffic classes.
3686 	 * Also, we need to extract just the 3-bit PCP field from the VLAN
3687 	 * header and we can only do that by using a mask
3688 	 */
3689 	if (dpaa2_eth_tc_count(priv) == 1 || !dpaa2_eth_fs_mask_enabled(priv)) {
3690 		dev_dbg(dev, "VLAN-based QoS classification not supported\n");
3691 		return -EOPNOTSUPP;
3692 	}
3693 
3694 	dma_mem = kzalloc(DPAA2_CLASSIFIER_DMA_SIZE, GFP_KERNEL);
3695 	if (!dma_mem)
3696 		return -ENOMEM;
3697 
3698 	kg_cfg.num_extracts = 1;
3699 	kg_cfg.extracts[0].type = DPKG_EXTRACT_FROM_HDR;
3700 	kg_cfg.extracts[0].extract.from_hdr.prot = NET_PROT_VLAN;
3701 	kg_cfg.extracts[0].extract.from_hdr.type = DPKG_FULL_FIELD;
3702 	kg_cfg.extracts[0].extract.from_hdr.field = NH_FLD_VLAN_TCI;
3703 
3704 	err = dpni_prepare_key_cfg(&kg_cfg, dma_mem);
3705 	if (err) {
3706 		dev_err(dev, "dpni_prepare_key_cfg failed\n");
3707 		goto out_free_tbl;
3708 	}
3709 
3710 	/* set QoS table */
3711 	qos_cfg.default_tc = 0;
3712 	qos_cfg.discard_on_miss = 0;
3713 	qos_cfg.key_cfg_iova = dma_map_single(dev, dma_mem,
3714 					      DPAA2_CLASSIFIER_DMA_SIZE,
3715 					      DMA_TO_DEVICE);
3716 	if (dma_mapping_error(dev, qos_cfg.key_cfg_iova)) {
3717 		dev_err(dev, "QoS table DMA mapping failed\n");
3718 		err = -ENOMEM;
3719 		goto out_free_tbl;
3720 	}
3721 
3722 	err = dpni_set_qos_table(priv->mc_io, 0, priv->mc_token, &qos_cfg);
3723 	if (err) {
3724 		dev_err(dev, "dpni_set_qos_table failed\n");
3725 		goto out_unmap_tbl;
3726 	}
3727 
3728 	/* Add QoS table entries */
3729 	key = kzalloc(key_size * 2, GFP_KERNEL);
3730 	if (!key) {
3731 		err = -ENOMEM;
3732 		goto out_unmap_tbl;
3733 	}
3734 	mask = key + key_size;
3735 	*(__be16 *)mask = cpu_to_be16(VLAN_PRIO_MASK);
3736 
3737 	key_params.key_iova = dma_map_single(dev, key, key_size * 2,
3738 					     DMA_TO_DEVICE);
3739 	if (dma_mapping_error(dev, key_params.key_iova)) {
3740 		dev_err(dev, "Qos table entry DMA mapping failed\n");
3741 		err = -ENOMEM;
3742 		goto out_free_key;
3743 	}
3744 
3745 	key_params.mask_iova = key_params.key_iova + key_size;
3746 	key_params.key_size = key_size;
3747 
3748 	/* We add rules for PCP-based distribution starting with highest
3749 	 * priority (VLAN PCP = 7). If this DPNI doesn't have enough traffic
3750 	 * classes to accommodate all priority levels, the lowest ones end up
3751 	 * on TC 0 which was configured as default
3752 	 */
3753 	for (i = dpaa2_eth_tc_count(priv) - 1, pcp = 7; i >= 0; i--, pcp--) {
3754 		*(__be16 *)key = cpu_to_be16(pcp << VLAN_PRIO_SHIFT);
3755 		dma_sync_single_for_device(dev, key_params.key_iova,
3756 					   key_size * 2, DMA_TO_DEVICE);
3757 
3758 		err = dpni_add_qos_entry(priv->mc_io, 0, priv->mc_token,
3759 					 &key_params, i, i);
3760 		if (err) {
3761 			dev_err(dev, "dpni_add_qos_entry failed\n");
3762 			dpni_clear_qos_table(priv->mc_io, 0, priv->mc_token);
3763 			goto out_unmap_key;
3764 		}
3765 	}
3766 
3767 	priv->vlan_cls_enabled = true;
3768 
3769 	/* Table and key memory is not persistent, clean everything up after
3770 	 * configuration is finished
3771 	 */
3772 out_unmap_key:
3773 	dma_unmap_single(dev, key_params.key_iova, key_size * 2, DMA_TO_DEVICE);
3774 out_free_key:
3775 	kfree(key);
3776 out_unmap_tbl:
3777 	dma_unmap_single(dev, qos_cfg.key_cfg_iova, DPAA2_CLASSIFIER_DMA_SIZE,
3778 			 DMA_TO_DEVICE);
3779 out_free_tbl:
3780 	kfree(dma_mem);
3781 
3782 	return err;
3783 }
3784 
3785 /* Configure the DPNI object this interface is associated with */
3786 static int dpaa2_eth_setup_dpni(struct fsl_mc_device *ls_dev)
3787 {
3788 	struct device *dev = &ls_dev->dev;
3789 	struct dpaa2_eth_priv *priv;
3790 	struct net_device *net_dev;
3791 	int err;
3792 
3793 	net_dev = dev_get_drvdata(dev);
3794 	priv = netdev_priv(net_dev);
3795 
3796 	/* get a handle for the DPNI object */
3797 	err = dpni_open(priv->mc_io, 0, ls_dev->obj_desc.id, &priv->mc_token);
3798 	if (err) {
3799 		dev_err(dev, "dpni_open() failed\n");
3800 		return err;
3801 	}
3802 
3803 	/* Check if we can work with this DPNI object */
3804 	err = dpni_get_api_version(priv->mc_io, 0, &priv->dpni_ver_major,
3805 				   &priv->dpni_ver_minor);
3806 	if (err) {
3807 		dev_err(dev, "dpni_get_api_version() failed\n");
3808 		goto close;
3809 	}
3810 	if (dpaa2_eth_cmp_dpni_ver(priv, DPNI_VER_MAJOR, DPNI_VER_MINOR) < 0) {
3811 		dev_err(dev, "DPNI version %u.%u not supported, need >= %u.%u\n",
3812 			priv->dpni_ver_major, priv->dpni_ver_minor,
3813 			DPNI_VER_MAJOR, DPNI_VER_MINOR);
3814 		err = -EOPNOTSUPP;
3815 		goto close;
3816 	}
3817 
3818 	ls_dev->mc_io = priv->mc_io;
3819 	ls_dev->mc_handle = priv->mc_token;
3820 
3821 	err = dpni_reset(priv->mc_io, 0, priv->mc_token);
3822 	if (err) {
3823 		dev_err(dev, "dpni_reset() failed\n");
3824 		goto close;
3825 	}
3826 
3827 	err = dpni_get_attributes(priv->mc_io, 0, priv->mc_token,
3828 				  &priv->dpni_attrs);
3829 	if (err) {
3830 		dev_err(dev, "dpni_get_attributes() failed (err=%d)\n", err);
3831 		goto close;
3832 	}
3833 
3834 	err = dpaa2_eth_set_buffer_layout(priv);
3835 	if (err)
3836 		goto close;
3837 
3838 	dpaa2_eth_set_enqueue_mode(priv);
3839 
3840 	/* Enable pause frame support */
3841 	if (dpaa2_eth_has_pause_support(priv)) {
3842 		err = dpaa2_eth_set_pause(priv);
3843 		if (err)
3844 			goto close;
3845 	}
3846 
3847 	err = dpaa2_eth_set_vlan_qos(priv);
3848 	if (err && err != -EOPNOTSUPP)
3849 		goto close;
3850 
3851 	priv->cls_rules = devm_kcalloc(dev, dpaa2_eth_fs_count(priv),
3852 				       sizeof(struct dpaa2_eth_cls_rule),
3853 				       GFP_KERNEL);
3854 	if (!priv->cls_rules) {
3855 		err = -ENOMEM;
3856 		goto close;
3857 	}
3858 
3859 	return 0;
3860 
3861 close:
3862 	dpni_close(priv->mc_io, 0, priv->mc_token);
3863 
3864 	return err;
3865 }
3866 
3867 static void dpaa2_eth_free_dpni(struct dpaa2_eth_priv *priv)
3868 {
3869 	int err;
3870 
3871 	err = dpni_reset(priv->mc_io, 0, priv->mc_token);
3872 	if (err)
3873 		netdev_warn(priv->net_dev, "dpni_reset() failed (err %d)\n",
3874 			    err);
3875 
3876 	dpni_close(priv->mc_io, 0, priv->mc_token);
3877 }
3878 
3879 static int dpaa2_eth_setup_rx_flow(struct dpaa2_eth_priv *priv,
3880 				   struct dpaa2_eth_fq *fq)
3881 {
3882 	struct device *dev = priv->net_dev->dev.parent;
3883 	struct dpni_queue queue;
3884 	struct dpni_queue_id qid;
3885 	int err;
3886 
3887 	err = dpni_get_queue(priv->mc_io, 0, priv->mc_token,
3888 			     DPNI_QUEUE_RX, fq->tc, fq->flowid, &queue, &qid);
3889 	if (err) {
3890 		dev_err(dev, "dpni_get_queue(RX) failed\n");
3891 		return err;
3892 	}
3893 
3894 	fq->fqid = qid.fqid;
3895 
3896 	queue.destination.id = fq->channel->dpcon_id;
3897 	queue.destination.type = DPNI_DEST_DPCON;
3898 	queue.destination.priority = 1;
3899 	queue.user_context = (u64)(uintptr_t)fq;
3900 	err = dpni_set_queue(priv->mc_io, 0, priv->mc_token,
3901 			     DPNI_QUEUE_RX, fq->tc, fq->flowid,
3902 			     DPNI_QUEUE_OPT_USER_CTX | DPNI_QUEUE_OPT_DEST,
3903 			     &queue);
3904 	if (err) {
3905 		dev_err(dev, "dpni_set_queue(RX) failed\n");
3906 		return err;
3907 	}
3908 
3909 	/* xdp_rxq setup */
3910 	/* only once for each channel */
3911 	if (fq->tc > 0)
3912 		return 0;
3913 
3914 	err = xdp_rxq_info_reg(&fq->channel->xdp_rxq, priv->net_dev,
3915 			       fq->flowid, 0);
3916 	if (err) {
3917 		dev_err(dev, "xdp_rxq_info_reg failed\n");
3918 		return err;
3919 	}
3920 
3921 	err = xdp_rxq_info_reg_mem_model(&fq->channel->xdp_rxq,
3922 					 MEM_TYPE_PAGE_ORDER0, NULL);
3923 	if (err) {
3924 		dev_err(dev, "xdp_rxq_info_reg_mem_model failed\n");
3925 		return err;
3926 	}
3927 
3928 	return 0;
3929 }
3930 
3931 static int dpaa2_eth_setup_tx_flow(struct dpaa2_eth_priv *priv,
3932 				   struct dpaa2_eth_fq *fq)
3933 {
3934 	struct device *dev = priv->net_dev->dev.parent;
3935 	struct dpni_queue queue;
3936 	struct dpni_queue_id qid;
3937 	int i, err;
3938 
3939 	for (i = 0; i < dpaa2_eth_tc_count(priv); i++) {
3940 		err = dpni_get_queue(priv->mc_io, 0, priv->mc_token,
3941 				     DPNI_QUEUE_TX, i, fq->flowid,
3942 				     &queue, &qid);
3943 		if (err) {
3944 			dev_err(dev, "dpni_get_queue(TX) failed\n");
3945 			return err;
3946 		}
3947 		fq->tx_fqid[i] = qid.fqid;
3948 	}
3949 
3950 	/* All Tx queues belonging to the same flowid have the same qdbin */
3951 	fq->tx_qdbin = qid.qdbin;
3952 
3953 	err = dpni_get_queue(priv->mc_io, 0, priv->mc_token,
3954 			     DPNI_QUEUE_TX_CONFIRM, 0, fq->flowid,
3955 			     &queue, &qid);
3956 	if (err) {
3957 		dev_err(dev, "dpni_get_queue(TX_CONF) failed\n");
3958 		return err;
3959 	}
3960 
3961 	fq->fqid = qid.fqid;
3962 
3963 	queue.destination.id = fq->channel->dpcon_id;
3964 	queue.destination.type = DPNI_DEST_DPCON;
3965 	queue.destination.priority = 0;
3966 	queue.user_context = (u64)(uintptr_t)fq;
3967 	err = dpni_set_queue(priv->mc_io, 0, priv->mc_token,
3968 			     DPNI_QUEUE_TX_CONFIRM, 0, fq->flowid,
3969 			     DPNI_QUEUE_OPT_USER_CTX | DPNI_QUEUE_OPT_DEST,
3970 			     &queue);
3971 	if (err) {
3972 		dev_err(dev, "dpni_set_queue(TX_CONF) failed\n");
3973 		return err;
3974 	}
3975 
3976 	return 0;
3977 }
3978 
3979 static int setup_rx_err_flow(struct dpaa2_eth_priv *priv,
3980 			     struct dpaa2_eth_fq *fq)
3981 {
3982 	struct device *dev = priv->net_dev->dev.parent;
3983 	struct dpni_queue q = { { 0 } };
3984 	struct dpni_queue_id qid;
3985 	u8 q_opt = DPNI_QUEUE_OPT_USER_CTX | DPNI_QUEUE_OPT_DEST;
3986 	int err;
3987 
3988 	err = dpni_get_queue(priv->mc_io, 0, priv->mc_token,
3989 			     DPNI_QUEUE_RX_ERR, 0, 0, &q, &qid);
3990 	if (err) {
3991 		dev_err(dev, "dpni_get_queue() failed (%d)\n", err);
3992 		return err;
3993 	}
3994 
3995 	fq->fqid = qid.fqid;
3996 
3997 	q.destination.id = fq->channel->dpcon_id;
3998 	q.destination.type = DPNI_DEST_DPCON;
3999 	q.destination.priority = 1;
4000 	q.user_context = (u64)(uintptr_t)fq;
4001 	err = dpni_set_queue(priv->mc_io, 0, priv->mc_token,
4002 			     DPNI_QUEUE_RX_ERR, 0, 0, q_opt, &q);
4003 	if (err) {
4004 		dev_err(dev, "dpni_set_queue() failed (%d)\n", err);
4005 		return err;
4006 	}
4007 
4008 	return 0;
4009 }
4010 
4011 /* Supported header fields for Rx hash distribution key */
4012 static const struct dpaa2_eth_dist_fields dist_fields[] = {
4013 	{
4014 		/* L2 header */
4015 		.rxnfc_field = RXH_L2DA,
4016 		.cls_prot = NET_PROT_ETH,
4017 		.cls_field = NH_FLD_ETH_DA,
4018 		.id = DPAA2_ETH_DIST_ETHDST,
4019 		.size = 6,
4020 	}, {
4021 		.cls_prot = NET_PROT_ETH,
4022 		.cls_field = NH_FLD_ETH_SA,
4023 		.id = DPAA2_ETH_DIST_ETHSRC,
4024 		.size = 6,
4025 	}, {
4026 		/* This is the last ethertype field parsed:
4027 		 * depending on frame format, it can be the MAC ethertype
4028 		 * or the VLAN etype.
4029 		 */
4030 		.cls_prot = NET_PROT_ETH,
4031 		.cls_field = NH_FLD_ETH_TYPE,
4032 		.id = DPAA2_ETH_DIST_ETHTYPE,
4033 		.size = 2,
4034 	}, {
4035 		/* VLAN header */
4036 		.rxnfc_field = RXH_VLAN,
4037 		.cls_prot = NET_PROT_VLAN,
4038 		.cls_field = NH_FLD_VLAN_TCI,
4039 		.id = DPAA2_ETH_DIST_VLAN,
4040 		.size = 2,
4041 	}, {
4042 		/* IP header */
4043 		.rxnfc_field = RXH_IP_SRC,
4044 		.cls_prot = NET_PROT_IP,
4045 		.cls_field = NH_FLD_IP_SRC,
4046 		.id = DPAA2_ETH_DIST_IPSRC,
4047 		.size = 4,
4048 	}, {
4049 		.rxnfc_field = RXH_IP_DST,
4050 		.cls_prot = NET_PROT_IP,
4051 		.cls_field = NH_FLD_IP_DST,
4052 		.id = DPAA2_ETH_DIST_IPDST,
4053 		.size = 4,
4054 	}, {
4055 		.rxnfc_field = RXH_L3_PROTO,
4056 		.cls_prot = NET_PROT_IP,
4057 		.cls_field = NH_FLD_IP_PROTO,
4058 		.id = DPAA2_ETH_DIST_IPPROTO,
4059 		.size = 1,
4060 	}, {
4061 		/* Using UDP ports, this is functionally equivalent to raw
4062 		 * byte pairs from L4 header.
4063 		 */
4064 		.rxnfc_field = RXH_L4_B_0_1,
4065 		.cls_prot = NET_PROT_UDP,
4066 		.cls_field = NH_FLD_UDP_PORT_SRC,
4067 		.id = DPAA2_ETH_DIST_L4SRC,
4068 		.size = 2,
4069 	}, {
4070 		.rxnfc_field = RXH_L4_B_2_3,
4071 		.cls_prot = NET_PROT_UDP,
4072 		.cls_field = NH_FLD_UDP_PORT_DST,
4073 		.id = DPAA2_ETH_DIST_L4DST,
4074 		.size = 2,
4075 	},
4076 };
4077 
4078 /* Configure the Rx hash key using the legacy API */
4079 static int dpaa2_eth_config_legacy_hash_key(struct dpaa2_eth_priv *priv, dma_addr_t key)
4080 {
4081 	struct device *dev = priv->net_dev->dev.parent;
4082 	struct dpni_rx_tc_dist_cfg dist_cfg;
4083 	int i, err = 0;
4084 
4085 	memset(&dist_cfg, 0, sizeof(dist_cfg));
4086 
4087 	dist_cfg.key_cfg_iova = key;
4088 	dist_cfg.dist_size = dpaa2_eth_queue_count(priv);
4089 	dist_cfg.dist_mode = DPNI_DIST_MODE_HASH;
4090 
4091 	for (i = 0; i < dpaa2_eth_tc_count(priv); i++) {
4092 		err = dpni_set_rx_tc_dist(priv->mc_io, 0, priv->mc_token,
4093 					  i, &dist_cfg);
4094 		if (err) {
4095 			dev_err(dev, "dpni_set_rx_tc_dist failed\n");
4096 			break;
4097 		}
4098 	}
4099 
4100 	return err;
4101 }
4102 
4103 /* Configure the Rx hash key using the new API */
4104 static int dpaa2_eth_config_hash_key(struct dpaa2_eth_priv *priv, dma_addr_t key)
4105 {
4106 	struct device *dev = priv->net_dev->dev.parent;
4107 	struct dpni_rx_dist_cfg dist_cfg;
4108 	int i, err = 0;
4109 
4110 	memset(&dist_cfg, 0, sizeof(dist_cfg));
4111 
4112 	dist_cfg.key_cfg_iova = key;
4113 	dist_cfg.dist_size = dpaa2_eth_queue_count(priv);
4114 	dist_cfg.enable = 1;
4115 
4116 	for (i = 0; i < dpaa2_eth_tc_count(priv); i++) {
4117 		dist_cfg.tc = i;
4118 		err = dpni_set_rx_hash_dist(priv->mc_io, 0, priv->mc_token,
4119 					    &dist_cfg);
4120 		if (err) {
4121 			dev_err(dev, "dpni_set_rx_hash_dist failed\n");
4122 			break;
4123 		}
4124 
4125 		/* If the flow steering / hashing key is shared between all
4126 		 * traffic classes, install it just once
4127 		 */
4128 		if (priv->dpni_attrs.options & DPNI_OPT_SHARED_FS)
4129 			break;
4130 	}
4131 
4132 	return err;
4133 }
4134 
4135 /* Configure the Rx flow classification key */
4136 static int dpaa2_eth_config_cls_key(struct dpaa2_eth_priv *priv, dma_addr_t key)
4137 {
4138 	struct device *dev = priv->net_dev->dev.parent;
4139 	struct dpni_rx_dist_cfg dist_cfg;
4140 	int i, err = 0;
4141 
4142 	memset(&dist_cfg, 0, sizeof(dist_cfg));
4143 
4144 	dist_cfg.key_cfg_iova = key;
4145 	dist_cfg.dist_size = dpaa2_eth_queue_count(priv);
4146 	dist_cfg.enable = 1;
4147 
4148 	for (i = 0; i < dpaa2_eth_tc_count(priv); i++) {
4149 		dist_cfg.tc = i;
4150 		err = dpni_set_rx_fs_dist(priv->mc_io, 0, priv->mc_token,
4151 					  &dist_cfg);
4152 		if (err) {
4153 			dev_err(dev, "dpni_set_rx_fs_dist failed\n");
4154 			break;
4155 		}
4156 
4157 		/* If the flow steering / hashing key is shared between all
4158 		 * traffic classes, install it just once
4159 		 */
4160 		if (priv->dpni_attrs.options & DPNI_OPT_SHARED_FS)
4161 			break;
4162 	}
4163 
4164 	return err;
4165 }
4166 
4167 /* Size of the Rx flow classification key */
4168 int dpaa2_eth_cls_key_size(u64 fields)
4169 {
4170 	int i, size = 0;
4171 
4172 	for (i = 0; i < ARRAY_SIZE(dist_fields); i++) {
4173 		if (!(fields & dist_fields[i].id))
4174 			continue;
4175 		size += dist_fields[i].size;
4176 	}
4177 
4178 	return size;
4179 }
4180 
4181 /* Offset of header field in Rx classification key */
4182 int dpaa2_eth_cls_fld_off(int prot, int field)
4183 {
4184 	int i, off = 0;
4185 
4186 	for (i = 0; i < ARRAY_SIZE(dist_fields); i++) {
4187 		if (dist_fields[i].cls_prot == prot &&
4188 		    dist_fields[i].cls_field == field)
4189 			return off;
4190 		off += dist_fields[i].size;
4191 	}
4192 
4193 	WARN_ONCE(1, "Unsupported header field used for Rx flow cls\n");
4194 	return 0;
4195 }
4196 
4197 /* Prune unused fields from the classification rule.
4198  * Used when masking is not supported
4199  */
4200 void dpaa2_eth_cls_trim_rule(void *key_mem, u64 fields)
4201 {
4202 	int off = 0, new_off = 0;
4203 	int i, size;
4204 
4205 	for (i = 0; i < ARRAY_SIZE(dist_fields); i++) {
4206 		size = dist_fields[i].size;
4207 		if (dist_fields[i].id & fields) {
4208 			memcpy(key_mem + new_off, key_mem + off, size);
4209 			new_off += size;
4210 		}
4211 		off += size;
4212 	}
4213 }
4214 
4215 /* Set Rx distribution (hash or flow classification) key
4216  * flags is a combination of RXH_ bits
4217  */
4218 static int dpaa2_eth_set_dist_key(struct net_device *net_dev,
4219 				  enum dpaa2_eth_rx_dist type, u64 flags)
4220 {
4221 	struct device *dev = net_dev->dev.parent;
4222 	struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
4223 	struct dpkg_profile_cfg cls_cfg;
4224 	u32 rx_hash_fields = 0;
4225 	dma_addr_t key_iova;
4226 	u8 *dma_mem;
4227 	int i;
4228 	int err = 0;
4229 
4230 	memset(&cls_cfg, 0, sizeof(cls_cfg));
4231 
4232 	for (i = 0; i < ARRAY_SIZE(dist_fields); i++) {
4233 		struct dpkg_extract *key =
4234 			&cls_cfg.extracts[cls_cfg.num_extracts];
4235 
4236 		/* For both Rx hashing and classification keys
4237 		 * we set only the selected fields.
4238 		 */
4239 		if (!(flags & dist_fields[i].id))
4240 			continue;
4241 		if (type == DPAA2_ETH_RX_DIST_HASH)
4242 			rx_hash_fields |= dist_fields[i].rxnfc_field;
4243 
4244 		if (cls_cfg.num_extracts >= DPKG_MAX_NUM_OF_EXTRACTS) {
4245 			dev_err(dev, "error adding key extraction rule, too many rules?\n");
4246 			return -E2BIG;
4247 		}
4248 
4249 		key->type = DPKG_EXTRACT_FROM_HDR;
4250 		key->extract.from_hdr.prot = dist_fields[i].cls_prot;
4251 		key->extract.from_hdr.type = DPKG_FULL_FIELD;
4252 		key->extract.from_hdr.field = dist_fields[i].cls_field;
4253 		cls_cfg.num_extracts++;
4254 	}
4255 
4256 	dma_mem = kzalloc(DPAA2_CLASSIFIER_DMA_SIZE, GFP_KERNEL);
4257 	if (!dma_mem)
4258 		return -ENOMEM;
4259 
4260 	err = dpni_prepare_key_cfg(&cls_cfg, dma_mem);
4261 	if (err) {
4262 		dev_err(dev, "dpni_prepare_key_cfg error %d\n", err);
4263 		goto free_key;
4264 	}
4265 
4266 	/* Prepare for setting the rx dist */
4267 	key_iova = dma_map_single(dev, dma_mem, DPAA2_CLASSIFIER_DMA_SIZE,
4268 				  DMA_TO_DEVICE);
4269 	if (dma_mapping_error(dev, key_iova)) {
4270 		dev_err(dev, "DMA mapping failed\n");
4271 		err = -ENOMEM;
4272 		goto free_key;
4273 	}
4274 
4275 	if (type == DPAA2_ETH_RX_DIST_HASH) {
4276 		if (dpaa2_eth_has_legacy_dist(priv))
4277 			err = dpaa2_eth_config_legacy_hash_key(priv, key_iova);
4278 		else
4279 			err = dpaa2_eth_config_hash_key(priv, key_iova);
4280 	} else {
4281 		err = dpaa2_eth_config_cls_key(priv, key_iova);
4282 	}
4283 
4284 	dma_unmap_single(dev, key_iova, DPAA2_CLASSIFIER_DMA_SIZE,
4285 			 DMA_TO_DEVICE);
4286 	if (!err && type == DPAA2_ETH_RX_DIST_HASH)
4287 		priv->rx_hash_fields = rx_hash_fields;
4288 
4289 free_key:
4290 	kfree(dma_mem);
4291 	return err;
4292 }
4293 
4294 int dpaa2_eth_set_hash(struct net_device *net_dev, u64 flags)
4295 {
4296 	struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
4297 	u64 key = 0;
4298 	int i;
4299 
4300 	if (!dpaa2_eth_hash_enabled(priv))
4301 		return -EOPNOTSUPP;
4302 
4303 	for (i = 0; i < ARRAY_SIZE(dist_fields); i++)
4304 		if (dist_fields[i].rxnfc_field & flags)
4305 			key |= dist_fields[i].id;
4306 
4307 	return dpaa2_eth_set_dist_key(net_dev, DPAA2_ETH_RX_DIST_HASH, key);
4308 }
4309 
4310 int dpaa2_eth_set_cls(struct net_device *net_dev, u64 flags)
4311 {
4312 	return dpaa2_eth_set_dist_key(net_dev, DPAA2_ETH_RX_DIST_CLS, flags);
4313 }
4314 
4315 static int dpaa2_eth_set_default_cls(struct dpaa2_eth_priv *priv)
4316 {
4317 	struct device *dev = priv->net_dev->dev.parent;
4318 	int err;
4319 
4320 	/* Check if we actually support Rx flow classification */
4321 	if (dpaa2_eth_has_legacy_dist(priv)) {
4322 		dev_dbg(dev, "Rx cls not supported by current MC version\n");
4323 		return -EOPNOTSUPP;
4324 	}
4325 
4326 	if (!dpaa2_eth_fs_enabled(priv)) {
4327 		dev_dbg(dev, "Rx cls disabled in DPNI options\n");
4328 		return -EOPNOTSUPP;
4329 	}
4330 
4331 	if (!dpaa2_eth_hash_enabled(priv)) {
4332 		dev_dbg(dev, "Rx cls disabled for single queue DPNIs\n");
4333 		return -EOPNOTSUPP;
4334 	}
4335 
4336 	/* If there is no support for masking in the classification table,
4337 	 * we don't set a default key, as it will depend on the rules
4338 	 * added by the user at runtime.
4339 	 */
4340 	if (!dpaa2_eth_fs_mask_enabled(priv))
4341 		goto out;
4342 
4343 	err = dpaa2_eth_set_cls(priv->net_dev, DPAA2_ETH_DIST_ALL);
4344 	if (err)
4345 		return err;
4346 
4347 out:
4348 	priv->rx_cls_enabled = 1;
4349 
4350 	return 0;
4351 }
4352 
4353 /* Bind the DPNI to its needed objects and resources: buffer pool, DPIOs,
4354  * frame queues and channels
4355  */
4356 static int dpaa2_eth_bind_dpni(struct dpaa2_eth_priv *priv)
4357 {
4358 	struct dpaa2_eth_bp *bp = priv->bp[DPAA2_ETH_DEFAULT_BP_IDX];
4359 	struct net_device *net_dev = priv->net_dev;
4360 	struct dpni_pools_cfg pools_params = { 0 };
4361 	struct device *dev = net_dev->dev.parent;
4362 	struct dpni_error_cfg err_cfg;
4363 	int err = 0;
4364 	int i;
4365 
4366 	pools_params.num_dpbp = 1;
4367 	pools_params.pools[0].dpbp_id = bp->dev->obj_desc.id;
4368 	pools_params.pools[0].backup_pool = 0;
4369 	pools_params.pools[0].buffer_size = priv->rx_buf_size;
4370 	err = dpni_set_pools(priv->mc_io, 0, priv->mc_token, &pools_params);
4371 	if (err) {
4372 		dev_err(dev, "dpni_set_pools() failed\n");
4373 		return err;
4374 	}
4375 
4376 	/* have the interface implicitly distribute traffic based on
4377 	 * the default hash key
4378 	 */
4379 	err = dpaa2_eth_set_hash(net_dev, DPAA2_RXH_DEFAULT);
4380 	if (err && err != -EOPNOTSUPP)
4381 		dev_err(dev, "Failed to configure hashing\n");
4382 
4383 	/* Configure the flow classification key; it includes all
4384 	 * supported header fields and cannot be modified at runtime
4385 	 */
4386 	err = dpaa2_eth_set_default_cls(priv);
4387 	if (err && err != -EOPNOTSUPP)
4388 		dev_err(dev, "Failed to configure Rx classification key\n");
4389 
4390 	/* Configure handling of error frames */
4391 	err_cfg.errors = DPAA2_FAS_RX_ERR_MASK;
4392 	err_cfg.set_frame_annotation = 1;
4393 	err_cfg.error_action = DPNI_ERROR_ACTION_DISCARD;
4394 	err = dpni_set_errors_behavior(priv->mc_io, 0, priv->mc_token,
4395 				       &err_cfg);
4396 	if (err) {
4397 		dev_err(dev, "dpni_set_errors_behavior failed\n");
4398 		return err;
4399 	}
4400 
4401 	/* Configure Rx and Tx conf queues to generate CDANs */
4402 	for (i = 0; i < priv->num_fqs; i++) {
4403 		switch (priv->fq[i].type) {
4404 		case DPAA2_RX_FQ:
4405 			err = dpaa2_eth_setup_rx_flow(priv, &priv->fq[i]);
4406 			break;
4407 		case DPAA2_TX_CONF_FQ:
4408 			err = dpaa2_eth_setup_tx_flow(priv, &priv->fq[i]);
4409 			break;
4410 		case DPAA2_RX_ERR_FQ:
4411 			err = setup_rx_err_flow(priv, &priv->fq[i]);
4412 			break;
4413 		default:
4414 			dev_err(dev, "Invalid FQ type %d\n", priv->fq[i].type);
4415 			return -EINVAL;
4416 		}
4417 		if (err)
4418 			return err;
4419 	}
4420 
4421 	err = dpni_get_qdid(priv->mc_io, 0, priv->mc_token,
4422 			    DPNI_QUEUE_TX, &priv->tx_qdid);
4423 	if (err) {
4424 		dev_err(dev, "dpni_get_qdid() failed\n");
4425 		return err;
4426 	}
4427 
4428 	return 0;
4429 }
4430 
4431 /* Allocate rings for storing incoming frame descriptors */
4432 static int dpaa2_eth_alloc_rings(struct dpaa2_eth_priv *priv)
4433 {
4434 	struct net_device *net_dev = priv->net_dev;
4435 	struct device *dev = net_dev->dev.parent;
4436 	int i;
4437 
4438 	for (i = 0; i < priv->num_channels; i++) {
4439 		priv->channel[i]->store =
4440 			dpaa2_io_store_create(DPAA2_ETH_STORE_SIZE, dev);
4441 		if (!priv->channel[i]->store) {
4442 			netdev_err(net_dev, "dpaa2_io_store_create() failed\n");
4443 			goto err_ring;
4444 		}
4445 	}
4446 
4447 	return 0;
4448 
4449 err_ring:
4450 	for (i = 0; i < priv->num_channels; i++) {
4451 		if (!priv->channel[i]->store)
4452 			break;
4453 		dpaa2_io_store_destroy(priv->channel[i]->store);
4454 	}
4455 
4456 	return -ENOMEM;
4457 }
4458 
4459 static void dpaa2_eth_free_rings(struct dpaa2_eth_priv *priv)
4460 {
4461 	int i;
4462 
4463 	for (i = 0; i < priv->num_channels; i++)
4464 		dpaa2_io_store_destroy(priv->channel[i]->store);
4465 }
4466 
4467 static int dpaa2_eth_set_mac_addr(struct dpaa2_eth_priv *priv)
4468 {
4469 	struct net_device *net_dev = priv->net_dev;
4470 	struct device *dev = net_dev->dev.parent;
4471 	u8 mac_addr[ETH_ALEN], dpni_mac_addr[ETH_ALEN];
4472 	int err;
4473 
4474 	/* Get firmware address, if any */
4475 	err = dpni_get_port_mac_addr(priv->mc_io, 0, priv->mc_token, mac_addr);
4476 	if (err) {
4477 		dev_err(dev, "dpni_get_port_mac_addr() failed\n");
4478 		return err;
4479 	}
4480 
4481 	/* Get DPNI attributes address, if any */
4482 	err = dpni_get_primary_mac_addr(priv->mc_io, 0, priv->mc_token,
4483 					dpni_mac_addr);
4484 	if (err) {
4485 		dev_err(dev, "dpni_get_primary_mac_addr() failed\n");
4486 		return err;
4487 	}
4488 
4489 	/* First check if firmware has any address configured by bootloader */
4490 	if (!is_zero_ether_addr(mac_addr)) {
4491 		/* If the DPMAC addr != DPNI addr, update it */
4492 		if (!ether_addr_equal(mac_addr, dpni_mac_addr)) {
4493 			err = dpni_set_primary_mac_addr(priv->mc_io, 0,
4494 							priv->mc_token,
4495 							mac_addr);
4496 			if (err) {
4497 				dev_err(dev, "dpni_set_primary_mac_addr() failed\n");
4498 				return err;
4499 			}
4500 		}
4501 		eth_hw_addr_set(net_dev, mac_addr);
4502 	} else if (is_zero_ether_addr(dpni_mac_addr)) {
4503 		/* No MAC address configured, fill in net_dev->dev_addr
4504 		 * with a random one
4505 		 */
4506 		eth_hw_addr_random(net_dev);
4507 		dev_dbg_once(dev, "device(s) have all-zero hwaddr, replaced with random\n");
4508 
4509 		err = dpni_set_primary_mac_addr(priv->mc_io, 0, priv->mc_token,
4510 						net_dev->dev_addr);
4511 		if (err) {
4512 			dev_err(dev, "dpni_set_primary_mac_addr() failed\n");
4513 			return err;
4514 		}
4515 
4516 		/* Override NET_ADDR_RANDOM set by eth_hw_addr_random(); for all
4517 		 * practical purposes, this will be our "permanent" mac address,
4518 		 * at least until the next reboot. This move will also permit
4519 		 * register_netdevice() to properly fill up net_dev->perm_addr.
4520 		 */
4521 		net_dev->addr_assign_type = NET_ADDR_PERM;
4522 	} else {
4523 		/* NET_ADDR_PERM is default, all we have to do is
4524 		 * fill in the device addr.
4525 		 */
4526 		eth_hw_addr_set(net_dev, dpni_mac_addr);
4527 	}
4528 
4529 	return 0;
4530 }
4531 
4532 static int dpaa2_eth_netdev_init(struct net_device *net_dev)
4533 {
4534 	struct device *dev = net_dev->dev.parent;
4535 	struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
4536 	u32 options = priv->dpni_attrs.options;
4537 	u64 supported = 0, not_supported = 0;
4538 	u8 bcast_addr[ETH_ALEN];
4539 	u8 num_queues;
4540 	int err;
4541 
4542 	net_dev->netdev_ops = &dpaa2_eth_ops;
4543 	net_dev->ethtool_ops = &dpaa2_ethtool_ops;
4544 
4545 	err = dpaa2_eth_set_mac_addr(priv);
4546 	if (err)
4547 		return err;
4548 
4549 	/* Explicitly add the broadcast address to the MAC filtering table */
4550 	eth_broadcast_addr(bcast_addr);
4551 	err = dpni_add_mac_addr(priv->mc_io, 0, priv->mc_token, bcast_addr);
4552 	if (err) {
4553 		dev_err(dev, "dpni_add_mac_addr() failed\n");
4554 		return err;
4555 	}
4556 
4557 	/* Set MTU upper limit; lower limit is 68B (default value) */
4558 	net_dev->max_mtu = DPAA2_ETH_MAX_MTU;
4559 	err = dpni_set_max_frame_length(priv->mc_io, 0, priv->mc_token,
4560 					DPAA2_ETH_MFL);
4561 	if (err) {
4562 		dev_err(dev, "dpni_set_max_frame_length() failed\n");
4563 		return err;
4564 	}
4565 
4566 	/* Set actual number of queues in the net device */
4567 	num_queues = dpaa2_eth_queue_count(priv);
4568 	err = netif_set_real_num_tx_queues(net_dev, num_queues);
4569 	if (err) {
4570 		dev_err(dev, "netif_set_real_num_tx_queues() failed\n");
4571 		return err;
4572 	}
4573 	err = netif_set_real_num_rx_queues(net_dev, num_queues);
4574 	if (err) {
4575 		dev_err(dev, "netif_set_real_num_rx_queues() failed\n");
4576 		return err;
4577 	}
4578 
4579 	dpaa2_eth_detect_features(priv);
4580 
4581 	/* Capabilities listing */
4582 	supported |= IFF_LIVE_ADDR_CHANGE;
4583 
4584 	if (options & DPNI_OPT_NO_MAC_FILTER)
4585 		not_supported |= IFF_UNICAST_FLT;
4586 	else
4587 		supported |= IFF_UNICAST_FLT;
4588 
4589 	net_dev->priv_flags |= supported;
4590 	net_dev->priv_flags &= ~not_supported;
4591 
4592 	/* Features */
4593 	net_dev->features = NETIF_F_RXCSUM |
4594 			    NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
4595 			    NETIF_F_SG | NETIF_F_HIGHDMA |
4596 			    NETIF_F_LLTX | NETIF_F_HW_TC | NETIF_F_TSO;
4597 	net_dev->gso_max_segs = DPAA2_ETH_ENQUEUE_MAX_FDS;
4598 	net_dev->hw_features = net_dev->features;
4599 	net_dev->xdp_features = NETDEV_XDP_ACT_BASIC |
4600 				NETDEV_XDP_ACT_REDIRECT |
4601 				NETDEV_XDP_ACT_NDO_XMIT;
4602 	if (priv->dpni_attrs.wriop_version >= DPAA2_WRIOP_VERSION(3, 0, 0) &&
4603 	    priv->dpni_attrs.num_queues <= 8)
4604 		net_dev->xdp_features |= NETDEV_XDP_ACT_XSK_ZEROCOPY;
4605 
4606 	if (priv->dpni_attrs.vlan_filter_entries)
4607 		net_dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
4608 
4609 	return 0;
4610 }
4611 
4612 static int dpaa2_eth_poll_link_state(void *arg)
4613 {
4614 	struct dpaa2_eth_priv *priv = (struct dpaa2_eth_priv *)arg;
4615 	int err;
4616 
4617 	while (!kthread_should_stop()) {
4618 		err = dpaa2_eth_link_state_update(priv);
4619 		if (unlikely(err))
4620 			return err;
4621 
4622 		msleep(DPAA2_ETH_LINK_STATE_REFRESH);
4623 	}
4624 
4625 	return 0;
4626 }
4627 
4628 static int dpaa2_eth_connect_mac(struct dpaa2_eth_priv *priv)
4629 {
4630 	struct fsl_mc_device *dpni_dev, *dpmac_dev;
4631 	struct dpaa2_mac *mac;
4632 	int err;
4633 
4634 	dpni_dev = to_fsl_mc_device(priv->net_dev->dev.parent);
4635 	dpmac_dev = fsl_mc_get_endpoint(dpni_dev, 0);
4636 
4637 	if (PTR_ERR(dpmac_dev) == -EPROBE_DEFER) {
4638 		netdev_dbg(priv->net_dev, "waiting for mac\n");
4639 		return PTR_ERR(dpmac_dev);
4640 	}
4641 
4642 	if (IS_ERR(dpmac_dev) || dpmac_dev->dev.type != &fsl_mc_bus_dpmac_type)
4643 		return 0;
4644 
4645 	mac = kzalloc(sizeof(struct dpaa2_mac), GFP_KERNEL);
4646 	if (!mac)
4647 		return -ENOMEM;
4648 
4649 	mac->mc_dev = dpmac_dev;
4650 	mac->mc_io = priv->mc_io;
4651 	mac->net_dev = priv->net_dev;
4652 
4653 	err = dpaa2_mac_open(mac);
4654 	if (err)
4655 		goto err_free_mac;
4656 
4657 	if (dpaa2_mac_is_type_phy(mac)) {
4658 		err = dpaa2_mac_connect(mac);
4659 		if (err) {
4660 			if (err == -EPROBE_DEFER)
4661 				netdev_dbg(priv->net_dev,
4662 					   "could not connect to MAC\n");
4663 			else
4664 				netdev_err(priv->net_dev,
4665 					   "Error connecting to the MAC endpoint: %pe",
4666 					   ERR_PTR(err));
4667 			goto err_close_mac;
4668 		}
4669 	}
4670 
4671 	mutex_lock(&priv->mac_lock);
4672 	priv->mac = mac;
4673 	mutex_unlock(&priv->mac_lock);
4674 
4675 	return 0;
4676 
4677 err_close_mac:
4678 	dpaa2_mac_close(mac);
4679 err_free_mac:
4680 	kfree(mac);
4681 	return err;
4682 }
4683 
4684 static void dpaa2_eth_disconnect_mac(struct dpaa2_eth_priv *priv)
4685 {
4686 	struct dpaa2_mac *mac;
4687 
4688 	mutex_lock(&priv->mac_lock);
4689 	mac = priv->mac;
4690 	priv->mac = NULL;
4691 	mutex_unlock(&priv->mac_lock);
4692 
4693 	if (!mac)
4694 		return;
4695 
4696 	if (dpaa2_mac_is_type_phy(mac))
4697 		dpaa2_mac_disconnect(mac);
4698 
4699 	dpaa2_mac_close(mac);
4700 	kfree(mac);
4701 }
4702 
4703 static irqreturn_t dpni_irq0_handler_thread(int irq_num, void *arg)
4704 {
4705 	u32 status = ~0;
4706 	struct device *dev = (struct device *)arg;
4707 	struct fsl_mc_device *dpni_dev = to_fsl_mc_device(dev);
4708 	struct net_device *net_dev = dev_get_drvdata(dev);
4709 	struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
4710 	bool had_mac;
4711 	int err;
4712 
4713 	err = dpni_get_irq_status(dpni_dev->mc_io, 0, dpni_dev->mc_handle,
4714 				  DPNI_IRQ_INDEX, &status);
4715 	if (unlikely(err)) {
4716 		netdev_err(net_dev, "Can't get irq status (err %d)\n", err);
4717 		return IRQ_HANDLED;
4718 	}
4719 
4720 	if (status & DPNI_IRQ_EVENT_LINK_CHANGED)
4721 		dpaa2_eth_link_state_update(netdev_priv(net_dev));
4722 
4723 	if (status & DPNI_IRQ_EVENT_ENDPOINT_CHANGED) {
4724 		dpaa2_eth_set_mac_addr(netdev_priv(net_dev));
4725 		dpaa2_eth_update_tx_fqids(priv);
4726 
4727 		/* We can avoid locking because the "endpoint changed" IRQ
4728 		 * handler is the only one who changes priv->mac at runtime,
4729 		 * so we are not racing with anyone.
4730 		 */
4731 		had_mac = !!priv->mac;
4732 		if (had_mac)
4733 			dpaa2_eth_disconnect_mac(priv);
4734 		else
4735 			dpaa2_eth_connect_mac(priv);
4736 	}
4737 
4738 	return IRQ_HANDLED;
4739 }
4740 
4741 static int dpaa2_eth_setup_irqs(struct fsl_mc_device *ls_dev)
4742 {
4743 	int err = 0;
4744 	struct fsl_mc_device_irq *irq;
4745 
4746 	err = fsl_mc_allocate_irqs(ls_dev);
4747 	if (err) {
4748 		dev_err(&ls_dev->dev, "MC irqs allocation failed\n");
4749 		return err;
4750 	}
4751 
4752 	irq = ls_dev->irqs[0];
4753 	err = devm_request_threaded_irq(&ls_dev->dev, irq->virq,
4754 					NULL, dpni_irq0_handler_thread,
4755 					IRQF_NO_SUSPEND | IRQF_ONESHOT,
4756 					dev_name(&ls_dev->dev), &ls_dev->dev);
4757 	if (err < 0) {
4758 		dev_err(&ls_dev->dev, "devm_request_threaded_irq(): %d\n", err);
4759 		goto free_mc_irq;
4760 	}
4761 
4762 	err = dpni_set_irq_mask(ls_dev->mc_io, 0, ls_dev->mc_handle,
4763 				DPNI_IRQ_INDEX, DPNI_IRQ_EVENT_LINK_CHANGED |
4764 				DPNI_IRQ_EVENT_ENDPOINT_CHANGED);
4765 	if (err < 0) {
4766 		dev_err(&ls_dev->dev, "dpni_set_irq_mask(): %d\n", err);
4767 		goto free_irq;
4768 	}
4769 
4770 	err = dpni_set_irq_enable(ls_dev->mc_io, 0, ls_dev->mc_handle,
4771 				  DPNI_IRQ_INDEX, 1);
4772 	if (err < 0) {
4773 		dev_err(&ls_dev->dev, "dpni_set_irq_enable(): %d\n", err);
4774 		goto free_irq;
4775 	}
4776 
4777 	return 0;
4778 
4779 free_irq:
4780 	devm_free_irq(&ls_dev->dev, irq->virq, &ls_dev->dev);
4781 free_mc_irq:
4782 	fsl_mc_free_irqs(ls_dev);
4783 
4784 	return err;
4785 }
4786 
4787 static void dpaa2_eth_add_ch_napi(struct dpaa2_eth_priv *priv)
4788 {
4789 	int i;
4790 	struct dpaa2_eth_channel *ch;
4791 
4792 	for (i = 0; i < priv->num_channels; i++) {
4793 		ch = priv->channel[i];
4794 		/* NAPI weight *MUST* be a multiple of DPAA2_ETH_STORE_SIZE */
4795 		netif_napi_add(priv->net_dev, &ch->napi, dpaa2_eth_poll);
4796 	}
4797 }
4798 
4799 static void dpaa2_eth_del_ch_napi(struct dpaa2_eth_priv *priv)
4800 {
4801 	int i;
4802 	struct dpaa2_eth_channel *ch;
4803 
4804 	for (i = 0; i < priv->num_channels; i++) {
4805 		ch = priv->channel[i];
4806 		netif_napi_del(&ch->napi);
4807 	}
4808 }
4809 
4810 static int dpaa2_eth_probe(struct fsl_mc_device *dpni_dev)
4811 {
4812 	struct device *dev;
4813 	struct net_device *net_dev = NULL;
4814 	struct dpaa2_eth_priv *priv = NULL;
4815 	int err = 0;
4816 
4817 	dev = &dpni_dev->dev;
4818 
4819 	/* Net device */
4820 	net_dev = alloc_etherdev_mq(sizeof(*priv), DPAA2_ETH_MAX_NETDEV_QUEUES);
4821 	if (!net_dev) {
4822 		dev_err(dev, "alloc_etherdev_mq() failed\n");
4823 		return -ENOMEM;
4824 	}
4825 
4826 	SET_NETDEV_DEV(net_dev, dev);
4827 	dev_set_drvdata(dev, net_dev);
4828 
4829 	priv = netdev_priv(net_dev);
4830 	priv->net_dev = net_dev;
4831 	SET_NETDEV_DEVLINK_PORT(net_dev, &priv->devlink_port);
4832 
4833 	mutex_init(&priv->mac_lock);
4834 
4835 	priv->iommu_domain = iommu_get_domain_for_dev(dev);
4836 
4837 	priv->tx_tstamp_type = HWTSTAMP_TX_OFF;
4838 	priv->rx_tstamp = false;
4839 
4840 	priv->dpaa2_ptp_wq = alloc_workqueue("dpaa2_ptp_wq", 0, 0);
4841 	if (!priv->dpaa2_ptp_wq) {
4842 		err = -ENOMEM;
4843 		goto err_wq_alloc;
4844 	}
4845 
4846 	INIT_WORK(&priv->tx_onestep_tstamp, dpaa2_eth_tx_onestep_tstamp);
4847 	mutex_init(&priv->onestep_tstamp_lock);
4848 	skb_queue_head_init(&priv->tx_skbs);
4849 
4850 	priv->rx_copybreak = DPAA2_ETH_DEFAULT_COPYBREAK;
4851 
4852 	/* Obtain a MC portal */
4853 	err = fsl_mc_portal_allocate(dpni_dev, FSL_MC_IO_ATOMIC_CONTEXT_PORTAL,
4854 				     &priv->mc_io);
4855 	if (err) {
4856 		if (err == -ENXIO) {
4857 			dev_dbg(dev, "waiting for MC portal\n");
4858 			err = -EPROBE_DEFER;
4859 		} else {
4860 			dev_err(dev, "MC portal allocation failed\n");
4861 		}
4862 		goto err_portal_alloc;
4863 	}
4864 
4865 	/* MC objects initialization and configuration */
4866 	err = dpaa2_eth_setup_dpni(dpni_dev);
4867 	if (err)
4868 		goto err_dpni_setup;
4869 
4870 	err = dpaa2_eth_setup_dpio(priv);
4871 	if (err)
4872 		goto err_dpio_setup;
4873 
4874 	dpaa2_eth_setup_fqs(priv);
4875 
4876 	err = dpaa2_eth_setup_default_dpbp(priv);
4877 	if (err)
4878 		goto err_dpbp_setup;
4879 
4880 	err = dpaa2_eth_bind_dpni(priv);
4881 	if (err)
4882 		goto err_bind;
4883 
4884 	/* Add a NAPI context for each channel */
4885 	dpaa2_eth_add_ch_napi(priv);
4886 
4887 	/* Percpu statistics */
4888 	priv->percpu_stats = alloc_percpu(*priv->percpu_stats);
4889 	if (!priv->percpu_stats) {
4890 		dev_err(dev, "alloc_percpu(percpu_stats) failed\n");
4891 		err = -ENOMEM;
4892 		goto err_alloc_percpu_stats;
4893 	}
4894 	priv->percpu_extras = alloc_percpu(*priv->percpu_extras);
4895 	if (!priv->percpu_extras) {
4896 		dev_err(dev, "alloc_percpu(percpu_extras) failed\n");
4897 		err = -ENOMEM;
4898 		goto err_alloc_percpu_extras;
4899 	}
4900 
4901 	priv->sgt_cache = alloc_percpu(*priv->sgt_cache);
4902 	if (!priv->sgt_cache) {
4903 		dev_err(dev, "alloc_percpu(sgt_cache) failed\n");
4904 		err = -ENOMEM;
4905 		goto err_alloc_sgt_cache;
4906 	}
4907 
4908 	priv->fd = alloc_percpu(*priv->fd);
4909 	if (!priv->fd) {
4910 		dev_err(dev, "alloc_percpu(fds) failed\n");
4911 		err = -ENOMEM;
4912 		goto err_alloc_fds;
4913 	}
4914 
4915 	err = dpaa2_eth_netdev_init(net_dev);
4916 	if (err)
4917 		goto err_netdev_init;
4918 
4919 	/* Configure checksum offload based on current interface flags */
4920 	err = dpaa2_eth_set_rx_csum(priv, !!(net_dev->features & NETIF_F_RXCSUM));
4921 	if (err)
4922 		goto err_csum;
4923 
4924 	err = dpaa2_eth_set_tx_csum(priv,
4925 				    !!(net_dev->features & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)));
4926 	if (err)
4927 		goto err_csum;
4928 
4929 	err = dpaa2_eth_alloc_rings(priv);
4930 	if (err)
4931 		goto err_alloc_rings;
4932 
4933 #ifdef CONFIG_FSL_DPAA2_ETH_DCB
4934 	if (dpaa2_eth_has_pause_support(priv) && priv->vlan_cls_enabled) {
4935 		priv->dcbx_mode = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_IEEE;
4936 		net_dev->dcbnl_ops = &dpaa2_eth_dcbnl_ops;
4937 	} else {
4938 		dev_dbg(dev, "PFC not supported\n");
4939 	}
4940 #endif
4941 
4942 	err = dpaa2_eth_connect_mac(priv);
4943 	if (err)
4944 		goto err_connect_mac;
4945 
4946 	err = dpaa2_eth_setup_irqs(dpni_dev);
4947 	if (err) {
4948 		netdev_warn(net_dev, "Failed to set link interrupt, fall back to polling\n");
4949 		priv->poll_thread = kthread_run(dpaa2_eth_poll_link_state, priv,
4950 						"%s_poll_link", net_dev->name);
4951 		if (IS_ERR(priv->poll_thread)) {
4952 			dev_err(dev, "Error starting polling thread\n");
4953 			goto err_poll_thread;
4954 		}
4955 		priv->do_link_poll = true;
4956 	}
4957 
4958 	err = dpaa2_eth_dl_alloc(priv);
4959 	if (err)
4960 		goto err_dl_register;
4961 
4962 	err = dpaa2_eth_dl_traps_register(priv);
4963 	if (err)
4964 		goto err_dl_trap_register;
4965 
4966 	err = dpaa2_eth_dl_port_add(priv);
4967 	if (err)
4968 		goto err_dl_port_add;
4969 
4970 	err = register_netdev(net_dev);
4971 	if (err < 0) {
4972 		dev_err(dev, "register_netdev() failed\n");
4973 		goto err_netdev_reg;
4974 	}
4975 
4976 #ifdef CONFIG_DEBUG_FS
4977 	dpaa2_dbg_add(priv);
4978 #endif
4979 
4980 	dpaa2_eth_dl_register(priv);
4981 	dev_info(dev, "Probed interface %s\n", net_dev->name);
4982 	return 0;
4983 
4984 err_netdev_reg:
4985 	dpaa2_eth_dl_port_del(priv);
4986 err_dl_port_add:
4987 	dpaa2_eth_dl_traps_unregister(priv);
4988 err_dl_trap_register:
4989 	dpaa2_eth_dl_free(priv);
4990 err_dl_register:
4991 	if (priv->do_link_poll)
4992 		kthread_stop(priv->poll_thread);
4993 	else
4994 		fsl_mc_free_irqs(dpni_dev);
4995 err_poll_thread:
4996 	dpaa2_eth_disconnect_mac(priv);
4997 err_connect_mac:
4998 	dpaa2_eth_free_rings(priv);
4999 err_alloc_rings:
5000 err_csum:
5001 err_netdev_init:
5002 	free_percpu(priv->fd);
5003 err_alloc_fds:
5004 	free_percpu(priv->sgt_cache);
5005 err_alloc_sgt_cache:
5006 	free_percpu(priv->percpu_extras);
5007 err_alloc_percpu_extras:
5008 	free_percpu(priv->percpu_stats);
5009 err_alloc_percpu_stats:
5010 	dpaa2_eth_del_ch_napi(priv);
5011 err_bind:
5012 	dpaa2_eth_free_dpbps(priv);
5013 err_dpbp_setup:
5014 	dpaa2_eth_free_dpio(priv);
5015 err_dpio_setup:
5016 	dpaa2_eth_free_dpni(priv);
5017 err_dpni_setup:
5018 	fsl_mc_portal_free(priv->mc_io);
5019 err_portal_alloc:
5020 	destroy_workqueue(priv->dpaa2_ptp_wq);
5021 err_wq_alloc:
5022 	dev_set_drvdata(dev, NULL);
5023 	free_netdev(net_dev);
5024 
5025 	return err;
5026 }
5027 
5028 static void dpaa2_eth_remove(struct fsl_mc_device *ls_dev)
5029 {
5030 	struct device *dev;
5031 	struct net_device *net_dev;
5032 	struct dpaa2_eth_priv *priv;
5033 
5034 	dev = &ls_dev->dev;
5035 	net_dev = dev_get_drvdata(dev);
5036 	priv = netdev_priv(net_dev);
5037 
5038 	dpaa2_eth_dl_unregister(priv);
5039 
5040 #ifdef CONFIG_DEBUG_FS
5041 	dpaa2_dbg_remove(priv);
5042 #endif
5043 
5044 	unregister_netdev(net_dev);
5045 
5046 	dpaa2_eth_dl_port_del(priv);
5047 	dpaa2_eth_dl_traps_unregister(priv);
5048 	dpaa2_eth_dl_free(priv);
5049 
5050 	if (priv->do_link_poll)
5051 		kthread_stop(priv->poll_thread);
5052 	else
5053 		fsl_mc_free_irqs(ls_dev);
5054 
5055 	dpaa2_eth_disconnect_mac(priv);
5056 	dpaa2_eth_free_rings(priv);
5057 	free_percpu(priv->fd);
5058 	free_percpu(priv->sgt_cache);
5059 	free_percpu(priv->percpu_stats);
5060 	free_percpu(priv->percpu_extras);
5061 
5062 	dpaa2_eth_del_ch_napi(priv);
5063 	dpaa2_eth_free_dpbps(priv);
5064 	dpaa2_eth_free_dpio(priv);
5065 	dpaa2_eth_free_dpni(priv);
5066 	if (priv->onestep_reg_base)
5067 		iounmap(priv->onestep_reg_base);
5068 
5069 	fsl_mc_portal_free(priv->mc_io);
5070 
5071 	destroy_workqueue(priv->dpaa2_ptp_wq);
5072 
5073 	dev_dbg(net_dev->dev.parent, "Removed interface %s\n", net_dev->name);
5074 
5075 	free_netdev(net_dev);
5076 }
5077 
5078 static const struct fsl_mc_device_id dpaa2_eth_match_id_table[] = {
5079 	{
5080 		.vendor = FSL_MC_VENDOR_FREESCALE,
5081 		.obj_type = "dpni",
5082 	},
5083 	{ .vendor = 0x0 }
5084 };
5085 MODULE_DEVICE_TABLE(fslmc, dpaa2_eth_match_id_table);
5086 
5087 static struct fsl_mc_driver dpaa2_eth_driver = {
5088 	.driver = {
5089 		.name = KBUILD_MODNAME,
5090 		.owner = THIS_MODULE,
5091 	},
5092 	.probe = dpaa2_eth_probe,
5093 	.remove = dpaa2_eth_remove,
5094 	.match_id_table = dpaa2_eth_match_id_table
5095 };
5096 
5097 static int __init dpaa2_eth_driver_init(void)
5098 {
5099 	int err;
5100 
5101 	dpaa2_eth_dbg_init();
5102 	err = fsl_mc_driver_register(&dpaa2_eth_driver);
5103 	if (err) {
5104 		dpaa2_eth_dbg_exit();
5105 		return err;
5106 	}
5107 
5108 	return 0;
5109 }
5110 
5111 static void __exit dpaa2_eth_driver_exit(void)
5112 {
5113 	dpaa2_eth_dbg_exit();
5114 	fsl_mc_driver_unregister(&dpaa2_eth_driver);
5115 }
5116 
5117 module_init(dpaa2_eth_driver_init);
5118 module_exit(dpaa2_eth_driver_exit);
5119