19ad1a374SMadalin Bucur /* Copyright 2008 - 2016 Freescale Semiconductor Inc.
29ad1a374SMadalin Bucur  *
39ad1a374SMadalin Bucur  * Redistribution and use in source and binary forms, with or without
49ad1a374SMadalin Bucur  * modification, are permitted provided that the following conditions are met:
59ad1a374SMadalin Bucur  *     * Redistributions of source code must retain the above copyright
69ad1a374SMadalin Bucur  *	 notice, this list of conditions and the following disclaimer.
79ad1a374SMadalin Bucur  *     * Redistributions in binary form must reproduce the above copyright
89ad1a374SMadalin Bucur  *	 notice, this list of conditions and the following disclaimer in the
99ad1a374SMadalin Bucur  *	 documentation and/or other materials provided with the distribution.
109ad1a374SMadalin Bucur  *     * Neither the name of Freescale Semiconductor nor the
119ad1a374SMadalin Bucur  *	 names of its contributors may be used to endorse or promote products
129ad1a374SMadalin Bucur  *	 derived from this software without specific prior written permission.
139ad1a374SMadalin Bucur  *
149ad1a374SMadalin Bucur  * ALTERNATIVELY, this software may be distributed under the terms of the
159ad1a374SMadalin Bucur  * GNU General Public License ("GPL") as published by the Free Software
169ad1a374SMadalin Bucur  * Foundation, either version 2 of that License or (at your option) any
179ad1a374SMadalin Bucur  * later version.
189ad1a374SMadalin Bucur  *
199ad1a374SMadalin Bucur  * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
209ad1a374SMadalin Bucur  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
219ad1a374SMadalin Bucur  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
229ad1a374SMadalin Bucur  * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
239ad1a374SMadalin Bucur  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
249ad1a374SMadalin Bucur  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
259ad1a374SMadalin Bucur  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
269ad1a374SMadalin Bucur  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
279ad1a374SMadalin Bucur  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
289ad1a374SMadalin Bucur  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
299ad1a374SMadalin Bucur  */
309ad1a374SMadalin Bucur 
319ad1a374SMadalin Bucur #ifndef __DPAA_H
329ad1a374SMadalin Bucur #define __DPAA_H
339ad1a374SMadalin Bucur 
349ad1a374SMadalin Bucur #include <linux/netdevice.h>
3531168a6dSChuhong Yuan #include <linux/refcount.h>
369ad1a374SMadalin Bucur #include <soc/fsl/qman.h>
379ad1a374SMadalin Bucur #include <soc/fsl/bman.h>
389ad1a374SMadalin Bucur 
399ad1a374SMadalin Bucur #include "fman.h"
409ad1a374SMadalin Bucur #include "mac.h"
41eb11ddf3SMadalin Bucur #include "dpaa_eth_trace.h"
429ad1a374SMadalin Bucur 
43c44efa1dSCamelia Groza /* Number of prioritised traffic classes */
44c44efa1dSCamelia Groza #define DPAA_TC_NUM		4
45c44efa1dSCamelia Groza /* Number of Tx queues per traffic class */
46c44efa1dSCamelia Groza #define DPAA_TC_TXQ_NUM		NR_CPUS
47c44efa1dSCamelia Groza /* Total number of Tx queues */
48c44efa1dSCamelia Groza #define DPAA_ETH_TXQ_NUM	(DPAA_TC_NUM * DPAA_TC_TXQ_NUM)
499ad1a374SMadalin Bucur 
509ad1a374SMadalin Bucur /* More detailed FQ types - used for fine-grained WQ assignments */
519ad1a374SMadalin Bucur enum dpaa_fq_type {
529ad1a374SMadalin Bucur 	FQ_TYPE_RX_DEFAULT = 1, /* Rx Default FQs */
539ad1a374SMadalin Bucur 	FQ_TYPE_RX_ERROR,	/* Rx Error FQs */
543150b7c2SMadalin Bucur 	FQ_TYPE_RX_PCD,		/* Rx Parse Classify Distribute FQs */
559ad1a374SMadalin Bucur 	FQ_TYPE_TX,		/* "Real" Tx FQs */
569ad1a374SMadalin Bucur 	FQ_TYPE_TX_CONFIRM,	/* Tx default Conf FQ (actually an Rx FQ) */
579ad1a374SMadalin Bucur 	FQ_TYPE_TX_CONF_MQ,	/* Tx conf FQs (one for each Tx FQ) */
589ad1a374SMadalin Bucur 	FQ_TYPE_TX_ERROR,	/* Tx Error FQs (these are actually Rx FQs) */
599ad1a374SMadalin Bucur };
609ad1a374SMadalin Bucur 
619ad1a374SMadalin Bucur struct dpaa_fq {
629ad1a374SMadalin Bucur 	struct qman_fq fq_base;
639ad1a374SMadalin Bucur 	struct list_head list;
649ad1a374SMadalin Bucur 	struct net_device *net_dev;
659ad1a374SMadalin Bucur 	bool init;
669ad1a374SMadalin Bucur 	u32 fqid;
679ad1a374SMadalin Bucur 	u32 flags;
689ad1a374SMadalin Bucur 	u16 channel;
699ad1a374SMadalin Bucur 	u8 wq;
709ad1a374SMadalin Bucur 	enum dpaa_fq_type fq_type;
71*d57e57d0SCamelia Groza 	struct xdp_rxq_info xdp_rxq;
729ad1a374SMadalin Bucur };
739ad1a374SMadalin Bucur 
749ad1a374SMadalin Bucur struct dpaa_fq_cbs {
759ad1a374SMadalin Bucur 	struct qman_fq rx_defq;
769ad1a374SMadalin Bucur 	struct qman_fq tx_defq;
779ad1a374SMadalin Bucur 	struct qman_fq rx_errq;
789ad1a374SMadalin Bucur 	struct qman_fq tx_errq;
799ad1a374SMadalin Bucur 	struct qman_fq egress_ern;
809ad1a374SMadalin Bucur };
819ad1a374SMadalin Bucur 
82060ad66fSMadalin Bucur struct dpaa_priv;
83060ad66fSMadalin Bucur 
849ad1a374SMadalin Bucur struct dpaa_bp {
85060ad66fSMadalin Bucur 	/* used in the DMA mapping operations */
86060ad66fSMadalin Bucur 	struct dpaa_priv *priv;
879ad1a374SMadalin Bucur 	/* current number of buffers in the buffer pool alloted to each CPU */
889ad1a374SMadalin Bucur 	int __percpu *percpu_count;
899ad1a374SMadalin Bucur 	/* all buffers allocated for this pool have this raw size */
909ad1a374SMadalin Bucur 	size_t raw_size;
919ad1a374SMadalin Bucur 	/* all buffers in this pool have this same usable size */
929ad1a374SMadalin Bucur 	size_t size;
939ad1a374SMadalin Bucur 	/* the buffer pools are initialized with config_count buffers for each
949ad1a374SMadalin Bucur 	 * CPU; at runtime the number of buffers per CPU is constantly brought
959ad1a374SMadalin Bucur 	 * back to this level
969ad1a374SMadalin Bucur 	 */
979ad1a374SMadalin Bucur 	u16 config_count;
989ad1a374SMadalin Bucur 	u8 bpid;
999ad1a374SMadalin Bucur 	struct bman_pool *pool;
1009ad1a374SMadalin Bucur 	/* bpool can be seeded before use by this cb */
1019ad1a374SMadalin Bucur 	int (*seed_cb)(struct dpaa_bp *);
1029ad1a374SMadalin Bucur 	/* bpool can be emptied before freeing by this cb */
1039ad1a374SMadalin Bucur 	void (*free_buf_cb)(const struct dpaa_bp *, struct bm_buffer *);
10431168a6dSChuhong Yuan 	refcount_t refs;
1059ad1a374SMadalin Bucur };
1069ad1a374SMadalin Bucur 
107b0ce0d02SMadalin Bucur struct dpaa_rx_errors {
108b0ce0d02SMadalin Bucur 	u64 dme;		/* DMA Error */
109b0ce0d02SMadalin Bucur 	u64 fpe;		/* Frame Physical Error */
110b0ce0d02SMadalin Bucur 	u64 fse;		/* Frame Size Error */
111b0ce0d02SMadalin Bucur 	u64 phe;		/* Header Error */
112b0ce0d02SMadalin Bucur };
113b0ce0d02SMadalin Bucur 
114b0ce0d02SMadalin Bucur /* Counters for QMan ERN frames - one counter per rejection code */
115b0ce0d02SMadalin Bucur struct dpaa_ern_cnt {
116b0ce0d02SMadalin Bucur 	u64 cg_tdrop;		/* Congestion group taildrop */
117b0ce0d02SMadalin Bucur 	u64 wred;		/* WRED congestion */
118b0ce0d02SMadalin Bucur 	u64 err_cond;		/* Error condition */
119b0ce0d02SMadalin Bucur 	u64 early_window;	/* Order restoration, frame too early */
120b0ce0d02SMadalin Bucur 	u64 late_window;	/* Order restoration, frame too late */
121b0ce0d02SMadalin Bucur 	u64 fq_tdrop;		/* FQ taildrop */
122b0ce0d02SMadalin Bucur 	u64 fq_retired;		/* FQ is retired */
123b0ce0d02SMadalin Bucur 	u64 orp_zero;		/* ORP disabled */
124b0ce0d02SMadalin Bucur };
125b0ce0d02SMadalin Bucur 
1269ad1a374SMadalin Bucur struct dpaa_napi_portal {
1279ad1a374SMadalin Bucur 	struct napi_struct napi;
1289ad1a374SMadalin Bucur 	struct qman_portal *p;
1299ad1a374SMadalin Bucur 	bool down;
1309ad1a374SMadalin Bucur };
1319ad1a374SMadalin Bucur 
1329ad1a374SMadalin Bucur struct dpaa_percpu_priv {
1339ad1a374SMadalin Bucur 	struct net_device *net_dev;
1349ad1a374SMadalin Bucur 	struct dpaa_napi_portal np;
135b0ce0d02SMadalin Bucur 	u64 in_interrupt;
136b0ce0d02SMadalin Bucur 	u64 tx_confirm;
137b0ce0d02SMadalin Bucur 	/* fragmented (non-linear) skbuffs received from the stack */
138b0ce0d02SMadalin Bucur 	u64 tx_frag_skbuffs;
1399ad1a374SMadalin Bucur 	struct rtnl_link_stats64 stats;
140b0ce0d02SMadalin Bucur 	struct dpaa_rx_errors rx_errors;
141b0ce0d02SMadalin Bucur 	struct dpaa_ern_cnt ern_cnt;
1429ad1a374SMadalin Bucur };
1439ad1a374SMadalin Bucur 
1449ad1a374SMadalin Bucur struct dpaa_buffer_layout {
1459ad1a374SMadalin Bucur 	u16 priv_data_size;
1469ad1a374SMadalin Bucur };
1479ad1a374SMadalin Bucur 
148fb9afd96SCamelia Groza /* Information to be used on the Tx confirmation path. Stored just
149fb9afd96SCamelia Groza  * before the start of the transmit buffer. Maximum size allowed
150fb9afd96SCamelia Groza  * is DPAA_TX_PRIV_DATA_SIZE bytes.
151fb9afd96SCamelia Groza  */
152fb9afd96SCamelia Groza struct dpaa_eth_swbp {
153fb9afd96SCamelia Groza 	struct sk_buff *skb;
154*d57e57d0SCamelia Groza 	struct xdp_frame *xdpf;
155fb9afd96SCamelia Groza };
156fb9afd96SCamelia Groza 
1579ad1a374SMadalin Bucur struct dpaa_priv {
1589ad1a374SMadalin Bucur 	struct dpaa_percpu_priv __percpu *percpu_priv;
159f07f3004SMadalin Bucur 	struct dpaa_bp *dpaa_bp;
1609ad1a374SMadalin Bucur 	/* Store here the needed Tx headroom for convenience and speed
1619ad1a374SMadalin Bucur 	 * (even though it can be computed based on the fields of buf_layout)
1629ad1a374SMadalin Bucur 	 */
1639ad1a374SMadalin Bucur 	u16 tx_headroom;
1649ad1a374SMadalin Bucur 	struct net_device *net_dev;
1659ad1a374SMadalin Bucur 	struct mac_device *mac_dev;
166060ad66fSMadalin Bucur 	struct device *rx_dma_dev;
167060ad66fSMadalin Bucur 	struct device *tx_dma_dev;
1689ad1a374SMadalin Bucur 	struct qman_fq *egress_fqs[DPAA_ETH_TXQ_NUM];
1699ad1a374SMadalin Bucur 	struct qman_fq *conf_fqs[DPAA_ETH_TXQ_NUM];
1709ad1a374SMadalin Bucur 
1719ad1a374SMadalin Bucur 	u16 channel;
1729ad1a374SMadalin Bucur 	struct list_head dpaa_fq_list;
1739ad1a374SMadalin Bucur 
174c44efa1dSCamelia Groza 	u8 num_tc;
175056057e2SMadalin Bucur 	bool keygen_in_use;
1769ad1a374SMadalin Bucur 	u32 msg_enable;	/* net_device message level */
1779ad1a374SMadalin Bucur 
1789ad1a374SMadalin Bucur 	struct {
1799ad1a374SMadalin Bucur 		/* All egress queues to a given net device belong to one
1809ad1a374SMadalin Bucur 		 * (and the same) congestion group.
1819ad1a374SMadalin Bucur 		 */
1829ad1a374SMadalin Bucur 		struct qman_cgr cgr;
183b0ce0d02SMadalin Bucur 		/* If congested, when it began. Used for performance stats. */
184b0ce0d02SMadalin Bucur 		u32 congestion_start_jiffies;
185b0ce0d02SMadalin Bucur 		/* Number of jiffies the Tx port was congested. */
186b0ce0d02SMadalin Bucur 		u32 congested_jiffies;
187b0ce0d02SMadalin Bucur 		/* Counter for the number of times the CGR
188b0ce0d02SMadalin Bucur 		 * entered congestion state
189b0ce0d02SMadalin Bucur 		 */
190b0ce0d02SMadalin Bucur 		u32 cgr_congested_count;
1919ad1a374SMadalin Bucur 	} cgr_data;
1929ad1a374SMadalin Bucur 	/* Use a per-port CGR for ingress traffic. */
1939ad1a374SMadalin Bucur 	bool use_ingress_cgr;
1949ad1a374SMadalin Bucur 	struct qman_cgr ingress_cgr;
1959ad1a374SMadalin Bucur 
1969ad1a374SMadalin Bucur 	struct dpaa_buffer_layout buf_layout[2];
1979ad1a374SMadalin Bucur 	u16 rx_headroom;
1984664856eSYangbo Lu 
1994664856eSYangbo Lu 	bool tx_tstamp; /* Tx timestamping enabled */
2004664856eSYangbo Lu 	bool rx_tstamp; /* Rx timestamping enabled */
20186c0c196SCamelia Groza 
20286c0c196SCamelia Groza 	struct bpf_prog *xdp_prog;
2039ad1a374SMadalin Bucur };
204b0cdb168SMadalin Bucur 
205b0cdb168SMadalin Bucur /* from dpaa_ethtool.c */
206b0cdb168SMadalin Bucur extern const struct ethtool_ops dpaa_ethtool_ops;
207846a86e2SMadalin Bucur 
208846a86e2SMadalin Bucur /* from dpaa_eth_sysfs.c */
209846a86e2SMadalin Bucur void dpaa_eth_sysfs_remove(struct device *dev);
210846a86e2SMadalin Bucur void dpaa_eth_sysfs_init(struct device *dev);
2119ad1a374SMadalin Bucur #endif	/* __DPAA_H */
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