1 /* Copyright 2008 - 2016 Freescale Semiconductor Inc. 2 * 3 * Redistribution and use in source and binary forms, with or without 4 * modification, are permitted provided that the following conditions are met: 5 * * Redistributions of source code must retain the above copyright 6 * notice, this list of conditions and the following disclaimer. 7 * * Redistributions in binary form must reproduce the above copyright 8 * notice, this list of conditions and the following disclaimer in the 9 * documentation and/or other materials provided with the distribution. 10 * * Neither the name of Freescale Semiconductor nor the 11 * names of its contributors may be used to endorse or promote products 12 * derived from this software without specific prior written permission. 13 * 14 * ALTERNATIVELY, this software may be distributed under the terms of the 15 * GNU General Public License ("GPL") as published by the Free Software 16 * Foundation, either version 2 of that License or (at your option) any 17 * later version. 18 * 19 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 20 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 32 33 #include <linux/init.h> 34 #include <linux/module.h> 35 #include <linux/of_platform.h> 36 #include <linux/of_mdio.h> 37 #include <linux/of_net.h> 38 #include <linux/io.h> 39 #include <linux/if_arp.h> 40 #include <linux/if_vlan.h> 41 #include <linux/icmp.h> 42 #include <linux/ip.h> 43 #include <linux/ipv6.h> 44 #include <linux/udp.h> 45 #include <linux/tcp.h> 46 #include <linux/net.h> 47 #include <linux/skbuff.h> 48 #include <linux/etherdevice.h> 49 #include <linux/if_ether.h> 50 #include <linux/highmem.h> 51 #include <linux/percpu.h> 52 #include <linux/dma-mapping.h> 53 #include <linux/sort.h> 54 #include <linux/phy_fixed.h> 55 #include <soc/fsl/bman.h> 56 #include <soc/fsl/qman.h> 57 #include "fman.h" 58 #include "fman_port.h" 59 #include "mac.h" 60 #include "dpaa_eth.h" 61 62 /* CREATE_TRACE_POINTS only needs to be defined once. Other dpaa files 63 * using trace events only need to #include <trace/events/sched.h> 64 */ 65 #define CREATE_TRACE_POINTS 66 #include "dpaa_eth_trace.h" 67 68 static int debug = -1; 69 module_param(debug, int, 0444); 70 MODULE_PARM_DESC(debug, "Module/Driver verbosity level (0=none,...,16=all)"); 71 72 static u16 tx_timeout = 1000; 73 module_param(tx_timeout, ushort, 0444); 74 MODULE_PARM_DESC(tx_timeout, "The Tx timeout in ms"); 75 76 #define FM_FD_STAT_RX_ERRORS \ 77 (FM_FD_ERR_DMA | FM_FD_ERR_PHYSICAL | \ 78 FM_FD_ERR_SIZE | FM_FD_ERR_CLS_DISCARD | \ 79 FM_FD_ERR_EXTRACTION | FM_FD_ERR_NO_SCHEME | \ 80 FM_FD_ERR_PRS_TIMEOUT | FM_FD_ERR_PRS_ILL_INSTRUCT | \ 81 FM_FD_ERR_PRS_HDR_ERR) 82 83 #define FM_FD_STAT_TX_ERRORS \ 84 (FM_FD_ERR_UNSUPPORTED_FORMAT | \ 85 FM_FD_ERR_LENGTH | FM_FD_ERR_DMA) 86 87 #define DPAA_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \ 88 NETIF_MSG_LINK | NETIF_MSG_IFUP | \ 89 NETIF_MSG_IFDOWN) 90 91 #define DPAA_INGRESS_CS_THRESHOLD 0x10000000 92 /* Ingress congestion threshold on FMan ports 93 * The size in bytes of the ingress tail-drop threshold on FMan ports. 94 * Traffic piling up above this value will be rejected by QMan and discarded 95 * by FMan. 96 */ 97 98 /* Size in bytes of the FQ taildrop threshold */ 99 #define DPAA_FQ_TD 0x200000 100 101 #define DPAA_CS_THRESHOLD_1G 0x06000000 102 /* Egress congestion threshold on 1G ports, range 0x1000 .. 0x10000000 103 * The size in bytes of the egress Congestion State notification threshold on 104 * 1G ports. The 1G dTSECs can quite easily be flooded by cores doing Tx in a 105 * tight loop (e.g. by sending UDP datagrams at "while(1) speed"), 106 * and the larger the frame size, the more acute the problem. 107 * So we have to find a balance between these factors: 108 * - avoiding the device staying congested for a prolonged time (risking 109 * the netdev watchdog to fire - see also the tx_timeout module param); 110 * - affecting performance of protocols such as TCP, which otherwise 111 * behave well under the congestion notification mechanism; 112 * - preventing the Tx cores from tightly-looping (as if the congestion 113 * threshold was too low to be effective); 114 * - running out of memory if the CS threshold is set too high. 115 */ 116 117 #define DPAA_CS_THRESHOLD_10G 0x10000000 118 /* The size in bytes of the egress Congestion State notification threshold on 119 * 10G ports, range 0x1000 .. 0x10000000 120 */ 121 122 /* Largest value that the FQD's OAL field can hold */ 123 #define FSL_QMAN_MAX_OAL 127 124 125 /* Default alignment for start of data in an Rx FD */ 126 #define DPAA_FD_DATA_ALIGNMENT 16 127 128 /* The DPAA requires 256 bytes reserved and mapped for the SGT */ 129 #define DPAA_SGT_SIZE 256 130 131 /* Values for the L3R field of the FM Parse Results 132 */ 133 /* L3 Type field: First IP Present IPv4 */ 134 #define FM_L3_PARSE_RESULT_IPV4 0x8000 135 /* L3 Type field: First IP Present IPv6 */ 136 #define FM_L3_PARSE_RESULT_IPV6 0x4000 137 /* Values for the L4R field of the FM Parse Results */ 138 /* L4 Type field: UDP */ 139 #define FM_L4_PARSE_RESULT_UDP 0x40 140 /* L4 Type field: TCP */ 141 #define FM_L4_PARSE_RESULT_TCP 0x20 142 143 /* FD status field indicating whether the FM Parser has attempted to validate 144 * the L4 csum of the frame. 145 * Note that having this bit set doesn't necessarily imply that the checksum 146 * is valid. One would have to check the parse results to find that out. 147 */ 148 #define FM_FD_STAT_L4CV 0x00000004 149 150 #define DPAA_SGT_MAX_ENTRIES 16 /* maximum number of entries in SG Table */ 151 #define DPAA_BUFF_RELEASE_MAX 8 /* maximum number of buffers released at once */ 152 153 #define FSL_DPAA_BPID_INV 0xff 154 #define FSL_DPAA_ETH_MAX_BUF_COUNT 128 155 #define FSL_DPAA_ETH_REFILL_THRESHOLD 80 156 157 #define DPAA_TX_PRIV_DATA_SIZE 16 158 #define DPAA_PARSE_RESULTS_SIZE sizeof(struct fman_prs_result) 159 #define DPAA_TIME_STAMP_SIZE 8 160 #define DPAA_HASH_RESULTS_SIZE 8 161 #define DPAA_RX_PRIV_DATA_SIZE (u16)(DPAA_TX_PRIV_DATA_SIZE + \ 162 dpaa_rx_extra_headroom) 163 164 #define DPAA_ETH_PCD_RXQ_NUM 128 165 166 #define DPAA_ENQUEUE_RETRIES 100000 167 168 enum port_type {RX, TX}; 169 170 struct fm_port_fqs { 171 struct dpaa_fq *tx_defq; 172 struct dpaa_fq *tx_errq; 173 struct dpaa_fq *rx_defq; 174 struct dpaa_fq *rx_errq; 175 struct dpaa_fq *rx_pcdq; 176 }; 177 178 /* All the dpa bps in use at any moment */ 179 static struct dpaa_bp *dpaa_bp_array[BM_MAX_NUM_OF_POOLS]; 180 181 #define DPAA_BP_RAW_SIZE 4096 182 183 #define dpaa_bp_size(raw_size) SKB_WITH_OVERHEAD(raw_size) 184 185 static int dpaa_max_frm; 186 187 static int dpaa_rx_extra_headroom; 188 189 #define dpaa_get_max_mtu() \ 190 (dpaa_max_frm - (VLAN_ETH_HLEN + ETH_FCS_LEN)) 191 192 static int dpaa_netdev_init(struct net_device *net_dev, 193 const struct net_device_ops *dpaa_ops, 194 u16 tx_timeout) 195 { 196 struct dpaa_priv *priv = netdev_priv(net_dev); 197 struct device *dev = net_dev->dev.parent; 198 struct dpaa_percpu_priv *percpu_priv; 199 const u8 *mac_addr; 200 int i, err; 201 202 /* Although we access another CPU's private data here 203 * we do it at initialization so it is safe 204 */ 205 for_each_possible_cpu(i) { 206 percpu_priv = per_cpu_ptr(priv->percpu_priv, i); 207 percpu_priv->net_dev = net_dev; 208 } 209 210 net_dev->netdev_ops = dpaa_ops; 211 mac_addr = priv->mac_dev->addr; 212 213 net_dev->mem_start = priv->mac_dev->res->start; 214 net_dev->mem_end = priv->mac_dev->res->end; 215 216 net_dev->min_mtu = ETH_MIN_MTU; 217 net_dev->max_mtu = dpaa_get_max_mtu(); 218 219 net_dev->hw_features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 220 NETIF_F_LLTX | NETIF_F_RXHASH); 221 222 net_dev->hw_features |= NETIF_F_SG | NETIF_F_HIGHDMA; 223 /* The kernels enables GSO automatically, if we declare NETIF_F_SG. 224 * For conformity, we'll still declare GSO explicitly. 225 */ 226 net_dev->features |= NETIF_F_GSO; 227 net_dev->features |= NETIF_F_RXCSUM; 228 229 net_dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 230 /* we do not want shared skbs on TX */ 231 net_dev->priv_flags &= ~IFF_TX_SKB_SHARING; 232 233 net_dev->features |= net_dev->hw_features; 234 net_dev->vlan_features = net_dev->features; 235 236 if (is_valid_ether_addr(mac_addr)) { 237 memcpy(net_dev->perm_addr, mac_addr, net_dev->addr_len); 238 memcpy(net_dev->dev_addr, mac_addr, net_dev->addr_len); 239 } else { 240 eth_hw_addr_random(net_dev); 241 err = priv->mac_dev->change_addr(priv->mac_dev->fman_mac, 242 (enet_addr_t *)net_dev->dev_addr); 243 if (err) { 244 dev_err(dev, "Failed to set random MAC address\n"); 245 return -EINVAL; 246 } 247 dev_info(dev, "Using random MAC address: %pM\n", 248 net_dev->dev_addr); 249 } 250 251 net_dev->ethtool_ops = &dpaa_ethtool_ops; 252 253 net_dev->needed_headroom = priv->tx_headroom; 254 net_dev->watchdog_timeo = msecs_to_jiffies(tx_timeout); 255 256 /* start without the RUNNING flag, phylib controls it later */ 257 netif_carrier_off(net_dev); 258 259 err = register_netdev(net_dev); 260 if (err < 0) { 261 dev_err(dev, "register_netdev() = %d\n", err); 262 return err; 263 } 264 265 return 0; 266 } 267 268 static int dpaa_stop(struct net_device *net_dev) 269 { 270 struct mac_device *mac_dev; 271 struct dpaa_priv *priv; 272 int i, err, error; 273 274 priv = netdev_priv(net_dev); 275 mac_dev = priv->mac_dev; 276 277 netif_tx_stop_all_queues(net_dev); 278 /* Allow the Fman (Tx) port to process in-flight frames before we 279 * try switching it off. 280 */ 281 msleep(200); 282 283 err = mac_dev->stop(mac_dev); 284 if (err < 0) 285 netif_err(priv, ifdown, net_dev, "mac_dev->stop() = %d\n", 286 err); 287 288 for (i = 0; i < ARRAY_SIZE(mac_dev->port); i++) { 289 error = fman_port_disable(mac_dev->port[i]); 290 if (error) 291 err = error; 292 } 293 294 if (net_dev->phydev) 295 phy_disconnect(net_dev->phydev); 296 net_dev->phydev = NULL; 297 298 msleep(200); 299 300 return err; 301 } 302 303 static void dpaa_tx_timeout(struct net_device *net_dev, unsigned int txqueue) 304 { 305 struct dpaa_percpu_priv *percpu_priv; 306 const struct dpaa_priv *priv; 307 308 priv = netdev_priv(net_dev); 309 percpu_priv = this_cpu_ptr(priv->percpu_priv); 310 311 netif_crit(priv, timer, net_dev, "Transmit timeout latency: %u ms\n", 312 jiffies_to_msecs(jiffies - dev_trans_start(net_dev))); 313 314 percpu_priv->stats.tx_errors++; 315 } 316 317 /* Calculates the statistics for the given device by adding the statistics 318 * collected by each CPU. 319 */ 320 static void dpaa_get_stats64(struct net_device *net_dev, 321 struct rtnl_link_stats64 *s) 322 { 323 int numstats = sizeof(struct rtnl_link_stats64) / sizeof(u64); 324 struct dpaa_priv *priv = netdev_priv(net_dev); 325 struct dpaa_percpu_priv *percpu_priv; 326 u64 *netstats = (u64 *)s; 327 u64 *cpustats; 328 int i, j; 329 330 for_each_possible_cpu(i) { 331 percpu_priv = per_cpu_ptr(priv->percpu_priv, i); 332 333 cpustats = (u64 *)&percpu_priv->stats; 334 335 /* add stats from all CPUs */ 336 for (j = 0; j < numstats; j++) 337 netstats[j] += cpustats[j]; 338 } 339 } 340 341 static int dpaa_setup_tc(struct net_device *net_dev, enum tc_setup_type type, 342 void *type_data) 343 { 344 struct dpaa_priv *priv = netdev_priv(net_dev); 345 struct tc_mqprio_qopt *mqprio = type_data; 346 u8 num_tc; 347 int i; 348 349 if (type != TC_SETUP_QDISC_MQPRIO) 350 return -EOPNOTSUPP; 351 352 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS; 353 num_tc = mqprio->num_tc; 354 355 if (num_tc == priv->num_tc) 356 return 0; 357 358 if (!num_tc) { 359 netdev_reset_tc(net_dev); 360 goto out; 361 } 362 363 if (num_tc > DPAA_TC_NUM) { 364 netdev_err(net_dev, "Too many traffic classes: max %d supported.\n", 365 DPAA_TC_NUM); 366 return -EINVAL; 367 } 368 369 netdev_set_num_tc(net_dev, num_tc); 370 371 for (i = 0; i < num_tc; i++) 372 netdev_set_tc_queue(net_dev, i, DPAA_TC_TXQ_NUM, 373 i * DPAA_TC_TXQ_NUM); 374 375 out: 376 priv->num_tc = num_tc ? : 1; 377 netif_set_real_num_tx_queues(net_dev, priv->num_tc * DPAA_TC_TXQ_NUM); 378 return 0; 379 } 380 381 static struct mac_device *dpaa_mac_dev_get(struct platform_device *pdev) 382 { 383 struct dpaa_eth_data *eth_data; 384 struct device *dpaa_dev; 385 struct mac_device *mac_dev; 386 387 dpaa_dev = &pdev->dev; 388 eth_data = dpaa_dev->platform_data; 389 if (!eth_data) { 390 dev_err(dpaa_dev, "eth_data missing\n"); 391 return ERR_PTR(-ENODEV); 392 } 393 mac_dev = eth_data->mac_dev; 394 if (!mac_dev) { 395 dev_err(dpaa_dev, "mac_dev missing\n"); 396 return ERR_PTR(-EINVAL); 397 } 398 399 return mac_dev; 400 } 401 402 static int dpaa_set_mac_address(struct net_device *net_dev, void *addr) 403 { 404 const struct dpaa_priv *priv; 405 struct mac_device *mac_dev; 406 struct sockaddr old_addr; 407 int err; 408 409 priv = netdev_priv(net_dev); 410 411 memcpy(old_addr.sa_data, net_dev->dev_addr, ETH_ALEN); 412 413 err = eth_mac_addr(net_dev, addr); 414 if (err < 0) { 415 netif_err(priv, drv, net_dev, "eth_mac_addr() = %d\n", err); 416 return err; 417 } 418 419 mac_dev = priv->mac_dev; 420 421 err = mac_dev->change_addr(mac_dev->fman_mac, 422 (enet_addr_t *)net_dev->dev_addr); 423 if (err < 0) { 424 netif_err(priv, drv, net_dev, "mac_dev->change_addr() = %d\n", 425 err); 426 /* reverting to previous address */ 427 eth_mac_addr(net_dev, &old_addr); 428 429 return err; 430 } 431 432 return 0; 433 } 434 435 static void dpaa_set_rx_mode(struct net_device *net_dev) 436 { 437 const struct dpaa_priv *priv; 438 int err; 439 440 priv = netdev_priv(net_dev); 441 442 if (!!(net_dev->flags & IFF_PROMISC) != priv->mac_dev->promisc) { 443 priv->mac_dev->promisc = !priv->mac_dev->promisc; 444 err = priv->mac_dev->set_promisc(priv->mac_dev->fman_mac, 445 priv->mac_dev->promisc); 446 if (err < 0) 447 netif_err(priv, drv, net_dev, 448 "mac_dev->set_promisc() = %d\n", 449 err); 450 } 451 452 if (!!(net_dev->flags & IFF_ALLMULTI) != priv->mac_dev->allmulti) { 453 priv->mac_dev->allmulti = !priv->mac_dev->allmulti; 454 err = priv->mac_dev->set_allmulti(priv->mac_dev->fman_mac, 455 priv->mac_dev->allmulti); 456 if (err < 0) 457 netif_err(priv, drv, net_dev, 458 "mac_dev->set_allmulti() = %d\n", 459 err); 460 } 461 462 err = priv->mac_dev->set_multi(net_dev, priv->mac_dev); 463 if (err < 0) 464 netif_err(priv, drv, net_dev, "mac_dev->set_multi() = %d\n", 465 err); 466 } 467 468 static struct dpaa_bp *dpaa_bpid2pool(int bpid) 469 { 470 if (WARN_ON(bpid < 0 || bpid >= BM_MAX_NUM_OF_POOLS)) 471 return NULL; 472 473 return dpaa_bp_array[bpid]; 474 } 475 476 /* checks if this bpool is already allocated */ 477 static bool dpaa_bpid2pool_use(int bpid) 478 { 479 if (dpaa_bpid2pool(bpid)) { 480 refcount_inc(&dpaa_bp_array[bpid]->refs); 481 return true; 482 } 483 484 return false; 485 } 486 487 /* called only once per bpid by dpaa_bp_alloc_pool() */ 488 static void dpaa_bpid2pool_map(int bpid, struct dpaa_bp *dpaa_bp) 489 { 490 dpaa_bp_array[bpid] = dpaa_bp; 491 refcount_set(&dpaa_bp->refs, 1); 492 } 493 494 static int dpaa_bp_alloc_pool(struct dpaa_bp *dpaa_bp) 495 { 496 int err; 497 498 if (dpaa_bp->size == 0 || dpaa_bp->config_count == 0) { 499 pr_err("%s: Buffer pool is not properly initialized! Missing size or initial number of buffers\n", 500 __func__); 501 return -EINVAL; 502 } 503 504 /* If the pool is already specified, we only create one per bpid */ 505 if (dpaa_bp->bpid != FSL_DPAA_BPID_INV && 506 dpaa_bpid2pool_use(dpaa_bp->bpid)) 507 return 0; 508 509 if (dpaa_bp->bpid == FSL_DPAA_BPID_INV) { 510 dpaa_bp->pool = bman_new_pool(); 511 if (!dpaa_bp->pool) { 512 pr_err("%s: bman_new_pool() failed\n", 513 __func__); 514 return -ENODEV; 515 } 516 517 dpaa_bp->bpid = (u8)bman_get_bpid(dpaa_bp->pool); 518 } 519 520 if (dpaa_bp->seed_cb) { 521 err = dpaa_bp->seed_cb(dpaa_bp); 522 if (err) 523 goto pool_seed_failed; 524 } 525 526 dpaa_bpid2pool_map(dpaa_bp->bpid, dpaa_bp); 527 528 return 0; 529 530 pool_seed_failed: 531 pr_err("%s: pool seeding failed\n", __func__); 532 bman_free_pool(dpaa_bp->pool); 533 534 return err; 535 } 536 537 /* remove and free all the buffers from the given buffer pool */ 538 static void dpaa_bp_drain(struct dpaa_bp *bp) 539 { 540 u8 num = 8; 541 int ret; 542 543 do { 544 struct bm_buffer bmb[8]; 545 int i; 546 547 ret = bman_acquire(bp->pool, bmb, num); 548 if (ret < 0) { 549 if (num == 8) { 550 /* we have less than 8 buffers left; 551 * drain them one by one 552 */ 553 num = 1; 554 ret = 1; 555 continue; 556 } else { 557 /* Pool is fully drained */ 558 break; 559 } 560 } 561 562 if (bp->free_buf_cb) 563 for (i = 0; i < num; i++) 564 bp->free_buf_cb(bp, &bmb[i]); 565 } while (ret > 0); 566 } 567 568 static void dpaa_bp_free(struct dpaa_bp *dpaa_bp) 569 { 570 struct dpaa_bp *bp = dpaa_bpid2pool(dpaa_bp->bpid); 571 572 /* the mapping between bpid and dpaa_bp is done very late in the 573 * allocation procedure; if something failed before the mapping, the bp 574 * was not configured, therefore we don't need the below instructions 575 */ 576 if (!bp) 577 return; 578 579 if (!refcount_dec_and_test(&bp->refs)) 580 return; 581 582 if (bp->free_buf_cb) 583 dpaa_bp_drain(bp); 584 585 dpaa_bp_array[bp->bpid] = NULL; 586 bman_free_pool(bp->pool); 587 } 588 589 static void dpaa_bps_free(struct dpaa_priv *priv) 590 { 591 dpaa_bp_free(priv->dpaa_bp); 592 } 593 594 /* Use multiple WQs for FQ assignment: 595 * - Tx Confirmation queues go to WQ1. 596 * - Rx Error and Tx Error queues go to WQ5 (giving them a better chance 597 * to be scheduled, in case there are many more FQs in WQ6). 598 * - Rx Default goes to WQ6. 599 * - Tx queues go to different WQs depending on their priority. Equal 600 * chunks of NR_CPUS queues go to WQ6 (lowest priority), WQ2, WQ1 and 601 * WQ0 (highest priority). 602 * This ensures that Tx-confirmed buffers are timely released. In particular, 603 * it avoids congestion on the Tx Confirm FQs, which can pile up PFDRs if they 604 * are greatly outnumbered by other FQs in the system, while 605 * dequeue scheduling is round-robin. 606 */ 607 static inline void dpaa_assign_wq(struct dpaa_fq *fq, int idx) 608 { 609 switch (fq->fq_type) { 610 case FQ_TYPE_TX_CONFIRM: 611 case FQ_TYPE_TX_CONF_MQ: 612 fq->wq = 1; 613 break; 614 case FQ_TYPE_RX_ERROR: 615 case FQ_TYPE_TX_ERROR: 616 fq->wq = 5; 617 break; 618 case FQ_TYPE_RX_DEFAULT: 619 case FQ_TYPE_RX_PCD: 620 fq->wq = 6; 621 break; 622 case FQ_TYPE_TX: 623 switch (idx / DPAA_TC_TXQ_NUM) { 624 case 0: 625 /* Low priority (best effort) */ 626 fq->wq = 6; 627 break; 628 case 1: 629 /* Medium priority */ 630 fq->wq = 2; 631 break; 632 case 2: 633 /* High priority */ 634 fq->wq = 1; 635 break; 636 case 3: 637 /* Very high priority */ 638 fq->wq = 0; 639 break; 640 default: 641 WARN(1, "Too many TX FQs: more than %d!\n", 642 DPAA_ETH_TXQ_NUM); 643 } 644 break; 645 default: 646 WARN(1, "Invalid FQ type %d for FQID %d!\n", 647 fq->fq_type, fq->fqid); 648 } 649 } 650 651 static struct dpaa_fq *dpaa_fq_alloc(struct device *dev, 652 u32 start, u32 count, 653 struct list_head *list, 654 enum dpaa_fq_type fq_type) 655 { 656 struct dpaa_fq *dpaa_fq; 657 int i; 658 659 dpaa_fq = devm_kcalloc(dev, count, sizeof(*dpaa_fq), 660 GFP_KERNEL); 661 if (!dpaa_fq) 662 return NULL; 663 664 for (i = 0; i < count; i++) { 665 dpaa_fq[i].fq_type = fq_type; 666 dpaa_fq[i].fqid = start ? start + i : 0; 667 list_add_tail(&dpaa_fq[i].list, list); 668 } 669 670 for (i = 0; i < count; i++) 671 dpaa_assign_wq(dpaa_fq + i, i); 672 673 return dpaa_fq; 674 } 675 676 static int dpaa_alloc_all_fqs(struct device *dev, struct list_head *list, 677 struct fm_port_fqs *port_fqs) 678 { 679 struct dpaa_fq *dpaa_fq; 680 u32 fq_base, fq_base_aligned, i; 681 682 dpaa_fq = dpaa_fq_alloc(dev, 0, 1, list, FQ_TYPE_RX_ERROR); 683 if (!dpaa_fq) 684 goto fq_alloc_failed; 685 686 port_fqs->rx_errq = &dpaa_fq[0]; 687 688 dpaa_fq = dpaa_fq_alloc(dev, 0, 1, list, FQ_TYPE_RX_DEFAULT); 689 if (!dpaa_fq) 690 goto fq_alloc_failed; 691 692 port_fqs->rx_defq = &dpaa_fq[0]; 693 694 /* the PCD FQIDs range needs to be aligned for correct operation */ 695 if (qman_alloc_fqid_range(&fq_base, 2 * DPAA_ETH_PCD_RXQ_NUM)) 696 goto fq_alloc_failed; 697 698 fq_base_aligned = ALIGN(fq_base, DPAA_ETH_PCD_RXQ_NUM); 699 700 for (i = fq_base; i < fq_base_aligned; i++) 701 qman_release_fqid(i); 702 703 for (i = fq_base_aligned + DPAA_ETH_PCD_RXQ_NUM; 704 i < (fq_base + 2 * DPAA_ETH_PCD_RXQ_NUM); i++) 705 qman_release_fqid(i); 706 707 dpaa_fq = dpaa_fq_alloc(dev, fq_base_aligned, DPAA_ETH_PCD_RXQ_NUM, 708 list, FQ_TYPE_RX_PCD); 709 if (!dpaa_fq) 710 goto fq_alloc_failed; 711 712 port_fqs->rx_pcdq = &dpaa_fq[0]; 713 714 if (!dpaa_fq_alloc(dev, 0, DPAA_ETH_TXQ_NUM, list, FQ_TYPE_TX_CONF_MQ)) 715 goto fq_alloc_failed; 716 717 dpaa_fq = dpaa_fq_alloc(dev, 0, 1, list, FQ_TYPE_TX_ERROR); 718 if (!dpaa_fq) 719 goto fq_alloc_failed; 720 721 port_fqs->tx_errq = &dpaa_fq[0]; 722 723 dpaa_fq = dpaa_fq_alloc(dev, 0, 1, list, FQ_TYPE_TX_CONFIRM); 724 if (!dpaa_fq) 725 goto fq_alloc_failed; 726 727 port_fqs->tx_defq = &dpaa_fq[0]; 728 729 if (!dpaa_fq_alloc(dev, 0, DPAA_ETH_TXQ_NUM, list, FQ_TYPE_TX)) 730 goto fq_alloc_failed; 731 732 return 0; 733 734 fq_alloc_failed: 735 dev_err(dev, "dpaa_fq_alloc() failed\n"); 736 return -ENOMEM; 737 } 738 739 static u32 rx_pool_channel; 740 static DEFINE_SPINLOCK(rx_pool_channel_init); 741 742 static int dpaa_get_channel(void) 743 { 744 spin_lock(&rx_pool_channel_init); 745 if (!rx_pool_channel) { 746 u32 pool; 747 int ret; 748 749 ret = qman_alloc_pool(&pool); 750 751 if (!ret) 752 rx_pool_channel = pool; 753 } 754 spin_unlock(&rx_pool_channel_init); 755 if (!rx_pool_channel) 756 return -ENOMEM; 757 return rx_pool_channel; 758 } 759 760 static void dpaa_release_channel(void) 761 { 762 qman_release_pool(rx_pool_channel); 763 } 764 765 static void dpaa_eth_add_channel(u16 channel, struct device *dev) 766 { 767 u32 pool = QM_SDQCR_CHANNELS_POOL_CONV(channel); 768 const cpumask_t *cpus = qman_affine_cpus(); 769 struct qman_portal *portal; 770 int cpu; 771 772 for_each_cpu_and(cpu, cpus, cpu_online_mask) { 773 portal = qman_get_affine_portal(cpu); 774 qman_p_static_dequeue_add(portal, pool); 775 qman_start_using_portal(portal, dev); 776 } 777 } 778 779 /* Congestion group state change notification callback. 780 * Stops the device's egress queues while they are congested and 781 * wakes them upon exiting congested state. 782 * Also updates some CGR-related stats. 783 */ 784 static void dpaa_eth_cgscn(struct qman_portal *qm, struct qman_cgr *cgr, 785 int congested) 786 { 787 struct dpaa_priv *priv = (struct dpaa_priv *)container_of(cgr, 788 struct dpaa_priv, cgr_data.cgr); 789 790 if (congested) { 791 priv->cgr_data.congestion_start_jiffies = jiffies; 792 netif_tx_stop_all_queues(priv->net_dev); 793 priv->cgr_data.cgr_congested_count++; 794 } else { 795 priv->cgr_data.congested_jiffies += 796 (jiffies - priv->cgr_data.congestion_start_jiffies); 797 netif_tx_wake_all_queues(priv->net_dev); 798 } 799 } 800 801 static int dpaa_eth_cgr_init(struct dpaa_priv *priv) 802 { 803 struct qm_mcc_initcgr initcgr; 804 u32 cs_th; 805 int err; 806 807 err = qman_alloc_cgrid(&priv->cgr_data.cgr.cgrid); 808 if (err < 0) { 809 if (netif_msg_drv(priv)) 810 pr_err("%s: Error %d allocating CGR ID\n", 811 __func__, err); 812 goto out_error; 813 } 814 priv->cgr_data.cgr.cb = dpaa_eth_cgscn; 815 816 /* Enable Congestion State Change Notifications and CS taildrop */ 817 memset(&initcgr, 0, sizeof(initcgr)); 818 initcgr.we_mask = cpu_to_be16(QM_CGR_WE_CSCN_EN | QM_CGR_WE_CS_THRES); 819 initcgr.cgr.cscn_en = QM_CGR_EN; 820 821 /* Set different thresholds based on the MAC speed. 822 * This may turn suboptimal if the MAC is reconfigured at a speed 823 * lower than its max, e.g. if a dTSEC later negotiates a 100Mbps link. 824 * In such cases, we ought to reconfigure the threshold, too. 825 */ 826 if (priv->mac_dev->if_support & SUPPORTED_10000baseT_Full) 827 cs_th = DPAA_CS_THRESHOLD_10G; 828 else 829 cs_th = DPAA_CS_THRESHOLD_1G; 830 qm_cgr_cs_thres_set64(&initcgr.cgr.cs_thres, cs_th, 1); 831 832 initcgr.we_mask |= cpu_to_be16(QM_CGR_WE_CSTD_EN); 833 initcgr.cgr.cstd_en = QM_CGR_EN; 834 835 err = qman_create_cgr(&priv->cgr_data.cgr, QMAN_CGR_FLAG_USE_INIT, 836 &initcgr); 837 if (err < 0) { 838 if (netif_msg_drv(priv)) 839 pr_err("%s: Error %d creating CGR with ID %d\n", 840 __func__, err, priv->cgr_data.cgr.cgrid); 841 qman_release_cgrid(priv->cgr_data.cgr.cgrid); 842 goto out_error; 843 } 844 if (netif_msg_drv(priv)) 845 pr_debug("Created CGR %d for netdev with hwaddr %pM on QMan channel %d\n", 846 priv->cgr_data.cgr.cgrid, priv->mac_dev->addr, 847 priv->cgr_data.cgr.chan); 848 849 out_error: 850 return err; 851 } 852 853 static inline void dpaa_setup_ingress(const struct dpaa_priv *priv, 854 struct dpaa_fq *fq, 855 const struct qman_fq *template) 856 { 857 fq->fq_base = *template; 858 fq->net_dev = priv->net_dev; 859 860 fq->flags = QMAN_FQ_FLAG_NO_ENQUEUE; 861 fq->channel = priv->channel; 862 } 863 864 static inline void dpaa_setup_egress(const struct dpaa_priv *priv, 865 struct dpaa_fq *fq, 866 struct fman_port *port, 867 const struct qman_fq *template) 868 { 869 fq->fq_base = *template; 870 fq->net_dev = priv->net_dev; 871 872 if (port) { 873 fq->flags = QMAN_FQ_FLAG_TO_DCPORTAL; 874 fq->channel = (u16)fman_port_get_qman_channel_id(port); 875 } else { 876 fq->flags = QMAN_FQ_FLAG_NO_MODIFY; 877 } 878 } 879 880 static void dpaa_fq_setup(struct dpaa_priv *priv, 881 const struct dpaa_fq_cbs *fq_cbs, 882 struct fman_port *tx_port) 883 { 884 int egress_cnt = 0, conf_cnt = 0, num_portals = 0, portal_cnt = 0, cpu; 885 const cpumask_t *affine_cpus = qman_affine_cpus(); 886 u16 channels[NR_CPUS]; 887 struct dpaa_fq *fq; 888 889 for_each_cpu_and(cpu, affine_cpus, cpu_online_mask) 890 channels[num_portals++] = qman_affine_channel(cpu); 891 892 if (num_portals == 0) 893 dev_err(priv->net_dev->dev.parent, 894 "No Qman software (affine) channels found\n"); 895 896 /* Initialize each FQ in the list */ 897 list_for_each_entry(fq, &priv->dpaa_fq_list, list) { 898 switch (fq->fq_type) { 899 case FQ_TYPE_RX_DEFAULT: 900 dpaa_setup_ingress(priv, fq, &fq_cbs->rx_defq); 901 break; 902 case FQ_TYPE_RX_ERROR: 903 dpaa_setup_ingress(priv, fq, &fq_cbs->rx_errq); 904 break; 905 case FQ_TYPE_RX_PCD: 906 if (!num_portals) 907 continue; 908 dpaa_setup_ingress(priv, fq, &fq_cbs->rx_defq); 909 fq->channel = channels[portal_cnt++ % num_portals]; 910 break; 911 case FQ_TYPE_TX: 912 dpaa_setup_egress(priv, fq, tx_port, 913 &fq_cbs->egress_ern); 914 /* If we have more Tx queues than the number of cores, 915 * just ignore the extra ones. 916 */ 917 if (egress_cnt < DPAA_ETH_TXQ_NUM) 918 priv->egress_fqs[egress_cnt++] = &fq->fq_base; 919 break; 920 case FQ_TYPE_TX_CONF_MQ: 921 priv->conf_fqs[conf_cnt++] = &fq->fq_base; 922 /* fall through */ 923 case FQ_TYPE_TX_CONFIRM: 924 dpaa_setup_ingress(priv, fq, &fq_cbs->tx_defq); 925 break; 926 case FQ_TYPE_TX_ERROR: 927 dpaa_setup_ingress(priv, fq, &fq_cbs->tx_errq); 928 break; 929 default: 930 dev_warn(priv->net_dev->dev.parent, 931 "Unknown FQ type detected!\n"); 932 break; 933 } 934 } 935 936 /* Make sure all CPUs receive a corresponding Tx queue. */ 937 while (egress_cnt < DPAA_ETH_TXQ_NUM) { 938 list_for_each_entry(fq, &priv->dpaa_fq_list, list) { 939 if (fq->fq_type != FQ_TYPE_TX) 940 continue; 941 priv->egress_fqs[egress_cnt++] = &fq->fq_base; 942 if (egress_cnt == DPAA_ETH_TXQ_NUM) 943 break; 944 } 945 } 946 } 947 948 static inline int dpaa_tx_fq_to_id(const struct dpaa_priv *priv, 949 struct qman_fq *tx_fq) 950 { 951 int i; 952 953 for (i = 0; i < DPAA_ETH_TXQ_NUM; i++) 954 if (priv->egress_fqs[i] == tx_fq) 955 return i; 956 957 return -EINVAL; 958 } 959 960 static int dpaa_fq_init(struct dpaa_fq *dpaa_fq, bool td_enable) 961 { 962 const struct dpaa_priv *priv; 963 struct qman_fq *confq = NULL; 964 struct qm_mcc_initfq initfq; 965 struct device *dev; 966 struct qman_fq *fq; 967 int queue_id; 968 int err; 969 970 priv = netdev_priv(dpaa_fq->net_dev); 971 dev = dpaa_fq->net_dev->dev.parent; 972 973 if (dpaa_fq->fqid == 0) 974 dpaa_fq->flags |= QMAN_FQ_FLAG_DYNAMIC_FQID; 975 976 dpaa_fq->init = !(dpaa_fq->flags & QMAN_FQ_FLAG_NO_MODIFY); 977 978 err = qman_create_fq(dpaa_fq->fqid, dpaa_fq->flags, &dpaa_fq->fq_base); 979 if (err) { 980 dev_err(dev, "qman_create_fq() failed\n"); 981 return err; 982 } 983 fq = &dpaa_fq->fq_base; 984 985 if (dpaa_fq->init) { 986 memset(&initfq, 0, sizeof(initfq)); 987 988 initfq.we_mask = cpu_to_be16(QM_INITFQ_WE_FQCTRL); 989 /* Note: we may get to keep an empty FQ in cache */ 990 initfq.fqd.fq_ctrl = cpu_to_be16(QM_FQCTRL_PREFERINCACHE); 991 992 /* Try to reduce the number of portal interrupts for 993 * Tx Confirmation FQs. 994 */ 995 if (dpaa_fq->fq_type == FQ_TYPE_TX_CONFIRM) 996 initfq.fqd.fq_ctrl |= cpu_to_be16(QM_FQCTRL_AVOIDBLOCK); 997 998 /* FQ placement */ 999 initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_DESTWQ); 1000 1001 qm_fqd_set_destwq(&initfq.fqd, dpaa_fq->channel, dpaa_fq->wq); 1002 1003 /* Put all egress queues in a congestion group of their own. 1004 * Sensu stricto, the Tx confirmation queues are Rx FQs, 1005 * rather than Tx - but they nonetheless account for the 1006 * memory footprint on behalf of egress traffic. We therefore 1007 * place them in the netdev's CGR, along with the Tx FQs. 1008 */ 1009 if (dpaa_fq->fq_type == FQ_TYPE_TX || 1010 dpaa_fq->fq_type == FQ_TYPE_TX_CONFIRM || 1011 dpaa_fq->fq_type == FQ_TYPE_TX_CONF_MQ) { 1012 initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_CGID); 1013 initfq.fqd.fq_ctrl |= cpu_to_be16(QM_FQCTRL_CGE); 1014 initfq.fqd.cgid = (u8)priv->cgr_data.cgr.cgrid; 1015 /* Set a fixed overhead accounting, in an attempt to 1016 * reduce the impact of fixed-size skb shells and the 1017 * driver's needed headroom on system memory. This is 1018 * especially the case when the egress traffic is 1019 * composed of small datagrams. 1020 * Unfortunately, QMan's OAL value is capped to an 1021 * insufficient value, but even that is better than 1022 * no overhead accounting at all. 1023 */ 1024 initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_OAC); 1025 qm_fqd_set_oac(&initfq.fqd, QM_OAC_CG); 1026 qm_fqd_set_oal(&initfq.fqd, 1027 min(sizeof(struct sk_buff) + 1028 priv->tx_headroom, 1029 (size_t)FSL_QMAN_MAX_OAL)); 1030 } 1031 1032 if (td_enable) { 1033 initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_TDTHRESH); 1034 qm_fqd_set_taildrop(&initfq.fqd, DPAA_FQ_TD, 1); 1035 initfq.fqd.fq_ctrl = cpu_to_be16(QM_FQCTRL_TDE); 1036 } 1037 1038 if (dpaa_fq->fq_type == FQ_TYPE_TX) { 1039 queue_id = dpaa_tx_fq_to_id(priv, &dpaa_fq->fq_base); 1040 if (queue_id >= 0) 1041 confq = priv->conf_fqs[queue_id]; 1042 if (confq) { 1043 initfq.we_mask |= 1044 cpu_to_be16(QM_INITFQ_WE_CONTEXTA); 1045 /* ContextA: OVOM=1(use contextA2 bits instead of ICAD) 1046 * A2V=1 (contextA A2 field is valid) 1047 * A0V=1 (contextA A0 field is valid) 1048 * B0V=1 (contextB field is valid) 1049 * ContextA A2: EBD=1 (deallocate buffers inside FMan) 1050 * ContextB B0(ASPID): 0 (absolute Virtual Storage ID) 1051 */ 1052 qm_fqd_context_a_set64(&initfq.fqd, 1053 0x1e00000080000000ULL); 1054 } 1055 } 1056 1057 /* Put all the ingress queues in our "ingress CGR". */ 1058 if (priv->use_ingress_cgr && 1059 (dpaa_fq->fq_type == FQ_TYPE_RX_DEFAULT || 1060 dpaa_fq->fq_type == FQ_TYPE_RX_ERROR || 1061 dpaa_fq->fq_type == FQ_TYPE_RX_PCD)) { 1062 initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_CGID); 1063 initfq.fqd.fq_ctrl |= cpu_to_be16(QM_FQCTRL_CGE); 1064 initfq.fqd.cgid = (u8)priv->ingress_cgr.cgrid; 1065 /* Set a fixed overhead accounting, just like for the 1066 * egress CGR. 1067 */ 1068 initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_OAC); 1069 qm_fqd_set_oac(&initfq.fqd, QM_OAC_CG); 1070 qm_fqd_set_oal(&initfq.fqd, 1071 min(sizeof(struct sk_buff) + 1072 priv->tx_headroom, 1073 (size_t)FSL_QMAN_MAX_OAL)); 1074 } 1075 1076 /* Initialization common to all ingress queues */ 1077 if (dpaa_fq->flags & QMAN_FQ_FLAG_NO_ENQUEUE) { 1078 initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_CONTEXTA); 1079 initfq.fqd.fq_ctrl |= cpu_to_be16(QM_FQCTRL_HOLDACTIVE | 1080 QM_FQCTRL_CTXASTASHING); 1081 initfq.fqd.context_a.stashing.exclusive = 1082 QM_STASHING_EXCL_DATA | QM_STASHING_EXCL_CTX | 1083 QM_STASHING_EXCL_ANNOTATION; 1084 qm_fqd_set_stashing(&initfq.fqd, 1, 2, 1085 DIV_ROUND_UP(sizeof(struct qman_fq), 1086 64)); 1087 } 1088 1089 err = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &initfq); 1090 if (err < 0) { 1091 dev_err(dev, "qman_init_fq(%u) = %d\n", 1092 qman_fq_fqid(fq), err); 1093 qman_destroy_fq(fq); 1094 return err; 1095 } 1096 } 1097 1098 dpaa_fq->fqid = qman_fq_fqid(fq); 1099 1100 return 0; 1101 } 1102 1103 static int dpaa_fq_free_entry(struct device *dev, struct qman_fq *fq) 1104 { 1105 const struct dpaa_priv *priv; 1106 struct dpaa_fq *dpaa_fq; 1107 int err, error; 1108 1109 err = 0; 1110 1111 dpaa_fq = container_of(fq, struct dpaa_fq, fq_base); 1112 priv = netdev_priv(dpaa_fq->net_dev); 1113 1114 if (dpaa_fq->init) { 1115 err = qman_retire_fq(fq, NULL); 1116 if (err < 0 && netif_msg_drv(priv)) 1117 dev_err(dev, "qman_retire_fq(%u) = %d\n", 1118 qman_fq_fqid(fq), err); 1119 1120 error = qman_oos_fq(fq); 1121 if (error < 0 && netif_msg_drv(priv)) { 1122 dev_err(dev, "qman_oos_fq(%u) = %d\n", 1123 qman_fq_fqid(fq), error); 1124 if (err >= 0) 1125 err = error; 1126 } 1127 } 1128 1129 qman_destroy_fq(fq); 1130 list_del(&dpaa_fq->list); 1131 1132 return err; 1133 } 1134 1135 static int dpaa_fq_free(struct device *dev, struct list_head *list) 1136 { 1137 struct dpaa_fq *dpaa_fq, *tmp; 1138 int err, error; 1139 1140 err = 0; 1141 list_for_each_entry_safe(dpaa_fq, tmp, list, list) { 1142 error = dpaa_fq_free_entry(dev, (struct qman_fq *)dpaa_fq); 1143 if (error < 0 && err >= 0) 1144 err = error; 1145 } 1146 1147 return err; 1148 } 1149 1150 static int dpaa_eth_init_tx_port(struct fman_port *port, struct dpaa_fq *errq, 1151 struct dpaa_fq *defq, 1152 struct dpaa_buffer_layout *buf_layout) 1153 { 1154 struct fman_buffer_prefix_content buf_prefix_content; 1155 struct fman_port_params params; 1156 int err; 1157 1158 memset(¶ms, 0, sizeof(params)); 1159 memset(&buf_prefix_content, 0, sizeof(buf_prefix_content)); 1160 1161 buf_prefix_content.priv_data_size = buf_layout->priv_data_size; 1162 buf_prefix_content.pass_prs_result = true; 1163 buf_prefix_content.pass_hash_result = true; 1164 buf_prefix_content.pass_time_stamp = true; 1165 buf_prefix_content.data_align = DPAA_FD_DATA_ALIGNMENT; 1166 1167 params.specific_params.non_rx_params.err_fqid = errq->fqid; 1168 params.specific_params.non_rx_params.dflt_fqid = defq->fqid; 1169 1170 err = fman_port_config(port, ¶ms); 1171 if (err) { 1172 pr_err("%s: fman_port_config failed\n", __func__); 1173 return err; 1174 } 1175 1176 err = fman_port_cfg_buf_prefix_content(port, &buf_prefix_content); 1177 if (err) { 1178 pr_err("%s: fman_port_cfg_buf_prefix_content failed\n", 1179 __func__); 1180 return err; 1181 } 1182 1183 err = fman_port_init(port); 1184 if (err) 1185 pr_err("%s: fm_port_init failed\n", __func__); 1186 1187 return err; 1188 } 1189 1190 static int dpaa_eth_init_rx_port(struct fman_port *port, struct dpaa_bp *bp, 1191 struct dpaa_fq *errq, 1192 struct dpaa_fq *defq, struct dpaa_fq *pcdq, 1193 struct dpaa_buffer_layout *buf_layout) 1194 { 1195 struct fman_buffer_prefix_content buf_prefix_content; 1196 struct fman_port_rx_params *rx_p; 1197 struct fman_port_params params; 1198 int err; 1199 1200 memset(¶ms, 0, sizeof(params)); 1201 memset(&buf_prefix_content, 0, sizeof(buf_prefix_content)); 1202 1203 buf_prefix_content.priv_data_size = buf_layout->priv_data_size; 1204 buf_prefix_content.pass_prs_result = true; 1205 buf_prefix_content.pass_hash_result = true; 1206 buf_prefix_content.pass_time_stamp = true; 1207 buf_prefix_content.data_align = DPAA_FD_DATA_ALIGNMENT; 1208 1209 rx_p = ¶ms.specific_params.rx_params; 1210 rx_p->err_fqid = errq->fqid; 1211 rx_p->dflt_fqid = defq->fqid; 1212 if (pcdq) { 1213 rx_p->pcd_base_fqid = pcdq->fqid; 1214 rx_p->pcd_fqs_count = DPAA_ETH_PCD_RXQ_NUM; 1215 } 1216 1217 rx_p->ext_buf_pools.num_of_pools_used = 1; 1218 rx_p->ext_buf_pools.ext_buf_pool[0].id = bp->bpid; 1219 rx_p->ext_buf_pools.ext_buf_pool[0].size = (u16)bp->size; 1220 1221 err = fman_port_config(port, ¶ms); 1222 if (err) { 1223 pr_err("%s: fman_port_config failed\n", __func__); 1224 return err; 1225 } 1226 1227 err = fman_port_cfg_buf_prefix_content(port, &buf_prefix_content); 1228 if (err) { 1229 pr_err("%s: fman_port_cfg_buf_prefix_content failed\n", 1230 __func__); 1231 return err; 1232 } 1233 1234 err = fman_port_init(port); 1235 if (err) 1236 pr_err("%s: fm_port_init failed\n", __func__); 1237 1238 return err; 1239 } 1240 1241 static int dpaa_eth_init_ports(struct mac_device *mac_dev, 1242 struct dpaa_bp *bp, 1243 struct fm_port_fqs *port_fqs, 1244 struct dpaa_buffer_layout *buf_layout, 1245 struct device *dev) 1246 { 1247 struct fman_port *rxport = mac_dev->port[RX]; 1248 struct fman_port *txport = mac_dev->port[TX]; 1249 int err; 1250 1251 err = dpaa_eth_init_tx_port(txport, port_fqs->tx_errq, 1252 port_fqs->tx_defq, &buf_layout[TX]); 1253 if (err) 1254 return err; 1255 1256 err = dpaa_eth_init_rx_port(rxport, bp, port_fqs->rx_errq, 1257 port_fqs->rx_defq, port_fqs->rx_pcdq, 1258 &buf_layout[RX]); 1259 1260 return err; 1261 } 1262 1263 static int dpaa_bman_release(const struct dpaa_bp *dpaa_bp, 1264 struct bm_buffer *bmb, int cnt) 1265 { 1266 int err; 1267 1268 err = bman_release(dpaa_bp->pool, bmb, cnt); 1269 /* Should never occur, address anyway to avoid leaking the buffers */ 1270 if (WARN_ON(err) && dpaa_bp->free_buf_cb) 1271 while (cnt-- > 0) 1272 dpaa_bp->free_buf_cb(dpaa_bp, &bmb[cnt]); 1273 1274 return cnt; 1275 } 1276 1277 static void dpaa_release_sgt_members(struct qm_sg_entry *sgt) 1278 { 1279 struct bm_buffer bmb[DPAA_BUFF_RELEASE_MAX]; 1280 struct dpaa_bp *dpaa_bp; 1281 int i = 0, j; 1282 1283 memset(bmb, 0, sizeof(bmb)); 1284 1285 do { 1286 dpaa_bp = dpaa_bpid2pool(sgt[i].bpid); 1287 if (!dpaa_bp) 1288 return; 1289 1290 j = 0; 1291 do { 1292 WARN_ON(qm_sg_entry_is_ext(&sgt[i])); 1293 1294 bm_buffer_set64(&bmb[j], qm_sg_entry_get64(&sgt[i])); 1295 1296 j++; i++; 1297 } while (j < ARRAY_SIZE(bmb) && 1298 !qm_sg_entry_is_final(&sgt[i - 1]) && 1299 sgt[i - 1].bpid == sgt[i].bpid); 1300 1301 dpaa_bman_release(dpaa_bp, bmb, j); 1302 } while (!qm_sg_entry_is_final(&sgt[i - 1])); 1303 } 1304 1305 static void dpaa_fd_release(const struct net_device *net_dev, 1306 const struct qm_fd *fd) 1307 { 1308 struct qm_sg_entry *sgt; 1309 struct dpaa_bp *dpaa_bp; 1310 struct bm_buffer bmb; 1311 dma_addr_t addr; 1312 void *vaddr; 1313 1314 bmb.data = 0; 1315 bm_buffer_set64(&bmb, qm_fd_addr(fd)); 1316 1317 dpaa_bp = dpaa_bpid2pool(fd->bpid); 1318 if (!dpaa_bp) 1319 return; 1320 1321 if (qm_fd_get_format(fd) == qm_fd_sg) { 1322 vaddr = phys_to_virt(qm_fd_addr(fd)); 1323 sgt = vaddr + qm_fd_get_offset(fd); 1324 1325 dma_unmap_page(dpaa_bp->priv->rx_dma_dev, qm_fd_addr(fd), 1326 DPAA_BP_RAW_SIZE, DMA_FROM_DEVICE); 1327 1328 dpaa_release_sgt_members(sgt); 1329 1330 addr = dma_map_page(dpaa_bp->priv->rx_dma_dev, 1331 virt_to_page(vaddr), 0, DPAA_BP_RAW_SIZE, 1332 DMA_FROM_DEVICE); 1333 if (dma_mapping_error(dpaa_bp->priv->rx_dma_dev, addr)) { 1334 netdev_err(net_dev, "DMA mapping failed\n"); 1335 return; 1336 } 1337 bm_buffer_set64(&bmb, addr); 1338 } 1339 1340 dpaa_bman_release(dpaa_bp, &bmb, 1); 1341 } 1342 1343 static void count_ern(struct dpaa_percpu_priv *percpu_priv, 1344 const union qm_mr_entry *msg) 1345 { 1346 switch (msg->ern.rc & QM_MR_RC_MASK) { 1347 case QM_MR_RC_CGR_TAILDROP: 1348 percpu_priv->ern_cnt.cg_tdrop++; 1349 break; 1350 case QM_MR_RC_WRED: 1351 percpu_priv->ern_cnt.wred++; 1352 break; 1353 case QM_MR_RC_ERROR: 1354 percpu_priv->ern_cnt.err_cond++; 1355 break; 1356 case QM_MR_RC_ORPWINDOW_EARLY: 1357 percpu_priv->ern_cnt.early_window++; 1358 break; 1359 case QM_MR_RC_ORPWINDOW_LATE: 1360 percpu_priv->ern_cnt.late_window++; 1361 break; 1362 case QM_MR_RC_FQ_TAILDROP: 1363 percpu_priv->ern_cnt.fq_tdrop++; 1364 break; 1365 case QM_MR_RC_ORPWINDOW_RETIRED: 1366 percpu_priv->ern_cnt.fq_retired++; 1367 break; 1368 case QM_MR_RC_ORP_ZERO: 1369 percpu_priv->ern_cnt.orp_zero++; 1370 break; 1371 } 1372 } 1373 1374 /* Turn on HW checksum computation for this outgoing frame. 1375 * If the current protocol is not something we support in this regard 1376 * (or if the stack has already computed the SW checksum), we do nothing. 1377 * 1378 * Returns 0 if all goes well (or HW csum doesn't apply), and a negative value 1379 * otherwise. 1380 * 1381 * Note that this function may modify the fd->cmd field and the skb data buffer 1382 * (the Parse Results area). 1383 */ 1384 static int dpaa_enable_tx_csum(struct dpaa_priv *priv, 1385 struct sk_buff *skb, 1386 struct qm_fd *fd, 1387 void *parse_results) 1388 { 1389 struct fman_prs_result *parse_result; 1390 u16 ethertype = ntohs(skb->protocol); 1391 struct ipv6hdr *ipv6h = NULL; 1392 struct iphdr *iph; 1393 int retval = 0; 1394 u8 l4_proto; 1395 1396 if (skb->ip_summed != CHECKSUM_PARTIAL) 1397 return 0; 1398 1399 /* Note: L3 csum seems to be already computed in sw, but we can't choose 1400 * L4 alone from the FM configuration anyway. 1401 */ 1402 1403 /* Fill in some fields of the Parse Results array, so the FMan 1404 * can find them as if they came from the FMan Parser. 1405 */ 1406 parse_result = (struct fman_prs_result *)parse_results; 1407 1408 /* If we're dealing with VLAN, get the real Ethernet type */ 1409 if (ethertype == ETH_P_8021Q) { 1410 /* We can't always assume the MAC header is set correctly 1411 * by the stack, so reset to beginning of skb->data 1412 */ 1413 skb_reset_mac_header(skb); 1414 ethertype = ntohs(vlan_eth_hdr(skb)->h_vlan_encapsulated_proto); 1415 } 1416 1417 /* Fill in the relevant L3 parse result fields 1418 * and read the L4 protocol type 1419 */ 1420 switch (ethertype) { 1421 case ETH_P_IP: 1422 parse_result->l3r = cpu_to_be16(FM_L3_PARSE_RESULT_IPV4); 1423 iph = ip_hdr(skb); 1424 WARN_ON(!iph); 1425 l4_proto = iph->protocol; 1426 break; 1427 case ETH_P_IPV6: 1428 parse_result->l3r = cpu_to_be16(FM_L3_PARSE_RESULT_IPV6); 1429 ipv6h = ipv6_hdr(skb); 1430 WARN_ON(!ipv6h); 1431 l4_proto = ipv6h->nexthdr; 1432 break; 1433 default: 1434 /* We shouldn't even be here */ 1435 if (net_ratelimit()) 1436 netif_alert(priv, tx_err, priv->net_dev, 1437 "Can't compute HW csum for L3 proto 0x%x\n", 1438 ntohs(skb->protocol)); 1439 retval = -EIO; 1440 goto return_error; 1441 } 1442 1443 /* Fill in the relevant L4 parse result fields */ 1444 switch (l4_proto) { 1445 case IPPROTO_UDP: 1446 parse_result->l4r = FM_L4_PARSE_RESULT_UDP; 1447 break; 1448 case IPPROTO_TCP: 1449 parse_result->l4r = FM_L4_PARSE_RESULT_TCP; 1450 break; 1451 default: 1452 if (net_ratelimit()) 1453 netif_alert(priv, tx_err, priv->net_dev, 1454 "Can't compute HW csum for L4 proto 0x%x\n", 1455 l4_proto); 1456 retval = -EIO; 1457 goto return_error; 1458 } 1459 1460 /* At index 0 is IPOffset_1 as defined in the Parse Results */ 1461 parse_result->ip_off[0] = (u8)skb_network_offset(skb); 1462 parse_result->l4_off = (u8)skb_transport_offset(skb); 1463 1464 /* Enable L3 (and L4, if TCP or UDP) HW checksum. */ 1465 fd->cmd |= cpu_to_be32(FM_FD_CMD_RPD | FM_FD_CMD_DTC); 1466 1467 /* On P1023 and similar platforms fd->cmd interpretation could 1468 * be disabled by setting CONTEXT_A bit ICMD; currently this bit 1469 * is not set so we do not need to check; in the future, if/when 1470 * using context_a we need to check this bit 1471 */ 1472 1473 return_error: 1474 return retval; 1475 } 1476 1477 static int dpaa_bp_add_8_bufs(const struct dpaa_bp *dpaa_bp) 1478 { 1479 struct net_device *net_dev = dpaa_bp->priv->net_dev; 1480 struct bm_buffer bmb[8]; 1481 dma_addr_t addr; 1482 struct page *p; 1483 u8 i; 1484 1485 for (i = 0; i < 8; i++) { 1486 p = dev_alloc_pages(0); 1487 if (unlikely(!p)) { 1488 netdev_err(net_dev, "dev_alloc_pages() failed\n"); 1489 goto release_previous_buffs; 1490 } 1491 1492 addr = dma_map_page(dpaa_bp->priv->rx_dma_dev, p, 0, 1493 DPAA_BP_RAW_SIZE, DMA_FROM_DEVICE); 1494 if (unlikely(dma_mapping_error(dpaa_bp->priv->rx_dma_dev, 1495 addr))) { 1496 netdev_err(net_dev, "DMA map failed\n"); 1497 goto release_previous_buffs; 1498 } 1499 1500 bmb[i].data = 0; 1501 bm_buffer_set64(&bmb[i], addr); 1502 } 1503 1504 release_bufs: 1505 return dpaa_bman_release(dpaa_bp, bmb, i); 1506 1507 release_previous_buffs: 1508 WARN_ONCE(1, "dpaa_eth: failed to add buffers on Rx\n"); 1509 1510 bm_buffer_set64(&bmb[i], 0); 1511 /* Avoid releasing a completely null buffer; bman_release() requires 1512 * at least one buffer. 1513 */ 1514 if (likely(i)) 1515 goto release_bufs; 1516 1517 return 0; 1518 } 1519 1520 static int dpaa_bp_seed(struct dpaa_bp *dpaa_bp) 1521 { 1522 int i; 1523 1524 /* Give each CPU an allotment of "config_count" buffers */ 1525 for_each_possible_cpu(i) { 1526 int *count_ptr = per_cpu_ptr(dpaa_bp->percpu_count, i); 1527 int j; 1528 1529 /* Although we access another CPU's counters here 1530 * we do it at boot time so it is safe 1531 */ 1532 for (j = 0; j < dpaa_bp->config_count; j += 8) 1533 *count_ptr += dpaa_bp_add_8_bufs(dpaa_bp); 1534 } 1535 return 0; 1536 } 1537 1538 /* Add buffers/(pages) for Rx processing whenever bpool count falls below 1539 * REFILL_THRESHOLD. 1540 */ 1541 static int dpaa_eth_refill_bpool(struct dpaa_bp *dpaa_bp, int *countptr) 1542 { 1543 int count = *countptr; 1544 int new_bufs; 1545 1546 if (unlikely(count < FSL_DPAA_ETH_REFILL_THRESHOLD)) { 1547 do { 1548 new_bufs = dpaa_bp_add_8_bufs(dpaa_bp); 1549 if (unlikely(!new_bufs)) { 1550 /* Avoid looping forever if we've temporarily 1551 * run out of memory. We'll try again at the 1552 * next NAPI cycle. 1553 */ 1554 break; 1555 } 1556 count += new_bufs; 1557 } while (count < FSL_DPAA_ETH_MAX_BUF_COUNT); 1558 1559 *countptr = count; 1560 if (unlikely(count < FSL_DPAA_ETH_MAX_BUF_COUNT)) 1561 return -ENOMEM; 1562 } 1563 1564 return 0; 1565 } 1566 1567 static int dpaa_eth_refill_bpools(struct dpaa_priv *priv) 1568 { 1569 struct dpaa_bp *dpaa_bp; 1570 int *countptr; 1571 int res; 1572 1573 dpaa_bp = priv->dpaa_bp; 1574 if (!dpaa_bp) 1575 return -EINVAL; 1576 countptr = this_cpu_ptr(dpaa_bp->percpu_count); 1577 res = dpaa_eth_refill_bpool(dpaa_bp, countptr); 1578 if (res) 1579 return res; 1580 1581 return 0; 1582 } 1583 1584 /* Cleanup function for outgoing frame descriptors that were built on Tx path, 1585 * either contiguous frames or scatter/gather ones. 1586 * Skb freeing is not handled here. 1587 * 1588 * This function may be called on error paths in the Tx function, so guard 1589 * against cases when not all fd relevant fields were filled in. To avoid 1590 * reading the invalid transmission timestamp for the error paths set ts to 1591 * false. 1592 * 1593 * Return the skb backpointer, since for S/G frames the buffer containing it 1594 * gets freed here. 1595 */ 1596 static struct sk_buff *dpaa_cleanup_tx_fd(const struct dpaa_priv *priv, 1597 const struct qm_fd *fd, bool ts) 1598 { 1599 const enum dma_data_direction dma_dir = DMA_TO_DEVICE; 1600 struct device *dev = priv->net_dev->dev.parent; 1601 struct skb_shared_hwtstamps shhwtstamps; 1602 dma_addr_t addr = qm_fd_addr(fd); 1603 void *vaddr = phys_to_virt(addr); 1604 const struct qm_sg_entry *sgt; 1605 struct sk_buff *skb; 1606 u64 ns; 1607 int i; 1608 1609 if (unlikely(qm_fd_get_format(fd) == qm_fd_sg)) { 1610 dma_unmap_page(priv->tx_dma_dev, addr, 1611 qm_fd_get_offset(fd) + DPAA_SGT_SIZE, 1612 dma_dir); 1613 1614 /* The sgt buffer has been allocated with netdev_alloc_frag(), 1615 * it's from lowmem. 1616 */ 1617 sgt = vaddr + qm_fd_get_offset(fd); 1618 1619 /* sgt[0] is from lowmem, was dma_map_single()-ed */ 1620 dma_unmap_single(priv->tx_dma_dev, qm_sg_addr(&sgt[0]), 1621 qm_sg_entry_get_len(&sgt[0]), dma_dir); 1622 1623 /* remaining pages were mapped with skb_frag_dma_map() */ 1624 for (i = 1; (i < DPAA_SGT_MAX_ENTRIES) && 1625 !qm_sg_entry_is_final(&sgt[i - 1]); i++) { 1626 WARN_ON(qm_sg_entry_is_ext(&sgt[i])); 1627 1628 dma_unmap_page(priv->tx_dma_dev, qm_sg_addr(&sgt[i]), 1629 qm_sg_entry_get_len(&sgt[i]), dma_dir); 1630 } 1631 } else { 1632 dma_unmap_single(priv->tx_dma_dev, addr, 1633 priv->tx_headroom + qm_fd_get_length(fd), 1634 dma_dir); 1635 } 1636 1637 skb = *(struct sk_buff **)vaddr; 1638 1639 /* DMA unmapping is required before accessing the HW provided info */ 1640 if (ts && priv->tx_tstamp && 1641 skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) { 1642 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 1643 1644 if (!fman_port_get_tstamp(priv->mac_dev->port[TX], vaddr, 1645 &ns)) { 1646 shhwtstamps.hwtstamp = ns_to_ktime(ns); 1647 skb_tstamp_tx(skb, &shhwtstamps); 1648 } else { 1649 dev_warn(dev, "fman_port_get_tstamp failed!\n"); 1650 } 1651 } 1652 1653 if (qm_fd_get_format(fd) == qm_fd_sg) 1654 /* Free the page that we allocated on Tx for the SGT */ 1655 free_pages((unsigned long)vaddr, 0); 1656 1657 return skb; 1658 } 1659 1660 static u8 rx_csum_offload(const struct dpaa_priv *priv, const struct qm_fd *fd) 1661 { 1662 /* The parser has run and performed L4 checksum validation. 1663 * We know there were no parser errors (and implicitly no 1664 * L4 csum error), otherwise we wouldn't be here. 1665 */ 1666 if ((priv->net_dev->features & NETIF_F_RXCSUM) && 1667 (be32_to_cpu(fd->status) & FM_FD_STAT_L4CV)) 1668 return CHECKSUM_UNNECESSARY; 1669 1670 /* We're here because either the parser didn't run or the L4 checksum 1671 * was not verified. This may include the case of a UDP frame with 1672 * checksum zero or an L4 proto other than TCP/UDP 1673 */ 1674 return CHECKSUM_NONE; 1675 } 1676 1677 /* Build a linear skb around the received buffer. 1678 * We are guaranteed there is enough room at the end of the data buffer to 1679 * accommodate the shared info area of the skb. 1680 */ 1681 static struct sk_buff *contig_fd_to_skb(const struct dpaa_priv *priv, 1682 const struct qm_fd *fd) 1683 { 1684 ssize_t fd_off = qm_fd_get_offset(fd); 1685 dma_addr_t addr = qm_fd_addr(fd); 1686 struct dpaa_bp *dpaa_bp; 1687 struct sk_buff *skb; 1688 void *vaddr; 1689 1690 vaddr = phys_to_virt(addr); 1691 WARN_ON(!IS_ALIGNED((unsigned long)vaddr, SMP_CACHE_BYTES)); 1692 1693 dpaa_bp = dpaa_bpid2pool(fd->bpid); 1694 if (!dpaa_bp) 1695 goto free_buffer; 1696 1697 skb = build_skb(vaddr, dpaa_bp->size + 1698 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))); 1699 if (WARN_ONCE(!skb, "Build skb failure on Rx\n")) 1700 goto free_buffer; 1701 WARN_ON(fd_off != priv->rx_headroom); 1702 skb_reserve(skb, fd_off); 1703 skb_put(skb, qm_fd_get_length(fd)); 1704 1705 skb->ip_summed = rx_csum_offload(priv, fd); 1706 1707 return skb; 1708 1709 free_buffer: 1710 free_pages((unsigned long)vaddr, 0); 1711 return NULL; 1712 } 1713 1714 /* Build an skb with the data of the first S/G entry in the linear portion and 1715 * the rest of the frame as skb fragments. 1716 * 1717 * The page fragment holding the S/G Table is recycled here. 1718 */ 1719 static struct sk_buff *sg_fd_to_skb(const struct dpaa_priv *priv, 1720 const struct qm_fd *fd) 1721 { 1722 ssize_t fd_off = qm_fd_get_offset(fd); 1723 dma_addr_t addr = qm_fd_addr(fd); 1724 const struct qm_sg_entry *sgt; 1725 struct page *page, *head_page; 1726 struct dpaa_bp *dpaa_bp; 1727 void *vaddr, *sg_vaddr; 1728 int frag_off, frag_len; 1729 struct sk_buff *skb; 1730 dma_addr_t sg_addr; 1731 int page_offset; 1732 unsigned int sz; 1733 int *count_ptr; 1734 int i, j; 1735 1736 vaddr = phys_to_virt(addr); 1737 WARN_ON(!IS_ALIGNED((unsigned long)vaddr, SMP_CACHE_BYTES)); 1738 1739 /* Iterate through the SGT entries and add data buffers to the skb */ 1740 sgt = vaddr + fd_off; 1741 skb = NULL; 1742 for (i = 0; i < DPAA_SGT_MAX_ENTRIES; i++) { 1743 /* Extension bit is not supported */ 1744 WARN_ON(qm_sg_entry_is_ext(&sgt[i])); 1745 1746 sg_addr = qm_sg_addr(&sgt[i]); 1747 sg_vaddr = phys_to_virt(sg_addr); 1748 WARN_ON(!IS_ALIGNED((unsigned long)sg_vaddr, 1749 SMP_CACHE_BYTES)); 1750 1751 dma_unmap_page(priv->rx_dma_dev, sg_addr, 1752 DPAA_BP_RAW_SIZE, DMA_FROM_DEVICE); 1753 1754 /* We may use multiple Rx pools */ 1755 dpaa_bp = dpaa_bpid2pool(sgt[i].bpid); 1756 if (!dpaa_bp) 1757 goto free_buffers; 1758 1759 if (!skb) { 1760 sz = dpaa_bp->size + 1761 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 1762 skb = build_skb(sg_vaddr, sz); 1763 if (WARN_ON(!skb)) 1764 goto free_buffers; 1765 1766 skb->ip_summed = rx_csum_offload(priv, fd); 1767 1768 /* Make sure forwarded skbs will have enough space 1769 * on Tx, if extra headers are added. 1770 */ 1771 WARN_ON(fd_off != priv->rx_headroom); 1772 skb_reserve(skb, fd_off); 1773 skb_put(skb, qm_sg_entry_get_len(&sgt[i])); 1774 } else { 1775 /* Not the first S/G entry; all data from buffer will 1776 * be added in an skb fragment; fragment index is offset 1777 * by one since first S/G entry was incorporated in the 1778 * linear part of the skb. 1779 * 1780 * Caution: 'page' may be a tail page. 1781 */ 1782 page = virt_to_page(sg_vaddr); 1783 head_page = virt_to_head_page(sg_vaddr); 1784 1785 /* Compute offset in (possibly tail) page */ 1786 page_offset = ((unsigned long)sg_vaddr & 1787 (PAGE_SIZE - 1)) + 1788 (page_address(page) - page_address(head_page)); 1789 /* page_offset only refers to the beginning of sgt[i]; 1790 * but the buffer itself may have an internal offset. 1791 */ 1792 frag_off = qm_sg_entry_get_off(&sgt[i]) + page_offset; 1793 frag_len = qm_sg_entry_get_len(&sgt[i]); 1794 /* skb_add_rx_frag() does no checking on the page; if 1795 * we pass it a tail page, we'll end up with 1796 * bad page accounting and eventually with segafults. 1797 */ 1798 skb_add_rx_frag(skb, i - 1, head_page, frag_off, 1799 frag_len, dpaa_bp->size); 1800 } 1801 1802 /* Update the pool count for the current {cpu x bpool} */ 1803 count_ptr = this_cpu_ptr(dpaa_bp->percpu_count); 1804 (*count_ptr)--; 1805 1806 if (qm_sg_entry_is_final(&sgt[i])) 1807 break; 1808 } 1809 WARN_ONCE(i == DPAA_SGT_MAX_ENTRIES, "No final bit on SGT\n"); 1810 1811 /* free the SG table buffer */ 1812 free_pages((unsigned long)vaddr, 0); 1813 1814 return skb; 1815 1816 free_buffers: 1817 /* free all the SG entries */ 1818 for (j = 0; j < DPAA_SGT_MAX_ENTRIES ; j++) { 1819 sg_addr = qm_sg_addr(&sgt[j]); 1820 sg_vaddr = phys_to_virt(sg_addr); 1821 /* all pages 0..i were unmaped */ 1822 if (j > i) 1823 dma_unmap_page(priv->rx_dma_dev, qm_sg_addr(&sgt[j]), 1824 DPAA_BP_RAW_SIZE, DMA_FROM_DEVICE); 1825 free_pages((unsigned long)sg_vaddr, 0); 1826 /* counters 0..i-1 were decremented */ 1827 if (j >= i) { 1828 dpaa_bp = dpaa_bpid2pool(sgt[j].bpid); 1829 if (dpaa_bp) { 1830 count_ptr = this_cpu_ptr(dpaa_bp->percpu_count); 1831 (*count_ptr)--; 1832 } 1833 } 1834 1835 if (qm_sg_entry_is_final(&sgt[j])) 1836 break; 1837 } 1838 /* free the SGT fragment */ 1839 free_pages((unsigned long)vaddr, 0); 1840 1841 return NULL; 1842 } 1843 1844 static int skb_to_contig_fd(struct dpaa_priv *priv, 1845 struct sk_buff *skb, struct qm_fd *fd, 1846 int *offset) 1847 { 1848 struct net_device *net_dev = priv->net_dev; 1849 enum dma_data_direction dma_dir; 1850 unsigned char *buff_start; 1851 struct sk_buff **skbh; 1852 dma_addr_t addr; 1853 int err; 1854 1855 /* We are guaranteed to have at least tx_headroom bytes 1856 * available, so just use that for offset. 1857 */ 1858 fd->bpid = FSL_DPAA_BPID_INV; 1859 buff_start = skb->data - priv->tx_headroom; 1860 dma_dir = DMA_TO_DEVICE; 1861 1862 skbh = (struct sk_buff **)buff_start; 1863 *skbh = skb; 1864 1865 /* Enable L3/L4 hardware checksum computation. 1866 * 1867 * We must do this before dma_map_single(DMA_TO_DEVICE), because we may 1868 * need to write into the skb. 1869 */ 1870 err = dpaa_enable_tx_csum(priv, skb, fd, 1871 buff_start + DPAA_TX_PRIV_DATA_SIZE); 1872 if (unlikely(err < 0)) { 1873 if (net_ratelimit()) 1874 netif_err(priv, tx_err, net_dev, "HW csum error: %d\n", 1875 err); 1876 return err; 1877 } 1878 1879 /* Fill in the rest of the FD fields */ 1880 qm_fd_set_contig(fd, priv->tx_headroom, skb->len); 1881 fd->cmd |= cpu_to_be32(FM_FD_CMD_FCO); 1882 1883 /* Map the entire buffer size that may be seen by FMan, but no more */ 1884 addr = dma_map_single(priv->tx_dma_dev, buff_start, 1885 priv->tx_headroom + skb->len, dma_dir); 1886 if (unlikely(dma_mapping_error(priv->tx_dma_dev, addr))) { 1887 if (net_ratelimit()) 1888 netif_err(priv, tx_err, net_dev, "dma_map_single() failed\n"); 1889 return -EINVAL; 1890 } 1891 qm_fd_addr_set64(fd, addr); 1892 1893 return 0; 1894 } 1895 1896 static int skb_to_sg_fd(struct dpaa_priv *priv, 1897 struct sk_buff *skb, struct qm_fd *fd) 1898 { 1899 const enum dma_data_direction dma_dir = DMA_TO_DEVICE; 1900 const int nr_frags = skb_shinfo(skb)->nr_frags; 1901 struct net_device *net_dev = priv->net_dev; 1902 struct qm_sg_entry *sgt; 1903 struct sk_buff **skbh; 1904 void *buff_start; 1905 skb_frag_t *frag; 1906 dma_addr_t addr; 1907 size_t frag_len; 1908 struct page *p; 1909 int i, j, err; 1910 1911 /* get a page to store the SGTable */ 1912 p = dev_alloc_pages(0); 1913 if (unlikely(!p)) { 1914 netdev_err(net_dev, "dev_alloc_pages() failed\n"); 1915 return -ENOMEM; 1916 } 1917 buff_start = page_address(p); 1918 1919 /* Enable L3/L4 hardware checksum computation. 1920 * 1921 * We must do this before dma_map_single(DMA_TO_DEVICE), because we may 1922 * need to write into the skb. 1923 */ 1924 err = dpaa_enable_tx_csum(priv, skb, fd, 1925 buff_start + DPAA_TX_PRIV_DATA_SIZE); 1926 if (unlikely(err < 0)) { 1927 if (net_ratelimit()) 1928 netif_err(priv, tx_err, net_dev, "HW csum error: %d\n", 1929 err); 1930 goto csum_failed; 1931 } 1932 1933 /* SGT[0] is used by the linear part */ 1934 sgt = (struct qm_sg_entry *)(buff_start + priv->tx_headroom); 1935 frag_len = skb_headlen(skb); 1936 qm_sg_entry_set_len(&sgt[0], frag_len); 1937 sgt[0].bpid = FSL_DPAA_BPID_INV; 1938 sgt[0].offset = 0; 1939 addr = dma_map_single(priv->tx_dma_dev, skb->data, 1940 skb_headlen(skb), dma_dir); 1941 if (unlikely(dma_mapping_error(priv->tx_dma_dev, addr))) { 1942 netdev_err(priv->net_dev, "DMA mapping failed\n"); 1943 err = -EINVAL; 1944 goto sg0_map_failed; 1945 } 1946 qm_sg_entry_set64(&sgt[0], addr); 1947 1948 /* populate the rest of SGT entries */ 1949 for (i = 0; i < nr_frags; i++) { 1950 frag = &skb_shinfo(skb)->frags[i]; 1951 frag_len = skb_frag_size(frag); 1952 WARN_ON(!skb_frag_page(frag)); 1953 addr = skb_frag_dma_map(priv->tx_dma_dev, frag, 0, 1954 frag_len, dma_dir); 1955 if (unlikely(dma_mapping_error(priv->tx_dma_dev, addr))) { 1956 netdev_err(priv->net_dev, "DMA mapping failed\n"); 1957 err = -EINVAL; 1958 goto sg_map_failed; 1959 } 1960 1961 qm_sg_entry_set_len(&sgt[i + 1], frag_len); 1962 sgt[i + 1].bpid = FSL_DPAA_BPID_INV; 1963 sgt[i + 1].offset = 0; 1964 1965 /* keep the offset in the address */ 1966 qm_sg_entry_set64(&sgt[i + 1], addr); 1967 } 1968 1969 /* Set the final bit in the last used entry of the SGT */ 1970 qm_sg_entry_set_f(&sgt[nr_frags], frag_len); 1971 1972 /* set fd offset to priv->tx_headroom */ 1973 qm_fd_set_sg(fd, priv->tx_headroom, skb->len); 1974 1975 /* DMA map the SGT page */ 1976 skbh = (struct sk_buff **)buff_start; 1977 *skbh = skb; 1978 1979 addr = dma_map_page(priv->tx_dma_dev, p, 0, 1980 priv->tx_headroom + DPAA_SGT_SIZE, dma_dir); 1981 if (unlikely(dma_mapping_error(priv->tx_dma_dev, addr))) { 1982 netdev_err(priv->net_dev, "DMA mapping failed\n"); 1983 err = -EINVAL; 1984 goto sgt_map_failed; 1985 } 1986 1987 fd->bpid = FSL_DPAA_BPID_INV; 1988 fd->cmd |= cpu_to_be32(FM_FD_CMD_FCO); 1989 qm_fd_addr_set64(fd, addr); 1990 1991 return 0; 1992 1993 sgt_map_failed: 1994 sg_map_failed: 1995 for (j = 0; j < i; j++) 1996 dma_unmap_page(priv->tx_dma_dev, qm_sg_addr(&sgt[j]), 1997 qm_sg_entry_get_len(&sgt[j]), dma_dir); 1998 sg0_map_failed: 1999 csum_failed: 2000 free_pages((unsigned long)buff_start, 0); 2001 2002 return err; 2003 } 2004 2005 static inline int dpaa_xmit(struct dpaa_priv *priv, 2006 struct rtnl_link_stats64 *percpu_stats, 2007 int queue, 2008 struct qm_fd *fd) 2009 { 2010 struct qman_fq *egress_fq; 2011 int err, i; 2012 2013 egress_fq = priv->egress_fqs[queue]; 2014 if (fd->bpid == FSL_DPAA_BPID_INV) 2015 fd->cmd |= cpu_to_be32(qman_fq_fqid(priv->conf_fqs[queue])); 2016 2017 /* Trace this Tx fd */ 2018 trace_dpaa_tx_fd(priv->net_dev, egress_fq, fd); 2019 2020 for (i = 0; i < DPAA_ENQUEUE_RETRIES; i++) { 2021 err = qman_enqueue(egress_fq, fd); 2022 if (err != -EBUSY) 2023 break; 2024 } 2025 2026 if (unlikely(err < 0)) { 2027 percpu_stats->tx_fifo_errors++; 2028 return err; 2029 } 2030 2031 percpu_stats->tx_packets++; 2032 percpu_stats->tx_bytes += qm_fd_get_length(fd); 2033 2034 return 0; 2035 } 2036 2037 static netdev_tx_t 2038 dpaa_start_xmit(struct sk_buff *skb, struct net_device *net_dev) 2039 { 2040 const int queue_mapping = skb_get_queue_mapping(skb); 2041 bool nonlinear = skb_is_nonlinear(skb); 2042 struct rtnl_link_stats64 *percpu_stats; 2043 struct dpaa_percpu_priv *percpu_priv; 2044 struct netdev_queue *txq; 2045 struct dpaa_priv *priv; 2046 struct qm_fd fd; 2047 int offset = 0; 2048 int err = 0; 2049 2050 priv = netdev_priv(net_dev); 2051 percpu_priv = this_cpu_ptr(priv->percpu_priv); 2052 percpu_stats = &percpu_priv->stats; 2053 2054 qm_fd_clear_fd(&fd); 2055 2056 if (!nonlinear) { 2057 /* We're going to store the skb backpointer at the beginning 2058 * of the data buffer, so we need a privately owned skb 2059 * 2060 * We've made sure skb is not shared in dev->priv_flags, 2061 * we need to verify the skb head is not cloned 2062 */ 2063 if (skb_cow_head(skb, priv->tx_headroom)) 2064 goto enomem; 2065 2066 WARN_ON(skb_is_nonlinear(skb)); 2067 } 2068 2069 /* MAX_SKB_FRAGS is equal or larger than our dpaa_SGT_MAX_ENTRIES; 2070 * make sure we don't feed FMan with more fragments than it supports. 2071 */ 2072 if (unlikely(nonlinear && 2073 (skb_shinfo(skb)->nr_frags >= DPAA_SGT_MAX_ENTRIES))) { 2074 /* If the egress skb contains more fragments than we support 2075 * we have no choice but to linearize it ourselves. 2076 */ 2077 if (__skb_linearize(skb)) 2078 goto enomem; 2079 2080 nonlinear = skb_is_nonlinear(skb); 2081 } 2082 2083 if (nonlinear) { 2084 /* Just create a S/G fd based on the skb */ 2085 err = skb_to_sg_fd(priv, skb, &fd); 2086 percpu_priv->tx_frag_skbuffs++; 2087 } else { 2088 /* Create a contig FD from this skb */ 2089 err = skb_to_contig_fd(priv, skb, &fd, &offset); 2090 } 2091 if (unlikely(err < 0)) 2092 goto skb_to_fd_failed; 2093 2094 txq = netdev_get_tx_queue(net_dev, queue_mapping); 2095 2096 /* LLTX requires to do our own update of trans_start */ 2097 txq->trans_start = jiffies; 2098 2099 if (priv->tx_tstamp && skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) { 2100 fd.cmd |= cpu_to_be32(FM_FD_CMD_UPD); 2101 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 2102 } 2103 2104 if (likely(dpaa_xmit(priv, percpu_stats, queue_mapping, &fd) == 0)) 2105 return NETDEV_TX_OK; 2106 2107 dpaa_cleanup_tx_fd(priv, &fd, false); 2108 skb_to_fd_failed: 2109 enomem: 2110 percpu_stats->tx_errors++; 2111 dev_kfree_skb(skb); 2112 return NETDEV_TX_OK; 2113 } 2114 2115 static void dpaa_rx_error(struct net_device *net_dev, 2116 const struct dpaa_priv *priv, 2117 struct dpaa_percpu_priv *percpu_priv, 2118 const struct qm_fd *fd, 2119 u32 fqid) 2120 { 2121 if (net_ratelimit()) 2122 netif_err(priv, hw, net_dev, "Err FD status = 0x%08x\n", 2123 be32_to_cpu(fd->status) & FM_FD_STAT_RX_ERRORS); 2124 2125 percpu_priv->stats.rx_errors++; 2126 2127 if (be32_to_cpu(fd->status) & FM_FD_ERR_DMA) 2128 percpu_priv->rx_errors.dme++; 2129 if (be32_to_cpu(fd->status) & FM_FD_ERR_PHYSICAL) 2130 percpu_priv->rx_errors.fpe++; 2131 if (be32_to_cpu(fd->status) & FM_FD_ERR_SIZE) 2132 percpu_priv->rx_errors.fse++; 2133 if (be32_to_cpu(fd->status) & FM_FD_ERR_PRS_HDR_ERR) 2134 percpu_priv->rx_errors.phe++; 2135 2136 dpaa_fd_release(net_dev, fd); 2137 } 2138 2139 static void dpaa_tx_error(struct net_device *net_dev, 2140 const struct dpaa_priv *priv, 2141 struct dpaa_percpu_priv *percpu_priv, 2142 const struct qm_fd *fd, 2143 u32 fqid) 2144 { 2145 struct sk_buff *skb; 2146 2147 if (net_ratelimit()) 2148 netif_warn(priv, hw, net_dev, "FD status = 0x%08x\n", 2149 be32_to_cpu(fd->status) & FM_FD_STAT_TX_ERRORS); 2150 2151 percpu_priv->stats.tx_errors++; 2152 2153 skb = dpaa_cleanup_tx_fd(priv, fd, false); 2154 dev_kfree_skb(skb); 2155 } 2156 2157 static int dpaa_eth_poll(struct napi_struct *napi, int budget) 2158 { 2159 struct dpaa_napi_portal *np = 2160 container_of(napi, struct dpaa_napi_portal, napi); 2161 2162 int cleaned = qman_p_poll_dqrr(np->p, budget); 2163 2164 if (cleaned < budget) { 2165 napi_complete_done(napi, cleaned); 2166 qman_p_irqsource_add(np->p, QM_PIRQ_DQRI); 2167 } else if (np->down) { 2168 qman_p_irqsource_add(np->p, QM_PIRQ_DQRI); 2169 } 2170 2171 return cleaned; 2172 } 2173 2174 static void dpaa_tx_conf(struct net_device *net_dev, 2175 const struct dpaa_priv *priv, 2176 struct dpaa_percpu_priv *percpu_priv, 2177 const struct qm_fd *fd, 2178 u32 fqid) 2179 { 2180 struct sk_buff *skb; 2181 2182 if (unlikely(be32_to_cpu(fd->status) & FM_FD_STAT_TX_ERRORS)) { 2183 if (net_ratelimit()) 2184 netif_warn(priv, hw, net_dev, "FD status = 0x%08x\n", 2185 be32_to_cpu(fd->status) & 2186 FM_FD_STAT_TX_ERRORS); 2187 2188 percpu_priv->stats.tx_errors++; 2189 } 2190 2191 percpu_priv->tx_confirm++; 2192 2193 skb = dpaa_cleanup_tx_fd(priv, fd, true); 2194 2195 consume_skb(skb); 2196 } 2197 2198 static inline int dpaa_eth_napi_schedule(struct dpaa_percpu_priv *percpu_priv, 2199 struct qman_portal *portal) 2200 { 2201 if (unlikely(in_irq() || !in_serving_softirq())) { 2202 /* Disable QMan IRQ and invoke NAPI */ 2203 qman_p_irqsource_remove(portal, QM_PIRQ_DQRI); 2204 2205 percpu_priv->np.p = portal; 2206 napi_schedule(&percpu_priv->np.napi); 2207 percpu_priv->in_interrupt++; 2208 return 1; 2209 } 2210 return 0; 2211 } 2212 2213 static enum qman_cb_dqrr_result rx_error_dqrr(struct qman_portal *portal, 2214 struct qman_fq *fq, 2215 const struct qm_dqrr_entry *dq) 2216 { 2217 struct dpaa_fq *dpaa_fq = container_of(fq, struct dpaa_fq, fq_base); 2218 struct dpaa_percpu_priv *percpu_priv; 2219 struct net_device *net_dev; 2220 struct dpaa_bp *dpaa_bp; 2221 struct dpaa_priv *priv; 2222 2223 net_dev = dpaa_fq->net_dev; 2224 priv = netdev_priv(net_dev); 2225 dpaa_bp = dpaa_bpid2pool(dq->fd.bpid); 2226 if (!dpaa_bp) 2227 return qman_cb_dqrr_consume; 2228 2229 percpu_priv = this_cpu_ptr(priv->percpu_priv); 2230 2231 if (dpaa_eth_napi_schedule(percpu_priv, portal)) 2232 return qman_cb_dqrr_stop; 2233 2234 dpaa_eth_refill_bpools(priv); 2235 dpaa_rx_error(net_dev, priv, percpu_priv, &dq->fd, fq->fqid); 2236 2237 return qman_cb_dqrr_consume; 2238 } 2239 2240 static enum qman_cb_dqrr_result rx_default_dqrr(struct qman_portal *portal, 2241 struct qman_fq *fq, 2242 const struct qm_dqrr_entry *dq) 2243 { 2244 struct skb_shared_hwtstamps *shhwtstamps; 2245 struct rtnl_link_stats64 *percpu_stats; 2246 struct dpaa_percpu_priv *percpu_priv; 2247 const struct qm_fd *fd = &dq->fd; 2248 dma_addr_t addr = qm_fd_addr(fd); 2249 enum qm_fd_format fd_format; 2250 struct net_device *net_dev; 2251 u32 fd_status, hash_offset; 2252 struct dpaa_bp *dpaa_bp; 2253 struct dpaa_priv *priv; 2254 unsigned int skb_len; 2255 struct sk_buff *skb; 2256 int *count_ptr; 2257 void *vaddr; 2258 u64 ns; 2259 2260 fd_status = be32_to_cpu(fd->status); 2261 fd_format = qm_fd_get_format(fd); 2262 net_dev = ((struct dpaa_fq *)fq)->net_dev; 2263 priv = netdev_priv(net_dev); 2264 dpaa_bp = dpaa_bpid2pool(dq->fd.bpid); 2265 if (!dpaa_bp) 2266 return qman_cb_dqrr_consume; 2267 2268 /* Trace the Rx fd */ 2269 trace_dpaa_rx_fd(net_dev, fq, &dq->fd); 2270 2271 percpu_priv = this_cpu_ptr(priv->percpu_priv); 2272 percpu_stats = &percpu_priv->stats; 2273 2274 if (unlikely(dpaa_eth_napi_schedule(percpu_priv, portal))) 2275 return qman_cb_dqrr_stop; 2276 2277 /* Make sure we didn't run out of buffers */ 2278 if (unlikely(dpaa_eth_refill_bpools(priv))) { 2279 /* Unable to refill the buffer pool due to insufficient 2280 * system memory. Just release the frame back into the pool, 2281 * otherwise we'll soon end up with an empty buffer pool. 2282 */ 2283 dpaa_fd_release(net_dev, &dq->fd); 2284 return qman_cb_dqrr_consume; 2285 } 2286 2287 if (unlikely(fd_status & FM_FD_STAT_RX_ERRORS) != 0) { 2288 if (net_ratelimit()) 2289 netif_warn(priv, hw, net_dev, "FD status = 0x%08x\n", 2290 fd_status & FM_FD_STAT_RX_ERRORS); 2291 2292 percpu_stats->rx_errors++; 2293 dpaa_fd_release(net_dev, fd); 2294 return qman_cb_dqrr_consume; 2295 } 2296 2297 dma_unmap_page(dpaa_bp->priv->rx_dma_dev, addr, DPAA_BP_RAW_SIZE, 2298 DMA_FROM_DEVICE); 2299 2300 /* prefetch the first 64 bytes of the frame or the SGT start */ 2301 vaddr = phys_to_virt(addr); 2302 prefetch(vaddr + qm_fd_get_offset(fd)); 2303 2304 /* The only FD types that we may receive are contig and S/G */ 2305 WARN_ON((fd_format != qm_fd_contig) && (fd_format != qm_fd_sg)); 2306 2307 /* Account for either the contig buffer or the SGT buffer (depending on 2308 * which case we were in) having been removed from the pool. 2309 */ 2310 count_ptr = this_cpu_ptr(dpaa_bp->percpu_count); 2311 (*count_ptr)--; 2312 2313 if (likely(fd_format == qm_fd_contig)) 2314 skb = contig_fd_to_skb(priv, fd); 2315 else 2316 skb = sg_fd_to_skb(priv, fd); 2317 if (!skb) 2318 return qman_cb_dqrr_consume; 2319 2320 if (priv->rx_tstamp) { 2321 shhwtstamps = skb_hwtstamps(skb); 2322 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 2323 2324 if (!fman_port_get_tstamp(priv->mac_dev->port[RX], vaddr, &ns)) 2325 shhwtstamps->hwtstamp = ns_to_ktime(ns); 2326 else 2327 dev_warn(net_dev->dev.parent, "fman_port_get_tstamp failed!\n"); 2328 } 2329 2330 skb->protocol = eth_type_trans(skb, net_dev); 2331 2332 if (net_dev->features & NETIF_F_RXHASH && priv->keygen_in_use && 2333 !fman_port_get_hash_result_offset(priv->mac_dev->port[RX], 2334 &hash_offset)) { 2335 enum pkt_hash_types type; 2336 2337 /* if L4 exists, it was used in the hash generation */ 2338 type = be32_to_cpu(fd->status) & FM_FD_STAT_L4CV ? 2339 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3; 2340 skb_set_hash(skb, be32_to_cpu(*(u32 *)(vaddr + hash_offset)), 2341 type); 2342 } 2343 2344 skb_len = skb->len; 2345 2346 if (unlikely(netif_receive_skb(skb) == NET_RX_DROP)) { 2347 percpu_stats->rx_dropped++; 2348 return qman_cb_dqrr_consume; 2349 } 2350 2351 percpu_stats->rx_packets++; 2352 percpu_stats->rx_bytes += skb_len; 2353 2354 return qman_cb_dqrr_consume; 2355 } 2356 2357 static enum qman_cb_dqrr_result conf_error_dqrr(struct qman_portal *portal, 2358 struct qman_fq *fq, 2359 const struct qm_dqrr_entry *dq) 2360 { 2361 struct dpaa_percpu_priv *percpu_priv; 2362 struct net_device *net_dev; 2363 struct dpaa_priv *priv; 2364 2365 net_dev = ((struct dpaa_fq *)fq)->net_dev; 2366 priv = netdev_priv(net_dev); 2367 2368 percpu_priv = this_cpu_ptr(priv->percpu_priv); 2369 2370 if (dpaa_eth_napi_schedule(percpu_priv, portal)) 2371 return qman_cb_dqrr_stop; 2372 2373 dpaa_tx_error(net_dev, priv, percpu_priv, &dq->fd, fq->fqid); 2374 2375 return qman_cb_dqrr_consume; 2376 } 2377 2378 static enum qman_cb_dqrr_result conf_dflt_dqrr(struct qman_portal *portal, 2379 struct qman_fq *fq, 2380 const struct qm_dqrr_entry *dq) 2381 { 2382 struct dpaa_percpu_priv *percpu_priv; 2383 struct net_device *net_dev; 2384 struct dpaa_priv *priv; 2385 2386 net_dev = ((struct dpaa_fq *)fq)->net_dev; 2387 priv = netdev_priv(net_dev); 2388 2389 /* Trace the fd */ 2390 trace_dpaa_tx_conf_fd(net_dev, fq, &dq->fd); 2391 2392 percpu_priv = this_cpu_ptr(priv->percpu_priv); 2393 2394 if (dpaa_eth_napi_schedule(percpu_priv, portal)) 2395 return qman_cb_dqrr_stop; 2396 2397 dpaa_tx_conf(net_dev, priv, percpu_priv, &dq->fd, fq->fqid); 2398 2399 return qman_cb_dqrr_consume; 2400 } 2401 2402 static void egress_ern(struct qman_portal *portal, 2403 struct qman_fq *fq, 2404 const union qm_mr_entry *msg) 2405 { 2406 const struct qm_fd *fd = &msg->ern.fd; 2407 struct dpaa_percpu_priv *percpu_priv; 2408 const struct dpaa_priv *priv; 2409 struct net_device *net_dev; 2410 struct sk_buff *skb; 2411 2412 net_dev = ((struct dpaa_fq *)fq)->net_dev; 2413 priv = netdev_priv(net_dev); 2414 percpu_priv = this_cpu_ptr(priv->percpu_priv); 2415 2416 percpu_priv->stats.tx_dropped++; 2417 percpu_priv->stats.tx_fifo_errors++; 2418 count_ern(percpu_priv, msg); 2419 2420 skb = dpaa_cleanup_tx_fd(priv, fd, false); 2421 dev_kfree_skb_any(skb); 2422 } 2423 2424 static const struct dpaa_fq_cbs dpaa_fq_cbs = { 2425 .rx_defq = { .cb = { .dqrr = rx_default_dqrr } }, 2426 .tx_defq = { .cb = { .dqrr = conf_dflt_dqrr } }, 2427 .rx_errq = { .cb = { .dqrr = rx_error_dqrr } }, 2428 .tx_errq = { .cb = { .dqrr = conf_error_dqrr } }, 2429 .egress_ern = { .cb = { .ern = egress_ern } } 2430 }; 2431 2432 static void dpaa_eth_napi_enable(struct dpaa_priv *priv) 2433 { 2434 struct dpaa_percpu_priv *percpu_priv; 2435 int i; 2436 2437 for_each_online_cpu(i) { 2438 percpu_priv = per_cpu_ptr(priv->percpu_priv, i); 2439 2440 percpu_priv->np.down = 0; 2441 napi_enable(&percpu_priv->np.napi); 2442 } 2443 } 2444 2445 static void dpaa_eth_napi_disable(struct dpaa_priv *priv) 2446 { 2447 struct dpaa_percpu_priv *percpu_priv; 2448 int i; 2449 2450 for_each_online_cpu(i) { 2451 percpu_priv = per_cpu_ptr(priv->percpu_priv, i); 2452 2453 percpu_priv->np.down = 1; 2454 napi_disable(&percpu_priv->np.napi); 2455 } 2456 } 2457 2458 static void dpaa_adjust_link(struct net_device *net_dev) 2459 { 2460 struct mac_device *mac_dev; 2461 struct dpaa_priv *priv; 2462 2463 priv = netdev_priv(net_dev); 2464 mac_dev = priv->mac_dev; 2465 mac_dev->adjust_link(mac_dev); 2466 } 2467 2468 /* The Aquantia PHYs are capable of performing rate adaptation */ 2469 #define PHY_VEND_AQUANTIA 0x03a1b400 2470 2471 static int dpaa_phy_init(struct net_device *net_dev) 2472 { 2473 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 2474 struct mac_device *mac_dev; 2475 struct phy_device *phy_dev; 2476 struct dpaa_priv *priv; 2477 2478 priv = netdev_priv(net_dev); 2479 mac_dev = priv->mac_dev; 2480 2481 phy_dev = of_phy_connect(net_dev, mac_dev->phy_node, 2482 &dpaa_adjust_link, 0, 2483 mac_dev->phy_if); 2484 if (!phy_dev) { 2485 netif_err(priv, ifup, net_dev, "init_phy() failed\n"); 2486 return -ENODEV; 2487 } 2488 2489 /* Unless the PHY is capable of rate adaptation */ 2490 if (mac_dev->phy_if != PHY_INTERFACE_MODE_XGMII || 2491 ((phy_dev->drv->phy_id & GENMASK(31, 10)) != PHY_VEND_AQUANTIA)) { 2492 /* remove any features not supported by the controller */ 2493 ethtool_convert_legacy_u32_to_link_mode(mask, 2494 mac_dev->if_support); 2495 linkmode_and(phy_dev->supported, phy_dev->supported, mask); 2496 } 2497 2498 phy_support_asym_pause(phy_dev); 2499 2500 mac_dev->phy_dev = phy_dev; 2501 net_dev->phydev = phy_dev; 2502 2503 return 0; 2504 } 2505 2506 static int dpaa_open(struct net_device *net_dev) 2507 { 2508 struct mac_device *mac_dev; 2509 struct dpaa_priv *priv; 2510 int err, i; 2511 2512 priv = netdev_priv(net_dev); 2513 mac_dev = priv->mac_dev; 2514 dpaa_eth_napi_enable(priv); 2515 2516 err = dpaa_phy_init(net_dev); 2517 if (err) 2518 goto phy_init_failed; 2519 2520 for (i = 0; i < ARRAY_SIZE(mac_dev->port); i++) { 2521 err = fman_port_enable(mac_dev->port[i]); 2522 if (err) 2523 goto mac_start_failed; 2524 } 2525 2526 err = priv->mac_dev->start(mac_dev); 2527 if (err < 0) { 2528 netif_err(priv, ifup, net_dev, "mac_dev->start() = %d\n", err); 2529 goto mac_start_failed; 2530 } 2531 2532 netif_tx_start_all_queues(net_dev); 2533 2534 return 0; 2535 2536 mac_start_failed: 2537 for (i = 0; i < ARRAY_SIZE(mac_dev->port); i++) 2538 fman_port_disable(mac_dev->port[i]); 2539 2540 phy_init_failed: 2541 dpaa_eth_napi_disable(priv); 2542 2543 return err; 2544 } 2545 2546 static int dpaa_eth_stop(struct net_device *net_dev) 2547 { 2548 struct dpaa_priv *priv; 2549 int err; 2550 2551 err = dpaa_stop(net_dev); 2552 2553 priv = netdev_priv(net_dev); 2554 dpaa_eth_napi_disable(priv); 2555 2556 return err; 2557 } 2558 2559 static int dpaa_ts_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 2560 { 2561 struct dpaa_priv *priv = netdev_priv(dev); 2562 struct hwtstamp_config config; 2563 2564 if (copy_from_user(&config, rq->ifr_data, sizeof(config))) 2565 return -EFAULT; 2566 2567 switch (config.tx_type) { 2568 case HWTSTAMP_TX_OFF: 2569 /* Couldn't disable rx/tx timestamping separately. 2570 * Do nothing here. 2571 */ 2572 priv->tx_tstamp = false; 2573 break; 2574 case HWTSTAMP_TX_ON: 2575 priv->mac_dev->set_tstamp(priv->mac_dev->fman_mac, true); 2576 priv->tx_tstamp = true; 2577 break; 2578 default: 2579 return -ERANGE; 2580 } 2581 2582 if (config.rx_filter == HWTSTAMP_FILTER_NONE) { 2583 /* Couldn't disable rx/tx timestamping separately. 2584 * Do nothing here. 2585 */ 2586 priv->rx_tstamp = false; 2587 } else { 2588 priv->mac_dev->set_tstamp(priv->mac_dev->fman_mac, true); 2589 priv->rx_tstamp = true; 2590 /* TS is set for all frame types, not only those requested */ 2591 config.rx_filter = HWTSTAMP_FILTER_ALL; 2592 } 2593 2594 return copy_to_user(rq->ifr_data, &config, sizeof(config)) ? 2595 -EFAULT : 0; 2596 } 2597 2598 static int dpaa_ioctl(struct net_device *net_dev, struct ifreq *rq, int cmd) 2599 { 2600 int ret = -EINVAL; 2601 2602 if (cmd == SIOCGMIIREG) { 2603 if (net_dev->phydev) 2604 return phy_mii_ioctl(net_dev->phydev, rq, cmd); 2605 } 2606 2607 if (cmd == SIOCSHWTSTAMP) 2608 return dpaa_ts_ioctl(net_dev, rq, cmd); 2609 2610 return ret; 2611 } 2612 2613 static const struct net_device_ops dpaa_ops = { 2614 .ndo_open = dpaa_open, 2615 .ndo_start_xmit = dpaa_start_xmit, 2616 .ndo_stop = dpaa_eth_stop, 2617 .ndo_tx_timeout = dpaa_tx_timeout, 2618 .ndo_get_stats64 = dpaa_get_stats64, 2619 .ndo_change_carrier = fixed_phy_change_carrier, 2620 .ndo_set_mac_address = dpaa_set_mac_address, 2621 .ndo_validate_addr = eth_validate_addr, 2622 .ndo_set_rx_mode = dpaa_set_rx_mode, 2623 .ndo_do_ioctl = dpaa_ioctl, 2624 .ndo_setup_tc = dpaa_setup_tc, 2625 }; 2626 2627 static int dpaa_napi_add(struct net_device *net_dev) 2628 { 2629 struct dpaa_priv *priv = netdev_priv(net_dev); 2630 struct dpaa_percpu_priv *percpu_priv; 2631 int cpu; 2632 2633 for_each_possible_cpu(cpu) { 2634 percpu_priv = per_cpu_ptr(priv->percpu_priv, cpu); 2635 2636 netif_napi_add(net_dev, &percpu_priv->np.napi, 2637 dpaa_eth_poll, NAPI_POLL_WEIGHT); 2638 } 2639 2640 return 0; 2641 } 2642 2643 static void dpaa_napi_del(struct net_device *net_dev) 2644 { 2645 struct dpaa_priv *priv = netdev_priv(net_dev); 2646 struct dpaa_percpu_priv *percpu_priv; 2647 int cpu; 2648 2649 for_each_possible_cpu(cpu) { 2650 percpu_priv = per_cpu_ptr(priv->percpu_priv, cpu); 2651 2652 netif_napi_del(&percpu_priv->np.napi); 2653 } 2654 } 2655 2656 static inline void dpaa_bp_free_pf(const struct dpaa_bp *bp, 2657 struct bm_buffer *bmb) 2658 { 2659 dma_addr_t addr = bm_buf_addr(bmb); 2660 2661 dma_unmap_page(bp->priv->rx_dma_dev, addr, DPAA_BP_RAW_SIZE, 2662 DMA_FROM_DEVICE); 2663 2664 skb_free_frag(phys_to_virt(addr)); 2665 } 2666 2667 /* Alloc the dpaa_bp struct and configure default values */ 2668 static struct dpaa_bp *dpaa_bp_alloc(struct device *dev) 2669 { 2670 struct dpaa_bp *dpaa_bp; 2671 2672 dpaa_bp = devm_kzalloc(dev, sizeof(*dpaa_bp), GFP_KERNEL); 2673 if (!dpaa_bp) 2674 return ERR_PTR(-ENOMEM); 2675 2676 dpaa_bp->bpid = FSL_DPAA_BPID_INV; 2677 dpaa_bp->percpu_count = devm_alloc_percpu(dev, *dpaa_bp->percpu_count); 2678 if (!dpaa_bp->percpu_count) 2679 return ERR_PTR(-ENOMEM); 2680 2681 dpaa_bp->config_count = FSL_DPAA_ETH_MAX_BUF_COUNT; 2682 2683 dpaa_bp->seed_cb = dpaa_bp_seed; 2684 dpaa_bp->free_buf_cb = dpaa_bp_free_pf; 2685 2686 return dpaa_bp; 2687 } 2688 2689 /* Place all ingress FQs (Rx Default, Rx Error) in a dedicated CGR. 2690 * We won't be sending congestion notifications to FMan; for now, we just use 2691 * this CGR to generate enqueue rejections to FMan in order to drop the frames 2692 * before they reach our ingress queues and eat up memory. 2693 */ 2694 static int dpaa_ingress_cgr_init(struct dpaa_priv *priv) 2695 { 2696 struct qm_mcc_initcgr initcgr; 2697 u32 cs_th; 2698 int err; 2699 2700 err = qman_alloc_cgrid(&priv->ingress_cgr.cgrid); 2701 if (err < 0) { 2702 if (netif_msg_drv(priv)) 2703 pr_err("Error %d allocating CGR ID\n", err); 2704 goto out_error; 2705 } 2706 2707 /* Enable CS TD, but disable Congestion State Change Notifications. */ 2708 memset(&initcgr, 0, sizeof(initcgr)); 2709 initcgr.we_mask = cpu_to_be16(QM_CGR_WE_CS_THRES); 2710 initcgr.cgr.cscn_en = QM_CGR_EN; 2711 cs_th = DPAA_INGRESS_CS_THRESHOLD; 2712 qm_cgr_cs_thres_set64(&initcgr.cgr.cs_thres, cs_th, 1); 2713 2714 initcgr.we_mask |= cpu_to_be16(QM_CGR_WE_CSTD_EN); 2715 initcgr.cgr.cstd_en = QM_CGR_EN; 2716 2717 /* This CGR will be associated with the SWP affined to the current CPU. 2718 * However, we'll place all our ingress FQs in it. 2719 */ 2720 err = qman_create_cgr(&priv->ingress_cgr, QMAN_CGR_FLAG_USE_INIT, 2721 &initcgr); 2722 if (err < 0) { 2723 if (netif_msg_drv(priv)) 2724 pr_err("Error %d creating ingress CGR with ID %d\n", 2725 err, priv->ingress_cgr.cgrid); 2726 qman_release_cgrid(priv->ingress_cgr.cgrid); 2727 goto out_error; 2728 } 2729 if (netif_msg_drv(priv)) 2730 pr_debug("Created ingress CGR %d for netdev with hwaddr %pM\n", 2731 priv->ingress_cgr.cgrid, priv->mac_dev->addr); 2732 2733 priv->use_ingress_cgr = true; 2734 2735 out_error: 2736 return err; 2737 } 2738 2739 static inline u16 dpaa_get_headroom(struct dpaa_buffer_layout *bl) 2740 { 2741 u16 headroom; 2742 2743 /* The frame headroom must accommodate: 2744 * - the driver private data area 2745 * - parse results, hash results, timestamp if selected 2746 * If either hash results or time stamp are selected, both will 2747 * be copied to/from the frame headroom, as TS is located between PR and 2748 * HR in the IC and IC copy size has a granularity of 16bytes 2749 * (see description of FMBM_RICP and FMBM_TICP registers in DPAARM) 2750 * 2751 * Also make sure the headroom is a multiple of data_align bytes 2752 */ 2753 headroom = (u16)(bl->priv_data_size + DPAA_PARSE_RESULTS_SIZE + 2754 DPAA_TIME_STAMP_SIZE + DPAA_HASH_RESULTS_SIZE); 2755 2756 return DPAA_FD_DATA_ALIGNMENT ? ALIGN(headroom, 2757 DPAA_FD_DATA_ALIGNMENT) : 2758 headroom; 2759 } 2760 2761 static int dpaa_eth_probe(struct platform_device *pdev) 2762 { 2763 struct net_device *net_dev = NULL; 2764 struct dpaa_bp *dpaa_bp = NULL; 2765 struct dpaa_fq *dpaa_fq, *tmp; 2766 struct dpaa_priv *priv = NULL; 2767 struct fm_port_fqs port_fqs; 2768 struct mac_device *mac_dev; 2769 int err = 0, channel; 2770 struct device *dev; 2771 2772 dev = &pdev->dev; 2773 2774 err = bman_is_probed(); 2775 if (!err) 2776 return -EPROBE_DEFER; 2777 if (err < 0) { 2778 dev_err(dev, "failing probe due to bman probe error\n"); 2779 return -ENODEV; 2780 } 2781 err = qman_is_probed(); 2782 if (!err) 2783 return -EPROBE_DEFER; 2784 if (err < 0) { 2785 dev_err(dev, "failing probe due to qman probe error\n"); 2786 return -ENODEV; 2787 } 2788 err = bman_portals_probed(); 2789 if (!err) 2790 return -EPROBE_DEFER; 2791 if (err < 0) { 2792 dev_err(dev, 2793 "failing probe due to bman portals probe error\n"); 2794 return -ENODEV; 2795 } 2796 err = qman_portals_probed(); 2797 if (!err) 2798 return -EPROBE_DEFER; 2799 if (err < 0) { 2800 dev_err(dev, 2801 "failing probe due to qman portals probe error\n"); 2802 return -ENODEV; 2803 } 2804 2805 /* Allocate this early, so we can store relevant information in 2806 * the private area 2807 */ 2808 net_dev = alloc_etherdev_mq(sizeof(*priv), DPAA_ETH_TXQ_NUM); 2809 if (!net_dev) { 2810 dev_err(dev, "alloc_etherdev_mq() failed\n"); 2811 return -ENOMEM; 2812 } 2813 2814 /* Do this here, so we can be verbose early */ 2815 SET_NETDEV_DEV(net_dev, dev); 2816 dev_set_drvdata(dev, net_dev); 2817 2818 priv = netdev_priv(net_dev); 2819 priv->net_dev = net_dev; 2820 2821 priv->msg_enable = netif_msg_init(debug, DPAA_MSG_DEFAULT); 2822 2823 mac_dev = dpaa_mac_dev_get(pdev); 2824 if (IS_ERR(mac_dev)) { 2825 netdev_err(net_dev, "dpaa_mac_dev_get() failed\n"); 2826 err = PTR_ERR(mac_dev); 2827 goto free_netdev; 2828 } 2829 2830 /* Devices used for DMA mapping */ 2831 priv->rx_dma_dev = fman_port_get_device(mac_dev->port[RX]); 2832 priv->tx_dma_dev = fman_port_get_device(mac_dev->port[TX]); 2833 err = dma_coerce_mask_and_coherent(priv->rx_dma_dev, DMA_BIT_MASK(40)); 2834 if (!err) 2835 err = dma_coerce_mask_and_coherent(priv->tx_dma_dev, 2836 DMA_BIT_MASK(40)); 2837 if (err) { 2838 netdev_err(net_dev, "dma_coerce_mask_and_coherent() failed\n"); 2839 return err; 2840 } 2841 2842 /* If fsl_fm_max_frm is set to a higher value than the all-common 1500, 2843 * we choose conservatively and let the user explicitly set a higher 2844 * MTU via ifconfig. Otherwise, the user may end up with different MTUs 2845 * in the same LAN. 2846 * If on the other hand fsl_fm_max_frm has been chosen below 1500, 2847 * start with the maximum allowed. 2848 */ 2849 net_dev->mtu = min(dpaa_get_max_mtu(), ETH_DATA_LEN); 2850 2851 netdev_dbg(net_dev, "Setting initial MTU on net device: %d\n", 2852 net_dev->mtu); 2853 2854 priv->buf_layout[RX].priv_data_size = DPAA_RX_PRIV_DATA_SIZE; /* Rx */ 2855 priv->buf_layout[TX].priv_data_size = DPAA_TX_PRIV_DATA_SIZE; /* Tx */ 2856 2857 /* bp init */ 2858 dpaa_bp = dpaa_bp_alloc(dev); 2859 if (IS_ERR(dpaa_bp)) { 2860 err = PTR_ERR(dpaa_bp); 2861 goto free_dpaa_bps; 2862 } 2863 /* the raw size of the buffers used for reception */ 2864 dpaa_bp->raw_size = DPAA_BP_RAW_SIZE; 2865 /* avoid runtime computations by keeping the usable size here */ 2866 dpaa_bp->size = dpaa_bp_size(dpaa_bp->raw_size); 2867 dpaa_bp->priv = priv; 2868 2869 err = dpaa_bp_alloc_pool(dpaa_bp); 2870 if (err < 0) 2871 goto free_dpaa_bps; 2872 priv->dpaa_bp = dpaa_bp; 2873 2874 INIT_LIST_HEAD(&priv->dpaa_fq_list); 2875 2876 memset(&port_fqs, 0, sizeof(port_fqs)); 2877 2878 err = dpaa_alloc_all_fqs(dev, &priv->dpaa_fq_list, &port_fqs); 2879 if (err < 0) { 2880 dev_err(dev, "dpaa_alloc_all_fqs() failed\n"); 2881 goto free_dpaa_bps; 2882 } 2883 2884 priv->mac_dev = mac_dev; 2885 2886 channel = dpaa_get_channel(); 2887 if (channel < 0) { 2888 dev_err(dev, "dpaa_get_channel() failed\n"); 2889 err = channel; 2890 goto free_dpaa_bps; 2891 } 2892 2893 priv->channel = (u16)channel; 2894 2895 /* Walk the CPUs with affine portals 2896 * and add this pool channel to each's dequeue mask. 2897 */ 2898 dpaa_eth_add_channel(priv->channel, &pdev->dev); 2899 2900 dpaa_fq_setup(priv, &dpaa_fq_cbs, priv->mac_dev->port[TX]); 2901 2902 /* Create a congestion group for this netdev, with 2903 * dynamically-allocated CGR ID. 2904 * Must be executed after probing the MAC, but before 2905 * assigning the egress FQs to the CGRs. 2906 */ 2907 err = dpaa_eth_cgr_init(priv); 2908 if (err < 0) { 2909 dev_err(dev, "Error initializing CGR\n"); 2910 goto free_dpaa_bps; 2911 } 2912 2913 err = dpaa_ingress_cgr_init(priv); 2914 if (err < 0) { 2915 dev_err(dev, "Error initializing ingress CGR\n"); 2916 goto delete_egress_cgr; 2917 } 2918 2919 /* Add the FQs to the interface, and make them active */ 2920 list_for_each_entry_safe(dpaa_fq, tmp, &priv->dpaa_fq_list, list) { 2921 err = dpaa_fq_init(dpaa_fq, false); 2922 if (err < 0) 2923 goto free_dpaa_fqs; 2924 } 2925 2926 priv->tx_headroom = dpaa_get_headroom(&priv->buf_layout[TX]); 2927 priv->rx_headroom = dpaa_get_headroom(&priv->buf_layout[RX]); 2928 2929 /* All real interfaces need their ports initialized */ 2930 err = dpaa_eth_init_ports(mac_dev, dpaa_bp, &port_fqs, 2931 &priv->buf_layout[0], dev); 2932 if (err) 2933 goto free_dpaa_fqs; 2934 2935 /* Rx traffic distribution based on keygen hashing defaults to on */ 2936 priv->keygen_in_use = true; 2937 2938 priv->percpu_priv = devm_alloc_percpu(dev, *priv->percpu_priv); 2939 if (!priv->percpu_priv) { 2940 dev_err(dev, "devm_alloc_percpu() failed\n"); 2941 err = -ENOMEM; 2942 goto free_dpaa_fqs; 2943 } 2944 2945 priv->num_tc = 1; 2946 netif_set_real_num_tx_queues(net_dev, priv->num_tc * DPAA_TC_TXQ_NUM); 2947 2948 /* Initialize NAPI */ 2949 err = dpaa_napi_add(net_dev); 2950 if (err < 0) 2951 goto delete_dpaa_napi; 2952 2953 err = dpaa_netdev_init(net_dev, &dpaa_ops, tx_timeout); 2954 if (err < 0) 2955 goto delete_dpaa_napi; 2956 2957 dpaa_eth_sysfs_init(&net_dev->dev); 2958 2959 netif_info(priv, probe, net_dev, "Probed interface %s\n", 2960 net_dev->name); 2961 2962 return 0; 2963 2964 delete_dpaa_napi: 2965 dpaa_napi_del(net_dev); 2966 free_dpaa_fqs: 2967 dpaa_fq_free(dev, &priv->dpaa_fq_list); 2968 qman_delete_cgr_safe(&priv->ingress_cgr); 2969 qman_release_cgrid(priv->ingress_cgr.cgrid); 2970 delete_egress_cgr: 2971 qman_delete_cgr_safe(&priv->cgr_data.cgr); 2972 qman_release_cgrid(priv->cgr_data.cgr.cgrid); 2973 free_dpaa_bps: 2974 dpaa_bps_free(priv); 2975 free_netdev: 2976 dev_set_drvdata(dev, NULL); 2977 free_netdev(net_dev); 2978 2979 return err; 2980 } 2981 2982 static int dpaa_remove(struct platform_device *pdev) 2983 { 2984 struct net_device *net_dev; 2985 struct dpaa_priv *priv; 2986 struct device *dev; 2987 int err; 2988 2989 dev = &pdev->dev; 2990 net_dev = dev_get_drvdata(dev); 2991 2992 priv = netdev_priv(net_dev); 2993 2994 dpaa_eth_sysfs_remove(dev); 2995 2996 dev_set_drvdata(dev, NULL); 2997 unregister_netdev(net_dev); 2998 2999 err = dpaa_fq_free(dev, &priv->dpaa_fq_list); 3000 3001 qman_delete_cgr_safe(&priv->ingress_cgr); 3002 qman_release_cgrid(priv->ingress_cgr.cgrid); 3003 qman_delete_cgr_safe(&priv->cgr_data.cgr); 3004 qman_release_cgrid(priv->cgr_data.cgr.cgrid); 3005 3006 dpaa_napi_del(net_dev); 3007 3008 dpaa_bps_free(priv); 3009 3010 free_netdev(net_dev); 3011 3012 return err; 3013 } 3014 3015 static const struct platform_device_id dpaa_devtype[] = { 3016 { 3017 .name = "dpaa-ethernet", 3018 .driver_data = 0, 3019 }, { 3020 } 3021 }; 3022 MODULE_DEVICE_TABLE(platform, dpaa_devtype); 3023 3024 static struct platform_driver dpaa_driver = { 3025 .driver = { 3026 .name = KBUILD_MODNAME, 3027 }, 3028 .id_table = dpaa_devtype, 3029 .probe = dpaa_eth_probe, 3030 .remove = dpaa_remove 3031 }; 3032 3033 static int __init dpaa_load(void) 3034 { 3035 int err; 3036 3037 pr_debug("FSL DPAA Ethernet driver\n"); 3038 3039 /* initialize dpaa_eth mirror values */ 3040 dpaa_rx_extra_headroom = fman_get_rx_extra_headroom(); 3041 dpaa_max_frm = fman_get_max_frm(); 3042 3043 err = platform_driver_register(&dpaa_driver); 3044 if (err < 0) 3045 pr_err("Error, platform_driver_register() = %d\n", err); 3046 3047 return err; 3048 } 3049 module_init(dpaa_load); 3050 3051 static void __exit dpaa_unload(void) 3052 { 3053 platform_driver_unregister(&dpaa_driver); 3054 3055 /* Only one channel is used and needs to be released after all 3056 * interfaces are removed 3057 */ 3058 dpaa_release_channel(); 3059 } 3060 module_exit(dpaa_unload); 3061 3062 MODULE_LICENSE("Dual BSD/GPL"); 3063 MODULE_DESCRIPTION("FSL DPAA Ethernet driver"); 3064