1 /* Copyright 2008 - 2016 Freescale Semiconductor Inc. 2 * Copyright 2020 NXP 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * * Redistributions of source code must retain the above copyright 7 * notice, this list of conditions and the following disclaimer. 8 * * Redistributions in binary form must reproduce the above copyright 9 * notice, this list of conditions and the following disclaimer in the 10 * documentation and/or other materials provided with the distribution. 11 * * Neither the name of Freescale Semiconductor nor the 12 * names of its contributors may be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * ALTERNATIVELY, this software may be distributed under the terms of the 16 * GNU General Public License ("GPL") as published by the Free Software 17 * Foundation, either version 2 of that License or (at your option) any 18 * later version. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 21 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 22 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 23 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 24 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 25 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 27 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 29 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 33 34 #include <linux/init.h> 35 #include <linux/module.h> 36 #include <linux/of_platform.h> 37 #include <linux/of_mdio.h> 38 #include <linux/of_net.h> 39 #include <linux/io.h> 40 #include <linux/if_arp.h> 41 #include <linux/if_vlan.h> 42 #include <linux/icmp.h> 43 #include <linux/ip.h> 44 #include <linux/ipv6.h> 45 #include <linux/udp.h> 46 #include <linux/tcp.h> 47 #include <linux/net.h> 48 #include <linux/skbuff.h> 49 #include <linux/etherdevice.h> 50 #include <linux/if_ether.h> 51 #include <linux/highmem.h> 52 #include <linux/percpu.h> 53 #include <linux/dma-mapping.h> 54 #include <linux/sort.h> 55 #include <linux/phy_fixed.h> 56 #include <soc/fsl/bman.h> 57 #include <soc/fsl/qman.h> 58 #include "fman.h" 59 #include "fman_port.h" 60 #include "mac.h" 61 #include "dpaa_eth.h" 62 63 /* CREATE_TRACE_POINTS only needs to be defined once. Other dpaa files 64 * using trace events only need to #include <trace/events/sched.h> 65 */ 66 #define CREATE_TRACE_POINTS 67 #include "dpaa_eth_trace.h" 68 69 static int debug = -1; 70 module_param(debug, int, 0444); 71 MODULE_PARM_DESC(debug, "Module/Driver verbosity level (0=none,...,16=all)"); 72 73 static u16 tx_timeout = 1000; 74 module_param(tx_timeout, ushort, 0444); 75 MODULE_PARM_DESC(tx_timeout, "The Tx timeout in ms"); 76 77 #define FM_FD_STAT_RX_ERRORS \ 78 (FM_FD_ERR_DMA | FM_FD_ERR_PHYSICAL | \ 79 FM_FD_ERR_SIZE | FM_FD_ERR_CLS_DISCARD | \ 80 FM_FD_ERR_EXTRACTION | FM_FD_ERR_NO_SCHEME | \ 81 FM_FD_ERR_PRS_TIMEOUT | FM_FD_ERR_PRS_ILL_INSTRUCT | \ 82 FM_FD_ERR_PRS_HDR_ERR) 83 84 #define FM_FD_STAT_TX_ERRORS \ 85 (FM_FD_ERR_UNSUPPORTED_FORMAT | \ 86 FM_FD_ERR_LENGTH | FM_FD_ERR_DMA) 87 88 #define DPAA_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \ 89 NETIF_MSG_LINK | NETIF_MSG_IFUP | \ 90 NETIF_MSG_IFDOWN) 91 92 #define DPAA_INGRESS_CS_THRESHOLD 0x10000000 93 /* Ingress congestion threshold on FMan ports 94 * The size in bytes of the ingress tail-drop threshold on FMan ports. 95 * Traffic piling up above this value will be rejected by QMan and discarded 96 * by FMan. 97 */ 98 99 /* Size in bytes of the FQ taildrop threshold */ 100 #define DPAA_FQ_TD 0x200000 101 102 #define DPAA_CS_THRESHOLD_1G 0x06000000 103 /* Egress congestion threshold on 1G ports, range 0x1000 .. 0x10000000 104 * The size in bytes of the egress Congestion State notification threshold on 105 * 1G ports. The 1G dTSECs can quite easily be flooded by cores doing Tx in a 106 * tight loop (e.g. by sending UDP datagrams at "while(1) speed"), 107 * and the larger the frame size, the more acute the problem. 108 * So we have to find a balance between these factors: 109 * - avoiding the device staying congested for a prolonged time (risking 110 * the netdev watchdog to fire - see also the tx_timeout module param); 111 * - affecting performance of protocols such as TCP, which otherwise 112 * behave well under the congestion notification mechanism; 113 * - preventing the Tx cores from tightly-looping (as if the congestion 114 * threshold was too low to be effective); 115 * - running out of memory if the CS threshold is set too high. 116 */ 117 118 #define DPAA_CS_THRESHOLD_10G 0x10000000 119 /* The size in bytes of the egress Congestion State notification threshold on 120 * 10G ports, range 0x1000 .. 0x10000000 121 */ 122 123 /* Largest value that the FQD's OAL field can hold */ 124 #define FSL_QMAN_MAX_OAL 127 125 126 /* Default alignment for start of data in an Rx FD */ 127 #ifdef CONFIG_DPAA_ERRATUM_A050385 128 /* aligning data start to 64 avoids DMA transaction splits, unless the buffer 129 * is crossing a 4k page boundary 130 */ 131 #define DPAA_FD_DATA_ALIGNMENT (fman_has_errata_a050385() ? 64 : 16) 132 /* aligning to 256 avoids DMA transaction splits caused by 4k page boundary 133 * crossings; also, all SG fragments except the last must have a size multiple 134 * of 256 to avoid DMA transaction splits 135 */ 136 #define DPAA_A050385_ALIGN 256 137 #define DPAA_FD_RX_DATA_ALIGNMENT (fman_has_errata_a050385() ? \ 138 DPAA_A050385_ALIGN : 16) 139 #else 140 #define DPAA_FD_DATA_ALIGNMENT 16 141 #define DPAA_FD_RX_DATA_ALIGNMENT DPAA_FD_DATA_ALIGNMENT 142 #endif 143 144 /* The DPAA requires 256 bytes reserved and mapped for the SGT */ 145 #define DPAA_SGT_SIZE 256 146 147 /* Values for the L3R field of the FM Parse Results 148 */ 149 /* L3 Type field: First IP Present IPv4 */ 150 #define FM_L3_PARSE_RESULT_IPV4 0x8000 151 /* L3 Type field: First IP Present IPv6 */ 152 #define FM_L3_PARSE_RESULT_IPV6 0x4000 153 /* Values for the L4R field of the FM Parse Results */ 154 /* L4 Type field: UDP */ 155 #define FM_L4_PARSE_RESULT_UDP 0x40 156 /* L4 Type field: TCP */ 157 #define FM_L4_PARSE_RESULT_TCP 0x20 158 159 /* FD status field indicating whether the FM Parser has attempted to validate 160 * the L4 csum of the frame. 161 * Note that having this bit set doesn't necessarily imply that the checksum 162 * is valid. One would have to check the parse results to find that out. 163 */ 164 #define FM_FD_STAT_L4CV 0x00000004 165 166 #define DPAA_SGT_MAX_ENTRIES 16 /* maximum number of entries in SG Table */ 167 #define DPAA_BUFF_RELEASE_MAX 8 /* maximum number of buffers released at once */ 168 169 #define FSL_DPAA_BPID_INV 0xff 170 #define FSL_DPAA_ETH_MAX_BUF_COUNT 128 171 #define FSL_DPAA_ETH_REFILL_THRESHOLD 80 172 173 #define DPAA_TX_PRIV_DATA_SIZE 16 174 #define DPAA_PARSE_RESULTS_SIZE sizeof(struct fman_prs_result) 175 #define DPAA_TIME_STAMP_SIZE 8 176 #define DPAA_HASH_RESULTS_SIZE 8 177 #ifdef CONFIG_DPAA_ERRATUM_A050385 178 #define DPAA_RX_PRIV_DATA_SIZE (DPAA_A050385_ALIGN - (DPAA_PARSE_RESULTS_SIZE\ 179 + DPAA_TIME_STAMP_SIZE + DPAA_HASH_RESULTS_SIZE)) 180 #else 181 #define DPAA_RX_PRIV_DATA_SIZE (u16)(DPAA_TX_PRIV_DATA_SIZE + \ 182 dpaa_rx_extra_headroom) 183 #endif 184 185 #define DPAA_ETH_PCD_RXQ_NUM 128 186 187 #define DPAA_ENQUEUE_RETRIES 100000 188 189 enum port_type {RX, TX}; 190 191 struct fm_port_fqs { 192 struct dpaa_fq *tx_defq; 193 struct dpaa_fq *tx_errq; 194 struct dpaa_fq *rx_defq; 195 struct dpaa_fq *rx_errq; 196 struct dpaa_fq *rx_pcdq; 197 }; 198 199 /* All the dpa bps in use at any moment */ 200 static struct dpaa_bp *dpaa_bp_array[BM_MAX_NUM_OF_POOLS]; 201 202 #define DPAA_BP_RAW_SIZE 4096 203 204 #ifdef CONFIG_DPAA_ERRATUM_A050385 205 #define dpaa_bp_size(raw_size) (SKB_WITH_OVERHEAD(raw_size) & \ 206 ~(DPAA_A050385_ALIGN - 1)) 207 #else 208 #define dpaa_bp_size(raw_size) SKB_WITH_OVERHEAD(raw_size) 209 #endif 210 211 static int dpaa_max_frm; 212 213 static int dpaa_rx_extra_headroom; 214 215 #define dpaa_get_max_mtu() \ 216 (dpaa_max_frm - (VLAN_ETH_HLEN + ETH_FCS_LEN)) 217 218 static int dpaa_netdev_init(struct net_device *net_dev, 219 const struct net_device_ops *dpaa_ops, 220 u16 tx_timeout) 221 { 222 struct dpaa_priv *priv = netdev_priv(net_dev); 223 struct device *dev = net_dev->dev.parent; 224 struct dpaa_percpu_priv *percpu_priv; 225 const u8 *mac_addr; 226 int i, err; 227 228 /* Although we access another CPU's private data here 229 * we do it at initialization so it is safe 230 */ 231 for_each_possible_cpu(i) { 232 percpu_priv = per_cpu_ptr(priv->percpu_priv, i); 233 percpu_priv->net_dev = net_dev; 234 } 235 236 net_dev->netdev_ops = dpaa_ops; 237 mac_addr = priv->mac_dev->addr; 238 239 net_dev->mem_start = priv->mac_dev->res->start; 240 net_dev->mem_end = priv->mac_dev->res->end; 241 242 net_dev->min_mtu = ETH_MIN_MTU; 243 net_dev->max_mtu = dpaa_get_max_mtu(); 244 245 net_dev->hw_features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 246 NETIF_F_LLTX | NETIF_F_RXHASH); 247 248 net_dev->hw_features |= NETIF_F_SG | NETIF_F_HIGHDMA; 249 /* The kernels enables GSO automatically, if we declare NETIF_F_SG. 250 * For conformity, we'll still declare GSO explicitly. 251 */ 252 net_dev->features |= NETIF_F_GSO; 253 net_dev->features |= NETIF_F_RXCSUM; 254 255 net_dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 256 /* we do not want shared skbs on TX */ 257 net_dev->priv_flags &= ~IFF_TX_SKB_SHARING; 258 259 net_dev->features |= net_dev->hw_features; 260 net_dev->vlan_features = net_dev->features; 261 262 memcpy(net_dev->perm_addr, mac_addr, net_dev->addr_len); 263 memcpy(net_dev->dev_addr, mac_addr, net_dev->addr_len); 264 265 net_dev->ethtool_ops = &dpaa_ethtool_ops; 266 267 net_dev->needed_headroom = priv->tx_headroom; 268 net_dev->watchdog_timeo = msecs_to_jiffies(tx_timeout); 269 270 /* start without the RUNNING flag, phylib controls it later */ 271 netif_carrier_off(net_dev); 272 273 err = register_netdev(net_dev); 274 if (err < 0) { 275 dev_err(dev, "register_netdev() = %d\n", err); 276 return err; 277 } 278 279 return 0; 280 } 281 282 static int dpaa_stop(struct net_device *net_dev) 283 { 284 struct mac_device *mac_dev; 285 struct dpaa_priv *priv; 286 int i, err, error; 287 288 priv = netdev_priv(net_dev); 289 mac_dev = priv->mac_dev; 290 291 netif_tx_stop_all_queues(net_dev); 292 /* Allow the Fman (Tx) port to process in-flight frames before we 293 * try switching it off. 294 */ 295 msleep(200); 296 297 err = mac_dev->stop(mac_dev); 298 if (err < 0) 299 netif_err(priv, ifdown, net_dev, "mac_dev->stop() = %d\n", 300 err); 301 302 for (i = 0; i < ARRAY_SIZE(mac_dev->port); i++) { 303 error = fman_port_disable(mac_dev->port[i]); 304 if (error) 305 err = error; 306 } 307 308 if (net_dev->phydev) 309 phy_disconnect(net_dev->phydev); 310 net_dev->phydev = NULL; 311 312 msleep(200); 313 314 return err; 315 } 316 317 static void dpaa_tx_timeout(struct net_device *net_dev, unsigned int txqueue) 318 { 319 struct dpaa_percpu_priv *percpu_priv; 320 const struct dpaa_priv *priv; 321 322 priv = netdev_priv(net_dev); 323 percpu_priv = this_cpu_ptr(priv->percpu_priv); 324 325 netif_crit(priv, timer, net_dev, "Transmit timeout latency: %u ms\n", 326 jiffies_to_msecs(jiffies - dev_trans_start(net_dev))); 327 328 percpu_priv->stats.tx_errors++; 329 } 330 331 /* Calculates the statistics for the given device by adding the statistics 332 * collected by each CPU. 333 */ 334 static void dpaa_get_stats64(struct net_device *net_dev, 335 struct rtnl_link_stats64 *s) 336 { 337 int numstats = sizeof(struct rtnl_link_stats64) / sizeof(u64); 338 struct dpaa_priv *priv = netdev_priv(net_dev); 339 struct dpaa_percpu_priv *percpu_priv; 340 u64 *netstats = (u64 *)s; 341 u64 *cpustats; 342 int i, j; 343 344 for_each_possible_cpu(i) { 345 percpu_priv = per_cpu_ptr(priv->percpu_priv, i); 346 347 cpustats = (u64 *)&percpu_priv->stats; 348 349 /* add stats from all CPUs */ 350 for (j = 0; j < numstats; j++) 351 netstats[j] += cpustats[j]; 352 } 353 } 354 355 static int dpaa_setup_tc(struct net_device *net_dev, enum tc_setup_type type, 356 void *type_data) 357 { 358 struct dpaa_priv *priv = netdev_priv(net_dev); 359 struct tc_mqprio_qopt *mqprio = type_data; 360 u8 num_tc; 361 int i; 362 363 if (type != TC_SETUP_QDISC_MQPRIO) 364 return -EOPNOTSUPP; 365 366 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS; 367 num_tc = mqprio->num_tc; 368 369 if (num_tc == priv->num_tc) 370 return 0; 371 372 if (!num_tc) { 373 netdev_reset_tc(net_dev); 374 goto out; 375 } 376 377 if (num_tc > DPAA_TC_NUM) { 378 netdev_err(net_dev, "Too many traffic classes: max %d supported.\n", 379 DPAA_TC_NUM); 380 return -EINVAL; 381 } 382 383 netdev_set_num_tc(net_dev, num_tc); 384 385 for (i = 0; i < num_tc; i++) 386 netdev_set_tc_queue(net_dev, i, DPAA_TC_TXQ_NUM, 387 i * DPAA_TC_TXQ_NUM); 388 389 out: 390 priv->num_tc = num_tc ? : 1; 391 netif_set_real_num_tx_queues(net_dev, priv->num_tc * DPAA_TC_TXQ_NUM); 392 return 0; 393 } 394 395 static struct mac_device *dpaa_mac_dev_get(struct platform_device *pdev) 396 { 397 struct dpaa_eth_data *eth_data; 398 struct device *dpaa_dev; 399 struct mac_device *mac_dev; 400 401 dpaa_dev = &pdev->dev; 402 eth_data = dpaa_dev->platform_data; 403 if (!eth_data) { 404 dev_err(dpaa_dev, "eth_data missing\n"); 405 return ERR_PTR(-ENODEV); 406 } 407 mac_dev = eth_data->mac_dev; 408 if (!mac_dev) { 409 dev_err(dpaa_dev, "mac_dev missing\n"); 410 return ERR_PTR(-EINVAL); 411 } 412 413 return mac_dev; 414 } 415 416 static int dpaa_set_mac_address(struct net_device *net_dev, void *addr) 417 { 418 const struct dpaa_priv *priv; 419 struct mac_device *mac_dev; 420 struct sockaddr old_addr; 421 int err; 422 423 priv = netdev_priv(net_dev); 424 425 memcpy(old_addr.sa_data, net_dev->dev_addr, ETH_ALEN); 426 427 err = eth_mac_addr(net_dev, addr); 428 if (err < 0) { 429 netif_err(priv, drv, net_dev, "eth_mac_addr() = %d\n", err); 430 return err; 431 } 432 433 mac_dev = priv->mac_dev; 434 435 err = mac_dev->change_addr(mac_dev->fman_mac, 436 (enet_addr_t *)net_dev->dev_addr); 437 if (err < 0) { 438 netif_err(priv, drv, net_dev, "mac_dev->change_addr() = %d\n", 439 err); 440 /* reverting to previous address */ 441 eth_mac_addr(net_dev, &old_addr); 442 443 return err; 444 } 445 446 return 0; 447 } 448 449 static void dpaa_set_rx_mode(struct net_device *net_dev) 450 { 451 const struct dpaa_priv *priv; 452 int err; 453 454 priv = netdev_priv(net_dev); 455 456 if (!!(net_dev->flags & IFF_PROMISC) != priv->mac_dev->promisc) { 457 priv->mac_dev->promisc = !priv->mac_dev->promisc; 458 err = priv->mac_dev->set_promisc(priv->mac_dev->fman_mac, 459 priv->mac_dev->promisc); 460 if (err < 0) 461 netif_err(priv, drv, net_dev, 462 "mac_dev->set_promisc() = %d\n", 463 err); 464 } 465 466 if (!!(net_dev->flags & IFF_ALLMULTI) != priv->mac_dev->allmulti) { 467 priv->mac_dev->allmulti = !priv->mac_dev->allmulti; 468 err = priv->mac_dev->set_allmulti(priv->mac_dev->fman_mac, 469 priv->mac_dev->allmulti); 470 if (err < 0) 471 netif_err(priv, drv, net_dev, 472 "mac_dev->set_allmulti() = %d\n", 473 err); 474 } 475 476 err = priv->mac_dev->set_multi(net_dev, priv->mac_dev); 477 if (err < 0) 478 netif_err(priv, drv, net_dev, "mac_dev->set_multi() = %d\n", 479 err); 480 } 481 482 static struct dpaa_bp *dpaa_bpid2pool(int bpid) 483 { 484 if (WARN_ON(bpid < 0 || bpid >= BM_MAX_NUM_OF_POOLS)) 485 return NULL; 486 487 return dpaa_bp_array[bpid]; 488 } 489 490 /* checks if this bpool is already allocated */ 491 static bool dpaa_bpid2pool_use(int bpid) 492 { 493 if (dpaa_bpid2pool(bpid)) { 494 refcount_inc(&dpaa_bp_array[bpid]->refs); 495 return true; 496 } 497 498 return false; 499 } 500 501 /* called only once per bpid by dpaa_bp_alloc_pool() */ 502 static void dpaa_bpid2pool_map(int bpid, struct dpaa_bp *dpaa_bp) 503 { 504 dpaa_bp_array[bpid] = dpaa_bp; 505 refcount_set(&dpaa_bp->refs, 1); 506 } 507 508 static int dpaa_bp_alloc_pool(struct dpaa_bp *dpaa_bp) 509 { 510 int err; 511 512 if (dpaa_bp->size == 0 || dpaa_bp->config_count == 0) { 513 pr_err("%s: Buffer pool is not properly initialized! Missing size or initial number of buffers\n", 514 __func__); 515 return -EINVAL; 516 } 517 518 /* If the pool is already specified, we only create one per bpid */ 519 if (dpaa_bp->bpid != FSL_DPAA_BPID_INV && 520 dpaa_bpid2pool_use(dpaa_bp->bpid)) 521 return 0; 522 523 if (dpaa_bp->bpid == FSL_DPAA_BPID_INV) { 524 dpaa_bp->pool = bman_new_pool(); 525 if (!dpaa_bp->pool) { 526 pr_err("%s: bman_new_pool() failed\n", 527 __func__); 528 return -ENODEV; 529 } 530 531 dpaa_bp->bpid = (u8)bman_get_bpid(dpaa_bp->pool); 532 } 533 534 if (dpaa_bp->seed_cb) { 535 err = dpaa_bp->seed_cb(dpaa_bp); 536 if (err) 537 goto pool_seed_failed; 538 } 539 540 dpaa_bpid2pool_map(dpaa_bp->bpid, dpaa_bp); 541 542 return 0; 543 544 pool_seed_failed: 545 pr_err("%s: pool seeding failed\n", __func__); 546 bman_free_pool(dpaa_bp->pool); 547 548 return err; 549 } 550 551 /* remove and free all the buffers from the given buffer pool */ 552 static void dpaa_bp_drain(struct dpaa_bp *bp) 553 { 554 u8 num = 8; 555 int ret; 556 557 do { 558 struct bm_buffer bmb[8]; 559 int i; 560 561 ret = bman_acquire(bp->pool, bmb, num); 562 if (ret < 0) { 563 if (num == 8) { 564 /* we have less than 8 buffers left; 565 * drain them one by one 566 */ 567 num = 1; 568 ret = 1; 569 continue; 570 } else { 571 /* Pool is fully drained */ 572 break; 573 } 574 } 575 576 if (bp->free_buf_cb) 577 for (i = 0; i < num; i++) 578 bp->free_buf_cb(bp, &bmb[i]); 579 } while (ret > 0); 580 } 581 582 static void dpaa_bp_free(struct dpaa_bp *dpaa_bp) 583 { 584 struct dpaa_bp *bp = dpaa_bpid2pool(dpaa_bp->bpid); 585 586 /* the mapping between bpid and dpaa_bp is done very late in the 587 * allocation procedure; if something failed before the mapping, the bp 588 * was not configured, therefore we don't need the below instructions 589 */ 590 if (!bp) 591 return; 592 593 if (!refcount_dec_and_test(&bp->refs)) 594 return; 595 596 if (bp->free_buf_cb) 597 dpaa_bp_drain(bp); 598 599 dpaa_bp_array[bp->bpid] = NULL; 600 bman_free_pool(bp->pool); 601 } 602 603 static void dpaa_bps_free(struct dpaa_priv *priv) 604 { 605 dpaa_bp_free(priv->dpaa_bp); 606 } 607 608 /* Use multiple WQs for FQ assignment: 609 * - Tx Confirmation queues go to WQ1. 610 * - Rx Error and Tx Error queues go to WQ5 (giving them a better chance 611 * to be scheduled, in case there are many more FQs in WQ6). 612 * - Rx Default goes to WQ6. 613 * - Tx queues go to different WQs depending on their priority. Equal 614 * chunks of NR_CPUS queues go to WQ6 (lowest priority), WQ2, WQ1 and 615 * WQ0 (highest priority). 616 * This ensures that Tx-confirmed buffers are timely released. In particular, 617 * it avoids congestion on the Tx Confirm FQs, which can pile up PFDRs if they 618 * are greatly outnumbered by other FQs in the system, while 619 * dequeue scheduling is round-robin. 620 */ 621 static inline void dpaa_assign_wq(struct dpaa_fq *fq, int idx) 622 { 623 switch (fq->fq_type) { 624 case FQ_TYPE_TX_CONFIRM: 625 case FQ_TYPE_TX_CONF_MQ: 626 fq->wq = 1; 627 break; 628 case FQ_TYPE_RX_ERROR: 629 case FQ_TYPE_TX_ERROR: 630 fq->wq = 5; 631 break; 632 case FQ_TYPE_RX_DEFAULT: 633 case FQ_TYPE_RX_PCD: 634 fq->wq = 6; 635 break; 636 case FQ_TYPE_TX: 637 switch (idx / DPAA_TC_TXQ_NUM) { 638 case 0: 639 /* Low priority (best effort) */ 640 fq->wq = 6; 641 break; 642 case 1: 643 /* Medium priority */ 644 fq->wq = 2; 645 break; 646 case 2: 647 /* High priority */ 648 fq->wq = 1; 649 break; 650 case 3: 651 /* Very high priority */ 652 fq->wq = 0; 653 break; 654 default: 655 WARN(1, "Too many TX FQs: more than %d!\n", 656 DPAA_ETH_TXQ_NUM); 657 } 658 break; 659 default: 660 WARN(1, "Invalid FQ type %d for FQID %d!\n", 661 fq->fq_type, fq->fqid); 662 } 663 } 664 665 static struct dpaa_fq *dpaa_fq_alloc(struct device *dev, 666 u32 start, u32 count, 667 struct list_head *list, 668 enum dpaa_fq_type fq_type) 669 { 670 struct dpaa_fq *dpaa_fq; 671 int i; 672 673 dpaa_fq = devm_kcalloc(dev, count, sizeof(*dpaa_fq), 674 GFP_KERNEL); 675 if (!dpaa_fq) 676 return NULL; 677 678 for (i = 0; i < count; i++) { 679 dpaa_fq[i].fq_type = fq_type; 680 dpaa_fq[i].fqid = start ? start + i : 0; 681 list_add_tail(&dpaa_fq[i].list, list); 682 } 683 684 for (i = 0; i < count; i++) 685 dpaa_assign_wq(dpaa_fq + i, i); 686 687 return dpaa_fq; 688 } 689 690 static int dpaa_alloc_all_fqs(struct device *dev, struct list_head *list, 691 struct fm_port_fqs *port_fqs) 692 { 693 struct dpaa_fq *dpaa_fq; 694 u32 fq_base, fq_base_aligned, i; 695 696 dpaa_fq = dpaa_fq_alloc(dev, 0, 1, list, FQ_TYPE_RX_ERROR); 697 if (!dpaa_fq) 698 goto fq_alloc_failed; 699 700 port_fqs->rx_errq = &dpaa_fq[0]; 701 702 dpaa_fq = dpaa_fq_alloc(dev, 0, 1, list, FQ_TYPE_RX_DEFAULT); 703 if (!dpaa_fq) 704 goto fq_alloc_failed; 705 706 port_fqs->rx_defq = &dpaa_fq[0]; 707 708 /* the PCD FQIDs range needs to be aligned for correct operation */ 709 if (qman_alloc_fqid_range(&fq_base, 2 * DPAA_ETH_PCD_RXQ_NUM)) 710 goto fq_alloc_failed; 711 712 fq_base_aligned = ALIGN(fq_base, DPAA_ETH_PCD_RXQ_NUM); 713 714 for (i = fq_base; i < fq_base_aligned; i++) 715 qman_release_fqid(i); 716 717 for (i = fq_base_aligned + DPAA_ETH_PCD_RXQ_NUM; 718 i < (fq_base + 2 * DPAA_ETH_PCD_RXQ_NUM); i++) 719 qman_release_fqid(i); 720 721 dpaa_fq = dpaa_fq_alloc(dev, fq_base_aligned, DPAA_ETH_PCD_RXQ_NUM, 722 list, FQ_TYPE_RX_PCD); 723 if (!dpaa_fq) 724 goto fq_alloc_failed; 725 726 port_fqs->rx_pcdq = &dpaa_fq[0]; 727 728 if (!dpaa_fq_alloc(dev, 0, DPAA_ETH_TXQ_NUM, list, FQ_TYPE_TX_CONF_MQ)) 729 goto fq_alloc_failed; 730 731 dpaa_fq = dpaa_fq_alloc(dev, 0, 1, list, FQ_TYPE_TX_ERROR); 732 if (!dpaa_fq) 733 goto fq_alloc_failed; 734 735 port_fqs->tx_errq = &dpaa_fq[0]; 736 737 dpaa_fq = dpaa_fq_alloc(dev, 0, 1, list, FQ_TYPE_TX_CONFIRM); 738 if (!dpaa_fq) 739 goto fq_alloc_failed; 740 741 port_fqs->tx_defq = &dpaa_fq[0]; 742 743 if (!dpaa_fq_alloc(dev, 0, DPAA_ETH_TXQ_NUM, list, FQ_TYPE_TX)) 744 goto fq_alloc_failed; 745 746 return 0; 747 748 fq_alloc_failed: 749 dev_err(dev, "dpaa_fq_alloc() failed\n"); 750 return -ENOMEM; 751 } 752 753 static u32 rx_pool_channel; 754 static DEFINE_SPINLOCK(rx_pool_channel_init); 755 756 static int dpaa_get_channel(void) 757 { 758 spin_lock(&rx_pool_channel_init); 759 if (!rx_pool_channel) { 760 u32 pool; 761 int ret; 762 763 ret = qman_alloc_pool(&pool); 764 765 if (!ret) 766 rx_pool_channel = pool; 767 } 768 spin_unlock(&rx_pool_channel_init); 769 if (!rx_pool_channel) 770 return -ENOMEM; 771 return rx_pool_channel; 772 } 773 774 static void dpaa_release_channel(void) 775 { 776 qman_release_pool(rx_pool_channel); 777 } 778 779 static void dpaa_eth_add_channel(u16 channel, struct device *dev) 780 { 781 u32 pool = QM_SDQCR_CHANNELS_POOL_CONV(channel); 782 const cpumask_t *cpus = qman_affine_cpus(); 783 struct qman_portal *portal; 784 int cpu; 785 786 for_each_cpu_and(cpu, cpus, cpu_online_mask) { 787 portal = qman_get_affine_portal(cpu); 788 qman_p_static_dequeue_add(portal, pool); 789 qman_start_using_portal(portal, dev); 790 } 791 } 792 793 /* Congestion group state change notification callback. 794 * Stops the device's egress queues while they are congested and 795 * wakes them upon exiting congested state. 796 * Also updates some CGR-related stats. 797 */ 798 static void dpaa_eth_cgscn(struct qman_portal *qm, struct qman_cgr *cgr, 799 int congested) 800 { 801 struct dpaa_priv *priv = (struct dpaa_priv *)container_of(cgr, 802 struct dpaa_priv, cgr_data.cgr); 803 804 if (congested) { 805 priv->cgr_data.congestion_start_jiffies = jiffies; 806 netif_tx_stop_all_queues(priv->net_dev); 807 priv->cgr_data.cgr_congested_count++; 808 } else { 809 priv->cgr_data.congested_jiffies += 810 (jiffies - priv->cgr_data.congestion_start_jiffies); 811 netif_tx_wake_all_queues(priv->net_dev); 812 } 813 } 814 815 static int dpaa_eth_cgr_init(struct dpaa_priv *priv) 816 { 817 struct qm_mcc_initcgr initcgr; 818 u32 cs_th; 819 int err; 820 821 err = qman_alloc_cgrid(&priv->cgr_data.cgr.cgrid); 822 if (err < 0) { 823 if (netif_msg_drv(priv)) 824 pr_err("%s: Error %d allocating CGR ID\n", 825 __func__, err); 826 goto out_error; 827 } 828 priv->cgr_data.cgr.cb = dpaa_eth_cgscn; 829 830 /* Enable Congestion State Change Notifications and CS taildrop */ 831 memset(&initcgr, 0, sizeof(initcgr)); 832 initcgr.we_mask = cpu_to_be16(QM_CGR_WE_CSCN_EN | QM_CGR_WE_CS_THRES); 833 initcgr.cgr.cscn_en = QM_CGR_EN; 834 835 /* Set different thresholds based on the MAC speed. 836 * This may turn suboptimal if the MAC is reconfigured at a speed 837 * lower than its max, e.g. if a dTSEC later negotiates a 100Mbps link. 838 * In such cases, we ought to reconfigure the threshold, too. 839 */ 840 if (priv->mac_dev->if_support & SUPPORTED_10000baseT_Full) 841 cs_th = DPAA_CS_THRESHOLD_10G; 842 else 843 cs_th = DPAA_CS_THRESHOLD_1G; 844 qm_cgr_cs_thres_set64(&initcgr.cgr.cs_thres, cs_th, 1); 845 846 initcgr.we_mask |= cpu_to_be16(QM_CGR_WE_CSTD_EN); 847 initcgr.cgr.cstd_en = QM_CGR_EN; 848 849 err = qman_create_cgr(&priv->cgr_data.cgr, QMAN_CGR_FLAG_USE_INIT, 850 &initcgr); 851 if (err < 0) { 852 if (netif_msg_drv(priv)) 853 pr_err("%s: Error %d creating CGR with ID %d\n", 854 __func__, err, priv->cgr_data.cgr.cgrid); 855 qman_release_cgrid(priv->cgr_data.cgr.cgrid); 856 goto out_error; 857 } 858 if (netif_msg_drv(priv)) 859 pr_debug("Created CGR %d for netdev with hwaddr %pM on QMan channel %d\n", 860 priv->cgr_data.cgr.cgrid, priv->mac_dev->addr, 861 priv->cgr_data.cgr.chan); 862 863 out_error: 864 return err; 865 } 866 867 static inline void dpaa_setup_ingress(const struct dpaa_priv *priv, 868 struct dpaa_fq *fq, 869 const struct qman_fq *template) 870 { 871 fq->fq_base = *template; 872 fq->net_dev = priv->net_dev; 873 874 fq->flags = QMAN_FQ_FLAG_NO_ENQUEUE; 875 fq->channel = priv->channel; 876 } 877 878 static inline void dpaa_setup_egress(const struct dpaa_priv *priv, 879 struct dpaa_fq *fq, 880 struct fman_port *port, 881 const struct qman_fq *template) 882 { 883 fq->fq_base = *template; 884 fq->net_dev = priv->net_dev; 885 886 if (port) { 887 fq->flags = QMAN_FQ_FLAG_TO_DCPORTAL; 888 fq->channel = (u16)fman_port_get_qman_channel_id(port); 889 } else { 890 fq->flags = QMAN_FQ_FLAG_NO_MODIFY; 891 } 892 } 893 894 static void dpaa_fq_setup(struct dpaa_priv *priv, 895 const struct dpaa_fq_cbs *fq_cbs, 896 struct fman_port *tx_port) 897 { 898 int egress_cnt = 0, conf_cnt = 0, num_portals = 0, portal_cnt = 0, cpu; 899 const cpumask_t *affine_cpus = qman_affine_cpus(); 900 u16 channels[NR_CPUS]; 901 struct dpaa_fq *fq; 902 903 for_each_cpu_and(cpu, affine_cpus, cpu_online_mask) 904 channels[num_portals++] = qman_affine_channel(cpu); 905 906 if (num_portals == 0) 907 dev_err(priv->net_dev->dev.parent, 908 "No Qman software (affine) channels found\n"); 909 910 /* Initialize each FQ in the list */ 911 list_for_each_entry(fq, &priv->dpaa_fq_list, list) { 912 switch (fq->fq_type) { 913 case FQ_TYPE_RX_DEFAULT: 914 dpaa_setup_ingress(priv, fq, &fq_cbs->rx_defq); 915 break; 916 case FQ_TYPE_RX_ERROR: 917 dpaa_setup_ingress(priv, fq, &fq_cbs->rx_errq); 918 break; 919 case FQ_TYPE_RX_PCD: 920 if (!num_portals) 921 continue; 922 dpaa_setup_ingress(priv, fq, &fq_cbs->rx_defq); 923 fq->channel = channels[portal_cnt++ % num_portals]; 924 break; 925 case FQ_TYPE_TX: 926 dpaa_setup_egress(priv, fq, tx_port, 927 &fq_cbs->egress_ern); 928 /* If we have more Tx queues than the number of cores, 929 * just ignore the extra ones. 930 */ 931 if (egress_cnt < DPAA_ETH_TXQ_NUM) 932 priv->egress_fqs[egress_cnt++] = &fq->fq_base; 933 break; 934 case FQ_TYPE_TX_CONF_MQ: 935 priv->conf_fqs[conf_cnt++] = &fq->fq_base; 936 /* fall through */ 937 case FQ_TYPE_TX_CONFIRM: 938 dpaa_setup_ingress(priv, fq, &fq_cbs->tx_defq); 939 break; 940 case FQ_TYPE_TX_ERROR: 941 dpaa_setup_ingress(priv, fq, &fq_cbs->tx_errq); 942 break; 943 default: 944 dev_warn(priv->net_dev->dev.parent, 945 "Unknown FQ type detected!\n"); 946 break; 947 } 948 } 949 950 /* Make sure all CPUs receive a corresponding Tx queue. */ 951 while (egress_cnt < DPAA_ETH_TXQ_NUM) { 952 list_for_each_entry(fq, &priv->dpaa_fq_list, list) { 953 if (fq->fq_type != FQ_TYPE_TX) 954 continue; 955 priv->egress_fqs[egress_cnt++] = &fq->fq_base; 956 if (egress_cnt == DPAA_ETH_TXQ_NUM) 957 break; 958 } 959 } 960 } 961 962 static inline int dpaa_tx_fq_to_id(const struct dpaa_priv *priv, 963 struct qman_fq *tx_fq) 964 { 965 int i; 966 967 for (i = 0; i < DPAA_ETH_TXQ_NUM; i++) 968 if (priv->egress_fqs[i] == tx_fq) 969 return i; 970 971 return -EINVAL; 972 } 973 974 static int dpaa_fq_init(struct dpaa_fq *dpaa_fq, bool td_enable) 975 { 976 const struct dpaa_priv *priv; 977 struct qman_fq *confq = NULL; 978 struct qm_mcc_initfq initfq; 979 struct device *dev; 980 struct qman_fq *fq; 981 int queue_id; 982 int err; 983 984 priv = netdev_priv(dpaa_fq->net_dev); 985 dev = dpaa_fq->net_dev->dev.parent; 986 987 if (dpaa_fq->fqid == 0) 988 dpaa_fq->flags |= QMAN_FQ_FLAG_DYNAMIC_FQID; 989 990 dpaa_fq->init = !(dpaa_fq->flags & QMAN_FQ_FLAG_NO_MODIFY); 991 992 err = qman_create_fq(dpaa_fq->fqid, dpaa_fq->flags, &dpaa_fq->fq_base); 993 if (err) { 994 dev_err(dev, "qman_create_fq() failed\n"); 995 return err; 996 } 997 fq = &dpaa_fq->fq_base; 998 999 if (dpaa_fq->init) { 1000 memset(&initfq, 0, sizeof(initfq)); 1001 1002 initfq.we_mask = cpu_to_be16(QM_INITFQ_WE_FQCTRL); 1003 /* Note: we may get to keep an empty FQ in cache */ 1004 initfq.fqd.fq_ctrl = cpu_to_be16(QM_FQCTRL_PREFERINCACHE); 1005 1006 /* Try to reduce the number of portal interrupts for 1007 * Tx Confirmation FQs. 1008 */ 1009 if (dpaa_fq->fq_type == FQ_TYPE_TX_CONFIRM) 1010 initfq.fqd.fq_ctrl |= cpu_to_be16(QM_FQCTRL_AVOIDBLOCK); 1011 1012 /* FQ placement */ 1013 initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_DESTWQ); 1014 1015 qm_fqd_set_destwq(&initfq.fqd, dpaa_fq->channel, dpaa_fq->wq); 1016 1017 /* Put all egress queues in a congestion group of their own. 1018 * Sensu stricto, the Tx confirmation queues are Rx FQs, 1019 * rather than Tx - but they nonetheless account for the 1020 * memory footprint on behalf of egress traffic. We therefore 1021 * place them in the netdev's CGR, along with the Tx FQs. 1022 */ 1023 if (dpaa_fq->fq_type == FQ_TYPE_TX || 1024 dpaa_fq->fq_type == FQ_TYPE_TX_CONFIRM || 1025 dpaa_fq->fq_type == FQ_TYPE_TX_CONF_MQ) { 1026 initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_CGID); 1027 initfq.fqd.fq_ctrl |= cpu_to_be16(QM_FQCTRL_CGE); 1028 initfq.fqd.cgid = (u8)priv->cgr_data.cgr.cgrid; 1029 /* Set a fixed overhead accounting, in an attempt to 1030 * reduce the impact of fixed-size skb shells and the 1031 * driver's needed headroom on system memory. This is 1032 * especially the case when the egress traffic is 1033 * composed of small datagrams. 1034 * Unfortunately, QMan's OAL value is capped to an 1035 * insufficient value, but even that is better than 1036 * no overhead accounting at all. 1037 */ 1038 initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_OAC); 1039 qm_fqd_set_oac(&initfq.fqd, QM_OAC_CG); 1040 qm_fqd_set_oal(&initfq.fqd, 1041 min(sizeof(struct sk_buff) + 1042 priv->tx_headroom, 1043 (size_t)FSL_QMAN_MAX_OAL)); 1044 } 1045 1046 if (td_enable) { 1047 initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_TDTHRESH); 1048 qm_fqd_set_taildrop(&initfq.fqd, DPAA_FQ_TD, 1); 1049 initfq.fqd.fq_ctrl = cpu_to_be16(QM_FQCTRL_TDE); 1050 } 1051 1052 if (dpaa_fq->fq_type == FQ_TYPE_TX) { 1053 queue_id = dpaa_tx_fq_to_id(priv, &dpaa_fq->fq_base); 1054 if (queue_id >= 0) 1055 confq = priv->conf_fqs[queue_id]; 1056 if (confq) { 1057 initfq.we_mask |= 1058 cpu_to_be16(QM_INITFQ_WE_CONTEXTA); 1059 /* ContextA: OVOM=1(use contextA2 bits instead of ICAD) 1060 * A2V=1 (contextA A2 field is valid) 1061 * A0V=1 (contextA A0 field is valid) 1062 * B0V=1 (contextB field is valid) 1063 * ContextA A2: EBD=1 (deallocate buffers inside FMan) 1064 * ContextB B0(ASPID): 0 (absolute Virtual Storage ID) 1065 */ 1066 qm_fqd_context_a_set64(&initfq.fqd, 1067 0x1e00000080000000ULL); 1068 } 1069 } 1070 1071 /* Put all the ingress queues in our "ingress CGR". */ 1072 if (priv->use_ingress_cgr && 1073 (dpaa_fq->fq_type == FQ_TYPE_RX_DEFAULT || 1074 dpaa_fq->fq_type == FQ_TYPE_RX_ERROR || 1075 dpaa_fq->fq_type == FQ_TYPE_RX_PCD)) { 1076 initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_CGID); 1077 initfq.fqd.fq_ctrl |= cpu_to_be16(QM_FQCTRL_CGE); 1078 initfq.fqd.cgid = (u8)priv->ingress_cgr.cgrid; 1079 /* Set a fixed overhead accounting, just like for the 1080 * egress CGR. 1081 */ 1082 initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_OAC); 1083 qm_fqd_set_oac(&initfq.fqd, QM_OAC_CG); 1084 qm_fqd_set_oal(&initfq.fqd, 1085 min(sizeof(struct sk_buff) + 1086 priv->tx_headroom, 1087 (size_t)FSL_QMAN_MAX_OAL)); 1088 } 1089 1090 /* Initialization common to all ingress queues */ 1091 if (dpaa_fq->flags & QMAN_FQ_FLAG_NO_ENQUEUE) { 1092 initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_CONTEXTA); 1093 initfq.fqd.fq_ctrl |= cpu_to_be16(QM_FQCTRL_HOLDACTIVE | 1094 QM_FQCTRL_CTXASTASHING); 1095 initfq.fqd.context_a.stashing.exclusive = 1096 QM_STASHING_EXCL_DATA | QM_STASHING_EXCL_CTX | 1097 QM_STASHING_EXCL_ANNOTATION; 1098 qm_fqd_set_stashing(&initfq.fqd, 1, 2, 1099 DIV_ROUND_UP(sizeof(struct qman_fq), 1100 64)); 1101 } 1102 1103 err = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &initfq); 1104 if (err < 0) { 1105 dev_err(dev, "qman_init_fq(%u) = %d\n", 1106 qman_fq_fqid(fq), err); 1107 qman_destroy_fq(fq); 1108 return err; 1109 } 1110 } 1111 1112 dpaa_fq->fqid = qman_fq_fqid(fq); 1113 1114 return 0; 1115 } 1116 1117 static int dpaa_fq_free_entry(struct device *dev, struct qman_fq *fq) 1118 { 1119 const struct dpaa_priv *priv; 1120 struct dpaa_fq *dpaa_fq; 1121 int err, error; 1122 1123 err = 0; 1124 1125 dpaa_fq = container_of(fq, struct dpaa_fq, fq_base); 1126 priv = netdev_priv(dpaa_fq->net_dev); 1127 1128 if (dpaa_fq->init) { 1129 err = qman_retire_fq(fq, NULL); 1130 if (err < 0 && netif_msg_drv(priv)) 1131 dev_err(dev, "qman_retire_fq(%u) = %d\n", 1132 qman_fq_fqid(fq), err); 1133 1134 error = qman_oos_fq(fq); 1135 if (error < 0 && netif_msg_drv(priv)) { 1136 dev_err(dev, "qman_oos_fq(%u) = %d\n", 1137 qman_fq_fqid(fq), error); 1138 if (err >= 0) 1139 err = error; 1140 } 1141 } 1142 1143 qman_destroy_fq(fq); 1144 list_del(&dpaa_fq->list); 1145 1146 return err; 1147 } 1148 1149 static int dpaa_fq_free(struct device *dev, struct list_head *list) 1150 { 1151 struct dpaa_fq *dpaa_fq, *tmp; 1152 int err, error; 1153 1154 err = 0; 1155 list_for_each_entry_safe(dpaa_fq, tmp, list, list) { 1156 error = dpaa_fq_free_entry(dev, (struct qman_fq *)dpaa_fq); 1157 if (error < 0 && err >= 0) 1158 err = error; 1159 } 1160 1161 return err; 1162 } 1163 1164 static int dpaa_eth_init_tx_port(struct fman_port *port, struct dpaa_fq *errq, 1165 struct dpaa_fq *defq, 1166 struct dpaa_buffer_layout *buf_layout) 1167 { 1168 struct fman_buffer_prefix_content buf_prefix_content; 1169 struct fman_port_params params; 1170 int err; 1171 1172 memset(¶ms, 0, sizeof(params)); 1173 memset(&buf_prefix_content, 0, sizeof(buf_prefix_content)); 1174 1175 buf_prefix_content.priv_data_size = buf_layout->priv_data_size; 1176 buf_prefix_content.pass_prs_result = true; 1177 buf_prefix_content.pass_hash_result = true; 1178 buf_prefix_content.pass_time_stamp = true; 1179 buf_prefix_content.data_align = DPAA_FD_DATA_ALIGNMENT; 1180 1181 params.specific_params.non_rx_params.err_fqid = errq->fqid; 1182 params.specific_params.non_rx_params.dflt_fqid = defq->fqid; 1183 1184 err = fman_port_config(port, ¶ms); 1185 if (err) { 1186 pr_err("%s: fman_port_config failed\n", __func__); 1187 return err; 1188 } 1189 1190 err = fman_port_cfg_buf_prefix_content(port, &buf_prefix_content); 1191 if (err) { 1192 pr_err("%s: fman_port_cfg_buf_prefix_content failed\n", 1193 __func__); 1194 return err; 1195 } 1196 1197 err = fman_port_init(port); 1198 if (err) 1199 pr_err("%s: fm_port_init failed\n", __func__); 1200 1201 return err; 1202 } 1203 1204 static int dpaa_eth_init_rx_port(struct fman_port *port, struct dpaa_bp *bp, 1205 struct dpaa_fq *errq, 1206 struct dpaa_fq *defq, struct dpaa_fq *pcdq, 1207 struct dpaa_buffer_layout *buf_layout) 1208 { 1209 struct fman_buffer_prefix_content buf_prefix_content; 1210 struct fman_port_rx_params *rx_p; 1211 struct fman_port_params params; 1212 int err; 1213 1214 memset(¶ms, 0, sizeof(params)); 1215 memset(&buf_prefix_content, 0, sizeof(buf_prefix_content)); 1216 1217 buf_prefix_content.priv_data_size = buf_layout->priv_data_size; 1218 buf_prefix_content.pass_prs_result = true; 1219 buf_prefix_content.pass_hash_result = true; 1220 buf_prefix_content.pass_time_stamp = true; 1221 buf_prefix_content.data_align = DPAA_FD_RX_DATA_ALIGNMENT; 1222 1223 rx_p = ¶ms.specific_params.rx_params; 1224 rx_p->err_fqid = errq->fqid; 1225 rx_p->dflt_fqid = defq->fqid; 1226 if (pcdq) { 1227 rx_p->pcd_base_fqid = pcdq->fqid; 1228 rx_p->pcd_fqs_count = DPAA_ETH_PCD_RXQ_NUM; 1229 } 1230 1231 rx_p->ext_buf_pools.num_of_pools_used = 1; 1232 rx_p->ext_buf_pools.ext_buf_pool[0].id = bp->bpid; 1233 rx_p->ext_buf_pools.ext_buf_pool[0].size = (u16)bp->size; 1234 1235 err = fman_port_config(port, ¶ms); 1236 if (err) { 1237 pr_err("%s: fman_port_config failed\n", __func__); 1238 return err; 1239 } 1240 1241 err = fman_port_cfg_buf_prefix_content(port, &buf_prefix_content); 1242 if (err) { 1243 pr_err("%s: fman_port_cfg_buf_prefix_content failed\n", 1244 __func__); 1245 return err; 1246 } 1247 1248 err = fman_port_init(port); 1249 if (err) 1250 pr_err("%s: fm_port_init failed\n", __func__); 1251 1252 return err; 1253 } 1254 1255 static int dpaa_eth_init_ports(struct mac_device *mac_dev, 1256 struct dpaa_bp *bp, 1257 struct fm_port_fqs *port_fqs, 1258 struct dpaa_buffer_layout *buf_layout, 1259 struct device *dev) 1260 { 1261 struct fman_port *rxport = mac_dev->port[RX]; 1262 struct fman_port *txport = mac_dev->port[TX]; 1263 int err; 1264 1265 err = dpaa_eth_init_tx_port(txport, port_fqs->tx_errq, 1266 port_fqs->tx_defq, &buf_layout[TX]); 1267 if (err) 1268 return err; 1269 1270 err = dpaa_eth_init_rx_port(rxport, bp, port_fqs->rx_errq, 1271 port_fqs->rx_defq, port_fqs->rx_pcdq, 1272 &buf_layout[RX]); 1273 1274 return err; 1275 } 1276 1277 static int dpaa_bman_release(const struct dpaa_bp *dpaa_bp, 1278 struct bm_buffer *bmb, int cnt) 1279 { 1280 int err; 1281 1282 err = bman_release(dpaa_bp->pool, bmb, cnt); 1283 /* Should never occur, address anyway to avoid leaking the buffers */ 1284 if (WARN_ON(err) && dpaa_bp->free_buf_cb) 1285 while (cnt-- > 0) 1286 dpaa_bp->free_buf_cb(dpaa_bp, &bmb[cnt]); 1287 1288 return cnt; 1289 } 1290 1291 static void dpaa_release_sgt_members(struct qm_sg_entry *sgt) 1292 { 1293 struct bm_buffer bmb[DPAA_BUFF_RELEASE_MAX]; 1294 struct dpaa_bp *dpaa_bp; 1295 int i = 0, j; 1296 1297 memset(bmb, 0, sizeof(bmb)); 1298 1299 do { 1300 dpaa_bp = dpaa_bpid2pool(sgt[i].bpid); 1301 if (!dpaa_bp) 1302 return; 1303 1304 j = 0; 1305 do { 1306 WARN_ON(qm_sg_entry_is_ext(&sgt[i])); 1307 1308 bm_buffer_set64(&bmb[j], qm_sg_entry_get64(&sgt[i])); 1309 1310 j++; i++; 1311 } while (j < ARRAY_SIZE(bmb) && 1312 !qm_sg_entry_is_final(&sgt[i - 1]) && 1313 sgt[i - 1].bpid == sgt[i].bpid); 1314 1315 dpaa_bman_release(dpaa_bp, bmb, j); 1316 } while (!qm_sg_entry_is_final(&sgt[i - 1])); 1317 } 1318 1319 static void dpaa_fd_release(const struct net_device *net_dev, 1320 const struct qm_fd *fd) 1321 { 1322 struct qm_sg_entry *sgt; 1323 struct dpaa_bp *dpaa_bp; 1324 struct bm_buffer bmb; 1325 dma_addr_t addr; 1326 void *vaddr; 1327 1328 bmb.data = 0; 1329 bm_buffer_set64(&bmb, qm_fd_addr(fd)); 1330 1331 dpaa_bp = dpaa_bpid2pool(fd->bpid); 1332 if (!dpaa_bp) 1333 return; 1334 1335 if (qm_fd_get_format(fd) == qm_fd_sg) { 1336 vaddr = phys_to_virt(qm_fd_addr(fd)); 1337 sgt = vaddr + qm_fd_get_offset(fd); 1338 1339 dma_unmap_page(dpaa_bp->priv->rx_dma_dev, qm_fd_addr(fd), 1340 DPAA_BP_RAW_SIZE, DMA_FROM_DEVICE); 1341 1342 dpaa_release_sgt_members(sgt); 1343 1344 addr = dma_map_page(dpaa_bp->priv->rx_dma_dev, 1345 virt_to_page(vaddr), 0, DPAA_BP_RAW_SIZE, 1346 DMA_FROM_DEVICE); 1347 if (dma_mapping_error(dpaa_bp->priv->rx_dma_dev, addr)) { 1348 netdev_err(net_dev, "DMA mapping failed\n"); 1349 return; 1350 } 1351 bm_buffer_set64(&bmb, addr); 1352 } 1353 1354 dpaa_bman_release(dpaa_bp, &bmb, 1); 1355 } 1356 1357 static void count_ern(struct dpaa_percpu_priv *percpu_priv, 1358 const union qm_mr_entry *msg) 1359 { 1360 switch (msg->ern.rc & QM_MR_RC_MASK) { 1361 case QM_MR_RC_CGR_TAILDROP: 1362 percpu_priv->ern_cnt.cg_tdrop++; 1363 break; 1364 case QM_MR_RC_WRED: 1365 percpu_priv->ern_cnt.wred++; 1366 break; 1367 case QM_MR_RC_ERROR: 1368 percpu_priv->ern_cnt.err_cond++; 1369 break; 1370 case QM_MR_RC_ORPWINDOW_EARLY: 1371 percpu_priv->ern_cnt.early_window++; 1372 break; 1373 case QM_MR_RC_ORPWINDOW_LATE: 1374 percpu_priv->ern_cnt.late_window++; 1375 break; 1376 case QM_MR_RC_FQ_TAILDROP: 1377 percpu_priv->ern_cnt.fq_tdrop++; 1378 break; 1379 case QM_MR_RC_ORPWINDOW_RETIRED: 1380 percpu_priv->ern_cnt.fq_retired++; 1381 break; 1382 case QM_MR_RC_ORP_ZERO: 1383 percpu_priv->ern_cnt.orp_zero++; 1384 break; 1385 } 1386 } 1387 1388 /* Turn on HW checksum computation for this outgoing frame. 1389 * If the current protocol is not something we support in this regard 1390 * (or if the stack has already computed the SW checksum), we do nothing. 1391 * 1392 * Returns 0 if all goes well (or HW csum doesn't apply), and a negative value 1393 * otherwise. 1394 * 1395 * Note that this function may modify the fd->cmd field and the skb data buffer 1396 * (the Parse Results area). 1397 */ 1398 static int dpaa_enable_tx_csum(struct dpaa_priv *priv, 1399 struct sk_buff *skb, 1400 struct qm_fd *fd, 1401 void *parse_results) 1402 { 1403 struct fman_prs_result *parse_result; 1404 u16 ethertype = ntohs(skb->protocol); 1405 struct ipv6hdr *ipv6h = NULL; 1406 struct iphdr *iph; 1407 int retval = 0; 1408 u8 l4_proto; 1409 1410 if (skb->ip_summed != CHECKSUM_PARTIAL) 1411 return 0; 1412 1413 /* Note: L3 csum seems to be already computed in sw, but we can't choose 1414 * L4 alone from the FM configuration anyway. 1415 */ 1416 1417 /* Fill in some fields of the Parse Results array, so the FMan 1418 * can find them as if they came from the FMan Parser. 1419 */ 1420 parse_result = (struct fman_prs_result *)parse_results; 1421 1422 /* If we're dealing with VLAN, get the real Ethernet type */ 1423 if (ethertype == ETH_P_8021Q) { 1424 /* We can't always assume the MAC header is set correctly 1425 * by the stack, so reset to beginning of skb->data 1426 */ 1427 skb_reset_mac_header(skb); 1428 ethertype = ntohs(vlan_eth_hdr(skb)->h_vlan_encapsulated_proto); 1429 } 1430 1431 /* Fill in the relevant L3 parse result fields 1432 * and read the L4 protocol type 1433 */ 1434 switch (ethertype) { 1435 case ETH_P_IP: 1436 parse_result->l3r = cpu_to_be16(FM_L3_PARSE_RESULT_IPV4); 1437 iph = ip_hdr(skb); 1438 WARN_ON(!iph); 1439 l4_proto = iph->protocol; 1440 break; 1441 case ETH_P_IPV6: 1442 parse_result->l3r = cpu_to_be16(FM_L3_PARSE_RESULT_IPV6); 1443 ipv6h = ipv6_hdr(skb); 1444 WARN_ON(!ipv6h); 1445 l4_proto = ipv6h->nexthdr; 1446 break; 1447 default: 1448 /* We shouldn't even be here */ 1449 if (net_ratelimit()) 1450 netif_alert(priv, tx_err, priv->net_dev, 1451 "Can't compute HW csum for L3 proto 0x%x\n", 1452 ntohs(skb->protocol)); 1453 retval = -EIO; 1454 goto return_error; 1455 } 1456 1457 /* Fill in the relevant L4 parse result fields */ 1458 switch (l4_proto) { 1459 case IPPROTO_UDP: 1460 parse_result->l4r = FM_L4_PARSE_RESULT_UDP; 1461 break; 1462 case IPPROTO_TCP: 1463 parse_result->l4r = FM_L4_PARSE_RESULT_TCP; 1464 break; 1465 default: 1466 if (net_ratelimit()) 1467 netif_alert(priv, tx_err, priv->net_dev, 1468 "Can't compute HW csum for L4 proto 0x%x\n", 1469 l4_proto); 1470 retval = -EIO; 1471 goto return_error; 1472 } 1473 1474 /* At index 0 is IPOffset_1 as defined in the Parse Results */ 1475 parse_result->ip_off[0] = (u8)skb_network_offset(skb); 1476 parse_result->l4_off = (u8)skb_transport_offset(skb); 1477 1478 /* Enable L3 (and L4, if TCP or UDP) HW checksum. */ 1479 fd->cmd |= cpu_to_be32(FM_FD_CMD_RPD | FM_FD_CMD_DTC); 1480 1481 /* On P1023 and similar platforms fd->cmd interpretation could 1482 * be disabled by setting CONTEXT_A bit ICMD; currently this bit 1483 * is not set so we do not need to check; in the future, if/when 1484 * using context_a we need to check this bit 1485 */ 1486 1487 return_error: 1488 return retval; 1489 } 1490 1491 static int dpaa_bp_add_8_bufs(const struct dpaa_bp *dpaa_bp) 1492 { 1493 struct net_device *net_dev = dpaa_bp->priv->net_dev; 1494 struct bm_buffer bmb[8]; 1495 dma_addr_t addr; 1496 struct page *p; 1497 u8 i; 1498 1499 for (i = 0; i < 8; i++) { 1500 p = dev_alloc_pages(0); 1501 if (unlikely(!p)) { 1502 netdev_err(net_dev, "dev_alloc_pages() failed\n"); 1503 goto release_previous_buffs; 1504 } 1505 1506 addr = dma_map_page(dpaa_bp->priv->rx_dma_dev, p, 0, 1507 DPAA_BP_RAW_SIZE, DMA_FROM_DEVICE); 1508 if (unlikely(dma_mapping_error(dpaa_bp->priv->rx_dma_dev, 1509 addr))) { 1510 netdev_err(net_dev, "DMA map failed\n"); 1511 goto release_previous_buffs; 1512 } 1513 1514 bmb[i].data = 0; 1515 bm_buffer_set64(&bmb[i], addr); 1516 } 1517 1518 release_bufs: 1519 return dpaa_bman_release(dpaa_bp, bmb, i); 1520 1521 release_previous_buffs: 1522 WARN_ONCE(1, "dpaa_eth: failed to add buffers on Rx\n"); 1523 1524 bm_buffer_set64(&bmb[i], 0); 1525 /* Avoid releasing a completely null buffer; bman_release() requires 1526 * at least one buffer. 1527 */ 1528 if (likely(i)) 1529 goto release_bufs; 1530 1531 return 0; 1532 } 1533 1534 static int dpaa_bp_seed(struct dpaa_bp *dpaa_bp) 1535 { 1536 int i; 1537 1538 /* Give each CPU an allotment of "config_count" buffers */ 1539 for_each_possible_cpu(i) { 1540 int *count_ptr = per_cpu_ptr(dpaa_bp->percpu_count, i); 1541 int j; 1542 1543 /* Although we access another CPU's counters here 1544 * we do it at boot time so it is safe 1545 */ 1546 for (j = 0; j < dpaa_bp->config_count; j += 8) 1547 *count_ptr += dpaa_bp_add_8_bufs(dpaa_bp); 1548 } 1549 return 0; 1550 } 1551 1552 /* Add buffers/(pages) for Rx processing whenever bpool count falls below 1553 * REFILL_THRESHOLD. 1554 */ 1555 static int dpaa_eth_refill_bpool(struct dpaa_bp *dpaa_bp, int *countptr) 1556 { 1557 int count = *countptr; 1558 int new_bufs; 1559 1560 if (unlikely(count < FSL_DPAA_ETH_REFILL_THRESHOLD)) { 1561 do { 1562 new_bufs = dpaa_bp_add_8_bufs(dpaa_bp); 1563 if (unlikely(!new_bufs)) { 1564 /* Avoid looping forever if we've temporarily 1565 * run out of memory. We'll try again at the 1566 * next NAPI cycle. 1567 */ 1568 break; 1569 } 1570 count += new_bufs; 1571 } while (count < FSL_DPAA_ETH_MAX_BUF_COUNT); 1572 1573 *countptr = count; 1574 if (unlikely(count < FSL_DPAA_ETH_MAX_BUF_COUNT)) 1575 return -ENOMEM; 1576 } 1577 1578 return 0; 1579 } 1580 1581 static int dpaa_eth_refill_bpools(struct dpaa_priv *priv) 1582 { 1583 struct dpaa_bp *dpaa_bp; 1584 int *countptr; 1585 int res; 1586 1587 dpaa_bp = priv->dpaa_bp; 1588 if (!dpaa_bp) 1589 return -EINVAL; 1590 countptr = this_cpu_ptr(dpaa_bp->percpu_count); 1591 res = dpaa_eth_refill_bpool(dpaa_bp, countptr); 1592 if (res) 1593 return res; 1594 1595 return 0; 1596 } 1597 1598 /* Cleanup function for outgoing frame descriptors that were built on Tx path, 1599 * either contiguous frames or scatter/gather ones. 1600 * Skb freeing is not handled here. 1601 * 1602 * This function may be called on error paths in the Tx function, so guard 1603 * against cases when not all fd relevant fields were filled in. To avoid 1604 * reading the invalid transmission timestamp for the error paths set ts to 1605 * false. 1606 * 1607 * Return the skb backpointer, since for S/G frames the buffer containing it 1608 * gets freed here. 1609 */ 1610 static struct sk_buff *dpaa_cleanup_tx_fd(const struct dpaa_priv *priv, 1611 const struct qm_fd *fd, bool ts) 1612 { 1613 const enum dma_data_direction dma_dir = DMA_TO_DEVICE; 1614 struct device *dev = priv->net_dev->dev.parent; 1615 struct skb_shared_hwtstamps shhwtstamps; 1616 dma_addr_t addr = qm_fd_addr(fd); 1617 void *vaddr = phys_to_virt(addr); 1618 const struct qm_sg_entry *sgt; 1619 struct sk_buff *skb; 1620 u64 ns; 1621 int i; 1622 1623 if (unlikely(qm_fd_get_format(fd) == qm_fd_sg)) { 1624 dma_unmap_page(priv->tx_dma_dev, addr, 1625 qm_fd_get_offset(fd) + DPAA_SGT_SIZE, 1626 dma_dir); 1627 1628 /* The sgt buffer has been allocated with netdev_alloc_frag(), 1629 * it's from lowmem. 1630 */ 1631 sgt = vaddr + qm_fd_get_offset(fd); 1632 1633 /* sgt[0] is from lowmem, was dma_map_single()-ed */ 1634 dma_unmap_single(priv->tx_dma_dev, qm_sg_addr(&sgt[0]), 1635 qm_sg_entry_get_len(&sgt[0]), dma_dir); 1636 1637 /* remaining pages were mapped with skb_frag_dma_map() */ 1638 for (i = 1; (i < DPAA_SGT_MAX_ENTRIES) && 1639 !qm_sg_entry_is_final(&sgt[i - 1]); i++) { 1640 WARN_ON(qm_sg_entry_is_ext(&sgt[i])); 1641 1642 dma_unmap_page(priv->tx_dma_dev, qm_sg_addr(&sgt[i]), 1643 qm_sg_entry_get_len(&sgt[i]), dma_dir); 1644 } 1645 } else { 1646 dma_unmap_single(priv->tx_dma_dev, addr, 1647 priv->tx_headroom + qm_fd_get_length(fd), 1648 dma_dir); 1649 } 1650 1651 skb = *(struct sk_buff **)vaddr; 1652 1653 /* DMA unmapping is required before accessing the HW provided info */ 1654 if (ts && priv->tx_tstamp && 1655 skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) { 1656 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 1657 1658 if (!fman_port_get_tstamp(priv->mac_dev->port[TX], vaddr, 1659 &ns)) { 1660 shhwtstamps.hwtstamp = ns_to_ktime(ns); 1661 skb_tstamp_tx(skb, &shhwtstamps); 1662 } else { 1663 dev_warn(dev, "fman_port_get_tstamp failed!\n"); 1664 } 1665 } 1666 1667 if (qm_fd_get_format(fd) == qm_fd_sg) 1668 /* Free the page that we allocated on Tx for the SGT */ 1669 free_pages((unsigned long)vaddr, 0); 1670 1671 return skb; 1672 } 1673 1674 static u8 rx_csum_offload(const struct dpaa_priv *priv, const struct qm_fd *fd) 1675 { 1676 /* The parser has run and performed L4 checksum validation. 1677 * We know there were no parser errors (and implicitly no 1678 * L4 csum error), otherwise we wouldn't be here. 1679 */ 1680 if ((priv->net_dev->features & NETIF_F_RXCSUM) && 1681 (be32_to_cpu(fd->status) & FM_FD_STAT_L4CV)) 1682 return CHECKSUM_UNNECESSARY; 1683 1684 /* We're here because either the parser didn't run or the L4 checksum 1685 * was not verified. This may include the case of a UDP frame with 1686 * checksum zero or an L4 proto other than TCP/UDP 1687 */ 1688 return CHECKSUM_NONE; 1689 } 1690 1691 #define PTR_IS_ALIGNED(x, a) (IS_ALIGNED((unsigned long)(x), (a))) 1692 1693 /* Build a linear skb around the received buffer. 1694 * We are guaranteed there is enough room at the end of the data buffer to 1695 * accommodate the shared info area of the skb. 1696 */ 1697 static struct sk_buff *contig_fd_to_skb(const struct dpaa_priv *priv, 1698 const struct qm_fd *fd) 1699 { 1700 ssize_t fd_off = qm_fd_get_offset(fd); 1701 dma_addr_t addr = qm_fd_addr(fd); 1702 struct dpaa_bp *dpaa_bp; 1703 struct sk_buff *skb; 1704 void *vaddr; 1705 1706 vaddr = phys_to_virt(addr); 1707 WARN_ON(!IS_ALIGNED((unsigned long)vaddr, SMP_CACHE_BYTES)); 1708 1709 dpaa_bp = dpaa_bpid2pool(fd->bpid); 1710 if (!dpaa_bp) 1711 goto free_buffer; 1712 1713 skb = build_skb(vaddr, dpaa_bp->size + 1714 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))); 1715 if (WARN_ONCE(!skb, "Build skb failure on Rx\n")) 1716 goto free_buffer; 1717 WARN_ON(fd_off != priv->rx_headroom); 1718 skb_reserve(skb, fd_off); 1719 skb_put(skb, qm_fd_get_length(fd)); 1720 1721 skb->ip_summed = rx_csum_offload(priv, fd); 1722 1723 return skb; 1724 1725 free_buffer: 1726 free_pages((unsigned long)vaddr, 0); 1727 return NULL; 1728 } 1729 1730 /* Build an skb with the data of the first S/G entry in the linear portion and 1731 * the rest of the frame as skb fragments. 1732 * 1733 * The page fragment holding the S/G Table is recycled here. 1734 */ 1735 static struct sk_buff *sg_fd_to_skb(const struct dpaa_priv *priv, 1736 const struct qm_fd *fd) 1737 { 1738 ssize_t fd_off = qm_fd_get_offset(fd); 1739 dma_addr_t addr = qm_fd_addr(fd); 1740 const struct qm_sg_entry *sgt; 1741 struct page *page, *head_page; 1742 struct dpaa_bp *dpaa_bp; 1743 void *vaddr, *sg_vaddr; 1744 int frag_off, frag_len; 1745 struct sk_buff *skb; 1746 dma_addr_t sg_addr; 1747 int page_offset; 1748 unsigned int sz; 1749 int *count_ptr; 1750 int i, j; 1751 1752 vaddr = phys_to_virt(addr); 1753 WARN_ON(!IS_ALIGNED((unsigned long)vaddr, SMP_CACHE_BYTES)); 1754 1755 /* Iterate through the SGT entries and add data buffers to the skb */ 1756 sgt = vaddr + fd_off; 1757 skb = NULL; 1758 for (i = 0; i < DPAA_SGT_MAX_ENTRIES; i++) { 1759 /* Extension bit is not supported */ 1760 WARN_ON(qm_sg_entry_is_ext(&sgt[i])); 1761 1762 sg_addr = qm_sg_addr(&sgt[i]); 1763 sg_vaddr = phys_to_virt(sg_addr); 1764 WARN_ON(!PTR_IS_ALIGNED(sg_vaddr, SMP_CACHE_BYTES)); 1765 1766 dma_unmap_page(priv->rx_dma_dev, sg_addr, 1767 DPAA_BP_RAW_SIZE, DMA_FROM_DEVICE); 1768 1769 /* We may use multiple Rx pools */ 1770 dpaa_bp = dpaa_bpid2pool(sgt[i].bpid); 1771 if (!dpaa_bp) 1772 goto free_buffers; 1773 1774 if (!skb) { 1775 sz = dpaa_bp->size + 1776 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 1777 skb = build_skb(sg_vaddr, sz); 1778 if (WARN_ON(!skb)) 1779 goto free_buffers; 1780 1781 skb->ip_summed = rx_csum_offload(priv, fd); 1782 1783 /* Make sure forwarded skbs will have enough space 1784 * on Tx, if extra headers are added. 1785 */ 1786 WARN_ON(fd_off != priv->rx_headroom); 1787 skb_reserve(skb, fd_off); 1788 skb_put(skb, qm_sg_entry_get_len(&sgt[i])); 1789 } else { 1790 /* Not the first S/G entry; all data from buffer will 1791 * be added in an skb fragment; fragment index is offset 1792 * by one since first S/G entry was incorporated in the 1793 * linear part of the skb. 1794 * 1795 * Caution: 'page' may be a tail page. 1796 */ 1797 page = virt_to_page(sg_vaddr); 1798 head_page = virt_to_head_page(sg_vaddr); 1799 1800 /* Compute offset in (possibly tail) page */ 1801 page_offset = ((unsigned long)sg_vaddr & 1802 (PAGE_SIZE - 1)) + 1803 (page_address(page) - page_address(head_page)); 1804 /* page_offset only refers to the beginning of sgt[i]; 1805 * but the buffer itself may have an internal offset. 1806 */ 1807 frag_off = qm_sg_entry_get_off(&sgt[i]) + page_offset; 1808 frag_len = qm_sg_entry_get_len(&sgt[i]); 1809 /* skb_add_rx_frag() does no checking on the page; if 1810 * we pass it a tail page, we'll end up with 1811 * bad page accounting and eventually with segafults. 1812 */ 1813 skb_add_rx_frag(skb, i - 1, head_page, frag_off, 1814 frag_len, dpaa_bp->size); 1815 } 1816 1817 /* Update the pool count for the current {cpu x bpool} */ 1818 count_ptr = this_cpu_ptr(dpaa_bp->percpu_count); 1819 (*count_ptr)--; 1820 1821 if (qm_sg_entry_is_final(&sgt[i])) 1822 break; 1823 } 1824 WARN_ONCE(i == DPAA_SGT_MAX_ENTRIES, "No final bit on SGT\n"); 1825 1826 /* free the SG table buffer */ 1827 free_pages((unsigned long)vaddr, 0); 1828 1829 return skb; 1830 1831 free_buffers: 1832 /* free all the SG entries */ 1833 for (j = 0; j < DPAA_SGT_MAX_ENTRIES ; j++) { 1834 sg_addr = qm_sg_addr(&sgt[j]); 1835 sg_vaddr = phys_to_virt(sg_addr); 1836 /* all pages 0..i were unmaped */ 1837 if (j > i) 1838 dma_unmap_page(priv->rx_dma_dev, qm_sg_addr(&sgt[j]), 1839 DPAA_BP_RAW_SIZE, DMA_FROM_DEVICE); 1840 free_pages((unsigned long)sg_vaddr, 0); 1841 /* counters 0..i-1 were decremented */ 1842 if (j >= i) { 1843 dpaa_bp = dpaa_bpid2pool(sgt[j].bpid); 1844 if (dpaa_bp) { 1845 count_ptr = this_cpu_ptr(dpaa_bp->percpu_count); 1846 (*count_ptr)--; 1847 } 1848 } 1849 1850 if (qm_sg_entry_is_final(&sgt[j])) 1851 break; 1852 } 1853 /* free the SGT fragment */ 1854 free_pages((unsigned long)vaddr, 0); 1855 1856 return NULL; 1857 } 1858 1859 static int skb_to_contig_fd(struct dpaa_priv *priv, 1860 struct sk_buff *skb, struct qm_fd *fd, 1861 int *offset) 1862 { 1863 struct net_device *net_dev = priv->net_dev; 1864 enum dma_data_direction dma_dir; 1865 unsigned char *buff_start; 1866 struct sk_buff **skbh; 1867 dma_addr_t addr; 1868 int err; 1869 1870 /* We are guaranteed to have at least tx_headroom bytes 1871 * available, so just use that for offset. 1872 */ 1873 fd->bpid = FSL_DPAA_BPID_INV; 1874 buff_start = skb->data - priv->tx_headroom; 1875 dma_dir = DMA_TO_DEVICE; 1876 1877 skbh = (struct sk_buff **)buff_start; 1878 *skbh = skb; 1879 1880 /* Enable L3/L4 hardware checksum computation. 1881 * 1882 * We must do this before dma_map_single(DMA_TO_DEVICE), because we may 1883 * need to write into the skb. 1884 */ 1885 err = dpaa_enable_tx_csum(priv, skb, fd, 1886 buff_start + DPAA_TX_PRIV_DATA_SIZE); 1887 if (unlikely(err < 0)) { 1888 if (net_ratelimit()) 1889 netif_err(priv, tx_err, net_dev, "HW csum error: %d\n", 1890 err); 1891 return err; 1892 } 1893 1894 /* Fill in the rest of the FD fields */ 1895 qm_fd_set_contig(fd, priv->tx_headroom, skb->len); 1896 fd->cmd |= cpu_to_be32(FM_FD_CMD_FCO); 1897 1898 /* Map the entire buffer size that may be seen by FMan, but no more */ 1899 addr = dma_map_single(priv->tx_dma_dev, buff_start, 1900 priv->tx_headroom + skb->len, dma_dir); 1901 if (unlikely(dma_mapping_error(priv->tx_dma_dev, addr))) { 1902 if (net_ratelimit()) 1903 netif_err(priv, tx_err, net_dev, "dma_map_single() failed\n"); 1904 return -EINVAL; 1905 } 1906 qm_fd_addr_set64(fd, addr); 1907 1908 return 0; 1909 } 1910 1911 static int skb_to_sg_fd(struct dpaa_priv *priv, 1912 struct sk_buff *skb, struct qm_fd *fd) 1913 { 1914 const enum dma_data_direction dma_dir = DMA_TO_DEVICE; 1915 const int nr_frags = skb_shinfo(skb)->nr_frags; 1916 struct net_device *net_dev = priv->net_dev; 1917 struct qm_sg_entry *sgt; 1918 struct sk_buff **skbh; 1919 void *buff_start; 1920 skb_frag_t *frag; 1921 dma_addr_t addr; 1922 size_t frag_len; 1923 struct page *p; 1924 int i, j, err; 1925 1926 /* get a page to store the SGTable */ 1927 p = dev_alloc_pages(0); 1928 if (unlikely(!p)) { 1929 netdev_err(net_dev, "dev_alloc_pages() failed\n"); 1930 return -ENOMEM; 1931 } 1932 buff_start = page_address(p); 1933 1934 /* Enable L3/L4 hardware checksum computation. 1935 * 1936 * We must do this before dma_map_single(DMA_TO_DEVICE), because we may 1937 * need to write into the skb. 1938 */ 1939 err = dpaa_enable_tx_csum(priv, skb, fd, 1940 buff_start + DPAA_TX_PRIV_DATA_SIZE); 1941 if (unlikely(err < 0)) { 1942 if (net_ratelimit()) 1943 netif_err(priv, tx_err, net_dev, "HW csum error: %d\n", 1944 err); 1945 goto csum_failed; 1946 } 1947 1948 /* SGT[0] is used by the linear part */ 1949 sgt = (struct qm_sg_entry *)(buff_start + priv->tx_headroom); 1950 frag_len = skb_headlen(skb); 1951 qm_sg_entry_set_len(&sgt[0], frag_len); 1952 sgt[0].bpid = FSL_DPAA_BPID_INV; 1953 sgt[0].offset = 0; 1954 addr = dma_map_single(priv->tx_dma_dev, skb->data, 1955 skb_headlen(skb), dma_dir); 1956 if (unlikely(dma_mapping_error(priv->tx_dma_dev, addr))) { 1957 netdev_err(priv->net_dev, "DMA mapping failed\n"); 1958 err = -EINVAL; 1959 goto sg0_map_failed; 1960 } 1961 qm_sg_entry_set64(&sgt[0], addr); 1962 1963 /* populate the rest of SGT entries */ 1964 for (i = 0; i < nr_frags; i++) { 1965 frag = &skb_shinfo(skb)->frags[i]; 1966 frag_len = skb_frag_size(frag); 1967 WARN_ON(!skb_frag_page(frag)); 1968 addr = skb_frag_dma_map(priv->tx_dma_dev, frag, 0, 1969 frag_len, dma_dir); 1970 if (unlikely(dma_mapping_error(priv->tx_dma_dev, addr))) { 1971 netdev_err(priv->net_dev, "DMA mapping failed\n"); 1972 err = -EINVAL; 1973 goto sg_map_failed; 1974 } 1975 1976 qm_sg_entry_set_len(&sgt[i + 1], frag_len); 1977 sgt[i + 1].bpid = FSL_DPAA_BPID_INV; 1978 sgt[i + 1].offset = 0; 1979 1980 /* keep the offset in the address */ 1981 qm_sg_entry_set64(&sgt[i + 1], addr); 1982 } 1983 1984 /* Set the final bit in the last used entry of the SGT */ 1985 qm_sg_entry_set_f(&sgt[nr_frags], frag_len); 1986 1987 /* set fd offset to priv->tx_headroom */ 1988 qm_fd_set_sg(fd, priv->tx_headroom, skb->len); 1989 1990 /* DMA map the SGT page */ 1991 skbh = (struct sk_buff **)buff_start; 1992 *skbh = skb; 1993 1994 addr = dma_map_page(priv->tx_dma_dev, p, 0, 1995 priv->tx_headroom + DPAA_SGT_SIZE, dma_dir); 1996 if (unlikely(dma_mapping_error(priv->tx_dma_dev, addr))) { 1997 netdev_err(priv->net_dev, "DMA mapping failed\n"); 1998 err = -EINVAL; 1999 goto sgt_map_failed; 2000 } 2001 2002 fd->bpid = FSL_DPAA_BPID_INV; 2003 fd->cmd |= cpu_to_be32(FM_FD_CMD_FCO); 2004 qm_fd_addr_set64(fd, addr); 2005 2006 return 0; 2007 2008 sgt_map_failed: 2009 sg_map_failed: 2010 for (j = 0; j < i; j++) 2011 dma_unmap_page(priv->tx_dma_dev, qm_sg_addr(&sgt[j]), 2012 qm_sg_entry_get_len(&sgt[j]), dma_dir); 2013 sg0_map_failed: 2014 csum_failed: 2015 free_pages((unsigned long)buff_start, 0); 2016 2017 return err; 2018 } 2019 2020 static inline int dpaa_xmit(struct dpaa_priv *priv, 2021 struct rtnl_link_stats64 *percpu_stats, 2022 int queue, 2023 struct qm_fd *fd) 2024 { 2025 struct qman_fq *egress_fq; 2026 int err, i; 2027 2028 egress_fq = priv->egress_fqs[queue]; 2029 if (fd->bpid == FSL_DPAA_BPID_INV) 2030 fd->cmd |= cpu_to_be32(qman_fq_fqid(priv->conf_fqs[queue])); 2031 2032 /* Trace this Tx fd */ 2033 trace_dpaa_tx_fd(priv->net_dev, egress_fq, fd); 2034 2035 for (i = 0; i < DPAA_ENQUEUE_RETRIES; i++) { 2036 err = qman_enqueue(egress_fq, fd); 2037 if (err != -EBUSY) 2038 break; 2039 } 2040 2041 if (unlikely(err < 0)) { 2042 percpu_stats->tx_fifo_errors++; 2043 return err; 2044 } 2045 2046 percpu_stats->tx_packets++; 2047 percpu_stats->tx_bytes += qm_fd_get_length(fd); 2048 2049 return 0; 2050 } 2051 2052 #ifdef CONFIG_DPAA_ERRATUM_A050385 2053 int dpaa_a050385_wa(struct net_device *net_dev, struct sk_buff **s) 2054 { 2055 struct dpaa_priv *priv = netdev_priv(net_dev); 2056 struct sk_buff *new_skb, *skb = *s; 2057 unsigned char *start, i; 2058 2059 /* check linear buffer alignment */ 2060 if (!PTR_IS_ALIGNED(skb->data, DPAA_A050385_ALIGN)) 2061 goto workaround; 2062 2063 /* linear buffers just need to have an aligned start */ 2064 if (!skb_is_nonlinear(skb)) 2065 return 0; 2066 2067 /* linear data size for nonlinear skbs needs to be aligned */ 2068 if (!IS_ALIGNED(skb_headlen(skb), DPAA_A050385_ALIGN)) 2069 goto workaround; 2070 2071 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 2072 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 2073 2074 /* all fragments need to have aligned start addresses */ 2075 if (!IS_ALIGNED(skb_frag_off(frag), DPAA_A050385_ALIGN)) 2076 goto workaround; 2077 2078 /* all but last fragment need to have aligned sizes */ 2079 if (!IS_ALIGNED(skb_frag_size(frag), DPAA_A050385_ALIGN) && 2080 (i < skb_shinfo(skb)->nr_frags - 1)) 2081 goto workaround; 2082 } 2083 2084 return 0; 2085 2086 workaround: 2087 /* copy all the skb content into a new linear buffer */ 2088 new_skb = netdev_alloc_skb(net_dev, skb->len + DPAA_A050385_ALIGN - 1 + 2089 priv->tx_headroom); 2090 if (!new_skb) 2091 return -ENOMEM; 2092 2093 /* NET_SKB_PAD bytes already reserved, adding up to tx_headroom */ 2094 skb_reserve(new_skb, priv->tx_headroom - NET_SKB_PAD); 2095 2096 /* Workaround for DPAA_A050385 requires data start to be aligned */ 2097 start = PTR_ALIGN(new_skb->data, DPAA_A050385_ALIGN); 2098 if (start - new_skb->data != 0) 2099 skb_reserve(new_skb, start - new_skb->data); 2100 2101 skb_put(new_skb, skb->len); 2102 skb_copy_bits(skb, 0, new_skb->data, skb->len); 2103 skb_copy_header(new_skb, skb); 2104 new_skb->dev = skb->dev; 2105 2106 /* We move the headroom when we align it so we have to reset the 2107 * network and transport header offsets relative to the new data 2108 * pointer. The checksum offload relies on these offsets. 2109 */ 2110 skb_set_network_header(new_skb, skb_network_offset(skb)); 2111 skb_set_transport_header(new_skb, skb_transport_offset(skb)); 2112 2113 /* TODO: does timestamping need the result in the old skb? */ 2114 dev_kfree_skb(skb); 2115 *s = new_skb; 2116 2117 return 0; 2118 } 2119 #endif 2120 2121 static netdev_tx_t 2122 dpaa_start_xmit(struct sk_buff *skb, struct net_device *net_dev) 2123 { 2124 const int queue_mapping = skb_get_queue_mapping(skb); 2125 bool nonlinear = skb_is_nonlinear(skb); 2126 struct rtnl_link_stats64 *percpu_stats; 2127 struct dpaa_percpu_priv *percpu_priv; 2128 struct netdev_queue *txq; 2129 struct dpaa_priv *priv; 2130 struct qm_fd fd; 2131 int offset = 0; 2132 int err = 0; 2133 2134 priv = netdev_priv(net_dev); 2135 percpu_priv = this_cpu_ptr(priv->percpu_priv); 2136 percpu_stats = &percpu_priv->stats; 2137 2138 qm_fd_clear_fd(&fd); 2139 2140 if (!nonlinear) { 2141 /* We're going to store the skb backpointer at the beginning 2142 * of the data buffer, so we need a privately owned skb 2143 * 2144 * We've made sure skb is not shared in dev->priv_flags, 2145 * we need to verify the skb head is not cloned 2146 */ 2147 if (skb_cow_head(skb, priv->tx_headroom)) 2148 goto enomem; 2149 2150 WARN_ON(skb_is_nonlinear(skb)); 2151 } 2152 2153 /* MAX_SKB_FRAGS is equal or larger than our dpaa_SGT_MAX_ENTRIES; 2154 * make sure we don't feed FMan with more fragments than it supports. 2155 */ 2156 if (unlikely(nonlinear && 2157 (skb_shinfo(skb)->nr_frags >= DPAA_SGT_MAX_ENTRIES))) { 2158 /* If the egress skb contains more fragments than we support 2159 * we have no choice but to linearize it ourselves. 2160 */ 2161 if (__skb_linearize(skb)) 2162 goto enomem; 2163 2164 nonlinear = skb_is_nonlinear(skb); 2165 } 2166 2167 #ifdef CONFIG_DPAA_ERRATUM_A050385 2168 if (unlikely(fman_has_errata_a050385())) { 2169 if (dpaa_a050385_wa(net_dev, &skb)) 2170 goto enomem; 2171 nonlinear = skb_is_nonlinear(skb); 2172 } 2173 #endif 2174 2175 if (nonlinear) { 2176 /* Just create a S/G fd based on the skb */ 2177 err = skb_to_sg_fd(priv, skb, &fd); 2178 percpu_priv->tx_frag_skbuffs++; 2179 } else { 2180 /* Create a contig FD from this skb */ 2181 err = skb_to_contig_fd(priv, skb, &fd, &offset); 2182 } 2183 if (unlikely(err < 0)) 2184 goto skb_to_fd_failed; 2185 2186 txq = netdev_get_tx_queue(net_dev, queue_mapping); 2187 2188 /* LLTX requires to do our own update of trans_start */ 2189 txq->trans_start = jiffies; 2190 2191 if (priv->tx_tstamp && skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) { 2192 fd.cmd |= cpu_to_be32(FM_FD_CMD_UPD); 2193 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 2194 } 2195 2196 if (likely(dpaa_xmit(priv, percpu_stats, queue_mapping, &fd) == 0)) 2197 return NETDEV_TX_OK; 2198 2199 dpaa_cleanup_tx_fd(priv, &fd, false); 2200 skb_to_fd_failed: 2201 enomem: 2202 percpu_stats->tx_errors++; 2203 dev_kfree_skb(skb); 2204 return NETDEV_TX_OK; 2205 } 2206 2207 static void dpaa_rx_error(struct net_device *net_dev, 2208 const struct dpaa_priv *priv, 2209 struct dpaa_percpu_priv *percpu_priv, 2210 const struct qm_fd *fd, 2211 u32 fqid) 2212 { 2213 if (net_ratelimit()) 2214 netif_err(priv, hw, net_dev, "Err FD status = 0x%08x\n", 2215 be32_to_cpu(fd->status) & FM_FD_STAT_RX_ERRORS); 2216 2217 percpu_priv->stats.rx_errors++; 2218 2219 if (be32_to_cpu(fd->status) & FM_FD_ERR_DMA) 2220 percpu_priv->rx_errors.dme++; 2221 if (be32_to_cpu(fd->status) & FM_FD_ERR_PHYSICAL) 2222 percpu_priv->rx_errors.fpe++; 2223 if (be32_to_cpu(fd->status) & FM_FD_ERR_SIZE) 2224 percpu_priv->rx_errors.fse++; 2225 if (be32_to_cpu(fd->status) & FM_FD_ERR_PRS_HDR_ERR) 2226 percpu_priv->rx_errors.phe++; 2227 2228 dpaa_fd_release(net_dev, fd); 2229 } 2230 2231 static void dpaa_tx_error(struct net_device *net_dev, 2232 const struct dpaa_priv *priv, 2233 struct dpaa_percpu_priv *percpu_priv, 2234 const struct qm_fd *fd, 2235 u32 fqid) 2236 { 2237 struct sk_buff *skb; 2238 2239 if (net_ratelimit()) 2240 netif_warn(priv, hw, net_dev, "FD status = 0x%08x\n", 2241 be32_to_cpu(fd->status) & FM_FD_STAT_TX_ERRORS); 2242 2243 percpu_priv->stats.tx_errors++; 2244 2245 skb = dpaa_cleanup_tx_fd(priv, fd, false); 2246 dev_kfree_skb(skb); 2247 } 2248 2249 static int dpaa_eth_poll(struct napi_struct *napi, int budget) 2250 { 2251 struct dpaa_napi_portal *np = 2252 container_of(napi, struct dpaa_napi_portal, napi); 2253 2254 int cleaned = qman_p_poll_dqrr(np->p, budget); 2255 2256 if (cleaned < budget) { 2257 napi_complete_done(napi, cleaned); 2258 qman_p_irqsource_add(np->p, QM_PIRQ_DQRI); 2259 } else if (np->down) { 2260 qman_p_irqsource_add(np->p, QM_PIRQ_DQRI); 2261 } 2262 2263 return cleaned; 2264 } 2265 2266 static void dpaa_tx_conf(struct net_device *net_dev, 2267 const struct dpaa_priv *priv, 2268 struct dpaa_percpu_priv *percpu_priv, 2269 const struct qm_fd *fd, 2270 u32 fqid) 2271 { 2272 struct sk_buff *skb; 2273 2274 if (unlikely(be32_to_cpu(fd->status) & FM_FD_STAT_TX_ERRORS)) { 2275 if (net_ratelimit()) 2276 netif_warn(priv, hw, net_dev, "FD status = 0x%08x\n", 2277 be32_to_cpu(fd->status) & 2278 FM_FD_STAT_TX_ERRORS); 2279 2280 percpu_priv->stats.tx_errors++; 2281 } 2282 2283 percpu_priv->tx_confirm++; 2284 2285 skb = dpaa_cleanup_tx_fd(priv, fd, true); 2286 2287 consume_skb(skb); 2288 } 2289 2290 static inline int dpaa_eth_napi_schedule(struct dpaa_percpu_priv *percpu_priv, 2291 struct qman_portal *portal) 2292 { 2293 if (unlikely(in_irq() || !in_serving_softirq())) { 2294 /* Disable QMan IRQ and invoke NAPI */ 2295 qman_p_irqsource_remove(portal, QM_PIRQ_DQRI); 2296 2297 percpu_priv->np.p = portal; 2298 napi_schedule(&percpu_priv->np.napi); 2299 percpu_priv->in_interrupt++; 2300 return 1; 2301 } 2302 return 0; 2303 } 2304 2305 static enum qman_cb_dqrr_result rx_error_dqrr(struct qman_portal *portal, 2306 struct qman_fq *fq, 2307 const struct qm_dqrr_entry *dq) 2308 { 2309 struct dpaa_fq *dpaa_fq = container_of(fq, struct dpaa_fq, fq_base); 2310 struct dpaa_percpu_priv *percpu_priv; 2311 struct net_device *net_dev; 2312 struct dpaa_bp *dpaa_bp; 2313 struct dpaa_priv *priv; 2314 2315 net_dev = dpaa_fq->net_dev; 2316 priv = netdev_priv(net_dev); 2317 dpaa_bp = dpaa_bpid2pool(dq->fd.bpid); 2318 if (!dpaa_bp) 2319 return qman_cb_dqrr_consume; 2320 2321 percpu_priv = this_cpu_ptr(priv->percpu_priv); 2322 2323 if (dpaa_eth_napi_schedule(percpu_priv, portal)) 2324 return qman_cb_dqrr_stop; 2325 2326 dpaa_eth_refill_bpools(priv); 2327 dpaa_rx_error(net_dev, priv, percpu_priv, &dq->fd, fq->fqid); 2328 2329 return qman_cb_dqrr_consume; 2330 } 2331 2332 static enum qman_cb_dqrr_result rx_default_dqrr(struct qman_portal *portal, 2333 struct qman_fq *fq, 2334 const struct qm_dqrr_entry *dq) 2335 { 2336 struct skb_shared_hwtstamps *shhwtstamps; 2337 struct rtnl_link_stats64 *percpu_stats; 2338 struct dpaa_percpu_priv *percpu_priv; 2339 const struct qm_fd *fd = &dq->fd; 2340 dma_addr_t addr = qm_fd_addr(fd); 2341 enum qm_fd_format fd_format; 2342 struct net_device *net_dev; 2343 u32 fd_status, hash_offset; 2344 struct dpaa_bp *dpaa_bp; 2345 struct dpaa_priv *priv; 2346 unsigned int skb_len; 2347 struct sk_buff *skb; 2348 int *count_ptr; 2349 void *vaddr; 2350 u64 ns; 2351 2352 fd_status = be32_to_cpu(fd->status); 2353 fd_format = qm_fd_get_format(fd); 2354 net_dev = ((struct dpaa_fq *)fq)->net_dev; 2355 priv = netdev_priv(net_dev); 2356 dpaa_bp = dpaa_bpid2pool(dq->fd.bpid); 2357 if (!dpaa_bp) 2358 return qman_cb_dqrr_consume; 2359 2360 /* Trace the Rx fd */ 2361 trace_dpaa_rx_fd(net_dev, fq, &dq->fd); 2362 2363 percpu_priv = this_cpu_ptr(priv->percpu_priv); 2364 percpu_stats = &percpu_priv->stats; 2365 2366 if (unlikely(dpaa_eth_napi_schedule(percpu_priv, portal))) 2367 return qman_cb_dqrr_stop; 2368 2369 /* Make sure we didn't run out of buffers */ 2370 if (unlikely(dpaa_eth_refill_bpools(priv))) { 2371 /* Unable to refill the buffer pool due to insufficient 2372 * system memory. Just release the frame back into the pool, 2373 * otherwise we'll soon end up with an empty buffer pool. 2374 */ 2375 dpaa_fd_release(net_dev, &dq->fd); 2376 return qman_cb_dqrr_consume; 2377 } 2378 2379 if (unlikely(fd_status & FM_FD_STAT_RX_ERRORS) != 0) { 2380 if (net_ratelimit()) 2381 netif_warn(priv, hw, net_dev, "FD status = 0x%08x\n", 2382 fd_status & FM_FD_STAT_RX_ERRORS); 2383 2384 percpu_stats->rx_errors++; 2385 dpaa_fd_release(net_dev, fd); 2386 return qman_cb_dqrr_consume; 2387 } 2388 2389 dma_unmap_page(dpaa_bp->priv->rx_dma_dev, addr, DPAA_BP_RAW_SIZE, 2390 DMA_FROM_DEVICE); 2391 2392 /* prefetch the first 64 bytes of the frame or the SGT start */ 2393 vaddr = phys_to_virt(addr); 2394 prefetch(vaddr + qm_fd_get_offset(fd)); 2395 2396 /* The only FD types that we may receive are contig and S/G */ 2397 WARN_ON((fd_format != qm_fd_contig) && (fd_format != qm_fd_sg)); 2398 2399 /* Account for either the contig buffer or the SGT buffer (depending on 2400 * which case we were in) having been removed from the pool. 2401 */ 2402 count_ptr = this_cpu_ptr(dpaa_bp->percpu_count); 2403 (*count_ptr)--; 2404 2405 if (likely(fd_format == qm_fd_contig)) 2406 skb = contig_fd_to_skb(priv, fd); 2407 else 2408 skb = sg_fd_to_skb(priv, fd); 2409 if (!skb) 2410 return qman_cb_dqrr_consume; 2411 2412 if (priv->rx_tstamp) { 2413 shhwtstamps = skb_hwtstamps(skb); 2414 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 2415 2416 if (!fman_port_get_tstamp(priv->mac_dev->port[RX], vaddr, &ns)) 2417 shhwtstamps->hwtstamp = ns_to_ktime(ns); 2418 else 2419 dev_warn(net_dev->dev.parent, "fman_port_get_tstamp failed!\n"); 2420 } 2421 2422 skb->protocol = eth_type_trans(skb, net_dev); 2423 2424 if (net_dev->features & NETIF_F_RXHASH && priv->keygen_in_use && 2425 !fman_port_get_hash_result_offset(priv->mac_dev->port[RX], 2426 &hash_offset)) { 2427 enum pkt_hash_types type; 2428 2429 /* if L4 exists, it was used in the hash generation */ 2430 type = be32_to_cpu(fd->status) & FM_FD_STAT_L4CV ? 2431 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3; 2432 skb_set_hash(skb, be32_to_cpu(*(u32 *)(vaddr + hash_offset)), 2433 type); 2434 } 2435 2436 skb_len = skb->len; 2437 2438 if (unlikely(netif_receive_skb(skb) == NET_RX_DROP)) { 2439 percpu_stats->rx_dropped++; 2440 return qman_cb_dqrr_consume; 2441 } 2442 2443 percpu_stats->rx_packets++; 2444 percpu_stats->rx_bytes += skb_len; 2445 2446 return qman_cb_dqrr_consume; 2447 } 2448 2449 static enum qman_cb_dqrr_result conf_error_dqrr(struct qman_portal *portal, 2450 struct qman_fq *fq, 2451 const struct qm_dqrr_entry *dq) 2452 { 2453 struct dpaa_percpu_priv *percpu_priv; 2454 struct net_device *net_dev; 2455 struct dpaa_priv *priv; 2456 2457 net_dev = ((struct dpaa_fq *)fq)->net_dev; 2458 priv = netdev_priv(net_dev); 2459 2460 percpu_priv = this_cpu_ptr(priv->percpu_priv); 2461 2462 if (dpaa_eth_napi_schedule(percpu_priv, portal)) 2463 return qman_cb_dqrr_stop; 2464 2465 dpaa_tx_error(net_dev, priv, percpu_priv, &dq->fd, fq->fqid); 2466 2467 return qman_cb_dqrr_consume; 2468 } 2469 2470 static enum qman_cb_dqrr_result conf_dflt_dqrr(struct qman_portal *portal, 2471 struct qman_fq *fq, 2472 const struct qm_dqrr_entry *dq) 2473 { 2474 struct dpaa_percpu_priv *percpu_priv; 2475 struct net_device *net_dev; 2476 struct dpaa_priv *priv; 2477 2478 net_dev = ((struct dpaa_fq *)fq)->net_dev; 2479 priv = netdev_priv(net_dev); 2480 2481 /* Trace the fd */ 2482 trace_dpaa_tx_conf_fd(net_dev, fq, &dq->fd); 2483 2484 percpu_priv = this_cpu_ptr(priv->percpu_priv); 2485 2486 if (dpaa_eth_napi_schedule(percpu_priv, portal)) 2487 return qman_cb_dqrr_stop; 2488 2489 dpaa_tx_conf(net_dev, priv, percpu_priv, &dq->fd, fq->fqid); 2490 2491 return qman_cb_dqrr_consume; 2492 } 2493 2494 static void egress_ern(struct qman_portal *portal, 2495 struct qman_fq *fq, 2496 const union qm_mr_entry *msg) 2497 { 2498 const struct qm_fd *fd = &msg->ern.fd; 2499 struct dpaa_percpu_priv *percpu_priv; 2500 const struct dpaa_priv *priv; 2501 struct net_device *net_dev; 2502 struct sk_buff *skb; 2503 2504 net_dev = ((struct dpaa_fq *)fq)->net_dev; 2505 priv = netdev_priv(net_dev); 2506 percpu_priv = this_cpu_ptr(priv->percpu_priv); 2507 2508 percpu_priv->stats.tx_dropped++; 2509 percpu_priv->stats.tx_fifo_errors++; 2510 count_ern(percpu_priv, msg); 2511 2512 skb = dpaa_cleanup_tx_fd(priv, fd, false); 2513 dev_kfree_skb_any(skb); 2514 } 2515 2516 static const struct dpaa_fq_cbs dpaa_fq_cbs = { 2517 .rx_defq = { .cb = { .dqrr = rx_default_dqrr } }, 2518 .tx_defq = { .cb = { .dqrr = conf_dflt_dqrr } }, 2519 .rx_errq = { .cb = { .dqrr = rx_error_dqrr } }, 2520 .tx_errq = { .cb = { .dqrr = conf_error_dqrr } }, 2521 .egress_ern = { .cb = { .ern = egress_ern } } 2522 }; 2523 2524 static void dpaa_eth_napi_enable(struct dpaa_priv *priv) 2525 { 2526 struct dpaa_percpu_priv *percpu_priv; 2527 int i; 2528 2529 for_each_online_cpu(i) { 2530 percpu_priv = per_cpu_ptr(priv->percpu_priv, i); 2531 2532 percpu_priv->np.down = 0; 2533 napi_enable(&percpu_priv->np.napi); 2534 } 2535 } 2536 2537 static void dpaa_eth_napi_disable(struct dpaa_priv *priv) 2538 { 2539 struct dpaa_percpu_priv *percpu_priv; 2540 int i; 2541 2542 for_each_online_cpu(i) { 2543 percpu_priv = per_cpu_ptr(priv->percpu_priv, i); 2544 2545 percpu_priv->np.down = 1; 2546 napi_disable(&percpu_priv->np.napi); 2547 } 2548 } 2549 2550 static void dpaa_adjust_link(struct net_device *net_dev) 2551 { 2552 struct mac_device *mac_dev; 2553 struct dpaa_priv *priv; 2554 2555 priv = netdev_priv(net_dev); 2556 mac_dev = priv->mac_dev; 2557 mac_dev->adjust_link(mac_dev); 2558 } 2559 2560 /* The Aquantia PHYs are capable of performing rate adaptation */ 2561 #define PHY_VEND_AQUANTIA 0x03a1b400 2562 2563 static int dpaa_phy_init(struct net_device *net_dev) 2564 { 2565 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 2566 struct mac_device *mac_dev; 2567 struct phy_device *phy_dev; 2568 struct dpaa_priv *priv; 2569 2570 priv = netdev_priv(net_dev); 2571 mac_dev = priv->mac_dev; 2572 2573 phy_dev = of_phy_connect(net_dev, mac_dev->phy_node, 2574 &dpaa_adjust_link, 0, 2575 mac_dev->phy_if); 2576 if (!phy_dev) { 2577 netif_err(priv, ifup, net_dev, "init_phy() failed\n"); 2578 return -ENODEV; 2579 } 2580 2581 /* Unless the PHY is capable of rate adaptation */ 2582 if (mac_dev->phy_if != PHY_INTERFACE_MODE_XGMII || 2583 ((phy_dev->drv->phy_id & GENMASK(31, 10)) != PHY_VEND_AQUANTIA)) { 2584 /* remove any features not supported by the controller */ 2585 ethtool_convert_legacy_u32_to_link_mode(mask, 2586 mac_dev->if_support); 2587 linkmode_and(phy_dev->supported, phy_dev->supported, mask); 2588 } 2589 2590 phy_support_asym_pause(phy_dev); 2591 2592 mac_dev->phy_dev = phy_dev; 2593 net_dev->phydev = phy_dev; 2594 2595 return 0; 2596 } 2597 2598 static int dpaa_open(struct net_device *net_dev) 2599 { 2600 struct mac_device *mac_dev; 2601 struct dpaa_priv *priv; 2602 int err, i; 2603 2604 priv = netdev_priv(net_dev); 2605 mac_dev = priv->mac_dev; 2606 dpaa_eth_napi_enable(priv); 2607 2608 err = dpaa_phy_init(net_dev); 2609 if (err) 2610 goto phy_init_failed; 2611 2612 for (i = 0; i < ARRAY_SIZE(mac_dev->port); i++) { 2613 err = fman_port_enable(mac_dev->port[i]); 2614 if (err) 2615 goto mac_start_failed; 2616 } 2617 2618 err = priv->mac_dev->start(mac_dev); 2619 if (err < 0) { 2620 netif_err(priv, ifup, net_dev, "mac_dev->start() = %d\n", err); 2621 goto mac_start_failed; 2622 } 2623 2624 netif_tx_start_all_queues(net_dev); 2625 2626 return 0; 2627 2628 mac_start_failed: 2629 for (i = 0; i < ARRAY_SIZE(mac_dev->port); i++) 2630 fman_port_disable(mac_dev->port[i]); 2631 2632 phy_init_failed: 2633 dpaa_eth_napi_disable(priv); 2634 2635 return err; 2636 } 2637 2638 static int dpaa_eth_stop(struct net_device *net_dev) 2639 { 2640 struct dpaa_priv *priv; 2641 int err; 2642 2643 err = dpaa_stop(net_dev); 2644 2645 priv = netdev_priv(net_dev); 2646 dpaa_eth_napi_disable(priv); 2647 2648 return err; 2649 } 2650 2651 static int dpaa_ts_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 2652 { 2653 struct dpaa_priv *priv = netdev_priv(dev); 2654 struct hwtstamp_config config; 2655 2656 if (copy_from_user(&config, rq->ifr_data, sizeof(config))) 2657 return -EFAULT; 2658 2659 switch (config.tx_type) { 2660 case HWTSTAMP_TX_OFF: 2661 /* Couldn't disable rx/tx timestamping separately. 2662 * Do nothing here. 2663 */ 2664 priv->tx_tstamp = false; 2665 break; 2666 case HWTSTAMP_TX_ON: 2667 priv->mac_dev->set_tstamp(priv->mac_dev->fman_mac, true); 2668 priv->tx_tstamp = true; 2669 break; 2670 default: 2671 return -ERANGE; 2672 } 2673 2674 if (config.rx_filter == HWTSTAMP_FILTER_NONE) { 2675 /* Couldn't disable rx/tx timestamping separately. 2676 * Do nothing here. 2677 */ 2678 priv->rx_tstamp = false; 2679 } else { 2680 priv->mac_dev->set_tstamp(priv->mac_dev->fman_mac, true); 2681 priv->rx_tstamp = true; 2682 /* TS is set for all frame types, not only those requested */ 2683 config.rx_filter = HWTSTAMP_FILTER_ALL; 2684 } 2685 2686 return copy_to_user(rq->ifr_data, &config, sizeof(config)) ? 2687 -EFAULT : 0; 2688 } 2689 2690 static int dpaa_ioctl(struct net_device *net_dev, struct ifreq *rq, int cmd) 2691 { 2692 int ret = -EINVAL; 2693 2694 if (cmd == SIOCGMIIREG) { 2695 if (net_dev->phydev) 2696 return phy_mii_ioctl(net_dev->phydev, rq, cmd); 2697 } 2698 2699 if (cmd == SIOCSHWTSTAMP) 2700 return dpaa_ts_ioctl(net_dev, rq, cmd); 2701 2702 return ret; 2703 } 2704 2705 static const struct net_device_ops dpaa_ops = { 2706 .ndo_open = dpaa_open, 2707 .ndo_start_xmit = dpaa_start_xmit, 2708 .ndo_stop = dpaa_eth_stop, 2709 .ndo_tx_timeout = dpaa_tx_timeout, 2710 .ndo_get_stats64 = dpaa_get_stats64, 2711 .ndo_change_carrier = fixed_phy_change_carrier, 2712 .ndo_set_mac_address = dpaa_set_mac_address, 2713 .ndo_validate_addr = eth_validate_addr, 2714 .ndo_set_rx_mode = dpaa_set_rx_mode, 2715 .ndo_do_ioctl = dpaa_ioctl, 2716 .ndo_setup_tc = dpaa_setup_tc, 2717 }; 2718 2719 static int dpaa_napi_add(struct net_device *net_dev) 2720 { 2721 struct dpaa_priv *priv = netdev_priv(net_dev); 2722 struct dpaa_percpu_priv *percpu_priv; 2723 int cpu; 2724 2725 for_each_possible_cpu(cpu) { 2726 percpu_priv = per_cpu_ptr(priv->percpu_priv, cpu); 2727 2728 netif_napi_add(net_dev, &percpu_priv->np.napi, 2729 dpaa_eth_poll, NAPI_POLL_WEIGHT); 2730 } 2731 2732 return 0; 2733 } 2734 2735 static void dpaa_napi_del(struct net_device *net_dev) 2736 { 2737 struct dpaa_priv *priv = netdev_priv(net_dev); 2738 struct dpaa_percpu_priv *percpu_priv; 2739 int cpu; 2740 2741 for_each_possible_cpu(cpu) { 2742 percpu_priv = per_cpu_ptr(priv->percpu_priv, cpu); 2743 2744 netif_napi_del(&percpu_priv->np.napi); 2745 } 2746 } 2747 2748 static inline void dpaa_bp_free_pf(const struct dpaa_bp *bp, 2749 struct bm_buffer *bmb) 2750 { 2751 dma_addr_t addr = bm_buf_addr(bmb); 2752 2753 dma_unmap_page(bp->priv->rx_dma_dev, addr, DPAA_BP_RAW_SIZE, 2754 DMA_FROM_DEVICE); 2755 2756 skb_free_frag(phys_to_virt(addr)); 2757 } 2758 2759 /* Alloc the dpaa_bp struct and configure default values */ 2760 static struct dpaa_bp *dpaa_bp_alloc(struct device *dev) 2761 { 2762 struct dpaa_bp *dpaa_bp; 2763 2764 dpaa_bp = devm_kzalloc(dev, sizeof(*dpaa_bp), GFP_KERNEL); 2765 if (!dpaa_bp) 2766 return ERR_PTR(-ENOMEM); 2767 2768 dpaa_bp->bpid = FSL_DPAA_BPID_INV; 2769 dpaa_bp->percpu_count = devm_alloc_percpu(dev, *dpaa_bp->percpu_count); 2770 if (!dpaa_bp->percpu_count) 2771 return ERR_PTR(-ENOMEM); 2772 2773 dpaa_bp->config_count = FSL_DPAA_ETH_MAX_BUF_COUNT; 2774 2775 dpaa_bp->seed_cb = dpaa_bp_seed; 2776 dpaa_bp->free_buf_cb = dpaa_bp_free_pf; 2777 2778 return dpaa_bp; 2779 } 2780 2781 /* Place all ingress FQs (Rx Default, Rx Error) in a dedicated CGR. 2782 * We won't be sending congestion notifications to FMan; for now, we just use 2783 * this CGR to generate enqueue rejections to FMan in order to drop the frames 2784 * before they reach our ingress queues and eat up memory. 2785 */ 2786 static int dpaa_ingress_cgr_init(struct dpaa_priv *priv) 2787 { 2788 struct qm_mcc_initcgr initcgr; 2789 u32 cs_th; 2790 int err; 2791 2792 err = qman_alloc_cgrid(&priv->ingress_cgr.cgrid); 2793 if (err < 0) { 2794 if (netif_msg_drv(priv)) 2795 pr_err("Error %d allocating CGR ID\n", err); 2796 goto out_error; 2797 } 2798 2799 /* Enable CS TD, but disable Congestion State Change Notifications. */ 2800 memset(&initcgr, 0, sizeof(initcgr)); 2801 initcgr.we_mask = cpu_to_be16(QM_CGR_WE_CS_THRES); 2802 initcgr.cgr.cscn_en = QM_CGR_EN; 2803 cs_th = DPAA_INGRESS_CS_THRESHOLD; 2804 qm_cgr_cs_thres_set64(&initcgr.cgr.cs_thres, cs_th, 1); 2805 2806 initcgr.we_mask |= cpu_to_be16(QM_CGR_WE_CSTD_EN); 2807 initcgr.cgr.cstd_en = QM_CGR_EN; 2808 2809 /* This CGR will be associated with the SWP affined to the current CPU. 2810 * However, we'll place all our ingress FQs in it. 2811 */ 2812 err = qman_create_cgr(&priv->ingress_cgr, QMAN_CGR_FLAG_USE_INIT, 2813 &initcgr); 2814 if (err < 0) { 2815 if (netif_msg_drv(priv)) 2816 pr_err("Error %d creating ingress CGR with ID %d\n", 2817 err, priv->ingress_cgr.cgrid); 2818 qman_release_cgrid(priv->ingress_cgr.cgrid); 2819 goto out_error; 2820 } 2821 if (netif_msg_drv(priv)) 2822 pr_debug("Created ingress CGR %d for netdev with hwaddr %pM\n", 2823 priv->ingress_cgr.cgrid, priv->mac_dev->addr); 2824 2825 priv->use_ingress_cgr = true; 2826 2827 out_error: 2828 return err; 2829 } 2830 2831 static inline u16 dpaa_get_headroom(struct dpaa_buffer_layout *bl) 2832 { 2833 u16 headroom; 2834 2835 /* The frame headroom must accommodate: 2836 * - the driver private data area 2837 * - parse results, hash results, timestamp if selected 2838 * If either hash results or time stamp are selected, both will 2839 * be copied to/from the frame headroom, as TS is located between PR and 2840 * HR in the IC and IC copy size has a granularity of 16bytes 2841 * (see description of FMBM_RICP and FMBM_TICP registers in DPAARM) 2842 * 2843 * Also make sure the headroom is a multiple of data_align bytes 2844 */ 2845 headroom = (u16)(bl->priv_data_size + DPAA_PARSE_RESULTS_SIZE + 2846 DPAA_TIME_STAMP_SIZE + DPAA_HASH_RESULTS_SIZE); 2847 2848 return ALIGN(headroom, DPAA_FD_DATA_ALIGNMENT); 2849 } 2850 2851 static int dpaa_eth_probe(struct platform_device *pdev) 2852 { 2853 struct net_device *net_dev = NULL; 2854 struct dpaa_bp *dpaa_bp = NULL; 2855 struct dpaa_fq *dpaa_fq, *tmp; 2856 struct dpaa_priv *priv = NULL; 2857 struct fm_port_fqs port_fqs; 2858 struct mac_device *mac_dev; 2859 int err = 0, channel; 2860 struct device *dev; 2861 2862 dev = &pdev->dev; 2863 2864 err = bman_is_probed(); 2865 if (!err) 2866 return -EPROBE_DEFER; 2867 if (err < 0) { 2868 dev_err(dev, "failing probe due to bman probe error\n"); 2869 return -ENODEV; 2870 } 2871 err = qman_is_probed(); 2872 if (!err) 2873 return -EPROBE_DEFER; 2874 if (err < 0) { 2875 dev_err(dev, "failing probe due to qman probe error\n"); 2876 return -ENODEV; 2877 } 2878 err = bman_portals_probed(); 2879 if (!err) 2880 return -EPROBE_DEFER; 2881 if (err < 0) { 2882 dev_err(dev, 2883 "failing probe due to bman portals probe error\n"); 2884 return -ENODEV; 2885 } 2886 err = qman_portals_probed(); 2887 if (!err) 2888 return -EPROBE_DEFER; 2889 if (err < 0) { 2890 dev_err(dev, 2891 "failing probe due to qman portals probe error\n"); 2892 return -ENODEV; 2893 } 2894 2895 /* Allocate this early, so we can store relevant information in 2896 * the private area 2897 */ 2898 net_dev = alloc_etherdev_mq(sizeof(*priv), DPAA_ETH_TXQ_NUM); 2899 if (!net_dev) { 2900 dev_err(dev, "alloc_etherdev_mq() failed\n"); 2901 return -ENOMEM; 2902 } 2903 2904 /* Do this here, so we can be verbose early */ 2905 SET_NETDEV_DEV(net_dev, dev); 2906 dev_set_drvdata(dev, net_dev); 2907 2908 priv = netdev_priv(net_dev); 2909 priv->net_dev = net_dev; 2910 2911 priv->msg_enable = netif_msg_init(debug, DPAA_MSG_DEFAULT); 2912 2913 mac_dev = dpaa_mac_dev_get(pdev); 2914 if (IS_ERR(mac_dev)) { 2915 netdev_err(net_dev, "dpaa_mac_dev_get() failed\n"); 2916 err = PTR_ERR(mac_dev); 2917 goto free_netdev; 2918 } 2919 2920 /* Devices used for DMA mapping */ 2921 priv->rx_dma_dev = fman_port_get_device(mac_dev->port[RX]); 2922 priv->tx_dma_dev = fman_port_get_device(mac_dev->port[TX]); 2923 err = dma_coerce_mask_and_coherent(priv->rx_dma_dev, DMA_BIT_MASK(40)); 2924 if (!err) 2925 err = dma_coerce_mask_and_coherent(priv->tx_dma_dev, 2926 DMA_BIT_MASK(40)); 2927 if (err) { 2928 netdev_err(net_dev, "dma_coerce_mask_and_coherent() failed\n"); 2929 return err; 2930 } 2931 2932 /* If fsl_fm_max_frm is set to a higher value than the all-common 1500, 2933 * we choose conservatively and let the user explicitly set a higher 2934 * MTU via ifconfig. Otherwise, the user may end up with different MTUs 2935 * in the same LAN. 2936 * If on the other hand fsl_fm_max_frm has been chosen below 1500, 2937 * start with the maximum allowed. 2938 */ 2939 net_dev->mtu = min(dpaa_get_max_mtu(), ETH_DATA_LEN); 2940 2941 netdev_dbg(net_dev, "Setting initial MTU on net device: %d\n", 2942 net_dev->mtu); 2943 2944 priv->buf_layout[RX].priv_data_size = DPAA_RX_PRIV_DATA_SIZE; /* Rx */ 2945 priv->buf_layout[TX].priv_data_size = DPAA_TX_PRIV_DATA_SIZE; /* Tx */ 2946 2947 /* bp init */ 2948 dpaa_bp = dpaa_bp_alloc(dev); 2949 if (IS_ERR(dpaa_bp)) { 2950 err = PTR_ERR(dpaa_bp); 2951 goto free_dpaa_bps; 2952 } 2953 /* the raw size of the buffers used for reception */ 2954 dpaa_bp->raw_size = DPAA_BP_RAW_SIZE; 2955 /* avoid runtime computations by keeping the usable size here */ 2956 dpaa_bp->size = dpaa_bp_size(dpaa_bp->raw_size); 2957 dpaa_bp->priv = priv; 2958 2959 err = dpaa_bp_alloc_pool(dpaa_bp); 2960 if (err < 0) 2961 goto free_dpaa_bps; 2962 priv->dpaa_bp = dpaa_bp; 2963 2964 INIT_LIST_HEAD(&priv->dpaa_fq_list); 2965 2966 memset(&port_fqs, 0, sizeof(port_fqs)); 2967 2968 err = dpaa_alloc_all_fqs(dev, &priv->dpaa_fq_list, &port_fqs); 2969 if (err < 0) { 2970 dev_err(dev, "dpaa_alloc_all_fqs() failed\n"); 2971 goto free_dpaa_bps; 2972 } 2973 2974 priv->mac_dev = mac_dev; 2975 2976 channel = dpaa_get_channel(); 2977 if (channel < 0) { 2978 dev_err(dev, "dpaa_get_channel() failed\n"); 2979 err = channel; 2980 goto free_dpaa_bps; 2981 } 2982 2983 priv->channel = (u16)channel; 2984 2985 /* Walk the CPUs with affine portals 2986 * and add this pool channel to each's dequeue mask. 2987 */ 2988 dpaa_eth_add_channel(priv->channel, &pdev->dev); 2989 2990 dpaa_fq_setup(priv, &dpaa_fq_cbs, priv->mac_dev->port[TX]); 2991 2992 /* Create a congestion group for this netdev, with 2993 * dynamically-allocated CGR ID. 2994 * Must be executed after probing the MAC, but before 2995 * assigning the egress FQs to the CGRs. 2996 */ 2997 err = dpaa_eth_cgr_init(priv); 2998 if (err < 0) { 2999 dev_err(dev, "Error initializing CGR\n"); 3000 goto free_dpaa_bps; 3001 } 3002 3003 err = dpaa_ingress_cgr_init(priv); 3004 if (err < 0) { 3005 dev_err(dev, "Error initializing ingress CGR\n"); 3006 goto delete_egress_cgr; 3007 } 3008 3009 /* Add the FQs to the interface, and make them active */ 3010 list_for_each_entry_safe(dpaa_fq, tmp, &priv->dpaa_fq_list, list) { 3011 err = dpaa_fq_init(dpaa_fq, false); 3012 if (err < 0) 3013 goto free_dpaa_fqs; 3014 } 3015 3016 priv->tx_headroom = dpaa_get_headroom(&priv->buf_layout[TX]); 3017 priv->rx_headroom = dpaa_get_headroom(&priv->buf_layout[RX]); 3018 3019 /* All real interfaces need their ports initialized */ 3020 err = dpaa_eth_init_ports(mac_dev, dpaa_bp, &port_fqs, 3021 &priv->buf_layout[0], dev); 3022 if (err) 3023 goto free_dpaa_fqs; 3024 3025 /* Rx traffic distribution based on keygen hashing defaults to on */ 3026 priv->keygen_in_use = true; 3027 3028 priv->percpu_priv = devm_alloc_percpu(dev, *priv->percpu_priv); 3029 if (!priv->percpu_priv) { 3030 dev_err(dev, "devm_alloc_percpu() failed\n"); 3031 err = -ENOMEM; 3032 goto free_dpaa_fqs; 3033 } 3034 3035 priv->num_tc = 1; 3036 netif_set_real_num_tx_queues(net_dev, priv->num_tc * DPAA_TC_TXQ_NUM); 3037 3038 /* Initialize NAPI */ 3039 err = dpaa_napi_add(net_dev); 3040 if (err < 0) 3041 goto delete_dpaa_napi; 3042 3043 err = dpaa_netdev_init(net_dev, &dpaa_ops, tx_timeout); 3044 if (err < 0) 3045 goto delete_dpaa_napi; 3046 3047 dpaa_eth_sysfs_init(&net_dev->dev); 3048 3049 netif_info(priv, probe, net_dev, "Probed interface %s\n", 3050 net_dev->name); 3051 3052 return 0; 3053 3054 delete_dpaa_napi: 3055 dpaa_napi_del(net_dev); 3056 free_dpaa_fqs: 3057 dpaa_fq_free(dev, &priv->dpaa_fq_list); 3058 qman_delete_cgr_safe(&priv->ingress_cgr); 3059 qman_release_cgrid(priv->ingress_cgr.cgrid); 3060 delete_egress_cgr: 3061 qman_delete_cgr_safe(&priv->cgr_data.cgr); 3062 qman_release_cgrid(priv->cgr_data.cgr.cgrid); 3063 free_dpaa_bps: 3064 dpaa_bps_free(priv); 3065 free_netdev: 3066 dev_set_drvdata(dev, NULL); 3067 free_netdev(net_dev); 3068 3069 return err; 3070 } 3071 3072 static int dpaa_remove(struct platform_device *pdev) 3073 { 3074 struct net_device *net_dev; 3075 struct dpaa_priv *priv; 3076 struct device *dev; 3077 int err; 3078 3079 dev = &pdev->dev; 3080 net_dev = dev_get_drvdata(dev); 3081 3082 priv = netdev_priv(net_dev); 3083 3084 dpaa_eth_sysfs_remove(dev); 3085 3086 dev_set_drvdata(dev, NULL); 3087 unregister_netdev(net_dev); 3088 3089 err = dpaa_fq_free(dev, &priv->dpaa_fq_list); 3090 3091 qman_delete_cgr_safe(&priv->ingress_cgr); 3092 qman_release_cgrid(priv->ingress_cgr.cgrid); 3093 qman_delete_cgr_safe(&priv->cgr_data.cgr); 3094 qman_release_cgrid(priv->cgr_data.cgr.cgrid); 3095 3096 dpaa_napi_del(net_dev); 3097 3098 dpaa_bps_free(priv); 3099 3100 free_netdev(net_dev); 3101 3102 return err; 3103 } 3104 3105 static const struct platform_device_id dpaa_devtype[] = { 3106 { 3107 .name = "dpaa-ethernet", 3108 .driver_data = 0, 3109 }, { 3110 } 3111 }; 3112 MODULE_DEVICE_TABLE(platform, dpaa_devtype); 3113 3114 static struct platform_driver dpaa_driver = { 3115 .driver = { 3116 .name = KBUILD_MODNAME, 3117 }, 3118 .id_table = dpaa_devtype, 3119 .probe = dpaa_eth_probe, 3120 .remove = dpaa_remove 3121 }; 3122 3123 static int __init dpaa_load(void) 3124 { 3125 int err; 3126 3127 pr_debug("FSL DPAA Ethernet driver\n"); 3128 3129 /* initialize dpaa_eth mirror values */ 3130 dpaa_rx_extra_headroom = fman_get_rx_extra_headroom(); 3131 dpaa_max_frm = fman_get_max_frm(); 3132 3133 err = platform_driver_register(&dpaa_driver); 3134 if (err < 0) 3135 pr_err("Error, platform_driver_register() = %d\n", err); 3136 3137 return err; 3138 } 3139 module_init(dpaa_load); 3140 3141 static void __exit dpaa_unload(void) 3142 { 3143 platform_driver_unregister(&dpaa_driver); 3144 3145 /* Only one channel is used and needs to be released after all 3146 * interfaces are removed 3147 */ 3148 dpaa_release_channel(); 3149 } 3150 module_exit(dpaa_unload); 3151 3152 MODULE_LICENSE("Dual BSD/GPL"); 3153 MODULE_DESCRIPTION("FSL DPAA Ethernet driver"); 3154