1 /* 2 Written 1998-2000 by Donald Becker. 3 4 This software may be used and distributed according to the terms of 5 the GNU General Public License (GPL), incorporated herein by reference. 6 Drivers based on or derived from this code fall under the GPL and must 7 retain the authorship, copyright and license notice. This file is not 8 a complete program and may only be used when the entire operating 9 system is licensed under the GPL. 10 11 The author may be reached as becker@scyld.com, or C/O 12 Scyld Computing Corporation 13 410 Severn Ave., Suite 210 14 Annapolis MD 21403 15 16 Support information and updates available at 17 http://www.scyld.com/network/pci-skeleton.html 18 19 Linux kernel updates: 20 21 Version 2.51, Nov 17, 2001 (jgarzik): 22 - Add ethtool support 23 - Replace some MII-related magic numbers with constants 24 25 */ 26 27 #define DRV_NAME "fealnx" 28 29 static int debug; /* 1-> print debug message */ 30 static int max_interrupt_work = 20; 31 32 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). */ 33 static int multicast_filter_limit = 32; 34 35 /* Set the copy breakpoint for the copy-only-tiny-frames scheme. */ 36 /* Setting to > 1518 effectively disables this feature. */ 37 static int rx_copybreak; 38 39 /* Used to pass the media type, etc. */ 40 /* Both 'options[]' and 'full_duplex[]' should exist for driver */ 41 /* interoperability. */ 42 /* The media type is usually passed in 'options[]'. */ 43 #define MAX_UNITS 8 /* More are supported, limit only on options */ 44 static int options[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 }; 45 static int full_duplex[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 }; 46 47 /* Operational parameters that are set at compile time. */ 48 /* Keep the ring sizes a power of two for compile efficiency. */ 49 /* The compiler will convert <unsigned>'%'<2^N> into a bit mask. */ 50 /* Making the Tx ring too large decreases the effectiveness of channel */ 51 /* bonding and packet priority. */ 52 /* There are no ill effects from too-large receive rings. */ 53 // 88-12-9 modify, 54 // #define TX_RING_SIZE 16 55 // #define RX_RING_SIZE 32 56 #define TX_RING_SIZE 6 57 #define RX_RING_SIZE 12 58 #define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct fealnx_desc) 59 #define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct fealnx_desc) 60 61 /* Operational parameters that usually are not changed. */ 62 /* Time in jiffies before concluding the transmitter is hung. */ 63 #define TX_TIMEOUT (2*HZ) 64 65 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer. */ 66 67 68 /* Include files, designed to support most kernel versions 2.0.0 and later. */ 69 #include <linux/module.h> 70 #include <linux/kernel.h> 71 #include <linux/string.h> 72 #include <linux/timer.h> 73 #include <linux/errno.h> 74 #include <linux/ioport.h> 75 #include <linux/interrupt.h> 76 #include <linux/pci.h> 77 #include <linux/netdevice.h> 78 #include <linux/etherdevice.h> 79 #include <linux/skbuff.h> 80 #include <linux/init.h> 81 #include <linux/mii.h> 82 #include <linux/ethtool.h> 83 #include <linux/crc32.h> 84 #include <linux/delay.h> 85 #include <linux/bitops.h> 86 87 #include <asm/processor.h> /* Processor type for cache alignment. */ 88 #include <asm/io.h> 89 #include <linux/uaccess.h> 90 #include <asm/byteorder.h> 91 92 /* This driver was written to use PCI memory space, however some x86 systems 93 work only with I/O space accesses. */ 94 #ifndef __alpha__ 95 #define USE_IO_OPS 96 #endif 97 98 /* Kernel compatibility defines, some common to David Hinds' PCMCIA package. */ 99 /* This is only in the support-all-kernels source code. */ 100 101 #define RUN_AT(x) (jiffies + (x)) 102 103 MODULE_AUTHOR("Myson or whoever"); 104 MODULE_DESCRIPTION("Myson MTD-8xx 100/10M Ethernet PCI Adapter Driver"); 105 MODULE_LICENSE("GPL"); 106 module_param(max_interrupt_work, int, 0); 107 module_param(debug, int, 0); 108 module_param(rx_copybreak, int, 0); 109 module_param(multicast_filter_limit, int, 0); 110 module_param_array(options, int, NULL, 0); 111 module_param_array(full_duplex, int, NULL, 0); 112 MODULE_PARM_DESC(max_interrupt_work, "fealnx maximum events handled per interrupt"); 113 MODULE_PARM_DESC(debug, "fealnx enable debugging (0-1)"); 114 MODULE_PARM_DESC(rx_copybreak, "fealnx copy breakpoint for copy-only-tiny-frames"); 115 MODULE_PARM_DESC(multicast_filter_limit, "fealnx maximum number of filtered multicast addresses"); 116 MODULE_PARM_DESC(options, "fealnx: Bits 0-3: media type, bit 17: full duplex"); 117 MODULE_PARM_DESC(full_duplex, "fealnx full duplex setting(s) (1)"); 118 119 enum { 120 MIN_REGION_SIZE = 136, 121 }; 122 123 /* A chip capabilities table, matching the entries in pci_tbl[] above. */ 124 enum chip_capability_flags { 125 HAS_MII_XCVR, 126 HAS_CHIP_XCVR, 127 }; 128 129 /* 89/6/13 add, */ 130 /* for different PHY */ 131 enum phy_type_flags { 132 MysonPHY = 1, 133 AhdocPHY = 2, 134 SeeqPHY = 3, 135 MarvellPHY = 4, 136 Myson981 = 5, 137 LevelOnePHY = 6, 138 OtherPHY = 10, 139 }; 140 141 struct chip_info { 142 char *chip_name; 143 int flags; 144 }; 145 146 static const struct chip_info skel_netdrv_tbl[] = { 147 { "100/10M Ethernet PCI Adapter", HAS_MII_XCVR }, 148 { "100/10M Ethernet PCI Adapter", HAS_CHIP_XCVR }, 149 { "1000/100/10M Ethernet PCI Adapter", HAS_MII_XCVR }, 150 }; 151 152 /* Offsets to the Command and Status Registers. */ 153 enum fealnx_offsets { 154 PAR0 = 0x0, /* physical address 0-3 */ 155 PAR1 = 0x04, /* physical address 4-5 */ 156 MAR0 = 0x08, /* multicast address 0-3 */ 157 MAR1 = 0x0C, /* multicast address 4-7 */ 158 FAR0 = 0x10, /* flow-control address 0-3 */ 159 FAR1 = 0x14, /* flow-control address 4-5 */ 160 TCRRCR = 0x18, /* receive & transmit configuration */ 161 BCR = 0x1C, /* bus command */ 162 TXPDR = 0x20, /* transmit polling demand */ 163 RXPDR = 0x24, /* receive polling demand */ 164 RXCWP = 0x28, /* receive current word pointer */ 165 TXLBA = 0x2C, /* transmit list base address */ 166 RXLBA = 0x30, /* receive list base address */ 167 ISR = 0x34, /* interrupt status */ 168 IMR = 0x38, /* interrupt mask */ 169 FTH = 0x3C, /* flow control high/low threshold */ 170 MANAGEMENT = 0x40, /* bootrom/eeprom and mii management */ 171 TALLY = 0x44, /* tally counters for crc and mpa */ 172 TSR = 0x48, /* tally counter for transmit status */ 173 BMCRSR = 0x4c, /* basic mode control and status */ 174 PHYIDENTIFIER = 0x50, /* phy identifier */ 175 ANARANLPAR = 0x54, /* auto-negotiation advertisement and link 176 partner ability */ 177 ANEROCR = 0x58, /* auto-negotiation expansion and pci conf. */ 178 BPREMRPSR = 0x5c, /* bypass & receive error mask and phy status */ 179 }; 180 181 /* Bits in the interrupt status/enable registers. */ 182 /* The bits in the Intr Status/Enable registers, mostly interrupt sources. */ 183 enum intr_status_bits { 184 RFCON = 0x00020000, /* receive flow control xon packet */ 185 RFCOFF = 0x00010000, /* receive flow control xoff packet */ 186 LSCStatus = 0x00008000, /* link status change */ 187 ANCStatus = 0x00004000, /* autonegotiation completed */ 188 FBE = 0x00002000, /* fatal bus error */ 189 FBEMask = 0x00001800, /* mask bit12-11 */ 190 ParityErr = 0x00000000, /* parity error */ 191 TargetErr = 0x00001000, /* target abort */ 192 MasterErr = 0x00000800, /* master error */ 193 TUNF = 0x00000400, /* transmit underflow */ 194 ROVF = 0x00000200, /* receive overflow */ 195 ETI = 0x00000100, /* transmit early int */ 196 ERI = 0x00000080, /* receive early int */ 197 CNTOVF = 0x00000040, /* counter overflow */ 198 RBU = 0x00000020, /* receive buffer unavailable */ 199 TBU = 0x00000010, /* transmit buffer unavilable */ 200 TI = 0x00000008, /* transmit interrupt */ 201 RI = 0x00000004, /* receive interrupt */ 202 RxErr = 0x00000002, /* receive error */ 203 }; 204 205 /* Bits in the NetworkConfig register, W for writing, R for reading */ 206 /* FIXME: some names are invented by me. Marked with (name?) */ 207 /* If you have docs and know bit names, please fix 'em */ 208 enum rx_mode_bits { 209 CR_W_ENH = 0x02000000, /* enhanced mode (name?) */ 210 CR_W_FD = 0x00100000, /* full duplex */ 211 CR_W_PS10 = 0x00080000, /* 10 mbit */ 212 CR_W_TXEN = 0x00040000, /* tx enable (name?) */ 213 CR_W_PS1000 = 0x00010000, /* 1000 mbit */ 214 /* CR_W_RXBURSTMASK= 0x00000e00, Im unsure about this */ 215 CR_W_RXMODEMASK = 0x000000e0, 216 CR_W_PROM = 0x00000080, /* promiscuous mode */ 217 CR_W_AB = 0x00000040, /* accept broadcast */ 218 CR_W_AM = 0x00000020, /* accept mutlicast */ 219 CR_W_ARP = 0x00000008, /* receive runt pkt */ 220 CR_W_ALP = 0x00000004, /* receive long pkt */ 221 CR_W_SEP = 0x00000002, /* receive error pkt */ 222 CR_W_RXEN = 0x00000001, /* rx enable (unicast?) (name?) */ 223 224 CR_R_TXSTOP = 0x04000000, /* tx stopped (name?) */ 225 CR_R_FD = 0x00100000, /* full duplex detected */ 226 CR_R_PS10 = 0x00080000, /* 10 mbit detected */ 227 CR_R_RXSTOP = 0x00008000, /* rx stopped (name?) */ 228 }; 229 230 /* The Tulip Rx and Tx buffer descriptors. */ 231 struct fealnx_desc { 232 s32 status; 233 s32 control; 234 u32 buffer; 235 u32 next_desc; 236 struct fealnx_desc *next_desc_logical; 237 struct sk_buff *skbuff; 238 u32 reserved1; 239 u32 reserved2; 240 }; 241 242 /* Bits in network_desc.status */ 243 enum rx_desc_status_bits { 244 RXOWN = 0x80000000, /* own bit */ 245 FLNGMASK = 0x0fff0000, /* frame length */ 246 FLNGShift = 16, 247 MARSTATUS = 0x00004000, /* multicast address received */ 248 BARSTATUS = 0x00002000, /* broadcast address received */ 249 PHYSTATUS = 0x00001000, /* physical address received */ 250 RXFSD = 0x00000800, /* first descriptor */ 251 RXLSD = 0x00000400, /* last descriptor */ 252 ErrorSummary = 0x80, /* error summary */ 253 RUNTPKT = 0x40, /* runt packet received */ 254 LONGPKT = 0x20, /* long packet received */ 255 FAE = 0x10, /* frame align error */ 256 CRC = 0x08, /* crc error */ 257 RXER = 0x04, /* receive error */ 258 }; 259 260 enum rx_desc_control_bits { 261 RXIC = 0x00800000, /* interrupt control */ 262 RBSShift = 0, 263 }; 264 265 enum tx_desc_status_bits { 266 TXOWN = 0x80000000, /* own bit */ 267 JABTO = 0x00004000, /* jabber timeout */ 268 CSL = 0x00002000, /* carrier sense lost */ 269 LC = 0x00001000, /* late collision */ 270 EC = 0x00000800, /* excessive collision */ 271 UDF = 0x00000400, /* fifo underflow */ 272 DFR = 0x00000200, /* deferred */ 273 HF = 0x00000100, /* heartbeat fail */ 274 NCRMask = 0x000000ff, /* collision retry count */ 275 NCRShift = 0, 276 }; 277 278 enum tx_desc_control_bits { 279 TXIC = 0x80000000, /* interrupt control */ 280 ETIControl = 0x40000000, /* early transmit interrupt */ 281 TXLD = 0x20000000, /* last descriptor */ 282 TXFD = 0x10000000, /* first descriptor */ 283 CRCEnable = 0x08000000, /* crc control */ 284 PADEnable = 0x04000000, /* padding control */ 285 RetryTxLC = 0x02000000, /* retry late collision */ 286 PKTSMask = 0x3ff800, /* packet size bit21-11 */ 287 PKTSShift = 11, 288 TBSMask = 0x000007ff, /* transmit buffer bit 10-0 */ 289 TBSShift = 0, 290 }; 291 292 /* BootROM/EEPROM/MII Management Register */ 293 #define MASK_MIIR_MII_READ 0x00000000 294 #define MASK_MIIR_MII_WRITE 0x00000008 295 #define MASK_MIIR_MII_MDO 0x00000004 296 #define MASK_MIIR_MII_MDI 0x00000002 297 #define MASK_MIIR_MII_MDC 0x00000001 298 299 /* ST+OP+PHYAD+REGAD+TA */ 300 #define OP_READ 0x6000 /* ST:01+OP:10+PHYAD+REGAD+TA:Z0 */ 301 #define OP_WRITE 0x5002 /* ST:01+OP:01+PHYAD+REGAD+TA:10 */ 302 303 /* ------------------------------------------------------------------------- */ 304 /* Constants for Myson PHY */ 305 /* ------------------------------------------------------------------------- */ 306 #define MysonPHYID 0xd0000302 307 /* 89-7-27 add, (begin) */ 308 #define MysonPHYID0 0x0302 309 #define StatusRegister 18 310 #define SPEED100 0x0400 // bit10 311 #define FULLMODE 0x0800 // bit11 312 /* 89-7-27 add, (end) */ 313 314 /* ------------------------------------------------------------------------- */ 315 /* Constants for Seeq 80225 PHY */ 316 /* ------------------------------------------------------------------------- */ 317 #define SeeqPHYID0 0x0016 318 319 #define MIIRegister18 18 320 #define SPD_DET_100 0x80 321 #define DPLX_DET_FULL 0x40 322 323 /* ------------------------------------------------------------------------- */ 324 /* Constants for Ahdoc 101 PHY */ 325 /* ------------------------------------------------------------------------- */ 326 #define AhdocPHYID0 0x0022 327 328 #define DiagnosticReg 18 329 #define DPLX_FULL 0x0800 330 #define Speed_100 0x0400 331 332 /* 89/6/13 add, */ 333 /* -------------------------------------------------------------------------- */ 334 /* Constants */ 335 /* -------------------------------------------------------------------------- */ 336 #define MarvellPHYID0 0x0141 337 #define LevelOnePHYID0 0x0013 338 339 #define MII1000BaseTControlReg 9 340 #define MII1000BaseTStatusReg 10 341 #define SpecificReg 17 342 343 /* for 1000BaseT Control Register */ 344 #define PHYAbletoPerform1000FullDuplex 0x0200 345 #define PHYAbletoPerform1000HalfDuplex 0x0100 346 #define PHY1000AbilityMask 0x300 347 348 // for phy specific status register, marvell phy. 349 #define SpeedMask 0x0c000 350 #define Speed_1000M 0x08000 351 #define Speed_100M 0x4000 352 #define Speed_10M 0 353 #define Full_Duplex 0x2000 354 355 // 89/12/29 add, for phy specific status register, levelone phy, (begin) 356 #define LXT1000_100M 0x08000 357 #define LXT1000_1000M 0x0c000 358 #define LXT1000_Full 0x200 359 // 89/12/29 add, for phy specific status register, levelone phy, (end) 360 361 /* for 3-in-1 case, BMCRSR register */ 362 #define LinkIsUp2 0x00040000 363 364 /* for PHY */ 365 #define LinkIsUp 0x0004 366 367 368 struct netdev_private { 369 /* Descriptor rings first for alignment. */ 370 struct fealnx_desc *rx_ring; 371 struct fealnx_desc *tx_ring; 372 373 dma_addr_t rx_ring_dma; 374 dma_addr_t tx_ring_dma; 375 376 spinlock_t lock; 377 378 /* Media monitoring timer. */ 379 struct timer_list timer; 380 381 /* Reset timer */ 382 struct timer_list reset_timer; 383 int reset_timer_armed; 384 unsigned long crvalue_sv; 385 unsigned long imrvalue_sv; 386 387 /* Frequently used values: keep some adjacent for cache effect. */ 388 int flags; 389 struct pci_dev *pci_dev; 390 unsigned long crvalue; 391 unsigned long bcrvalue; 392 unsigned long imrvalue; 393 struct fealnx_desc *cur_rx; 394 struct fealnx_desc *lack_rxbuf; 395 int really_rx_count; 396 struct fealnx_desc *cur_tx; 397 struct fealnx_desc *cur_tx_copy; 398 int really_tx_count; 399 int free_tx_count; 400 unsigned int rx_buf_sz; /* Based on MTU+slack. */ 401 402 /* These values are keep track of the transceiver/media in use. */ 403 unsigned int linkok; 404 unsigned int line_speed; 405 unsigned int duplexmode; 406 unsigned int default_port:4; /* Last dev->if_port value. */ 407 unsigned int PHYType; 408 409 /* MII transceiver section. */ 410 int mii_cnt; /* MII device addresses. */ 411 unsigned char phys[2]; /* MII device addresses. */ 412 struct mii_if_info mii; 413 void __iomem *mem; 414 }; 415 416 417 static int mdio_read(struct net_device *dev, int phy_id, int location); 418 static void mdio_write(struct net_device *dev, int phy_id, int location, int value); 419 static int netdev_open(struct net_device *dev); 420 static void getlinktype(struct net_device *dev); 421 static void getlinkstatus(struct net_device *dev); 422 static void netdev_timer(struct timer_list *t); 423 static void reset_timer(struct timer_list *t); 424 static void fealnx_tx_timeout(struct net_device *dev, unsigned int txqueue); 425 static void init_ring(struct net_device *dev); 426 static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev); 427 static irqreturn_t intr_handler(int irq, void *dev_instance); 428 static int netdev_rx(struct net_device *dev); 429 static void set_rx_mode(struct net_device *dev); 430 static void __set_rx_mode(struct net_device *dev); 431 static struct net_device_stats *get_stats(struct net_device *dev); 432 static int mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); 433 static const struct ethtool_ops netdev_ethtool_ops; 434 static int netdev_close(struct net_device *dev); 435 static void reset_rx_descriptors(struct net_device *dev); 436 static void reset_tx_descriptors(struct net_device *dev); 437 438 static void stop_nic_rx(void __iomem *ioaddr, long crvalue) 439 { 440 int delay = 0x1000; 441 iowrite32(crvalue & ~(CR_W_RXEN), ioaddr + TCRRCR); 442 while (--delay) { 443 if ( (ioread32(ioaddr + TCRRCR) & CR_R_RXSTOP) == CR_R_RXSTOP) 444 break; 445 } 446 } 447 448 449 static void stop_nic_rxtx(void __iomem *ioaddr, long crvalue) 450 { 451 int delay = 0x1000; 452 iowrite32(crvalue & ~(CR_W_RXEN+CR_W_TXEN), ioaddr + TCRRCR); 453 while (--delay) { 454 if ( (ioread32(ioaddr + TCRRCR) & (CR_R_RXSTOP+CR_R_TXSTOP)) 455 == (CR_R_RXSTOP+CR_R_TXSTOP) ) 456 break; 457 } 458 } 459 460 static const struct net_device_ops netdev_ops = { 461 .ndo_open = netdev_open, 462 .ndo_stop = netdev_close, 463 .ndo_start_xmit = start_tx, 464 .ndo_get_stats = get_stats, 465 .ndo_set_rx_mode = set_rx_mode, 466 .ndo_eth_ioctl = mii_ioctl, 467 .ndo_tx_timeout = fealnx_tx_timeout, 468 .ndo_set_mac_address = eth_mac_addr, 469 .ndo_validate_addr = eth_validate_addr, 470 }; 471 472 static int fealnx_init_one(struct pci_dev *pdev, 473 const struct pci_device_id *ent) 474 { 475 struct netdev_private *np; 476 int i, option, err, irq; 477 static int card_idx = -1; 478 char boardname[12]; 479 void __iomem *ioaddr; 480 unsigned long len; 481 unsigned int chip_id = ent->driver_data; 482 struct net_device *dev; 483 void *ring_space; 484 dma_addr_t ring_dma; 485 #ifdef USE_IO_OPS 486 int bar = 0; 487 #else 488 int bar = 1; 489 #endif 490 491 card_idx++; 492 sprintf(boardname, "fealnx%d", card_idx); 493 494 option = card_idx < MAX_UNITS ? options[card_idx] : 0; 495 496 i = pci_enable_device(pdev); 497 if (i) return i; 498 pci_set_master(pdev); 499 500 len = pci_resource_len(pdev, bar); 501 if (len < MIN_REGION_SIZE) { 502 dev_err(&pdev->dev, 503 "region size %ld too small, aborting\n", len); 504 return -ENODEV; 505 } 506 507 i = pci_request_regions(pdev, boardname); 508 if (i) 509 return i; 510 511 irq = pdev->irq; 512 513 ioaddr = pci_iomap(pdev, bar, len); 514 if (!ioaddr) { 515 err = -ENOMEM; 516 goto err_out_res; 517 } 518 519 dev = alloc_etherdev(sizeof(struct netdev_private)); 520 if (!dev) { 521 err = -ENOMEM; 522 goto err_out_unmap; 523 } 524 SET_NETDEV_DEV(dev, &pdev->dev); 525 526 /* read ethernet id */ 527 for (i = 0; i < 6; ++i) 528 dev->dev_addr[i] = ioread8(ioaddr + PAR0 + i); 529 530 /* Reset the chip to erase previous misconfiguration. */ 531 iowrite32(0x00000001, ioaddr + BCR); 532 533 /* Make certain the descriptor lists are aligned. */ 534 np = netdev_priv(dev); 535 np->mem = ioaddr; 536 spin_lock_init(&np->lock); 537 np->pci_dev = pdev; 538 np->flags = skel_netdrv_tbl[chip_id].flags; 539 pci_set_drvdata(pdev, dev); 540 np->mii.dev = dev; 541 np->mii.mdio_read = mdio_read; 542 np->mii.mdio_write = mdio_write; 543 np->mii.phy_id_mask = 0x1f; 544 np->mii.reg_num_mask = 0x1f; 545 546 ring_space = dma_alloc_coherent(&pdev->dev, RX_TOTAL_SIZE, &ring_dma, 547 GFP_KERNEL); 548 if (!ring_space) { 549 err = -ENOMEM; 550 goto err_out_free_dev; 551 } 552 np->rx_ring = ring_space; 553 np->rx_ring_dma = ring_dma; 554 555 ring_space = dma_alloc_coherent(&pdev->dev, TX_TOTAL_SIZE, &ring_dma, 556 GFP_KERNEL); 557 if (!ring_space) { 558 err = -ENOMEM; 559 goto err_out_free_rx; 560 } 561 np->tx_ring = ring_space; 562 np->tx_ring_dma = ring_dma; 563 564 /* find the connected MII xcvrs */ 565 if (np->flags == HAS_MII_XCVR) { 566 int phy, phy_idx = 0; 567 568 for (phy = 1; phy < 32 && phy_idx < ARRAY_SIZE(np->phys); 569 phy++) { 570 int mii_status = mdio_read(dev, phy, 1); 571 572 if (mii_status != 0xffff && mii_status != 0x0000) { 573 np->phys[phy_idx++] = phy; 574 dev_info(&pdev->dev, 575 "MII PHY found at address %d, status " 576 "0x%4.4x.\n", phy, mii_status); 577 /* get phy type */ 578 { 579 unsigned int data; 580 581 data = mdio_read(dev, np->phys[0], 2); 582 if (data == SeeqPHYID0) 583 np->PHYType = SeeqPHY; 584 else if (data == AhdocPHYID0) 585 np->PHYType = AhdocPHY; 586 else if (data == MarvellPHYID0) 587 np->PHYType = MarvellPHY; 588 else if (data == MysonPHYID0) 589 np->PHYType = Myson981; 590 else if (data == LevelOnePHYID0) 591 np->PHYType = LevelOnePHY; 592 else 593 np->PHYType = OtherPHY; 594 } 595 } 596 } 597 598 np->mii_cnt = phy_idx; 599 if (phy_idx == 0) 600 dev_warn(&pdev->dev, 601 "MII PHY not found -- this device may " 602 "not operate correctly.\n"); 603 } else { 604 np->phys[0] = 32; 605 /* 89/6/23 add, (begin) */ 606 /* get phy type */ 607 if (ioread32(ioaddr + PHYIDENTIFIER) == MysonPHYID) 608 np->PHYType = MysonPHY; 609 else 610 np->PHYType = OtherPHY; 611 } 612 np->mii.phy_id = np->phys[0]; 613 614 if (dev->mem_start) 615 option = dev->mem_start; 616 617 /* The lower four bits are the media type. */ 618 if (option > 0) { 619 if (option & 0x200) 620 np->mii.full_duplex = 1; 621 np->default_port = option & 15; 622 } 623 624 if (card_idx < MAX_UNITS && full_duplex[card_idx] > 0) 625 np->mii.full_duplex = full_duplex[card_idx]; 626 627 if (np->mii.full_duplex) { 628 dev_info(&pdev->dev, "Media type forced to Full Duplex.\n"); 629 /* 89/6/13 add, (begin) */ 630 // if (np->PHYType==MarvellPHY) 631 if ((np->PHYType == MarvellPHY) || (np->PHYType == LevelOnePHY)) { 632 unsigned int data; 633 634 data = mdio_read(dev, np->phys[0], 9); 635 data = (data & 0xfcff) | 0x0200; 636 mdio_write(dev, np->phys[0], 9, data); 637 } 638 /* 89/6/13 add, (end) */ 639 if (np->flags == HAS_MII_XCVR) 640 mdio_write(dev, np->phys[0], MII_ADVERTISE, ADVERTISE_FULL); 641 else 642 iowrite32(ADVERTISE_FULL, ioaddr + ANARANLPAR); 643 np->mii.force_media = 1; 644 } 645 646 dev->netdev_ops = &netdev_ops; 647 dev->ethtool_ops = &netdev_ethtool_ops; 648 dev->watchdog_timeo = TX_TIMEOUT; 649 650 err = register_netdev(dev); 651 if (err) 652 goto err_out_free_tx; 653 654 printk(KERN_INFO "%s: %s at %p, %pM, IRQ %d.\n", 655 dev->name, skel_netdrv_tbl[chip_id].chip_name, ioaddr, 656 dev->dev_addr, irq); 657 658 return 0; 659 660 err_out_free_tx: 661 dma_free_coherent(&pdev->dev, TX_TOTAL_SIZE, np->tx_ring, 662 np->tx_ring_dma); 663 err_out_free_rx: 664 dma_free_coherent(&pdev->dev, RX_TOTAL_SIZE, np->rx_ring, 665 np->rx_ring_dma); 666 err_out_free_dev: 667 free_netdev(dev); 668 err_out_unmap: 669 pci_iounmap(pdev, ioaddr); 670 err_out_res: 671 pci_release_regions(pdev); 672 return err; 673 } 674 675 676 static void fealnx_remove_one(struct pci_dev *pdev) 677 { 678 struct net_device *dev = pci_get_drvdata(pdev); 679 680 if (dev) { 681 struct netdev_private *np = netdev_priv(dev); 682 683 dma_free_coherent(&pdev->dev, TX_TOTAL_SIZE, np->tx_ring, 684 np->tx_ring_dma); 685 dma_free_coherent(&pdev->dev, RX_TOTAL_SIZE, np->rx_ring, 686 np->rx_ring_dma); 687 unregister_netdev(dev); 688 pci_iounmap(pdev, np->mem); 689 free_netdev(dev); 690 pci_release_regions(pdev); 691 } else 692 printk(KERN_ERR "fealnx: remove for unknown device\n"); 693 } 694 695 696 static ulong m80x_send_cmd_to_phy(void __iomem *miiport, int opcode, int phyad, int regad) 697 { 698 ulong miir; 699 int i; 700 unsigned int mask, data; 701 702 /* enable MII output */ 703 miir = (ulong) ioread32(miiport); 704 miir &= 0xfffffff0; 705 706 miir |= MASK_MIIR_MII_WRITE + MASK_MIIR_MII_MDO; 707 708 /* send 32 1's preamble */ 709 for (i = 0; i < 32; i++) { 710 /* low MDC; MDO is already high (miir) */ 711 miir &= ~MASK_MIIR_MII_MDC; 712 iowrite32(miir, miiport); 713 714 /* high MDC */ 715 miir |= MASK_MIIR_MII_MDC; 716 iowrite32(miir, miiport); 717 } 718 719 /* calculate ST+OP+PHYAD+REGAD+TA */ 720 data = opcode | (phyad << 7) | (regad << 2); 721 722 /* sent out */ 723 mask = 0x8000; 724 while (mask) { 725 /* low MDC, prepare MDO */ 726 miir &= ~(MASK_MIIR_MII_MDC + MASK_MIIR_MII_MDO); 727 if (mask & data) 728 miir |= MASK_MIIR_MII_MDO; 729 730 iowrite32(miir, miiport); 731 /* high MDC */ 732 miir |= MASK_MIIR_MII_MDC; 733 iowrite32(miir, miiport); 734 udelay(30); 735 736 /* next */ 737 mask >>= 1; 738 if (mask == 0x2 && opcode == OP_READ) 739 miir &= ~MASK_MIIR_MII_WRITE; 740 } 741 return miir; 742 } 743 744 745 static int mdio_read(struct net_device *dev, int phyad, int regad) 746 { 747 struct netdev_private *np = netdev_priv(dev); 748 void __iomem *miiport = np->mem + MANAGEMENT; 749 ulong miir; 750 unsigned int mask, data; 751 752 miir = m80x_send_cmd_to_phy(miiport, OP_READ, phyad, regad); 753 754 /* read data */ 755 mask = 0x8000; 756 data = 0; 757 while (mask) { 758 /* low MDC */ 759 miir &= ~MASK_MIIR_MII_MDC; 760 iowrite32(miir, miiport); 761 762 /* read MDI */ 763 miir = ioread32(miiport); 764 if (miir & MASK_MIIR_MII_MDI) 765 data |= mask; 766 767 /* high MDC, and wait */ 768 miir |= MASK_MIIR_MII_MDC; 769 iowrite32(miir, miiport); 770 udelay(30); 771 772 /* next */ 773 mask >>= 1; 774 } 775 776 /* low MDC */ 777 miir &= ~MASK_MIIR_MII_MDC; 778 iowrite32(miir, miiport); 779 780 return data & 0xffff; 781 } 782 783 784 static void mdio_write(struct net_device *dev, int phyad, int regad, int data) 785 { 786 struct netdev_private *np = netdev_priv(dev); 787 void __iomem *miiport = np->mem + MANAGEMENT; 788 ulong miir; 789 unsigned int mask; 790 791 miir = m80x_send_cmd_to_phy(miiport, OP_WRITE, phyad, regad); 792 793 /* write data */ 794 mask = 0x8000; 795 while (mask) { 796 /* low MDC, prepare MDO */ 797 miir &= ~(MASK_MIIR_MII_MDC + MASK_MIIR_MII_MDO); 798 if (mask & data) 799 miir |= MASK_MIIR_MII_MDO; 800 iowrite32(miir, miiport); 801 802 /* high MDC */ 803 miir |= MASK_MIIR_MII_MDC; 804 iowrite32(miir, miiport); 805 806 /* next */ 807 mask >>= 1; 808 } 809 810 /* low MDC */ 811 miir &= ~MASK_MIIR_MII_MDC; 812 iowrite32(miir, miiport); 813 } 814 815 816 static int netdev_open(struct net_device *dev) 817 { 818 struct netdev_private *np = netdev_priv(dev); 819 void __iomem *ioaddr = np->mem; 820 const int irq = np->pci_dev->irq; 821 int rc, i; 822 823 iowrite32(0x00000001, ioaddr + BCR); /* Reset */ 824 825 rc = request_irq(irq, intr_handler, IRQF_SHARED, dev->name, dev); 826 if (rc) 827 return -EAGAIN; 828 829 for (i = 0; i < 3; i++) 830 iowrite16(((unsigned short*)dev->dev_addr)[i], 831 ioaddr + PAR0 + i*2); 832 833 init_ring(dev); 834 835 iowrite32(np->rx_ring_dma, ioaddr + RXLBA); 836 iowrite32(np->tx_ring_dma, ioaddr + TXLBA); 837 838 /* Initialize other registers. */ 839 /* Configure the PCI bus bursts and FIFO thresholds. 840 486: Set 8 longword burst. 841 586: no burst limit. 842 Burst length 5:3 843 0 0 0 1 844 0 0 1 4 845 0 1 0 8 846 0 1 1 16 847 1 0 0 32 848 1 0 1 64 849 1 1 0 128 850 1 1 1 256 851 Wait the specified 50 PCI cycles after a reset by initializing 852 Tx and Rx queues and the address filter list. 853 FIXME (Ueimor): optimistic for alpha + posted writes ? */ 854 855 np->bcrvalue = 0x10; /* little-endian, 8 burst length */ 856 #ifdef __BIG_ENDIAN 857 np->bcrvalue |= 0x04; /* big-endian */ 858 #endif 859 860 #if defined(__i386__) && !defined(MODULE) 861 if (boot_cpu_data.x86 <= 4) 862 np->crvalue = 0xa00; 863 else 864 #endif 865 np->crvalue = 0xe00; /* rx 128 burst length */ 866 867 868 // 89/12/29 add, 869 // 90/1/16 modify, 870 // np->imrvalue=FBE|TUNF|CNTOVF|RBU|TI|RI; 871 np->imrvalue = TUNF | CNTOVF | RBU | TI | RI; 872 if (np->pci_dev->device == 0x891) { 873 np->bcrvalue |= 0x200; /* set PROG bit */ 874 np->crvalue |= CR_W_ENH; /* set enhanced bit */ 875 np->imrvalue |= ETI; 876 } 877 iowrite32(np->bcrvalue, ioaddr + BCR); 878 879 if (dev->if_port == 0) 880 dev->if_port = np->default_port; 881 882 iowrite32(0, ioaddr + RXPDR); 883 // 89/9/1 modify, 884 // np->crvalue = 0x00e40001; /* tx store and forward, tx/rx enable */ 885 np->crvalue |= 0x00e40001; /* tx store and forward, tx/rx enable */ 886 np->mii.full_duplex = np->mii.force_media; 887 getlinkstatus(dev); 888 if (np->linkok) 889 getlinktype(dev); 890 __set_rx_mode(dev); 891 892 netif_start_queue(dev); 893 894 /* Clear and Enable interrupts by setting the interrupt mask. */ 895 iowrite32(FBE | TUNF | CNTOVF | RBU | TI | RI, ioaddr + ISR); 896 iowrite32(np->imrvalue, ioaddr + IMR); 897 898 if (debug) 899 printk(KERN_DEBUG "%s: Done netdev_open().\n", dev->name); 900 901 /* Set the timer to check for link beat. */ 902 timer_setup(&np->timer, netdev_timer, 0); 903 np->timer.expires = RUN_AT(3 * HZ); 904 905 /* timer handler */ 906 add_timer(&np->timer); 907 908 timer_setup(&np->reset_timer, reset_timer, 0); 909 np->reset_timer_armed = 0; 910 return rc; 911 } 912 913 914 static void getlinkstatus(struct net_device *dev) 915 /* function: Routine will read MII Status Register to get link status. */ 916 /* input : dev... pointer to the adapter block. */ 917 /* output : none. */ 918 { 919 struct netdev_private *np = netdev_priv(dev); 920 unsigned int i, DelayTime = 0x1000; 921 922 np->linkok = 0; 923 924 if (np->PHYType == MysonPHY) { 925 for (i = 0; i < DelayTime; ++i) { 926 if (ioread32(np->mem + BMCRSR) & LinkIsUp2) { 927 np->linkok = 1; 928 return; 929 } 930 udelay(100); 931 } 932 } else { 933 for (i = 0; i < DelayTime; ++i) { 934 if (mdio_read(dev, np->phys[0], MII_BMSR) & BMSR_LSTATUS) { 935 np->linkok = 1; 936 return; 937 } 938 udelay(100); 939 } 940 } 941 } 942 943 944 static void getlinktype(struct net_device *dev) 945 { 946 struct netdev_private *np = netdev_priv(dev); 947 948 if (np->PHYType == MysonPHY) { /* 3-in-1 case */ 949 if (ioread32(np->mem + TCRRCR) & CR_R_FD) 950 np->duplexmode = 2; /* full duplex */ 951 else 952 np->duplexmode = 1; /* half duplex */ 953 if (ioread32(np->mem + TCRRCR) & CR_R_PS10) 954 np->line_speed = 1; /* 10M */ 955 else 956 np->line_speed = 2; /* 100M */ 957 } else { 958 if (np->PHYType == SeeqPHY) { /* this PHY is SEEQ 80225 */ 959 unsigned int data; 960 961 data = mdio_read(dev, np->phys[0], MIIRegister18); 962 if (data & SPD_DET_100) 963 np->line_speed = 2; /* 100M */ 964 else 965 np->line_speed = 1; /* 10M */ 966 if (data & DPLX_DET_FULL) 967 np->duplexmode = 2; /* full duplex mode */ 968 else 969 np->duplexmode = 1; /* half duplex mode */ 970 } else if (np->PHYType == AhdocPHY) { 971 unsigned int data; 972 973 data = mdio_read(dev, np->phys[0], DiagnosticReg); 974 if (data & Speed_100) 975 np->line_speed = 2; /* 100M */ 976 else 977 np->line_speed = 1; /* 10M */ 978 if (data & DPLX_FULL) 979 np->duplexmode = 2; /* full duplex mode */ 980 else 981 np->duplexmode = 1; /* half duplex mode */ 982 } 983 /* 89/6/13 add, (begin) */ 984 else if (np->PHYType == MarvellPHY) { 985 unsigned int data; 986 987 data = mdio_read(dev, np->phys[0], SpecificReg); 988 if (data & Full_Duplex) 989 np->duplexmode = 2; /* full duplex mode */ 990 else 991 np->duplexmode = 1; /* half duplex mode */ 992 data &= SpeedMask; 993 if (data == Speed_1000M) 994 np->line_speed = 3; /* 1000M */ 995 else if (data == Speed_100M) 996 np->line_speed = 2; /* 100M */ 997 else 998 np->line_speed = 1; /* 10M */ 999 } 1000 /* 89/6/13 add, (end) */ 1001 /* 89/7/27 add, (begin) */ 1002 else if (np->PHYType == Myson981) { 1003 unsigned int data; 1004 1005 data = mdio_read(dev, np->phys[0], StatusRegister); 1006 1007 if (data & SPEED100) 1008 np->line_speed = 2; 1009 else 1010 np->line_speed = 1; 1011 1012 if (data & FULLMODE) 1013 np->duplexmode = 2; 1014 else 1015 np->duplexmode = 1; 1016 } 1017 /* 89/7/27 add, (end) */ 1018 /* 89/12/29 add */ 1019 else if (np->PHYType == LevelOnePHY) { 1020 unsigned int data; 1021 1022 data = mdio_read(dev, np->phys[0], SpecificReg); 1023 if (data & LXT1000_Full) 1024 np->duplexmode = 2; /* full duplex mode */ 1025 else 1026 np->duplexmode = 1; /* half duplex mode */ 1027 data &= SpeedMask; 1028 if (data == LXT1000_1000M) 1029 np->line_speed = 3; /* 1000M */ 1030 else if (data == LXT1000_100M) 1031 np->line_speed = 2; /* 100M */ 1032 else 1033 np->line_speed = 1; /* 10M */ 1034 } 1035 np->crvalue &= (~CR_W_PS10) & (~CR_W_FD) & (~CR_W_PS1000); 1036 if (np->line_speed == 1) 1037 np->crvalue |= CR_W_PS10; 1038 else if (np->line_speed == 3) 1039 np->crvalue |= CR_W_PS1000; 1040 if (np->duplexmode == 2) 1041 np->crvalue |= CR_W_FD; 1042 } 1043 } 1044 1045 1046 /* Take lock before calling this */ 1047 static void allocate_rx_buffers(struct net_device *dev) 1048 { 1049 struct netdev_private *np = netdev_priv(dev); 1050 1051 /* allocate skb for rx buffers */ 1052 while (np->really_rx_count != RX_RING_SIZE) { 1053 struct sk_buff *skb; 1054 1055 skb = netdev_alloc_skb(dev, np->rx_buf_sz); 1056 if (skb == NULL) 1057 break; /* Better luck next round. */ 1058 1059 while (np->lack_rxbuf->skbuff) 1060 np->lack_rxbuf = np->lack_rxbuf->next_desc_logical; 1061 1062 np->lack_rxbuf->skbuff = skb; 1063 np->lack_rxbuf->buffer = dma_map_single(&np->pci_dev->dev, 1064 skb->data, 1065 np->rx_buf_sz, 1066 DMA_FROM_DEVICE); 1067 np->lack_rxbuf->status = RXOWN; 1068 ++np->really_rx_count; 1069 } 1070 } 1071 1072 1073 static void netdev_timer(struct timer_list *t) 1074 { 1075 struct netdev_private *np = from_timer(np, t, timer); 1076 struct net_device *dev = np->mii.dev; 1077 void __iomem *ioaddr = np->mem; 1078 int old_crvalue = np->crvalue; 1079 unsigned int old_linkok = np->linkok; 1080 unsigned long flags; 1081 1082 if (debug) 1083 printk(KERN_DEBUG "%s: Media selection timer tick, status %8.8x " 1084 "config %8.8x.\n", dev->name, ioread32(ioaddr + ISR), 1085 ioread32(ioaddr + TCRRCR)); 1086 1087 spin_lock_irqsave(&np->lock, flags); 1088 1089 if (np->flags == HAS_MII_XCVR) { 1090 getlinkstatus(dev); 1091 if ((old_linkok == 0) && (np->linkok == 1)) { /* we need to detect the media type again */ 1092 getlinktype(dev); 1093 if (np->crvalue != old_crvalue) { 1094 stop_nic_rxtx(ioaddr, np->crvalue); 1095 iowrite32(np->crvalue, ioaddr + TCRRCR); 1096 } 1097 } 1098 } 1099 1100 allocate_rx_buffers(dev); 1101 1102 spin_unlock_irqrestore(&np->lock, flags); 1103 1104 np->timer.expires = RUN_AT(10 * HZ); 1105 add_timer(&np->timer); 1106 } 1107 1108 1109 /* Take lock before calling */ 1110 /* Reset chip and disable rx, tx and interrupts */ 1111 static void reset_and_disable_rxtx(struct net_device *dev) 1112 { 1113 struct netdev_private *np = netdev_priv(dev); 1114 void __iomem *ioaddr = np->mem; 1115 int delay=51; 1116 1117 /* Reset the chip's Tx and Rx processes. */ 1118 stop_nic_rxtx(ioaddr, 0); 1119 1120 /* Disable interrupts by clearing the interrupt mask. */ 1121 iowrite32(0, ioaddr + IMR); 1122 1123 /* Reset the chip to erase previous misconfiguration. */ 1124 iowrite32(0x00000001, ioaddr + BCR); 1125 1126 /* Ueimor: wait for 50 PCI cycles (and flush posted writes btw). 1127 We surely wait too long (address+data phase). Who cares? */ 1128 while (--delay) { 1129 ioread32(ioaddr + BCR); 1130 rmb(); 1131 } 1132 } 1133 1134 1135 /* Take lock before calling */ 1136 /* Restore chip after reset */ 1137 static void enable_rxtx(struct net_device *dev) 1138 { 1139 struct netdev_private *np = netdev_priv(dev); 1140 void __iomem *ioaddr = np->mem; 1141 1142 reset_rx_descriptors(dev); 1143 1144 iowrite32(np->tx_ring_dma + ((char*)np->cur_tx - (char*)np->tx_ring), 1145 ioaddr + TXLBA); 1146 iowrite32(np->rx_ring_dma + ((char*)np->cur_rx - (char*)np->rx_ring), 1147 ioaddr + RXLBA); 1148 1149 iowrite32(np->bcrvalue, ioaddr + BCR); 1150 1151 iowrite32(0, ioaddr + RXPDR); 1152 __set_rx_mode(dev); /* changes np->crvalue, writes it into TCRRCR */ 1153 1154 /* Clear and Enable interrupts by setting the interrupt mask. */ 1155 iowrite32(FBE | TUNF | CNTOVF | RBU | TI | RI, ioaddr + ISR); 1156 iowrite32(np->imrvalue, ioaddr + IMR); 1157 1158 iowrite32(0, ioaddr + TXPDR); 1159 } 1160 1161 1162 static void reset_timer(struct timer_list *t) 1163 { 1164 struct netdev_private *np = from_timer(np, t, reset_timer); 1165 struct net_device *dev = np->mii.dev; 1166 unsigned long flags; 1167 1168 printk(KERN_WARNING "%s: resetting tx and rx machinery\n", dev->name); 1169 1170 spin_lock_irqsave(&np->lock, flags); 1171 np->crvalue = np->crvalue_sv; 1172 np->imrvalue = np->imrvalue_sv; 1173 1174 reset_and_disable_rxtx(dev); 1175 /* works for me without this: 1176 reset_tx_descriptors(dev); */ 1177 enable_rxtx(dev); 1178 netif_start_queue(dev); /* FIXME: or netif_wake_queue(dev); ? */ 1179 1180 np->reset_timer_armed = 0; 1181 1182 spin_unlock_irqrestore(&np->lock, flags); 1183 } 1184 1185 1186 static void fealnx_tx_timeout(struct net_device *dev, unsigned int txqueue) 1187 { 1188 struct netdev_private *np = netdev_priv(dev); 1189 void __iomem *ioaddr = np->mem; 1190 unsigned long flags; 1191 int i; 1192 1193 printk(KERN_WARNING 1194 "%s: Transmit timed out, status %8.8x, resetting...\n", 1195 dev->name, ioread32(ioaddr + ISR)); 1196 1197 { 1198 printk(KERN_DEBUG " Rx ring %p: ", np->rx_ring); 1199 for (i = 0; i < RX_RING_SIZE; i++) 1200 printk(KERN_CONT " %8.8x", 1201 (unsigned int) np->rx_ring[i].status); 1202 printk(KERN_CONT "\n"); 1203 printk(KERN_DEBUG " Tx ring %p: ", np->tx_ring); 1204 for (i = 0; i < TX_RING_SIZE; i++) 1205 printk(KERN_CONT " %4.4x", np->tx_ring[i].status); 1206 printk(KERN_CONT "\n"); 1207 } 1208 1209 spin_lock_irqsave(&np->lock, flags); 1210 1211 reset_and_disable_rxtx(dev); 1212 reset_tx_descriptors(dev); 1213 enable_rxtx(dev); 1214 1215 spin_unlock_irqrestore(&np->lock, flags); 1216 1217 netif_trans_update(dev); /* prevent tx timeout */ 1218 dev->stats.tx_errors++; 1219 netif_wake_queue(dev); /* or .._start_.. ?? */ 1220 } 1221 1222 1223 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */ 1224 static void init_ring(struct net_device *dev) 1225 { 1226 struct netdev_private *np = netdev_priv(dev); 1227 int i; 1228 1229 /* initialize rx variables */ 1230 np->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32); 1231 np->cur_rx = &np->rx_ring[0]; 1232 np->lack_rxbuf = np->rx_ring; 1233 np->really_rx_count = 0; 1234 1235 /* initial rx descriptors. */ 1236 for (i = 0; i < RX_RING_SIZE; i++) { 1237 np->rx_ring[i].status = 0; 1238 np->rx_ring[i].control = np->rx_buf_sz << RBSShift; 1239 np->rx_ring[i].next_desc = np->rx_ring_dma + 1240 (i + 1)*sizeof(struct fealnx_desc); 1241 np->rx_ring[i].next_desc_logical = &np->rx_ring[i + 1]; 1242 np->rx_ring[i].skbuff = NULL; 1243 } 1244 1245 /* for the last rx descriptor */ 1246 np->rx_ring[i - 1].next_desc = np->rx_ring_dma; 1247 np->rx_ring[i - 1].next_desc_logical = np->rx_ring; 1248 1249 /* allocate skb for rx buffers */ 1250 for (i = 0; i < RX_RING_SIZE; i++) { 1251 struct sk_buff *skb = netdev_alloc_skb(dev, np->rx_buf_sz); 1252 1253 if (skb == NULL) { 1254 np->lack_rxbuf = &np->rx_ring[i]; 1255 break; 1256 } 1257 1258 ++np->really_rx_count; 1259 np->rx_ring[i].skbuff = skb; 1260 np->rx_ring[i].buffer = dma_map_single(&np->pci_dev->dev, 1261 skb->data, 1262 np->rx_buf_sz, 1263 DMA_FROM_DEVICE); 1264 np->rx_ring[i].status = RXOWN; 1265 np->rx_ring[i].control |= RXIC; 1266 } 1267 1268 /* initialize tx variables */ 1269 np->cur_tx = &np->tx_ring[0]; 1270 np->cur_tx_copy = &np->tx_ring[0]; 1271 np->really_tx_count = 0; 1272 np->free_tx_count = TX_RING_SIZE; 1273 1274 for (i = 0; i < TX_RING_SIZE; i++) { 1275 np->tx_ring[i].status = 0; 1276 /* do we need np->tx_ring[i].control = XXX; ?? */ 1277 np->tx_ring[i].next_desc = np->tx_ring_dma + 1278 (i + 1)*sizeof(struct fealnx_desc); 1279 np->tx_ring[i].next_desc_logical = &np->tx_ring[i + 1]; 1280 np->tx_ring[i].skbuff = NULL; 1281 } 1282 1283 /* for the last tx descriptor */ 1284 np->tx_ring[i - 1].next_desc = np->tx_ring_dma; 1285 np->tx_ring[i - 1].next_desc_logical = &np->tx_ring[0]; 1286 } 1287 1288 1289 static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev) 1290 { 1291 struct netdev_private *np = netdev_priv(dev); 1292 unsigned long flags; 1293 1294 spin_lock_irqsave(&np->lock, flags); 1295 1296 np->cur_tx_copy->skbuff = skb; 1297 1298 #define one_buffer 1299 #define BPT 1022 1300 #if defined(one_buffer) 1301 np->cur_tx_copy->buffer = dma_map_single(&np->pci_dev->dev, skb->data, 1302 skb->len, DMA_TO_DEVICE); 1303 np->cur_tx_copy->control = TXIC | TXLD | TXFD | CRCEnable | PADEnable; 1304 np->cur_tx_copy->control |= (skb->len << PKTSShift); /* pkt size */ 1305 np->cur_tx_copy->control |= (skb->len << TBSShift); /* buffer size */ 1306 // 89/12/29 add, 1307 if (np->pci_dev->device == 0x891) 1308 np->cur_tx_copy->control |= ETIControl | RetryTxLC; 1309 np->cur_tx_copy->status = TXOWN; 1310 np->cur_tx_copy = np->cur_tx_copy->next_desc_logical; 1311 --np->free_tx_count; 1312 #elif defined(two_buffer) 1313 if (skb->len > BPT) { 1314 struct fealnx_desc *next; 1315 1316 /* for the first descriptor */ 1317 np->cur_tx_copy->buffer = dma_map_single(&np->pci_dev->dev, 1318 skb->data, BPT, 1319 DMA_TO_DEVICE); 1320 np->cur_tx_copy->control = TXIC | TXFD | CRCEnable | PADEnable; 1321 np->cur_tx_copy->control |= (skb->len << PKTSShift); /* pkt size */ 1322 np->cur_tx_copy->control |= (BPT << TBSShift); /* buffer size */ 1323 1324 /* for the last descriptor */ 1325 next = np->cur_tx_copy->next_desc_logical; 1326 next->skbuff = skb; 1327 next->control = TXIC | TXLD | CRCEnable | PADEnable; 1328 next->control |= (skb->len << PKTSShift); /* pkt size */ 1329 next->control |= ((skb->len - BPT) << TBSShift); /* buf size */ 1330 // 89/12/29 add, 1331 if (np->pci_dev->device == 0x891) 1332 np->cur_tx_copy->control |= ETIControl | RetryTxLC; 1333 next->buffer = dma_map_single(&ep->pci_dev->dev, 1334 skb->data + BPT, skb->len - BPT, 1335 DMA_TO_DEVICE); 1336 1337 next->status = TXOWN; 1338 np->cur_tx_copy->status = TXOWN; 1339 1340 np->cur_tx_copy = next->next_desc_logical; 1341 np->free_tx_count -= 2; 1342 } else { 1343 np->cur_tx_copy->buffer = dma_map_single(&np->pci_dev->dev, 1344 skb->data, skb->len, 1345 DMA_TO_DEVICE); 1346 np->cur_tx_copy->control = TXIC | TXLD | TXFD | CRCEnable | PADEnable; 1347 np->cur_tx_copy->control |= (skb->len << PKTSShift); /* pkt size */ 1348 np->cur_tx_copy->control |= (skb->len << TBSShift); /* buffer size */ 1349 // 89/12/29 add, 1350 if (np->pci_dev->device == 0x891) 1351 np->cur_tx_copy->control |= ETIControl | RetryTxLC; 1352 np->cur_tx_copy->status = TXOWN; 1353 np->cur_tx_copy = np->cur_tx_copy->next_desc_logical; 1354 --np->free_tx_count; 1355 } 1356 #endif 1357 1358 if (np->free_tx_count < 2) 1359 netif_stop_queue(dev); 1360 ++np->really_tx_count; 1361 iowrite32(0, np->mem + TXPDR); 1362 1363 spin_unlock_irqrestore(&np->lock, flags); 1364 return NETDEV_TX_OK; 1365 } 1366 1367 1368 /* Take lock before calling */ 1369 /* Chip probably hosed tx ring. Clean up. */ 1370 static void reset_tx_descriptors(struct net_device *dev) 1371 { 1372 struct netdev_private *np = netdev_priv(dev); 1373 struct fealnx_desc *cur; 1374 int i; 1375 1376 /* initialize tx variables */ 1377 np->cur_tx = &np->tx_ring[0]; 1378 np->cur_tx_copy = &np->tx_ring[0]; 1379 np->really_tx_count = 0; 1380 np->free_tx_count = TX_RING_SIZE; 1381 1382 for (i = 0; i < TX_RING_SIZE; i++) { 1383 cur = &np->tx_ring[i]; 1384 if (cur->skbuff) { 1385 dma_unmap_single(&np->pci_dev->dev, cur->buffer, 1386 cur->skbuff->len, DMA_TO_DEVICE); 1387 dev_kfree_skb_any(cur->skbuff); 1388 cur->skbuff = NULL; 1389 } 1390 cur->status = 0; 1391 cur->control = 0; /* needed? */ 1392 /* probably not needed. We do it for purely paranoid reasons */ 1393 cur->next_desc = np->tx_ring_dma + 1394 (i + 1)*sizeof(struct fealnx_desc); 1395 cur->next_desc_logical = &np->tx_ring[i + 1]; 1396 } 1397 /* for the last tx descriptor */ 1398 np->tx_ring[TX_RING_SIZE - 1].next_desc = np->tx_ring_dma; 1399 np->tx_ring[TX_RING_SIZE - 1].next_desc_logical = &np->tx_ring[0]; 1400 } 1401 1402 1403 /* Take lock and stop rx before calling this */ 1404 static void reset_rx_descriptors(struct net_device *dev) 1405 { 1406 struct netdev_private *np = netdev_priv(dev); 1407 struct fealnx_desc *cur = np->cur_rx; 1408 int i; 1409 1410 allocate_rx_buffers(dev); 1411 1412 for (i = 0; i < RX_RING_SIZE; i++) { 1413 if (cur->skbuff) 1414 cur->status = RXOWN; 1415 cur = cur->next_desc_logical; 1416 } 1417 1418 iowrite32(np->rx_ring_dma + ((char*)np->cur_rx - (char*)np->rx_ring), 1419 np->mem + RXLBA); 1420 } 1421 1422 1423 /* The interrupt handler does all of the Rx thread work and cleans up 1424 after the Tx thread. */ 1425 static irqreturn_t intr_handler(int irq, void *dev_instance) 1426 { 1427 struct net_device *dev = (struct net_device *) dev_instance; 1428 struct netdev_private *np = netdev_priv(dev); 1429 void __iomem *ioaddr = np->mem; 1430 long boguscnt = max_interrupt_work; 1431 unsigned int num_tx = 0; 1432 int handled = 0; 1433 1434 spin_lock(&np->lock); 1435 1436 iowrite32(0, ioaddr + IMR); 1437 1438 do { 1439 u32 intr_status = ioread32(ioaddr + ISR); 1440 1441 /* Acknowledge all of the current interrupt sources ASAP. */ 1442 iowrite32(intr_status, ioaddr + ISR); 1443 1444 if (debug) 1445 printk(KERN_DEBUG "%s: Interrupt, status %4.4x.\n", dev->name, 1446 intr_status); 1447 1448 if (!(intr_status & np->imrvalue)) 1449 break; 1450 1451 handled = 1; 1452 1453 // 90/1/16 delete, 1454 // 1455 // if (intr_status & FBE) 1456 // { /* fatal error */ 1457 // stop_nic_tx(ioaddr, 0); 1458 // stop_nic_rx(ioaddr, 0); 1459 // break; 1460 // }; 1461 1462 if (intr_status & TUNF) 1463 iowrite32(0, ioaddr + TXPDR); 1464 1465 if (intr_status & CNTOVF) { 1466 /* missed pkts */ 1467 dev->stats.rx_missed_errors += 1468 ioread32(ioaddr + TALLY) & 0x7fff; 1469 1470 /* crc error */ 1471 dev->stats.rx_crc_errors += 1472 (ioread32(ioaddr + TALLY) & 0x7fff0000) >> 16; 1473 } 1474 1475 if (intr_status & (RI | RBU)) { 1476 if (intr_status & RI) 1477 netdev_rx(dev); 1478 else { 1479 stop_nic_rx(ioaddr, np->crvalue); 1480 reset_rx_descriptors(dev); 1481 iowrite32(np->crvalue, ioaddr + TCRRCR); 1482 } 1483 } 1484 1485 while (np->really_tx_count) { 1486 long tx_status = np->cur_tx->status; 1487 long tx_control = np->cur_tx->control; 1488 1489 if (!(tx_control & TXLD)) { /* this pkt is combined by two tx descriptors */ 1490 struct fealnx_desc *next; 1491 1492 next = np->cur_tx->next_desc_logical; 1493 tx_status = next->status; 1494 tx_control = next->control; 1495 } 1496 1497 if (tx_status & TXOWN) 1498 break; 1499 1500 if (!(np->crvalue & CR_W_ENH)) { 1501 if (tx_status & (CSL | LC | EC | UDF | HF)) { 1502 dev->stats.tx_errors++; 1503 if (tx_status & EC) 1504 dev->stats.tx_aborted_errors++; 1505 if (tx_status & CSL) 1506 dev->stats.tx_carrier_errors++; 1507 if (tx_status & LC) 1508 dev->stats.tx_window_errors++; 1509 if (tx_status & UDF) 1510 dev->stats.tx_fifo_errors++; 1511 if ((tx_status & HF) && np->mii.full_duplex == 0) 1512 dev->stats.tx_heartbeat_errors++; 1513 1514 } else { 1515 dev->stats.tx_bytes += 1516 ((tx_control & PKTSMask) >> PKTSShift); 1517 1518 dev->stats.collisions += 1519 ((tx_status & NCRMask) >> NCRShift); 1520 dev->stats.tx_packets++; 1521 } 1522 } else { 1523 dev->stats.tx_bytes += 1524 ((tx_control & PKTSMask) >> PKTSShift); 1525 dev->stats.tx_packets++; 1526 } 1527 1528 /* Free the original skb. */ 1529 dma_unmap_single(&np->pci_dev->dev, 1530 np->cur_tx->buffer, 1531 np->cur_tx->skbuff->len, 1532 DMA_TO_DEVICE); 1533 dev_consume_skb_irq(np->cur_tx->skbuff); 1534 np->cur_tx->skbuff = NULL; 1535 --np->really_tx_count; 1536 if (np->cur_tx->control & TXLD) { 1537 np->cur_tx = np->cur_tx->next_desc_logical; 1538 ++np->free_tx_count; 1539 } else { 1540 np->cur_tx = np->cur_tx->next_desc_logical; 1541 np->cur_tx = np->cur_tx->next_desc_logical; 1542 np->free_tx_count += 2; 1543 } 1544 num_tx++; 1545 } /* end of for loop */ 1546 1547 if (num_tx && np->free_tx_count >= 2) 1548 netif_wake_queue(dev); 1549 1550 /* read transmit status for enhanced mode only */ 1551 if (np->crvalue & CR_W_ENH) { 1552 long data; 1553 1554 data = ioread32(ioaddr + TSR); 1555 dev->stats.tx_errors += (data & 0xff000000) >> 24; 1556 dev->stats.tx_aborted_errors += 1557 (data & 0xff000000) >> 24; 1558 dev->stats.tx_window_errors += 1559 (data & 0x00ff0000) >> 16; 1560 dev->stats.collisions += (data & 0x0000ffff); 1561 } 1562 1563 if (--boguscnt < 0) { 1564 printk(KERN_WARNING "%s: Too much work at interrupt, " 1565 "status=0x%4.4x.\n", dev->name, intr_status); 1566 if (!np->reset_timer_armed) { 1567 np->reset_timer_armed = 1; 1568 np->reset_timer.expires = RUN_AT(HZ/2); 1569 add_timer(&np->reset_timer); 1570 stop_nic_rxtx(ioaddr, 0); 1571 netif_stop_queue(dev); 1572 /* or netif_tx_disable(dev); ?? */ 1573 /* Prevent other paths from enabling tx,rx,intrs */ 1574 np->crvalue_sv = np->crvalue; 1575 np->imrvalue_sv = np->imrvalue; 1576 np->crvalue &= ~(CR_W_TXEN | CR_W_RXEN); /* or simply = 0? */ 1577 np->imrvalue = 0; 1578 } 1579 1580 break; 1581 } 1582 } while (1); 1583 1584 /* read the tally counters */ 1585 /* missed pkts */ 1586 dev->stats.rx_missed_errors += ioread32(ioaddr + TALLY) & 0x7fff; 1587 1588 /* crc error */ 1589 dev->stats.rx_crc_errors += 1590 (ioread32(ioaddr + TALLY) & 0x7fff0000) >> 16; 1591 1592 if (debug) 1593 printk(KERN_DEBUG "%s: exiting interrupt, status=%#4.4x.\n", 1594 dev->name, ioread32(ioaddr + ISR)); 1595 1596 iowrite32(np->imrvalue, ioaddr + IMR); 1597 1598 spin_unlock(&np->lock); 1599 1600 return IRQ_RETVAL(handled); 1601 } 1602 1603 1604 /* This routine is logically part of the interrupt handler, but separated 1605 for clarity and better register allocation. */ 1606 static int netdev_rx(struct net_device *dev) 1607 { 1608 struct netdev_private *np = netdev_priv(dev); 1609 void __iomem *ioaddr = np->mem; 1610 1611 /* If EOP is set on the next entry, it's a new packet. Send it up. */ 1612 while (!(np->cur_rx->status & RXOWN) && np->cur_rx->skbuff) { 1613 s32 rx_status = np->cur_rx->status; 1614 1615 if (np->really_rx_count == 0) 1616 break; 1617 1618 if (debug) 1619 printk(KERN_DEBUG " netdev_rx() status was %8.8x.\n", rx_status); 1620 1621 if ((!((rx_status & RXFSD) && (rx_status & RXLSD))) || 1622 (rx_status & ErrorSummary)) { 1623 if (rx_status & ErrorSummary) { /* there was a fatal error */ 1624 if (debug) 1625 printk(KERN_DEBUG 1626 "%s: Receive error, Rx status %8.8x.\n", 1627 dev->name, rx_status); 1628 1629 dev->stats.rx_errors++; /* end of a packet. */ 1630 if (rx_status & (LONGPKT | RUNTPKT)) 1631 dev->stats.rx_length_errors++; 1632 if (rx_status & RXER) 1633 dev->stats.rx_frame_errors++; 1634 if (rx_status & CRC) 1635 dev->stats.rx_crc_errors++; 1636 } else { 1637 int need_to_reset = 0; 1638 int desno = 0; 1639 1640 if (rx_status & RXFSD) { /* this pkt is too long, over one rx buffer */ 1641 struct fealnx_desc *cur; 1642 1643 /* check this packet is received completely? */ 1644 cur = np->cur_rx; 1645 while (desno <= np->really_rx_count) { 1646 ++desno; 1647 if ((!(cur->status & RXOWN)) && 1648 (cur->status & RXLSD)) 1649 break; 1650 /* goto next rx descriptor */ 1651 cur = cur->next_desc_logical; 1652 } 1653 if (desno > np->really_rx_count) 1654 need_to_reset = 1; 1655 } else /* RXLSD did not find, something error */ 1656 need_to_reset = 1; 1657 1658 if (need_to_reset == 0) { 1659 int i; 1660 1661 dev->stats.rx_length_errors++; 1662 1663 /* free all rx descriptors related this long pkt */ 1664 for (i = 0; i < desno; ++i) { 1665 if (!np->cur_rx->skbuff) { 1666 printk(KERN_DEBUG 1667 "%s: I'm scared\n", dev->name); 1668 break; 1669 } 1670 np->cur_rx->status = RXOWN; 1671 np->cur_rx = np->cur_rx->next_desc_logical; 1672 } 1673 continue; 1674 } else { /* rx error, need to reset this chip */ 1675 stop_nic_rx(ioaddr, np->crvalue); 1676 reset_rx_descriptors(dev); 1677 iowrite32(np->crvalue, ioaddr + TCRRCR); 1678 } 1679 break; /* exit the while loop */ 1680 } 1681 } else { /* this received pkt is ok */ 1682 1683 struct sk_buff *skb; 1684 /* Omit the four octet CRC from the length. */ 1685 short pkt_len = ((rx_status & FLNGMASK) >> FLNGShift) - 4; 1686 1687 #ifndef final_version 1688 if (debug) 1689 printk(KERN_DEBUG " netdev_rx() normal Rx pkt length %d" 1690 " status %x.\n", pkt_len, rx_status); 1691 #endif 1692 1693 /* Check if the packet is long enough to accept without copying 1694 to a minimally-sized skbuff. */ 1695 if (pkt_len < rx_copybreak && 1696 (skb = netdev_alloc_skb(dev, pkt_len + 2)) != NULL) { 1697 skb_reserve(skb, 2); /* 16 byte align the IP header */ 1698 dma_sync_single_for_cpu(&np->pci_dev->dev, 1699 np->cur_rx->buffer, 1700 np->rx_buf_sz, 1701 DMA_FROM_DEVICE); 1702 /* Call copy + cksum if available. */ 1703 1704 #if ! defined(__alpha__) 1705 skb_copy_to_linear_data(skb, 1706 np->cur_rx->skbuff->data, pkt_len); 1707 skb_put(skb, pkt_len); 1708 #else 1709 skb_put_data(skb, np->cur_rx->skbuff->data, 1710 pkt_len); 1711 #endif 1712 dma_sync_single_for_device(&np->pci_dev->dev, 1713 np->cur_rx->buffer, 1714 np->rx_buf_sz, 1715 DMA_FROM_DEVICE); 1716 } else { 1717 dma_unmap_single(&np->pci_dev->dev, 1718 np->cur_rx->buffer, 1719 np->rx_buf_sz, 1720 DMA_FROM_DEVICE); 1721 skb_put(skb = np->cur_rx->skbuff, pkt_len); 1722 np->cur_rx->skbuff = NULL; 1723 --np->really_rx_count; 1724 } 1725 skb->protocol = eth_type_trans(skb, dev); 1726 netif_rx(skb); 1727 dev->stats.rx_packets++; 1728 dev->stats.rx_bytes += pkt_len; 1729 } 1730 1731 np->cur_rx = np->cur_rx->next_desc_logical; 1732 } /* end of while loop */ 1733 1734 /* allocate skb for rx buffers */ 1735 allocate_rx_buffers(dev); 1736 1737 return 0; 1738 } 1739 1740 1741 static struct net_device_stats *get_stats(struct net_device *dev) 1742 { 1743 struct netdev_private *np = netdev_priv(dev); 1744 void __iomem *ioaddr = np->mem; 1745 1746 /* The chip only need report frame silently dropped. */ 1747 if (netif_running(dev)) { 1748 dev->stats.rx_missed_errors += 1749 ioread32(ioaddr + TALLY) & 0x7fff; 1750 dev->stats.rx_crc_errors += 1751 (ioread32(ioaddr + TALLY) & 0x7fff0000) >> 16; 1752 } 1753 1754 return &dev->stats; 1755 } 1756 1757 1758 /* for dev->set_multicast_list */ 1759 static void set_rx_mode(struct net_device *dev) 1760 { 1761 spinlock_t *lp = &((struct netdev_private *)netdev_priv(dev))->lock; 1762 unsigned long flags; 1763 spin_lock_irqsave(lp, flags); 1764 __set_rx_mode(dev); 1765 spin_unlock_irqrestore(lp, flags); 1766 } 1767 1768 1769 /* Take lock before calling */ 1770 static void __set_rx_mode(struct net_device *dev) 1771 { 1772 struct netdev_private *np = netdev_priv(dev); 1773 void __iomem *ioaddr = np->mem; 1774 u32 mc_filter[2]; /* Multicast hash filter */ 1775 u32 rx_mode; 1776 1777 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */ 1778 memset(mc_filter, 0xff, sizeof(mc_filter)); 1779 rx_mode = CR_W_PROM | CR_W_AB | CR_W_AM; 1780 } else if ((netdev_mc_count(dev) > multicast_filter_limit) || 1781 (dev->flags & IFF_ALLMULTI)) { 1782 /* Too many to match, or accept all multicasts. */ 1783 memset(mc_filter, 0xff, sizeof(mc_filter)); 1784 rx_mode = CR_W_AB | CR_W_AM; 1785 } else { 1786 struct netdev_hw_addr *ha; 1787 1788 memset(mc_filter, 0, sizeof(mc_filter)); 1789 netdev_for_each_mc_addr(ha, dev) { 1790 unsigned int bit; 1791 bit = (ether_crc(ETH_ALEN, ha->addr) >> 26) ^ 0x3F; 1792 mc_filter[bit >> 5] |= (1 << bit); 1793 } 1794 rx_mode = CR_W_AB | CR_W_AM; 1795 } 1796 1797 stop_nic_rxtx(ioaddr, np->crvalue); 1798 1799 iowrite32(mc_filter[0], ioaddr + MAR0); 1800 iowrite32(mc_filter[1], ioaddr + MAR1); 1801 np->crvalue &= ~CR_W_RXMODEMASK; 1802 np->crvalue |= rx_mode; 1803 iowrite32(np->crvalue, ioaddr + TCRRCR); 1804 } 1805 1806 static void netdev_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) 1807 { 1808 struct netdev_private *np = netdev_priv(dev); 1809 1810 strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); 1811 strlcpy(info->bus_info, pci_name(np->pci_dev), sizeof(info->bus_info)); 1812 } 1813 1814 static int netdev_get_link_ksettings(struct net_device *dev, 1815 struct ethtool_link_ksettings *cmd) 1816 { 1817 struct netdev_private *np = netdev_priv(dev); 1818 1819 spin_lock_irq(&np->lock); 1820 mii_ethtool_get_link_ksettings(&np->mii, cmd); 1821 spin_unlock_irq(&np->lock); 1822 1823 return 0; 1824 } 1825 1826 static int netdev_set_link_ksettings(struct net_device *dev, 1827 const struct ethtool_link_ksettings *cmd) 1828 { 1829 struct netdev_private *np = netdev_priv(dev); 1830 int rc; 1831 1832 spin_lock_irq(&np->lock); 1833 rc = mii_ethtool_set_link_ksettings(&np->mii, cmd); 1834 spin_unlock_irq(&np->lock); 1835 1836 return rc; 1837 } 1838 1839 static int netdev_nway_reset(struct net_device *dev) 1840 { 1841 struct netdev_private *np = netdev_priv(dev); 1842 return mii_nway_restart(&np->mii); 1843 } 1844 1845 static u32 netdev_get_link(struct net_device *dev) 1846 { 1847 struct netdev_private *np = netdev_priv(dev); 1848 return mii_link_ok(&np->mii); 1849 } 1850 1851 static u32 netdev_get_msglevel(struct net_device *dev) 1852 { 1853 return debug; 1854 } 1855 1856 static void netdev_set_msglevel(struct net_device *dev, u32 value) 1857 { 1858 debug = value; 1859 } 1860 1861 static const struct ethtool_ops netdev_ethtool_ops = { 1862 .get_drvinfo = netdev_get_drvinfo, 1863 .nway_reset = netdev_nway_reset, 1864 .get_link = netdev_get_link, 1865 .get_msglevel = netdev_get_msglevel, 1866 .set_msglevel = netdev_set_msglevel, 1867 .get_link_ksettings = netdev_get_link_ksettings, 1868 .set_link_ksettings = netdev_set_link_ksettings, 1869 }; 1870 1871 static int mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 1872 { 1873 struct netdev_private *np = netdev_priv(dev); 1874 int rc; 1875 1876 if (!netif_running(dev)) 1877 return -EINVAL; 1878 1879 spin_lock_irq(&np->lock); 1880 rc = generic_mii_ioctl(&np->mii, if_mii(rq), cmd, NULL); 1881 spin_unlock_irq(&np->lock); 1882 1883 return rc; 1884 } 1885 1886 1887 static int netdev_close(struct net_device *dev) 1888 { 1889 struct netdev_private *np = netdev_priv(dev); 1890 void __iomem *ioaddr = np->mem; 1891 int i; 1892 1893 netif_stop_queue(dev); 1894 1895 /* Disable interrupts by clearing the interrupt mask. */ 1896 iowrite32(0x0000, ioaddr + IMR); 1897 1898 /* Stop the chip's Tx and Rx processes. */ 1899 stop_nic_rxtx(ioaddr, 0); 1900 1901 del_timer_sync(&np->timer); 1902 del_timer_sync(&np->reset_timer); 1903 1904 free_irq(np->pci_dev->irq, dev); 1905 1906 /* Free all the skbuffs in the Rx queue. */ 1907 for (i = 0; i < RX_RING_SIZE; i++) { 1908 struct sk_buff *skb = np->rx_ring[i].skbuff; 1909 1910 np->rx_ring[i].status = 0; 1911 if (skb) { 1912 dma_unmap_single(&np->pci_dev->dev, 1913 np->rx_ring[i].buffer, np->rx_buf_sz, 1914 DMA_FROM_DEVICE); 1915 dev_kfree_skb(skb); 1916 np->rx_ring[i].skbuff = NULL; 1917 } 1918 } 1919 1920 for (i = 0; i < TX_RING_SIZE; i++) { 1921 struct sk_buff *skb = np->tx_ring[i].skbuff; 1922 1923 if (skb) { 1924 dma_unmap_single(&np->pci_dev->dev, 1925 np->tx_ring[i].buffer, skb->len, 1926 DMA_TO_DEVICE); 1927 dev_kfree_skb(skb); 1928 np->tx_ring[i].skbuff = NULL; 1929 } 1930 } 1931 1932 return 0; 1933 } 1934 1935 static const struct pci_device_id fealnx_pci_tbl[] = { 1936 {0x1516, 0x0800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 1937 {0x1516, 0x0803, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1}, 1938 {0x1516, 0x0891, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2}, 1939 {} /* terminate list */ 1940 }; 1941 MODULE_DEVICE_TABLE(pci, fealnx_pci_tbl); 1942 1943 1944 static struct pci_driver fealnx_driver = { 1945 .name = "fealnx", 1946 .id_table = fealnx_pci_tbl, 1947 .probe = fealnx_init_one, 1948 .remove = fealnx_remove_one, 1949 }; 1950 1951 module_pci_driver(fealnx_driver); 1952