1 /* 2 Written 1998-2000 by Donald Becker. 3 4 This software may be used and distributed according to the terms of 5 the GNU General Public License (GPL), incorporated herein by reference. 6 Drivers based on or derived from this code fall under the GPL and must 7 retain the authorship, copyright and license notice. This file is not 8 a complete program and may only be used when the entire operating 9 system is licensed under the GPL. 10 11 The author may be reached as becker@scyld.com, or C/O 12 Scyld Computing Corporation 13 410 Severn Ave., Suite 210 14 Annapolis MD 21403 15 16 Support information and updates available at 17 http://www.scyld.com/network/pci-skeleton.html 18 19 Linux kernel updates: 20 21 Version 2.51, Nov 17, 2001 (jgarzik): 22 - Add ethtool support 23 - Replace some MII-related magic numbers with constants 24 25 */ 26 27 #define DRV_NAME "fealnx" 28 29 static int debug; /* 1-> print debug message */ 30 static int max_interrupt_work = 20; 31 32 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). */ 33 static int multicast_filter_limit = 32; 34 35 /* Set the copy breakpoint for the copy-only-tiny-frames scheme. */ 36 /* Setting to > 1518 effectively disables this feature. */ 37 static int rx_copybreak; 38 39 /* Used to pass the media type, etc. */ 40 /* Both 'options[]' and 'full_duplex[]' should exist for driver */ 41 /* interoperability. */ 42 /* The media type is usually passed in 'options[]'. */ 43 #define MAX_UNITS 8 /* More are supported, limit only on options */ 44 static int options[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 }; 45 static int full_duplex[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 }; 46 47 /* Operational parameters that are set at compile time. */ 48 /* Keep the ring sizes a power of two for compile efficiency. */ 49 /* The compiler will convert <unsigned>'%'<2^N> into a bit mask. */ 50 /* Making the Tx ring too large decreases the effectiveness of channel */ 51 /* bonding and packet priority. */ 52 /* There are no ill effects from too-large receive rings. */ 53 // 88-12-9 modify, 54 // #define TX_RING_SIZE 16 55 // #define RX_RING_SIZE 32 56 #define TX_RING_SIZE 6 57 #define RX_RING_SIZE 12 58 #define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct fealnx_desc) 59 #define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct fealnx_desc) 60 61 /* Operational parameters that usually are not changed. */ 62 /* Time in jiffies before concluding the transmitter is hung. */ 63 #define TX_TIMEOUT (2*HZ) 64 65 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer. */ 66 67 68 /* Include files, designed to support most kernel versions 2.0.0 and later. */ 69 #include <linux/module.h> 70 #include <linux/kernel.h> 71 #include <linux/string.h> 72 #include <linux/timer.h> 73 #include <linux/errno.h> 74 #include <linux/ioport.h> 75 #include <linux/interrupt.h> 76 #include <linux/pci.h> 77 #include <linux/netdevice.h> 78 #include <linux/etherdevice.h> 79 #include <linux/skbuff.h> 80 #include <linux/init.h> 81 #include <linux/mii.h> 82 #include <linux/ethtool.h> 83 #include <linux/crc32.h> 84 #include <linux/delay.h> 85 #include <linux/bitops.h> 86 87 #include <asm/processor.h> /* Processor type for cache alignment. */ 88 #include <asm/io.h> 89 #include <linux/uaccess.h> 90 #include <asm/byteorder.h> 91 92 /* This driver was written to use PCI memory space, however some x86 systems 93 work only with I/O space accesses. */ 94 #ifndef __alpha__ 95 #define USE_IO_OPS 96 #endif 97 98 /* Kernel compatibility defines, some common to David Hinds' PCMCIA package. */ 99 /* This is only in the support-all-kernels source code. */ 100 101 #define RUN_AT(x) (jiffies + (x)) 102 103 MODULE_AUTHOR("Myson or whoever"); 104 MODULE_DESCRIPTION("Myson MTD-8xx 100/10M Ethernet PCI Adapter Driver"); 105 MODULE_LICENSE("GPL"); 106 module_param(max_interrupt_work, int, 0); 107 module_param(debug, int, 0); 108 module_param(rx_copybreak, int, 0); 109 module_param(multicast_filter_limit, int, 0); 110 module_param_array(options, int, NULL, 0); 111 module_param_array(full_duplex, int, NULL, 0); 112 MODULE_PARM_DESC(max_interrupt_work, "fealnx maximum events handled per interrupt"); 113 MODULE_PARM_DESC(debug, "fealnx enable debugging (0-1)"); 114 MODULE_PARM_DESC(rx_copybreak, "fealnx copy breakpoint for copy-only-tiny-frames"); 115 MODULE_PARM_DESC(multicast_filter_limit, "fealnx maximum number of filtered multicast addresses"); 116 MODULE_PARM_DESC(options, "fealnx: Bits 0-3: media type, bit 17: full duplex"); 117 MODULE_PARM_DESC(full_duplex, "fealnx full duplex setting(s) (1)"); 118 119 enum { 120 MIN_REGION_SIZE = 136, 121 }; 122 123 /* A chip capabilities table, matching the entries in pci_tbl[] above. */ 124 enum chip_capability_flags { 125 HAS_MII_XCVR, 126 HAS_CHIP_XCVR, 127 }; 128 129 /* 89/6/13 add, */ 130 /* for different PHY */ 131 enum phy_type_flags { 132 MysonPHY = 1, 133 AhdocPHY = 2, 134 SeeqPHY = 3, 135 MarvellPHY = 4, 136 Myson981 = 5, 137 LevelOnePHY = 6, 138 OtherPHY = 10, 139 }; 140 141 struct chip_info { 142 char *chip_name; 143 int flags; 144 }; 145 146 static const struct chip_info skel_netdrv_tbl[] = { 147 { "100/10M Ethernet PCI Adapter", HAS_MII_XCVR }, 148 { "100/10M Ethernet PCI Adapter", HAS_CHIP_XCVR }, 149 { "1000/100/10M Ethernet PCI Adapter", HAS_MII_XCVR }, 150 }; 151 152 /* Offsets to the Command and Status Registers. */ 153 enum fealnx_offsets { 154 PAR0 = 0x0, /* physical address 0-3 */ 155 PAR1 = 0x04, /* physical address 4-5 */ 156 MAR0 = 0x08, /* multicast address 0-3 */ 157 MAR1 = 0x0C, /* multicast address 4-7 */ 158 FAR0 = 0x10, /* flow-control address 0-3 */ 159 FAR1 = 0x14, /* flow-control address 4-5 */ 160 TCRRCR = 0x18, /* receive & transmit configuration */ 161 BCR = 0x1C, /* bus command */ 162 TXPDR = 0x20, /* transmit polling demand */ 163 RXPDR = 0x24, /* receive polling demand */ 164 RXCWP = 0x28, /* receive current word pointer */ 165 TXLBA = 0x2C, /* transmit list base address */ 166 RXLBA = 0x30, /* receive list base address */ 167 ISR = 0x34, /* interrupt status */ 168 IMR = 0x38, /* interrupt mask */ 169 FTH = 0x3C, /* flow control high/low threshold */ 170 MANAGEMENT = 0x40, /* bootrom/eeprom and mii management */ 171 TALLY = 0x44, /* tally counters for crc and mpa */ 172 TSR = 0x48, /* tally counter for transmit status */ 173 BMCRSR = 0x4c, /* basic mode control and status */ 174 PHYIDENTIFIER = 0x50, /* phy identifier */ 175 ANARANLPAR = 0x54, /* auto-negotiation advertisement and link 176 partner ability */ 177 ANEROCR = 0x58, /* auto-negotiation expansion and pci conf. */ 178 BPREMRPSR = 0x5c, /* bypass & receive error mask and phy status */ 179 }; 180 181 /* Bits in the interrupt status/enable registers. */ 182 /* The bits in the Intr Status/Enable registers, mostly interrupt sources. */ 183 enum intr_status_bits { 184 RFCON = 0x00020000, /* receive flow control xon packet */ 185 RFCOFF = 0x00010000, /* receive flow control xoff packet */ 186 LSCStatus = 0x00008000, /* link status change */ 187 ANCStatus = 0x00004000, /* autonegotiation completed */ 188 FBE = 0x00002000, /* fatal bus error */ 189 FBEMask = 0x00001800, /* mask bit12-11 */ 190 ParityErr = 0x00000000, /* parity error */ 191 TargetErr = 0x00001000, /* target abort */ 192 MasterErr = 0x00000800, /* master error */ 193 TUNF = 0x00000400, /* transmit underflow */ 194 ROVF = 0x00000200, /* receive overflow */ 195 ETI = 0x00000100, /* transmit early int */ 196 ERI = 0x00000080, /* receive early int */ 197 CNTOVF = 0x00000040, /* counter overflow */ 198 RBU = 0x00000020, /* receive buffer unavailable */ 199 TBU = 0x00000010, /* transmit buffer unavilable */ 200 TI = 0x00000008, /* transmit interrupt */ 201 RI = 0x00000004, /* receive interrupt */ 202 RxErr = 0x00000002, /* receive error */ 203 }; 204 205 /* Bits in the NetworkConfig register, W for writing, R for reading */ 206 /* FIXME: some names are invented by me. Marked with (name?) */ 207 /* If you have docs and know bit names, please fix 'em */ 208 enum rx_mode_bits { 209 CR_W_ENH = 0x02000000, /* enhanced mode (name?) */ 210 CR_W_FD = 0x00100000, /* full duplex */ 211 CR_W_PS10 = 0x00080000, /* 10 mbit */ 212 CR_W_TXEN = 0x00040000, /* tx enable (name?) */ 213 CR_W_PS1000 = 0x00010000, /* 1000 mbit */ 214 /* CR_W_RXBURSTMASK= 0x00000e00, Im unsure about this */ 215 CR_W_RXMODEMASK = 0x000000e0, 216 CR_W_PROM = 0x00000080, /* promiscuous mode */ 217 CR_W_AB = 0x00000040, /* accept broadcast */ 218 CR_W_AM = 0x00000020, /* accept mutlicast */ 219 CR_W_ARP = 0x00000008, /* receive runt pkt */ 220 CR_W_ALP = 0x00000004, /* receive long pkt */ 221 CR_W_SEP = 0x00000002, /* receive error pkt */ 222 CR_W_RXEN = 0x00000001, /* rx enable (unicast?) (name?) */ 223 224 CR_R_TXSTOP = 0x04000000, /* tx stopped (name?) */ 225 CR_R_FD = 0x00100000, /* full duplex detected */ 226 CR_R_PS10 = 0x00080000, /* 10 mbit detected */ 227 CR_R_RXSTOP = 0x00008000, /* rx stopped (name?) */ 228 }; 229 230 /* The Tulip Rx and Tx buffer descriptors. */ 231 struct fealnx_desc { 232 s32 status; 233 s32 control; 234 u32 buffer; 235 u32 next_desc; 236 struct fealnx_desc *next_desc_logical; 237 struct sk_buff *skbuff; 238 u32 reserved1; 239 u32 reserved2; 240 }; 241 242 /* Bits in network_desc.status */ 243 enum rx_desc_status_bits { 244 RXOWN = 0x80000000, /* own bit */ 245 FLNGMASK = 0x0fff0000, /* frame length */ 246 FLNGShift = 16, 247 MARSTATUS = 0x00004000, /* multicast address received */ 248 BARSTATUS = 0x00002000, /* broadcast address received */ 249 PHYSTATUS = 0x00001000, /* physical address received */ 250 RXFSD = 0x00000800, /* first descriptor */ 251 RXLSD = 0x00000400, /* last descriptor */ 252 ErrorSummary = 0x80, /* error summary */ 253 RUNTPKT = 0x40, /* runt packet received */ 254 LONGPKT = 0x20, /* long packet received */ 255 FAE = 0x10, /* frame align error */ 256 CRC = 0x08, /* crc error */ 257 RXER = 0x04, /* receive error */ 258 }; 259 260 enum rx_desc_control_bits { 261 RXIC = 0x00800000, /* interrupt control */ 262 RBSShift = 0, 263 }; 264 265 enum tx_desc_status_bits { 266 TXOWN = 0x80000000, /* own bit */ 267 JABTO = 0x00004000, /* jabber timeout */ 268 CSL = 0x00002000, /* carrier sense lost */ 269 LC = 0x00001000, /* late collision */ 270 EC = 0x00000800, /* excessive collision */ 271 UDF = 0x00000400, /* fifo underflow */ 272 DFR = 0x00000200, /* deferred */ 273 HF = 0x00000100, /* heartbeat fail */ 274 NCRMask = 0x000000ff, /* collision retry count */ 275 NCRShift = 0, 276 }; 277 278 enum tx_desc_control_bits { 279 TXIC = 0x80000000, /* interrupt control */ 280 ETIControl = 0x40000000, /* early transmit interrupt */ 281 TXLD = 0x20000000, /* last descriptor */ 282 TXFD = 0x10000000, /* first descriptor */ 283 CRCEnable = 0x08000000, /* crc control */ 284 PADEnable = 0x04000000, /* padding control */ 285 RetryTxLC = 0x02000000, /* retry late collision */ 286 PKTSMask = 0x3ff800, /* packet size bit21-11 */ 287 PKTSShift = 11, 288 TBSMask = 0x000007ff, /* transmit buffer bit 10-0 */ 289 TBSShift = 0, 290 }; 291 292 /* BootROM/EEPROM/MII Management Register */ 293 #define MASK_MIIR_MII_READ 0x00000000 294 #define MASK_MIIR_MII_WRITE 0x00000008 295 #define MASK_MIIR_MII_MDO 0x00000004 296 #define MASK_MIIR_MII_MDI 0x00000002 297 #define MASK_MIIR_MII_MDC 0x00000001 298 299 /* ST+OP+PHYAD+REGAD+TA */ 300 #define OP_READ 0x6000 /* ST:01+OP:10+PHYAD+REGAD+TA:Z0 */ 301 #define OP_WRITE 0x5002 /* ST:01+OP:01+PHYAD+REGAD+TA:10 */ 302 303 /* ------------------------------------------------------------------------- */ 304 /* Constants for Myson PHY */ 305 /* ------------------------------------------------------------------------- */ 306 #define MysonPHYID 0xd0000302 307 /* 89-7-27 add, (begin) */ 308 #define MysonPHYID0 0x0302 309 #define StatusRegister 18 310 #define SPEED100 0x0400 // bit10 311 #define FULLMODE 0x0800 // bit11 312 /* 89-7-27 add, (end) */ 313 314 /* ------------------------------------------------------------------------- */ 315 /* Constants for Seeq 80225 PHY */ 316 /* ------------------------------------------------------------------------- */ 317 #define SeeqPHYID0 0x0016 318 319 #define MIIRegister18 18 320 #define SPD_DET_100 0x80 321 #define DPLX_DET_FULL 0x40 322 323 /* ------------------------------------------------------------------------- */ 324 /* Constants for Ahdoc 101 PHY */ 325 /* ------------------------------------------------------------------------- */ 326 #define AhdocPHYID0 0x0022 327 328 #define DiagnosticReg 18 329 #define DPLX_FULL 0x0800 330 #define Speed_100 0x0400 331 332 /* 89/6/13 add, */ 333 /* -------------------------------------------------------------------------- */ 334 /* Constants */ 335 /* -------------------------------------------------------------------------- */ 336 #define MarvellPHYID0 0x0141 337 #define LevelOnePHYID0 0x0013 338 339 #define MII1000BaseTControlReg 9 340 #define MII1000BaseTStatusReg 10 341 #define SpecificReg 17 342 343 /* for 1000BaseT Control Register */ 344 #define PHYAbletoPerform1000FullDuplex 0x0200 345 #define PHYAbletoPerform1000HalfDuplex 0x0100 346 #define PHY1000AbilityMask 0x300 347 348 // for phy specific status register, marvell phy. 349 #define SpeedMask 0x0c000 350 #define Speed_1000M 0x08000 351 #define Speed_100M 0x4000 352 #define Speed_10M 0 353 #define Full_Duplex 0x2000 354 355 // 89/12/29 add, for phy specific status register, levelone phy, (begin) 356 #define LXT1000_100M 0x08000 357 #define LXT1000_1000M 0x0c000 358 #define LXT1000_Full 0x200 359 // 89/12/29 add, for phy specific status register, levelone phy, (end) 360 361 /* for 3-in-1 case, BMCRSR register */ 362 #define LinkIsUp2 0x00040000 363 364 /* for PHY */ 365 #define LinkIsUp 0x0004 366 367 368 struct netdev_private { 369 /* Descriptor rings first for alignment. */ 370 struct fealnx_desc *rx_ring; 371 struct fealnx_desc *tx_ring; 372 373 dma_addr_t rx_ring_dma; 374 dma_addr_t tx_ring_dma; 375 376 spinlock_t lock; 377 378 /* Media monitoring timer. */ 379 struct timer_list timer; 380 381 /* Reset timer */ 382 struct timer_list reset_timer; 383 int reset_timer_armed; 384 unsigned long crvalue_sv; 385 unsigned long imrvalue_sv; 386 387 /* Frequently used values: keep some adjacent for cache effect. */ 388 int flags; 389 struct pci_dev *pci_dev; 390 unsigned long crvalue; 391 unsigned long bcrvalue; 392 unsigned long imrvalue; 393 struct fealnx_desc *cur_rx; 394 struct fealnx_desc *lack_rxbuf; 395 int really_rx_count; 396 struct fealnx_desc *cur_tx; 397 struct fealnx_desc *cur_tx_copy; 398 int really_tx_count; 399 int free_tx_count; 400 unsigned int rx_buf_sz; /* Based on MTU+slack. */ 401 402 /* These values are keep track of the transceiver/media in use. */ 403 unsigned int linkok; 404 unsigned int line_speed; 405 unsigned int duplexmode; 406 unsigned int default_port:4; /* Last dev->if_port value. */ 407 unsigned int PHYType; 408 409 /* MII transceiver section. */ 410 int mii_cnt; /* MII device addresses. */ 411 unsigned char phys[2]; /* MII device addresses. */ 412 struct mii_if_info mii; 413 void __iomem *mem; 414 }; 415 416 417 static int mdio_read(struct net_device *dev, int phy_id, int location); 418 static void mdio_write(struct net_device *dev, int phy_id, int location, int value); 419 static int netdev_open(struct net_device *dev); 420 static void getlinktype(struct net_device *dev); 421 static void getlinkstatus(struct net_device *dev); 422 static void netdev_timer(struct timer_list *t); 423 static void reset_timer(struct timer_list *t); 424 static void fealnx_tx_timeout(struct net_device *dev, unsigned int txqueue); 425 static void init_ring(struct net_device *dev); 426 static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev); 427 static irqreturn_t intr_handler(int irq, void *dev_instance); 428 static int netdev_rx(struct net_device *dev); 429 static void set_rx_mode(struct net_device *dev); 430 static void __set_rx_mode(struct net_device *dev); 431 static struct net_device_stats *get_stats(struct net_device *dev); 432 static int mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); 433 static const struct ethtool_ops netdev_ethtool_ops; 434 static int netdev_close(struct net_device *dev); 435 static void reset_rx_descriptors(struct net_device *dev); 436 static void reset_tx_descriptors(struct net_device *dev); 437 438 static void stop_nic_rx(void __iomem *ioaddr, long crvalue) 439 { 440 int delay = 0x1000; 441 iowrite32(crvalue & ~(CR_W_RXEN), ioaddr + TCRRCR); 442 while (--delay) { 443 if ( (ioread32(ioaddr + TCRRCR) & CR_R_RXSTOP) == CR_R_RXSTOP) 444 break; 445 } 446 } 447 448 449 static void stop_nic_rxtx(void __iomem *ioaddr, long crvalue) 450 { 451 int delay = 0x1000; 452 iowrite32(crvalue & ~(CR_W_RXEN+CR_W_TXEN), ioaddr + TCRRCR); 453 while (--delay) { 454 if ( (ioread32(ioaddr + TCRRCR) & (CR_R_RXSTOP+CR_R_TXSTOP)) 455 == (CR_R_RXSTOP+CR_R_TXSTOP) ) 456 break; 457 } 458 } 459 460 static const struct net_device_ops netdev_ops = { 461 .ndo_open = netdev_open, 462 .ndo_stop = netdev_close, 463 .ndo_start_xmit = start_tx, 464 .ndo_get_stats = get_stats, 465 .ndo_set_rx_mode = set_rx_mode, 466 .ndo_do_ioctl = mii_ioctl, 467 .ndo_tx_timeout = fealnx_tx_timeout, 468 .ndo_set_mac_address = eth_mac_addr, 469 .ndo_validate_addr = eth_validate_addr, 470 }; 471 472 static int fealnx_init_one(struct pci_dev *pdev, 473 const struct pci_device_id *ent) 474 { 475 struct netdev_private *np; 476 int i, option, err, irq; 477 static int card_idx = -1; 478 char boardname[12]; 479 void __iomem *ioaddr; 480 unsigned long len; 481 unsigned int chip_id = ent->driver_data; 482 struct net_device *dev; 483 void *ring_space; 484 dma_addr_t ring_dma; 485 #ifdef USE_IO_OPS 486 int bar = 0; 487 #else 488 int bar = 1; 489 #endif 490 491 card_idx++; 492 sprintf(boardname, "fealnx%d", card_idx); 493 494 option = card_idx < MAX_UNITS ? options[card_idx] : 0; 495 496 i = pci_enable_device(pdev); 497 if (i) return i; 498 pci_set_master(pdev); 499 500 len = pci_resource_len(pdev, bar); 501 if (len < MIN_REGION_SIZE) { 502 dev_err(&pdev->dev, 503 "region size %ld too small, aborting\n", len); 504 return -ENODEV; 505 } 506 507 i = pci_request_regions(pdev, boardname); 508 if (i) 509 return i; 510 511 irq = pdev->irq; 512 513 ioaddr = pci_iomap(pdev, bar, len); 514 if (!ioaddr) { 515 err = -ENOMEM; 516 goto err_out_res; 517 } 518 519 dev = alloc_etherdev(sizeof(struct netdev_private)); 520 if (!dev) { 521 err = -ENOMEM; 522 goto err_out_unmap; 523 } 524 SET_NETDEV_DEV(dev, &pdev->dev); 525 526 /* read ethernet id */ 527 for (i = 0; i < 6; ++i) 528 dev->dev_addr[i] = ioread8(ioaddr + PAR0 + i); 529 530 /* Reset the chip to erase previous misconfiguration. */ 531 iowrite32(0x00000001, ioaddr + BCR); 532 533 /* Make certain the descriptor lists are aligned. */ 534 np = netdev_priv(dev); 535 np->mem = ioaddr; 536 spin_lock_init(&np->lock); 537 np->pci_dev = pdev; 538 np->flags = skel_netdrv_tbl[chip_id].flags; 539 pci_set_drvdata(pdev, dev); 540 np->mii.dev = dev; 541 np->mii.mdio_read = mdio_read; 542 np->mii.mdio_write = mdio_write; 543 np->mii.phy_id_mask = 0x1f; 544 np->mii.reg_num_mask = 0x1f; 545 546 ring_space = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &ring_dma); 547 if (!ring_space) { 548 err = -ENOMEM; 549 goto err_out_free_dev; 550 } 551 np->rx_ring = ring_space; 552 np->rx_ring_dma = ring_dma; 553 554 ring_space = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &ring_dma); 555 if (!ring_space) { 556 err = -ENOMEM; 557 goto err_out_free_rx; 558 } 559 np->tx_ring = ring_space; 560 np->tx_ring_dma = ring_dma; 561 562 /* find the connected MII xcvrs */ 563 if (np->flags == HAS_MII_XCVR) { 564 int phy, phy_idx = 0; 565 566 for (phy = 1; phy < 32 && phy_idx < ARRAY_SIZE(np->phys); 567 phy++) { 568 int mii_status = mdio_read(dev, phy, 1); 569 570 if (mii_status != 0xffff && mii_status != 0x0000) { 571 np->phys[phy_idx++] = phy; 572 dev_info(&pdev->dev, 573 "MII PHY found at address %d, status " 574 "0x%4.4x.\n", phy, mii_status); 575 /* get phy type */ 576 { 577 unsigned int data; 578 579 data = mdio_read(dev, np->phys[0], 2); 580 if (data == SeeqPHYID0) 581 np->PHYType = SeeqPHY; 582 else if (data == AhdocPHYID0) 583 np->PHYType = AhdocPHY; 584 else if (data == MarvellPHYID0) 585 np->PHYType = MarvellPHY; 586 else if (data == MysonPHYID0) 587 np->PHYType = Myson981; 588 else if (data == LevelOnePHYID0) 589 np->PHYType = LevelOnePHY; 590 else 591 np->PHYType = OtherPHY; 592 } 593 } 594 } 595 596 np->mii_cnt = phy_idx; 597 if (phy_idx == 0) 598 dev_warn(&pdev->dev, 599 "MII PHY not found -- this device may " 600 "not operate correctly.\n"); 601 } else { 602 np->phys[0] = 32; 603 /* 89/6/23 add, (begin) */ 604 /* get phy type */ 605 if (ioread32(ioaddr + PHYIDENTIFIER) == MysonPHYID) 606 np->PHYType = MysonPHY; 607 else 608 np->PHYType = OtherPHY; 609 } 610 np->mii.phy_id = np->phys[0]; 611 612 if (dev->mem_start) 613 option = dev->mem_start; 614 615 /* The lower four bits are the media type. */ 616 if (option > 0) { 617 if (option & 0x200) 618 np->mii.full_duplex = 1; 619 np->default_port = option & 15; 620 } 621 622 if (card_idx < MAX_UNITS && full_duplex[card_idx] > 0) 623 np->mii.full_duplex = full_duplex[card_idx]; 624 625 if (np->mii.full_duplex) { 626 dev_info(&pdev->dev, "Media type forced to Full Duplex.\n"); 627 /* 89/6/13 add, (begin) */ 628 // if (np->PHYType==MarvellPHY) 629 if ((np->PHYType == MarvellPHY) || (np->PHYType == LevelOnePHY)) { 630 unsigned int data; 631 632 data = mdio_read(dev, np->phys[0], 9); 633 data = (data & 0xfcff) | 0x0200; 634 mdio_write(dev, np->phys[0], 9, data); 635 } 636 /* 89/6/13 add, (end) */ 637 if (np->flags == HAS_MII_XCVR) 638 mdio_write(dev, np->phys[0], MII_ADVERTISE, ADVERTISE_FULL); 639 else 640 iowrite32(ADVERTISE_FULL, ioaddr + ANARANLPAR); 641 np->mii.force_media = 1; 642 } 643 644 dev->netdev_ops = &netdev_ops; 645 dev->ethtool_ops = &netdev_ethtool_ops; 646 dev->watchdog_timeo = TX_TIMEOUT; 647 648 err = register_netdev(dev); 649 if (err) 650 goto err_out_free_tx; 651 652 printk(KERN_INFO "%s: %s at %p, %pM, IRQ %d.\n", 653 dev->name, skel_netdrv_tbl[chip_id].chip_name, ioaddr, 654 dev->dev_addr, irq); 655 656 return 0; 657 658 err_out_free_tx: 659 pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma); 660 err_out_free_rx: 661 pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma); 662 err_out_free_dev: 663 free_netdev(dev); 664 err_out_unmap: 665 pci_iounmap(pdev, ioaddr); 666 err_out_res: 667 pci_release_regions(pdev); 668 return err; 669 } 670 671 672 static void fealnx_remove_one(struct pci_dev *pdev) 673 { 674 struct net_device *dev = pci_get_drvdata(pdev); 675 676 if (dev) { 677 struct netdev_private *np = netdev_priv(dev); 678 679 pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring, 680 np->tx_ring_dma); 681 pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring, 682 np->rx_ring_dma); 683 unregister_netdev(dev); 684 pci_iounmap(pdev, np->mem); 685 free_netdev(dev); 686 pci_release_regions(pdev); 687 } else 688 printk(KERN_ERR "fealnx: remove for unknown device\n"); 689 } 690 691 692 static ulong m80x_send_cmd_to_phy(void __iomem *miiport, int opcode, int phyad, int regad) 693 { 694 ulong miir; 695 int i; 696 unsigned int mask, data; 697 698 /* enable MII output */ 699 miir = (ulong) ioread32(miiport); 700 miir &= 0xfffffff0; 701 702 miir |= MASK_MIIR_MII_WRITE + MASK_MIIR_MII_MDO; 703 704 /* send 32 1's preamble */ 705 for (i = 0; i < 32; i++) { 706 /* low MDC; MDO is already high (miir) */ 707 miir &= ~MASK_MIIR_MII_MDC; 708 iowrite32(miir, miiport); 709 710 /* high MDC */ 711 miir |= MASK_MIIR_MII_MDC; 712 iowrite32(miir, miiport); 713 } 714 715 /* calculate ST+OP+PHYAD+REGAD+TA */ 716 data = opcode | (phyad << 7) | (regad << 2); 717 718 /* sent out */ 719 mask = 0x8000; 720 while (mask) { 721 /* low MDC, prepare MDO */ 722 miir &= ~(MASK_MIIR_MII_MDC + MASK_MIIR_MII_MDO); 723 if (mask & data) 724 miir |= MASK_MIIR_MII_MDO; 725 726 iowrite32(miir, miiport); 727 /* high MDC */ 728 miir |= MASK_MIIR_MII_MDC; 729 iowrite32(miir, miiport); 730 udelay(30); 731 732 /* next */ 733 mask >>= 1; 734 if (mask == 0x2 && opcode == OP_READ) 735 miir &= ~MASK_MIIR_MII_WRITE; 736 } 737 return miir; 738 } 739 740 741 static int mdio_read(struct net_device *dev, int phyad, int regad) 742 { 743 struct netdev_private *np = netdev_priv(dev); 744 void __iomem *miiport = np->mem + MANAGEMENT; 745 ulong miir; 746 unsigned int mask, data; 747 748 miir = m80x_send_cmd_to_phy(miiport, OP_READ, phyad, regad); 749 750 /* read data */ 751 mask = 0x8000; 752 data = 0; 753 while (mask) { 754 /* low MDC */ 755 miir &= ~MASK_MIIR_MII_MDC; 756 iowrite32(miir, miiport); 757 758 /* read MDI */ 759 miir = ioread32(miiport); 760 if (miir & MASK_MIIR_MII_MDI) 761 data |= mask; 762 763 /* high MDC, and wait */ 764 miir |= MASK_MIIR_MII_MDC; 765 iowrite32(miir, miiport); 766 udelay(30); 767 768 /* next */ 769 mask >>= 1; 770 } 771 772 /* low MDC */ 773 miir &= ~MASK_MIIR_MII_MDC; 774 iowrite32(miir, miiport); 775 776 return data & 0xffff; 777 } 778 779 780 static void mdio_write(struct net_device *dev, int phyad, int regad, int data) 781 { 782 struct netdev_private *np = netdev_priv(dev); 783 void __iomem *miiport = np->mem + MANAGEMENT; 784 ulong miir; 785 unsigned int mask; 786 787 miir = m80x_send_cmd_to_phy(miiport, OP_WRITE, phyad, regad); 788 789 /* write data */ 790 mask = 0x8000; 791 while (mask) { 792 /* low MDC, prepare MDO */ 793 miir &= ~(MASK_MIIR_MII_MDC + MASK_MIIR_MII_MDO); 794 if (mask & data) 795 miir |= MASK_MIIR_MII_MDO; 796 iowrite32(miir, miiport); 797 798 /* high MDC */ 799 miir |= MASK_MIIR_MII_MDC; 800 iowrite32(miir, miiport); 801 802 /* next */ 803 mask >>= 1; 804 } 805 806 /* low MDC */ 807 miir &= ~MASK_MIIR_MII_MDC; 808 iowrite32(miir, miiport); 809 } 810 811 812 static int netdev_open(struct net_device *dev) 813 { 814 struct netdev_private *np = netdev_priv(dev); 815 void __iomem *ioaddr = np->mem; 816 const int irq = np->pci_dev->irq; 817 int rc, i; 818 819 iowrite32(0x00000001, ioaddr + BCR); /* Reset */ 820 821 rc = request_irq(irq, intr_handler, IRQF_SHARED, dev->name, dev); 822 if (rc) 823 return -EAGAIN; 824 825 for (i = 0; i < 3; i++) 826 iowrite16(((unsigned short*)dev->dev_addr)[i], 827 ioaddr + PAR0 + i*2); 828 829 init_ring(dev); 830 831 iowrite32(np->rx_ring_dma, ioaddr + RXLBA); 832 iowrite32(np->tx_ring_dma, ioaddr + TXLBA); 833 834 /* Initialize other registers. */ 835 /* Configure the PCI bus bursts and FIFO thresholds. 836 486: Set 8 longword burst. 837 586: no burst limit. 838 Burst length 5:3 839 0 0 0 1 840 0 0 1 4 841 0 1 0 8 842 0 1 1 16 843 1 0 0 32 844 1 0 1 64 845 1 1 0 128 846 1 1 1 256 847 Wait the specified 50 PCI cycles after a reset by initializing 848 Tx and Rx queues and the address filter list. 849 FIXME (Ueimor): optimistic for alpha + posted writes ? */ 850 851 np->bcrvalue = 0x10; /* little-endian, 8 burst length */ 852 #ifdef __BIG_ENDIAN 853 np->bcrvalue |= 0x04; /* big-endian */ 854 #endif 855 856 #if defined(__i386__) && !defined(MODULE) 857 if (boot_cpu_data.x86 <= 4) 858 np->crvalue = 0xa00; 859 else 860 #endif 861 np->crvalue = 0xe00; /* rx 128 burst length */ 862 863 864 // 89/12/29 add, 865 // 90/1/16 modify, 866 // np->imrvalue=FBE|TUNF|CNTOVF|RBU|TI|RI; 867 np->imrvalue = TUNF | CNTOVF | RBU | TI | RI; 868 if (np->pci_dev->device == 0x891) { 869 np->bcrvalue |= 0x200; /* set PROG bit */ 870 np->crvalue |= CR_W_ENH; /* set enhanced bit */ 871 np->imrvalue |= ETI; 872 } 873 iowrite32(np->bcrvalue, ioaddr + BCR); 874 875 if (dev->if_port == 0) 876 dev->if_port = np->default_port; 877 878 iowrite32(0, ioaddr + RXPDR); 879 // 89/9/1 modify, 880 // np->crvalue = 0x00e40001; /* tx store and forward, tx/rx enable */ 881 np->crvalue |= 0x00e40001; /* tx store and forward, tx/rx enable */ 882 np->mii.full_duplex = np->mii.force_media; 883 getlinkstatus(dev); 884 if (np->linkok) 885 getlinktype(dev); 886 __set_rx_mode(dev); 887 888 netif_start_queue(dev); 889 890 /* Clear and Enable interrupts by setting the interrupt mask. */ 891 iowrite32(FBE | TUNF | CNTOVF | RBU | TI | RI, ioaddr + ISR); 892 iowrite32(np->imrvalue, ioaddr + IMR); 893 894 if (debug) 895 printk(KERN_DEBUG "%s: Done netdev_open().\n", dev->name); 896 897 /* Set the timer to check for link beat. */ 898 timer_setup(&np->timer, netdev_timer, 0); 899 np->timer.expires = RUN_AT(3 * HZ); 900 901 /* timer handler */ 902 add_timer(&np->timer); 903 904 timer_setup(&np->reset_timer, reset_timer, 0); 905 np->reset_timer_armed = 0; 906 return rc; 907 } 908 909 910 static void getlinkstatus(struct net_device *dev) 911 /* function: Routine will read MII Status Register to get link status. */ 912 /* input : dev... pointer to the adapter block. */ 913 /* output : none. */ 914 { 915 struct netdev_private *np = netdev_priv(dev); 916 unsigned int i, DelayTime = 0x1000; 917 918 np->linkok = 0; 919 920 if (np->PHYType == MysonPHY) { 921 for (i = 0; i < DelayTime; ++i) { 922 if (ioread32(np->mem + BMCRSR) & LinkIsUp2) { 923 np->linkok = 1; 924 return; 925 } 926 udelay(100); 927 } 928 } else { 929 for (i = 0; i < DelayTime; ++i) { 930 if (mdio_read(dev, np->phys[0], MII_BMSR) & BMSR_LSTATUS) { 931 np->linkok = 1; 932 return; 933 } 934 udelay(100); 935 } 936 } 937 } 938 939 940 static void getlinktype(struct net_device *dev) 941 { 942 struct netdev_private *np = netdev_priv(dev); 943 944 if (np->PHYType == MysonPHY) { /* 3-in-1 case */ 945 if (ioread32(np->mem + TCRRCR) & CR_R_FD) 946 np->duplexmode = 2; /* full duplex */ 947 else 948 np->duplexmode = 1; /* half duplex */ 949 if (ioread32(np->mem + TCRRCR) & CR_R_PS10) 950 np->line_speed = 1; /* 10M */ 951 else 952 np->line_speed = 2; /* 100M */ 953 } else { 954 if (np->PHYType == SeeqPHY) { /* this PHY is SEEQ 80225 */ 955 unsigned int data; 956 957 data = mdio_read(dev, np->phys[0], MIIRegister18); 958 if (data & SPD_DET_100) 959 np->line_speed = 2; /* 100M */ 960 else 961 np->line_speed = 1; /* 10M */ 962 if (data & DPLX_DET_FULL) 963 np->duplexmode = 2; /* full duplex mode */ 964 else 965 np->duplexmode = 1; /* half duplex mode */ 966 } else if (np->PHYType == AhdocPHY) { 967 unsigned int data; 968 969 data = mdio_read(dev, np->phys[0], DiagnosticReg); 970 if (data & Speed_100) 971 np->line_speed = 2; /* 100M */ 972 else 973 np->line_speed = 1; /* 10M */ 974 if (data & DPLX_FULL) 975 np->duplexmode = 2; /* full duplex mode */ 976 else 977 np->duplexmode = 1; /* half duplex mode */ 978 } 979 /* 89/6/13 add, (begin) */ 980 else if (np->PHYType == MarvellPHY) { 981 unsigned int data; 982 983 data = mdio_read(dev, np->phys[0], SpecificReg); 984 if (data & Full_Duplex) 985 np->duplexmode = 2; /* full duplex mode */ 986 else 987 np->duplexmode = 1; /* half duplex mode */ 988 data &= SpeedMask; 989 if (data == Speed_1000M) 990 np->line_speed = 3; /* 1000M */ 991 else if (data == Speed_100M) 992 np->line_speed = 2; /* 100M */ 993 else 994 np->line_speed = 1; /* 10M */ 995 } 996 /* 89/6/13 add, (end) */ 997 /* 89/7/27 add, (begin) */ 998 else if (np->PHYType == Myson981) { 999 unsigned int data; 1000 1001 data = mdio_read(dev, np->phys[0], StatusRegister); 1002 1003 if (data & SPEED100) 1004 np->line_speed = 2; 1005 else 1006 np->line_speed = 1; 1007 1008 if (data & FULLMODE) 1009 np->duplexmode = 2; 1010 else 1011 np->duplexmode = 1; 1012 } 1013 /* 89/7/27 add, (end) */ 1014 /* 89/12/29 add */ 1015 else if (np->PHYType == LevelOnePHY) { 1016 unsigned int data; 1017 1018 data = mdio_read(dev, np->phys[0], SpecificReg); 1019 if (data & LXT1000_Full) 1020 np->duplexmode = 2; /* full duplex mode */ 1021 else 1022 np->duplexmode = 1; /* half duplex mode */ 1023 data &= SpeedMask; 1024 if (data == LXT1000_1000M) 1025 np->line_speed = 3; /* 1000M */ 1026 else if (data == LXT1000_100M) 1027 np->line_speed = 2; /* 100M */ 1028 else 1029 np->line_speed = 1; /* 10M */ 1030 } 1031 np->crvalue &= (~CR_W_PS10) & (~CR_W_FD) & (~CR_W_PS1000); 1032 if (np->line_speed == 1) 1033 np->crvalue |= CR_W_PS10; 1034 else if (np->line_speed == 3) 1035 np->crvalue |= CR_W_PS1000; 1036 if (np->duplexmode == 2) 1037 np->crvalue |= CR_W_FD; 1038 } 1039 } 1040 1041 1042 /* Take lock before calling this */ 1043 static void allocate_rx_buffers(struct net_device *dev) 1044 { 1045 struct netdev_private *np = netdev_priv(dev); 1046 1047 /* allocate skb for rx buffers */ 1048 while (np->really_rx_count != RX_RING_SIZE) { 1049 struct sk_buff *skb; 1050 1051 skb = netdev_alloc_skb(dev, np->rx_buf_sz); 1052 if (skb == NULL) 1053 break; /* Better luck next round. */ 1054 1055 while (np->lack_rxbuf->skbuff) 1056 np->lack_rxbuf = np->lack_rxbuf->next_desc_logical; 1057 1058 np->lack_rxbuf->skbuff = skb; 1059 np->lack_rxbuf->buffer = pci_map_single(np->pci_dev, skb->data, 1060 np->rx_buf_sz, PCI_DMA_FROMDEVICE); 1061 np->lack_rxbuf->status = RXOWN; 1062 ++np->really_rx_count; 1063 } 1064 } 1065 1066 1067 static void netdev_timer(struct timer_list *t) 1068 { 1069 struct netdev_private *np = from_timer(np, t, timer); 1070 struct net_device *dev = np->mii.dev; 1071 void __iomem *ioaddr = np->mem; 1072 int old_crvalue = np->crvalue; 1073 unsigned int old_linkok = np->linkok; 1074 unsigned long flags; 1075 1076 if (debug) 1077 printk(KERN_DEBUG "%s: Media selection timer tick, status %8.8x " 1078 "config %8.8x.\n", dev->name, ioread32(ioaddr + ISR), 1079 ioread32(ioaddr + TCRRCR)); 1080 1081 spin_lock_irqsave(&np->lock, flags); 1082 1083 if (np->flags == HAS_MII_XCVR) { 1084 getlinkstatus(dev); 1085 if ((old_linkok == 0) && (np->linkok == 1)) { /* we need to detect the media type again */ 1086 getlinktype(dev); 1087 if (np->crvalue != old_crvalue) { 1088 stop_nic_rxtx(ioaddr, np->crvalue); 1089 iowrite32(np->crvalue, ioaddr + TCRRCR); 1090 } 1091 } 1092 } 1093 1094 allocate_rx_buffers(dev); 1095 1096 spin_unlock_irqrestore(&np->lock, flags); 1097 1098 np->timer.expires = RUN_AT(10 * HZ); 1099 add_timer(&np->timer); 1100 } 1101 1102 1103 /* Take lock before calling */ 1104 /* Reset chip and disable rx, tx and interrupts */ 1105 static void reset_and_disable_rxtx(struct net_device *dev) 1106 { 1107 struct netdev_private *np = netdev_priv(dev); 1108 void __iomem *ioaddr = np->mem; 1109 int delay=51; 1110 1111 /* Reset the chip's Tx and Rx processes. */ 1112 stop_nic_rxtx(ioaddr, 0); 1113 1114 /* Disable interrupts by clearing the interrupt mask. */ 1115 iowrite32(0, ioaddr + IMR); 1116 1117 /* Reset the chip to erase previous misconfiguration. */ 1118 iowrite32(0x00000001, ioaddr + BCR); 1119 1120 /* Ueimor: wait for 50 PCI cycles (and flush posted writes btw). 1121 We surely wait too long (address+data phase). Who cares? */ 1122 while (--delay) { 1123 ioread32(ioaddr + BCR); 1124 rmb(); 1125 } 1126 } 1127 1128 1129 /* Take lock before calling */ 1130 /* Restore chip after reset */ 1131 static void enable_rxtx(struct net_device *dev) 1132 { 1133 struct netdev_private *np = netdev_priv(dev); 1134 void __iomem *ioaddr = np->mem; 1135 1136 reset_rx_descriptors(dev); 1137 1138 iowrite32(np->tx_ring_dma + ((char*)np->cur_tx - (char*)np->tx_ring), 1139 ioaddr + TXLBA); 1140 iowrite32(np->rx_ring_dma + ((char*)np->cur_rx - (char*)np->rx_ring), 1141 ioaddr + RXLBA); 1142 1143 iowrite32(np->bcrvalue, ioaddr + BCR); 1144 1145 iowrite32(0, ioaddr + RXPDR); 1146 __set_rx_mode(dev); /* changes np->crvalue, writes it into TCRRCR */ 1147 1148 /* Clear and Enable interrupts by setting the interrupt mask. */ 1149 iowrite32(FBE | TUNF | CNTOVF | RBU | TI | RI, ioaddr + ISR); 1150 iowrite32(np->imrvalue, ioaddr + IMR); 1151 1152 iowrite32(0, ioaddr + TXPDR); 1153 } 1154 1155 1156 static void reset_timer(struct timer_list *t) 1157 { 1158 struct netdev_private *np = from_timer(np, t, reset_timer); 1159 struct net_device *dev = np->mii.dev; 1160 unsigned long flags; 1161 1162 printk(KERN_WARNING "%s: resetting tx and rx machinery\n", dev->name); 1163 1164 spin_lock_irqsave(&np->lock, flags); 1165 np->crvalue = np->crvalue_sv; 1166 np->imrvalue = np->imrvalue_sv; 1167 1168 reset_and_disable_rxtx(dev); 1169 /* works for me without this: 1170 reset_tx_descriptors(dev); */ 1171 enable_rxtx(dev); 1172 netif_start_queue(dev); /* FIXME: or netif_wake_queue(dev); ? */ 1173 1174 np->reset_timer_armed = 0; 1175 1176 spin_unlock_irqrestore(&np->lock, flags); 1177 } 1178 1179 1180 static void fealnx_tx_timeout(struct net_device *dev, unsigned int txqueue) 1181 { 1182 struct netdev_private *np = netdev_priv(dev); 1183 void __iomem *ioaddr = np->mem; 1184 unsigned long flags; 1185 int i; 1186 1187 printk(KERN_WARNING 1188 "%s: Transmit timed out, status %8.8x, resetting...\n", 1189 dev->name, ioread32(ioaddr + ISR)); 1190 1191 { 1192 printk(KERN_DEBUG " Rx ring %p: ", np->rx_ring); 1193 for (i = 0; i < RX_RING_SIZE; i++) 1194 printk(KERN_CONT " %8.8x", 1195 (unsigned int) np->rx_ring[i].status); 1196 printk(KERN_CONT "\n"); 1197 printk(KERN_DEBUG " Tx ring %p: ", np->tx_ring); 1198 for (i = 0; i < TX_RING_SIZE; i++) 1199 printk(KERN_CONT " %4.4x", np->tx_ring[i].status); 1200 printk(KERN_CONT "\n"); 1201 } 1202 1203 spin_lock_irqsave(&np->lock, flags); 1204 1205 reset_and_disable_rxtx(dev); 1206 reset_tx_descriptors(dev); 1207 enable_rxtx(dev); 1208 1209 spin_unlock_irqrestore(&np->lock, flags); 1210 1211 netif_trans_update(dev); /* prevent tx timeout */ 1212 dev->stats.tx_errors++; 1213 netif_wake_queue(dev); /* or .._start_.. ?? */ 1214 } 1215 1216 1217 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */ 1218 static void init_ring(struct net_device *dev) 1219 { 1220 struct netdev_private *np = netdev_priv(dev); 1221 int i; 1222 1223 /* initialize rx variables */ 1224 np->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32); 1225 np->cur_rx = &np->rx_ring[0]; 1226 np->lack_rxbuf = np->rx_ring; 1227 np->really_rx_count = 0; 1228 1229 /* initial rx descriptors. */ 1230 for (i = 0; i < RX_RING_SIZE; i++) { 1231 np->rx_ring[i].status = 0; 1232 np->rx_ring[i].control = np->rx_buf_sz << RBSShift; 1233 np->rx_ring[i].next_desc = np->rx_ring_dma + 1234 (i + 1)*sizeof(struct fealnx_desc); 1235 np->rx_ring[i].next_desc_logical = &np->rx_ring[i + 1]; 1236 np->rx_ring[i].skbuff = NULL; 1237 } 1238 1239 /* for the last rx descriptor */ 1240 np->rx_ring[i - 1].next_desc = np->rx_ring_dma; 1241 np->rx_ring[i - 1].next_desc_logical = np->rx_ring; 1242 1243 /* allocate skb for rx buffers */ 1244 for (i = 0; i < RX_RING_SIZE; i++) { 1245 struct sk_buff *skb = netdev_alloc_skb(dev, np->rx_buf_sz); 1246 1247 if (skb == NULL) { 1248 np->lack_rxbuf = &np->rx_ring[i]; 1249 break; 1250 } 1251 1252 ++np->really_rx_count; 1253 np->rx_ring[i].skbuff = skb; 1254 np->rx_ring[i].buffer = pci_map_single(np->pci_dev, skb->data, 1255 np->rx_buf_sz, PCI_DMA_FROMDEVICE); 1256 np->rx_ring[i].status = RXOWN; 1257 np->rx_ring[i].control |= RXIC; 1258 } 1259 1260 /* initialize tx variables */ 1261 np->cur_tx = &np->tx_ring[0]; 1262 np->cur_tx_copy = &np->tx_ring[0]; 1263 np->really_tx_count = 0; 1264 np->free_tx_count = TX_RING_SIZE; 1265 1266 for (i = 0; i < TX_RING_SIZE; i++) { 1267 np->tx_ring[i].status = 0; 1268 /* do we need np->tx_ring[i].control = XXX; ?? */ 1269 np->tx_ring[i].next_desc = np->tx_ring_dma + 1270 (i + 1)*sizeof(struct fealnx_desc); 1271 np->tx_ring[i].next_desc_logical = &np->tx_ring[i + 1]; 1272 np->tx_ring[i].skbuff = NULL; 1273 } 1274 1275 /* for the last tx descriptor */ 1276 np->tx_ring[i - 1].next_desc = np->tx_ring_dma; 1277 np->tx_ring[i - 1].next_desc_logical = &np->tx_ring[0]; 1278 } 1279 1280 1281 static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev) 1282 { 1283 struct netdev_private *np = netdev_priv(dev); 1284 unsigned long flags; 1285 1286 spin_lock_irqsave(&np->lock, flags); 1287 1288 np->cur_tx_copy->skbuff = skb; 1289 1290 #define one_buffer 1291 #define BPT 1022 1292 #if defined(one_buffer) 1293 np->cur_tx_copy->buffer = pci_map_single(np->pci_dev, skb->data, 1294 skb->len, PCI_DMA_TODEVICE); 1295 np->cur_tx_copy->control = TXIC | TXLD | TXFD | CRCEnable | PADEnable; 1296 np->cur_tx_copy->control |= (skb->len << PKTSShift); /* pkt size */ 1297 np->cur_tx_copy->control |= (skb->len << TBSShift); /* buffer size */ 1298 // 89/12/29 add, 1299 if (np->pci_dev->device == 0x891) 1300 np->cur_tx_copy->control |= ETIControl | RetryTxLC; 1301 np->cur_tx_copy->status = TXOWN; 1302 np->cur_tx_copy = np->cur_tx_copy->next_desc_logical; 1303 --np->free_tx_count; 1304 #elif defined(two_buffer) 1305 if (skb->len > BPT) { 1306 struct fealnx_desc *next; 1307 1308 /* for the first descriptor */ 1309 np->cur_tx_copy->buffer = pci_map_single(np->pci_dev, skb->data, 1310 BPT, PCI_DMA_TODEVICE); 1311 np->cur_tx_copy->control = TXIC | TXFD | CRCEnable | PADEnable; 1312 np->cur_tx_copy->control |= (skb->len << PKTSShift); /* pkt size */ 1313 np->cur_tx_copy->control |= (BPT << TBSShift); /* buffer size */ 1314 1315 /* for the last descriptor */ 1316 next = np->cur_tx_copy->next_desc_logical; 1317 next->skbuff = skb; 1318 next->control = TXIC | TXLD | CRCEnable | PADEnable; 1319 next->control |= (skb->len << PKTSShift); /* pkt size */ 1320 next->control |= ((skb->len - BPT) << TBSShift); /* buf size */ 1321 // 89/12/29 add, 1322 if (np->pci_dev->device == 0x891) 1323 np->cur_tx_copy->control |= ETIControl | RetryTxLC; 1324 next->buffer = pci_map_single(ep->pci_dev, skb->data + BPT, 1325 skb->len - BPT, PCI_DMA_TODEVICE); 1326 1327 next->status = TXOWN; 1328 np->cur_tx_copy->status = TXOWN; 1329 1330 np->cur_tx_copy = next->next_desc_logical; 1331 np->free_tx_count -= 2; 1332 } else { 1333 np->cur_tx_copy->buffer = pci_map_single(np->pci_dev, skb->data, 1334 skb->len, PCI_DMA_TODEVICE); 1335 np->cur_tx_copy->control = TXIC | TXLD | TXFD | CRCEnable | PADEnable; 1336 np->cur_tx_copy->control |= (skb->len << PKTSShift); /* pkt size */ 1337 np->cur_tx_copy->control |= (skb->len << TBSShift); /* buffer size */ 1338 // 89/12/29 add, 1339 if (np->pci_dev->device == 0x891) 1340 np->cur_tx_copy->control |= ETIControl | RetryTxLC; 1341 np->cur_tx_copy->status = TXOWN; 1342 np->cur_tx_copy = np->cur_tx_copy->next_desc_logical; 1343 --np->free_tx_count; 1344 } 1345 #endif 1346 1347 if (np->free_tx_count < 2) 1348 netif_stop_queue(dev); 1349 ++np->really_tx_count; 1350 iowrite32(0, np->mem + TXPDR); 1351 1352 spin_unlock_irqrestore(&np->lock, flags); 1353 return NETDEV_TX_OK; 1354 } 1355 1356 1357 /* Take lock before calling */ 1358 /* Chip probably hosed tx ring. Clean up. */ 1359 static void reset_tx_descriptors(struct net_device *dev) 1360 { 1361 struct netdev_private *np = netdev_priv(dev); 1362 struct fealnx_desc *cur; 1363 int i; 1364 1365 /* initialize tx variables */ 1366 np->cur_tx = &np->tx_ring[0]; 1367 np->cur_tx_copy = &np->tx_ring[0]; 1368 np->really_tx_count = 0; 1369 np->free_tx_count = TX_RING_SIZE; 1370 1371 for (i = 0; i < TX_RING_SIZE; i++) { 1372 cur = &np->tx_ring[i]; 1373 if (cur->skbuff) { 1374 pci_unmap_single(np->pci_dev, cur->buffer, 1375 cur->skbuff->len, PCI_DMA_TODEVICE); 1376 dev_kfree_skb_any(cur->skbuff); 1377 cur->skbuff = NULL; 1378 } 1379 cur->status = 0; 1380 cur->control = 0; /* needed? */ 1381 /* probably not needed. We do it for purely paranoid reasons */ 1382 cur->next_desc = np->tx_ring_dma + 1383 (i + 1)*sizeof(struct fealnx_desc); 1384 cur->next_desc_logical = &np->tx_ring[i + 1]; 1385 } 1386 /* for the last tx descriptor */ 1387 np->tx_ring[TX_RING_SIZE - 1].next_desc = np->tx_ring_dma; 1388 np->tx_ring[TX_RING_SIZE - 1].next_desc_logical = &np->tx_ring[0]; 1389 } 1390 1391 1392 /* Take lock and stop rx before calling this */ 1393 static void reset_rx_descriptors(struct net_device *dev) 1394 { 1395 struct netdev_private *np = netdev_priv(dev); 1396 struct fealnx_desc *cur = np->cur_rx; 1397 int i; 1398 1399 allocate_rx_buffers(dev); 1400 1401 for (i = 0; i < RX_RING_SIZE; i++) { 1402 if (cur->skbuff) 1403 cur->status = RXOWN; 1404 cur = cur->next_desc_logical; 1405 } 1406 1407 iowrite32(np->rx_ring_dma + ((char*)np->cur_rx - (char*)np->rx_ring), 1408 np->mem + RXLBA); 1409 } 1410 1411 1412 /* The interrupt handler does all of the Rx thread work and cleans up 1413 after the Tx thread. */ 1414 static irqreturn_t intr_handler(int irq, void *dev_instance) 1415 { 1416 struct net_device *dev = (struct net_device *) dev_instance; 1417 struct netdev_private *np = netdev_priv(dev); 1418 void __iomem *ioaddr = np->mem; 1419 long boguscnt = max_interrupt_work; 1420 unsigned int num_tx = 0; 1421 int handled = 0; 1422 1423 spin_lock(&np->lock); 1424 1425 iowrite32(0, ioaddr + IMR); 1426 1427 do { 1428 u32 intr_status = ioread32(ioaddr + ISR); 1429 1430 /* Acknowledge all of the current interrupt sources ASAP. */ 1431 iowrite32(intr_status, ioaddr + ISR); 1432 1433 if (debug) 1434 printk(KERN_DEBUG "%s: Interrupt, status %4.4x.\n", dev->name, 1435 intr_status); 1436 1437 if (!(intr_status & np->imrvalue)) 1438 break; 1439 1440 handled = 1; 1441 1442 // 90/1/16 delete, 1443 // 1444 // if (intr_status & FBE) 1445 // { /* fatal error */ 1446 // stop_nic_tx(ioaddr, 0); 1447 // stop_nic_rx(ioaddr, 0); 1448 // break; 1449 // }; 1450 1451 if (intr_status & TUNF) 1452 iowrite32(0, ioaddr + TXPDR); 1453 1454 if (intr_status & CNTOVF) { 1455 /* missed pkts */ 1456 dev->stats.rx_missed_errors += 1457 ioread32(ioaddr + TALLY) & 0x7fff; 1458 1459 /* crc error */ 1460 dev->stats.rx_crc_errors += 1461 (ioread32(ioaddr + TALLY) & 0x7fff0000) >> 16; 1462 } 1463 1464 if (intr_status & (RI | RBU)) { 1465 if (intr_status & RI) 1466 netdev_rx(dev); 1467 else { 1468 stop_nic_rx(ioaddr, np->crvalue); 1469 reset_rx_descriptors(dev); 1470 iowrite32(np->crvalue, ioaddr + TCRRCR); 1471 } 1472 } 1473 1474 while (np->really_tx_count) { 1475 long tx_status = np->cur_tx->status; 1476 long tx_control = np->cur_tx->control; 1477 1478 if (!(tx_control & TXLD)) { /* this pkt is combined by two tx descriptors */ 1479 struct fealnx_desc *next; 1480 1481 next = np->cur_tx->next_desc_logical; 1482 tx_status = next->status; 1483 tx_control = next->control; 1484 } 1485 1486 if (tx_status & TXOWN) 1487 break; 1488 1489 if (!(np->crvalue & CR_W_ENH)) { 1490 if (tx_status & (CSL | LC | EC | UDF | HF)) { 1491 dev->stats.tx_errors++; 1492 if (tx_status & EC) 1493 dev->stats.tx_aborted_errors++; 1494 if (tx_status & CSL) 1495 dev->stats.tx_carrier_errors++; 1496 if (tx_status & LC) 1497 dev->stats.tx_window_errors++; 1498 if (tx_status & UDF) 1499 dev->stats.tx_fifo_errors++; 1500 if ((tx_status & HF) && np->mii.full_duplex == 0) 1501 dev->stats.tx_heartbeat_errors++; 1502 1503 } else { 1504 dev->stats.tx_bytes += 1505 ((tx_control & PKTSMask) >> PKTSShift); 1506 1507 dev->stats.collisions += 1508 ((tx_status & NCRMask) >> NCRShift); 1509 dev->stats.tx_packets++; 1510 } 1511 } else { 1512 dev->stats.tx_bytes += 1513 ((tx_control & PKTSMask) >> PKTSShift); 1514 dev->stats.tx_packets++; 1515 } 1516 1517 /* Free the original skb. */ 1518 pci_unmap_single(np->pci_dev, np->cur_tx->buffer, 1519 np->cur_tx->skbuff->len, PCI_DMA_TODEVICE); 1520 dev_consume_skb_irq(np->cur_tx->skbuff); 1521 np->cur_tx->skbuff = NULL; 1522 --np->really_tx_count; 1523 if (np->cur_tx->control & TXLD) { 1524 np->cur_tx = np->cur_tx->next_desc_logical; 1525 ++np->free_tx_count; 1526 } else { 1527 np->cur_tx = np->cur_tx->next_desc_logical; 1528 np->cur_tx = np->cur_tx->next_desc_logical; 1529 np->free_tx_count += 2; 1530 } 1531 num_tx++; 1532 } /* end of for loop */ 1533 1534 if (num_tx && np->free_tx_count >= 2) 1535 netif_wake_queue(dev); 1536 1537 /* read transmit status for enhanced mode only */ 1538 if (np->crvalue & CR_W_ENH) { 1539 long data; 1540 1541 data = ioread32(ioaddr + TSR); 1542 dev->stats.tx_errors += (data & 0xff000000) >> 24; 1543 dev->stats.tx_aborted_errors += 1544 (data & 0xff000000) >> 24; 1545 dev->stats.tx_window_errors += 1546 (data & 0x00ff0000) >> 16; 1547 dev->stats.collisions += (data & 0x0000ffff); 1548 } 1549 1550 if (--boguscnt < 0) { 1551 printk(KERN_WARNING "%s: Too much work at interrupt, " 1552 "status=0x%4.4x.\n", dev->name, intr_status); 1553 if (!np->reset_timer_armed) { 1554 np->reset_timer_armed = 1; 1555 np->reset_timer.expires = RUN_AT(HZ/2); 1556 add_timer(&np->reset_timer); 1557 stop_nic_rxtx(ioaddr, 0); 1558 netif_stop_queue(dev); 1559 /* or netif_tx_disable(dev); ?? */ 1560 /* Prevent other paths from enabling tx,rx,intrs */ 1561 np->crvalue_sv = np->crvalue; 1562 np->imrvalue_sv = np->imrvalue; 1563 np->crvalue &= ~(CR_W_TXEN | CR_W_RXEN); /* or simply = 0? */ 1564 np->imrvalue = 0; 1565 } 1566 1567 break; 1568 } 1569 } while (1); 1570 1571 /* read the tally counters */ 1572 /* missed pkts */ 1573 dev->stats.rx_missed_errors += ioread32(ioaddr + TALLY) & 0x7fff; 1574 1575 /* crc error */ 1576 dev->stats.rx_crc_errors += 1577 (ioread32(ioaddr + TALLY) & 0x7fff0000) >> 16; 1578 1579 if (debug) 1580 printk(KERN_DEBUG "%s: exiting interrupt, status=%#4.4x.\n", 1581 dev->name, ioread32(ioaddr + ISR)); 1582 1583 iowrite32(np->imrvalue, ioaddr + IMR); 1584 1585 spin_unlock(&np->lock); 1586 1587 return IRQ_RETVAL(handled); 1588 } 1589 1590 1591 /* This routine is logically part of the interrupt handler, but separated 1592 for clarity and better register allocation. */ 1593 static int netdev_rx(struct net_device *dev) 1594 { 1595 struct netdev_private *np = netdev_priv(dev); 1596 void __iomem *ioaddr = np->mem; 1597 1598 /* If EOP is set on the next entry, it's a new packet. Send it up. */ 1599 while (!(np->cur_rx->status & RXOWN) && np->cur_rx->skbuff) { 1600 s32 rx_status = np->cur_rx->status; 1601 1602 if (np->really_rx_count == 0) 1603 break; 1604 1605 if (debug) 1606 printk(KERN_DEBUG " netdev_rx() status was %8.8x.\n", rx_status); 1607 1608 if ((!((rx_status & RXFSD) && (rx_status & RXLSD))) || 1609 (rx_status & ErrorSummary)) { 1610 if (rx_status & ErrorSummary) { /* there was a fatal error */ 1611 if (debug) 1612 printk(KERN_DEBUG 1613 "%s: Receive error, Rx status %8.8x.\n", 1614 dev->name, rx_status); 1615 1616 dev->stats.rx_errors++; /* end of a packet. */ 1617 if (rx_status & (LONGPKT | RUNTPKT)) 1618 dev->stats.rx_length_errors++; 1619 if (rx_status & RXER) 1620 dev->stats.rx_frame_errors++; 1621 if (rx_status & CRC) 1622 dev->stats.rx_crc_errors++; 1623 } else { 1624 int need_to_reset = 0; 1625 int desno = 0; 1626 1627 if (rx_status & RXFSD) { /* this pkt is too long, over one rx buffer */ 1628 struct fealnx_desc *cur; 1629 1630 /* check this packet is received completely? */ 1631 cur = np->cur_rx; 1632 while (desno <= np->really_rx_count) { 1633 ++desno; 1634 if ((!(cur->status & RXOWN)) && 1635 (cur->status & RXLSD)) 1636 break; 1637 /* goto next rx descriptor */ 1638 cur = cur->next_desc_logical; 1639 } 1640 if (desno > np->really_rx_count) 1641 need_to_reset = 1; 1642 } else /* RXLSD did not find, something error */ 1643 need_to_reset = 1; 1644 1645 if (need_to_reset == 0) { 1646 int i; 1647 1648 dev->stats.rx_length_errors++; 1649 1650 /* free all rx descriptors related this long pkt */ 1651 for (i = 0; i < desno; ++i) { 1652 if (!np->cur_rx->skbuff) { 1653 printk(KERN_DEBUG 1654 "%s: I'm scared\n", dev->name); 1655 break; 1656 } 1657 np->cur_rx->status = RXOWN; 1658 np->cur_rx = np->cur_rx->next_desc_logical; 1659 } 1660 continue; 1661 } else { /* rx error, need to reset this chip */ 1662 stop_nic_rx(ioaddr, np->crvalue); 1663 reset_rx_descriptors(dev); 1664 iowrite32(np->crvalue, ioaddr + TCRRCR); 1665 } 1666 break; /* exit the while loop */ 1667 } 1668 } else { /* this received pkt is ok */ 1669 1670 struct sk_buff *skb; 1671 /* Omit the four octet CRC from the length. */ 1672 short pkt_len = ((rx_status & FLNGMASK) >> FLNGShift) - 4; 1673 1674 #ifndef final_version 1675 if (debug) 1676 printk(KERN_DEBUG " netdev_rx() normal Rx pkt length %d" 1677 " status %x.\n", pkt_len, rx_status); 1678 #endif 1679 1680 /* Check if the packet is long enough to accept without copying 1681 to a minimally-sized skbuff. */ 1682 if (pkt_len < rx_copybreak && 1683 (skb = netdev_alloc_skb(dev, pkt_len + 2)) != NULL) { 1684 skb_reserve(skb, 2); /* 16 byte align the IP header */ 1685 pci_dma_sync_single_for_cpu(np->pci_dev, 1686 np->cur_rx->buffer, 1687 np->rx_buf_sz, 1688 PCI_DMA_FROMDEVICE); 1689 /* Call copy + cksum if available. */ 1690 1691 #if ! defined(__alpha__) 1692 skb_copy_to_linear_data(skb, 1693 np->cur_rx->skbuff->data, pkt_len); 1694 skb_put(skb, pkt_len); 1695 #else 1696 skb_put_data(skb, np->cur_rx->skbuff->data, 1697 pkt_len); 1698 #endif 1699 pci_dma_sync_single_for_device(np->pci_dev, 1700 np->cur_rx->buffer, 1701 np->rx_buf_sz, 1702 PCI_DMA_FROMDEVICE); 1703 } else { 1704 pci_unmap_single(np->pci_dev, 1705 np->cur_rx->buffer, 1706 np->rx_buf_sz, 1707 PCI_DMA_FROMDEVICE); 1708 skb_put(skb = np->cur_rx->skbuff, pkt_len); 1709 np->cur_rx->skbuff = NULL; 1710 --np->really_rx_count; 1711 } 1712 skb->protocol = eth_type_trans(skb, dev); 1713 netif_rx(skb); 1714 dev->stats.rx_packets++; 1715 dev->stats.rx_bytes += pkt_len; 1716 } 1717 1718 np->cur_rx = np->cur_rx->next_desc_logical; 1719 } /* end of while loop */ 1720 1721 /* allocate skb for rx buffers */ 1722 allocate_rx_buffers(dev); 1723 1724 return 0; 1725 } 1726 1727 1728 static struct net_device_stats *get_stats(struct net_device *dev) 1729 { 1730 struct netdev_private *np = netdev_priv(dev); 1731 void __iomem *ioaddr = np->mem; 1732 1733 /* The chip only need report frame silently dropped. */ 1734 if (netif_running(dev)) { 1735 dev->stats.rx_missed_errors += 1736 ioread32(ioaddr + TALLY) & 0x7fff; 1737 dev->stats.rx_crc_errors += 1738 (ioread32(ioaddr + TALLY) & 0x7fff0000) >> 16; 1739 } 1740 1741 return &dev->stats; 1742 } 1743 1744 1745 /* for dev->set_multicast_list */ 1746 static void set_rx_mode(struct net_device *dev) 1747 { 1748 spinlock_t *lp = &((struct netdev_private *)netdev_priv(dev))->lock; 1749 unsigned long flags; 1750 spin_lock_irqsave(lp, flags); 1751 __set_rx_mode(dev); 1752 spin_unlock_irqrestore(lp, flags); 1753 } 1754 1755 1756 /* Take lock before calling */ 1757 static void __set_rx_mode(struct net_device *dev) 1758 { 1759 struct netdev_private *np = netdev_priv(dev); 1760 void __iomem *ioaddr = np->mem; 1761 u32 mc_filter[2]; /* Multicast hash filter */ 1762 u32 rx_mode; 1763 1764 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */ 1765 memset(mc_filter, 0xff, sizeof(mc_filter)); 1766 rx_mode = CR_W_PROM | CR_W_AB | CR_W_AM; 1767 } else if ((netdev_mc_count(dev) > multicast_filter_limit) || 1768 (dev->flags & IFF_ALLMULTI)) { 1769 /* Too many to match, or accept all multicasts. */ 1770 memset(mc_filter, 0xff, sizeof(mc_filter)); 1771 rx_mode = CR_W_AB | CR_W_AM; 1772 } else { 1773 struct netdev_hw_addr *ha; 1774 1775 memset(mc_filter, 0, sizeof(mc_filter)); 1776 netdev_for_each_mc_addr(ha, dev) { 1777 unsigned int bit; 1778 bit = (ether_crc(ETH_ALEN, ha->addr) >> 26) ^ 0x3F; 1779 mc_filter[bit >> 5] |= (1 << bit); 1780 } 1781 rx_mode = CR_W_AB | CR_W_AM; 1782 } 1783 1784 stop_nic_rxtx(ioaddr, np->crvalue); 1785 1786 iowrite32(mc_filter[0], ioaddr + MAR0); 1787 iowrite32(mc_filter[1], ioaddr + MAR1); 1788 np->crvalue &= ~CR_W_RXMODEMASK; 1789 np->crvalue |= rx_mode; 1790 iowrite32(np->crvalue, ioaddr + TCRRCR); 1791 } 1792 1793 static void netdev_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) 1794 { 1795 struct netdev_private *np = netdev_priv(dev); 1796 1797 strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); 1798 strlcpy(info->bus_info, pci_name(np->pci_dev), sizeof(info->bus_info)); 1799 } 1800 1801 static int netdev_get_link_ksettings(struct net_device *dev, 1802 struct ethtool_link_ksettings *cmd) 1803 { 1804 struct netdev_private *np = netdev_priv(dev); 1805 1806 spin_lock_irq(&np->lock); 1807 mii_ethtool_get_link_ksettings(&np->mii, cmd); 1808 spin_unlock_irq(&np->lock); 1809 1810 return 0; 1811 } 1812 1813 static int netdev_set_link_ksettings(struct net_device *dev, 1814 const struct ethtool_link_ksettings *cmd) 1815 { 1816 struct netdev_private *np = netdev_priv(dev); 1817 int rc; 1818 1819 spin_lock_irq(&np->lock); 1820 rc = mii_ethtool_set_link_ksettings(&np->mii, cmd); 1821 spin_unlock_irq(&np->lock); 1822 1823 return rc; 1824 } 1825 1826 static int netdev_nway_reset(struct net_device *dev) 1827 { 1828 struct netdev_private *np = netdev_priv(dev); 1829 return mii_nway_restart(&np->mii); 1830 } 1831 1832 static u32 netdev_get_link(struct net_device *dev) 1833 { 1834 struct netdev_private *np = netdev_priv(dev); 1835 return mii_link_ok(&np->mii); 1836 } 1837 1838 static u32 netdev_get_msglevel(struct net_device *dev) 1839 { 1840 return debug; 1841 } 1842 1843 static void netdev_set_msglevel(struct net_device *dev, u32 value) 1844 { 1845 debug = value; 1846 } 1847 1848 static const struct ethtool_ops netdev_ethtool_ops = { 1849 .get_drvinfo = netdev_get_drvinfo, 1850 .nway_reset = netdev_nway_reset, 1851 .get_link = netdev_get_link, 1852 .get_msglevel = netdev_get_msglevel, 1853 .set_msglevel = netdev_set_msglevel, 1854 .get_link_ksettings = netdev_get_link_ksettings, 1855 .set_link_ksettings = netdev_set_link_ksettings, 1856 }; 1857 1858 static int mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 1859 { 1860 struct netdev_private *np = netdev_priv(dev); 1861 int rc; 1862 1863 if (!netif_running(dev)) 1864 return -EINVAL; 1865 1866 spin_lock_irq(&np->lock); 1867 rc = generic_mii_ioctl(&np->mii, if_mii(rq), cmd, NULL); 1868 spin_unlock_irq(&np->lock); 1869 1870 return rc; 1871 } 1872 1873 1874 static int netdev_close(struct net_device *dev) 1875 { 1876 struct netdev_private *np = netdev_priv(dev); 1877 void __iomem *ioaddr = np->mem; 1878 int i; 1879 1880 netif_stop_queue(dev); 1881 1882 /* Disable interrupts by clearing the interrupt mask. */ 1883 iowrite32(0x0000, ioaddr + IMR); 1884 1885 /* Stop the chip's Tx and Rx processes. */ 1886 stop_nic_rxtx(ioaddr, 0); 1887 1888 del_timer_sync(&np->timer); 1889 del_timer_sync(&np->reset_timer); 1890 1891 free_irq(np->pci_dev->irq, dev); 1892 1893 /* Free all the skbuffs in the Rx queue. */ 1894 for (i = 0; i < RX_RING_SIZE; i++) { 1895 struct sk_buff *skb = np->rx_ring[i].skbuff; 1896 1897 np->rx_ring[i].status = 0; 1898 if (skb) { 1899 pci_unmap_single(np->pci_dev, np->rx_ring[i].buffer, 1900 np->rx_buf_sz, PCI_DMA_FROMDEVICE); 1901 dev_kfree_skb(skb); 1902 np->rx_ring[i].skbuff = NULL; 1903 } 1904 } 1905 1906 for (i = 0; i < TX_RING_SIZE; i++) { 1907 struct sk_buff *skb = np->tx_ring[i].skbuff; 1908 1909 if (skb) { 1910 pci_unmap_single(np->pci_dev, np->tx_ring[i].buffer, 1911 skb->len, PCI_DMA_TODEVICE); 1912 dev_kfree_skb(skb); 1913 np->tx_ring[i].skbuff = NULL; 1914 } 1915 } 1916 1917 return 0; 1918 } 1919 1920 static const struct pci_device_id fealnx_pci_tbl[] = { 1921 {0x1516, 0x0800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 1922 {0x1516, 0x0803, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1}, 1923 {0x1516, 0x0891, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2}, 1924 {} /* terminate list */ 1925 }; 1926 MODULE_DEVICE_TABLE(pci, fealnx_pci_tbl); 1927 1928 1929 static struct pci_driver fealnx_driver = { 1930 .name = "fealnx", 1931 .id_table = fealnx_pci_tbl, 1932 .probe = fealnx_init_one, 1933 .remove = fealnx_remove_one, 1934 }; 1935 1936 static int __init fealnx_init(void) 1937 { 1938 return pci_register_driver(&fealnx_driver); 1939 } 1940 1941 static void __exit fealnx_exit(void) 1942 { 1943 pci_unregister_driver(&fealnx_driver); 1944 } 1945 1946 module_init(fealnx_init); 1947 module_exit(fealnx_exit); 1948