1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * Faraday FTMAC100 10/100 Ethernet
4  *
5  * (C) Copyright 2009-2011 Faraday Technology
6  * Po-Yu Chuang <ratbert@faraday-tech.com>
7  */
8 
9 #ifndef __FTMAC100_H
10 #define __FTMAC100_H
11 
12 #define	FTMAC100_OFFSET_ISR		0x00
13 #define	FTMAC100_OFFSET_IMR		0x04
14 #define	FTMAC100_OFFSET_MAC_MADR	0x08
15 #define	FTMAC100_OFFSET_MAC_LADR	0x0c
16 #define	FTMAC100_OFFSET_MAHT0		0x10
17 #define	FTMAC100_OFFSET_MAHT1		0x14
18 #define	FTMAC100_OFFSET_TXPD		0x18
19 #define	FTMAC100_OFFSET_RXPD		0x1c
20 #define	FTMAC100_OFFSET_TXR_BADR	0x20
21 #define	FTMAC100_OFFSET_RXR_BADR	0x24
22 #define	FTMAC100_OFFSET_ITC		0x28
23 #define	FTMAC100_OFFSET_APTC		0x2c
24 #define	FTMAC100_OFFSET_DBLAC		0x30
25 #define	FTMAC100_OFFSET_MACCR		0x88
26 #define	FTMAC100_OFFSET_MACSR		0x8c
27 #define	FTMAC100_OFFSET_PHYCR		0x90
28 #define	FTMAC100_OFFSET_PHYWDATA	0x94
29 #define	FTMAC100_OFFSET_FCR		0x98
30 #define	FTMAC100_OFFSET_BPR		0x9c
31 #define	FTMAC100_OFFSET_TS		0xc4
32 #define	FTMAC100_OFFSET_DMAFIFOS	0xc8
33 #define	FTMAC100_OFFSET_TM		0xcc
34 #define	FTMAC100_OFFSET_TX_MCOL_SCOL	0xd4
35 #define	FTMAC100_OFFSET_RPF_AEP		0xd8
36 #define	FTMAC100_OFFSET_XM_PG		0xdc
37 #define	FTMAC100_OFFSET_RUNT_TLCC	0xe0
38 #define	FTMAC100_OFFSET_CRCER_FTL	0xe4
39 #define	FTMAC100_OFFSET_RLC_RCC		0xe8
40 #define	FTMAC100_OFFSET_BROC		0xec
41 #define	FTMAC100_OFFSET_MULCA		0xf0
42 #define	FTMAC100_OFFSET_RP		0xf4
43 #define	FTMAC100_OFFSET_XP		0xf8
44 
45 /*
46  * Interrupt status register & interrupt mask register
47  */
48 #define	FTMAC100_INT_RPKT_FINISH	(1 << 0)
49 #define	FTMAC100_INT_NORXBUF		(1 << 1)
50 #define	FTMAC100_INT_XPKT_FINISH	(1 << 2)
51 #define	FTMAC100_INT_NOTXBUF		(1 << 3)
52 #define	FTMAC100_INT_XPKT_OK		(1 << 4)
53 #define	FTMAC100_INT_XPKT_LOST		(1 << 5)
54 #define	FTMAC100_INT_RPKT_SAV		(1 << 6)
55 #define	FTMAC100_INT_RPKT_LOST		(1 << 7)
56 #define	FTMAC100_INT_AHB_ERR		(1 << 8)
57 #define	FTMAC100_INT_PHYSTS_CHG		(1 << 9)
58 
59 /*
60  * Interrupt timer control register
61  */
62 #define FTMAC100_ITC_RXINT_CNT(x)	(((x) & 0xf) << 0)
63 #define FTMAC100_ITC_RXINT_THR(x)	(((x) & 0x7) << 4)
64 #define FTMAC100_ITC_RXINT_TIME_SEL	(1 << 7)
65 #define FTMAC100_ITC_TXINT_CNT(x)	(((x) & 0xf) << 8)
66 #define FTMAC100_ITC_TXINT_THR(x)	(((x) & 0x7) << 12)
67 #define FTMAC100_ITC_TXINT_TIME_SEL	(1 << 15)
68 
69 /*
70  * Automatic polling timer control register
71  */
72 #define	FTMAC100_APTC_RXPOLL_CNT(x)	(((x) & 0xf) << 0)
73 #define	FTMAC100_APTC_RXPOLL_TIME_SEL	(1 << 4)
74 #define	FTMAC100_APTC_TXPOLL_CNT(x)	(((x) & 0xf) << 8)
75 #define	FTMAC100_APTC_TXPOLL_TIME_SEL	(1 << 12)
76 
77 /*
78  * DMA burst length and arbitration control register
79  */
80 #define FTMAC100_DBLAC_INCR4_EN		(1 << 0)
81 #define FTMAC100_DBLAC_INCR8_EN		(1 << 1)
82 #define FTMAC100_DBLAC_INCR16_EN	(1 << 2)
83 #define FTMAC100_DBLAC_RXFIFO_LTHR(x)	(((x) & 0x7) << 3)
84 #define FTMAC100_DBLAC_RXFIFO_HTHR(x)	(((x) & 0x7) << 6)
85 #define FTMAC100_DBLAC_RX_THR_EN	(1 << 9)
86 
87 /*
88  * MAC control register
89  */
90 #define	FTMAC100_MACCR_XDMA_EN		(1 << 0)
91 #define	FTMAC100_MACCR_RDMA_EN		(1 << 1)
92 #define	FTMAC100_MACCR_SW_RST		(1 << 2)
93 #define	FTMAC100_MACCR_LOOP_EN		(1 << 3)
94 #define	FTMAC100_MACCR_CRC_DIS		(1 << 4)
95 #define	FTMAC100_MACCR_XMT_EN		(1 << 5)
96 #define	FTMAC100_MACCR_ENRX_IN_HALFTX	(1 << 6)
97 #define	FTMAC100_MACCR_RCV_EN		(1 << 8)
98 #define	FTMAC100_MACCR_HT_MULTI_EN	(1 << 9)
99 #define	FTMAC100_MACCR_RX_RUNT		(1 << 10)
100 #define	FTMAC100_MACCR_RX_FTL		(1 << 11)
101 #define	FTMAC100_MACCR_RCV_ALL		(1 << 12)
102 #define	FTMAC100_MACCR_CRC_APD		(1 << 14)
103 #define	FTMAC100_MACCR_FULLDUP		(1 << 15)
104 #define	FTMAC100_MACCR_RX_MULTIPKT	(1 << 16)
105 #define	FTMAC100_MACCR_RX_BROADPKT	(1 << 17)
106 
107 /*
108  * PHY control register
109  */
110 #define FTMAC100_PHYCR_MIIRDATA		0xffff
111 #define FTMAC100_PHYCR_PHYAD(x)		(((x) & 0x1f) << 16)
112 #define FTMAC100_PHYCR_REGAD(x)		(((x) & 0x1f) << 21)
113 #define FTMAC100_PHYCR_MIIRD		(1 << 26)
114 #define FTMAC100_PHYCR_MIIWR		(1 << 27)
115 
116 /*
117  * PHY write data register
118  */
119 #define FTMAC100_PHYWDATA_MIIWDATA(x)	((x) & 0xffff)
120 
121 /*
122  * Transmit descriptor, aligned to 16 bytes
123  */
124 struct ftmac100_txdes {
125 	unsigned int	txdes0;
126 	unsigned int	txdes1;
127 	unsigned int	txdes2;	/* TXBUF_BADR */
128 	unsigned int	txdes3;	/* not used by HW */
129 } __attribute__ ((aligned(16)));
130 
131 #define	FTMAC100_TXDES0_TXPKT_LATECOL	(1 << 0)
132 #define	FTMAC100_TXDES0_TXPKT_EXSCOL	(1 << 1)
133 #define	FTMAC100_TXDES0_TXDMA_OWN	(1 << 31)
134 
135 #define	FTMAC100_TXDES1_TXBUF_SIZE(x)	((x) & 0x7ff)
136 #define	FTMAC100_TXDES1_LTS		(1 << 27)
137 #define	FTMAC100_TXDES1_FTS		(1 << 28)
138 #define	FTMAC100_TXDES1_TX2FIC		(1 << 29)
139 #define	FTMAC100_TXDES1_TXIC		(1 << 30)
140 #define	FTMAC100_TXDES1_EDOTR		(1 << 31)
141 
142 /*
143  * Receive descriptor, aligned to 16 bytes
144  */
145 struct ftmac100_rxdes {
146 	unsigned int	rxdes0;
147 	unsigned int	rxdes1;
148 	unsigned int	rxdes2;	/* RXBUF_BADR */
149 	unsigned int	rxdes3;	/* not used by HW */
150 } __attribute__ ((aligned(16)));
151 
152 #define	FTMAC100_RXDES0_RFL		0x7ff
153 #define	FTMAC100_RXDES0_MULTICAST	(1 << 16)
154 #define	FTMAC100_RXDES0_BROADCAST	(1 << 17)
155 #define	FTMAC100_RXDES0_RX_ERR		(1 << 18)
156 #define	FTMAC100_RXDES0_CRC_ERR		(1 << 19)
157 #define	FTMAC100_RXDES0_FTL		(1 << 20)
158 #define	FTMAC100_RXDES0_RUNT		(1 << 21)
159 #define	FTMAC100_RXDES0_RX_ODD_NB	(1 << 22)
160 #define	FTMAC100_RXDES0_LRS		(1 << 28)
161 #define	FTMAC100_RXDES0_FRS		(1 << 29)
162 #define	FTMAC100_RXDES0_RXDMA_OWN	(1 << 31)
163 
164 #define	FTMAC100_RXDES1_RXBUF_SIZE(x)	((x) & 0x7ff)
165 #define	FTMAC100_RXDES1_EDORR		(1 << 31)
166 
167 #endif /* __FTMAC100_H */
168