1 /* 2 * Copyright(c) 2015 EZchip Technologies. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * The full GNU General Public License is included in this distribution in 14 * the file called "COPYING". 15 */ 16 17 #ifndef _NPS_ENET_H 18 #define _NPS_ENET_H 19 20 /* default values */ 21 #define NPS_ENET_NAPI_POLL_WEIGHT 0x2 22 #define NPS_ENET_MAX_FRAME_LENGTH 0x3FFF 23 #define NPS_ENET_GE_MAC_CFG_0_TX_FC_RETR 0x7 24 #define NPS_ENET_GE_MAC_CFG_0_RX_IFG 0x5 25 #define NPS_ENET_GE_MAC_CFG_0_TX_IFG 0xC 26 #define NPS_ENET_GE_MAC_CFG_0_TX_PR_LEN 0x7 27 #define NPS_ENET_GE_MAC_CFG_2_STAT_EN 0x3 28 #define NPS_ENET_GE_MAC_CFG_3_RX_IFG_TH 0x14 29 #define NPS_ENET_GE_MAC_CFG_3_MAX_LEN 0x3FFC 30 #define NPS_ENET_ENABLE 1 31 #define NPS_ENET_DISABLE 0 32 33 /* register definitions */ 34 #define NPS_ENET_REG_TX_CTL 0x800 35 #define NPS_ENET_REG_TX_BUF 0x808 36 #define NPS_ENET_REG_RX_CTL 0x810 37 #define NPS_ENET_REG_RX_BUF 0x818 38 #define NPS_ENET_REG_BUF_INT_ENABLE 0x8C0 39 #define NPS_ENET_REG_BUF_INT_CAUSE 0x8C4 40 #define NPS_ENET_REG_GE_MAC_CFG_0 0x1000 41 #define NPS_ENET_REG_GE_MAC_CFG_1 0x1004 42 #define NPS_ENET_REG_GE_MAC_CFG_2 0x1008 43 #define NPS_ENET_REG_GE_MAC_CFG_3 0x100C 44 #define NPS_ENET_REG_GE_RST 0x1400 45 #define NPS_ENET_REG_PHASE_FIFO_CTL 0x1404 46 47 /* Tx control register */ 48 struct nps_enet_tx_ctl { 49 union { 50 /* ct: SW sets to indicate frame ready in Tx buffer for 51 * transmission. HW resets to when transmission done 52 * et: Transmit error 53 * nt: Length in bytes of Tx frame loaded to Tx buffer 54 */ 55 struct { 56 u32 57 __reserved_1:16, 58 ct:1, 59 et:1, 60 __reserved_2:3, 61 nt:11; 62 }; 63 64 u32 value; 65 }; 66 }; 67 68 /* Rx control register */ 69 struct nps_enet_rx_ctl { 70 union { 71 /* cr: HW sets to indicate frame ready in Rx buffer. 72 * SW resets to indicate host read received frame 73 * and new frames can be written to Rx buffer 74 * er: Rx error indication 75 * crc: Rx CRC error indication 76 * nr: Length in bytes of Rx frame loaded by MAC to Rx buffer 77 */ 78 struct { 79 u32 80 __reserved_1:16, 81 cr:1, 82 er:1, 83 crc:1, 84 __reserved_2:2, 85 nr:11; 86 }; 87 88 u32 value; 89 }; 90 }; 91 92 /* Interrupt enable for data buffer events register */ 93 struct nps_enet_buf_int_enable { 94 union { 95 /* tx_done: Interrupt generation in the case when new frame 96 * is ready in Rx buffer 97 * rx_rdy: Interrupt generation in the case when current frame 98 * was read from TX buffer 99 */ 100 struct { 101 u32 102 __reserved:30, 103 tx_done:1, 104 rx_rdy:1; 105 }; 106 107 u32 value; 108 }; 109 }; 110 111 /* Interrupt cause for data buffer events register */ 112 struct nps_enet_buf_int_cause { 113 union { 114 /* tx_done: Interrupt in the case when current frame was 115 * read from TX buffer. 116 * rx_rdy: Interrupt in the case when new frame is ready 117 * in RX buffer. 118 */ 119 struct { 120 u32 121 __reserved:30, 122 tx_done:1, 123 rx_rdy:1; 124 }; 125 126 u32 value; 127 }; 128 }; 129 130 /* Gbps Eth MAC Configuration 0 register */ 131 struct nps_enet_ge_mac_cfg_0 { 132 union { 133 /* tx_pr_len: Transmit preamble length in bytes 134 * tx_ifg_nib: Tx idle pattern 135 * nib_mode: Nibble (4-bit) Mode 136 * rx_pr_check_en: Receive preamble Check Enable 137 * tx_ifg: Transmit inter-Frame Gap 138 * rx_ifg: Receive inter-Frame Gap 139 * tx_fc_retr: Transmit Flow Control Retransmit Mode 140 * rx_length_check_en: Receive Length Check Enable 141 * rx_crc_ignore: Results of the CRC check are ignored 142 * rx_crc_strip: MAC strips the CRC from received frames 143 * rx_fc_en: Receive Flow Control Enable 144 * tx_crc_en: Transmit CRC Enabled 145 * tx_pad_en: Transmit Padding Enable 146 * tx_cf_en: Transmit Flow Control Enable 147 * tx_en: Transmit Enable 148 * rx_en: Receive Enable 149 */ 150 struct { 151 u32 152 tx_pr_len:4, 153 tx_ifg_nib:4, 154 nib_mode:1, 155 rx_pr_check_en:1, 156 tx_ifg:6, 157 rx_ifg:4, 158 tx_fc_retr:3, 159 rx_length_check_en:1, 160 rx_crc_ignore:1, 161 rx_crc_strip:1, 162 rx_fc_en:1, 163 tx_crc_en:1, 164 tx_pad_en:1, 165 tx_fc_en:1, 166 tx_en:1, 167 rx_en:1; 168 }; 169 170 u32 value; 171 }; 172 }; 173 174 /* Gbps Eth MAC Configuration 1 register */ 175 struct nps_enet_ge_mac_cfg_1 { 176 union { 177 /* octet_3: MAC address octet 3 178 * octet_2: MAC address octet 2 179 * octet_1: MAC address octet 1 180 * octet_0: MAC address octet 0 181 */ 182 struct { 183 u32 184 octet_3:8, 185 octet_2:8, 186 octet_1:8, 187 octet_0:8; 188 }; 189 190 u32 value; 191 }; 192 }; 193 194 /* Gbps Eth MAC Configuration 2 register */ 195 struct nps_enet_ge_mac_cfg_2 { 196 union { 197 /* transmit_flush_en: MAC flush enable 198 * stat_en: RMON statistics interface enable 199 * disc_da: Discard frames with DA different 200 * from MAC address 201 * disc_bc: Discard broadcast frames 202 * disc_mc: Discard multicast frames 203 * octet_5: MAC address octet 5 204 * octet_4: MAC address octet 4 205 */ 206 struct { 207 u32 208 transmit_flush_en:1, 209 __reserved_1:5, 210 stat_en:2, 211 __reserved_2:1, 212 disc_da:1, 213 disc_bc:1, 214 disc_mc:1, 215 __reserved_3:4, 216 octet_5:8, 217 octet_4:8; 218 }; 219 220 u32 value; 221 }; 222 }; 223 224 /* Gbps Eth MAC Configuration 3 register */ 225 struct nps_enet_ge_mac_cfg_3 { 226 union { 227 /* ext_oob_cbfc_sel: Selects one of the 4 profiles for 228 * extended OOB in-flow-control indication 229 * max_len: Maximum receive frame length in bytes 230 * tx_cbfc_en: Enable transmission of class-based 231 * flow control packets 232 * rx_ifg_th: Threshold for IFG status reporting via OOB 233 * cf_timeout: Configurable time to decrement FC counters 234 * cf_drop: Drop control frames 235 * redirect_cbfc_sel: Selects one of CBFC redirect profiles 236 * rx_cbfc_redir_en: Enable Rx class-based flow 237 * control redirect 238 * rx_cbfc_en: Enable Rx class-based flow control 239 * tm_hd_mode: TM header mode 240 */ 241 struct { 242 u32 243 ext_oob_cbfc_sel:2, 244 max_len:14, 245 tx_cbfc_en:1, 246 rx_ifg_th:5, 247 cf_timeout:4, 248 cf_drop:1, 249 redirect_cbfc_sel:2, 250 rx_cbfc_redir_en:1, 251 rx_cbfc_en:1, 252 tm_hd_mode:1; 253 }; 254 255 u32 value; 256 }; 257 }; 258 259 /* GE MAC, PCS reset control register */ 260 struct nps_enet_ge_rst { 261 union { 262 /* gmac_0: GE MAC reset 263 * spcs_0: SGMII PCS reset 264 */ 265 struct { 266 u32 267 __reserved_1:23, 268 gmac_0:1, 269 __reserved_2:7, 270 spcs_0:1; 271 }; 272 273 u32 value; 274 }; 275 }; 276 277 /* Tx phase sync FIFO control register */ 278 struct nps_enet_phase_fifo_ctl { 279 union { 280 /* init: initialize serdes TX phase sync FIFO pointers 281 * rst: reset serdes TX phase sync FIFO 282 */ 283 struct { 284 u32 285 __reserved:30, 286 init:1, 287 rst:1; 288 }; 289 290 u32 value; 291 }; 292 }; 293 294 /** 295 * struct nps_enet_priv - Storage of ENET's private information. 296 * @regs_base: Base address of ENET memory-mapped control registers. 297 * @irq: For RX/TX IRQ number. 298 * @tx_packet_sent: SW indication if frame is being sent. 299 * @tx_skb: socket buffer of sent frame. 300 * @napi: Structure for NAPI. 301 */ 302 struct nps_enet_priv { 303 void __iomem *regs_base; 304 s32 irq; 305 bool tx_packet_sent; 306 struct sk_buff *tx_skb; 307 struct napi_struct napi; 308 struct nps_enet_ge_mac_cfg_2 ge_mac_cfg_2; 309 struct nps_enet_ge_mac_cfg_3 ge_mac_cfg_3; 310 }; 311 312 /** 313 * nps_reg_set - Sets ENET register with provided value. 314 * @priv: Pointer to EZchip ENET private data structure. 315 * @reg: Register offset from base address. 316 * @value: Value to set in register. 317 */ 318 static inline void nps_enet_reg_set(struct nps_enet_priv *priv, 319 s32 reg, s32 value) 320 { 321 iowrite32be(value, priv->regs_base + reg); 322 } 323 324 /** 325 * nps_reg_get - Gets value of specified ENET register. 326 * @priv: Pointer to EZchip ENET private data structure. 327 * @reg: Register offset from base address. 328 * 329 * returns: Value of requested register. 330 */ 331 static inline u32 nps_enet_reg_get(struct nps_enet_priv *priv, s32 reg) 332 { 333 return ioread32be(priv->regs_base + reg); 334 } 335 336 #endif /* _NPS_ENET_H */ 337