1 /* 2 * Copyright(c) 2015 EZchip Technologies. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * The full GNU General Public License is included in this distribution in 14 * the file called "COPYING". 15 */ 16 17 #ifndef _NPS_ENET_H 18 #define _NPS_ENET_H 19 20 /* default values */ 21 #define NPS_ENET_NAPI_POLL_WEIGHT 0x2 22 #define NPS_ENET_MAX_FRAME_LENGTH 0x3FFF 23 #define NPS_ENET_GE_MAC_CFG_0_TX_FC_RETR 0x7 24 #define NPS_ENET_GE_MAC_CFG_0_RX_IFG 0x5 25 #define NPS_ENET_GE_MAC_CFG_0_TX_IFG 0xC 26 #define NPS_ENET_GE_MAC_CFG_0_TX_PR_LEN 0x7 27 #define NPS_ENET_GE_MAC_CFG_2_STAT_EN 0x3 28 #define NPS_ENET_GE_MAC_CFG_3_RX_IFG_TH 0x14 29 #define NPS_ENET_GE_MAC_CFG_3_MAX_LEN 0x3FFC 30 #define NPS_ENET_ENABLE 1 31 #define NPS_ENET_DISABLE 0 32 33 /* register definitions */ 34 #define NPS_ENET_REG_TX_CTL 0x800 35 #define NPS_ENET_REG_TX_BUF 0x808 36 #define NPS_ENET_REG_RX_CTL 0x810 37 #define NPS_ENET_REG_RX_BUF 0x818 38 #define NPS_ENET_REG_BUF_INT_ENABLE 0x8C0 39 #define NPS_ENET_REG_GE_MAC_CFG_0 0x1000 40 #define NPS_ENET_REG_GE_MAC_CFG_1 0x1004 41 #define NPS_ENET_REG_GE_MAC_CFG_2 0x1008 42 #define NPS_ENET_REG_GE_MAC_CFG_3 0x100C 43 #define NPS_ENET_REG_GE_RST 0x1400 44 #define NPS_ENET_REG_PHASE_FIFO_CTL 0x1404 45 46 /* Tx control register masks and shifts */ 47 #define TX_CTL_NT_MASK 0x7FF 48 #define TX_CTL_NT_SHIFT 0 49 #define TX_CTL_ET_MASK 0x4000 50 #define TX_CTL_ET_SHIFT 14 51 #define TX_CTL_CT_MASK 0x8000 52 #define TX_CTL_CT_SHIFT 15 53 54 /* Rx control register masks and shifts */ 55 #define RX_CTL_NR_MASK 0x7FF 56 #define RX_CTL_NR_SHIFT 0 57 #define RX_CTL_CRC_MASK 0x2000 58 #define RX_CTL_CRC_SHIFT 13 59 #define RX_CTL_ER_MASK 0x4000 60 #define RX_CTL_ER_SHIFT 14 61 #define RX_CTL_CR_MASK 0x8000 62 #define RX_CTL_CR_SHIFT 15 63 64 /* Interrupt enable for data buffer events register masks and shifts */ 65 #define RX_RDY_MASK 0x1 66 #define RX_RDY_SHIFT 0 67 #define TX_DONE_MASK 0x2 68 #define TX_DONE_SHIFT 1 69 70 /* Gbps Eth MAC Configuration 0 register masks and shifts */ 71 #define CFG_0_RX_EN_MASK 0x1 72 #define CFG_0_RX_EN_SHIFT 0 73 #define CFG_0_TX_EN_MASK 0x2 74 #define CFG_0_TX_EN_SHIFT 1 75 #define CFG_0_TX_FC_EN_MASK 0x4 76 #define CFG_0_TX_FC_EN_SHIFT 2 77 #define CFG_0_TX_PAD_EN_MASK 0x8 78 #define CFG_0_TX_PAD_EN_SHIFT 3 79 #define CFG_0_TX_CRC_EN_MASK 0x10 80 #define CFG_0_TX_CRC_EN_SHIFT 4 81 #define CFG_0_RX_FC_EN_MASK 0x20 82 #define CFG_0_RX_FC_EN_SHIFT 5 83 #define CFG_0_RX_CRC_STRIP_MASK 0x40 84 #define CFG_0_RX_CRC_STRIP_SHIFT 6 85 #define CFG_0_RX_CRC_IGNORE_MASK 0x80 86 #define CFG_0_RX_CRC_IGNORE_SHIFT 7 87 #define CFG_0_RX_LENGTH_CHECK_EN_MASK 0x100 88 #define CFG_0_RX_LENGTH_CHECK_EN_SHIFT 8 89 #define CFG_0_TX_FC_RETR_MASK 0xE00 90 #define CFG_0_TX_FC_RETR_SHIFT 9 91 #define CFG_0_RX_IFG_MASK 0xF000 92 #define CFG_0_RX_IFG_SHIFT 12 93 #define CFG_0_TX_IFG_MASK 0x3F0000 94 #define CFG_0_TX_IFG_SHIFT 16 95 #define CFG_0_RX_PR_CHECK_EN_MASK 0x400000 96 #define CFG_0_RX_PR_CHECK_EN_SHIFT 22 97 #define CFG_0_NIB_MODE_MASK 0x800000 98 #define CFG_0_NIB_MODE_SHIFT 23 99 #define CFG_0_TX_IFG_NIB_MASK 0xF000000 100 #define CFG_0_TX_IFG_NIB_SHIFT 24 101 #define CFG_0_TX_PR_LEN_MASK 0xF0000000 102 #define CFG_0_TX_PR_LEN_SHIFT 28 103 104 /* Gbps Eth MAC Configuration 1 register masks and shifts */ 105 #define CFG_1_OCTET_0_MASK 0x000000FF 106 #define CFG_1_OCTET_0_SHIFT 0 107 #define CFG_1_OCTET_1_MASK 0x0000FF00 108 #define CFG_1_OCTET_1_SHIFT 8 109 #define CFG_1_OCTET_2_MASK 0x00FF0000 110 #define CFG_1_OCTET_2_SHIFT 16 111 #define CFG_1_OCTET_3_MASK 0xFF000000 112 #define CFG_1_OCTET_3_SHIFT 24 113 114 /* Gbps Eth MAC Configuration 2 register masks and shifts */ 115 #define CFG_2_OCTET_4_MASK 0x000000FF 116 #define CFG_2_OCTET_4_SHIFT 0 117 #define CFG_2_OCTET_5_MASK 0x0000FF00 118 #define CFG_2_OCTET_5_SHIFT 8 119 #define CFG_2_DISK_MC_MASK 0x00100000 120 #define CFG_2_DISK_MC_SHIFT 20 121 #define CFG_2_DISK_BC_MASK 0x00200000 122 #define CFG_2_DISK_BC_SHIFT 21 123 #define CFG_2_DISK_DA_MASK 0x00400000 124 #define CFG_2_DISK_DA_SHIFT 22 125 #define CFG_2_STAT_EN_MASK 0x3000000 126 #define CFG_2_STAT_EN_SHIFT 24 127 #define CFG_2_TRANSMIT_FLUSH_EN_MASK 0x80000000 128 #define CFG_2_TRANSMIT_FLUSH_EN_SHIFT 31 129 130 /* Gbps Eth MAC Configuration 3 register masks and shifts */ 131 #define CFG_3_TM_HD_MODE_MASK 0x1 132 #define CFG_3_TM_HD_MODE_SHIFT 0 133 #define CFG_3_RX_CBFC_EN_MASK 0x2 134 #define CFG_3_RX_CBFC_EN_SHIFT 1 135 #define CFG_3_RX_CBFC_REDIR_EN_MASK 0x4 136 #define CFG_3_RX_CBFC_REDIR_EN_SHIFT 2 137 #define CFG_3_REDIRECT_CBFC_SEL_MASK 0x18 138 #define CFG_3_REDIRECT_CBFC_SEL_SHIFT 3 139 #define CFG_3_CF_DROP_MASK 0x20 140 #define CFG_3_CF_DROP_SHIFT 5 141 #define CFG_3_CF_TIMEOUT_MASK 0x3C0 142 #define CFG_3_CF_TIMEOUT_SHIFT 6 143 #define CFG_3_RX_IFG_TH_MASK 0x7C00 144 #define CFG_3_RX_IFG_TH_SHIFT 10 145 #define CFG_3_TX_CBFC_EN_MASK 0x8000 146 #define CFG_3_TX_CBFC_EN_SHIFT 15 147 #define CFG_3_MAX_LEN_MASK 0x3FFF0000 148 #define CFG_3_MAX_LEN_SHIFT 16 149 #define CFG_3_EXT_OOB_CBFC_SEL_MASK 0xC0000000 150 #define CFG_3_EXT_OOB_CBFC_SEL_SHIFT 30 151 152 /* GE MAC, PCS reset control register masks and shifts */ 153 #define RST_SPCS_MASK 0x1 154 #define RST_SPCS_SHIFT 0 155 #define RST_GMAC_0_MASK 0x100 156 #define RST_GMAC_0_SHIFT 8 157 158 /* Tx phase sync FIFO control register masks and shifts */ 159 #define PHASE_FIFO_CTL_RST_MASK 0x1 160 #define PHASE_FIFO_CTL_RST_SHIFT 0 161 #define PHASE_FIFO_CTL_INIT_MASK 0x2 162 #define PHASE_FIFO_CTL_INIT_SHIFT 1 163 164 /** 165 * struct nps_enet_priv - Storage of ENET's private information. 166 * @regs_base: Base address of ENET memory-mapped control registers. 167 * @irq: For RX/TX IRQ number. 168 * @tx_skb: socket buffer of sent frame. 169 * @napi: Structure for NAPI. 170 */ 171 struct nps_enet_priv { 172 void __iomem *regs_base; 173 s32 irq; 174 struct sk_buff *tx_skb; 175 struct napi_struct napi; 176 u32 ge_mac_cfg_2_value; 177 u32 ge_mac_cfg_3_value; 178 }; 179 180 /** 181 * nps_reg_set - Sets ENET register with provided value. 182 * @priv: Pointer to EZchip ENET private data structure. 183 * @reg: Register offset from base address. 184 * @value: Value to set in register. 185 */ 186 static inline void nps_enet_reg_set(struct nps_enet_priv *priv, 187 s32 reg, s32 value) 188 { 189 iowrite32be(value, priv->regs_base + reg); 190 } 191 192 /** 193 * nps_reg_get - Gets value of specified ENET register. 194 * @priv: Pointer to EZchip ENET private data structure. 195 * @reg: Register offset from base address. 196 * 197 * returns: Value of requested register. 198 */ 199 static inline u32 nps_enet_reg_get(struct nps_enet_priv *priv, s32 reg) 200 { 201 return ioread32be(priv->regs_base + reg); 202 } 203 204 #endif /* _NPS_ENET_H */ 205