1 /*
2  * Copyright(c) 2015 EZchip Technologies.
3  *
4  * This program is free software; you can redistribute it and/or modify it
5  * under the terms and conditions of the GNU General Public License,
6  * version 2, as published by the Free Software Foundation.
7  *
8  * This program is distributed in the hope it will be useful, but WITHOUT
9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
11  * more details.
12  *
13  * The full GNU General Public License is included in this distribution in
14  * the file called "COPYING".
15  */
16 
17 #include <linux/module.h>
18 #include <linux/etherdevice.h>
19 #include <linux/of_address.h>
20 #include <linux/of_irq.h>
21 #include <linux/of_net.h>
22 #include <linux/of_platform.h>
23 #include "nps_enet.h"
24 
25 #define DRV_NAME			"nps_mgt_enet"
26 
27 static void nps_enet_clean_rx_fifo(struct net_device *ndev, u32 frame_len)
28 {
29 	struct nps_enet_priv *priv = netdev_priv(ndev);
30 	u32 i, len = DIV_ROUND_UP(frame_len, sizeof(u32));
31 
32 	/* Empty Rx FIFO buffer by reading all words */
33 	for (i = 0; i < len; i++)
34 		nps_enet_reg_get(priv, NPS_ENET_REG_RX_BUF);
35 }
36 
37 static void nps_enet_read_rx_fifo(struct net_device *ndev,
38 				  unsigned char *dst, u32 length)
39 {
40 	struct nps_enet_priv *priv = netdev_priv(ndev);
41 	s32 i, last = length & (sizeof(u32) - 1);
42 	u32 *reg = (u32 *)dst, len = length / sizeof(u32);
43 	bool dst_is_aligned = IS_ALIGNED((unsigned long)dst, sizeof(u32));
44 
45 	/* In case dst is not aligned we need an intermediate buffer */
46 	if (dst_is_aligned) {
47 		ioread32_rep(priv->regs_base + NPS_ENET_REG_RX_BUF, reg, len);
48 		reg += len;
49 	}
50 	else { /* !dst_is_aligned */
51 		for (i = 0; i < len; i++, reg++) {
52 			u32 buf = nps_enet_reg_get(priv, NPS_ENET_REG_RX_BUF);
53 			put_unaligned_be32(buf, reg);
54 		}
55 	}
56 	/* copy last bytes (if any) */
57 	if (last) {
58 		u32 buf;
59 		ioread32_rep(priv->regs_base + NPS_ENET_REG_RX_BUF, &buf, 1);
60 		memcpy((u8 *)reg, &buf, last);
61 	}
62 }
63 
64 static u32 nps_enet_rx_handler(struct net_device *ndev)
65 {
66 	u32 frame_len, err = 0;
67 	u32 work_done = 0;
68 	struct nps_enet_priv *priv = netdev_priv(ndev);
69 	struct sk_buff *skb;
70 	u32 rx_ctrl_value = nps_enet_reg_get(priv, NPS_ENET_REG_RX_CTL);
71 	u32 rx_ctrl_cr = (rx_ctrl_value & RX_CTL_CR_MASK) >> RX_CTL_CR_SHIFT;
72 	u32 rx_ctrl_er = (rx_ctrl_value & RX_CTL_ER_MASK) >> RX_CTL_ER_SHIFT;
73 	u32 rx_ctrl_crc = (rx_ctrl_value & RX_CTL_CRC_MASK) >> RX_CTL_CRC_SHIFT;
74 
75 	frame_len = (rx_ctrl_value & RX_CTL_NR_MASK) >> RX_CTL_NR_SHIFT;
76 
77 	/* Check if we got RX */
78 	if (!rx_ctrl_cr)
79 		return work_done;
80 
81 	/* If we got here there is a work for us */
82 	work_done++;
83 
84 	/* Check Rx error */
85 	if (rx_ctrl_er) {
86 		ndev->stats.rx_errors++;
87 		err = 1;
88 	}
89 
90 	/* Check Rx CRC error */
91 	if (rx_ctrl_crc) {
92 		ndev->stats.rx_crc_errors++;
93 		ndev->stats.rx_dropped++;
94 		err = 1;
95 	}
96 
97 	/* Check Frame length Min 64b */
98 	if (unlikely(frame_len < ETH_ZLEN)) {
99 		ndev->stats.rx_length_errors++;
100 		ndev->stats.rx_dropped++;
101 		err = 1;
102 	}
103 
104 	if (err)
105 		goto rx_irq_clean;
106 
107 	/* Skb allocation */
108 	skb = netdev_alloc_skb_ip_align(ndev, frame_len);
109 	if (unlikely(!skb)) {
110 		ndev->stats.rx_errors++;
111 		ndev->stats.rx_dropped++;
112 		goto rx_irq_clean;
113 	}
114 
115 	/* Copy frame from Rx fifo into the skb */
116 	nps_enet_read_rx_fifo(ndev, skb->data, frame_len);
117 
118 	skb_put(skb, frame_len);
119 	skb->protocol = eth_type_trans(skb, ndev);
120 	skb->ip_summed = CHECKSUM_UNNECESSARY;
121 
122 	ndev->stats.rx_packets++;
123 	ndev->stats.rx_bytes += frame_len;
124 	netif_receive_skb(skb);
125 
126 	goto rx_irq_frame_done;
127 
128 rx_irq_clean:
129 	/* Clean Rx fifo */
130 	nps_enet_clean_rx_fifo(ndev, frame_len);
131 
132 rx_irq_frame_done:
133 	/* Ack Rx ctrl register */
134 	nps_enet_reg_set(priv, NPS_ENET_REG_RX_CTL, 0);
135 
136 	return work_done;
137 }
138 
139 static void nps_enet_tx_handler(struct net_device *ndev)
140 {
141 	struct nps_enet_priv *priv = netdev_priv(ndev);
142 	u32 tx_ctrl_value = nps_enet_reg_get(priv, NPS_ENET_REG_TX_CTL);
143 	u32 tx_ctrl_ct = (tx_ctrl_value & TX_CTL_CT_MASK) >> TX_CTL_CT_SHIFT;
144 	u32 tx_ctrl_et = (tx_ctrl_value & TX_CTL_ET_MASK) >> TX_CTL_ET_SHIFT;
145 	u32 tx_ctrl_nt = (tx_ctrl_value & TX_CTL_NT_MASK) >> TX_CTL_NT_SHIFT;
146 
147 	/* Check if we got TX */
148 	if (!priv->tx_skb || tx_ctrl_ct)
149 		return;
150 
151 	/* Ack Tx ctrl register */
152 	nps_enet_reg_set(priv, NPS_ENET_REG_TX_CTL, 0);
153 
154 	/* Check Tx transmit error */
155 	if (unlikely(tx_ctrl_et)) {
156 		ndev->stats.tx_errors++;
157 	} else {
158 		ndev->stats.tx_packets++;
159 		ndev->stats.tx_bytes += tx_ctrl_nt;
160 	}
161 
162 	dev_kfree_skb(priv->tx_skb);
163 	priv->tx_skb = NULL;
164 
165 	if (netif_queue_stopped(ndev))
166 		netif_wake_queue(ndev);
167 }
168 
169 /**
170  * nps_enet_poll - NAPI poll handler.
171  * @napi:       Pointer to napi_struct structure.
172  * @budget:     How many frames to process on one call.
173  *
174  * returns:     Number of processed frames
175  */
176 static int nps_enet_poll(struct napi_struct *napi, int budget)
177 {
178 	struct net_device *ndev = napi->dev;
179 	struct nps_enet_priv *priv = netdev_priv(ndev);
180 	u32 work_done;
181 
182 	nps_enet_tx_handler(ndev);
183 	work_done = nps_enet_rx_handler(ndev);
184 	if (work_done < budget) {
185 		u32 buf_int_enable_value = 0;
186 		u32 tx_ctrl_value = nps_enet_reg_get(priv, NPS_ENET_REG_TX_CTL);
187 		u32 tx_ctrl_ct =
188 			(tx_ctrl_value & TX_CTL_CT_MASK) >> TX_CTL_CT_SHIFT;
189 
190 		napi_complete(napi);
191 
192 		/* set tx_done and rx_rdy bits */
193 		buf_int_enable_value |= NPS_ENET_ENABLE << RX_RDY_SHIFT;
194 		buf_int_enable_value |= NPS_ENET_ENABLE << TX_DONE_SHIFT;
195 
196 		nps_enet_reg_set(priv, NPS_ENET_REG_BUF_INT_ENABLE,
197 				 buf_int_enable_value);
198 
199 		/* in case we will get a tx interrupt while interrupts
200 		 * are masked, we will lose it since the tx is edge interrupt.
201 		 * specifically, while executing the code section above,
202 		 * between nps_enet_tx_handler and the interrupts enable, all
203 		 * tx requests will be stuck until we will get an rx interrupt.
204 		 * the two code lines below will solve this situation by
205 		 * re-adding ourselves to the poll list.
206 		 */
207 
208 		if (priv->tx_skb && !tx_ctrl_ct) {
209 			nps_enet_reg_set(priv, NPS_ENET_REG_BUF_INT_ENABLE, 0);
210 			napi_reschedule(napi);
211 		}
212 	}
213 
214 	return work_done;
215 }
216 
217 /**
218  * nps_enet_irq_handler - Global interrupt handler for ENET.
219  * @irq:                irq number.
220  * @dev_instance:       device instance.
221  *
222  * returns: IRQ_HANDLED for all cases.
223  *
224  * EZchip ENET has 2 interrupt causes, and depending on bits raised in
225  * CTRL registers we may tell what is a reason for interrupt to fire up.
226  * We got one for RX and the other for TX (completion).
227  */
228 static irqreturn_t nps_enet_irq_handler(s32 irq, void *dev_instance)
229 {
230 	struct net_device *ndev = dev_instance;
231 	struct nps_enet_priv *priv = netdev_priv(ndev);
232 	u32 rx_ctrl_value = nps_enet_reg_get(priv, NPS_ENET_REG_RX_CTL);
233 	u32 tx_ctrl_value = nps_enet_reg_get(priv, NPS_ENET_REG_TX_CTL);
234 	u32 tx_ctrl_ct = (tx_ctrl_value & TX_CTL_CT_MASK) >> TX_CTL_CT_SHIFT;
235 	u32 rx_ctrl_cr = (rx_ctrl_value & RX_CTL_CR_MASK) >> RX_CTL_CR_SHIFT;
236 
237 	if ((!tx_ctrl_ct && priv->tx_skb) || rx_ctrl_cr)
238 		if (likely(napi_schedule_prep(&priv->napi))) {
239 			nps_enet_reg_set(priv, NPS_ENET_REG_BUF_INT_ENABLE, 0);
240 			__napi_schedule(&priv->napi);
241 		}
242 
243 	return IRQ_HANDLED;
244 }
245 
246 static void nps_enet_set_hw_mac_address(struct net_device *ndev)
247 {
248 	struct nps_enet_priv *priv = netdev_priv(ndev);
249 	u32 ge_mac_cfg_1_value = 0;
250 	u32 *ge_mac_cfg_2_value = &priv->ge_mac_cfg_2_value;
251 
252 	/* set MAC address in HW */
253 	ge_mac_cfg_1_value |= ndev->dev_addr[0] << CFG_1_OCTET_0_SHIFT;
254 	ge_mac_cfg_1_value |= ndev->dev_addr[1] << CFG_1_OCTET_1_SHIFT;
255 	ge_mac_cfg_1_value |= ndev->dev_addr[2] << CFG_1_OCTET_2_SHIFT;
256 	ge_mac_cfg_1_value |= ndev->dev_addr[3] << CFG_1_OCTET_3_SHIFT;
257 	*ge_mac_cfg_2_value = (*ge_mac_cfg_2_value & ~CFG_2_OCTET_4_MASK)
258 		 | ndev->dev_addr[4] << CFG_2_OCTET_4_SHIFT;
259 	*ge_mac_cfg_2_value = (*ge_mac_cfg_2_value & ~CFG_2_OCTET_5_MASK)
260 		 | ndev->dev_addr[5] << CFG_2_OCTET_5_SHIFT;
261 
262 	nps_enet_reg_set(priv, NPS_ENET_REG_GE_MAC_CFG_1,
263 			 ge_mac_cfg_1_value);
264 
265 	nps_enet_reg_set(priv, NPS_ENET_REG_GE_MAC_CFG_2,
266 			 *ge_mac_cfg_2_value);
267 }
268 
269 /**
270  * nps_enet_hw_reset - Reset the network device.
271  * @ndev:       Pointer to the network device.
272  *
273  * This function reset the PCS and TX fifo.
274  * The programming model is to set the relevant reset bits
275  * wait for some time for this to propagate and then unset
276  * the reset bits. This way we ensure that reset procedure
277  * is done successfully by device.
278  */
279 static void nps_enet_hw_reset(struct net_device *ndev)
280 {
281 	struct nps_enet_priv *priv = netdev_priv(ndev);
282 	u32 ge_rst_value = 0, phase_fifo_ctl_value = 0;
283 
284 	/* Pcs reset sequence*/
285 	ge_rst_value |= NPS_ENET_ENABLE << RST_GMAC_0_SHIFT;
286 	nps_enet_reg_set(priv, NPS_ENET_REG_GE_RST, ge_rst_value);
287 	usleep_range(10, 20);
288 	ge_rst_value = 0;
289 	nps_enet_reg_set(priv, NPS_ENET_REG_GE_RST, ge_rst_value);
290 
291 	/* Tx fifo reset sequence */
292 	phase_fifo_ctl_value |= NPS_ENET_ENABLE << PHASE_FIFO_CTL_RST_SHIFT;
293 	phase_fifo_ctl_value |= NPS_ENET_ENABLE << PHASE_FIFO_CTL_INIT_SHIFT;
294 	nps_enet_reg_set(priv, NPS_ENET_REG_PHASE_FIFO_CTL,
295 			 phase_fifo_ctl_value);
296 	usleep_range(10, 20);
297 	phase_fifo_ctl_value = 0;
298 	nps_enet_reg_set(priv, NPS_ENET_REG_PHASE_FIFO_CTL,
299 			 phase_fifo_ctl_value);
300 }
301 
302 static void nps_enet_hw_enable_control(struct net_device *ndev)
303 {
304 	struct nps_enet_priv *priv = netdev_priv(ndev);
305 	u32 ge_mac_cfg_0_value = 0, buf_int_enable_value = 0;
306 	u32 *ge_mac_cfg_2_value = &priv->ge_mac_cfg_2_value;
307 	u32 *ge_mac_cfg_3_value = &priv->ge_mac_cfg_3_value;
308 	s32 max_frame_length;
309 
310 	/* Enable Rx and Tx statistics */
311 	*ge_mac_cfg_2_value = (*ge_mac_cfg_2_value & ~CFG_2_STAT_EN_MASK)
312 		 | NPS_ENET_GE_MAC_CFG_2_STAT_EN << CFG_2_STAT_EN_SHIFT;
313 
314 	/* Discard packets with different MAC address */
315 	*ge_mac_cfg_2_value = (*ge_mac_cfg_2_value & ~CFG_2_DISK_DA_MASK)
316 		 | NPS_ENET_ENABLE << CFG_2_DISK_DA_SHIFT;
317 
318 	/* Discard multicast packets */
319 	*ge_mac_cfg_2_value = (*ge_mac_cfg_2_value & ~CFG_2_DISK_MC_MASK)
320 		 | NPS_ENET_ENABLE << CFG_2_DISK_MC_SHIFT;
321 
322 	nps_enet_reg_set(priv, NPS_ENET_REG_GE_MAC_CFG_2,
323 			 *ge_mac_cfg_2_value);
324 
325 	/* Discard Packets bigger than max frame length */
326 	max_frame_length = ETH_HLEN + ndev->mtu + ETH_FCS_LEN;
327 	if (max_frame_length <= NPS_ENET_MAX_FRAME_LENGTH) {
328 		*ge_mac_cfg_3_value =
329 			 (*ge_mac_cfg_3_value & ~CFG_3_MAX_LEN_MASK)
330 			 | max_frame_length << CFG_3_MAX_LEN_SHIFT;
331 	}
332 
333 	/* Enable interrupts */
334 	buf_int_enable_value |= NPS_ENET_ENABLE << RX_RDY_SHIFT;
335 	buf_int_enable_value |= NPS_ENET_ENABLE << TX_DONE_SHIFT;
336 	nps_enet_reg_set(priv, NPS_ENET_REG_BUF_INT_ENABLE,
337 			 buf_int_enable_value);
338 
339 	/* Write device MAC address to HW */
340 	nps_enet_set_hw_mac_address(ndev);
341 
342 	/* Rx and Tx HW features */
343 	ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_TX_PAD_EN_SHIFT;
344 	ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_TX_CRC_EN_SHIFT;
345 	ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_RX_CRC_STRIP_SHIFT;
346 
347 	/* IFG configuration */
348 	ge_mac_cfg_0_value |=
349 		 NPS_ENET_GE_MAC_CFG_0_RX_IFG << CFG_0_RX_IFG_SHIFT;
350 	ge_mac_cfg_0_value |=
351 		 NPS_ENET_GE_MAC_CFG_0_TX_IFG << CFG_0_TX_IFG_SHIFT;
352 
353 	/* preamble configuration */
354 	ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_RX_PR_CHECK_EN_SHIFT;
355 	ge_mac_cfg_0_value |=
356 		 NPS_ENET_GE_MAC_CFG_0_TX_PR_LEN << CFG_0_TX_PR_LEN_SHIFT;
357 
358 	/* enable flow control frames */
359 	ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_TX_FC_EN_SHIFT;
360 	ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_RX_FC_EN_SHIFT;
361 	ge_mac_cfg_0_value |=
362 		 NPS_ENET_GE_MAC_CFG_0_TX_FC_RETR << CFG_0_TX_FC_RETR_SHIFT;
363 	*ge_mac_cfg_3_value = (*ge_mac_cfg_3_value & ~CFG_3_CF_DROP_MASK)
364 		 | NPS_ENET_ENABLE << CFG_3_CF_DROP_SHIFT;
365 
366 	/* Enable Rx and Tx */
367 	ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_RX_EN_SHIFT;
368 	ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_TX_EN_SHIFT;
369 
370 	nps_enet_reg_set(priv, NPS_ENET_REG_GE_MAC_CFG_3,
371 			 *ge_mac_cfg_3_value);
372 	nps_enet_reg_set(priv, NPS_ENET_REG_GE_MAC_CFG_0,
373 			 ge_mac_cfg_0_value);
374 }
375 
376 static void nps_enet_hw_disable_control(struct net_device *ndev)
377 {
378 	struct nps_enet_priv *priv = netdev_priv(ndev);
379 
380 	/* Disable interrupts */
381 	nps_enet_reg_set(priv, NPS_ENET_REG_BUF_INT_ENABLE, 0);
382 
383 	/* Disable Rx and Tx */
384 	nps_enet_reg_set(priv, NPS_ENET_REG_GE_MAC_CFG_0, 0);
385 }
386 
387 static void nps_enet_send_frame(struct net_device *ndev,
388 				struct sk_buff *skb)
389 {
390 	struct nps_enet_priv *priv = netdev_priv(ndev);
391 	u32 tx_ctrl_value = 0;
392 	short length = skb->len;
393 	u32 i, len = DIV_ROUND_UP(length, sizeof(u32));
394 	u32 *src = (void *)skb->data;
395 	bool src_is_aligned = IS_ALIGNED((unsigned long)src, sizeof(u32));
396 
397 	/* In case src is not aligned we need an intermediate buffer */
398 	if (src_is_aligned)
399 		iowrite32_rep(priv->regs_base + NPS_ENET_REG_TX_BUF, src, len);
400 	else /* !src_is_aligned */
401 		for (i = 0; i < len; i++, src++)
402 			nps_enet_reg_set(priv, NPS_ENET_REG_TX_BUF,
403 					 get_unaligned_be32(src));
404 
405 	/* Write the length of the Frame */
406 	tx_ctrl_value |= length << TX_CTL_NT_SHIFT;
407 
408 	tx_ctrl_value |= NPS_ENET_ENABLE << TX_CTL_CT_SHIFT;
409 	/* Send Frame */
410 	nps_enet_reg_set(priv, NPS_ENET_REG_TX_CTL, tx_ctrl_value);
411 }
412 
413 /**
414  * nps_enet_set_mac_address - Set the MAC address for this device.
415  * @ndev:       Pointer to net_device structure.
416  * @p:          6 byte Address to be written as MAC address.
417  *
418  * This function copies the HW address from the sockaddr structure to the
419  * net_device structure and updates the address in HW.
420  *
421  * returns:     -EBUSY if the net device is busy or 0 if the address is set
422  *              successfully.
423  */
424 static s32 nps_enet_set_mac_address(struct net_device *ndev, void *p)
425 {
426 	struct sockaddr *addr = p;
427 	s32 res;
428 
429 	if (netif_running(ndev))
430 		return -EBUSY;
431 
432 	res = eth_mac_addr(ndev, p);
433 	if (!res) {
434 		ether_addr_copy(ndev->dev_addr, addr->sa_data);
435 		nps_enet_set_hw_mac_address(ndev);
436 	}
437 
438 	return res;
439 }
440 
441 /**
442  * nps_enet_set_rx_mode - Change the receive filtering mode.
443  * @ndev:       Pointer to the network device.
444  *
445  * This function enables/disables promiscuous mode
446  */
447 static void nps_enet_set_rx_mode(struct net_device *ndev)
448 {
449 	struct nps_enet_priv *priv = netdev_priv(ndev);
450 	u32 ge_mac_cfg_2_value = priv->ge_mac_cfg_2_value;
451 
452 	if (ndev->flags & IFF_PROMISC) {
453 		ge_mac_cfg_2_value = (ge_mac_cfg_2_value & ~CFG_2_DISK_DA_MASK)
454 			 | NPS_ENET_DISABLE << CFG_2_DISK_DA_SHIFT;
455 		ge_mac_cfg_2_value = (ge_mac_cfg_2_value & ~CFG_2_DISK_MC_MASK)
456 			 | NPS_ENET_DISABLE << CFG_2_DISK_MC_SHIFT;
457 
458 	} else {
459 		ge_mac_cfg_2_value = (ge_mac_cfg_2_value & ~CFG_2_DISK_DA_MASK)
460 			 | NPS_ENET_ENABLE << CFG_2_DISK_DA_SHIFT;
461 		ge_mac_cfg_2_value = (ge_mac_cfg_2_value & ~CFG_2_DISK_MC_MASK)
462 			 | NPS_ENET_ENABLE << CFG_2_DISK_MC_SHIFT;
463 
464 	}
465 
466 	nps_enet_reg_set(priv, NPS_ENET_REG_GE_MAC_CFG_2, ge_mac_cfg_2_value);
467 }
468 
469 /**
470  * nps_enet_open - Open the network device.
471  * @ndev:       Pointer to the network device.
472  *
473  * returns: 0, on success or non-zero error value on failure.
474  *
475  * This function sets the MAC address, requests and enables an IRQ
476  * for the ENET device and starts the Tx queue.
477  */
478 static s32 nps_enet_open(struct net_device *ndev)
479 {
480 	struct nps_enet_priv *priv = netdev_priv(ndev);
481 	s32 err;
482 
483 	/* Reset private variables */
484 	priv->tx_skb = NULL;
485 	priv->ge_mac_cfg_2_value = 0;
486 	priv->ge_mac_cfg_3_value = 0;
487 
488 	/* ge_mac_cfg_3 default values */
489 	priv->ge_mac_cfg_3_value |=
490 		 NPS_ENET_GE_MAC_CFG_3_RX_IFG_TH << CFG_3_RX_IFG_TH_SHIFT;
491 
492 	priv->ge_mac_cfg_3_value |=
493 		 NPS_ENET_GE_MAC_CFG_3_MAX_LEN << CFG_3_MAX_LEN_SHIFT;
494 
495 	/* Disable HW device */
496 	nps_enet_hw_disable_control(ndev);
497 
498 	/* irq Rx allocation */
499 	err = request_irq(priv->irq, nps_enet_irq_handler,
500 			  0, "enet-rx-tx", ndev);
501 	if (err)
502 		return err;
503 
504 	napi_enable(&priv->napi);
505 
506 	/* Enable HW device */
507 	nps_enet_hw_reset(ndev);
508 	nps_enet_hw_enable_control(ndev);
509 
510 	netif_start_queue(ndev);
511 
512 	return 0;
513 }
514 
515 /**
516  * nps_enet_stop - Close the network device.
517  * @ndev:       Pointer to the network device.
518  *
519  * This function stops the Tx queue, disables interrupts for the ENET device.
520  */
521 static s32 nps_enet_stop(struct net_device *ndev)
522 {
523 	struct nps_enet_priv *priv = netdev_priv(ndev);
524 
525 	napi_disable(&priv->napi);
526 	netif_stop_queue(ndev);
527 	nps_enet_hw_disable_control(ndev);
528 	free_irq(priv->irq, ndev);
529 
530 	return 0;
531 }
532 
533 /**
534  * nps_enet_start_xmit - Starts the data transmission.
535  * @skb:        sk_buff pointer that contains data to be Transmitted.
536  * @ndev:       Pointer to net_device structure.
537  *
538  * returns: NETDEV_TX_OK, on success
539  *              NETDEV_TX_BUSY, if any of the descriptors are not free.
540  *
541  * This function is invoked from upper layers to initiate transmission.
542  */
543 static netdev_tx_t nps_enet_start_xmit(struct sk_buff *skb,
544 				       struct net_device *ndev)
545 {
546 	struct nps_enet_priv *priv = netdev_priv(ndev);
547 
548 	/* This driver handles one frame at a time  */
549 	netif_stop_queue(ndev);
550 
551 	priv->tx_skb = skb;
552 
553 	/* make sure tx_skb is actually written to the memory
554 	 * before the HW is informed and the IRQ is fired.
555 	 */
556 	wmb();
557 
558 	nps_enet_send_frame(ndev, skb);
559 
560 	return NETDEV_TX_OK;
561 }
562 
563 #ifdef CONFIG_NET_POLL_CONTROLLER
564 static void nps_enet_poll_controller(struct net_device *ndev)
565 {
566 	disable_irq(ndev->irq);
567 	nps_enet_irq_handler(ndev->irq, ndev);
568 	enable_irq(ndev->irq);
569 }
570 #endif
571 
572 static const struct net_device_ops nps_netdev_ops = {
573 	.ndo_open		= nps_enet_open,
574 	.ndo_stop		= nps_enet_stop,
575 	.ndo_start_xmit		= nps_enet_start_xmit,
576 	.ndo_set_mac_address	= nps_enet_set_mac_address,
577 	.ndo_set_rx_mode        = nps_enet_set_rx_mode,
578 #ifdef CONFIG_NET_POLL_CONTROLLER
579 	.ndo_poll_controller	= nps_enet_poll_controller,
580 #endif
581 };
582 
583 static s32 nps_enet_probe(struct platform_device *pdev)
584 {
585 	struct device *dev = &pdev->dev;
586 	struct net_device *ndev;
587 	struct nps_enet_priv *priv;
588 	s32 err = 0;
589 	const char *mac_addr;
590 	struct resource *res_regs;
591 
592 	if (!dev->of_node)
593 		return -ENODEV;
594 
595 	ndev = alloc_etherdev(sizeof(struct nps_enet_priv));
596 	if (!ndev)
597 		return -ENOMEM;
598 
599 	platform_set_drvdata(pdev, ndev);
600 	SET_NETDEV_DEV(ndev, dev);
601 	priv = netdev_priv(ndev);
602 
603 	/* The EZ NET specific entries in the device structure. */
604 	ndev->netdev_ops = &nps_netdev_ops;
605 	ndev->watchdog_timeo = (400 * HZ / 1000);
606 	/* FIXME :: no multicast support yet */
607 	ndev->flags &= ~IFF_MULTICAST;
608 
609 	res_regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
610 	priv->regs_base = devm_ioremap_resource(dev, res_regs);
611 	if (IS_ERR(priv->regs_base)) {
612 		err = PTR_ERR(priv->regs_base);
613 		goto out_netdev;
614 	}
615 	dev_dbg(dev, "Registers base address is 0x%p\n", priv->regs_base);
616 
617 	/* set kernel MAC address to dev */
618 	mac_addr = of_get_mac_address(dev->of_node);
619 	if (mac_addr)
620 		ether_addr_copy(ndev->dev_addr, mac_addr);
621 	else
622 		eth_hw_addr_random(ndev);
623 
624 	/* Get IRQ number */
625 	priv->irq = platform_get_irq(pdev, 0);
626 	if (!priv->irq) {
627 		dev_err(dev, "failed to retrieve <irq Rx-Tx> value from device tree\n");
628 		err = -ENODEV;
629 		goto out_netdev;
630 	}
631 
632 	netif_napi_add(ndev, &priv->napi, nps_enet_poll,
633 		       NPS_ENET_NAPI_POLL_WEIGHT);
634 
635 	/* Register the driver. Should be the last thing in probe */
636 	err = register_netdev(ndev);
637 	if (err) {
638 		dev_err(dev, "Failed to register ndev for %s, err = 0x%08x\n",
639 			ndev->name, (s32)err);
640 		goto out_netif_api;
641 	}
642 
643 	dev_info(dev, "(rx/tx=%d)\n", priv->irq);
644 	return 0;
645 
646 out_netif_api:
647 	netif_napi_del(&priv->napi);
648 out_netdev:
649 	if (err)
650 		free_netdev(ndev);
651 
652 	return err;
653 }
654 
655 static s32 nps_enet_remove(struct platform_device *pdev)
656 {
657 	struct net_device *ndev = platform_get_drvdata(pdev);
658 	struct nps_enet_priv *priv = netdev_priv(ndev);
659 
660 	unregister_netdev(ndev);
661 	free_netdev(ndev);
662 	netif_napi_del(&priv->napi);
663 
664 	return 0;
665 }
666 
667 static const struct of_device_id nps_enet_dt_ids[] = {
668 	{ .compatible = "ezchip,nps-mgt-enet" },
669 	{ /* Sentinel */ }
670 };
671 
672 static struct platform_driver nps_enet_driver = {
673 	.probe = nps_enet_probe,
674 	.remove = nps_enet_remove,
675 	.driver = {
676 		.name = DRV_NAME,
677 		.of_match_table  = nps_enet_dt_ids,
678 	},
679 };
680 
681 module_platform_driver(nps_enet_driver);
682 
683 MODULE_AUTHOR("EZchip Semiconductor");
684 MODULE_LICENSE("GPL v2");
685