1 /* 2 * linux/drivers/net/ethernet/ethoc.c 3 * 4 * Copyright (C) 2007-2008 Avionic Design Development GmbH 5 * Copyright (C) 2008-2009 Avionic Design GmbH 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * Written by Thierry Reding <thierry.reding@avionic-design.de> 12 */ 13 14 #include <linux/dma-mapping.h> 15 #include <linux/etherdevice.h> 16 #include <linux/clk.h> 17 #include <linux/crc32.h> 18 #include <linux/interrupt.h> 19 #include <linux/io.h> 20 #include <linux/mii.h> 21 #include <linux/phy.h> 22 #include <linux/platform_device.h> 23 #include <linux/sched.h> 24 #include <linux/slab.h> 25 #include <linux/of.h> 26 #include <linux/module.h> 27 #include <net/ethoc.h> 28 29 static int buffer_size = 0x8000; /* 32 KBytes */ 30 module_param(buffer_size, int, 0); 31 MODULE_PARM_DESC(buffer_size, "DMA buffer allocation size"); 32 33 /* register offsets */ 34 #define MODER 0x00 35 #define INT_SOURCE 0x04 36 #define INT_MASK 0x08 37 #define IPGT 0x0c 38 #define IPGR1 0x10 39 #define IPGR2 0x14 40 #define PACKETLEN 0x18 41 #define COLLCONF 0x1c 42 #define TX_BD_NUM 0x20 43 #define CTRLMODER 0x24 44 #define MIIMODER 0x28 45 #define MIICOMMAND 0x2c 46 #define MIIADDRESS 0x30 47 #define MIITX_DATA 0x34 48 #define MIIRX_DATA 0x38 49 #define MIISTATUS 0x3c 50 #define MAC_ADDR0 0x40 51 #define MAC_ADDR1 0x44 52 #define ETH_HASH0 0x48 53 #define ETH_HASH1 0x4c 54 #define ETH_TXCTRL 0x50 55 #define ETH_END 0x54 56 57 /* mode register */ 58 #define MODER_RXEN (1 << 0) /* receive enable */ 59 #define MODER_TXEN (1 << 1) /* transmit enable */ 60 #define MODER_NOPRE (1 << 2) /* no preamble */ 61 #define MODER_BRO (1 << 3) /* broadcast address */ 62 #define MODER_IAM (1 << 4) /* individual address mode */ 63 #define MODER_PRO (1 << 5) /* promiscuous mode */ 64 #define MODER_IFG (1 << 6) /* interframe gap for incoming frames */ 65 #define MODER_LOOP (1 << 7) /* loopback */ 66 #define MODER_NBO (1 << 8) /* no back-off */ 67 #define MODER_EDE (1 << 9) /* excess defer enable */ 68 #define MODER_FULLD (1 << 10) /* full duplex */ 69 #define MODER_RESET (1 << 11) /* FIXME: reset (undocumented) */ 70 #define MODER_DCRC (1 << 12) /* delayed CRC enable */ 71 #define MODER_CRC (1 << 13) /* CRC enable */ 72 #define MODER_HUGE (1 << 14) /* huge packets enable */ 73 #define MODER_PAD (1 << 15) /* padding enabled */ 74 #define MODER_RSM (1 << 16) /* receive small packets */ 75 76 /* interrupt source and mask registers */ 77 #define INT_MASK_TXF (1 << 0) /* transmit frame */ 78 #define INT_MASK_TXE (1 << 1) /* transmit error */ 79 #define INT_MASK_RXF (1 << 2) /* receive frame */ 80 #define INT_MASK_RXE (1 << 3) /* receive error */ 81 #define INT_MASK_BUSY (1 << 4) 82 #define INT_MASK_TXC (1 << 5) /* transmit control frame */ 83 #define INT_MASK_RXC (1 << 6) /* receive control frame */ 84 85 #define INT_MASK_TX (INT_MASK_TXF | INT_MASK_TXE) 86 #define INT_MASK_RX (INT_MASK_RXF | INT_MASK_RXE) 87 88 #define INT_MASK_ALL ( \ 89 INT_MASK_TXF | INT_MASK_TXE | \ 90 INT_MASK_RXF | INT_MASK_RXE | \ 91 INT_MASK_TXC | INT_MASK_RXC | \ 92 INT_MASK_BUSY \ 93 ) 94 95 /* packet length register */ 96 #define PACKETLEN_MIN(min) (((min) & 0xffff) << 16) 97 #define PACKETLEN_MAX(max) (((max) & 0xffff) << 0) 98 #define PACKETLEN_MIN_MAX(min, max) (PACKETLEN_MIN(min) | \ 99 PACKETLEN_MAX(max)) 100 101 /* transmit buffer number register */ 102 #define TX_BD_NUM_VAL(x) (((x) <= 0x80) ? (x) : 0x80) 103 104 /* control module mode register */ 105 #define CTRLMODER_PASSALL (1 << 0) /* pass all receive frames */ 106 #define CTRLMODER_RXFLOW (1 << 1) /* receive control flow */ 107 #define CTRLMODER_TXFLOW (1 << 2) /* transmit control flow */ 108 109 /* MII mode register */ 110 #define MIIMODER_CLKDIV(x) ((x) & 0xfe) /* needs to be an even number */ 111 #define MIIMODER_NOPRE (1 << 8) /* no preamble */ 112 113 /* MII command register */ 114 #define MIICOMMAND_SCAN (1 << 0) /* scan status */ 115 #define MIICOMMAND_READ (1 << 1) /* read status */ 116 #define MIICOMMAND_WRITE (1 << 2) /* write control data */ 117 118 /* MII address register */ 119 #define MIIADDRESS_FIAD(x) (((x) & 0x1f) << 0) 120 #define MIIADDRESS_RGAD(x) (((x) & 0x1f) << 8) 121 #define MIIADDRESS_ADDR(phy, reg) (MIIADDRESS_FIAD(phy) | \ 122 MIIADDRESS_RGAD(reg)) 123 124 /* MII transmit data register */ 125 #define MIITX_DATA_VAL(x) ((x) & 0xffff) 126 127 /* MII receive data register */ 128 #define MIIRX_DATA_VAL(x) ((x) & 0xffff) 129 130 /* MII status register */ 131 #define MIISTATUS_LINKFAIL (1 << 0) 132 #define MIISTATUS_BUSY (1 << 1) 133 #define MIISTATUS_INVALID (1 << 2) 134 135 /* TX buffer descriptor */ 136 #define TX_BD_CS (1 << 0) /* carrier sense lost */ 137 #define TX_BD_DF (1 << 1) /* defer indication */ 138 #define TX_BD_LC (1 << 2) /* late collision */ 139 #define TX_BD_RL (1 << 3) /* retransmission limit */ 140 #define TX_BD_RETRY_MASK (0x00f0) 141 #define TX_BD_RETRY(x) (((x) & 0x00f0) >> 4) 142 #define TX_BD_UR (1 << 8) /* transmitter underrun */ 143 #define TX_BD_CRC (1 << 11) /* TX CRC enable */ 144 #define TX_BD_PAD (1 << 12) /* pad enable for short packets */ 145 #define TX_BD_WRAP (1 << 13) 146 #define TX_BD_IRQ (1 << 14) /* interrupt request enable */ 147 #define TX_BD_READY (1 << 15) /* TX buffer ready */ 148 #define TX_BD_LEN(x) (((x) & 0xffff) << 16) 149 #define TX_BD_LEN_MASK (0xffff << 16) 150 151 #define TX_BD_STATS (TX_BD_CS | TX_BD_DF | TX_BD_LC | \ 152 TX_BD_RL | TX_BD_RETRY_MASK | TX_BD_UR) 153 154 /* RX buffer descriptor */ 155 #define RX_BD_LC (1 << 0) /* late collision */ 156 #define RX_BD_CRC (1 << 1) /* RX CRC error */ 157 #define RX_BD_SF (1 << 2) /* short frame */ 158 #define RX_BD_TL (1 << 3) /* too long */ 159 #define RX_BD_DN (1 << 4) /* dribble nibble */ 160 #define RX_BD_IS (1 << 5) /* invalid symbol */ 161 #define RX_BD_OR (1 << 6) /* receiver overrun */ 162 #define RX_BD_MISS (1 << 7) 163 #define RX_BD_CF (1 << 8) /* control frame */ 164 #define RX_BD_WRAP (1 << 13) 165 #define RX_BD_IRQ (1 << 14) /* interrupt request enable */ 166 #define RX_BD_EMPTY (1 << 15) 167 #define RX_BD_LEN(x) (((x) & 0xffff) << 16) 168 169 #define RX_BD_STATS (RX_BD_LC | RX_BD_CRC | RX_BD_SF | RX_BD_TL | \ 170 RX_BD_DN | RX_BD_IS | RX_BD_OR | RX_BD_MISS) 171 172 #define ETHOC_BUFSIZ 1536 173 #define ETHOC_ZLEN 64 174 #define ETHOC_BD_BASE 0x400 175 #define ETHOC_TIMEOUT (HZ / 2) 176 #define ETHOC_MII_TIMEOUT (1 + (HZ / 5)) 177 178 /** 179 * struct ethoc - driver-private device structure 180 * @iobase: pointer to I/O memory region 181 * @membase: pointer to buffer memory region 182 * @dma_alloc: dma allocated buffer size 183 * @io_region_size: I/O memory region size 184 * @num_bd: number of buffer descriptors 185 * @num_tx: number of send buffers 186 * @cur_tx: last send buffer written 187 * @dty_tx: last buffer actually sent 188 * @num_rx: number of receive buffers 189 * @cur_rx: current receive buffer 190 * @vma: pointer to array of virtual memory addresses for buffers 191 * @netdev: pointer to network device structure 192 * @napi: NAPI structure 193 * @msg_enable: device state flags 194 * @lock: device lock 195 * @mdio: MDIO bus for PHY access 196 * @phy_id: address of attached PHY 197 */ 198 struct ethoc { 199 void __iomem *iobase; 200 void __iomem *membase; 201 int dma_alloc; 202 resource_size_t io_region_size; 203 bool big_endian; 204 205 unsigned int num_bd; 206 unsigned int num_tx; 207 unsigned int cur_tx; 208 unsigned int dty_tx; 209 210 unsigned int num_rx; 211 unsigned int cur_rx; 212 213 void **vma; 214 215 struct net_device *netdev; 216 struct napi_struct napi; 217 u32 msg_enable; 218 219 spinlock_t lock; 220 221 struct mii_bus *mdio; 222 struct clk *clk; 223 s8 phy_id; 224 }; 225 226 /** 227 * struct ethoc_bd - buffer descriptor 228 * @stat: buffer statistics 229 * @addr: physical memory address 230 */ 231 struct ethoc_bd { 232 u32 stat; 233 u32 addr; 234 }; 235 236 static inline u32 ethoc_read(struct ethoc *dev, loff_t offset) 237 { 238 if (dev->big_endian) 239 return ioread32be(dev->iobase + offset); 240 else 241 return ioread32(dev->iobase + offset); 242 } 243 244 static inline void ethoc_write(struct ethoc *dev, loff_t offset, u32 data) 245 { 246 if (dev->big_endian) 247 iowrite32be(data, dev->iobase + offset); 248 else 249 iowrite32(data, dev->iobase + offset); 250 } 251 252 static inline void ethoc_read_bd(struct ethoc *dev, int index, 253 struct ethoc_bd *bd) 254 { 255 loff_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd)); 256 bd->stat = ethoc_read(dev, offset + 0); 257 bd->addr = ethoc_read(dev, offset + 4); 258 } 259 260 static inline void ethoc_write_bd(struct ethoc *dev, int index, 261 const struct ethoc_bd *bd) 262 { 263 loff_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd)); 264 ethoc_write(dev, offset + 0, bd->stat); 265 ethoc_write(dev, offset + 4, bd->addr); 266 } 267 268 static inline void ethoc_enable_irq(struct ethoc *dev, u32 mask) 269 { 270 u32 imask = ethoc_read(dev, INT_MASK); 271 imask |= mask; 272 ethoc_write(dev, INT_MASK, imask); 273 } 274 275 static inline void ethoc_disable_irq(struct ethoc *dev, u32 mask) 276 { 277 u32 imask = ethoc_read(dev, INT_MASK); 278 imask &= ~mask; 279 ethoc_write(dev, INT_MASK, imask); 280 } 281 282 static inline void ethoc_ack_irq(struct ethoc *dev, u32 mask) 283 { 284 ethoc_write(dev, INT_SOURCE, mask); 285 } 286 287 static inline void ethoc_enable_rx_and_tx(struct ethoc *dev) 288 { 289 u32 mode = ethoc_read(dev, MODER); 290 mode |= MODER_RXEN | MODER_TXEN; 291 ethoc_write(dev, MODER, mode); 292 } 293 294 static inline void ethoc_disable_rx_and_tx(struct ethoc *dev) 295 { 296 u32 mode = ethoc_read(dev, MODER); 297 mode &= ~(MODER_RXEN | MODER_TXEN); 298 ethoc_write(dev, MODER, mode); 299 } 300 301 static int ethoc_init_ring(struct ethoc *dev, unsigned long mem_start) 302 { 303 struct ethoc_bd bd; 304 int i; 305 void *vma; 306 307 dev->cur_tx = 0; 308 dev->dty_tx = 0; 309 dev->cur_rx = 0; 310 311 ethoc_write(dev, TX_BD_NUM, dev->num_tx); 312 313 /* setup transmission buffers */ 314 bd.addr = mem_start; 315 bd.stat = TX_BD_IRQ | TX_BD_CRC; 316 vma = dev->membase; 317 318 for (i = 0; i < dev->num_tx; i++) { 319 if (i == dev->num_tx - 1) 320 bd.stat |= TX_BD_WRAP; 321 322 ethoc_write_bd(dev, i, &bd); 323 bd.addr += ETHOC_BUFSIZ; 324 325 dev->vma[i] = vma; 326 vma += ETHOC_BUFSIZ; 327 } 328 329 bd.stat = RX_BD_EMPTY | RX_BD_IRQ; 330 331 for (i = 0; i < dev->num_rx; i++) { 332 if (i == dev->num_rx - 1) 333 bd.stat |= RX_BD_WRAP; 334 335 ethoc_write_bd(dev, dev->num_tx + i, &bd); 336 bd.addr += ETHOC_BUFSIZ; 337 338 dev->vma[dev->num_tx + i] = vma; 339 vma += ETHOC_BUFSIZ; 340 } 341 342 return 0; 343 } 344 345 static int ethoc_reset(struct ethoc *dev) 346 { 347 u32 mode; 348 349 /* TODO: reset controller? */ 350 351 ethoc_disable_rx_and_tx(dev); 352 353 /* TODO: setup registers */ 354 355 /* enable FCS generation and automatic padding */ 356 mode = ethoc_read(dev, MODER); 357 mode |= MODER_CRC | MODER_PAD; 358 ethoc_write(dev, MODER, mode); 359 360 /* set full-duplex mode */ 361 mode = ethoc_read(dev, MODER); 362 mode |= MODER_FULLD; 363 ethoc_write(dev, MODER, mode); 364 ethoc_write(dev, IPGT, 0x15); 365 366 ethoc_ack_irq(dev, INT_MASK_ALL); 367 ethoc_enable_irq(dev, INT_MASK_ALL); 368 ethoc_enable_rx_and_tx(dev); 369 return 0; 370 } 371 372 static unsigned int ethoc_update_rx_stats(struct ethoc *dev, 373 struct ethoc_bd *bd) 374 { 375 struct net_device *netdev = dev->netdev; 376 unsigned int ret = 0; 377 378 if (bd->stat & RX_BD_TL) { 379 dev_err(&netdev->dev, "RX: frame too long\n"); 380 netdev->stats.rx_length_errors++; 381 ret++; 382 } 383 384 if (bd->stat & RX_BD_SF) { 385 dev_err(&netdev->dev, "RX: frame too short\n"); 386 netdev->stats.rx_length_errors++; 387 ret++; 388 } 389 390 if (bd->stat & RX_BD_DN) { 391 dev_err(&netdev->dev, "RX: dribble nibble\n"); 392 netdev->stats.rx_frame_errors++; 393 } 394 395 if (bd->stat & RX_BD_CRC) { 396 dev_err(&netdev->dev, "RX: wrong CRC\n"); 397 netdev->stats.rx_crc_errors++; 398 ret++; 399 } 400 401 if (bd->stat & RX_BD_OR) { 402 dev_err(&netdev->dev, "RX: overrun\n"); 403 netdev->stats.rx_over_errors++; 404 ret++; 405 } 406 407 if (bd->stat & RX_BD_MISS) 408 netdev->stats.rx_missed_errors++; 409 410 if (bd->stat & RX_BD_LC) { 411 dev_err(&netdev->dev, "RX: late collision\n"); 412 netdev->stats.collisions++; 413 ret++; 414 } 415 416 return ret; 417 } 418 419 static int ethoc_rx(struct net_device *dev, int limit) 420 { 421 struct ethoc *priv = netdev_priv(dev); 422 int count; 423 424 for (count = 0; count < limit; ++count) { 425 unsigned int entry; 426 struct ethoc_bd bd; 427 428 entry = priv->num_tx + priv->cur_rx; 429 ethoc_read_bd(priv, entry, &bd); 430 if (bd.stat & RX_BD_EMPTY) { 431 ethoc_ack_irq(priv, INT_MASK_RX); 432 /* If packet (interrupt) came in between checking 433 * BD_EMTPY and clearing the interrupt source, then we 434 * risk missing the packet as the RX interrupt won't 435 * trigger right away when we reenable it; hence, check 436 * BD_EMTPY here again to make sure there isn't such a 437 * packet waiting for us... 438 */ 439 ethoc_read_bd(priv, entry, &bd); 440 if (bd.stat & RX_BD_EMPTY) 441 break; 442 } 443 444 if (ethoc_update_rx_stats(priv, &bd) == 0) { 445 int size = bd.stat >> 16; 446 struct sk_buff *skb; 447 448 size -= 4; /* strip the CRC */ 449 skb = netdev_alloc_skb_ip_align(dev, size); 450 451 if (likely(skb)) { 452 void *src = priv->vma[entry]; 453 memcpy_fromio(skb_put(skb, size), src, size); 454 skb->protocol = eth_type_trans(skb, dev); 455 dev->stats.rx_packets++; 456 dev->stats.rx_bytes += size; 457 netif_receive_skb(skb); 458 } else { 459 if (net_ratelimit()) 460 dev_warn(&dev->dev, 461 "low on memory - packet dropped\n"); 462 463 dev->stats.rx_dropped++; 464 break; 465 } 466 } 467 468 /* clear the buffer descriptor so it can be reused */ 469 bd.stat &= ~RX_BD_STATS; 470 bd.stat |= RX_BD_EMPTY; 471 ethoc_write_bd(priv, entry, &bd); 472 if (++priv->cur_rx == priv->num_rx) 473 priv->cur_rx = 0; 474 } 475 476 return count; 477 } 478 479 static void ethoc_update_tx_stats(struct ethoc *dev, struct ethoc_bd *bd) 480 { 481 struct net_device *netdev = dev->netdev; 482 483 if (bd->stat & TX_BD_LC) { 484 dev_err(&netdev->dev, "TX: late collision\n"); 485 netdev->stats.tx_window_errors++; 486 } 487 488 if (bd->stat & TX_BD_RL) { 489 dev_err(&netdev->dev, "TX: retransmit limit\n"); 490 netdev->stats.tx_aborted_errors++; 491 } 492 493 if (bd->stat & TX_BD_UR) { 494 dev_err(&netdev->dev, "TX: underrun\n"); 495 netdev->stats.tx_fifo_errors++; 496 } 497 498 if (bd->stat & TX_BD_CS) { 499 dev_err(&netdev->dev, "TX: carrier sense lost\n"); 500 netdev->stats.tx_carrier_errors++; 501 } 502 503 if (bd->stat & TX_BD_STATS) 504 netdev->stats.tx_errors++; 505 506 netdev->stats.collisions += (bd->stat >> 4) & 0xf; 507 netdev->stats.tx_bytes += bd->stat >> 16; 508 netdev->stats.tx_packets++; 509 } 510 511 static int ethoc_tx(struct net_device *dev, int limit) 512 { 513 struct ethoc *priv = netdev_priv(dev); 514 int count; 515 struct ethoc_bd bd; 516 517 for (count = 0; count < limit; ++count) { 518 unsigned int entry; 519 520 entry = priv->dty_tx & (priv->num_tx-1); 521 522 ethoc_read_bd(priv, entry, &bd); 523 524 if (bd.stat & TX_BD_READY || (priv->dty_tx == priv->cur_tx)) { 525 ethoc_ack_irq(priv, INT_MASK_TX); 526 /* If interrupt came in between reading in the BD 527 * and clearing the interrupt source, then we risk 528 * missing the event as the TX interrupt won't trigger 529 * right away when we reenable it; hence, check 530 * BD_EMPTY here again to make sure there isn't such an 531 * event pending... 532 */ 533 ethoc_read_bd(priv, entry, &bd); 534 if (bd.stat & TX_BD_READY || 535 (priv->dty_tx == priv->cur_tx)) 536 break; 537 } 538 539 ethoc_update_tx_stats(priv, &bd); 540 priv->dty_tx++; 541 } 542 543 if ((priv->cur_tx - priv->dty_tx) <= (priv->num_tx / 2)) 544 netif_wake_queue(dev); 545 546 return count; 547 } 548 549 static irqreturn_t ethoc_interrupt(int irq, void *dev_id) 550 { 551 struct net_device *dev = dev_id; 552 struct ethoc *priv = netdev_priv(dev); 553 u32 pending; 554 u32 mask; 555 556 /* Figure out what triggered the interrupt... 557 * The tricky bit here is that the interrupt source bits get 558 * set in INT_SOURCE for an event regardless of whether that 559 * event is masked or not. Thus, in order to figure out what 560 * triggered the interrupt, we need to remove the sources 561 * for all events that are currently masked. This behaviour 562 * is not particularly well documented but reasonable... 563 */ 564 mask = ethoc_read(priv, INT_MASK); 565 pending = ethoc_read(priv, INT_SOURCE); 566 pending &= mask; 567 568 if (unlikely(pending == 0)) 569 return IRQ_NONE; 570 571 ethoc_ack_irq(priv, pending); 572 573 /* We always handle the dropped packet interrupt */ 574 if (pending & INT_MASK_BUSY) { 575 dev_err(&dev->dev, "packet dropped\n"); 576 dev->stats.rx_dropped++; 577 } 578 579 /* Handle receive/transmit event by switching to polling */ 580 if (pending & (INT_MASK_TX | INT_MASK_RX)) { 581 ethoc_disable_irq(priv, INT_MASK_TX | INT_MASK_RX); 582 napi_schedule(&priv->napi); 583 } 584 585 return IRQ_HANDLED; 586 } 587 588 static int ethoc_get_mac_address(struct net_device *dev, void *addr) 589 { 590 struct ethoc *priv = netdev_priv(dev); 591 u8 *mac = (u8 *)addr; 592 u32 reg; 593 594 reg = ethoc_read(priv, MAC_ADDR0); 595 mac[2] = (reg >> 24) & 0xff; 596 mac[3] = (reg >> 16) & 0xff; 597 mac[4] = (reg >> 8) & 0xff; 598 mac[5] = (reg >> 0) & 0xff; 599 600 reg = ethoc_read(priv, MAC_ADDR1); 601 mac[0] = (reg >> 8) & 0xff; 602 mac[1] = (reg >> 0) & 0xff; 603 604 return 0; 605 } 606 607 static int ethoc_poll(struct napi_struct *napi, int budget) 608 { 609 struct ethoc *priv = container_of(napi, struct ethoc, napi); 610 int rx_work_done = 0; 611 int tx_work_done = 0; 612 613 rx_work_done = ethoc_rx(priv->netdev, budget); 614 tx_work_done = ethoc_tx(priv->netdev, budget); 615 616 if (rx_work_done < budget && tx_work_done < budget) { 617 napi_complete(napi); 618 ethoc_enable_irq(priv, INT_MASK_TX | INT_MASK_RX); 619 } 620 621 return rx_work_done; 622 } 623 624 static int ethoc_mdio_read(struct mii_bus *bus, int phy, int reg) 625 { 626 struct ethoc *priv = bus->priv; 627 int i; 628 629 ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(phy, reg)); 630 ethoc_write(priv, MIICOMMAND, MIICOMMAND_READ); 631 632 for (i = 0; i < 5; i++) { 633 u32 status = ethoc_read(priv, MIISTATUS); 634 if (!(status & MIISTATUS_BUSY)) { 635 u32 data = ethoc_read(priv, MIIRX_DATA); 636 /* reset MII command register */ 637 ethoc_write(priv, MIICOMMAND, 0); 638 return data; 639 } 640 usleep_range(100, 200); 641 } 642 643 return -EBUSY; 644 } 645 646 static int ethoc_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 647 { 648 struct ethoc *priv = bus->priv; 649 int i; 650 651 ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(phy, reg)); 652 ethoc_write(priv, MIITX_DATA, val); 653 ethoc_write(priv, MIICOMMAND, MIICOMMAND_WRITE); 654 655 for (i = 0; i < 5; i++) { 656 u32 stat = ethoc_read(priv, MIISTATUS); 657 if (!(stat & MIISTATUS_BUSY)) { 658 /* reset MII command register */ 659 ethoc_write(priv, MIICOMMAND, 0); 660 return 0; 661 } 662 usleep_range(100, 200); 663 } 664 665 return -EBUSY; 666 } 667 668 static void ethoc_mdio_poll(struct net_device *dev) 669 { 670 } 671 672 static int ethoc_mdio_probe(struct net_device *dev) 673 { 674 struct ethoc *priv = netdev_priv(dev); 675 struct phy_device *phy; 676 int err; 677 678 if (priv->phy_id != -1) 679 phy = mdiobus_get_phy(priv->mdio, priv->phy_id); 680 else 681 phy = phy_find_first(priv->mdio); 682 683 if (!phy) { 684 dev_err(&dev->dev, "no PHY found\n"); 685 return -ENXIO; 686 } 687 688 err = phy_connect_direct(dev, phy, ethoc_mdio_poll, 689 PHY_INTERFACE_MODE_GMII); 690 if (err) { 691 dev_err(&dev->dev, "could not attach to PHY\n"); 692 return err; 693 } 694 695 phy->advertising &= ~(ADVERTISED_1000baseT_Full | 696 ADVERTISED_1000baseT_Half); 697 phy->supported &= ~(SUPPORTED_1000baseT_Full | 698 SUPPORTED_1000baseT_Half); 699 700 return 0; 701 } 702 703 static int ethoc_open(struct net_device *dev) 704 { 705 struct ethoc *priv = netdev_priv(dev); 706 int ret; 707 708 ret = request_irq(dev->irq, ethoc_interrupt, IRQF_SHARED, 709 dev->name, dev); 710 if (ret) 711 return ret; 712 713 ethoc_init_ring(priv, dev->mem_start); 714 ethoc_reset(priv); 715 716 if (netif_queue_stopped(dev)) { 717 dev_dbg(&dev->dev, " resuming queue\n"); 718 netif_wake_queue(dev); 719 } else { 720 dev_dbg(&dev->dev, " starting queue\n"); 721 netif_start_queue(dev); 722 } 723 724 phy_start(dev->phydev); 725 napi_enable(&priv->napi); 726 727 if (netif_msg_ifup(priv)) { 728 dev_info(&dev->dev, "I/O: %08lx Memory: %08lx-%08lx\n", 729 dev->base_addr, dev->mem_start, dev->mem_end); 730 } 731 732 return 0; 733 } 734 735 static int ethoc_stop(struct net_device *dev) 736 { 737 struct ethoc *priv = netdev_priv(dev); 738 739 napi_disable(&priv->napi); 740 741 if (dev->phydev) 742 phy_stop(dev->phydev); 743 744 ethoc_disable_rx_and_tx(priv); 745 free_irq(dev->irq, dev); 746 747 if (!netif_queue_stopped(dev)) 748 netif_stop_queue(dev); 749 750 return 0; 751 } 752 753 static int ethoc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 754 { 755 struct ethoc *priv = netdev_priv(dev); 756 struct mii_ioctl_data *mdio = if_mii(ifr); 757 struct phy_device *phy = NULL; 758 759 if (!netif_running(dev)) 760 return -EINVAL; 761 762 if (cmd != SIOCGMIIPHY) { 763 if (mdio->phy_id >= PHY_MAX_ADDR) 764 return -ERANGE; 765 766 phy = mdiobus_get_phy(priv->mdio, mdio->phy_id); 767 if (!phy) 768 return -ENODEV; 769 } else { 770 phy = dev->phydev; 771 } 772 773 return phy_mii_ioctl(phy, ifr, cmd); 774 } 775 776 static void ethoc_do_set_mac_address(struct net_device *dev) 777 { 778 struct ethoc *priv = netdev_priv(dev); 779 unsigned char *mac = dev->dev_addr; 780 781 ethoc_write(priv, MAC_ADDR0, (mac[2] << 24) | (mac[3] << 16) | 782 (mac[4] << 8) | (mac[5] << 0)); 783 ethoc_write(priv, MAC_ADDR1, (mac[0] << 8) | (mac[1] << 0)); 784 } 785 786 static int ethoc_set_mac_address(struct net_device *dev, void *p) 787 { 788 const struct sockaddr *addr = p; 789 790 if (!is_valid_ether_addr(addr->sa_data)) 791 return -EADDRNOTAVAIL; 792 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); 793 ethoc_do_set_mac_address(dev); 794 return 0; 795 } 796 797 static void ethoc_set_multicast_list(struct net_device *dev) 798 { 799 struct ethoc *priv = netdev_priv(dev); 800 u32 mode = ethoc_read(priv, MODER); 801 struct netdev_hw_addr *ha; 802 u32 hash[2] = { 0, 0 }; 803 804 /* set loopback mode if requested */ 805 if (dev->flags & IFF_LOOPBACK) 806 mode |= MODER_LOOP; 807 else 808 mode &= ~MODER_LOOP; 809 810 /* receive broadcast frames if requested */ 811 if (dev->flags & IFF_BROADCAST) 812 mode &= ~MODER_BRO; 813 else 814 mode |= MODER_BRO; 815 816 /* enable promiscuous mode if requested */ 817 if (dev->flags & IFF_PROMISC) 818 mode |= MODER_PRO; 819 else 820 mode &= ~MODER_PRO; 821 822 ethoc_write(priv, MODER, mode); 823 824 /* receive multicast frames */ 825 if (dev->flags & IFF_ALLMULTI) { 826 hash[0] = 0xffffffff; 827 hash[1] = 0xffffffff; 828 } else { 829 netdev_for_each_mc_addr(ha, dev) { 830 u32 crc = ether_crc(ETH_ALEN, ha->addr); 831 int bit = (crc >> 26) & 0x3f; 832 hash[bit >> 5] |= 1 << (bit & 0x1f); 833 } 834 } 835 836 ethoc_write(priv, ETH_HASH0, hash[0]); 837 ethoc_write(priv, ETH_HASH1, hash[1]); 838 } 839 840 static int ethoc_change_mtu(struct net_device *dev, int new_mtu) 841 { 842 return -ENOSYS; 843 } 844 845 static void ethoc_tx_timeout(struct net_device *dev) 846 { 847 struct ethoc *priv = netdev_priv(dev); 848 u32 pending = ethoc_read(priv, INT_SOURCE); 849 if (likely(pending)) 850 ethoc_interrupt(dev->irq, dev); 851 } 852 853 static netdev_tx_t ethoc_start_xmit(struct sk_buff *skb, struct net_device *dev) 854 { 855 struct ethoc *priv = netdev_priv(dev); 856 struct ethoc_bd bd; 857 unsigned int entry; 858 void *dest; 859 860 if (skb_put_padto(skb, ETHOC_ZLEN)) { 861 dev->stats.tx_errors++; 862 goto out_no_free; 863 } 864 865 if (unlikely(skb->len > ETHOC_BUFSIZ)) { 866 dev->stats.tx_errors++; 867 goto out; 868 } 869 870 entry = priv->cur_tx % priv->num_tx; 871 spin_lock_irq(&priv->lock); 872 priv->cur_tx++; 873 874 ethoc_read_bd(priv, entry, &bd); 875 if (unlikely(skb->len < ETHOC_ZLEN)) 876 bd.stat |= TX_BD_PAD; 877 else 878 bd.stat &= ~TX_BD_PAD; 879 880 dest = priv->vma[entry]; 881 memcpy_toio(dest, skb->data, skb->len); 882 883 bd.stat &= ~(TX_BD_STATS | TX_BD_LEN_MASK); 884 bd.stat |= TX_BD_LEN(skb->len); 885 ethoc_write_bd(priv, entry, &bd); 886 887 bd.stat |= TX_BD_READY; 888 ethoc_write_bd(priv, entry, &bd); 889 890 if (priv->cur_tx == (priv->dty_tx + priv->num_tx)) { 891 dev_dbg(&dev->dev, "stopping queue\n"); 892 netif_stop_queue(dev); 893 } 894 895 spin_unlock_irq(&priv->lock); 896 skb_tx_timestamp(skb); 897 out: 898 dev_kfree_skb(skb); 899 out_no_free: 900 return NETDEV_TX_OK; 901 } 902 903 static int ethoc_get_regs_len(struct net_device *netdev) 904 { 905 return ETH_END; 906 } 907 908 static void ethoc_get_regs(struct net_device *dev, struct ethtool_regs *regs, 909 void *p) 910 { 911 struct ethoc *priv = netdev_priv(dev); 912 u32 *regs_buff = p; 913 unsigned i; 914 915 regs->version = 0; 916 for (i = 0; i < ETH_END / sizeof(u32); ++i) 917 regs_buff[i] = ethoc_read(priv, i * sizeof(u32)); 918 } 919 920 static void ethoc_get_ringparam(struct net_device *dev, 921 struct ethtool_ringparam *ring) 922 { 923 struct ethoc *priv = netdev_priv(dev); 924 925 ring->rx_max_pending = priv->num_bd - 1; 926 ring->rx_mini_max_pending = 0; 927 ring->rx_jumbo_max_pending = 0; 928 ring->tx_max_pending = priv->num_bd - 1; 929 930 ring->rx_pending = priv->num_rx; 931 ring->rx_mini_pending = 0; 932 ring->rx_jumbo_pending = 0; 933 ring->tx_pending = priv->num_tx; 934 } 935 936 static int ethoc_set_ringparam(struct net_device *dev, 937 struct ethtool_ringparam *ring) 938 { 939 struct ethoc *priv = netdev_priv(dev); 940 941 if (ring->tx_pending < 1 || ring->rx_pending < 1 || 942 ring->tx_pending + ring->rx_pending > priv->num_bd) 943 return -EINVAL; 944 if (ring->rx_mini_pending || ring->rx_jumbo_pending) 945 return -EINVAL; 946 947 if (netif_running(dev)) { 948 netif_tx_disable(dev); 949 ethoc_disable_rx_and_tx(priv); 950 ethoc_disable_irq(priv, INT_MASK_TX | INT_MASK_RX); 951 synchronize_irq(dev->irq); 952 } 953 954 priv->num_tx = rounddown_pow_of_two(ring->tx_pending); 955 priv->num_rx = ring->rx_pending; 956 ethoc_init_ring(priv, dev->mem_start); 957 958 if (netif_running(dev)) { 959 ethoc_enable_irq(priv, INT_MASK_TX | INT_MASK_RX); 960 ethoc_enable_rx_and_tx(priv); 961 netif_wake_queue(dev); 962 } 963 return 0; 964 } 965 966 const struct ethtool_ops ethoc_ethtool_ops = { 967 .get_regs_len = ethoc_get_regs_len, 968 .get_regs = ethoc_get_regs, 969 .get_link = ethtool_op_get_link, 970 .get_ringparam = ethoc_get_ringparam, 971 .set_ringparam = ethoc_set_ringparam, 972 .get_ts_info = ethtool_op_get_ts_info, 973 .get_link_ksettings = phy_ethtool_get_link_ksettings, 974 .set_link_ksettings = phy_ethtool_set_link_ksettings, 975 }; 976 977 static const struct net_device_ops ethoc_netdev_ops = { 978 .ndo_open = ethoc_open, 979 .ndo_stop = ethoc_stop, 980 .ndo_do_ioctl = ethoc_ioctl, 981 .ndo_set_mac_address = ethoc_set_mac_address, 982 .ndo_set_rx_mode = ethoc_set_multicast_list, 983 .ndo_change_mtu = ethoc_change_mtu, 984 .ndo_tx_timeout = ethoc_tx_timeout, 985 .ndo_start_xmit = ethoc_start_xmit, 986 }; 987 988 /** 989 * ethoc_probe - initialize OpenCores ethernet MAC 990 * pdev: platform device 991 */ 992 static int ethoc_probe(struct platform_device *pdev) 993 { 994 struct net_device *netdev = NULL; 995 struct resource *res = NULL; 996 struct resource *mmio = NULL; 997 struct resource *mem = NULL; 998 struct ethoc *priv = NULL; 999 int num_bd; 1000 int ret = 0; 1001 bool random_mac = false; 1002 struct ethoc_platform_data *pdata = dev_get_platdata(&pdev->dev); 1003 u32 eth_clkfreq = pdata ? pdata->eth_clkfreq : 0; 1004 1005 /* allocate networking device */ 1006 netdev = alloc_etherdev(sizeof(struct ethoc)); 1007 if (!netdev) { 1008 ret = -ENOMEM; 1009 goto out; 1010 } 1011 1012 SET_NETDEV_DEV(netdev, &pdev->dev); 1013 platform_set_drvdata(pdev, netdev); 1014 1015 /* obtain I/O memory space */ 1016 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1017 if (!res) { 1018 dev_err(&pdev->dev, "cannot obtain I/O memory space\n"); 1019 ret = -ENXIO; 1020 goto free; 1021 } 1022 1023 mmio = devm_request_mem_region(&pdev->dev, res->start, 1024 resource_size(res), res->name); 1025 if (!mmio) { 1026 dev_err(&pdev->dev, "cannot request I/O memory space\n"); 1027 ret = -ENXIO; 1028 goto free; 1029 } 1030 1031 netdev->base_addr = mmio->start; 1032 1033 /* obtain buffer memory space */ 1034 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1035 if (res) { 1036 mem = devm_request_mem_region(&pdev->dev, res->start, 1037 resource_size(res), res->name); 1038 if (!mem) { 1039 dev_err(&pdev->dev, "cannot request memory space\n"); 1040 ret = -ENXIO; 1041 goto free; 1042 } 1043 1044 netdev->mem_start = mem->start; 1045 netdev->mem_end = mem->end; 1046 } 1047 1048 1049 /* obtain device IRQ number */ 1050 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1051 if (!res) { 1052 dev_err(&pdev->dev, "cannot obtain IRQ\n"); 1053 ret = -ENXIO; 1054 goto free; 1055 } 1056 1057 netdev->irq = res->start; 1058 1059 /* setup driver-private data */ 1060 priv = netdev_priv(netdev); 1061 priv->netdev = netdev; 1062 priv->dma_alloc = 0; 1063 priv->io_region_size = resource_size(mmio); 1064 1065 priv->iobase = devm_ioremap_nocache(&pdev->dev, netdev->base_addr, 1066 resource_size(mmio)); 1067 if (!priv->iobase) { 1068 dev_err(&pdev->dev, "cannot remap I/O memory space\n"); 1069 ret = -ENXIO; 1070 goto free; 1071 } 1072 1073 if (netdev->mem_end) { 1074 priv->membase = devm_ioremap_nocache(&pdev->dev, 1075 netdev->mem_start, resource_size(mem)); 1076 if (!priv->membase) { 1077 dev_err(&pdev->dev, "cannot remap memory space\n"); 1078 ret = -ENXIO; 1079 goto free; 1080 } 1081 } else { 1082 /* Allocate buffer memory */ 1083 priv->membase = dmam_alloc_coherent(&pdev->dev, 1084 buffer_size, (void *)&netdev->mem_start, 1085 GFP_KERNEL); 1086 if (!priv->membase) { 1087 dev_err(&pdev->dev, "cannot allocate %dB buffer\n", 1088 buffer_size); 1089 ret = -ENOMEM; 1090 goto free; 1091 } 1092 netdev->mem_end = netdev->mem_start + buffer_size; 1093 priv->dma_alloc = buffer_size; 1094 } 1095 1096 priv->big_endian = pdata ? pdata->big_endian : 1097 of_device_is_big_endian(pdev->dev.of_node); 1098 1099 /* calculate the number of TX/RX buffers, maximum 128 supported */ 1100 num_bd = min_t(unsigned int, 1101 128, (netdev->mem_end - netdev->mem_start + 1) / ETHOC_BUFSIZ); 1102 if (num_bd < 4) { 1103 ret = -ENODEV; 1104 goto free; 1105 } 1106 priv->num_bd = num_bd; 1107 /* num_tx must be a power of two */ 1108 priv->num_tx = rounddown_pow_of_two(num_bd >> 1); 1109 priv->num_rx = num_bd - priv->num_tx; 1110 1111 dev_dbg(&pdev->dev, "ethoc: num_tx: %d num_rx: %d\n", 1112 priv->num_tx, priv->num_rx); 1113 1114 priv->vma = devm_kzalloc(&pdev->dev, num_bd*sizeof(void *), GFP_KERNEL); 1115 if (!priv->vma) { 1116 ret = -ENOMEM; 1117 goto free; 1118 } 1119 1120 /* Allow the platform setup code to pass in a MAC address. */ 1121 if (pdata) { 1122 memcpy(netdev->dev_addr, pdata->hwaddr, IFHWADDRLEN); 1123 priv->phy_id = pdata->phy_id; 1124 } else { 1125 const uint8_t *mac; 1126 1127 mac = of_get_property(pdev->dev.of_node, 1128 "local-mac-address", 1129 NULL); 1130 if (mac) 1131 memcpy(netdev->dev_addr, mac, IFHWADDRLEN); 1132 priv->phy_id = -1; 1133 } 1134 1135 /* Check that the given MAC address is valid. If it isn't, read the 1136 * current MAC from the controller. 1137 */ 1138 if (!is_valid_ether_addr(netdev->dev_addr)) 1139 ethoc_get_mac_address(netdev, netdev->dev_addr); 1140 1141 /* Check the MAC again for validity, if it still isn't choose and 1142 * program a random one. 1143 */ 1144 if (!is_valid_ether_addr(netdev->dev_addr)) { 1145 eth_random_addr(netdev->dev_addr); 1146 random_mac = true; 1147 } 1148 1149 ethoc_do_set_mac_address(netdev); 1150 1151 if (random_mac) 1152 netdev->addr_assign_type = NET_ADDR_RANDOM; 1153 1154 /* Allow the platform setup code to adjust MII management bus clock. */ 1155 if (!eth_clkfreq) { 1156 struct clk *clk = devm_clk_get(&pdev->dev, NULL); 1157 1158 if (!IS_ERR(clk)) { 1159 priv->clk = clk; 1160 clk_prepare_enable(clk); 1161 eth_clkfreq = clk_get_rate(clk); 1162 } 1163 } 1164 if (eth_clkfreq) { 1165 u32 clkdiv = MIIMODER_CLKDIV(eth_clkfreq / 2500000 + 1); 1166 1167 if (!clkdiv) 1168 clkdiv = 2; 1169 dev_dbg(&pdev->dev, "setting MII clkdiv to %u\n", clkdiv); 1170 ethoc_write(priv, MIIMODER, 1171 (ethoc_read(priv, MIIMODER) & MIIMODER_NOPRE) | 1172 clkdiv); 1173 } 1174 1175 /* register MII bus */ 1176 priv->mdio = mdiobus_alloc(); 1177 if (!priv->mdio) { 1178 ret = -ENOMEM; 1179 goto free2; 1180 } 1181 1182 priv->mdio->name = "ethoc-mdio"; 1183 snprintf(priv->mdio->id, MII_BUS_ID_SIZE, "%s-%d", 1184 priv->mdio->name, pdev->id); 1185 priv->mdio->read = ethoc_mdio_read; 1186 priv->mdio->write = ethoc_mdio_write; 1187 priv->mdio->priv = priv; 1188 1189 ret = mdiobus_register(priv->mdio); 1190 if (ret) { 1191 dev_err(&netdev->dev, "failed to register MDIO bus\n"); 1192 goto free2; 1193 } 1194 1195 ret = ethoc_mdio_probe(netdev); 1196 if (ret) { 1197 dev_err(&netdev->dev, "failed to probe MDIO bus\n"); 1198 goto error; 1199 } 1200 1201 /* setup the net_device structure */ 1202 netdev->netdev_ops = ðoc_netdev_ops; 1203 netdev->watchdog_timeo = ETHOC_TIMEOUT; 1204 netdev->features |= 0; 1205 netdev->ethtool_ops = ðoc_ethtool_ops; 1206 1207 /* setup NAPI */ 1208 netif_napi_add(netdev, &priv->napi, ethoc_poll, 64); 1209 1210 spin_lock_init(&priv->lock); 1211 1212 ret = register_netdev(netdev); 1213 if (ret < 0) { 1214 dev_err(&netdev->dev, "failed to register interface\n"); 1215 goto error2; 1216 } 1217 1218 goto out; 1219 1220 error2: 1221 netif_napi_del(&priv->napi); 1222 error: 1223 mdiobus_unregister(priv->mdio); 1224 mdiobus_free(priv->mdio); 1225 free2: 1226 if (priv->clk) 1227 clk_disable_unprepare(priv->clk); 1228 free: 1229 free_netdev(netdev); 1230 out: 1231 return ret; 1232 } 1233 1234 /** 1235 * ethoc_remove - shutdown OpenCores ethernet MAC 1236 * @pdev: platform device 1237 */ 1238 static int ethoc_remove(struct platform_device *pdev) 1239 { 1240 struct net_device *netdev = platform_get_drvdata(pdev); 1241 struct ethoc *priv = netdev_priv(netdev); 1242 1243 if (netdev) { 1244 netif_napi_del(&priv->napi); 1245 phy_disconnect(netdev->phydev); 1246 1247 if (priv->mdio) { 1248 mdiobus_unregister(priv->mdio); 1249 mdiobus_free(priv->mdio); 1250 } 1251 if (priv->clk) 1252 clk_disable_unprepare(priv->clk); 1253 unregister_netdev(netdev); 1254 free_netdev(netdev); 1255 } 1256 1257 return 0; 1258 } 1259 1260 #ifdef CONFIG_PM 1261 static int ethoc_suspend(struct platform_device *pdev, pm_message_t state) 1262 { 1263 return -ENOSYS; 1264 } 1265 1266 static int ethoc_resume(struct platform_device *pdev) 1267 { 1268 return -ENOSYS; 1269 } 1270 #else 1271 # define ethoc_suspend NULL 1272 # define ethoc_resume NULL 1273 #endif 1274 1275 static const struct of_device_id ethoc_match[] = { 1276 { .compatible = "opencores,ethoc", }, 1277 {}, 1278 }; 1279 MODULE_DEVICE_TABLE(of, ethoc_match); 1280 1281 static struct platform_driver ethoc_driver = { 1282 .probe = ethoc_probe, 1283 .remove = ethoc_remove, 1284 .suspend = ethoc_suspend, 1285 .resume = ethoc_resume, 1286 .driver = { 1287 .name = "ethoc", 1288 .of_match_table = ethoc_match, 1289 }, 1290 }; 1291 1292 module_platform_driver(ethoc_driver); 1293 1294 MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>"); 1295 MODULE_DESCRIPTION("OpenCores Ethernet MAC driver"); 1296 MODULE_LICENSE("GPL v2"); 1297 1298