1 /* 2 * Copyright (C) 2005-2016 Broadcom. 3 * All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License version 2 7 * as published by the Free Software Foundation. The full GNU General 8 * Public License is included in this distribution in the file called COPYING. 9 * 10 * Contact Information: 11 * linux-drivers@emulex.com 12 * 13 * Emulex 14 * 3333 Susan Street 15 * Costa Mesa, CA 92626 16 */ 17 18 /********* Mailbox door bell *************/ 19 /* Used for driver communication with the FW. 20 * The software must write this register twice to post any command. First, 21 * it writes the register with hi=1 and the upper bits of the physical address 22 * for the MAILBOX structure. Software must poll the ready bit until this 23 * is acknowledged. Then, sotware writes the register with hi=0 with the lower 24 * bits in the address. It must poll the ready bit until the command is 25 * complete. Upon completion, the MAILBOX will contain a valid completion 26 * queue entry. 27 */ 28 #define MPU_MAILBOX_DB_OFFSET 0x160 29 #define MPU_MAILBOX_DB_RDY_MASK 0x1 /* bit 0 */ 30 #define MPU_MAILBOX_DB_HI_MASK 0x2 /* bit 1 */ 31 32 #define MPU_EP_CONTROL 0 33 34 /********** MPU semphore: used for SH & BE *************/ 35 #define SLIPORT_SOFTRESET_OFFSET 0x5c /* CSR BAR offset */ 36 #define SLIPORT_SEMAPHORE_OFFSET_BEx 0xac /* CSR BAR offset */ 37 #define SLIPORT_SEMAPHORE_OFFSET_SH 0x94 /* PCI-CFG offset */ 38 #define POST_STAGE_MASK 0x0000FFFF 39 #define POST_ERR_MASK 0x1 40 #define POST_ERR_SHIFT 31 41 #define POST_ERR_RECOVERY_CODE_MASK 0xFFF 42 43 /* Soft Reset register masks */ 44 #define SLIPORT_SOFTRESET_SR_MASK 0x00000080 /* SR bit */ 45 46 /* MPU semphore POST stage values */ 47 #define POST_STAGE_AWAITING_HOST_RDY 0x1 /* FW awaiting goahead from host */ 48 #define POST_STAGE_HOST_RDY 0x2 /* Host has given go-ahed to FW */ 49 #define POST_STAGE_BE_RESET 0x3 /* Host wants to reset chip */ 50 #define POST_STAGE_ARMFW_RDY 0xc000 /* FW is done with POST */ 51 #define POST_STAGE_RECOVERABLE_ERR 0xE000 /* Recoverable err detected */ 52 /* FW has detected a UE and is dumping FAT log data */ 53 #define POST_STAGE_FAT_LOG_START 0x0D00 54 #define POST_STAGE_ARMFW_UE 0xF000 /*FW has asserted an UE*/ 55 56 /* Lancer SLIPORT registers */ 57 #define SLIPORT_STATUS_OFFSET 0x404 58 #define SLIPORT_CONTROL_OFFSET 0x408 59 #define SLIPORT_ERROR1_OFFSET 0x40C 60 #define SLIPORT_ERROR2_OFFSET 0x410 61 #define PHYSDEV_CONTROL_OFFSET 0x414 62 63 #define SLIPORT_STATUS_ERR_MASK 0x80000000 64 #define SLIPORT_STATUS_DIP_MASK 0x02000000 65 #define SLIPORT_STATUS_RN_MASK 0x01000000 66 #define SLIPORT_STATUS_RDY_MASK 0x00800000 67 #define SLI_PORT_CONTROL_IP_MASK 0x08000000 68 #define PHYSDEV_CONTROL_FW_RESET_MASK 0x00000002 69 #define PHYSDEV_CONTROL_DD_MASK 0x00000004 70 #define PHYSDEV_CONTROL_INP_MASK 0x40000000 71 72 #define SLIPORT_ERROR_NO_RESOURCE1 0x2 73 #define SLIPORT_ERROR_NO_RESOURCE2 0x9 74 75 #define SLIPORT_ERROR_FW_RESET1 0x2 76 #define SLIPORT_ERROR_FW_RESET2 0x0 77 78 /********* Memory BAR register ************/ 79 #define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET 0xfc 80 /* Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt 81 * Disable" may still globally block interrupts in addition to individual 82 * interrupt masks; a mechanism for the device driver to block all interrupts 83 * atomically without having to arbitrate for the PCI Interrupt Disable bit 84 * with the OS. 85 */ 86 #define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK BIT(29) /* bit 29 */ 87 88 /********* PCI Function Capability *********/ 89 #define BE_FUNCTION_CAPS_RSS 0x2 90 #define BE_FUNCTION_CAPS_SUPER_NIC 0x40 91 92 /********* Power management (WOL) **********/ 93 #define PCICFG_PM_CONTROL_OFFSET 0x44 94 #define PCICFG_PM_CONTROL_MASK 0x108 /* bits 3 & 8 */ 95 96 /********* Online Control Registers *******/ 97 #define PCICFG_ONLINE0 0xB0 98 #define PCICFG_ONLINE1 0xB4 99 100 /********* UE Status and Mask Registers ***/ 101 #define PCICFG_UE_STATUS_LOW 0xA0 102 #define PCICFG_UE_STATUS_HIGH 0xA4 103 #define PCICFG_UE_STATUS_LOW_MASK 0xA8 104 #define PCICFG_UE_STATUS_HI_MASK 0xAC 105 106 /******** SLI_INTF ***********************/ 107 #define SLI_INTF_REG_OFFSET 0x58 108 #define SLI_INTF_VALID_MASK 0xE0000000 109 #define SLI_INTF_VALID 0xC0000000 110 #define SLI_INTF_HINT2_MASK 0x1F000000 111 #define SLI_INTF_HINT2_SHIFT 24 112 #define SLI_INTF_HINT1_MASK 0x00FF0000 113 #define SLI_INTF_HINT1_SHIFT 16 114 #define SLI_INTF_FAMILY_MASK 0x00000F00 115 #define SLI_INTF_FAMILY_SHIFT 8 116 #define SLI_INTF_IF_TYPE_MASK 0x0000F000 117 #define SLI_INTF_IF_TYPE_SHIFT 12 118 #define SLI_INTF_REV_MASK 0x000000F0 119 #define SLI_INTF_REV_SHIFT 4 120 #define SLI_INTF_FT_MASK 0x00000001 121 122 #define SLI_INTF_TYPE_2 2 123 #define SLI_INTF_TYPE_3 3 124 125 /********* ISR0 Register offset **********/ 126 #define CEV_ISR0_OFFSET 0xC18 127 #define CEV_ISR_SIZE 4 128 129 /********* Event Q door bell *************/ 130 #define DB_EQ_OFFSET DB_CQ_OFFSET 131 #define DB_EQ_RING_ID_MASK 0x1FF /* bits 0 - 8 */ 132 #define DB_EQ_RING_ID_EXT_MASK 0x3e00 /* bits 9-13 */ 133 #define DB_EQ_RING_ID_EXT_MASK_SHIFT (2) /* qid bits 9-13 placing at 11-15 */ 134 135 /* Clear the interrupt for this eq */ 136 #define DB_EQ_CLR_SHIFT (9) /* bit 9 */ 137 /* Must be 1 */ 138 #define DB_EQ_EVNT_SHIFT (10) /* bit 10 */ 139 /* Number of event entries processed */ 140 #define DB_EQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */ 141 /* Rearm bit */ 142 #define DB_EQ_REARM_SHIFT (29) /* bit 29 */ 143 /* Rearm to interrupt delay encoding */ 144 #define DB_EQ_R2I_DLY_SHIFT (30) /* bits 30 - 31 */ 145 146 /* Rearm to interrupt (R2I) delay multiplier encoding represents 3 different 147 * values configured in CEV_REARM2IRPT_DLY_MULT_CSR register. This value is 148 * programmed by host driver while ringing an EQ doorbell(EQ_DB) if a delay 149 * between rearming the EQ and next interrupt on this EQ is desired. 150 */ 151 #define R2I_DLY_ENC_0 0 /* No delay */ 152 #define R2I_DLY_ENC_1 1 /* maps to 160us EQ delay */ 153 #define R2I_DLY_ENC_2 2 /* maps to 96us EQ delay */ 154 #define R2I_DLY_ENC_3 3 /* maps to 48us EQ delay */ 155 156 /********* Compl Q door bell *************/ 157 #define DB_CQ_OFFSET 0x120 158 #define DB_CQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */ 159 #define DB_CQ_RING_ID_EXT_MASK 0x7C00 /* bits 10-14 */ 160 #define DB_CQ_RING_ID_EXT_MASK_SHIFT (1) /* qid bits 10-14 161 placing at 11-15 */ 162 163 /* Number of event entries processed */ 164 #define DB_CQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */ 165 /* Rearm bit */ 166 #define DB_CQ_REARM_SHIFT (29) /* bit 29 */ 167 168 /********** TX ULP door bell *************/ 169 #define DB_TXULP1_OFFSET 0x60 170 #define DB_TXULP_RING_ID_MASK 0x7FF /* bits 0 - 10 */ 171 /* Number of tx entries posted */ 172 #define DB_TXULP_NUM_POSTED_SHIFT (16) /* bits 16 - 29 */ 173 #define DB_TXULP_NUM_POSTED_MASK 0x3FFF /* bits 16 - 29 */ 174 175 /********** RQ(erx) door bell ************/ 176 #define DB_RQ_OFFSET 0x100 177 #define DB_RQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */ 178 /* Number of rx frags posted */ 179 #define DB_RQ_NUM_POSTED_SHIFT (24) /* bits 24 - 31 */ 180 181 /********** MCC door bell ************/ 182 #define DB_MCCQ_OFFSET 0x140 183 #define DB_MCCQ_RING_ID_MASK 0x7FF /* bits 0 - 10 */ 184 /* Number of entries posted */ 185 #define DB_MCCQ_NUM_POSTED_SHIFT (16) /* bits 16 - 29 */ 186 187 /********** SRIOV VF PCICFG OFFSET ********/ 188 #define SRIOV_VF_PCICFG_OFFSET (4096) 189 190 /********** FAT TABLE ********/ 191 #define RETRIEVE_FAT 0 192 #define QUERY_FAT 1 193 194 /************* Rx Packet Type Encoding **************/ 195 #define BE_UNICAST_PACKET 0 196 #define BE_MULTICAST_PACKET 1 197 #define BE_BROADCAST_PACKET 2 198 #define BE_RSVD_PACKET 3 199 200 /* 201 * BE descriptors: host memory data structures whose formats 202 * are hardwired in BE silicon. 203 */ 204 /* Event Queue Descriptor */ 205 #define EQ_ENTRY_VALID_MASK 0x1 /* bit 0 */ 206 #define EQ_ENTRY_RES_ID_MASK 0xFFFF /* bits 16 - 31 */ 207 #define EQ_ENTRY_RES_ID_SHIFT 16 208 209 struct be_eq_entry { 210 u32 evt; 211 }; 212 213 /* TX Queue Descriptor */ 214 #define ETH_WRB_FRAG_LEN_MASK 0xFFFF 215 struct be_eth_wrb { 216 __le32 frag_pa_hi; /* dword 0 */ 217 __le32 frag_pa_lo; /* dword 1 */ 218 u32 rsvd0; /* dword 2 */ 219 __le32 frag_len; /* dword 3: bits 0 - 15 */ 220 } __packed; 221 222 /* Pseudo amap definition for eth_hdr_wrb in which each bit of the 223 * actual structure is defined as a byte : used to calculate 224 * offset/shift/mask of each field */ 225 struct amap_eth_hdr_wrb { 226 u8 rsvd0[32]; /* dword 0 */ 227 u8 rsvd1[32]; /* dword 1 */ 228 u8 complete; /* dword 2 */ 229 u8 event; 230 u8 crc; 231 u8 forward; 232 u8 lso6; 233 u8 mgmt; 234 u8 ipcs; 235 u8 udpcs; 236 u8 tcpcs; 237 u8 lso; 238 u8 vlan; 239 u8 gso[2]; 240 u8 num_wrb[5]; 241 u8 lso_mss[14]; 242 u8 len[16]; /* dword 3 */ 243 u8 vlan_tag[16]; 244 } __packed; 245 246 #define TX_HDR_WRB_COMPL 1 /* word 2 */ 247 #define TX_HDR_WRB_EVT BIT(1) /* word 2 */ 248 #define TX_HDR_WRB_NUM_SHIFT 13 /* word 2: bits 13:17 */ 249 #define TX_HDR_WRB_NUM_MASK 0x1F /* word 2: bits 13:17 */ 250 251 struct be_eth_hdr_wrb { 252 __le32 dw[4]; 253 }; 254 255 /********* Tx Compl Status Encoding *********/ 256 #define BE_TX_COMP_HDR_PARSE_ERR 0x2 257 #define BE_TX_COMP_NDMA_ERR 0x3 258 #define BE_TX_COMP_ACL_ERR 0x5 259 260 #define LANCER_TX_COMP_LSO_ERR 0x1 261 #define LANCER_TX_COMP_HSW_DROP_MAC_ERR 0x3 262 #define LANCER_TX_COMP_HSW_DROP_VLAN_ERR 0x5 263 #define LANCER_TX_COMP_QINQ_ERR 0x7 264 #define LANCER_TX_COMP_PARITY_ERR 0xb 265 #define LANCER_TX_COMP_DMA_ERR 0xd 266 267 /* TX Compl Queue Descriptor */ 268 269 /* Pseudo amap definition for eth_tx_compl in which each bit of the 270 * actual structure is defined as a byte: used to calculate 271 * offset/shift/mask of each field */ 272 struct amap_eth_tx_compl { 273 u8 wrb_index[16]; /* dword 0 */ 274 u8 ct[2]; /* dword 0 */ 275 u8 port[2]; /* dword 0 */ 276 u8 rsvd0[8]; /* dword 0 */ 277 u8 status[4]; /* dword 0 */ 278 u8 user_bytes[16]; /* dword 1 */ 279 u8 nwh_bytes[8]; /* dword 1 */ 280 u8 lso; /* dword 1 */ 281 u8 cast_enc[2]; /* dword 1 */ 282 u8 rsvd1[5]; /* dword 1 */ 283 u8 rsvd2[32]; /* dword 2 */ 284 u8 pkts[16]; /* dword 3 */ 285 u8 ringid[11]; /* dword 3 */ 286 u8 hash_val[4]; /* dword 3 */ 287 u8 valid; /* dword 3 */ 288 } __packed; 289 290 struct be_eth_tx_compl { 291 u32 dw[4]; 292 }; 293 294 /* RX Queue Descriptor */ 295 struct be_eth_rx_d { 296 u32 fragpa_hi; 297 u32 fragpa_lo; 298 }; 299 300 /* RX Compl Queue Descriptor */ 301 302 /* Pseudo amap definition for BE2 and BE3 legacy mode eth_rx_compl in which 303 * each bit of the actual structure is defined as a byte: used to calculate 304 * offset/shift/mask of each field */ 305 struct amap_eth_rx_compl_v0 { 306 u8 vlan_tag[16]; /* dword 0 */ 307 u8 pktsize[14]; /* dword 0 */ 308 u8 port; /* dword 0 */ 309 u8 ip_opt; /* dword 0 */ 310 u8 err; /* dword 1 */ 311 u8 rsshp; /* dword 1 */ 312 u8 ipf; /* dword 1 */ 313 u8 tcpf; /* dword 1 */ 314 u8 udpf; /* dword 1 */ 315 u8 ipcksm; /* dword 1 */ 316 u8 l4_cksm; /* dword 1 */ 317 u8 ip_version; /* dword 1 */ 318 u8 macdst[6]; /* dword 1 */ 319 u8 vtp; /* dword 1 */ 320 u8 ip_frag; /* dword 1 */ 321 u8 fragndx[10]; /* dword 1 */ 322 u8 ct[2]; /* dword 1 */ 323 u8 sw; /* dword 1 */ 324 u8 numfrags[3]; /* dword 1 */ 325 u8 rss_flush; /* dword 2 */ 326 u8 cast_enc[2]; /* dword 2 */ 327 u8 qnq; /* dword 2 */ 328 u8 rss_bank; /* dword 2 */ 329 u8 rsvd1[23]; /* dword 2 */ 330 u8 lro_pkt; /* dword 2 */ 331 u8 rsvd2[2]; /* dword 2 */ 332 u8 valid; /* dword 2 */ 333 u8 rsshash[32]; /* dword 3 */ 334 } __packed; 335 336 /* Pseudo amap definition for BE3 native mode eth_rx_compl in which 337 * each bit of the actual structure is defined as a byte: used to calculate 338 * offset/shift/mask of each field */ 339 struct amap_eth_rx_compl_v1 { 340 u8 vlan_tag[16]; /* dword 0 */ 341 u8 pktsize[14]; /* dword 0 */ 342 u8 vtp; /* dword 0 */ 343 u8 ip_opt; /* dword 0 */ 344 u8 err; /* dword 1 */ 345 u8 rsshp; /* dword 1 */ 346 u8 ipf; /* dword 1 */ 347 u8 tcpf; /* dword 1 */ 348 u8 udpf; /* dword 1 */ 349 u8 ipcksm; /* dword 1 */ 350 u8 l4_cksm; /* dword 1 */ 351 u8 ip_version; /* dword 1 */ 352 u8 macdst[7]; /* dword 1 */ 353 u8 rsvd0; /* dword 1 */ 354 u8 fragndx[10]; /* dword 1 */ 355 u8 ct[2]; /* dword 1 */ 356 u8 sw; /* dword 1 */ 357 u8 numfrags[3]; /* dword 1 */ 358 u8 rss_flush; /* dword 2 */ 359 u8 cast_enc[2]; /* dword 2 */ 360 u8 qnq; /* dword 2 */ 361 u8 rss_bank; /* dword 2 */ 362 u8 port[2]; /* dword 2 */ 363 u8 vntagp; /* dword 2 */ 364 u8 header_len[8]; /* dword 2 */ 365 u8 header_split[2]; /* dword 2 */ 366 u8 rsvd1[12]; /* dword 2 */ 367 u8 tunneled; 368 u8 valid; /* dword 2 */ 369 u8 rsshash[32]; /* dword 3 */ 370 } __packed; 371 372 struct be_eth_rx_compl { 373 u32 dw[4]; 374 }; 375