1 /*
2  * Copyright (C) 2005 - 2014 Emulex
3  * All rights reserved.
4  *
5  * This program is free software; you can redistribute it and/or
6  * modify it under the terms of the GNU General Public License version 2
7  * as published by the Free Software Foundation.  The full GNU General
8  * Public License is included in this distribution in the file called COPYING.
9  *
10  * Contact Information:
11  * linux-drivers@emulex.com
12  *
13  * Emulex
14  * 3333 Susan Street
15  * Costa Mesa, CA 92626
16  */
17 
18 /********* Mailbox door bell *************/
19 /* Used for driver communication with the FW.
20  * The software must write this register twice to post any command. First,
21  * it writes the register with hi=1 and the upper bits of the physical address
22  * for the MAILBOX structure. Software must poll the ready bit until this
23  * is acknowledged. Then, sotware writes the register with hi=0 with the lower
24  * bits in the address. It must poll the ready bit until the command is
25  * complete. Upon completion, the MAILBOX will contain a valid completion
26  * queue entry.
27  */
28 #define MPU_MAILBOX_DB_OFFSET	0x160
29 #define MPU_MAILBOX_DB_RDY_MASK	0x1 	/* bit 0 */
30 #define MPU_MAILBOX_DB_HI_MASK	0x2	/* bit 1 */
31 
32 #define MPU_EP_CONTROL 		0
33 
34 /********** MPU semphore: used for SH & BE  *************/
35 #define SLIPORT_SEMAPHORE_OFFSET_BEx		0xac  /* CSR BAR offset */
36 #define SLIPORT_SEMAPHORE_OFFSET_SH		0x94  /* PCI-CFG offset */
37 #define POST_STAGE_MASK				0x0000FFFF
38 #define POST_ERR_MASK				0x1
39 #define POST_ERR_SHIFT				31
40 
41 /* MPU semphore POST stage values */
42 #define POST_STAGE_AWAITING_HOST_RDY 	0x1 /* FW awaiting goahead from host */
43 #define POST_STAGE_HOST_RDY 		0x2 /* Host has given go-ahed to FW */
44 #define POST_STAGE_BE_RESET		0x3 /* Host wants to reset chip */
45 #define POST_STAGE_ARMFW_RDY		0xc000	/* FW is done with POST */
46 
47 
48 /* Lancer SLIPORT registers */
49 #define SLIPORT_STATUS_OFFSET		0x404
50 #define SLIPORT_CONTROL_OFFSET		0x408
51 #define SLIPORT_ERROR1_OFFSET		0x40C
52 #define SLIPORT_ERROR2_OFFSET		0x410
53 #define PHYSDEV_CONTROL_OFFSET		0x414
54 
55 #define SLIPORT_STATUS_ERR_MASK		0x80000000
56 #define SLIPORT_STATUS_DIP_MASK		0x02000000
57 #define SLIPORT_STATUS_RN_MASK		0x01000000
58 #define SLIPORT_STATUS_RDY_MASK		0x00800000
59 #define SLI_PORT_CONTROL_IP_MASK	0x08000000
60 #define PHYSDEV_CONTROL_FW_RESET_MASK	0x00000002
61 #define PHYSDEV_CONTROL_DD_MASK		0x00000004
62 #define PHYSDEV_CONTROL_INP_MASK	0x40000000
63 
64 #define SLIPORT_ERROR_NO_RESOURCE1	0x2
65 #define SLIPORT_ERROR_NO_RESOURCE2	0x9
66 
67 #define SLIPORT_ERROR_FW_RESET1		0x2
68 #define SLIPORT_ERROR_FW_RESET2		0x0
69 
70 /********* Memory BAR register ************/
71 #define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET 	0xfc
72 /* Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt
73  * Disable" may still globally block interrupts in addition to individual
74  * interrupt masks; a mechanism for the device driver to block all interrupts
75  * atomically without having to arbitrate for the PCI Interrupt Disable bit
76  * with the OS.
77  */
78 #define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK	(1 << 29) /* bit 29 */
79 
80 /********* PCI Function Capability *********/
81 #define BE_FUNCTION_CAPS_RSS			0x2
82 #define BE_FUNCTION_CAPS_SUPER_NIC		0x40
83 
84 /********* Power management (WOL) **********/
85 #define PCICFG_PM_CONTROL_OFFSET		0x44
86 #define PCICFG_PM_CONTROL_MASK			0x108	/* bits 3 & 8 */
87 
88 /********* Online Control Registers *******/
89 #define PCICFG_ONLINE0				0xB0
90 #define PCICFG_ONLINE1				0xB4
91 
92 /********* UE Status and Mask Registers ***/
93 #define PCICFG_UE_STATUS_LOW			0xA0
94 #define PCICFG_UE_STATUS_HIGH			0xA4
95 #define PCICFG_UE_STATUS_LOW_MASK		0xA8
96 #define PCICFG_UE_STATUS_HI_MASK		0xAC
97 
98 /******** SLI_INTF ***********************/
99 #define SLI_INTF_REG_OFFSET			0x58
100 #define SLI_INTF_VALID_MASK			0xE0000000
101 #define SLI_INTF_VALID				0xC0000000
102 #define SLI_INTF_HINT2_MASK			0x1F000000
103 #define SLI_INTF_HINT2_SHIFT			24
104 #define SLI_INTF_HINT1_MASK			0x00FF0000
105 #define SLI_INTF_HINT1_SHIFT			16
106 #define SLI_INTF_FAMILY_MASK			0x00000F00
107 #define SLI_INTF_FAMILY_SHIFT			8
108 #define SLI_INTF_IF_TYPE_MASK			0x0000F000
109 #define SLI_INTF_IF_TYPE_SHIFT			12
110 #define SLI_INTF_REV_MASK			0x000000F0
111 #define SLI_INTF_REV_SHIFT			4
112 #define SLI_INTF_FT_MASK			0x00000001
113 
114 #define SLI_INTF_TYPE_2		2
115 #define SLI_INTF_TYPE_3		3
116 
117 /********* ISR0 Register offset **********/
118 #define CEV_ISR0_OFFSET 			0xC18
119 #define CEV_ISR_SIZE				4
120 
121 /********* Event Q door bell *************/
122 #define DB_EQ_OFFSET			DB_CQ_OFFSET
123 #define DB_EQ_RING_ID_MASK		0x1FF	/* bits 0 - 8 */
124 #define DB_EQ_RING_ID_EXT_MASK		0x3e00  /* bits 9-13 */
125 #define DB_EQ_RING_ID_EXT_MASK_SHIFT	(2) /* qid bits 9-13 placing at 11-15 */
126 
127 /* Clear the interrupt for this eq */
128 #define DB_EQ_CLR_SHIFT			(9)	/* bit 9 */
129 /* Must be 1 */
130 #define DB_EQ_EVNT_SHIFT		(10)	/* bit 10 */
131 /* Number of event entries processed */
132 #define DB_EQ_NUM_POPPED_SHIFT		(16)	/* bits 16 - 28 */
133 /* Rearm bit */
134 #define DB_EQ_REARM_SHIFT		(29)	/* bit 29 */
135 
136 /********* Compl Q door bell *************/
137 #define DB_CQ_OFFSET 			0x120
138 #define DB_CQ_RING_ID_MASK		0x3FF	/* bits 0 - 9 */
139 #define DB_CQ_RING_ID_EXT_MASK		0x7C00	/* bits 10-14 */
140 #define DB_CQ_RING_ID_EXT_MASK_SHIFT	(1)	/* qid bits 10-14
141 						 placing at 11-15 */
142 
143 /* Number of event entries processed */
144 #define DB_CQ_NUM_POPPED_SHIFT		(16) 	/* bits 16 - 28 */
145 /* Rearm bit */
146 #define DB_CQ_REARM_SHIFT		(29) 	/* bit 29 */
147 
148 /********** TX ULP door bell *************/
149 #define DB_TXULP1_OFFSET		0x60
150 #define DB_TXULP_RING_ID_MASK		0x7FF	/* bits 0 - 10 */
151 /* Number of tx entries posted */
152 #define DB_TXULP_NUM_POSTED_SHIFT	(16)	/* bits 16 - 29 */
153 #define DB_TXULP_NUM_POSTED_MASK	0x3FFF	/* bits 16 - 29 */
154 
155 /********** RQ(erx) door bell ************/
156 #define DB_RQ_OFFSET 			0x100
157 #define DB_RQ_RING_ID_MASK		0x3FF	/* bits 0 - 9 */
158 /* Number of rx frags posted */
159 #define DB_RQ_NUM_POSTED_SHIFT		(24)	/* bits 24 - 31 */
160 
161 /********** MCC door bell ************/
162 #define DB_MCCQ_OFFSET 			0x140
163 #define DB_MCCQ_RING_ID_MASK		0x7FF	/* bits 0 - 10 */
164 /* Number of entries posted */
165 #define DB_MCCQ_NUM_POSTED_SHIFT	(16)	/* bits 16 - 29 */
166 
167 /********** SRIOV VF PCICFG OFFSET ********/
168 #define SRIOV_VF_PCICFG_OFFSET		(4096)
169 
170 /********** FAT TABLE  ********/
171 #define RETRIEVE_FAT	0
172 #define QUERY_FAT	1
173 
174 /* Flashrom related descriptors */
175 #define MAX_FLASH_COMP			32
176 #define IMAGE_TYPE_FIRMWARE		160
177 #define IMAGE_TYPE_BOOTCODE		224
178 #define IMAGE_TYPE_OPTIONROM		32
179 
180 #define NUM_FLASHDIR_ENTRIES		32
181 
182 #define OPTYPE_ISCSI_ACTIVE		0
183 #define OPTYPE_REDBOOT			1
184 #define OPTYPE_BIOS			2
185 #define OPTYPE_PXE_BIOS			3
186 #define OPTYPE_FCOE_BIOS		8
187 #define OPTYPE_ISCSI_BACKUP		9
188 #define OPTYPE_FCOE_FW_ACTIVE		10
189 #define OPTYPE_FCOE_FW_BACKUP		11
190 #define OPTYPE_NCSI_FW			13
191 #define OPTYPE_PHY_FW			99
192 #define TN_8022				13
193 
194 #define ILLEGAL_IOCTL_REQ		2
195 #define FLASHROM_OPER_PHY_FLASH		9
196 #define FLASHROM_OPER_PHY_SAVE		10
197 #define FLASHROM_OPER_FLASH		1
198 #define FLASHROM_OPER_SAVE		2
199 #define FLASHROM_OPER_REPORT		4
200 
201 #define FLASH_IMAGE_MAX_SIZE_g2		(1310720) /* Max firmware image size */
202 #define FLASH_BIOS_IMAGE_MAX_SIZE_g2	(262144)  /* Max OPTION ROM image sz */
203 #define FLASH_REDBOOT_IMAGE_MAX_SIZE_g2	(262144)  /* Max Redboot image sz    */
204 #define FLASH_IMAGE_MAX_SIZE_g3		(2097152) /* Max firmware image size */
205 #define FLASH_BIOS_IMAGE_MAX_SIZE_g3	(524288)  /* Max OPTION ROM image sz */
206 #define FLASH_REDBOOT_IMAGE_MAX_SIZE_g3	(1048576)  /* Max Redboot image sz    */
207 #define FLASH_NCSI_IMAGE_MAX_SIZE_g3	(262144)
208 #define FLASH_PHY_FW_IMAGE_MAX_SIZE_g3	262144
209 
210 #define FLASH_NCSI_MAGIC		(0x16032009)
211 #define FLASH_NCSI_DISABLED		(0)
212 #define FLASH_NCSI_ENABLED		(1)
213 
214 #define FLASH_NCSI_BITFILE_HDR_OFFSET	(0x600000)
215 
216 /* Offsets for components on Flash. */
217 #define FLASH_iSCSI_PRIMARY_IMAGE_START_g2 (1048576)
218 #define FLASH_iSCSI_BACKUP_IMAGE_START_g2  (2359296)
219 #define FLASH_FCoE_PRIMARY_IMAGE_START_g2  (3670016)
220 #define FLASH_FCoE_BACKUP_IMAGE_START_g2   (4980736)
221 #define FLASH_iSCSI_BIOS_START_g2          (7340032)
222 #define FLASH_PXE_BIOS_START_g2            (7864320)
223 #define FLASH_FCoE_BIOS_START_g2           (524288)
224 #define FLASH_REDBOOT_START_g2		  (0)
225 
226 #define FLASH_NCSI_START_g3		   (15990784)
227 #define FLASH_iSCSI_PRIMARY_IMAGE_START_g3 (2097152)
228 #define FLASH_iSCSI_BACKUP_IMAGE_START_g3  (4194304)
229 #define FLASH_FCoE_PRIMARY_IMAGE_START_g3  (6291456)
230 #define FLASH_FCoE_BACKUP_IMAGE_START_g3   (8388608)
231 #define FLASH_iSCSI_BIOS_START_g3          (12582912)
232 #define FLASH_PXE_BIOS_START_g3            (13107200)
233 #define FLASH_FCoE_BIOS_START_g3           (13631488)
234 #define FLASH_REDBOOT_START_g3             (262144)
235 #define FLASH_PHY_FW_START_g3		   1310720
236 
237 #define IMAGE_NCSI			16
238 #define IMAGE_OPTION_ROM_PXE		32
239 #define IMAGE_OPTION_ROM_FCoE		33
240 #define IMAGE_OPTION_ROM_ISCSI		34
241 #define IMAGE_FLASHISM_JUMPVECTOR	48
242 #define IMAGE_FLASH_ISM			49
243 #define IMAGE_JUMP_VECTOR		50
244 #define IMAGE_FIRMWARE_iSCSI		160
245 #define IMAGE_FIRMWARE_COMP_iSCSI	161
246 #define IMAGE_FIRMWARE_FCoE		162
247 #define IMAGE_FIRMWARE_COMP_FCoE	163
248 #define IMAGE_FIRMWARE_BACKUP_iSCSI	176
249 #define IMAGE_FIRMWARE_BACKUP_COMP_iSCSI 177
250 #define IMAGE_FIRMWARE_BACKUP_FCoE	178
251 #define IMAGE_FIRMWARE_BACKUP_COMP_FCoE 179
252 #define IMAGE_FIRMWARE_PHY		192
253 #define IMAGE_BOOT_CODE			224
254 
255 /************* Rx Packet Type Encoding **************/
256 #define BE_UNICAST_PACKET		0
257 #define BE_MULTICAST_PACKET		1
258 #define BE_BROADCAST_PACKET		2
259 #define BE_RSVD_PACKET			3
260 
261 /*
262  * BE descriptors: host memory data structures whose formats
263  * are hardwired in BE silicon.
264  */
265 /* Event Queue Descriptor */
266 #define EQ_ENTRY_VALID_MASK 		0x1	/* bit 0 */
267 #define EQ_ENTRY_RES_ID_MASK 		0xFFFF	/* bits 16 - 31 */
268 #define EQ_ENTRY_RES_ID_SHIFT 		16
269 
270 struct be_eq_entry {
271 	u32 evt;
272 };
273 
274 /* TX Queue Descriptor */
275 #define ETH_WRB_FRAG_LEN_MASK		0xFFFF
276 struct be_eth_wrb {
277 	u32 frag_pa_hi;		/* dword 0 */
278 	u32 frag_pa_lo;		/* dword 1 */
279 	u32 rsvd0;		/* dword 2 */
280 	u32 frag_len;		/* dword 3: bits 0 - 15 */
281 } __packed;
282 
283 /* Pseudo amap definition for eth_hdr_wrb in which each bit of the
284  * actual structure is defined as a byte : used to calculate
285  * offset/shift/mask of each field */
286 struct amap_eth_hdr_wrb {
287 	u8 rsvd0[32];		/* dword 0 */
288 	u8 rsvd1[32];		/* dword 1 */
289 	u8 complete;		/* dword 2 */
290 	u8 event;
291 	u8 crc;
292 	u8 forward;
293 	u8 lso6;
294 	u8 mgmt;
295 	u8 ipcs;
296 	u8 udpcs;
297 	u8 tcpcs;
298 	u8 lso;
299 	u8 vlan;
300 	u8 gso[2];
301 	u8 num_wrb[5];
302 	u8 lso_mss[14];
303 	u8 len[16];		/* dword 3 */
304 	u8 vlan_tag[16];
305 } __packed;
306 
307 struct be_eth_hdr_wrb {
308 	u32 dw[4];
309 };
310 
311 /* TX Compl Queue Descriptor */
312 
313 /* Pseudo amap definition for eth_tx_compl in which each bit of the
314  * actual structure is defined as a byte: used to calculate
315  * offset/shift/mask of each field */
316 struct amap_eth_tx_compl {
317 	u8 wrb_index[16];	/* dword 0 */
318 	u8 ct[2]; 		/* dword 0 */
319 	u8 port[2];		/* dword 0 */
320 	u8 rsvd0[8];		/* dword 0 */
321 	u8 status[4];		/* dword 0 */
322 	u8 user_bytes[16];	/* dword 1 */
323 	u8 nwh_bytes[8];	/* dword 1 */
324 	u8 lso;			/* dword 1 */
325 	u8 cast_enc[2];		/* dword 1 */
326 	u8 rsvd1[5];		/* dword 1 */
327 	u8 rsvd2[32];		/* dword 2 */
328 	u8 pkts[16];		/* dword 3 */
329 	u8 ringid[11];		/* dword 3 */
330 	u8 hash_val[4];		/* dword 3 */
331 	u8 valid;		/* dword 3 */
332 } __packed;
333 
334 struct be_eth_tx_compl {
335 	u32 dw[4];
336 };
337 
338 /* RX Queue Descriptor */
339 struct be_eth_rx_d {
340 	u32 fragpa_hi;
341 	u32 fragpa_lo;
342 };
343 
344 /* RX Compl Queue Descriptor */
345 
346 /* Pseudo amap definition for BE2 and BE3 legacy mode eth_rx_compl in which
347  * each bit of the actual structure is defined as a byte: used to calculate
348  * offset/shift/mask of each field */
349 struct amap_eth_rx_compl_v0 {
350 	u8 vlan_tag[16];	/* dword 0 */
351 	u8 pktsize[14];		/* dword 0 */
352 	u8 port;		/* dword 0 */
353 	u8 ip_opt;		/* dword 0 */
354 	u8 err;			/* dword 1 */
355 	u8 rsshp;		/* dword 1 */
356 	u8 ipf;			/* dword 1 */
357 	u8 tcpf;		/* dword 1 */
358 	u8 udpf;		/* dword 1 */
359 	u8 ipcksm;		/* dword 1 */
360 	u8 l4_cksm;		/* dword 1 */
361 	u8 ip_version;		/* dword 1 */
362 	u8 macdst[6];		/* dword 1 */
363 	u8 vtp;			/* dword 1 */
364 	u8 ip_frag;		/* dword 1 */
365 	u8 fragndx[10];		/* dword 1 */
366 	u8 ct[2];		/* dword 1 */
367 	u8 sw;			/* dword 1 */
368 	u8 numfrags[3];		/* dword 1 */
369 	u8 rss_flush;		/* dword 2 */
370 	u8 cast_enc[2];		/* dword 2 */
371 	u8 qnq;			/* dword 2 */
372 	u8 rss_bank;		/* dword 2 */
373 	u8 rsvd1[23];		/* dword 2 */
374 	u8 lro_pkt;		/* dword 2 */
375 	u8 rsvd2[2];		/* dword 2 */
376 	u8 valid;		/* dword 2 */
377 	u8 rsshash[32];		/* dword 3 */
378 } __packed;
379 
380 /* Pseudo amap definition for BE3 native mode eth_rx_compl in which
381  * each bit of the actual structure is defined as a byte: used to calculate
382  * offset/shift/mask of each field */
383 struct amap_eth_rx_compl_v1 {
384 	u8 vlan_tag[16];	/* dword 0 */
385 	u8 pktsize[14];		/* dword 0 */
386 	u8 vtp;			/* dword 0 */
387 	u8 ip_opt;		/* dword 0 */
388 	u8 err;			/* dword 1 */
389 	u8 rsshp;		/* dword 1 */
390 	u8 ipf;			/* dword 1 */
391 	u8 tcpf;		/* dword 1 */
392 	u8 udpf;		/* dword 1 */
393 	u8 ipcksm;		/* dword 1 */
394 	u8 l4_cksm;		/* dword 1 */
395 	u8 ip_version;		/* dword 1 */
396 	u8 macdst[7];		/* dword 1 */
397 	u8 rsvd0;		/* dword 1 */
398 	u8 fragndx[10];		/* dword 1 */
399 	u8 ct[2];		/* dword 1 */
400 	u8 sw;			/* dword 1 */
401 	u8 numfrags[3];		/* dword 1 */
402 	u8 rss_flush;		/* dword 2 */
403 	u8 cast_enc[2];		/* dword 2 */
404 	u8 qnq;			/* dword 2 */
405 	u8 rss_bank;		/* dword 2 */
406 	u8 port[2];		/* dword 2 */
407 	u8 vntagp;		/* dword 2 */
408 	u8 header_len[8];	/* dword 2 */
409 	u8 header_split[2];	/* dword 2 */
410 	u8 rsvd1[12];		/* dword 2 */
411 	u8 tunneled;
412 	u8 valid;		/* dword 2 */
413 	u8 rsshash[32];		/* dword 3 */
414 } __packed;
415 
416 struct be_eth_rx_compl {
417 	u32 dw[4];
418 };
419 
420 struct mgmt_hba_attribs {
421 	u8 flashrom_version_string[32];
422 	u8 manufacturer_name[32];
423 	u32 supported_modes;
424 	u32 rsvd0[3];
425 	u8 ncsi_ver_string[12];
426 	u32 default_extended_timeout;
427 	u8 controller_model_number[32];
428 	u8 controller_description[64];
429 	u8 controller_serial_number[32];
430 	u8 ip_version_string[32];
431 	u8 firmware_version_string[32];
432 	u8 bios_version_string[32];
433 	u8 redboot_version_string[32];
434 	u8 driver_version_string[32];
435 	u8 fw_on_flash_version_string[32];
436 	u32 functionalities_supported;
437 	u16 max_cdblength;
438 	u8 asic_revision;
439 	u8 generational_guid[16];
440 	u8 hba_port_count;
441 	u16 default_link_down_timeout;
442 	u8 iscsi_ver_min_max;
443 	u8 multifunction_device;
444 	u8 cache_valid;
445 	u8 hba_status;
446 	u8 max_domains_supported;
447 	u8 phy_port;
448 	u32 firmware_post_status;
449 	u32 hba_mtu[8];
450 	u32 rsvd1[4];
451 };
452 
453 struct mgmt_controller_attrib {
454 	struct mgmt_hba_attribs hba_attribs;
455 	u16 pci_vendor_id;
456 	u16 pci_device_id;
457 	u16 pci_sub_vendor_id;
458 	u16 pci_sub_system_id;
459 	u8 pci_bus_number;
460 	u8 pci_device_number;
461 	u8 pci_function_number;
462 	u8 interface_type;
463 	u64 unique_identifier;
464 	u32 rsvd0[5];
465 };
466 
467 struct controller_id {
468 	u32 vendor;
469 	u32 device;
470 	u32 subvendor;
471 	u32 subdevice;
472 };
473 
474 struct flash_comp {
475 	unsigned long offset;
476 	int optype;
477 	int size;
478 	int img_type;
479 };
480 
481 struct image_hdr {
482 	u32 imageid;
483 	u32 imageoffset;
484 	u32 imagelength;
485 	u32 image_checksum;
486 	u8 image_version[32];
487 };
488 struct flash_file_hdr_g2 {
489 	u8 sign[32];
490 	u32 cksum;
491 	u32 antidote;
492 	struct controller_id cont_id;
493 	u32 file_len;
494 	u32 chunk_num;
495 	u32 total_chunks;
496 	u32 num_imgs;
497 	u8 build[24];
498 };
499 
500 struct flash_file_hdr_g3 {
501 	u8 sign[52];
502 	u8 ufi_version[4];
503 	u32 file_len;
504 	u32 cksum;
505 	u32 antidote;
506 	u32 num_imgs;
507 	u8 build[24];
508 	u8 asic_type_rev;
509 	u8 rsvd[31];
510 };
511 
512 struct flash_section_hdr {
513 	u32 format_rev;
514 	u32 cksum;
515 	u32 antidote;
516 	u32 num_images;
517 	u8 id_string[128];
518 	u32 rsvd[4];
519 } __packed;
520 
521 struct flash_section_hdr_g2 {
522 	u32 format_rev;
523 	u32 cksum;
524 	u32 antidote;
525 	u32 build_num;
526 	u8 id_string[128];
527 	u32 rsvd[8];
528 } __packed;
529 
530 struct flash_section_entry {
531 	u32 type;
532 	u32 offset;
533 	u32 pad_size;
534 	u32 image_size;
535 	u32 cksum;
536 	u32 entry_point;
537 	u32 rsvd0;
538 	u32 rsvd1;
539 	u8 ver_data[32];
540 } __packed;
541 
542 struct flash_section_info {
543 	u8 cookie[32];
544 	struct flash_section_hdr fsec_hdr;
545 	struct flash_section_entry fsec_entry[32];
546 } __packed;
547 
548 struct flash_section_info_g2 {
549 	u8 cookie[32];
550 	struct flash_section_hdr_g2 fsec_hdr;
551 	struct flash_section_entry fsec_entry[32];
552 } __packed;
553