1 /* 2 * Copyright (C) 2005 - 2015 Emulex 3 * All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License version 2 7 * as published by the Free Software Foundation. The full GNU General 8 * Public License is included in this distribution in the file called COPYING. 9 * 10 * Contact Information: 11 * linux-drivers@emulex.com 12 * 13 * Emulex 14 * 3333 Susan Street 15 * Costa Mesa, CA 92626 16 */ 17 18 /* 19 * The driver sends configuration and managements command requests to the 20 * firmware in the BE. These requests are communicated to the processor 21 * using Work Request Blocks (WRBs) submitted to the MCC-WRB ring or via one 22 * WRB inside a MAILBOX. 23 * The commands are serviced by the ARM processor in the BladeEngine's MPU. 24 */ 25 26 struct be_sge { 27 u32 pa_lo; 28 u32 pa_hi; 29 u32 len; 30 }; 31 32 #define MCC_WRB_EMBEDDED_MASK 1 /* bit 0 of dword 0*/ 33 #define MCC_WRB_SGE_CNT_SHIFT 3 /* bits 3 - 7 of dword 0 */ 34 #define MCC_WRB_SGE_CNT_MASK 0x1F /* bits 3 - 7 of dword 0 */ 35 struct be_mcc_wrb { 36 u32 embedded; /* dword 0 */ 37 u32 payload_length; /* dword 1 */ 38 u32 tag0; /* dword 2 */ 39 u32 tag1; /* dword 3 */ 40 u32 rsvd; /* dword 4 */ 41 union { 42 u8 embedded_payload[236]; /* used by embedded cmds */ 43 struct be_sge sgl[19]; /* used by non-embedded cmds */ 44 } payload; 45 }; 46 47 #define CQE_FLAGS_VALID_MASK BIT(31) 48 #define CQE_FLAGS_ASYNC_MASK BIT(30) 49 #define CQE_FLAGS_COMPLETED_MASK BIT(28) 50 #define CQE_FLAGS_CONSUMED_MASK BIT(27) 51 52 /* Completion Status */ 53 enum mcc_base_status { 54 MCC_STATUS_SUCCESS = 0, 55 MCC_STATUS_FAILED = 1, 56 MCC_STATUS_ILLEGAL_REQUEST = 2, 57 MCC_STATUS_ILLEGAL_FIELD = 3, 58 MCC_STATUS_INSUFFICIENT_BUFFER = 4, 59 MCC_STATUS_UNAUTHORIZED_REQUEST = 5, 60 MCC_STATUS_NOT_SUPPORTED = 66, 61 MCC_STATUS_FEATURE_NOT_SUPPORTED = 68 62 }; 63 64 /* Additional status */ 65 enum mcc_addl_status { 66 MCC_ADDL_STATUS_INSUFFICIENT_RESOURCES = 0x16, 67 MCC_ADDL_STATUS_FLASH_IMAGE_CRC_MISMATCH = 0x4d, 68 MCC_ADDL_STATUS_TOO_MANY_INTERFACES = 0x4a, 69 MCC_ADDL_STATUS_INSUFFICIENT_VLANS = 0xab 70 }; 71 72 #define CQE_BASE_STATUS_MASK 0xFFFF 73 #define CQE_BASE_STATUS_SHIFT 0 /* bits 0 - 15 */ 74 #define CQE_ADDL_STATUS_MASK 0xFF 75 #define CQE_ADDL_STATUS_SHIFT 16 /* bits 16 - 31 */ 76 77 #define base_status(status) \ 78 ((enum mcc_base_status) \ 79 (status > 0 ? (status & CQE_BASE_STATUS_MASK) : 0)) 80 #define addl_status(status) \ 81 ((enum mcc_addl_status) \ 82 (status > 0 ? (status >> CQE_ADDL_STATUS_SHIFT) & \ 83 CQE_ADDL_STATUS_MASK : 0)) 84 85 struct be_mcc_compl { 86 u32 status; /* dword 0 */ 87 u32 tag0; /* dword 1 */ 88 u32 tag1; /* dword 2 */ 89 u32 flags; /* dword 3 */ 90 }; 91 92 /* When the async bit of mcc_compl flags is set, flags 93 * is interpreted as follows: 94 */ 95 #define ASYNC_EVENT_CODE_SHIFT 8 /* bits 8 - 15 */ 96 #define ASYNC_EVENT_CODE_MASK 0xFF 97 #define ASYNC_EVENT_TYPE_SHIFT 16 98 #define ASYNC_EVENT_TYPE_MASK 0xFF 99 #define ASYNC_EVENT_CODE_LINK_STATE 0x1 100 #define ASYNC_EVENT_CODE_GRP_5 0x5 101 #define ASYNC_EVENT_QOS_SPEED 0x1 102 #define ASYNC_EVENT_COS_PRIORITY 0x2 103 #define ASYNC_EVENT_PVID_STATE 0x3 104 #define ASYNC_EVENT_CODE_QNQ 0x6 105 #define ASYNC_DEBUG_EVENT_TYPE_QNQ 1 106 #define ASYNC_EVENT_CODE_SLIPORT 0x11 107 #define ASYNC_EVENT_PORT_MISCONFIG 0x9 108 #define ASYNC_EVENT_FW_CONTROL 0x5 109 110 enum { 111 LINK_DOWN = 0x0, 112 LINK_UP = 0x1 113 }; 114 #define LINK_STATUS_MASK 0x1 115 #define LOGICAL_LINK_STATUS_MASK 0x2 116 117 /* When the event code of compl->flags is link-state, the mcc_compl 118 * must be interpreted as follows 119 */ 120 struct be_async_event_link_state { 121 u8 physical_port; 122 u8 port_link_status; 123 u8 port_duplex; 124 u8 port_speed; 125 u8 port_fault; 126 u8 rsvd0[7]; 127 u32 flags; 128 } __packed; 129 130 /* When the event code of compl->flags is GRP-5 and event_type is QOS_SPEED 131 * the mcc_compl must be interpreted as follows 132 */ 133 struct be_async_event_grp5_qos_link_speed { 134 u8 physical_port; 135 u8 rsvd[5]; 136 u16 qos_link_speed; 137 u32 event_tag; 138 u32 flags; 139 } __packed; 140 141 /* When the event code of compl->flags is GRP5 and event type is 142 * CoS-Priority, the mcc_compl must be interpreted as follows 143 */ 144 struct be_async_event_grp5_cos_priority { 145 u8 physical_port; 146 u8 available_priority_bmap; 147 u8 reco_default_priority; 148 u8 valid; 149 u8 rsvd0; 150 u8 event_tag; 151 u32 flags; 152 } __packed; 153 154 /* When the event code of compl->flags is GRP5 and event type is 155 * PVID state, the mcc_compl must be interpreted as follows 156 */ 157 struct be_async_event_grp5_pvid_state { 158 u8 enabled; 159 u8 rsvd0; 160 u16 tag; 161 u32 event_tag; 162 u32 rsvd1; 163 u32 flags; 164 } __packed; 165 166 /* async event indicating outer VLAN tag in QnQ */ 167 struct be_async_event_qnq { 168 u8 valid; /* Indicates if outer VLAN is valid */ 169 u8 rsvd0; 170 u16 vlan_tag; 171 u32 event_tag; 172 u8 rsvd1[4]; 173 u32 flags; 174 } __packed; 175 176 #define INCOMPATIBLE_SFP 0x3 177 /* async event indicating misconfigured port */ 178 struct be_async_event_misconfig_port { 179 u32 event_data_word1; 180 u32 event_data_word2; 181 u32 rsvd0; 182 u32 flags; 183 } __packed; 184 185 #define BMC_FILT_BROADCAST_ARP BIT(0) 186 #define BMC_FILT_BROADCAST_DHCP_CLIENT BIT(1) 187 #define BMC_FILT_BROADCAST_DHCP_SERVER BIT(2) 188 #define BMC_FILT_BROADCAST_NET_BIOS BIT(3) 189 #define BMC_FILT_BROADCAST BIT(7) 190 #define BMC_FILT_MULTICAST_IPV6_NEIGH_ADVER BIT(8) 191 #define BMC_FILT_MULTICAST_IPV6_RA BIT(9) 192 #define BMC_FILT_MULTICAST_IPV6_RAS BIT(10) 193 #define BMC_FILT_MULTICAST BIT(15) 194 struct be_async_fw_control { 195 u32 event_data_word1; 196 u32 event_data_word2; 197 u32 evt_tag; 198 u32 event_data_word4; 199 } __packed; 200 201 struct be_mcc_mailbox { 202 struct be_mcc_wrb wrb; 203 struct be_mcc_compl compl; 204 }; 205 206 #define CMD_SUBSYSTEM_COMMON 0x1 207 #define CMD_SUBSYSTEM_ETH 0x3 208 #define CMD_SUBSYSTEM_LOWLEVEL 0xb 209 210 #define OPCODE_COMMON_NTWK_MAC_QUERY 1 211 #define OPCODE_COMMON_NTWK_MAC_SET 2 212 #define OPCODE_COMMON_NTWK_MULTICAST_SET 3 213 #define OPCODE_COMMON_NTWK_VLAN_CONFIG 4 214 #define OPCODE_COMMON_NTWK_LINK_STATUS_QUERY 5 215 #define OPCODE_COMMON_READ_FLASHROM 6 216 #define OPCODE_COMMON_WRITE_FLASHROM 7 217 #define OPCODE_COMMON_CQ_CREATE 12 218 #define OPCODE_COMMON_EQ_CREATE 13 219 #define OPCODE_COMMON_MCC_CREATE 21 220 #define OPCODE_COMMON_SET_QOS 28 221 #define OPCODE_COMMON_MCC_CREATE_EXT 90 222 #define OPCODE_COMMON_SEEPROM_READ 30 223 #define OPCODE_COMMON_GET_CNTL_ATTRIBUTES 32 224 #define OPCODE_COMMON_NTWK_RX_FILTER 34 225 #define OPCODE_COMMON_GET_FW_VERSION 35 226 #define OPCODE_COMMON_SET_FLOW_CONTROL 36 227 #define OPCODE_COMMON_GET_FLOW_CONTROL 37 228 #define OPCODE_COMMON_SET_FRAME_SIZE 39 229 #define OPCODE_COMMON_MODIFY_EQ_DELAY 41 230 #define OPCODE_COMMON_FIRMWARE_CONFIG 42 231 #define OPCODE_COMMON_NTWK_INTERFACE_CREATE 50 232 #define OPCODE_COMMON_NTWK_INTERFACE_DESTROY 51 233 #define OPCODE_COMMON_MCC_DESTROY 53 234 #define OPCODE_COMMON_CQ_DESTROY 54 235 #define OPCODE_COMMON_EQ_DESTROY 55 236 #define OPCODE_COMMON_QUERY_FIRMWARE_CONFIG 58 237 #define OPCODE_COMMON_NTWK_PMAC_ADD 59 238 #define OPCODE_COMMON_NTWK_PMAC_DEL 60 239 #define OPCODE_COMMON_FUNCTION_RESET 61 240 #define OPCODE_COMMON_MANAGE_FAT 68 241 #define OPCODE_COMMON_ENABLE_DISABLE_BEACON 69 242 #define OPCODE_COMMON_GET_BEACON_STATE 70 243 #define OPCODE_COMMON_READ_TRANSRECV_DATA 73 244 #define OPCODE_COMMON_GET_PORT_NAME 77 245 #define OPCODE_COMMON_SET_LOGICAL_LINK_CONFIG 80 246 #define OPCODE_COMMON_SET_INTERRUPT_ENABLE 89 247 #define OPCODE_COMMON_SET_FN_PRIVILEGES 100 248 #define OPCODE_COMMON_GET_PHY_DETAILS 102 249 #define OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP 103 250 #define OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES 121 251 #define OPCODE_COMMON_GET_EXT_FAT_CAPABILITES 125 252 #define OPCODE_COMMON_SET_EXT_FAT_CAPABILITES 126 253 #define OPCODE_COMMON_GET_MAC_LIST 147 254 #define OPCODE_COMMON_SET_MAC_LIST 148 255 #define OPCODE_COMMON_GET_HSW_CONFIG 152 256 #define OPCODE_COMMON_GET_FUNC_CONFIG 160 257 #define OPCODE_COMMON_GET_PROFILE_CONFIG 164 258 #define OPCODE_COMMON_SET_PROFILE_CONFIG 165 259 #define OPCODE_COMMON_GET_ACTIVE_PROFILE 167 260 #define OPCODE_COMMON_SET_HSW_CONFIG 153 261 #define OPCODE_COMMON_GET_FN_PRIVILEGES 170 262 #define OPCODE_COMMON_READ_OBJECT 171 263 #define OPCODE_COMMON_WRITE_OBJECT 172 264 #define OPCODE_COMMON_DELETE_OBJECT 174 265 #define OPCODE_COMMON_MANAGE_IFACE_FILTERS 193 266 #define OPCODE_COMMON_GET_IFACE_LIST 194 267 #define OPCODE_COMMON_ENABLE_DISABLE_VF 196 268 269 #define OPCODE_ETH_RSS_CONFIG 1 270 #define OPCODE_ETH_ACPI_CONFIG 2 271 #define OPCODE_ETH_PROMISCUOUS 3 272 #define OPCODE_ETH_GET_STATISTICS 4 273 #define OPCODE_ETH_TX_CREATE 7 274 #define OPCODE_ETH_RX_CREATE 8 275 #define OPCODE_ETH_TX_DESTROY 9 276 #define OPCODE_ETH_RX_DESTROY 10 277 #define OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG 12 278 #define OPCODE_ETH_GET_PPORT_STATS 18 279 280 #define OPCODE_LOWLEVEL_HOST_DDR_DMA 17 281 #define OPCODE_LOWLEVEL_LOOPBACK_TEST 18 282 #define OPCODE_LOWLEVEL_SET_LOOPBACK_MODE 19 283 284 struct be_cmd_req_hdr { 285 u8 opcode; /* dword 0 */ 286 u8 subsystem; /* dword 0 */ 287 u8 port_number; /* dword 0 */ 288 u8 domain; /* dword 0 */ 289 u32 timeout; /* dword 1 */ 290 u32 request_length; /* dword 2 */ 291 u8 version; /* dword 3 */ 292 u8 rsvd1; /* dword 3 */ 293 u8 pf_num; /* dword 3 */ 294 u8 rsvd2; /* dword 3 */ 295 }; 296 297 #define RESP_HDR_INFO_OPCODE_SHIFT 0 /* bits 0 - 7 */ 298 #define RESP_HDR_INFO_SUBSYS_SHIFT 8 /* bits 8 - 15 */ 299 struct be_cmd_resp_hdr { 300 u8 opcode; /* dword 0 */ 301 u8 subsystem; /* dword 0 */ 302 u8 rsvd[2]; /* dword 0 */ 303 u8 base_status; /* dword 1 */ 304 u8 addl_status; /* dword 1 */ 305 u8 rsvd1[2]; /* dword 1 */ 306 u32 response_length; /* dword 2 */ 307 u32 actual_resp_len; /* dword 3 */ 308 }; 309 310 struct phys_addr { 311 u32 lo; 312 u32 hi; 313 }; 314 315 /************************** 316 * BE Command definitions * 317 **************************/ 318 319 /* Pseudo amap definition in which each bit of the actual structure is defined 320 * as a byte: used to calculate offset/shift/mask of each field */ 321 struct amap_eq_context { 322 u8 cidx[13]; /* dword 0*/ 323 u8 rsvd0[3]; /* dword 0*/ 324 u8 epidx[13]; /* dword 0*/ 325 u8 valid; /* dword 0*/ 326 u8 rsvd1; /* dword 0*/ 327 u8 size; /* dword 0*/ 328 u8 pidx[13]; /* dword 1*/ 329 u8 rsvd2[3]; /* dword 1*/ 330 u8 pd[10]; /* dword 1*/ 331 u8 count[3]; /* dword 1*/ 332 u8 solevent; /* dword 1*/ 333 u8 stalled; /* dword 1*/ 334 u8 armed; /* dword 1*/ 335 u8 rsvd3[4]; /* dword 2*/ 336 u8 func[8]; /* dword 2*/ 337 u8 rsvd4; /* dword 2*/ 338 u8 delaymult[10]; /* dword 2*/ 339 u8 rsvd5[2]; /* dword 2*/ 340 u8 phase[2]; /* dword 2*/ 341 u8 nodelay; /* dword 2*/ 342 u8 rsvd6[4]; /* dword 2*/ 343 u8 rsvd7[32]; /* dword 3*/ 344 } __packed; 345 346 struct be_cmd_req_eq_create { 347 struct be_cmd_req_hdr hdr; 348 u16 num_pages; /* sword */ 349 u16 rsvd0; /* sword */ 350 u8 context[sizeof(struct amap_eq_context) / 8]; 351 struct phys_addr pages[8]; 352 } __packed; 353 354 struct be_cmd_resp_eq_create { 355 struct be_cmd_resp_hdr resp_hdr; 356 u16 eq_id; /* sword */ 357 u16 msix_idx; /* available only in v2 */ 358 } __packed; 359 360 /******************** Mac query ***************************/ 361 enum { 362 MAC_ADDRESS_TYPE_STORAGE = 0x0, 363 MAC_ADDRESS_TYPE_NETWORK = 0x1, 364 MAC_ADDRESS_TYPE_PD = 0x2, 365 MAC_ADDRESS_TYPE_MANAGEMENT = 0x3 366 }; 367 368 struct mac_addr { 369 u16 size_of_struct; 370 u8 addr[ETH_ALEN]; 371 } __packed; 372 373 struct be_cmd_req_mac_query { 374 struct be_cmd_req_hdr hdr; 375 u8 type; 376 u8 permanent; 377 u16 if_id; 378 u32 pmac_id; 379 } __packed; 380 381 struct be_cmd_resp_mac_query { 382 struct be_cmd_resp_hdr hdr; 383 struct mac_addr mac; 384 }; 385 386 /******************** PMac Add ***************************/ 387 struct be_cmd_req_pmac_add { 388 struct be_cmd_req_hdr hdr; 389 u32 if_id; 390 u8 mac_address[ETH_ALEN]; 391 u8 rsvd0[2]; 392 } __packed; 393 394 struct be_cmd_resp_pmac_add { 395 struct be_cmd_resp_hdr hdr; 396 u32 pmac_id; 397 }; 398 399 /******************** PMac Del ***************************/ 400 struct be_cmd_req_pmac_del { 401 struct be_cmd_req_hdr hdr; 402 u32 if_id; 403 u32 pmac_id; 404 }; 405 406 /******************** Create CQ ***************************/ 407 /* Pseudo amap definition in which each bit of the actual structure is defined 408 * as a byte: used to calculate offset/shift/mask of each field */ 409 struct amap_cq_context_be { 410 u8 cidx[11]; /* dword 0*/ 411 u8 rsvd0; /* dword 0*/ 412 u8 coalescwm[2]; /* dword 0*/ 413 u8 nodelay; /* dword 0*/ 414 u8 epidx[11]; /* dword 0*/ 415 u8 rsvd1; /* dword 0*/ 416 u8 count[2]; /* dword 0*/ 417 u8 valid; /* dword 0*/ 418 u8 solevent; /* dword 0*/ 419 u8 eventable; /* dword 0*/ 420 u8 pidx[11]; /* dword 1*/ 421 u8 rsvd2; /* dword 1*/ 422 u8 pd[10]; /* dword 1*/ 423 u8 eqid[8]; /* dword 1*/ 424 u8 stalled; /* dword 1*/ 425 u8 armed; /* dword 1*/ 426 u8 rsvd3[4]; /* dword 2*/ 427 u8 func[8]; /* dword 2*/ 428 u8 rsvd4[20]; /* dword 2*/ 429 u8 rsvd5[32]; /* dword 3*/ 430 } __packed; 431 432 struct amap_cq_context_v2 { 433 u8 rsvd0[12]; /* dword 0*/ 434 u8 coalescwm[2]; /* dword 0*/ 435 u8 nodelay; /* dword 0*/ 436 u8 rsvd1[12]; /* dword 0*/ 437 u8 count[2]; /* dword 0*/ 438 u8 valid; /* dword 0*/ 439 u8 rsvd2; /* dword 0*/ 440 u8 eventable; /* dword 0*/ 441 u8 eqid[16]; /* dword 1*/ 442 u8 rsvd3[15]; /* dword 1*/ 443 u8 armed; /* dword 1*/ 444 u8 rsvd4[32]; /* dword 2*/ 445 u8 rsvd5[32]; /* dword 3*/ 446 } __packed; 447 448 struct be_cmd_req_cq_create { 449 struct be_cmd_req_hdr hdr; 450 u16 num_pages; 451 u8 page_size; 452 u8 rsvd0; 453 u8 context[sizeof(struct amap_cq_context_be) / 8]; 454 struct phys_addr pages[8]; 455 } __packed; 456 457 458 struct be_cmd_resp_cq_create { 459 struct be_cmd_resp_hdr hdr; 460 u16 cq_id; 461 u16 rsvd0; 462 } __packed; 463 464 struct be_cmd_req_get_fat { 465 struct be_cmd_req_hdr hdr; 466 u32 fat_operation; 467 u32 read_log_offset; 468 u32 read_log_length; 469 u32 data_buffer_size; 470 u32 data_buffer[1]; 471 } __packed; 472 473 struct be_cmd_resp_get_fat { 474 struct be_cmd_resp_hdr hdr; 475 u32 log_size; 476 u32 read_log_length; 477 u32 rsvd[2]; 478 u32 data_buffer[1]; 479 } __packed; 480 481 482 /******************** Create MCCQ ***************************/ 483 /* Pseudo amap definition in which each bit of the actual structure is defined 484 * as a byte: used to calculate offset/shift/mask of each field */ 485 struct amap_mcc_context_be { 486 u8 con_index[14]; 487 u8 rsvd0[2]; 488 u8 ring_size[4]; 489 u8 fetch_wrb; 490 u8 fetch_r2t; 491 u8 cq_id[10]; 492 u8 prod_index[14]; 493 u8 fid[8]; 494 u8 pdid[9]; 495 u8 valid; 496 u8 rsvd1[32]; 497 u8 rsvd2[32]; 498 } __packed; 499 500 struct amap_mcc_context_v1 { 501 u8 async_cq_id[16]; 502 u8 ring_size[4]; 503 u8 rsvd0[12]; 504 u8 rsvd1[31]; 505 u8 valid; 506 u8 async_cq_valid[1]; 507 u8 rsvd2[31]; 508 u8 rsvd3[32]; 509 } __packed; 510 511 struct be_cmd_req_mcc_create { 512 struct be_cmd_req_hdr hdr; 513 u16 num_pages; 514 u16 cq_id; 515 u8 context[sizeof(struct amap_mcc_context_be) / 8]; 516 struct phys_addr pages[8]; 517 } __packed; 518 519 struct be_cmd_req_mcc_ext_create { 520 struct be_cmd_req_hdr hdr; 521 u16 num_pages; 522 u16 cq_id; 523 u32 async_event_bitmap[1]; 524 u8 context[sizeof(struct amap_mcc_context_v1) / 8]; 525 struct phys_addr pages[8]; 526 } __packed; 527 528 struct be_cmd_resp_mcc_create { 529 struct be_cmd_resp_hdr hdr; 530 u16 id; 531 u16 rsvd0; 532 } __packed; 533 534 /******************** Create TxQ ***************************/ 535 #define BE_ETH_TX_RING_TYPE_STANDARD 2 536 #define BE_ULP1_NUM 1 537 538 struct be_cmd_req_eth_tx_create { 539 struct be_cmd_req_hdr hdr; 540 u8 num_pages; 541 u8 ulp_num; 542 u16 type; 543 u16 if_id; 544 u8 queue_size; 545 u8 rsvd0; 546 u32 rsvd1; 547 u16 cq_id; 548 u16 rsvd2; 549 u32 rsvd3[13]; 550 struct phys_addr pages[8]; 551 } __packed; 552 553 struct be_cmd_resp_eth_tx_create { 554 struct be_cmd_resp_hdr hdr; 555 u16 cid; 556 u16 rid; 557 u32 db_offset; 558 u32 rsvd0[4]; 559 } __packed; 560 561 /******************** Create RxQ ***************************/ 562 struct be_cmd_req_eth_rx_create { 563 struct be_cmd_req_hdr hdr; 564 u16 cq_id; 565 u8 frag_size; 566 u8 num_pages; 567 struct phys_addr pages[2]; 568 u32 interface_id; 569 u16 max_frame_size; 570 u16 rsvd0; 571 u32 rss_queue; 572 } __packed; 573 574 struct be_cmd_resp_eth_rx_create { 575 struct be_cmd_resp_hdr hdr; 576 u16 id; 577 u8 rss_id; 578 u8 rsvd0; 579 } __packed; 580 581 /******************** Q Destroy ***************************/ 582 /* Type of Queue to be destroyed */ 583 enum { 584 QTYPE_EQ = 1, 585 QTYPE_CQ, 586 QTYPE_TXQ, 587 QTYPE_RXQ, 588 QTYPE_MCCQ 589 }; 590 591 struct be_cmd_req_q_destroy { 592 struct be_cmd_req_hdr hdr; 593 u16 id; 594 u16 bypass_flush; /* valid only for rx q destroy */ 595 } __packed; 596 597 /************ I/f Create (it's actually I/f Config Create)**********/ 598 599 /* Capability flags for the i/f */ 600 enum be_if_flags { 601 BE_IF_FLAGS_RSS = 0x4, 602 BE_IF_FLAGS_PROMISCUOUS = 0x8, 603 BE_IF_FLAGS_BROADCAST = 0x10, 604 BE_IF_FLAGS_UNTAGGED = 0x20, 605 BE_IF_FLAGS_ULP = 0x40, 606 BE_IF_FLAGS_VLAN_PROMISCUOUS = 0x80, 607 BE_IF_FLAGS_VLAN = 0x100, 608 BE_IF_FLAGS_MCAST_PROMISCUOUS = 0x200, 609 BE_IF_FLAGS_PASS_L2_ERRORS = 0x400, 610 BE_IF_FLAGS_PASS_L3L4_ERRORS = 0x800, 611 BE_IF_FLAGS_MULTICAST = 0x1000, 612 BE_IF_FLAGS_DEFQ_RSS = 0x1000000 613 }; 614 615 #define BE_IF_CAP_FLAGS_WANT (BE_IF_FLAGS_RSS | BE_IF_FLAGS_PROMISCUOUS |\ 616 BE_IF_FLAGS_BROADCAST | BE_IF_FLAGS_VLAN_PROMISCUOUS |\ 617 BE_IF_FLAGS_VLAN | BE_IF_FLAGS_MCAST_PROMISCUOUS |\ 618 BE_IF_FLAGS_PASS_L3L4_ERRORS | BE_IF_FLAGS_MULTICAST |\ 619 BE_IF_FLAGS_UNTAGGED | BE_IF_FLAGS_DEFQ_RSS) 620 621 #define BE_IF_FLAGS_ALL_PROMISCUOUS (BE_IF_FLAGS_PROMISCUOUS | \ 622 BE_IF_FLAGS_VLAN_PROMISCUOUS |\ 623 BE_IF_FLAGS_MCAST_PROMISCUOUS) 624 625 #define BE_IF_EN_FLAGS (BE_IF_FLAGS_BROADCAST | BE_IF_FLAGS_PASS_L3L4_ERRORS |\ 626 BE_IF_FLAGS_MULTICAST | BE_IF_FLAGS_UNTAGGED) 627 628 #define BE_IF_ALL_FILT_FLAGS (BE_IF_EN_FLAGS | BE_IF_FLAGS_ALL_PROMISCUOUS) 629 630 /* An RX interface is an object with one or more MAC addresses and 631 * filtering capabilities. */ 632 struct be_cmd_req_if_create { 633 struct be_cmd_req_hdr hdr; 634 u32 version; /* ignore currently */ 635 u32 capability_flags; 636 u32 enable_flags; 637 u8 mac_addr[ETH_ALEN]; 638 u8 rsvd0; 639 u8 pmac_invalid; /* if set, don't attach the mac addr to the i/f */ 640 u32 vlan_tag; /* not used currently */ 641 } __packed; 642 643 struct be_cmd_resp_if_create { 644 struct be_cmd_resp_hdr hdr; 645 u32 interface_id; 646 u32 pmac_id; 647 }; 648 649 /****** I/f Destroy(it's actually I/f Config Destroy )**********/ 650 struct be_cmd_req_if_destroy { 651 struct be_cmd_req_hdr hdr; 652 u32 interface_id; 653 }; 654 655 /*************** HW Stats Get **********************************/ 656 struct be_port_rxf_stats_v0 { 657 u32 rx_bytes_lsd; /* dword 0*/ 658 u32 rx_bytes_msd; /* dword 1*/ 659 u32 rx_total_frames; /* dword 2*/ 660 u32 rx_unicast_frames; /* dword 3*/ 661 u32 rx_multicast_frames; /* dword 4*/ 662 u32 rx_broadcast_frames; /* dword 5*/ 663 u32 rx_crc_errors; /* dword 6*/ 664 u32 rx_alignment_symbol_errors; /* dword 7*/ 665 u32 rx_pause_frames; /* dword 8*/ 666 u32 rx_control_frames; /* dword 9*/ 667 u32 rx_in_range_errors; /* dword 10*/ 668 u32 rx_out_range_errors; /* dword 11*/ 669 u32 rx_frame_too_long; /* dword 12*/ 670 u32 rx_address_filtered; /* dword 13*/ 671 u32 rx_vlan_filtered; /* dword 14*/ 672 u32 rx_dropped_too_small; /* dword 15*/ 673 u32 rx_dropped_too_short; /* dword 16*/ 674 u32 rx_dropped_header_too_small; /* dword 17*/ 675 u32 rx_dropped_tcp_length; /* dword 18*/ 676 u32 rx_dropped_runt; /* dword 19*/ 677 u32 rx_64_byte_packets; /* dword 20*/ 678 u32 rx_65_127_byte_packets; /* dword 21*/ 679 u32 rx_128_256_byte_packets; /* dword 22*/ 680 u32 rx_256_511_byte_packets; /* dword 23*/ 681 u32 rx_512_1023_byte_packets; /* dword 24*/ 682 u32 rx_1024_1518_byte_packets; /* dword 25*/ 683 u32 rx_1519_2047_byte_packets; /* dword 26*/ 684 u32 rx_2048_4095_byte_packets; /* dword 27*/ 685 u32 rx_4096_8191_byte_packets; /* dword 28*/ 686 u32 rx_8192_9216_byte_packets; /* dword 29*/ 687 u32 rx_ip_checksum_errs; /* dword 30*/ 688 u32 rx_tcp_checksum_errs; /* dword 31*/ 689 u32 rx_udp_checksum_errs; /* dword 32*/ 690 u32 rx_non_rss_packets; /* dword 33*/ 691 u32 rx_ipv4_packets; /* dword 34*/ 692 u32 rx_ipv6_packets; /* dword 35*/ 693 u32 rx_ipv4_bytes_lsd; /* dword 36*/ 694 u32 rx_ipv4_bytes_msd; /* dword 37*/ 695 u32 rx_ipv6_bytes_lsd; /* dword 38*/ 696 u32 rx_ipv6_bytes_msd; /* dword 39*/ 697 u32 rx_chute1_packets; /* dword 40*/ 698 u32 rx_chute2_packets; /* dword 41*/ 699 u32 rx_chute3_packets; /* dword 42*/ 700 u32 rx_management_packets; /* dword 43*/ 701 u32 rx_switched_unicast_packets; /* dword 44*/ 702 u32 rx_switched_multicast_packets; /* dword 45*/ 703 u32 rx_switched_broadcast_packets; /* dword 46*/ 704 u32 tx_bytes_lsd; /* dword 47*/ 705 u32 tx_bytes_msd; /* dword 48*/ 706 u32 tx_unicastframes; /* dword 49*/ 707 u32 tx_multicastframes; /* dword 50*/ 708 u32 tx_broadcastframes; /* dword 51*/ 709 u32 tx_pauseframes; /* dword 52*/ 710 u32 tx_controlframes; /* dword 53*/ 711 u32 tx_64_byte_packets; /* dword 54*/ 712 u32 tx_65_127_byte_packets; /* dword 55*/ 713 u32 tx_128_256_byte_packets; /* dword 56*/ 714 u32 tx_256_511_byte_packets; /* dword 57*/ 715 u32 tx_512_1023_byte_packets; /* dword 58*/ 716 u32 tx_1024_1518_byte_packets; /* dword 59*/ 717 u32 tx_1519_2047_byte_packets; /* dword 60*/ 718 u32 tx_2048_4095_byte_packets; /* dword 61*/ 719 u32 tx_4096_8191_byte_packets; /* dword 62*/ 720 u32 tx_8192_9216_byte_packets; /* dword 63*/ 721 u32 rx_fifo_overflow; /* dword 64*/ 722 u32 rx_input_fifo_overflow; /* dword 65*/ 723 }; 724 725 struct be_rxf_stats_v0 { 726 struct be_port_rxf_stats_v0 port[2]; 727 u32 rx_drops_no_pbuf; /* dword 132*/ 728 u32 rx_drops_no_txpb; /* dword 133*/ 729 u32 rx_drops_no_erx_descr; /* dword 134*/ 730 u32 rx_drops_no_tpre_descr; /* dword 135*/ 731 u32 management_rx_port_packets; /* dword 136*/ 732 u32 management_rx_port_bytes; /* dword 137*/ 733 u32 management_rx_port_pause_frames; /* dword 138*/ 734 u32 management_rx_port_errors; /* dword 139*/ 735 u32 management_tx_port_packets; /* dword 140*/ 736 u32 management_tx_port_bytes; /* dword 141*/ 737 u32 management_tx_port_pause; /* dword 142*/ 738 u32 management_rx_port_rxfifo_overflow; /* dword 143*/ 739 u32 rx_drops_too_many_frags; /* dword 144*/ 740 u32 rx_drops_invalid_ring; /* dword 145*/ 741 u32 forwarded_packets; /* dword 146*/ 742 u32 rx_drops_mtu; /* dword 147*/ 743 u32 rsvd0[7]; 744 u32 port0_jabber_events; 745 u32 port1_jabber_events; 746 u32 rsvd1[6]; 747 }; 748 749 struct be_erx_stats_v0 { 750 u32 rx_drops_no_fragments[44]; /* dwordS 0 to 43*/ 751 u32 rsvd[4]; 752 }; 753 754 struct be_pmem_stats { 755 u32 eth_red_drops; 756 u32 rsvd[5]; 757 }; 758 759 struct be_hw_stats_v0 { 760 struct be_rxf_stats_v0 rxf; 761 u32 rsvd[48]; 762 struct be_erx_stats_v0 erx; 763 struct be_pmem_stats pmem; 764 }; 765 766 struct be_cmd_req_get_stats_v0 { 767 struct be_cmd_req_hdr hdr; 768 u8 rsvd[sizeof(struct be_hw_stats_v0)]; 769 }; 770 771 struct be_cmd_resp_get_stats_v0 { 772 struct be_cmd_resp_hdr hdr; 773 struct be_hw_stats_v0 hw_stats; 774 }; 775 776 struct lancer_pport_stats { 777 u32 tx_packets_lo; 778 u32 tx_packets_hi; 779 u32 tx_unicast_packets_lo; 780 u32 tx_unicast_packets_hi; 781 u32 tx_multicast_packets_lo; 782 u32 tx_multicast_packets_hi; 783 u32 tx_broadcast_packets_lo; 784 u32 tx_broadcast_packets_hi; 785 u32 tx_bytes_lo; 786 u32 tx_bytes_hi; 787 u32 tx_unicast_bytes_lo; 788 u32 tx_unicast_bytes_hi; 789 u32 tx_multicast_bytes_lo; 790 u32 tx_multicast_bytes_hi; 791 u32 tx_broadcast_bytes_lo; 792 u32 tx_broadcast_bytes_hi; 793 u32 tx_discards_lo; 794 u32 tx_discards_hi; 795 u32 tx_errors_lo; 796 u32 tx_errors_hi; 797 u32 tx_pause_frames_lo; 798 u32 tx_pause_frames_hi; 799 u32 tx_pause_on_frames_lo; 800 u32 tx_pause_on_frames_hi; 801 u32 tx_pause_off_frames_lo; 802 u32 tx_pause_off_frames_hi; 803 u32 tx_internal_mac_errors_lo; 804 u32 tx_internal_mac_errors_hi; 805 u32 tx_control_frames_lo; 806 u32 tx_control_frames_hi; 807 u32 tx_packets_64_bytes_lo; 808 u32 tx_packets_64_bytes_hi; 809 u32 tx_packets_65_to_127_bytes_lo; 810 u32 tx_packets_65_to_127_bytes_hi; 811 u32 tx_packets_128_to_255_bytes_lo; 812 u32 tx_packets_128_to_255_bytes_hi; 813 u32 tx_packets_256_to_511_bytes_lo; 814 u32 tx_packets_256_to_511_bytes_hi; 815 u32 tx_packets_512_to_1023_bytes_lo; 816 u32 tx_packets_512_to_1023_bytes_hi; 817 u32 tx_packets_1024_to_1518_bytes_lo; 818 u32 tx_packets_1024_to_1518_bytes_hi; 819 u32 tx_packets_1519_to_2047_bytes_lo; 820 u32 tx_packets_1519_to_2047_bytes_hi; 821 u32 tx_packets_2048_to_4095_bytes_lo; 822 u32 tx_packets_2048_to_4095_bytes_hi; 823 u32 tx_packets_4096_to_8191_bytes_lo; 824 u32 tx_packets_4096_to_8191_bytes_hi; 825 u32 tx_packets_8192_to_9216_bytes_lo; 826 u32 tx_packets_8192_to_9216_bytes_hi; 827 u32 tx_lso_packets_lo; 828 u32 tx_lso_packets_hi; 829 u32 rx_packets_lo; 830 u32 rx_packets_hi; 831 u32 rx_unicast_packets_lo; 832 u32 rx_unicast_packets_hi; 833 u32 rx_multicast_packets_lo; 834 u32 rx_multicast_packets_hi; 835 u32 rx_broadcast_packets_lo; 836 u32 rx_broadcast_packets_hi; 837 u32 rx_bytes_lo; 838 u32 rx_bytes_hi; 839 u32 rx_unicast_bytes_lo; 840 u32 rx_unicast_bytes_hi; 841 u32 rx_multicast_bytes_lo; 842 u32 rx_multicast_bytes_hi; 843 u32 rx_broadcast_bytes_lo; 844 u32 rx_broadcast_bytes_hi; 845 u32 rx_unknown_protos; 846 u32 rsvd_69; /* Word 69 is reserved */ 847 u32 rx_discards_lo; 848 u32 rx_discards_hi; 849 u32 rx_errors_lo; 850 u32 rx_errors_hi; 851 u32 rx_crc_errors_lo; 852 u32 rx_crc_errors_hi; 853 u32 rx_alignment_errors_lo; 854 u32 rx_alignment_errors_hi; 855 u32 rx_symbol_errors_lo; 856 u32 rx_symbol_errors_hi; 857 u32 rx_pause_frames_lo; 858 u32 rx_pause_frames_hi; 859 u32 rx_pause_on_frames_lo; 860 u32 rx_pause_on_frames_hi; 861 u32 rx_pause_off_frames_lo; 862 u32 rx_pause_off_frames_hi; 863 u32 rx_frames_too_long_lo; 864 u32 rx_frames_too_long_hi; 865 u32 rx_internal_mac_errors_lo; 866 u32 rx_internal_mac_errors_hi; 867 u32 rx_undersize_packets; 868 u32 rx_oversize_packets; 869 u32 rx_fragment_packets; 870 u32 rx_jabbers; 871 u32 rx_control_frames_lo; 872 u32 rx_control_frames_hi; 873 u32 rx_control_frames_unknown_opcode_lo; 874 u32 rx_control_frames_unknown_opcode_hi; 875 u32 rx_in_range_errors; 876 u32 rx_out_of_range_errors; 877 u32 rx_address_filtered; 878 u32 rx_vlan_filtered; 879 u32 rx_dropped_too_small; 880 u32 rx_dropped_too_short; 881 u32 rx_dropped_header_too_small; 882 u32 rx_dropped_invalid_tcp_length; 883 u32 rx_dropped_runt; 884 u32 rx_ip_checksum_errors; 885 u32 rx_tcp_checksum_errors; 886 u32 rx_udp_checksum_errors; 887 u32 rx_non_rss_packets; 888 u32 rsvd_111; 889 u32 rx_ipv4_packets_lo; 890 u32 rx_ipv4_packets_hi; 891 u32 rx_ipv6_packets_lo; 892 u32 rx_ipv6_packets_hi; 893 u32 rx_ipv4_bytes_lo; 894 u32 rx_ipv4_bytes_hi; 895 u32 rx_ipv6_bytes_lo; 896 u32 rx_ipv6_bytes_hi; 897 u32 rx_nic_packets_lo; 898 u32 rx_nic_packets_hi; 899 u32 rx_tcp_packets_lo; 900 u32 rx_tcp_packets_hi; 901 u32 rx_iscsi_packets_lo; 902 u32 rx_iscsi_packets_hi; 903 u32 rx_management_packets_lo; 904 u32 rx_management_packets_hi; 905 u32 rx_switched_unicast_packets_lo; 906 u32 rx_switched_unicast_packets_hi; 907 u32 rx_switched_multicast_packets_lo; 908 u32 rx_switched_multicast_packets_hi; 909 u32 rx_switched_broadcast_packets_lo; 910 u32 rx_switched_broadcast_packets_hi; 911 u32 num_forwards_lo; 912 u32 num_forwards_hi; 913 u32 rx_fifo_overflow; 914 u32 rx_input_fifo_overflow; 915 u32 rx_drops_too_many_frags_lo; 916 u32 rx_drops_too_many_frags_hi; 917 u32 rx_drops_invalid_queue; 918 u32 rsvd_141; 919 u32 rx_drops_mtu_lo; 920 u32 rx_drops_mtu_hi; 921 u32 rx_packets_64_bytes_lo; 922 u32 rx_packets_64_bytes_hi; 923 u32 rx_packets_65_to_127_bytes_lo; 924 u32 rx_packets_65_to_127_bytes_hi; 925 u32 rx_packets_128_to_255_bytes_lo; 926 u32 rx_packets_128_to_255_bytes_hi; 927 u32 rx_packets_256_to_511_bytes_lo; 928 u32 rx_packets_256_to_511_bytes_hi; 929 u32 rx_packets_512_to_1023_bytes_lo; 930 u32 rx_packets_512_to_1023_bytes_hi; 931 u32 rx_packets_1024_to_1518_bytes_lo; 932 u32 rx_packets_1024_to_1518_bytes_hi; 933 u32 rx_packets_1519_to_2047_bytes_lo; 934 u32 rx_packets_1519_to_2047_bytes_hi; 935 u32 rx_packets_2048_to_4095_bytes_lo; 936 u32 rx_packets_2048_to_4095_bytes_hi; 937 u32 rx_packets_4096_to_8191_bytes_lo; 938 u32 rx_packets_4096_to_8191_bytes_hi; 939 u32 rx_packets_8192_to_9216_bytes_lo; 940 u32 rx_packets_8192_to_9216_bytes_hi; 941 }; 942 943 struct pport_stats_params { 944 u16 pport_num; 945 u8 rsvd; 946 u8 reset_stats; 947 }; 948 949 struct lancer_cmd_req_pport_stats { 950 struct be_cmd_req_hdr hdr; 951 union { 952 struct pport_stats_params params; 953 u8 rsvd[sizeof(struct lancer_pport_stats)]; 954 } cmd_params; 955 }; 956 957 struct lancer_cmd_resp_pport_stats { 958 struct be_cmd_resp_hdr hdr; 959 struct lancer_pport_stats pport_stats; 960 }; 961 962 static inline struct lancer_pport_stats* 963 pport_stats_from_cmd(struct be_adapter *adapter) 964 { 965 struct lancer_cmd_resp_pport_stats *cmd = adapter->stats_cmd.va; 966 return &cmd->pport_stats; 967 } 968 969 struct be_cmd_req_get_cntl_addnl_attribs { 970 struct be_cmd_req_hdr hdr; 971 u8 rsvd[8]; 972 }; 973 974 struct be_cmd_resp_get_cntl_addnl_attribs { 975 struct be_cmd_resp_hdr hdr; 976 u16 ipl_file_number; 977 u8 ipl_file_version; 978 u8 rsvd0; 979 u8 on_die_temperature; /* in degrees centigrade*/ 980 u8 rsvd1[3]; 981 }; 982 983 struct be_cmd_req_vlan_config { 984 struct be_cmd_req_hdr hdr; 985 u8 interface_id; 986 u8 promiscuous; 987 u8 untagged; 988 u8 num_vlan; 989 u16 normal_vlan[64]; 990 } __packed; 991 992 /******************* RX FILTER ******************************/ 993 #define BE_MAX_MC 64 /* set mcast promisc if > 64 */ 994 struct macaddr { 995 u8 byte[ETH_ALEN]; 996 }; 997 998 struct be_cmd_req_rx_filter { 999 struct be_cmd_req_hdr hdr; 1000 u32 global_flags_mask; 1001 u32 global_flags; 1002 u32 if_flags_mask; 1003 u32 if_flags; 1004 u32 if_id; 1005 u32 mcast_num; 1006 struct macaddr mcast_mac[BE_MAX_MC]; 1007 }; 1008 1009 /******************** Link Status Query *******************/ 1010 struct be_cmd_req_link_status { 1011 struct be_cmd_req_hdr hdr; 1012 u32 rsvd; 1013 }; 1014 1015 enum { 1016 PHY_LINK_DUPLEX_NONE = 0x0, 1017 PHY_LINK_DUPLEX_HALF = 0x1, 1018 PHY_LINK_DUPLEX_FULL = 0x2 1019 }; 1020 1021 enum { 1022 PHY_LINK_SPEED_ZERO = 0x0, /* => No link */ 1023 PHY_LINK_SPEED_10MBPS = 0x1, 1024 PHY_LINK_SPEED_100MBPS = 0x2, 1025 PHY_LINK_SPEED_1GBPS = 0x3, 1026 PHY_LINK_SPEED_10GBPS = 0x4, 1027 PHY_LINK_SPEED_20GBPS = 0x5, 1028 PHY_LINK_SPEED_25GBPS = 0x6, 1029 PHY_LINK_SPEED_40GBPS = 0x7 1030 }; 1031 1032 struct be_cmd_resp_link_status { 1033 struct be_cmd_resp_hdr hdr; 1034 u8 physical_port; 1035 u8 mac_duplex; 1036 u8 mac_speed; 1037 u8 mac_fault; 1038 u8 mgmt_mac_duplex; 1039 u8 mgmt_mac_speed; 1040 u16 link_speed; 1041 u8 logical_link_status; 1042 u8 rsvd1[3]; 1043 } __packed; 1044 1045 /******************** Port Identification ***************************/ 1046 /* Identifies the type of port attached to NIC */ 1047 struct be_cmd_req_port_type { 1048 struct be_cmd_req_hdr hdr; 1049 __le32 page_num; 1050 __le32 port; 1051 }; 1052 1053 enum { 1054 TR_PAGE_A0 = 0xa0, 1055 TR_PAGE_A2 = 0xa2 1056 }; 1057 1058 /* From SFF-8436 QSFP+ spec */ 1059 #define QSFP_PLUS_CABLE_TYPE_OFFSET 0x83 1060 #define QSFP_PLUS_CR4_CABLE 0x8 1061 #define QSFP_PLUS_SR4_CABLE 0x4 1062 #define QSFP_PLUS_LR4_CABLE 0x2 1063 1064 /* From SFF-8472 spec */ 1065 #define SFP_PLUS_SFF_8472_COMP 0x5E 1066 #define SFP_PLUS_CABLE_TYPE_OFFSET 0x8 1067 #define SFP_PLUS_COPPER_CABLE 0x4 1068 #define SFP_VENDOR_NAME_OFFSET 0x14 1069 #define SFP_VENDOR_PN_OFFSET 0x28 1070 1071 #define PAGE_DATA_LEN 256 1072 struct be_cmd_resp_port_type { 1073 struct be_cmd_resp_hdr hdr; 1074 u32 page_num; 1075 u32 port; 1076 u8 page_data[PAGE_DATA_LEN]; 1077 }; 1078 1079 /******************** Get FW Version *******************/ 1080 struct be_cmd_req_get_fw_version { 1081 struct be_cmd_req_hdr hdr; 1082 u8 rsvd0[FW_VER_LEN]; 1083 u8 rsvd1[FW_VER_LEN]; 1084 } __packed; 1085 1086 struct be_cmd_resp_get_fw_version { 1087 struct be_cmd_resp_hdr hdr; 1088 u8 firmware_version_string[FW_VER_LEN]; 1089 u8 fw_on_flash_version_string[FW_VER_LEN]; 1090 } __packed; 1091 1092 /******************** Set Flow Contrl *******************/ 1093 struct be_cmd_req_set_flow_control { 1094 struct be_cmd_req_hdr hdr; 1095 u16 tx_flow_control; 1096 u16 rx_flow_control; 1097 } __packed; 1098 1099 /******************** Get Flow Contrl *******************/ 1100 struct be_cmd_req_get_flow_control { 1101 struct be_cmd_req_hdr hdr; 1102 u32 rsvd; 1103 }; 1104 1105 struct be_cmd_resp_get_flow_control { 1106 struct be_cmd_resp_hdr hdr; 1107 u16 tx_flow_control; 1108 u16 rx_flow_control; 1109 } __packed; 1110 1111 /******************** Modify EQ Delay *******************/ 1112 struct be_set_eqd { 1113 u32 eq_id; 1114 u32 phase; 1115 u32 delay_multiplier; 1116 }; 1117 1118 struct be_cmd_req_modify_eq_delay { 1119 struct be_cmd_req_hdr hdr; 1120 u32 num_eq; 1121 struct be_set_eqd set_eqd[MAX_EVT_QS]; 1122 } __packed; 1123 1124 /******************** Get FW Config *******************/ 1125 /* The HW can come up in either of the following multi-channel modes 1126 * based on the skew/IPL. 1127 */ 1128 #define RDMA_ENABLED 0x4 1129 #define QNQ_MODE 0x400 1130 #define VNIC_MODE 0x20000 1131 #define UMC_ENABLED 0x1000000 1132 struct be_cmd_req_query_fw_cfg { 1133 struct be_cmd_req_hdr hdr; 1134 u32 rsvd[31]; 1135 }; 1136 1137 struct be_cmd_resp_query_fw_cfg { 1138 struct be_cmd_resp_hdr hdr; 1139 u32 be_config_number; 1140 u32 asic_revision; 1141 u32 phys_port; 1142 u32 function_mode; 1143 u32 rsvd[26]; 1144 u32 function_caps; 1145 }; 1146 1147 /******************** RSS Config ****************************************/ 1148 /* RSS type Input parameters used to compute RX hash 1149 * RSS_ENABLE_IPV4 SRC IPv4, DST IPv4 1150 * RSS_ENABLE_TCP_IPV4 SRC IPv4, DST IPv4, TCP SRC PORT, TCP DST PORT 1151 * RSS_ENABLE_IPV6 SRC IPv6, DST IPv6 1152 * RSS_ENABLE_TCP_IPV6 SRC IPv6, DST IPv6, TCP SRC PORT, TCP DST PORT 1153 * RSS_ENABLE_UDP_IPV4 SRC IPv4, DST IPv4, UDP SRC PORT, UDP DST PORT 1154 * RSS_ENABLE_UDP_IPV6 SRC IPv6, DST IPv6, UDP SRC PORT, UDP DST PORT 1155 * 1156 * When multiple RSS types are enabled, HW picks the best hash policy 1157 * based on the type of the received packet. 1158 */ 1159 #define RSS_ENABLE_NONE 0x0 1160 #define RSS_ENABLE_IPV4 0x1 1161 #define RSS_ENABLE_TCP_IPV4 0x2 1162 #define RSS_ENABLE_IPV6 0x4 1163 #define RSS_ENABLE_TCP_IPV6 0x8 1164 #define RSS_ENABLE_UDP_IPV4 0x10 1165 #define RSS_ENABLE_UDP_IPV6 0x20 1166 1167 #define L3_RSS_FLAGS (RXH_IP_DST | RXH_IP_SRC) 1168 #define L4_RSS_FLAGS (RXH_L4_B_0_1 | RXH_L4_B_2_3) 1169 1170 struct be_cmd_req_rss_config { 1171 struct be_cmd_req_hdr hdr; 1172 u32 if_id; 1173 u16 enable_rss; 1174 u16 cpu_table_size_log2; 1175 u32 hash[10]; 1176 u8 cpu_table[128]; 1177 u8 flush; 1178 u8 rsvd0[3]; 1179 }; 1180 1181 /******************** Port Beacon ***************************/ 1182 1183 #define BEACON_STATE_ENABLED 0x1 1184 #define BEACON_STATE_DISABLED 0x0 1185 1186 struct be_cmd_req_enable_disable_beacon { 1187 struct be_cmd_req_hdr hdr; 1188 u8 port_num; 1189 u8 beacon_state; 1190 u8 beacon_duration; 1191 u8 status_duration; 1192 } __packed; 1193 1194 struct be_cmd_req_get_beacon_state { 1195 struct be_cmd_req_hdr hdr; 1196 u8 port_num; 1197 u8 rsvd0; 1198 u16 rsvd1; 1199 } __packed; 1200 1201 struct be_cmd_resp_get_beacon_state { 1202 struct be_cmd_resp_hdr resp_hdr; 1203 u8 beacon_state; 1204 u8 rsvd0[3]; 1205 } __packed; 1206 1207 /* Flashrom related descriptors */ 1208 #define MAX_FLASH_COMP 32 1209 1210 #define OPTYPE_ISCSI_ACTIVE 0 1211 #define OPTYPE_REDBOOT 1 1212 #define OPTYPE_BIOS 2 1213 #define OPTYPE_PXE_BIOS 3 1214 #define OPTYPE_OFFSET_SPECIFIED 7 1215 #define OPTYPE_FCOE_BIOS 8 1216 #define OPTYPE_ISCSI_BACKUP 9 1217 #define OPTYPE_FCOE_FW_ACTIVE 10 1218 #define OPTYPE_FCOE_FW_BACKUP 11 1219 #define OPTYPE_NCSI_FW 13 1220 #define OPTYPE_REDBOOT_DIR 18 1221 #define OPTYPE_REDBOOT_CONFIG 19 1222 #define OPTYPE_SH_PHY_FW 21 1223 #define OPTYPE_FLASHISM_JUMPVECTOR 22 1224 #define OPTYPE_UFI_DIR 23 1225 #define OPTYPE_PHY_FW 99 1226 1227 #define FLASH_BIOS_IMAGE_MAX_SIZE_g2 262144 /* Max OPTION ROM image sz */ 1228 #define FLASH_REDBOOT_IMAGE_MAX_SIZE_g2 262144 /* Max Redboot image sz */ 1229 #define FLASH_IMAGE_MAX_SIZE_g2 1310720 /* Max firmware image size */ 1230 1231 #define FLASH_NCSI_IMAGE_MAX_SIZE_g3 262144 1232 #define FLASH_PHY_FW_IMAGE_MAX_SIZE_g3 262144 1233 #define FLASH_BIOS_IMAGE_MAX_SIZE_g3 524288 /* Max OPTION ROM image sz */ 1234 #define FLASH_REDBOOT_IMAGE_MAX_SIZE_g3 1048576 /* Max Redboot image sz */ 1235 #define FLASH_IMAGE_MAX_SIZE_g3 2097152 /* Max firmware image size */ 1236 1237 /* Offsets for components on Flash. */ 1238 #define FLASH_REDBOOT_START_g2 0 1239 #define FLASH_FCoE_BIOS_START_g2 524288 1240 #define FLASH_iSCSI_PRIMARY_IMAGE_START_g2 1048576 1241 #define FLASH_iSCSI_BACKUP_IMAGE_START_g2 2359296 1242 #define FLASH_FCoE_PRIMARY_IMAGE_START_g2 3670016 1243 #define FLASH_FCoE_BACKUP_IMAGE_START_g2 4980736 1244 #define FLASH_iSCSI_BIOS_START_g2 7340032 1245 #define FLASH_PXE_BIOS_START_g2 7864320 1246 1247 #define FLASH_REDBOOT_START_g3 262144 1248 #define FLASH_PHY_FW_START_g3 1310720 1249 #define FLASH_iSCSI_PRIMARY_IMAGE_START_g3 2097152 1250 #define FLASH_iSCSI_BACKUP_IMAGE_START_g3 4194304 1251 #define FLASH_FCoE_PRIMARY_IMAGE_START_g3 6291456 1252 #define FLASH_FCoE_BACKUP_IMAGE_START_g3 8388608 1253 #define FLASH_iSCSI_BIOS_START_g3 12582912 1254 #define FLASH_PXE_BIOS_START_g3 13107200 1255 #define FLASH_FCoE_BIOS_START_g3 13631488 1256 #define FLASH_NCSI_START_g3 15990784 1257 1258 #define IMAGE_NCSI 16 1259 #define IMAGE_OPTION_ROM_PXE 32 1260 #define IMAGE_OPTION_ROM_FCoE 33 1261 #define IMAGE_OPTION_ROM_ISCSI 34 1262 #define IMAGE_FLASHISM_JUMPVECTOR 48 1263 #define IMAGE_FIRMWARE_iSCSI 160 1264 #define IMAGE_FIRMWARE_FCoE 162 1265 #define IMAGE_FIRMWARE_BACKUP_iSCSI 176 1266 #define IMAGE_FIRMWARE_BACKUP_FCoE 178 1267 #define IMAGE_FIRMWARE_PHY 192 1268 #define IMAGE_REDBOOT_DIR 208 1269 #define IMAGE_REDBOOT_CONFIG 209 1270 #define IMAGE_UFI_DIR 210 1271 #define IMAGE_BOOT_CODE 224 1272 1273 struct controller_id { 1274 u32 vendor; 1275 u32 device; 1276 u32 subvendor; 1277 u32 subdevice; 1278 }; 1279 1280 struct flash_comp { 1281 unsigned long offset; 1282 int optype; 1283 int size; 1284 int img_type; 1285 }; 1286 1287 struct image_hdr { 1288 u32 imageid; 1289 u32 imageoffset; 1290 u32 imagelength; 1291 u32 image_checksum; 1292 u8 image_version[32]; 1293 }; 1294 1295 struct flash_file_hdr_g2 { 1296 u8 sign[32]; 1297 u32 cksum; 1298 u32 antidote; 1299 struct controller_id cont_id; 1300 u32 file_len; 1301 u32 chunk_num; 1302 u32 total_chunks; 1303 u32 num_imgs; 1304 u8 build[24]; 1305 }; 1306 1307 /* First letter of the build version of the image */ 1308 #define BLD_STR_UFI_TYPE_BE2 '2' 1309 #define BLD_STR_UFI_TYPE_BE3 '3' 1310 #define BLD_STR_UFI_TYPE_SH '4' 1311 1312 struct flash_file_hdr_g3 { 1313 u8 sign[52]; 1314 u8 ufi_version[4]; 1315 u32 file_len; 1316 u32 cksum; 1317 u32 antidote; 1318 u32 num_imgs; 1319 u8 build[24]; 1320 u8 asic_type_rev; 1321 u8 rsvd[31]; 1322 }; 1323 1324 struct flash_section_hdr { 1325 u32 format_rev; 1326 u32 cksum; 1327 u32 antidote; 1328 u32 num_images; 1329 u8 id_string[128]; 1330 u32 rsvd[4]; 1331 } __packed; 1332 1333 struct flash_section_hdr_g2 { 1334 u32 format_rev; 1335 u32 cksum; 1336 u32 antidote; 1337 u32 build_num; 1338 u8 id_string[128]; 1339 u32 rsvd[8]; 1340 } __packed; 1341 1342 struct flash_section_entry { 1343 u32 type; 1344 u32 offset; 1345 u32 pad_size; 1346 u32 image_size; 1347 u32 cksum; 1348 u32 entry_point; 1349 u16 optype; 1350 u16 rsvd0; 1351 u32 rsvd1; 1352 u8 ver_data[32]; 1353 } __packed; 1354 1355 struct flash_section_info { 1356 u8 cookie[32]; 1357 struct flash_section_hdr fsec_hdr; 1358 struct flash_section_entry fsec_entry[32]; 1359 } __packed; 1360 1361 struct flash_section_info_g2 { 1362 u8 cookie[32]; 1363 struct flash_section_hdr_g2 fsec_hdr; 1364 struct flash_section_entry fsec_entry[32]; 1365 } __packed; 1366 1367 /****************** Firmware Flash ******************/ 1368 #define FLASHROM_OPER_FLASH 1 1369 #define FLASHROM_OPER_SAVE 2 1370 #define FLASHROM_OPER_REPORT 4 1371 #define FLASHROM_OPER_PHY_FLASH 9 1372 #define FLASHROM_OPER_PHY_SAVE 10 1373 1374 struct flashrom_params { 1375 u32 op_code; 1376 u32 op_type; 1377 u32 data_buf_size; 1378 u32 offset; 1379 }; 1380 1381 struct be_cmd_write_flashrom { 1382 struct be_cmd_req_hdr hdr; 1383 struct flashrom_params params; 1384 u8 data_buf[32768]; 1385 u8 rsvd[4]; 1386 } __packed; 1387 1388 /* cmd to read flash crc */ 1389 struct be_cmd_read_flash_crc { 1390 struct be_cmd_req_hdr hdr; 1391 struct flashrom_params params; 1392 u8 crc[4]; 1393 u8 rsvd[4]; 1394 } __packed; 1395 1396 /**************** Lancer Firmware Flash ************/ 1397 struct amap_lancer_write_obj_context { 1398 u8 write_length[24]; 1399 u8 reserved1[7]; 1400 u8 eof; 1401 } __packed; 1402 1403 struct lancer_cmd_req_write_object { 1404 struct be_cmd_req_hdr hdr; 1405 u8 context[sizeof(struct amap_lancer_write_obj_context) / 8]; 1406 u32 write_offset; 1407 u8 object_name[104]; 1408 u32 descriptor_count; 1409 u32 buf_len; 1410 u32 addr_low; 1411 u32 addr_high; 1412 }; 1413 1414 #define LANCER_NO_RESET_NEEDED 0x00 1415 #define LANCER_FW_RESET_NEEDED 0x02 1416 struct lancer_cmd_resp_write_object { 1417 u8 opcode; 1418 u8 subsystem; 1419 u8 rsvd1[2]; 1420 u8 status; 1421 u8 additional_status; 1422 u8 rsvd2[2]; 1423 u32 resp_len; 1424 u32 actual_resp_len; 1425 u32 actual_write_len; 1426 u8 change_status; 1427 u8 rsvd3[3]; 1428 }; 1429 1430 /************************ Lancer Read FW info **************/ 1431 #define LANCER_READ_FILE_CHUNK (32*1024) 1432 #define LANCER_READ_FILE_EOF_MASK 0x80000000 1433 1434 #define LANCER_FW_DUMP_FILE "/dbg/dump.bin" 1435 #define LANCER_VPD_PF_FILE "/vpd/ntr_pf.vpd" 1436 #define LANCER_VPD_VF_FILE "/vpd/ntr_vf.vpd" 1437 1438 struct lancer_cmd_req_read_object { 1439 struct be_cmd_req_hdr hdr; 1440 u32 desired_read_len; 1441 u32 read_offset; 1442 u8 object_name[104]; 1443 u32 descriptor_count; 1444 u32 buf_len; 1445 u32 addr_low; 1446 u32 addr_high; 1447 }; 1448 1449 struct lancer_cmd_resp_read_object { 1450 u8 opcode; 1451 u8 subsystem; 1452 u8 rsvd1[2]; 1453 u8 status; 1454 u8 additional_status; 1455 u8 rsvd2[2]; 1456 u32 resp_len; 1457 u32 actual_resp_len; 1458 u32 actual_read_len; 1459 u32 eof; 1460 }; 1461 1462 struct lancer_cmd_req_delete_object { 1463 struct be_cmd_req_hdr hdr; 1464 u32 rsvd1; 1465 u32 rsvd2; 1466 u8 object_name[104]; 1467 }; 1468 1469 /************************ WOL *******************************/ 1470 struct be_cmd_req_acpi_wol_magic_config{ 1471 struct be_cmd_req_hdr hdr; 1472 u32 rsvd0[145]; 1473 u8 magic_mac[6]; 1474 u8 rsvd2[2]; 1475 } __packed; 1476 1477 struct be_cmd_req_acpi_wol_magic_config_v1 { 1478 struct be_cmd_req_hdr hdr; 1479 u8 rsvd0[2]; 1480 u8 query_options; 1481 u8 rsvd1[5]; 1482 u32 rsvd2[288]; 1483 u8 magic_mac[6]; 1484 u8 rsvd3[22]; 1485 } __packed; 1486 1487 struct be_cmd_resp_acpi_wol_magic_config_v1 { 1488 struct be_cmd_resp_hdr hdr; 1489 u8 rsvd0[2]; 1490 u8 wol_settings; 1491 u8 rsvd1[5]; 1492 u32 rsvd2[295]; 1493 } __packed; 1494 1495 #define BE_GET_WOL_CAP 2 1496 1497 #define BE_WOL_CAP 0x1 1498 #define BE_PME_D0_CAP 0x8 1499 #define BE_PME_D1_CAP 0x10 1500 #define BE_PME_D2_CAP 0x20 1501 #define BE_PME_D3HOT_CAP 0x40 1502 #define BE_PME_D3COLD_CAP 0x80 1503 1504 /********************** LoopBack test *********************/ 1505 #define SET_LB_MODE_TIMEOUT 12000 1506 1507 struct be_cmd_req_loopback_test { 1508 struct be_cmd_req_hdr hdr; 1509 u32 loopback_type; 1510 u32 num_pkts; 1511 u64 pattern; 1512 u32 src_port; 1513 u32 dest_port; 1514 u32 pkt_size; 1515 }; 1516 1517 struct be_cmd_resp_loopback_test { 1518 struct be_cmd_resp_hdr resp_hdr; 1519 u32 status; 1520 u32 num_txfer; 1521 u32 num_rx; 1522 u32 miscomp_off; 1523 u32 ticks_compl; 1524 }; 1525 1526 struct be_cmd_req_set_lmode { 1527 struct be_cmd_req_hdr hdr; 1528 u8 src_port; 1529 u8 dest_port; 1530 u8 loopback_type; 1531 u8 loopback_state; 1532 }; 1533 1534 /********************** DDR DMA test *********************/ 1535 struct be_cmd_req_ddrdma_test { 1536 struct be_cmd_req_hdr hdr; 1537 u64 pattern; 1538 u32 byte_count; 1539 u32 rsvd0; 1540 u8 snd_buff[4096]; 1541 u8 rsvd1[4096]; 1542 }; 1543 1544 struct be_cmd_resp_ddrdma_test { 1545 struct be_cmd_resp_hdr hdr; 1546 u64 pattern; 1547 u32 byte_cnt; 1548 u32 snd_err; 1549 u8 rsvd0[4096]; 1550 u8 rcv_buff[4096]; 1551 }; 1552 1553 /*********************** SEEPROM Read ***********************/ 1554 1555 #define BE_READ_SEEPROM_LEN 1024 1556 struct be_cmd_req_seeprom_read { 1557 struct be_cmd_req_hdr hdr; 1558 u8 rsvd0[BE_READ_SEEPROM_LEN]; 1559 }; 1560 1561 struct be_cmd_resp_seeprom_read { 1562 struct be_cmd_req_hdr hdr; 1563 u8 seeprom_data[BE_READ_SEEPROM_LEN]; 1564 }; 1565 1566 enum { 1567 PHY_TYPE_CX4_10GB = 0, 1568 PHY_TYPE_XFP_10GB, 1569 PHY_TYPE_SFP_1GB, 1570 PHY_TYPE_SFP_PLUS_10GB, 1571 PHY_TYPE_KR_10GB, 1572 PHY_TYPE_KX4_10GB, 1573 PHY_TYPE_BASET_10GB, 1574 PHY_TYPE_BASET_1GB, 1575 PHY_TYPE_BASEX_1GB, 1576 PHY_TYPE_SGMII, 1577 PHY_TYPE_QSFP, 1578 PHY_TYPE_KR4_40GB, 1579 PHY_TYPE_KR2_20GB, 1580 PHY_TYPE_TN_8022, 1581 PHY_TYPE_DISABLED = 255 1582 }; 1583 1584 #define BE_SUPPORTED_SPEED_NONE 0 1585 #define BE_SUPPORTED_SPEED_10MBPS 1 1586 #define BE_SUPPORTED_SPEED_100MBPS 2 1587 #define BE_SUPPORTED_SPEED_1GBPS 4 1588 #define BE_SUPPORTED_SPEED_10GBPS 8 1589 #define BE_SUPPORTED_SPEED_20GBPS 0x10 1590 #define BE_SUPPORTED_SPEED_40GBPS 0x20 1591 1592 #define BE_AN_EN 0x2 1593 #define BE_PAUSE_SYM_EN 0x80 1594 1595 /* MAC speed valid values */ 1596 #define SPEED_DEFAULT 0x0 1597 #define SPEED_FORCED_10GB 0x1 1598 #define SPEED_FORCED_1GB 0x2 1599 #define SPEED_AUTONEG_10GB 0x3 1600 #define SPEED_AUTONEG_1GB 0x4 1601 #define SPEED_AUTONEG_100MB 0x5 1602 #define SPEED_AUTONEG_10GB_1GB 0x6 1603 #define SPEED_AUTONEG_10GB_1GB_100MB 0x7 1604 #define SPEED_AUTONEG_1GB_100MB 0x8 1605 #define SPEED_AUTONEG_10MB 0x9 1606 #define SPEED_AUTONEG_1GB_100MB_10MB 0xa 1607 #define SPEED_AUTONEG_100MB_10MB 0xb 1608 #define SPEED_FORCED_100MB 0xc 1609 #define SPEED_FORCED_10MB 0xd 1610 1611 struct be_cmd_req_get_phy_info { 1612 struct be_cmd_req_hdr hdr; 1613 u8 rsvd0[24]; 1614 }; 1615 1616 struct be_phy_info { 1617 u16 phy_type; 1618 u16 interface_type; 1619 u32 misc_params; 1620 u16 ext_phy_details; 1621 u16 rsvd; 1622 u16 auto_speeds_supported; 1623 u16 fixed_speeds_supported; 1624 u32 future_use[2]; 1625 }; 1626 1627 struct be_cmd_resp_get_phy_info { 1628 struct be_cmd_req_hdr hdr; 1629 struct be_phy_info phy_info; 1630 }; 1631 1632 /*********************** Set QOS ***********************/ 1633 1634 #define BE_QOS_BITS_NIC 1 1635 1636 struct be_cmd_req_set_qos { 1637 struct be_cmd_req_hdr hdr; 1638 u32 valid_bits; 1639 u32 max_bps_nic; 1640 u32 rsvd[7]; 1641 }; 1642 1643 /*********************** Controller Attributes ***********************/ 1644 struct mgmt_hba_attribs { 1645 u32 rsvd0[24]; 1646 u8 controller_model_number[32]; 1647 u32 rsvd1[16]; 1648 u32 controller_serial_number[8]; 1649 u32 rsvd2[55]; 1650 u8 rsvd3[3]; 1651 u8 phy_port; 1652 u32 rsvd4[13]; 1653 } __packed; 1654 1655 struct mgmt_controller_attrib { 1656 struct mgmt_hba_attribs hba_attribs; 1657 u32 rsvd0[2]; 1658 u16 rsvd1; 1659 u8 pci_func_num; 1660 u8 rsvd2; 1661 u32 rsvd3[7]; 1662 } __packed; 1663 1664 struct be_cmd_req_cntl_attribs { 1665 struct be_cmd_req_hdr hdr; 1666 }; 1667 1668 struct be_cmd_resp_cntl_attribs { 1669 struct be_cmd_resp_hdr hdr; 1670 struct mgmt_controller_attrib attribs; 1671 }; 1672 1673 /*********************** Set driver function ***********************/ 1674 #define CAPABILITY_SW_TIMESTAMPS 2 1675 #define CAPABILITY_BE3_NATIVE_ERX_API 4 1676 1677 struct be_cmd_req_set_func_cap { 1678 struct be_cmd_req_hdr hdr; 1679 u32 valid_cap_flags; 1680 u32 cap_flags; 1681 u8 rsvd[212]; 1682 }; 1683 1684 struct be_cmd_resp_set_func_cap { 1685 struct be_cmd_resp_hdr hdr; 1686 u32 valid_cap_flags; 1687 u32 cap_flags; 1688 u8 rsvd[212]; 1689 }; 1690 1691 /*********************** Function Privileges ***********************/ 1692 enum { 1693 BE_PRIV_DEFAULT = 0x1, 1694 BE_PRIV_LNKQUERY = 0x2, 1695 BE_PRIV_LNKSTATS = 0x4, 1696 BE_PRIV_LNKMGMT = 0x8, 1697 BE_PRIV_LNKDIAG = 0x10, 1698 BE_PRIV_UTILQUERY = 0x20, 1699 BE_PRIV_FILTMGMT = 0x40, 1700 BE_PRIV_IFACEMGMT = 0x80, 1701 BE_PRIV_VHADM = 0x100, 1702 BE_PRIV_DEVCFG = 0x200, 1703 BE_PRIV_DEVSEC = 0x400 1704 }; 1705 #define MAX_PRIVILEGES (BE_PRIV_VHADM | BE_PRIV_DEVCFG | \ 1706 BE_PRIV_DEVSEC) 1707 #define MIN_PRIVILEGES BE_PRIV_DEFAULT 1708 1709 struct be_cmd_priv_map { 1710 u8 opcode; 1711 u8 subsystem; 1712 u32 priv_mask; 1713 }; 1714 1715 struct be_cmd_req_get_fn_privileges { 1716 struct be_cmd_req_hdr hdr; 1717 u32 rsvd; 1718 }; 1719 1720 struct be_cmd_resp_get_fn_privileges { 1721 struct be_cmd_resp_hdr hdr; 1722 u32 privilege_mask; 1723 }; 1724 1725 struct be_cmd_req_set_fn_privileges { 1726 struct be_cmd_req_hdr hdr; 1727 u32 privileges; /* Used by BE3, SH-R */ 1728 u32 privileges_lancer; /* Used by Lancer */ 1729 }; 1730 1731 /******************** GET/SET_MACLIST **************************/ 1732 #define BE_MAX_MAC 64 1733 struct be_cmd_req_get_mac_list { 1734 struct be_cmd_req_hdr hdr; 1735 u8 mac_type; 1736 u8 perm_override; 1737 u16 iface_id; 1738 u32 mac_id; 1739 u32 rsvd[3]; 1740 } __packed; 1741 1742 struct get_list_macaddr { 1743 u16 mac_addr_size; 1744 union { 1745 u8 macaddr[6]; 1746 struct { 1747 u8 rsvd[2]; 1748 u32 mac_id; 1749 } __packed s_mac_id; 1750 } __packed mac_addr_id; 1751 } __packed; 1752 1753 struct be_cmd_resp_get_mac_list { 1754 struct be_cmd_resp_hdr hdr; 1755 struct get_list_macaddr fd_macaddr; /* Factory default mac */ 1756 struct get_list_macaddr macid_macaddr; /* soft mac */ 1757 u8 true_mac_count; 1758 u8 pseudo_mac_count; 1759 u8 mac_list_size; 1760 u8 rsvd; 1761 /* perm override mac */ 1762 struct get_list_macaddr macaddr_list[BE_MAX_MAC]; 1763 } __packed; 1764 1765 struct be_cmd_req_set_mac_list { 1766 struct be_cmd_req_hdr hdr; 1767 u8 mac_count; 1768 u8 rsvd1; 1769 u16 rsvd2; 1770 struct macaddr mac[BE_MAX_MAC]; 1771 } __packed; 1772 1773 /*********************** HSW Config ***********************/ 1774 #define PORT_FWD_TYPE_VEPA 0x3 1775 #define PORT_FWD_TYPE_VEB 0x2 1776 #define PORT_FWD_TYPE_PASSTHRU 0x1 1777 1778 #define ENABLE_MAC_SPOOFCHK 0x2 1779 #define DISABLE_MAC_SPOOFCHK 0x3 1780 1781 struct amap_set_hsw_context { 1782 u8 interface_id[16]; 1783 u8 rsvd0[8]; 1784 u8 mac_spoofchk[2]; 1785 u8 rsvd1[4]; 1786 u8 pvid_valid; 1787 u8 pport; 1788 u8 rsvd2[6]; 1789 u8 port_fwd_type[3]; 1790 u8 rsvd3[5]; 1791 u8 vlan_spoofchk[2]; 1792 u8 pvid[16]; 1793 u8 rsvd4[32]; 1794 u8 rsvd5[32]; 1795 u8 rsvd6[32]; 1796 } __packed; 1797 1798 struct be_cmd_req_set_hsw_config { 1799 struct be_cmd_req_hdr hdr; 1800 u8 context[sizeof(struct amap_set_hsw_context) / 8]; 1801 } __packed; 1802 1803 struct amap_get_hsw_req_context { 1804 u8 interface_id[16]; 1805 u8 rsvd0[14]; 1806 u8 pvid_valid; 1807 u8 pport; 1808 } __packed; 1809 1810 struct amap_get_hsw_resp_context { 1811 u8 rsvd0[6]; 1812 u8 port_fwd_type[3]; 1813 u8 rsvd1[5]; 1814 u8 spoofchk; 1815 u8 rsvd2; 1816 u8 pvid[16]; 1817 u8 rsvd3[32]; 1818 u8 rsvd4[32]; 1819 u8 rsvd5[32]; 1820 } __packed; 1821 1822 struct be_cmd_req_get_hsw_config { 1823 struct be_cmd_req_hdr hdr; 1824 u8 context[sizeof(struct amap_get_hsw_req_context) / 8]; 1825 } __packed; 1826 1827 struct be_cmd_resp_get_hsw_config { 1828 struct be_cmd_resp_hdr hdr; 1829 u8 context[sizeof(struct amap_get_hsw_resp_context) / 8]; 1830 u32 rsvd; 1831 }; 1832 1833 /******************* get port names ***************/ 1834 struct be_cmd_req_get_port_name { 1835 struct be_cmd_req_hdr hdr; 1836 u32 rsvd0; 1837 }; 1838 1839 struct be_cmd_resp_get_port_name { 1840 struct be_cmd_req_hdr hdr; 1841 u8 port_name[4]; 1842 }; 1843 1844 /*************** HW Stats Get v1 **********************************/ 1845 #define BE_TXP_SW_SZ 48 1846 struct be_port_rxf_stats_v1 { 1847 u32 rsvd0[12]; 1848 u32 rx_crc_errors; 1849 u32 rx_alignment_symbol_errors; 1850 u32 rx_pause_frames; 1851 u32 rx_priority_pause_frames; 1852 u32 rx_control_frames; 1853 u32 rx_in_range_errors; 1854 u32 rx_out_range_errors; 1855 u32 rx_frame_too_long; 1856 u32 rx_address_filtered; 1857 u32 rx_dropped_too_small; 1858 u32 rx_dropped_too_short; 1859 u32 rx_dropped_header_too_small; 1860 u32 rx_dropped_tcp_length; 1861 u32 rx_dropped_runt; 1862 u32 rsvd1[10]; 1863 u32 rx_ip_checksum_errs; 1864 u32 rx_tcp_checksum_errs; 1865 u32 rx_udp_checksum_errs; 1866 u32 rsvd2[7]; 1867 u32 rx_switched_unicast_packets; 1868 u32 rx_switched_multicast_packets; 1869 u32 rx_switched_broadcast_packets; 1870 u32 rsvd3[3]; 1871 u32 tx_pauseframes; 1872 u32 tx_priority_pauseframes; 1873 u32 tx_controlframes; 1874 u32 rsvd4[10]; 1875 u32 rxpp_fifo_overflow_drop; 1876 u32 rx_input_fifo_overflow_drop; 1877 u32 pmem_fifo_overflow_drop; 1878 u32 jabber_events; 1879 u32 rsvd5[3]; 1880 }; 1881 1882 1883 struct be_rxf_stats_v1 { 1884 struct be_port_rxf_stats_v1 port[4]; 1885 u32 rsvd0[2]; 1886 u32 rx_drops_no_pbuf; 1887 u32 rx_drops_no_txpb; 1888 u32 rx_drops_no_erx_descr; 1889 u32 rx_drops_no_tpre_descr; 1890 u32 rsvd1[6]; 1891 u32 rx_drops_too_many_frags; 1892 u32 rx_drops_invalid_ring; 1893 u32 forwarded_packets; 1894 u32 rx_drops_mtu; 1895 u32 rsvd2[14]; 1896 }; 1897 1898 struct be_erx_stats_v1 { 1899 u32 rx_drops_no_fragments[68]; /* dwordS 0 to 67*/ 1900 u32 rsvd[4]; 1901 }; 1902 1903 struct be_port_rxf_stats_v2 { 1904 u32 rsvd0[10]; 1905 u32 roce_bytes_received_lsd; 1906 u32 roce_bytes_received_msd; 1907 u32 rsvd1[5]; 1908 u32 roce_frames_received; 1909 u32 rx_crc_errors; 1910 u32 rx_alignment_symbol_errors; 1911 u32 rx_pause_frames; 1912 u32 rx_priority_pause_frames; 1913 u32 rx_control_frames; 1914 u32 rx_in_range_errors; 1915 u32 rx_out_range_errors; 1916 u32 rx_frame_too_long; 1917 u32 rx_address_filtered; 1918 u32 rx_dropped_too_small; 1919 u32 rx_dropped_too_short; 1920 u32 rx_dropped_header_too_small; 1921 u32 rx_dropped_tcp_length; 1922 u32 rx_dropped_runt; 1923 u32 rsvd2[10]; 1924 u32 rx_ip_checksum_errs; 1925 u32 rx_tcp_checksum_errs; 1926 u32 rx_udp_checksum_errs; 1927 u32 rsvd3[7]; 1928 u32 rx_switched_unicast_packets; 1929 u32 rx_switched_multicast_packets; 1930 u32 rx_switched_broadcast_packets; 1931 u32 rsvd4[3]; 1932 u32 tx_pauseframes; 1933 u32 tx_priority_pauseframes; 1934 u32 tx_controlframes; 1935 u32 rsvd5[10]; 1936 u32 rxpp_fifo_overflow_drop; 1937 u32 rx_input_fifo_overflow_drop; 1938 u32 pmem_fifo_overflow_drop; 1939 u32 jabber_events; 1940 u32 rsvd6[3]; 1941 u32 rx_drops_payload_size; 1942 u32 rx_drops_clipped_header; 1943 u32 rx_drops_crc; 1944 u32 roce_drops_payload_len; 1945 u32 roce_drops_crc; 1946 u32 rsvd7[19]; 1947 }; 1948 1949 struct be_rxf_stats_v2 { 1950 struct be_port_rxf_stats_v2 port[4]; 1951 u32 rsvd0[2]; 1952 u32 rx_drops_no_pbuf; 1953 u32 rx_drops_no_txpb; 1954 u32 rx_drops_no_erx_descr; 1955 u32 rx_drops_no_tpre_descr; 1956 u32 rsvd1[6]; 1957 u32 rx_drops_too_many_frags; 1958 u32 rx_drops_invalid_ring; 1959 u32 forwarded_packets; 1960 u32 rx_drops_mtu; 1961 u32 rsvd2[35]; 1962 }; 1963 1964 struct be_hw_stats_v1 { 1965 struct be_rxf_stats_v1 rxf; 1966 u32 rsvd0[BE_TXP_SW_SZ]; 1967 struct be_erx_stats_v1 erx; 1968 struct be_pmem_stats pmem; 1969 u32 rsvd1[18]; 1970 }; 1971 1972 struct be_cmd_req_get_stats_v1 { 1973 struct be_cmd_req_hdr hdr; 1974 u8 rsvd[sizeof(struct be_hw_stats_v1)]; 1975 }; 1976 1977 struct be_cmd_resp_get_stats_v1 { 1978 struct be_cmd_resp_hdr hdr; 1979 struct be_hw_stats_v1 hw_stats; 1980 }; 1981 1982 struct be_erx_stats_v2 { 1983 u32 rx_drops_no_fragments[136]; /* dwordS 0 to 135*/ 1984 u32 rsvd[3]; 1985 }; 1986 1987 struct be_hw_stats_v2 { 1988 struct be_rxf_stats_v2 rxf; 1989 u32 rsvd0[BE_TXP_SW_SZ]; 1990 struct be_erx_stats_v2 erx; 1991 struct be_pmem_stats pmem; 1992 u32 rsvd1[18]; 1993 }; 1994 1995 struct be_cmd_req_get_stats_v2 { 1996 struct be_cmd_req_hdr hdr; 1997 u8 rsvd[sizeof(struct be_hw_stats_v2)]; 1998 }; 1999 2000 struct be_cmd_resp_get_stats_v2 { 2001 struct be_cmd_resp_hdr hdr; 2002 struct be_hw_stats_v2 hw_stats; 2003 }; 2004 2005 /************** get fat capabilites *******************/ 2006 #define MAX_MODULES 27 2007 #define MAX_MODES 4 2008 #define MODE_UART 0 2009 #define FW_LOG_LEVEL_DEFAULT 48 2010 #define FW_LOG_LEVEL_FATAL 64 2011 2012 struct ext_fat_mode { 2013 u8 mode; 2014 u8 rsvd0; 2015 u16 port_mask; 2016 u32 dbg_lvl; 2017 u64 fun_mask; 2018 } __packed; 2019 2020 struct ext_fat_modules { 2021 u8 modules_str[32]; 2022 u32 modules_id; 2023 u32 num_modes; 2024 struct ext_fat_mode trace_lvl[MAX_MODES]; 2025 } __packed; 2026 2027 struct be_fat_conf_params { 2028 u32 max_log_entries; 2029 u32 log_entry_size; 2030 u8 log_type; 2031 u8 max_log_funs; 2032 u8 max_log_ports; 2033 u8 rsvd0; 2034 u32 supp_modes; 2035 u32 num_modules; 2036 struct ext_fat_modules module[MAX_MODULES]; 2037 } __packed; 2038 2039 struct be_cmd_req_get_ext_fat_caps { 2040 struct be_cmd_req_hdr hdr; 2041 u32 parameter_type; 2042 }; 2043 2044 struct be_cmd_resp_get_ext_fat_caps { 2045 struct be_cmd_resp_hdr hdr; 2046 struct be_fat_conf_params get_params; 2047 }; 2048 2049 struct be_cmd_req_set_ext_fat_caps { 2050 struct be_cmd_req_hdr hdr; 2051 struct be_fat_conf_params set_params; 2052 }; 2053 2054 #define RESOURCE_DESC_SIZE_V0 72 2055 #define RESOURCE_DESC_SIZE_V1 88 2056 #define PCIE_RESOURCE_DESC_TYPE_V0 0x40 2057 #define NIC_RESOURCE_DESC_TYPE_V0 0x41 2058 #define PCIE_RESOURCE_DESC_TYPE_V1 0x50 2059 #define NIC_RESOURCE_DESC_TYPE_V1 0x51 2060 #define PORT_RESOURCE_DESC_TYPE_V1 0x55 2061 #define MAX_RESOURCE_DESC 264 2062 2063 #define IF_CAPS_FLAGS_VALID_SHIFT 0 /* IF caps valid */ 2064 #define VFT_SHIFT 3 /* VF template */ 2065 #define IMM_SHIFT 6 /* Immediate */ 2066 #define NOSV_SHIFT 7 /* No save */ 2067 2068 struct be_res_desc_hdr { 2069 u8 desc_type; 2070 u8 desc_len; 2071 } __packed; 2072 2073 struct be_port_res_desc { 2074 struct be_res_desc_hdr hdr; 2075 u8 rsvd0; 2076 u8 flags; 2077 u8 link_num; 2078 u8 mc_type; 2079 u16 rsvd1; 2080 2081 #define NV_TYPE_MASK 0x3 /* bits 0-1 */ 2082 #define NV_TYPE_DISABLED 1 2083 #define NV_TYPE_VXLAN 3 2084 #define SOCVID_SHIFT 2 /* Strip outer vlan */ 2085 #define RCVID_SHIFT 4 /* Report vlan */ 2086 u8 nv_flags; 2087 u8 rsvd2; 2088 __le16 nv_port; /* vxlan/gre port */ 2089 u32 rsvd3[19]; 2090 } __packed; 2091 2092 struct be_pcie_res_desc { 2093 struct be_res_desc_hdr hdr; 2094 u8 rsvd0; 2095 u8 flags; 2096 u16 rsvd1; 2097 u8 pf_num; 2098 u8 rsvd2; 2099 u32 rsvd3; 2100 u8 sriov_state; 2101 u8 pf_state; 2102 u8 pf_type; 2103 u8 rsvd4; 2104 u16 num_vfs; 2105 u16 rsvd5; 2106 u32 rsvd6[17]; 2107 } __packed; 2108 2109 struct be_nic_res_desc { 2110 struct be_res_desc_hdr hdr; 2111 u8 rsvd1; 2112 2113 #define QUN_SHIFT 4 /* QoS is in absolute units */ 2114 u8 flags; 2115 u8 vf_num; 2116 u8 rsvd2; 2117 u8 pf_num; 2118 u8 rsvd3; 2119 u16 unicast_mac_count; 2120 u8 rsvd4[6]; 2121 u16 mcc_count; 2122 u16 vlan_count; 2123 u16 mcast_mac_count; 2124 u16 txq_count; 2125 u16 rq_count; 2126 u16 rssq_count; 2127 u16 lro_count; 2128 u16 cq_count; 2129 u16 toe_conn_count; 2130 u16 eq_count; 2131 u16 vlan_id; 2132 u16 iface_count; 2133 u32 cap_flags; 2134 u8 link_param; 2135 u8 rsvd6; 2136 u16 channel_id_param; 2137 u32 bw_min; 2138 u32 bw_max; 2139 u8 acpi_params; 2140 u8 wol_param; 2141 u16 rsvd7; 2142 u16 tunnel_iface_count; 2143 u16 direct_tenant_iface_count; 2144 u32 rsvd8[6]; 2145 } __packed; 2146 2147 /************ Multi-Channel type ***********/ 2148 enum mc_type { 2149 MC_NONE = 0x01, 2150 UMC = 0x02, 2151 FLEX10 = 0x03, 2152 vNIC1 = 0x04, 2153 nPAR = 0x05, 2154 UFP = 0x06, 2155 vNIC2 = 0x07 2156 }; 2157 2158 /* Is BE in a multi-channel mode */ 2159 static inline bool be_is_mc(struct be_adapter *adapter) 2160 { 2161 return adapter->mc_type > MC_NONE; 2162 } 2163 2164 struct be_cmd_req_get_func_config { 2165 struct be_cmd_req_hdr hdr; 2166 }; 2167 2168 struct be_cmd_resp_get_func_config { 2169 struct be_cmd_resp_hdr hdr; 2170 u32 desc_count; 2171 u8 func_param[MAX_RESOURCE_DESC * RESOURCE_DESC_SIZE_V1]; 2172 }; 2173 2174 enum { 2175 RESOURCE_LIMITS, 2176 RESOURCE_MODIFIABLE 2177 }; 2178 2179 struct be_cmd_req_get_profile_config { 2180 struct be_cmd_req_hdr hdr; 2181 u8 rsvd; 2182 #define ACTIVE_PROFILE_TYPE 0x2 2183 #define QUERY_MODIFIABLE_FIELDS_TYPE BIT(3) 2184 u8 type; 2185 u16 rsvd1; 2186 }; 2187 2188 struct be_cmd_resp_get_profile_config { 2189 struct be_cmd_resp_hdr hdr; 2190 __le16 desc_count; 2191 u16 rsvd; 2192 u8 func_param[MAX_RESOURCE_DESC * RESOURCE_DESC_SIZE_V1]; 2193 }; 2194 2195 #define FIELD_MODIFIABLE 0xFFFF 2196 struct be_cmd_req_set_profile_config { 2197 struct be_cmd_req_hdr hdr; 2198 u32 rsvd; 2199 u32 desc_count; 2200 u8 desc[2 * RESOURCE_DESC_SIZE_V1]; 2201 } __packed; 2202 2203 struct be_cmd_req_get_active_profile { 2204 struct be_cmd_req_hdr hdr; 2205 u32 rsvd; 2206 } __packed; 2207 2208 struct be_cmd_resp_get_active_profile { 2209 struct be_cmd_resp_hdr hdr; 2210 u16 active_profile_id; 2211 u16 next_profile_id; 2212 } __packed; 2213 2214 struct be_cmd_enable_disable_vf { 2215 struct be_cmd_req_hdr hdr; 2216 u8 enable; 2217 u8 rsvd[3]; 2218 }; 2219 2220 struct be_cmd_req_intr_set { 2221 struct be_cmd_req_hdr hdr; 2222 u8 intr_enabled; 2223 u8 rsvd[3]; 2224 }; 2225 2226 static inline bool check_privilege(struct be_adapter *adapter, u32 flags) 2227 { 2228 return flags & adapter->cmd_privileges ? true : false; 2229 } 2230 2231 /************** Get IFACE LIST *******************/ 2232 struct be_if_desc { 2233 u32 if_id; 2234 u32 cap_flags; 2235 u32 en_flags; 2236 }; 2237 2238 struct be_cmd_req_get_iface_list { 2239 struct be_cmd_req_hdr hdr; 2240 }; 2241 2242 struct be_cmd_resp_get_iface_list { 2243 struct be_cmd_req_hdr hdr; 2244 u32 if_cnt; 2245 struct be_if_desc if_desc; 2246 }; 2247 2248 /*************** Set logical link ********************/ 2249 #define PLINK_TRACK_SHIFT 8 2250 struct be_cmd_req_set_ll_link { 2251 struct be_cmd_req_hdr hdr; 2252 u32 link_config; /* Bit 0: UP_DOWN, Bit 9: PLINK */ 2253 }; 2254 2255 /************** Manage IFACE Filters *******************/ 2256 #define OP_CONVERT_NORMAL_TO_TUNNEL 0 2257 #define OP_CONVERT_TUNNEL_TO_NORMAL 1 2258 2259 struct be_cmd_req_manage_iface_filters { 2260 struct be_cmd_req_hdr hdr; 2261 u8 op; 2262 u8 rsvd0; 2263 u8 flags; 2264 u8 rsvd1; 2265 u32 tunnel_iface_id; 2266 u32 target_iface_id; 2267 u8 mac[6]; 2268 u16 vlan_tag; 2269 u32 tenant_id; 2270 u32 filter_id; 2271 u32 cap_flags; 2272 u32 cap_control_flags; 2273 } __packed; 2274 2275 int be_pci_fnum_get(struct be_adapter *adapter); 2276 int be_fw_wait_ready(struct be_adapter *adapter); 2277 int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr, 2278 bool permanent, u32 if_handle, u32 pmac_id); 2279 int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr, u32 if_id, 2280 u32 *pmac_id, u32 domain); 2281 int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, int pmac_id, 2282 u32 domain); 2283 int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags, 2284 u32 *if_handle, u32 domain); 2285 int be_cmd_if_destroy(struct be_adapter *adapter, int if_handle, u32 domain); 2286 int be_cmd_eq_create(struct be_adapter *adapter, struct be_eq_obj *eqo); 2287 int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq, 2288 struct be_queue_info *eq, bool no_delay, 2289 int num_cqe_dma_coalesce); 2290 int be_cmd_mccq_create(struct be_adapter *adapter, struct be_queue_info *mccq, 2291 struct be_queue_info *cq); 2292 int be_cmd_txq_create(struct be_adapter *adapter, struct be_tx_obj *txo); 2293 int be_cmd_rxq_create(struct be_adapter *adapter, struct be_queue_info *rxq, 2294 u16 cq_id, u16 frag_size, u32 if_id, u32 rss, u8 *rss_id); 2295 int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q, 2296 int type); 2297 int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q); 2298 int be_cmd_link_status_query(struct be_adapter *adapter, u16 *link_speed, 2299 u8 *link_status, u32 dom); 2300 int be_cmd_reset(struct be_adapter *adapter); 2301 int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd); 2302 int lancer_cmd_get_pport_stats(struct be_adapter *adapter, 2303 struct be_dma_mem *nonemb_cmd); 2304 int be_cmd_get_fw_ver(struct be_adapter *adapter); 2305 int be_cmd_modify_eqd(struct be_adapter *adapter, struct be_set_eqd *, int num); 2306 int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array, 2307 u32 num, u32 domain); 2308 int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 status); 2309 int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc); 2310 int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc); 2311 int be_cmd_query_fw_cfg(struct be_adapter *adapter); 2312 int be_cmd_reset_function(struct be_adapter *adapter); 2313 int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable, 2314 u32 rss_hash_opts, u16 table_size, const u8 *rss_hkey); 2315 int be_process_mcc(struct be_adapter *adapter); 2316 int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num, u8 beacon, 2317 u8 status, u8 state); 2318 int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, 2319 u32 *state); 2320 int be_cmd_read_port_transceiver_data(struct be_adapter *adapter, 2321 u8 page_num, u8 *data); 2322 int be_cmd_query_cable_type(struct be_adapter *adapter); 2323 int be_cmd_query_sfp_info(struct be_adapter *adapter); 2324 int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd, 2325 u32 flash_oper, u32 flash_opcode, u32 img_offset, 2326 u32 buf_size); 2327 int lancer_cmd_write_object(struct be_adapter *adapter, struct be_dma_mem *cmd, 2328 u32 data_size, u32 data_offset, 2329 const char *obj_name, u32 *data_written, 2330 u8 *change_status, u8 *addn_status); 2331 int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd, 2332 u32 data_size, u32 data_offset, const char *obj_name, 2333 u32 *data_read, u32 *eof, u8 *addn_status); 2334 int lancer_cmd_delete_object(struct be_adapter *adapter, const char *obj_name); 2335 int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc, 2336 u16 img_optype, u32 img_offset, u32 crc_offset); 2337 int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac, 2338 struct be_dma_mem *nonemb_cmd); 2339 int be_cmd_fw_init(struct be_adapter *adapter); 2340 int be_cmd_fw_clean(struct be_adapter *adapter); 2341 void be_async_mcc_enable(struct be_adapter *adapter); 2342 void be_async_mcc_disable(struct be_adapter *adapter); 2343 int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num, 2344 u32 loopback_type, u32 pkt_size, u32 num_pkts, 2345 u64 pattern); 2346 int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern, u32 byte_cnt, 2347 struct be_dma_mem *cmd); 2348 int be_cmd_get_seeprom_data(struct be_adapter *adapter, 2349 struct be_dma_mem *nonemb_cmd); 2350 int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num, 2351 u8 loopback_type, u8 enable); 2352 int be_cmd_get_phy_info(struct be_adapter *adapter); 2353 int be_cmd_config_qos(struct be_adapter *adapter, u32 max_rate, 2354 u16 link_speed, u8 domain); 2355 void be_detect_error(struct be_adapter *adapter); 2356 int be_cmd_get_die_temperature(struct be_adapter *adapter); 2357 int be_cmd_get_cntl_attributes(struct be_adapter *adapter); 2358 int be_cmd_req_native_mode(struct be_adapter *adapter); 2359 int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size); 2360 int be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf); 2361 int be_cmd_get_fn_privileges(struct be_adapter *adapter, u32 *privilege, 2362 u32 domain); 2363 int be_cmd_set_fn_privileges(struct be_adapter *adapter, u32 privileges, 2364 u32 vf_num); 2365 int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac, 2366 bool *pmac_id_active, u32 *pmac_id, 2367 u32 if_handle, u8 domain); 2368 int be_cmd_get_active_mac(struct be_adapter *adapter, u32 pmac_id, u8 *mac, 2369 u32 if_handle, bool active, u32 domain); 2370 int be_cmd_get_perm_mac(struct be_adapter *adapter, u8 *mac); 2371 int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array, u8 mac_count, 2372 u32 domain); 2373 int be_cmd_set_mac(struct be_adapter *adapter, u8 *mac, int if_id, u32 dom); 2374 int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid, u32 domain, 2375 u16 intf_id, u16 hsw_mode, u8 spoofchk); 2376 int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid, u32 domain, 2377 u16 intf_id, u8 *mode, bool *spoofchk); 2378 int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter); 2379 int be_cmd_set_fw_log_level(struct be_adapter *adapter, u32 level); 2380 int be_cmd_get_fw_log_level(struct be_adapter *adapter); 2381 int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter, 2382 struct be_dma_mem *cmd); 2383 int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter, 2384 struct be_dma_mem *cmd, 2385 struct be_fat_conf_params *cfgs); 2386 int lancer_physdev_ctrl(struct be_adapter *adapter, u32 mask); 2387 int lancer_initiate_dump(struct be_adapter *adapter); 2388 int lancer_delete_dump(struct be_adapter *adapter); 2389 bool dump_present(struct be_adapter *adapter); 2390 int lancer_test_and_set_rdy_state(struct be_adapter *adapter); 2391 int be_cmd_query_port_name(struct be_adapter *adapter); 2392 int be_cmd_get_func_config(struct be_adapter *adapter, 2393 struct be_resources *res); 2394 int be_cmd_get_profile_config(struct be_adapter *adapter, 2395 struct be_resources *res, u8 query, u8 domain); 2396 int be_cmd_get_active_profile(struct be_adapter *adapter, u16 *profile); 2397 int be_cmd_get_if_id(struct be_adapter *adapter, struct be_vf_cfg *vf_cfg, 2398 int vf_num); 2399 int be_cmd_enable_vf(struct be_adapter *adapter, u8 domain); 2400 int be_cmd_intr_set(struct be_adapter *adapter, bool intr_enable); 2401 int be_cmd_set_logical_link_config(struct be_adapter *adapter, 2402 int link_state, u8 domain); 2403 int be_cmd_set_vxlan_port(struct be_adapter *adapter, __be16 port); 2404 int be_cmd_manage_iface(struct be_adapter *adapter, u32 iface, u8 op); 2405 int be_cmd_set_sriov_config(struct be_adapter *adapter, 2406 struct be_resources res, u16 num_vfs, 2407 u16 num_vf_qs); 2408