1 /* 2 * Copyright (C) 2005 - 2014 Emulex 3 * All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License version 2 7 * as published by the Free Software Foundation. The full GNU General 8 * Public License is included in this distribution in the file called COPYING. 9 * 10 * Contact Information: 11 * linux-drivers@emulex.com 12 * 13 * Emulex 14 * 3333 Susan Street 15 * Costa Mesa, CA 92626 16 */ 17 18 /* 19 * The driver sends configuration and managements command requests to the 20 * firmware in the BE. These requests are communicated to the processor 21 * using Work Request Blocks (WRBs) submitted to the MCC-WRB ring or via one 22 * WRB inside a MAILBOX. 23 * The commands are serviced by the ARM processor in the BladeEngine's MPU. 24 */ 25 26 struct be_sge { 27 u32 pa_lo; 28 u32 pa_hi; 29 u32 len; 30 }; 31 32 #define MCC_WRB_EMBEDDED_MASK 1 /* bit 0 of dword 0*/ 33 #define MCC_WRB_SGE_CNT_SHIFT 3 /* bits 3 - 7 of dword 0 */ 34 #define MCC_WRB_SGE_CNT_MASK 0x1F /* bits 3 - 7 of dword 0 */ 35 struct be_mcc_wrb { 36 u32 embedded; /* dword 0 */ 37 u32 payload_length; /* dword 1 */ 38 u32 tag0; /* dword 2 */ 39 u32 tag1; /* dword 3 */ 40 u32 rsvd; /* dword 4 */ 41 union { 42 u8 embedded_payload[236]; /* used by embedded cmds */ 43 struct be_sge sgl[19]; /* used by non-embedded cmds */ 44 } payload; 45 }; 46 47 #define CQE_FLAGS_VALID_MASK BIT(31) 48 #define CQE_FLAGS_ASYNC_MASK BIT(30) 49 #define CQE_FLAGS_COMPLETED_MASK BIT(28) 50 #define CQE_FLAGS_CONSUMED_MASK BIT(27) 51 52 /* Completion Status */ 53 enum mcc_base_status { 54 MCC_STATUS_SUCCESS = 0, 55 MCC_STATUS_FAILED = 1, 56 MCC_STATUS_ILLEGAL_REQUEST = 2, 57 MCC_STATUS_ILLEGAL_FIELD = 3, 58 MCC_STATUS_INSUFFICIENT_BUFFER = 4, 59 MCC_STATUS_UNAUTHORIZED_REQUEST = 5, 60 MCC_STATUS_NOT_SUPPORTED = 66, 61 MCC_STATUS_FEATURE_NOT_SUPPORTED = 68 62 }; 63 64 /* Additional status */ 65 enum mcc_addl_status { 66 MCC_ADDL_STATUS_INSUFFICIENT_RESOURCES = 0x16, 67 MCC_ADDL_STATUS_FLASH_IMAGE_CRC_MISMATCH = 0x4d, 68 MCC_ADDL_STATUS_TOO_MANY_INTERFACES = 0x4a 69 }; 70 71 #define CQE_BASE_STATUS_MASK 0xFFFF 72 #define CQE_BASE_STATUS_SHIFT 0 /* bits 0 - 15 */ 73 #define CQE_ADDL_STATUS_MASK 0xFF 74 #define CQE_ADDL_STATUS_SHIFT 16 /* bits 16 - 31 */ 75 76 #define base_status(status) \ 77 ((enum mcc_base_status) \ 78 (status > 0 ? (status & CQE_BASE_STATUS_MASK) : 0)) 79 #define addl_status(status) \ 80 ((enum mcc_addl_status) \ 81 (status > 0 ? (status >> CQE_ADDL_STATUS_SHIFT) & \ 82 CQE_ADDL_STATUS_MASK : 0)) 83 84 struct be_mcc_compl { 85 u32 status; /* dword 0 */ 86 u32 tag0; /* dword 1 */ 87 u32 tag1; /* dword 2 */ 88 u32 flags; /* dword 3 */ 89 }; 90 91 /* When the async bit of mcc_compl flags is set, flags 92 * is interpreted as follows: 93 */ 94 #define ASYNC_EVENT_CODE_SHIFT 8 /* bits 8 - 15 */ 95 #define ASYNC_EVENT_CODE_MASK 0xFF 96 #define ASYNC_EVENT_TYPE_SHIFT 16 97 #define ASYNC_EVENT_TYPE_MASK 0xFF 98 #define ASYNC_EVENT_CODE_LINK_STATE 0x1 99 #define ASYNC_EVENT_CODE_GRP_5 0x5 100 #define ASYNC_EVENT_QOS_SPEED 0x1 101 #define ASYNC_EVENT_COS_PRIORITY 0x2 102 #define ASYNC_EVENT_PVID_STATE 0x3 103 #define ASYNC_EVENT_CODE_QNQ 0x6 104 #define ASYNC_DEBUG_EVENT_TYPE_QNQ 1 105 #define ASYNC_EVENT_CODE_SLIPORT 0x11 106 #define ASYNC_EVENT_PORT_MISCONFIG 0x9 107 108 enum { 109 LINK_DOWN = 0x0, 110 LINK_UP = 0x1 111 }; 112 #define LINK_STATUS_MASK 0x1 113 #define LOGICAL_LINK_STATUS_MASK 0x2 114 115 /* When the event code of compl->flags is link-state, the mcc_compl 116 * must be interpreted as follows 117 */ 118 struct be_async_event_link_state { 119 u8 physical_port; 120 u8 port_link_status; 121 u8 port_duplex; 122 u8 port_speed; 123 u8 port_fault; 124 u8 rsvd0[7]; 125 u32 flags; 126 } __packed; 127 128 /* When the event code of compl->flags is GRP-5 and event_type is QOS_SPEED 129 * the mcc_compl must be interpreted as follows 130 */ 131 struct be_async_event_grp5_qos_link_speed { 132 u8 physical_port; 133 u8 rsvd[5]; 134 u16 qos_link_speed; 135 u32 event_tag; 136 u32 flags; 137 } __packed; 138 139 /* When the event code of compl->flags is GRP5 and event type is 140 * CoS-Priority, the mcc_compl must be interpreted as follows 141 */ 142 struct be_async_event_grp5_cos_priority { 143 u8 physical_port; 144 u8 available_priority_bmap; 145 u8 reco_default_priority; 146 u8 valid; 147 u8 rsvd0; 148 u8 event_tag; 149 u32 flags; 150 } __packed; 151 152 /* When the event code of compl->flags is GRP5 and event type is 153 * PVID state, the mcc_compl must be interpreted as follows 154 */ 155 struct be_async_event_grp5_pvid_state { 156 u8 enabled; 157 u8 rsvd0; 158 u16 tag; 159 u32 event_tag; 160 u32 rsvd1; 161 u32 flags; 162 } __packed; 163 164 /* async event indicating outer VLAN tag in QnQ */ 165 struct be_async_event_qnq { 166 u8 valid; /* Indicates if outer VLAN is valid */ 167 u8 rsvd0; 168 u16 vlan_tag; 169 u32 event_tag; 170 u8 rsvd1[4]; 171 u32 flags; 172 } __packed; 173 174 #define INCOMPATIBLE_SFP 0x3 175 /* async event indicating misconfigured port */ 176 struct be_async_event_misconfig_port { 177 u32 event_data_word1; 178 u32 event_data_word2; 179 u32 rsvd0; 180 u32 flags; 181 } __packed; 182 183 struct be_mcc_mailbox { 184 struct be_mcc_wrb wrb; 185 struct be_mcc_compl compl; 186 }; 187 188 #define CMD_SUBSYSTEM_COMMON 0x1 189 #define CMD_SUBSYSTEM_ETH 0x3 190 #define CMD_SUBSYSTEM_LOWLEVEL 0xb 191 192 #define OPCODE_COMMON_NTWK_MAC_QUERY 1 193 #define OPCODE_COMMON_NTWK_MAC_SET 2 194 #define OPCODE_COMMON_NTWK_MULTICAST_SET 3 195 #define OPCODE_COMMON_NTWK_VLAN_CONFIG 4 196 #define OPCODE_COMMON_NTWK_LINK_STATUS_QUERY 5 197 #define OPCODE_COMMON_READ_FLASHROM 6 198 #define OPCODE_COMMON_WRITE_FLASHROM 7 199 #define OPCODE_COMMON_CQ_CREATE 12 200 #define OPCODE_COMMON_EQ_CREATE 13 201 #define OPCODE_COMMON_MCC_CREATE 21 202 #define OPCODE_COMMON_SET_QOS 28 203 #define OPCODE_COMMON_MCC_CREATE_EXT 90 204 #define OPCODE_COMMON_SEEPROM_READ 30 205 #define OPCODE_COMMON_GET_CNTL_ATTRIBUTES 32 206 #define OPCODE_COMMON_NTWK_RX_FILTER 34 207 #define OPCODE_COMMON_GET_FW_VERSION 35 208 #define OPCODE_COMMON_SET_FLOW_CONTROL 36 209 #define OPCODE_COMMON_GET_FLOW_CONTROL 37 210 #define OPCODE_COMMON_SET_FRAME_SIZE 39 211 #define OPCODE_COMMON_MODIFY_EQ_DELAY 41 212 #define OPCODE_COMMON_FIRMWARE_CONFIG 42 213 #define OPCODE_COMMON_NTWK_INTERFACE_CREATE 50 214 #define OPCODE_COMMON_NTWK_INTERFACE_DESTROY 51 215 #define OPCODE_COMMON_MCC_DESTROY 53 216 #define OPCODE_COMMON_CQ_DESTROY 54 217 #define OPCODE_COMMON_EQ_DESTROY 55 218 #define OPCODE_COMMON_QUERY_FIRMWARE_CONFIG 58 219 #define OPCODE_COMMON_NTWK_PMAC_ADD 59 220 #define OPCODE_COMMON_NTWK_PMAC_DEL 60 221 #define OPCODE_COMMON_FUNCTION_RESET 61 222 #define OPCODE_COMMON_MANAGE_FAT 68 223 #define OPCODE_COMMON_ENABLE_DISABLE_BEACON 69 224 #define OPCODE_COMMON_GET_BEACON_STATE 70 225 #define OPCODE_COMMON_READ_TRANSRECV_DATA 73 226 #define OPCODE_COMMON_GET_PORT_NAME 77 227 #define OPCODE_COMMON_SET_LOGICAL_LINK_CONFIG 80 228 #define OPCODE_COMMON_SET_INTERRUPT_ENABLE 89 229 #define OPCODE_COMMON_SET_FN_PRIVILEGES 100 230 #define OPCODE_COMMON_GET_PHY_DETAILS 102 231 #define OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP 103 232 #define OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES 121 233 #define OPCODE_COMMON_GET_EXT_FAT_CAPABILITES 125 234 #define OPCODE_COMMON_SET_EXT_FAT_CAPABILITES 126 235 #define OPCODE_COMMON_GET_MAC_LIST 147 236 #define OPCODE_COMMON_SET_MAC_LIST 148 237 #define OPCODE_COMMON_GET_HSW_CONFIG 152 238 #define OPCODE_COMMON_GET_FUNC_CONFIG 160 239 #define OPCODE_COMMON_GET_PROFILE_CONFIG 164 240 #define OPCODE_COMMON_SET_PROFILE_CONFIG 165 241 #define OPCODE_COMMON_GET_ACTIVE_PROFILE 167 242 #define OPCODE_COMMON_SET_HSW_CONFIG 153 243 #define OPCODE_COMMON_GET_FN_PRIVILEGES 170 244 #define OPCODE_COMMON_READ_OBJECT 171 245 #define OPCODE_COMMON_WRITE_OBJECT 172 246 #define OPCODE_COMMON_DELETE_OBJECT 174 247 #define OPCODE_COMMON_MANAGE_IFACE_FILTERS 193 248 #define OPCODE_COMMON_GET_IFACE_LIST 194 249 #define OPCODE_COMMON_ENABLE_DISABLE_VF 196 250 251 #define OPCODE_ETH_RSS_CONFIG 1 252 #define OPCODE_ETH_ACPI_CONFIG 2 253 #define OPCODE_ETH_PROMISCUOUS 3 254 #define OPCODE_ETH_GET_STATISTICS 4 255 #define OPCODE_ETH_TX_CREATE 7 256 #define OPCODE_ETH_RX_CREATE 8 257 #define OPCODE_ETH_TX_DESTROY 9 258 #define OPCODE_ETH_RX_DESTROY 10 259 #define OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG 12 260 #define OPCODE_ETH_GET_PPORT_STATS 18 261 262 #define OPCODE_LOWLEVEL_HOST_DDR_DMA 17 263 #define OPCODE_LOWLEVEL_LOOPBACK_TEST 18 264 #define OPCODE_LOWLEVEL_SET_LOOPBACK_MODE 19 265 266 struct be_cmd_req_hdr { 267 u8 opcode; /* dword 0 */ 268 u8 subsystem; /* dword 0 */ 269 u8 port_number; /* dword 0 */ 270 u8 domain; /* dword 0 */ 271 u32 timeout; /* dword 1 */ 272 u32 request_length; /* dword 2 */ 273 u8 version; /* dword 3 */ 274 u8 rsvd[3]; /* dword 3 */ 275 }; 276 277 #define RESP_HDR_INFO_OPCODE_SHIFT 0 /* bits 0 - 7 */ 278 #define RESP_HDR_INFO_SUBSYS_SHIFT 8 /* bits 8 - 15 */ 279 struct be_cmd_resp_hdr { 280 u8 opcode; /* dword 0 */ 281 u8 subsystem; /* dword 0 */ 282 u8 rsvd[2]; /* dword 0 */ 283 u8 base_status; /* dword 1 */ 284 u8 addl_status; /* dword 1 */ 285 u8 rsvd1[2]; /* dword 1 */ 286 u32 response_length; /* dword 2 */ 287 u32 actual_resp_len; /* dword 3 */ 288 }; 289 290 struct phys_addr { 291 u32 lo; 292 u32 hi; 293 }; 294 295 /************************** 296 * BE Command definitions * 297 **************************/ 298 299 /* Pseudo amap definition in which each bit of the actual structure is defined 300 * as a byte: used to calculate offset/shift/mask of each field */ 301 struct amap_eq_context { 302 u8 cidx[13]; /* dword 0*/ 303 u8 rsvd0[3]; /* dword 0*/ 304 u8 epidx[13]; /* dword 0*/ 305 u8 valid; /* dword 0*/ 306 u8 rsvd1; /* dword 0*/ 307 u8 size; /* dword 0*/ 308 u8 pidx[13]; /* dword 1*/ 309 u8 rsvd2[3]; /* dword 1*/ 310 u8 pd[10]; /* dword 1*/ 311 u8 count[3]; /* dword 1*/ 312 u8 solevent; /* dword 1*/ 313 u8 stalled; /* dword 1*/ 314 u8 armed; /* dword 1*/ 315 u8 rsvd3[4]; /* dword 2*/ 316 u8 func[8]; /* dword 2*/ 317 u8 rsvd4; /* dword 2*/ 318 u8 delaymult[10]; /* dword 2*/ 319 u8 rsvd5[2]; /* dword 2*/ 320 u8 phase[2]; /* dword 2*/ 321 u8 nodelay; /* dword 2*/ 322 u8 rsvd6[4]; /* dword 2*/ 323 u8 rsvd7[32]; /* dword 3*/ 324 } __packed; 325 326 struct be_cmd_req_eq_create { 327 struct be_cmd_req_hdr hdr; 328 u16 num_pages; /* sword */ 329 u16 rsvd0; /* sword */ 330 u8 context[sizeof(struct amap_eq_context) / 8]; 331 struct phys_addr pages[8]; 332 } __packed; 333 334 struct be_cmd_resp_eq_create { 335 struct be_cmd_resp_hdr resp_hdr; 336 u16 eq_id; /* sword */ 337 u16 msix_idx; /* available only in v2 */ 338 } __packed; 339 340 /******************** Mac query ***************************/ 341 enum { 342 MAC_ADDRESS_TYPE_STORAGE = 0x0, 343 MAC_ADDRESS_TYPE_NETWORK = 0x1, 344 MAC_ADDRESS_TYPE_PD = 0x2, 345 MAC_ADDRESS_TYPE_MANAGEMENT = 0x3 346 }; 347 348 struct mac_addr { 349 u16 size_of_struct; 350 u8 addr[ETH_ALEN]; 351 } __packed; 352 353 struct be_cmd_req_mac_query { 354 struct be_cmd_req_hdr hdr; 355 u8 type; 356 u8 permanent; 357 u16 if_id; 358 u32 pmac_id; 359 } __packed; 360 361 struct be_cmd_resp_mac_query { 362 struct be_cmd_resp_hdr hdr; 363 struct mac_addr mac; 364 }; 365 366 /******************** PMac Add ***************************/ 367 struct be_cmd_req_pmac_add { 368 struct be_cmd_req_hdr hdr; 369 u32 if_id; 370 u8 mac_address[ETH_ALEN]; 371 u8 rsvd0[2]; 372 } __packed; 373 374 struct be_cmd_resp_pmac_add { 375 struct be_cmd_resp_hdr hdr; 376 u32 pmac_id; 377 }; 378 379 /******************** PMac Del ***************************/ 380 struct be_cmd_req_pmac_del { 381 struct be_cmd_req_hdr hdr; 382 u32 if_id; 383 u32 pmac_id; 384 }; 385 386 /******************** Create CQ ***************************/ 387 /* Pseudo amap definition in which each bit of the actual structure is defined 388 * as a byte: used to calculate offset/shift/mask of each field */ 389 struct amap_cq_context_be { 390 u8 cidx[11]; /* dword 0*/ 391 u8 rsvd0; /* dword 0*/ 392 u8 coalescwm[2]; /* dword 0*/ 393 u8 nodelay; /* dword 0*/ 394 u8 epidx[11]; /* dword 0*/ 395 u8 rsvd1; /* dword 0*/ 396 u8 count[2]; /* dword 0*/ 397 u8 valid; /* dword 0*/ 398 u8 solevent; /* dword 0*/ 399 u8 eventable; /* dword 0*/ 400 u8 pidx[11]; /* dword 1*/ 401 u8 rsvd2; /* dword 1*/ 402 u8 pd[10]; /* dword 1*/ 403 u8 eqid[8]; /* dword 1*/ 404 u8 stalled; /* dword 1*/ 405 u8 armed; /* dword 1*/ 406 u8 rsvd3[4]; /* dword 2*/ 407 u8 func[8]; /* dword 2*/ 408 u8 rsvd4[20]; /* dword 2*/ 409 u8 rsvd5[32]; /* dword 3*/ 410 } __packed; 411 412 struct amap_cq_context_v2 { 413 u8 rsvd0[12]; /* dword 0*/ 414 u8 coalescwm[2]; /* dword 0*/ 415 u8 nodelay; /* dword 0*/ 416 u8 rsvd1[12]; /* dword 0*/ 417 u8 count[2]; /* dword 0*/ 418 u8 valid; /* dword 0*/ 419 u8 rsvd2; /* dword 0*/ 420 u8 eventable; /* dword 0*/ 421 u8 eqid[16]; /* dword 1*/ 422 u8 rsvd3[15]; /* dword 1*/ 423 u8 armed; /* dword 1*/ 424 u8 rsvd4[32]; /* dword 2*/ 425 u8 rsvd5[32]; /* dword 3*/ 426 } __packed; 427 428 struct be_cmd_req_cq_create { 429 struct be_cmd_req_hdr hdr; 430 u16 num_pages; 431 u8 page_size; 432 u8 rsvd0; 433 u8 context[sizeof(struct amap_cq_context_be) / 8]; 434 struct phys_addr pages[8]; 435 } __packed; 436 437 438 struct be_cmd_resp_cq_create { 439 struct be_cmd_resp_hdr hdr; 440 u16 cq_id; 441 u16 rsvd0; 442 } __packed; 443 444 struct be_cmd_req_get_fat { 445 struct be_cmd_req_hdr hdr; 446 u32 fat_operation; 447 u32 read_log_offset; 448 u32 read_log_length; 449 u32 data_buffer_size; 450 u32 data_buffer[1]; 451 } __packed; 452 453 struct be_cmd_resp_get_fat { 454 struct be_cmd_resp_hdr hdr; 455 u32 log_size; 456 u32 read_log_length; 457 u32 rsvd[2]; 458 u32 data_buffer[1]; 459 } __packed; 460 461 462 /******************** Create MCCQ ***************************/ 463 /* Pseudo amap definition in which each bit of the actual structure is defined 464 * as a byte: used to calculate offset/shift/mask of each field */ 465 struct amap_mcc_context_be { 466 u8 con_index[14]; 467 u8 rsvd0[2]; 468 u8 ring_size[4]; 469 u8 fetch_wrb; 470 u8 fetch_r2t; 471 u8 cq_id[10]; 472 u8 prod_index[14]; 473 u8 fid[8]; 474 u8 pdid[9]; 475 u8 valid; 476 u8 rsvd1[32]; 477 u8 rsvd2[32]; 478 } __packed; 479 480 struct amap_mcc_context_v1 { 481 u8 async_cq_id[16]; 482 u8 ring_size[4]; 483 u8 rsvd0[12]; 484 u8 rsvd1[31]; 485 u8 valid; 486 u8 async_cq_valid[1]; 487 u8 rsvd2[31]; 488 u8 rsvd3[32]; 489 } __packed; 490 491 struct be_cmd_req_mcc_create { 492 struct be_cmd_req_hdr hdr; 493 u16 num_pages; 494 u16 cq_id; 495 u8 context[sizeof(struct amap_mcc_context_be) / 8]; 496 struct phys_addr pages[8]; 497 } __packed; 498 499 struct be_cmd_req_mcc_ext_create { 500 struct be_cmd_req_hdr hdr; 501 u16 num_pages; 502 u16 cq_id; 503 u32 async_event_bitmap[1]; 504 u8 context[sizeof(struct amap_mcc_context_v1) / 8]; 505 struct phys_addr pages[8]; 506 } __packed; 507 508 struct be_cmd_resp_mcc_create { 509 struct be_cmd_resp_hdr hdr; 510 u16 id; 511 u16 rsvd0; 512 } __packed; 513 514 /******************** Create TxQ ***************************/ 515 #define BE_ETH_TX_RING_TYPE_STANDARD 2 516 #define BE_ULP1_NUM 1 517 518 struct be_cmd_req_eth_tx_create { 519 struct be_cmd_req_hdr hdr; 520 u8 num_pages; 521 u8 ulp_num; 522 u16 type; 523 u16 if_id; 524 u8 queue_size; 525 u8 rsvd0; 526 u32 rsvd1; 527 u16 cq_id; 528 u16 rsvd2; 529 u32 rsvd3[13]; 530 struct phys_addr pages[8]; 531 } __packed; 532 533 struct be_cmd_resp_eth_tx_create { 534 struct be_cmd_resp_hdr hdr; 535 u16 cid; 536 u16 rid; 537 u32 db_offset; 538 u32 rsvd0[4]; 539 } __packed; 540 541 /******************** Create RxQ ***************************/ 542 struct be_cmd_req_eth_rx_create { 543 struct be_cmd_req_hdr hdr; 544 u16 cq_id; 545 u8 frag_size; 546 u8 num_pages; 547 struct phys_addr pages[2]; 548 u32 interface_id; 549 u16 max_frame_size; 550 u16 rsvd0; 551 u32 rss_queue; 552 } __packed; 553 554 struct be_cmd_resp_eth_rx_create { 555 struct be_cmd_resp_hdr hdr; 556 u16 id; 557 u8 rss_id; 558 u8 rsvd0; 559 } __packed; 560 561 /******************** Q Destroy ***************************/ 562 /* Type of Queue to be destroyed */ 563 enum { 564 QTYPE_EQ = 1, 565 QTYPE_CQ, 566 QTYPE_TXQ, 567 QTYPE_RXQ, 568 QTYPE_MCCQ 569 }; 570 571 struct be_cmd_req_q_destroy { 572 struct be_cmd_req_hdr hdr; 573 u16 id; 574 u16 bypass_flush; /* valid only for rx q destroy */ 575 } __packed; 576 577 /************ I/f Create (it's actually I/f Config Create)**********/ 578 579 /* Capability flags for the i/f */ 580 enum be_if_flags { 581 BE_IF_FLAGS_RSS = 0x4, 582 BE_IF_FLAGS_PROMISCUOUS = 0x8, 583 BE_IF_FLAGS_BROADCAST = 0x10, 584 BE_IF_FLAGS_UNTAGGED = 0x20, 585 BE_IF_FLAGS_ULP = 0x40, 586 BE_IF_FLAGS_VLAN_PROMISCUOUS = 0x80, 587 BE_IF_FLAGS_VLAN = 0x100, 588 BE_IF_FLAGS_MCAST_PROMISCUOUS = 0x200, 589 BE_IF_FLAGS_PASS_L2_ERRORS = 0x400, 590 BE_IF_FLAGS_PASS_L3L4_ERRORS = 0x800, 591 BE_IF_FLAGS_MULTICAST = 0x1000 592 }; 593 594 #define BE_IF_CAP_FLAGS_WANT (BE_IF_FLAGS_RSS | BE_IF_FLAGS_PROMISCUOUS |\ 595 BE_IF_FLAGS_BROADCAST | BE_IF_FLAGS_VLAN_PROMISCUOUS |\ 596 BE_IF_FLAGS_VLAN | BE_IF_FLAGS_MCAST_PROMISCUOUS |\ 597 BE_IF_FLAGS_PASS_L3L4_ERRORS | BE_IF_FLAGS_MULTICAST |\ 598 BE_IF_FLAGS_UNTAGGED) 599 600 #define BE_IF_FLAGS_ALL_PROMISCUOUS (BE_IF_FLAGS_PROMISCUOUS | \ 601 BE_IF_FLAGS_VLAN_PROMISCUOUS |\ 602 BE_IF_FLAGS_MCAST_PROMISCUOUS) 603 604 /* An RX interface is an object with one or more MAC addresses and 605 * filtering capabilities. */ 606 struct be_cmd_req_if_create { 607 struct be_cmd_req_hdr hdr; 608 u32 version; /* ignore currently */ 609 u32 capability_flags; 610 u32 enable_flags; 611 u8 mac_addr[ETH_ALEN]; 612 u8 rsvd0; 613 u8 pmac_invalid; /* if set, don't attach the mac addr to the i/f */ 614 u32 vlan_tag; /* not used currently */ 615 } __packed; 616 617 struct be_cmd_resp_if_create { 618 struct be_cmd_resp_hdr hdr; 619 u32 interface_id; 620 u32 pmac_id; 621 }; 622 623 /****** I/f Destroy(it's actually I/f Config Destroy )**********/ 624 struct be_cmd_req_if_destroy { 625 struct be_cmd_req_hdr hdr; 626 u32 interface_id; 627 }; 628 629 /*************** HW Stats Get **********************************/ 630 struct be_port_rxf_stats_v0 { 631 u32 rx_bytes_lsd; /* dword 0*/ 632 u32 rx_bytes_msd; /* dword 1*/ 633 u32 rx_total_frames; /* dword 2*/ 634 u32 rx_unicast_frames; /* dword 3*/ 635 u32 rx_multicast_frames; /* dword 4*/ 636 u32 rx_broadcast_frames; /* dword 5*/ 637 u32 rx_crc_errors; /* dword 6*/ 638 u32 rx_alignment_symbol_errors; /* dword 7*/ 639 u32 rx_pause_frames; /* dword 8*/ 640 u32 rx_control_frames; /* dword 9*/ 641 u32 rx_in_range_errors; /* dword 10*/ 642 u32 rx_out_range_errors; /* dword 11*/ 643 u32 rx_frame_too_long; /* dword 12*/ 644 u32 rx_address_filtered; /* dword 13*/ 645 u32 rx_vlan_filtered; /* dword 14*/ 646 u32 rx_dropped_too_small; /* dword 15*/ 647 u32 rx_dropped_too_short; /* dword 16*/ 648 u32 rx_dropped_header_too_small; /* dword 17*/ 649 u32 rx_dropped_tcp_length; /* dword 18*/ 650 u32 rx_dropped_runt; /* dword 19*/ 651 u32 rx_64_byte_packets; /* dword 20*/ 652 u32 rx_65_127_byte_packets; /* dword 21*/ 653 u32 rx_128_256_byte_packets; /* dword 22*/ 654 u32 rx_256_511_byte_packets; /* dword 23*/ 655 u32 rx_512_1023_byte_packets; /* dword 24*/ 656 u32 rx_1024_1518_byte_packets; /* dword 25*/ 657 u32 rx_1519_2047_byte_packets; /* dword 26*/ 658 u32 rx_2048_4095_byte_packets; /* dword 27*/ 659 u32 rx_4096_8191_byte_packets; /* dword 28*/ 660 u32 rx_8192_9216_byte_packets; /* dword 29*/ 661 u32 rx_ip_checksum_errs; /* dword 30*/ 662 u32 rx_tcp_checksum_errs; /* dword 31*/ 663 u32 rx_udp_checksum_errs; /* dword 32*/ 664 u32 rx_non_rss_packets; /* dword 33*/ 665 u32 rx_ipv4_packets; /* dword 34*/ 666 u32 rx_ipv6_packets; /* dword 35*/ 667 u32 rx_ipv4_bytes_lsd; /* dword 36*/ 668 u32 rx_ipv4_bytes_msd; /* dword 37*/ 669 u32 rx_ipv6_bytes_lsd; /* dword 38*/ 670 u32 rx_ipv6_bytes_msd; /* dword 39*/ 671 u32 rx_chute1_packets; /* dword 40*/ 672 u32 rx_chute2_packets; /* dword 41*/ 673 u32 rx_chute3_packets; /* dword 42*/ 674 u32 rx_management_packets; /* dword 43*/ 675 u32 rx_switched_unicast_packets; /* dword 44*/ 676 u32 rx_switched_multicast_packets; /* dword 45*/ 677 u32 rx_switched_broadcast_packets; /* dword 46*/ 678 u32 tx_bytes_lsd; /* dword 47*/ 679 u32 tx_bytes_msd; /* dword 48*/ 680 u32 tx_unicastframes; /* dword 49*/ 681 u32 tx_multicastframes; /* dword 50*/ 682 u32 tx_broadcastframes; /* dword 51*/ 683 u32 tx_pauseframes; /* dword 52*/ 684 u32 tx_controlframes; /* dword 53*/ 685 u32 tx_64_byte_packets; /* dword 54*/ 686 u32 tx_65_127_byte_packets; /* dword 55*/ 687 u32 tx_128_256_byte_packets; /* dword 56*/ 688 u32 tx_256_511_byte_packets; /* dword 57*/ 689 u32 tx_512_1023_byte_packets; /* dword 58*/ 690 u32 tx_1024_1518_byte_packets; /* dword 59*/ 691 u32 tx_1519_2047_byte_packets; /* dword 60*/ 692 u32 tx_2048_4095_byte_packets; /* dword 61*/ 693 u32 tx_4096_8191_byte_packets; /* dword 62*/ 694 u32 tx_8192_9216_byte_packets; /* dword 63*/ 695 u32 rx_fifo_overflow; /* dword 64*/ 696 u32 rx_input_fifo_overflow; /* dword 65*/ 697 }; 698 699 struct be_rxf_stats_v0 { 700 struct be_port_rxf_stats_v0 port[2]; 701 u32 rx_drops_no_pbuf; /* dword 132*/ 702 u32 rx_drops_no_txpb; /* dword 133*/ 703 u32 rx_drops_no_erx_descr; /* dword 134*/ 704 u32 rx_drops_no_tpre_descr; /* dword 135*/ 705 u32 management_rx_port_packets; /* dword 136*/ 706 u32 management_rx_port_bytes; /* dword 137*/ 707 u32 management_rx_port_pause_frames; /* dword 138*/ 708 u32 management_rx_port_errors; /* dword 139*/ 709 u32 management_tx_port_packets; /* dword 140*/ 710 u32 management_tx_port_bytes; /* dword 141*/ 711 u32 management_tx_port_pause; /* dword 142*/ 712 u32 management_rx_port_rxfifo_overflow; /* dword 143*/ 713 u32 rx_drops_too_many_frags; /* dword 144*/ 714 u32 rx_drops_invalid_ring; /* dword 145*/ 715 u32 forwarded_packets; /* dword 146*/ 716 u32 rx_drops_mtu; /* dword 147*/ 717 u32 rsvd0[7]; 718 u32 port0_jabber_events; 719 u32 port1_jabber_events; 720 u32 rsvd1[6]; 721 }; 722 723 struct be_erx_stats_v0 { 724 u32 rx_drops_no_fragments[44]; /* dwordS 0 to 43*/ 725 u32 rsvd[4]; 726 }; 727 728 struct be_pmem_stats { 729 u32 eth_red_drops; 730 u32 rsvd[5]; 731 }; 732 733 struct be_hw_stats_v0 { 734 struct be_rxf_stats_v0 rxf; 735 u32 rsvd[48]; 736 struct be_erx_stats_v0 erx; 737 struct be_pmem_stats pmem; 738 }; 739 740 struct be_cmd_req_get_stats_v0 { 741 struct be_cmd_req_hdr hdr; 742 u8 rsvd[sizeof(struct be_hw_stats_v0)]; 743 }; 744 745 struct be_cmd_resp_get_stats_v0 { 746 struct be_cmd_resp_hdr hdr; 747 struct be_hw_stats_v0 hw_stats; 748 }; 749 750 struct lancer_pport_stats { 751 u32 tx_packets_lo; 752 u32 tx_packets_hi; 753 u32 tx_unicast_packets_lo; 754 u32 tx_unicast_packets_hi; 755 u32 tx_multicast_packets_lo; 756 u32 tx_multicast_packets_hi; 757 u32 tx_broadcast_packets_lo; 758 u32 tx_broadcast_packets_hi; 759 u32 tx_bytes_lo; 760 u32 tx_bytes_hi; 761 u32 tx_unicast_bytes_lo; 762 u32 tx_unicast_bytes_hi; 763 u32 tx_multicast_bytes_lo; 764 u32 tx_multicast_bytes_hi; 765 u32 tx_broadcast_bytes_lo; 766 u32 tx_broadcast_bytes_hi; 767 u32 tx_discards_lo; 768 u32 tx_discards_hi; 769 u32 tx_errors_lo; 770 u32 tx_errors_hi; 771 u32 tx_pause_frames_lo; 772 u32 tx_pause_frames_hi; 773 u32 tx_pause_on_frames_lo; 774 u32 tx_pause_on_frames_hi; 775 u32 tx_pause_off_frames_lo; 776 u32 tx_pause_off_frames_hi; 777 u32 tx_internal_mac_errors_lo; 778 u32 tx_internal_mac_errors_hi; 779 u32 tx_control_frames_lo; 780 u32 tx_control_frames_hi; 781 u32 tx_packets_64_bytes_lo; 782 u32 tx_packets_64_bytes_hi; 783 u32 tx_packets_65_to_127_bytes_lo; 784 u32 tx_packets_65_to_127_bytes_hi; 785 u32 tx_packets_128_to_255_bytes_lo; 786 u32 tx_packets_128_to_255_bytes_hi; 787 u32 tx_packets_256_to_511_bytes_lo; 788 u32 tx_packets_256_to_511_bytes_hi; 789 u32 tx_packets_512_to_1023_bytes_lo; 790 u32 tx_packets_512_to_1023_bytes_hi; 791 u32 tx_packets_1024_to_1518_bytes_lo; 792 u32 tx_packets_1024_to_1518_bytes_hi; 793 u32 tx_packets_1519_to_2047_bytes_lo; 794 u32 tx_packets_1519_to_2047_bytes_hi; 795 u32 tx_packets_2048_to_4095_bytes_lo; 796 u32 tx_packets_2048_to_4095_bytes_hi; 797 u32 tx_packets_4096_to_8191_bytes_lo; 798 u32 tx_packets_4096_to_8191_bytes_hi; 799 u32 tx_packets_8192_to_9216_bytes_lo; 800 u32 tx_packets_8192_to_9216_bytes_hi; 801 u32 tx_lso_packets_lo; 802 u32 tx_lso_packets_hi; 803 u32 rx_packets_lo; 804 u32 rx_packets_hi; 805 u32 rx_unicast_packets_lo; 806 u32 rx_unicast_packets_hi; 807 u32 rx_multicast_packets_lo; 808 u32 rx_multicast_packets_hi; 809 u32 rx_broadcast_packets_lo; 810 u32 rx_broadcast_packets_hi; 811 u32 rx_bytes_lo; 812 u32 rx_bytes_hi; 813 u32 rx_unicast_bytes_lo; 814 u32 rx_unicast_bytes_hi; 815 u32 rx_multicast_bytes_lo; 816 u32 rx_multicast_bytes_hi; 817 u32 rx_broadcast_bytes_lo; 818 u32 rx_broadcast_bytes_hi; 819 u32 rx_unknown_protos; 820 u32 rsvd_69; /* Word 69 is reserved */ 821 u32 rx_discards_lo; 822 u32 rx_discards_hi; 823 u32 rx_errors_lo; 824 u32 rx_errors_hi; 825 u32 rx_crc_errors_lo; 826 u32 rx_crc_errors_hi; 827 u32 rx_alignment_errors_lo; 828 u32 rx_alignment_errors_hi; 829 u32 rx_symbol_errors_lo; 830 u32 rx_symbol_errors_hi; 831 u32 rx_pause_frames_lo; 832 u32 rx_pause_frames_hi; 833 u32 rx_pause_on_frames_lo; 834 u32 rx_pause_on_frames_hi; 835 u32 rx_pause_off_frames_lo; 836 u32 rx_pause_off_frames_hi; 837 u32 rx_frames_too_long_lo; 838 u32 rx_frames_too_long_hi; 839 u32 rx_internal_mac_errors_lo; 840 u32 rx_internal_mac_errors_hi; 841 u32 rx_undersize_packets; 842 u32 rx_oversize_packets; 843 u32 rx_fragment_packets; 844 u32 rx_jabbers; 845 u32 rx_control_frames_lo; 846 u32 rx_control_frames_hi; 847 u32 rx_control_frames_unknown_opcode_lo; 848 u32 rx_control_frames_unknown_opcode_hi; 849 u32 rx_in_range_errors; 850 u32 rx_out_of_range_errors; 851 u32 rx_address_filtered; 852 u32 rx_vlan_filtered; 853 u32 rx_dropped_too_small; 854 u32 rx_dropped_too_short; 855 u32 rx_dropped_header_too_small; 856 u32 rx_dropped_invalid_tcp_length; 857 u32 rx_dropped_runt; 858 u32 rx_ip_checksum_errors; 859 u32 rx_tcp_checksum_errors; 860 u32 rx_udp_checksum_errors; 861 u32 rx_non_rss_packets; 862 u32 rsvd_111; 863 u32 rx_ipv4_packets_lo; 864 u32 rx_ipv4_packets_hi; 865 u32 rx_ipv6_packets_lo; 866 u32 rx_ipv6_packets_hi; 867 u32 rx_ipv4_bytes_lo; 868 u32 rx_ipv4_bytes_hi; 869 u32 rx_ipv6_bytes_lo; 870 u32 rx_ipv6_bytes_hi; 871 u32 rx_nic_packets_lo; 872 u32 rx_nic_packets_hi; 873 u32 rx_tcp_packets_lo; 874 u32 rx_tcp_packets_hi; 875 u32 rx_iscsi_packets_lo; 876 u32 rx_iscsi_packets_hi; 877 u32 rx_management_packets_lo; 878 u32 rx_management_packets_hi; 879 u32 rx_switched_unicast_packets_lo; 880 u32 rx_switched_unicast_packets_hi; 881 u32 rx_switched_multicast_packets_lo; 882 u32 rx_switched_multicast_packets_hi; 883 u32 rx_switched_broadcast_packets_lo; 884 u32 rx_switched_broadcast_packets_hi; 885 u32 num_forwards_lo; 886 u32 num_forwards_hi; 887 u32 rx_fifo_overflow; 888 u32 rx_input_fifo_overflow; 889 u32 rx_drops_too_many_frags_lo; 890 u32 rx_drops_too_many_frags_hi; 891 u32 rx_drops_invalid_queue; 892 u32 rsvd_141; 893 u32 rx_drops_mtu_lo; 894 u32 rx_drops_mtu_hi; 895 u32 rx_packets_64_bytes_lo; 896 u32 rx_packets_64_bytes_hi; 897 u32 rx_packets_65_to_127_bytes_lo; 898 u32 rx_packets_65_to_127_bytes_hi; 899 u32 rx_packets_128_to_255_bytes_lo; 900 u32 rx_packets_128_to_255_bytes_hi; 901 u32 rx_packets_256_to_511_bytes_lo; 902 u32 rx_packets_256_to_511_bytes_hi; 903 u32 rx_packets_512_to_1023_bytes_lo; 904 u32 rx_packets_512_to_1023_bytes_hi; 905 u32 rx_packets_1024_to_1518_bytes_lo; 906 u32 rx_packets_1024_to_1518_bytes_hi; 907 u32 rx_packets_1519_to_2047_bytes_lo; 908 u32 rx_packets_1519_to_2047_bytes_hi; 909 u32 rx_packets_2048_to_4095_bytes_lo; 910 u32 rx_packets_2048_to_4095_bytes_hi; 911 u32 rx_packets_4096_to_8191_bytes_lo; 912 u32 rx_packets_4096_to_8191_bytes_hi; 913 u32 rx_packets_8192_to_9216_bytes_lo; 914 u32 rx_packets_8192_to_9216_bytes_hi; 915 }; 916 917 struct pport_stats_params { 918 u16 pport_num; 919 u8 rsvd; 920 u8 reset_stats; 921 }; 922 923 struct lancer_cmd_req_pport_stats { 924 struct be_cmd_req_hdr hdr; 925 union { 926 struct pport_stats_params params; 927 u8 rsvd[sizeof(struct lancer_pport_stats)]; 928 } cmd_params; 929 }; 930 931 struct lancer_cmd_resp_pport_stats { 932 struct be_cmd_resp_hdr hdr; 933 struct lancer_pport_stats pport_stats; 934 }; 935 936 static inline struct lancer_pport_stats* 937 pport_stats_from_cmd(struct be_adapter *adapter) 938 { 939 struct lancer_cmd_resp_pport_stats *cmd = adapter->stats_cmd.va; 940 return &cmd->pport_stats; 941 } 942 943 struct be_cmd_req_get_cntl_addnl_attribs { 944 struct be_cmd_req_hdr hdr; 945 u8 rsvd[8]; 946 }; 947 948 struct be_cmd_resp_get_cntl_addnl_attribs { 949 struct be_cmd_resp_hdr hdr; 950 u16 ipl_file_number; 951 u8 ipl_file_version; 952 u8 rsvd0; 953 u8 on_die_temperature; /* in degrees centigrade*/ 954 u8 rsvd1[3]; 955 }; 956 957 struct be_cmd_req_vlan_config { 958 struct be_cmd_req_hdr hdr; 959 u8 interface_id; 960 u8 promiscuous; 961 u8 untagged; 962 u8 num_vlan; 963 u16 normal_vlan[64]; 964 } __packed; 965 966 /******************* RX FILTER ******************************/ 967 #define BE_MAX_MC 64 /* set mcast promisc if > 64 */ 968 struct macaddr { 969 u8 byte[ETH_ALEN]; 970 }; 971 972 struct be_cmd_req_rx_filter { 973 struct be_cmd_req_hdr hdr; 974 u32 global_flags_mask; 975 u32 global_flags; 976 u32 if_flags_mask; 977 u32 if_flags; 978 u32 if_id; 979 u32 mcast_num; 980 struct macaddr mcast_mac[BE_MAX_MC]; 981 }; 982 983 /******************** Link Status Query *******************/ 984 struct be_cmd_req_link_status { 985 struct be_cmd_req_hdr hdr; 986 u32 rsvd; 987 }; 988 989 enum { 990 PHY_LINK_DUPLEX_NONE = 0x0, 991 PHY_LINK_DUPLEX_HALF = 0x1, 992 PHY_LINK_DUPLEX_FULL = 0x2 993 }; 994 995 enum { 996 PHY_LINK_SPEED_ZERO = 0x0, /* => No link */ 997 PHY_LINK_SPEED_10MBPS = 0x1, 998 PHY_LINK_SPEED_100MBPS = 0x2, 999 PHY_LINK_SPEED_1GBPS = 0x3, 1000 PHY_LINK_SPEED_10GBPS = 0x4, 1001 PHY_LINK_SPEED_20GBPS = 0x5, 1002 PHY_LINK_SPEED_25GBPS = 0x6, 1003 PHY_LINK_SPEED_40GBPS = 0x7 1004 }; 1005 1006 struct be_cmd_resp_link_status { 1007 struct be_cmd_resp_hdr hdr; 1008 u8 physical_port; 1009 u8 mac_duplex; 1010 u8 mac_speed; 1011 u8 mac_fault; 1012 u8 mgmt_mac_duplex; 1013 u8 mgmt_mac_speed; 1014 u16 link_speed; 1015 u8 logical_link_status; 1016 u8 rsvd1[3]; 1017 } __packed; 1018 1019 /******************** Port Identification ***************************/ 1020 /* Identifies the type of port attached to NIC */ 1021 struct be_cmd_req_port_type { 1022 struct be_cmd_req_hdr hdr; 1023 __le32 page_num; 1024 __le32 port; 1025 }; 1026 1027 enum { 1028 TR_PAGE_A0 = 0xa0, 1029 TR_PAGE_A2 = 0xa2 1030 }; 1031 1032 /* From SFF-8436 QSFP+ spec */ 1033 #define QSFP_PLUS_CABLE_TYPE_OFFSET 0x83 1034 #define QSFP_PLUS_CR4_CABLE 0x8 1035 #define QSFP_PLUS_SR4_CABLE 0x4 1036 #define QSFP_PLUS_LR4_CABLE 0x2 1037 1038 /* From SFF-8472 spec */ 1039 #define SFP_PLUS_SFF_8472_COMP 0x5E 1040 #define SFP_PLUS_CABLE_TYPE_OFFSET 0x8 1041 #define SFP_PLUS_COPPER_CABLE 0x4 1042 #define SFP_VENDOR_NAME_OFFSET 0x14 1043 #define SFP_VENDOR_PN_OFFSET 0x28 1044 1045 #define PAGE_DATA_LEN 256 1046 struct be_cmd_resp_port_type { 1047 struct be_cmd_resp_hdr hdr; 1048 u32 page_num; 1049 u32 port; 1050 u8 page_data[PAGE_DATA_LEN]; 1051 }; 1052 1053 /******************** Get FW Version *******************/ 1054 struct be_cmd_req_get_fw_version { 1055 struct be_cmd_req_hdr hdr; 1056 u8 rsvd0[FW_VER_LEN]; 1057 u8 rsvd1[FW_VER_LEN]; 1058 } __packed; 1059 1060 struct be_cmd_resp_get_fw_version { 1061 struct be_cmd_resp_hdr hdr; 1062 u8 firmware_version_string[FW_VER_LEN]; 1063 u8 fw_on_flash_version_string[FW_VER_LEN]; 1064 } __packed; 1065 1066 /******************** Set Flow Contrl *******************/ 1067 struct be_cmd_req_set_flow_control { 1068 struct be_cmd_req_hdr hdr; 1069 u16 tx_flow_control; 1070 u16 rx_flow_control; 1071 } __packed; 1072 1073 /******************** Get Flow Contrl *******************/ 1074 struct be_cmd_req_get_flow_control { 1075 struct be_cmd_req_hdr hdr; 1076 u32 rsvd; 1077 }; 1078 1079 struct be_cmd_resp_get_flow_control { 1080 struct be_cmd_resp_hdr hdr; 1081 u16 tx_flow_control; 1082 u16 rx_flow_control; 1083 } __packed; 1084 1085 /******************** Modify EQ Delay *******************/ 1086 struct be_set_eqd { 1087 u32 eq_id; 1088 u32 phase; 1089 u32 delay_multiplier; 1090 }; 1091 1092 struct be_cmd_req_modify_eq_delay { 1093 struct be_cmd_req_hdr hdr; 1094 u32 num_eq; 1095 struct be_set_eqd set_eqd[MAX_EVT_QS]; 1096 } __packed; 1097 1098 /******************** Get FW Config *******************/ 1099 /* The HW can come up in either of the following multi-channel modes 1100 * based on the skew/IPL. 1101 */ 1102 #define RDMA_ENABLED 0x4 1103 #define QNQ_MODE 0x400 1104 #define VNIC_MODE 0x20000 1105 #define UMC_ENABLED 0x1000000 1106 struct be_cmd_req_query_fw_cfg { 1107 struct be_cmd_req_hdr hdr; 1108 u32 rsvd[31]; 1109 }; 1110 1111 /* ASIC revisions */ 1112 #define ASIC_REV_B0 0x10 1113 #define ASIC_REV_P2 0x11 1114 1115 struct be_cmd_resp_query_fw_cfg { 1116 struct be_cmd_resp_hdr hdr; 1117 u32 be_config_number; 1118 u32 asic_revision; 1119 u32 phys_port; 1120 u32 function_mode; 1121 u32 rsvd[26]; 1122 u32 function_caps; 1123 }; 1124 1125 /******************** RSS Config ****************************************/ 1126 /* RSS type Input parameters used to compute RX hash 1127 * RSS_ENABLE_IPV4 SRC IPv4, DST IPv4 1128 * RSS_ENABLE_TCP_IPV4 SRC IPv4, DST IPv4, TCP SRC PORT, TCP DST PORT 1129 * RSS_ENABLE_IPV6 SRC IPv6, DST IPv6 1130 * RSS_ENABLE_TCP_IPV6 SRC IPv6, DST IPv6, TCP SRC PORT, TCP DST PORT 1131 * RSS_ENABLE_UDP_IPV4 SRC IPv4, DST IPv4, UDP SRC PORT, UDP DST PORT 1132 * RSS_ENABLE_UDP_IPV6 SRC IPv6, DST IPv6, UDP SRC PORT, UDP DST PORT 1133 * 1134 * When multiple RSS types are enabled, HW picks the best hash policy 1135 * based on the type of the received packet. 1136 */ 1137 #define RSS_ENABLE_NONE 0x0 1138 #define RSS_ENABLE_IPV4 0x1 1139 #define RSS_ENABLE_TCP_IPV4 0x2 1140 #define RSS_ENABLE_IPV6 0x4 1141 #define RSS_ENABLE_TCP_IPV6 0x8 1142 #define RSS_ENABLE_UDP_IPV4 0x10 1143 #define RSS_ENABLE_UDP_IPV6 0x20 1144 1145 #define L3_RSS_FLAGS (RXH_IP_DST | RXH_IP_SRC) 1146 #define L4_RSS_FLAGS (RXH_L4_B_0_1 | RXH_L4_B_2_3) 1147 1148 struct be_cmd_req_rss_config { 1149 struct be_cmd_req_hdr hdr; 1150 u32 if_id; 1151 u16 enable_rss; 1152 u16 cpu_table_size_log2; 1153 u32 hash[10]; 1154 u8 cpu_table[128]; 1155 u8 flush; 1156 u8 rsvd0[3]; 1157 }; 1158 1159 /******************** Port Beacon ***************************/ 1160 1161 #define BEACON_STATE_ENABLED 0x1 1162 #define BEACON_STATE_DISABLED 0x0 1163 1164 struct be_cmd_req_enable_disable_beacon { 1165 struct be_cmd_req_hdr hdr; 1166 u8 port_num; 1167 u8 beacon_state; 1168 u8 beacon_duration; 1169 u8 status_duration; 1170 } __packed; 1171 1172 struct be_cmd_req_get_beacon_state { 1173 struct be_cmd_req_hdr hdr; 1174 u8 port_num; 1175 u8 rsvd0; 1176 u16 rsvd1; 1177 } __packed; 1178 1179 struct be_cmd_resp_get_beacon_state { 1180 struct be_cmd_resp_hdr resp_hdr; 1181 u8 beacon_state; 1182 u8 rsvd0[3]; 1183 } __packed; 1184 1185 /* Flashrom related descriptors */ 1186 #define MAX_FLASH_COMP 32 1187 1188 #define OPTYPE_ISCSI_ACTIVE 0 1189 #define OPTYPE_REDBOOT 1 1190 #define OPTYPE_BIOS 2 1191 #define OPTYPE_PXE_BIOS 3 1192 #define OPTYPE_OFFSET_SPECIFIED 7 1193 #define OPTYPE_FCOE_BIOS 8 1194 #define OPTYPE_ISCSI_BACKUP 9 1195 #define OPTYPE_FCOE_FW_ACTIVE 10 1196 #define OPTYPE_FCOE_FW_BACKUP 11 1197 #define OPTYPE_NCSI_FW 13 1198 #define OPTYPE_REDBOOT_DIR 18 1199 #define OPTYPE_REDBOOT_CONFIG 19 1200 #define OPTYPE_SH_PHY_FW 21 1201 #define OPTYPE_FLASHISM_JUMPVECTOR 22 1202 #define OPTYPE_UFI_DIR 23 1203 #define OPTYPE_PHY_FW 99 1204 1205 #define FLASH_BIOS_IMAGE_MAX_SIZE_g2 262144 /* Max OPTION ROM image sz */ 1206 #define FLASH_REDBOOT_IMAGE_MAX_SIZE_g2 262144 /* Max Redboot image sz */ 1207 #define FLASH_IMAGE_MAX_SIZE_g2 1310720 /* Max firmware image size */ 1208 1209 #define FLASH_NCSI_IMAGE_MAX_SIZE_g3 262144 1210 #define FLASH_PHY_FW_IMAGE_MAX_SIZE_g3 262144 1211 #define FLASH_BIOS_IMAGE_MAX_SIZE_g3 524288 /* Max OPTION ROM image sz */ 1212 #define FLASH_REDBOOT_IMAGE_MAX_SIZE_g3 1048576 /* Max Redboot image sz */ 1213 #define FLASH_IMAGE_MAX_SIZE_g3 2097152 /* Max firmware image size */ 1214 1215 /* Offsets for components on Flash. */ 1216 #define FLASH_REDBOOT_START_g2 0 1217 #define FLASH_FCoE_BIOS_START_g2 524288 1218 #define FLASH_iSCSI_PRIMARY_IMAGE_START_g2 1048576 1219 #define FLASH_iSCSI_BACKUP_IMAGE_START_g2 2359296 1220 #define FLASH_FCoE_PRIMARY_IMAGE_START_g2 3670016 1221 #define FLASH_FCoE_BACKUP_IMAGE_START_g2 4980736 1222 #define FLASH_iSCSI_BIOS_START_g2 7340032 1223 #define FLASH_PXE_BIOS_START_g2 7864320 1224 1225 #define FLASH_REDBOOT_START_g3 262144 1226 #define FLASH_PHY_FW_START_g3 1310720 1227 #define FLASH_iSCSI_PRIMARY_IMAGE_START_g3 2097152 1228 #define FLASH_iSCSI_BACKUP_IMAGE_START_g3 4194304 1229 #define FLASH_FCoE_PRIMARY_IMAGE_START_g3 6291456 1230 #define FLASH_FCoE_BACKUP_IMAGE_START_g3 8388608 1231 #define FLASH_iSCSI_BIOS_START_g3 12582912 1232 #define FLASH_PXE_BIOS_START_g3 13107200 1233 #define FLASH_FCoE_BIOS_START_g3 13631488 1234 #define FLASH_NCSI_START_g3 15990784 1235 1236 #define IMAGE_NCSI 16 1237 #define IMAGE_OPTION_ROM_PXE 32 1238 #define IMAGE_OPTION_ROM_FCoE 33 1239 #define IMAGE_OPTION_ROM_ISCSI 34 1240 #define IMAGE_FLASHISM_JUMPVECTOR 48 1241 #define IMAGE_FIRMWARE_iSCSI 160 1242 #define IMAGE_FIRMWARE_FCoE 162 1243 #define IMAGE_FIRMWARE_BACKUP_iSCSI 176 1244 #define IMAGE_FIRMWARE_BACKUP_FCoE 178 1245 #define IMAGE_FIRMWARE_PHY 192 1246 #define IMAGE_REDBOOT_DIR 208 1247 #define IMAGE_REDBOOT_CONFIG 209 1248 #define IMAGE_UFI_DIR 210 1249 #define IMAGE_BOOT_CODE 224 1250 1251 struct controller_id { 1252 u32 vendor; 1253 u32 device; 1254 u32 subvendor; 1255 u32 subdevice; 1256 }; 1257 1258 struct flash_comp { 1259 unsigned long offset; 1260 int optype; 1261 int size; 1262 int img_type; 1263 }; 1264 1265 struct image_hdr { 1266 u32 imageid; 1267 u32 imageoffset; 1268 u32 imagelength; 1269 u32 image_checksum; 1270 u8 image_version[32]; 1271 }; 1272 1273 struct flash_file_hdr_g2 { 1274 u8 sign[32]; 1275 u32 cksum; 1276 u32 antidote; 1277 struct controller_id cont_id; 1278 u32 file_len; 1279 u32 chunk_num; 1280 u32 total_chunks; 1281 u32 num_imgs; 1282 u8 build[24]; 1283 }; 1284 1285 /* First letter of the build version of the image */ 1286 #define BLD_STR_UFI_TYPE_BE2 '2' 1287 #define BLD_STR_UFI_TYPE_BE3 '3' 1288 #define BLD_STR_UFI_TYPE_SH '4' 1289 1290 struct flash_file_hdr_g3 { 1291 u8 sign[52]; 1292 u8 ufi_version[4]; 1293 u32 file_len; 1294 u32 cksum; 1295 u32 antidote; 1296 u32 num_imgs; 1297 u8 build[24]; 1298 u8 asic_type_rev; 1299 u8 rsvd[31]; 1300 }; 1301 1302 struct flash_section_hdr { 1303 u32 format_rev; 1304 u32 cksum; 1305 u32 antidote; 1306 u32 num_images; 1307 u8 id_string[128]; 1308 u32 rsvd[4]; 1309 } __packed; 1310 1311 struct flash_section_hdr_g2 { 1312 u32 format_rev; 1313 u32 cksum; 1314 u32 antidote; 1315 u32 build_num; 1316 u8 id_string[128]; 1317 u32 rsvd[8]; 1318 } __packed; 1319 1320 struct flash_section_entry { 1321 u32 type; 1322 u32 offset; 1323 u32 pad_size; 1324 u32 image_size; 1325 u32 cksum; 1326 u32 entry_point; 1327 u16 optype; 1328 u16 rsvd0; 1329 u32 rsvd1; 1330 u8 ver_data[32]; 1331 } __packed; 1332 1333 struct flash_section_info { 1334 u8 cookie[32]; 1335 struct flash_section_hdr fsec_hdr; 1336 struct flash_section_entry fsec_entry[32]; 1337 } __packed; 1338 1339 struct flash_section_info_g2 { 1340 u8 cookie[32]; 1341 struct flash_section_hdr_g2 fsec_hdr; 1342 struct flash_section_entry fsec_entry[32]; 1343 } __packed; 1344 1345 /****************** Firmware Flash ******************/ 1346 #define FLASHROM_OPER_FLASH 1 1347 #define FLASHROM_OPER_SAVE 2 1348 #define FLASHROM_OPER_REPORT 4 1349 #define FLASHROM_OPER_PHY_FLASH 9 1350 #define FLASHROM_OPER_PHY_SAVE 10 1351 1352 struct flashrom_params { 1353 u32 op_code; 1354 u32 op_type; 1355 u32 data_buf_size; 1356 u32 offset; 1357 }; 1358 1359 struct be_cmd_write_flashrom { 1360 struct be_cmd_req_hdr hdr; 1361 struct flashrom_params params; 1362 u8 data_buf[32768]; 1363 u8 rsvd[4]; 1364 } __packed; 1365 1366 /* cmd to read flash crc */ 1367 struct be_cmd_read_flash_crc { 1368 struct be_cmd_req_hdr hdr; 1369 struct flashrom_params params; 1370 u8 crc[4]; 1371 u8 rsvd[4]; 1372 } __packed; 1373 1374 /**************** Lancer Firmware Flash ************/ 1375 struct amap_lancer_write_obj_context { 1376 u8 write_length[24]; 1377 u8 reserved1[7]; 1378 u8 eof; 1379 } __packed; 1380 1381 struct lancer_cmd_req_write_object { 1382 struct be_cmd_req_hdr hdr; 1383 u8 context[sizeof(struct amap_lancer_write_obj_context) / 8]; 1384 u32 write_offset; 1385 u8 object_name[104]; 1386 u32 descriptor_count; 1387 u32 buf_len; 1388 u32 addr_low; 1389 u32 addr_high; 1390 }; 1391 1392 #define LANCER_NO_RESET_NEEDED 0x00 1393 #define LANCER_FW_RESET_NEEDED 0x02 1394 struct lancer_cmd_resp_write_object { 1395 u8 opcode; 1396 u8 subsystem; 1397 u8 rsvd1[2]; 1398 u8 status; 1399 u8 additional_status; 1400 u8 rsvd2[2]; 1401 u32 resp_len; 1402 u32 actual_resp_len; 1403 u32 actual_write_len; 1404 u8 change_status; 1405 u8 rsvd3[3]; 1406 }; 1407 1408 /************************ Lancer Read FW info **************/ 1409 #define LANCER_READ_FILE_CHUNK (32*1024) 1410 #define LANCER_READ_FILE_EOF_MASK 0x80000000 1411 1412 #define LANCER_FW_DUMP_FILE "/dbg/dump.bin" 1413 #define LANCER_VPD_PF_FILE "/vpd/ntr_pf.vpd" 1414 #define LANCER_VPD_VF_FILE "/vpd/ntr_vf.vpd" 1415 1416 struct lancer_cmd_req_read_object { 1417 struct be_cmd_req_hdr hdr; 1418 u32 desired_read_len; 1419 u32 read_offset; 1420 u8 object_name[104]; 1421 u32 descriptor_count; 1422 u32 buf_len; 1423 u32 addr_low; 1424 u32 addr_high; 1425 }; 1426 1427 struct lancer_cmd_resp_read_object { 1428 u8 opcode; 1429 u8 subsystem; 1430 u8 rsvd1[2]; 1431 u8 status; 1432 u8 additional_status; 1433 u8 rsvd2[2]; 1434 u32 resp_len; 1435 u32 actual_resp_len; 1436 u32 actual_read_len; 1437 u32 eof; 1438 }; 1439 1440 struct lancer_cmd_req_delete_object { 1441 struct be_cmd_req_hdr hdr; 1442 u32 rsvd1; 1443 u32 rsvd2; 1444 u8 object_name[104]; 1445 }; 1446 1447 /************************ WOL *******************************/ 1448 struct be_cmd_req_acpi_wol_magic_config{ 1449 struct be_cmd_req_hdr hdr; 1450 u32 rsvd0[145]; 1451 u8 magic_mac[6]; 1452 u8 rsvd2[2]; 1453 } __packed; 1454 1455 struct be_cmd_req_acpi_wol_magic_config_v1 { 1456 struct be_cmd_req_hdr hdr; 1457 u8 rsvd0[2]; 1458 u8 query_options; 1459 u8 rsvd1[5]; 1460 u32 rsvd2[288]; 1461 u8 magic_mac[6]; 1462 u8 rsvd3[22]; 1463 } __packed; 1464 1465 struct be_cmd_resp_acpi_wol_magic_config_v1 { 1466 struct be_cmd_resp_hdr hdr; 1467 u8 rsvd0[2]; 1468 u8 wol_settings; 1469 u8 rsvd1[5]; 1470 u32 rsvd2[295]; 1471 } __packed; 1472 1473 #define BE_GET_WOL_CAP 2 1474 1475 #define BE_WOL_CAP 0x1 1476 #define BE_PME_D0_CAP 0x8 1477 #define BE_PME_D1_CAP 0x10 1478 #define BE_PME_D2_CAP 0x20 1479 #define BE_PME_D3HOT_CAP 0x40 1480 #define BE_PME_D3COLD_CAP 0x80 1481 1482 /********************** LoopBack test *********************/ 1483 struct be_cmd_req_loopback_test { 1484 struct be_cmd_req_hdr hdr; 1485 u32 loopback_type; 1486 u32 num_pkts; 1487 u64 pattern; 1488 u32 src_port; 1489 u32 dest_port; 1490 u32 pkt_size; 1491 }; 1492 1493 struct be_cmd_resp_loopback_test { 1494 struct be_cmd_resp_hdr resp_hdr; 1495 u32 status; 1496 u32 num_txfer; 1497 u32 num_rx; 1498 u32 miscomp_off; 1499 u32 ticks_compl; 1500 }; 1501 1502 struct be_cmd_req_set_lmode { 1503 struct be_cmd_req_hdr hdr; 1504 u8 src_port; 1505 u8 dest_port; 1506 u8 loopback_type; 1507 u8 loopback_state; 1508 }; 1509 1510 /********************** DDR DMA test *********************/ 1511 struct be_cmd_req_ddrdma_test { 1512 struct be_cmd_req_hdr hdr; 1513 u64 pattern; 1514 u32 byte_count; 1515 u32 rsvd0; 1516 u8 snd_buff[4096]; 1517 u8 rsvd1[4096]; 1518 }; 1519 1520 struct be_cmd_resp_ddrdma_test { 1521 struct be_cmd_resp_hdr hdr; 1522 u64 pattern; 1523 u32 byte_cnt; 1524 u32 snd_err; 1525 u8 rsvd0[4096]; 1526 u8 rcv_buff[4096]; 1527 }; 1528 1529 /*********************** SEEPROM Read ***********************/ 1530 1531 #define BE_READ_SEEPROM_LEN 1024 1532 struct be_cmd_req_seeprom_read { 1533 struct be_cmd_req_hdr hdr; 1534 u8 rsvd0[BE_READ_SEEPROM_LEN]; 1535 }; 1536 1537 struct be_cmd_resp_seeprom_read { 1538 struct be_cmd_req_hdr hdr; 1539 u8 seeprom_data[BE_READ_SEEPROM_LEN]; 1540 }; 1541 1542 enum { 1543 PHY_TYPE_CX4_10GB = 0, 1544 PHY_TYPE_XFP_10GB, 1545 PHY_TYPE_SFP_1GB, 1546 PHY_TYPE_SFP_PLUS_10GB, 1547 PHY_TYPE_KR_10GB, 1548 PHY_TYPE_KX4_10GB, 1549 PHY_TYPE_BASET_10GB, 1550 PHY_TYPE_BASET_1GB, 1551 PHY_TYPE_BASEX_1GB, 1552 PHY_TYPE_SGMII, 1553 PHY_TYPE_QSFP, 1554 PHY_TYPE_KR4_40GB, 1555 PHY_TYPE_KR2_20GB, 1556 PHY_TYPE_TN_8022, 1557 PHY_TYPE_DISABLED = 255 1558 }; 1559 1560 #define BE_SUPPORTED_SPEED_NONE 0 1561 #define BE_SUPPORTED_SPEED_10MBPS 1 1562 #define BE_SUPPORTED_SPEED_100MBPS 2 1563 #define BE_SUPPORTED_SPEED_1GBPS 4 1564 #define BE_SUPPORTED_SPEED_10GBPS 8 1565 #define BE_SUPPORTED_SPEED_20GBPS 0x10 1566 #define BE_SUPPORTED_SPEED_40GBPS 0x20 1567 1568 #define BE_AN_EN 0x2 1569 #define BE_PAUSE_SYM_EN 0x80 1570 1571 /* MAC speed valid values */ 1572 #define SPEED_DEFAULT 0x0 1573 #define SPEED_FORCED_10GB 0x1 1574 #define SPEED_FORCED_1GB 0x2 1575 #define SPEED_AUTONEG_10GB 0x3 1576 #define SPEED_AUTONEG_1GB 0x4 1577 #define SPEED_AUTONEG_100MB 0x5 1578 #define SPEED_AUTONEG_10GB_1GB 0x6 1579 #define SPEED_AUTONEG_10GB_1GB_100MB 0x7 1580 #define SPEED_AUTONEG_1GB_100MB 0x8 1581 #define SPEED_AUTONEG_10MB 0x9 1582 #define SPEED_AUTONEG_1GB_100MB_10MB 0xa 1583 #define SPEED_AUTONEG_100MB_10MB 0xb 1584 #define SPEED_FORCED_100MB 0xc 1585 #define SPEED_FORCED_10MB 0xd 1586 1587 struct be_cmd_req_get_phy_info { 1588 struct be_cmd_req_hdr hdr; 1589 u8 rsvd0[24]; 1590 }; 1591 1592 struct be_phy_info { 1593 u16 phy_type; 1594 u16 interface_type; 1595 u32 misc_params; 1596 u16 ext_phy_details; 1597 u16 rsvd; 1598 u16 auto_speeds_supported; 1599 u16 fixed_speeds_supported; 1600 u32 future_use[2]; 1601 }; 1602 1603 struct be_cmd_resp_get_phy_info { 1604 struct be_cmd_req_hdr hdr; 1605 struct be_phy_info phy_info; 1606 }; 1607 1608 /*********************** Set QOS ***********************/ 1609 1610 #define BE_QOS_BITS_NIC 1 1611 1612 struct be_cmd_req_set_qos { 1613 struct be_cmd_req_hdr hdr; 1614 u32 valid_bits; 1615 u32 max_bps_nic; 1616 u32 rsvd[7]; 1617 }; 1618 1619 /*********************** Controller Attributes ***********************/ 1620 struct mgmt_hba_attribs { 1621 u32 rsvd0[24]; 1622 u8 controller_model_number[32]; 1623 u32 rsvd1[79]; 1624 u8 rsvd2[3]; 1625 u8 phy_port; 1626 u32 rsvd3[13]; 1627 } __packed; 1628 1629 struct mgmt_controller_attrib { 1630 struct mgmt_hba_attribs hba_attribs; 1631 u32 rsvd0[10]; 1632 } __packed; 1633 1634 struct be_cmd_req_cntl_attribs { 1635 struct be_cmd_req_hdr hdr; 1636 }; 1637 1638 struct be_cmd_resp_cntl_attribs { 1639 struct be_cmd_resp_hdr hdr; 1640 struct mgmt_controller_attrib attribs; 1641 }; 1642 1643 /*********************** Set driver function ***********************/ 1644 #define CAPABILITY_SW_TIMESTAMPS 2 1645 #define CAPABILITY_BE3_NATIVE_ERX_API 4 1646 1647 struct be_cmd_req_set_func_cap { 1648 struct be_cmd_req_hdr hdr; 1649 u32 valid_cap_flags; 1650 u32 cap_flags; 1651 u8 rsvd[212]; 1652 }; 1653 1654 struct be_cmd_resp_set_func_cap { 1655 struct be_cmd_resp_hdr hdr; 1656 u32 valid_cap_flags; 1657 u32 cap_flags; 1658 u8 rsvd[212]; 1659 }; 1660 1661 /*********************** Function Privileges ***********************/ 1662 enum { 1663 BE_PRIV_DEFAULT = 0x1, 1664 BE_PRIV_LNKQUERY = 0x2, 1665 BE_PRIV_LNKSTATS = 0x4, 1666 BE_PRIV_LNKMGMT = 0x8, 1667 BE_PRIV_LNKDIAG = 0x10, 1668 BE_PRIV_UTILQUERY = 0x20, 1669 BE_PRIV_FILTMGMT = 0x40, 1670 BE_PRIV_IFACEMGMT = 0x80, 1671 BE_PRIV_VHADM = 0x100, 1672 BE_PRIV_DEVCFG = 0x200, 1673 BE_PRIV_DEVSEC = 0x400 1674 }; 1675 #define MAX_PRIVILEGES (BE_PRIV_VHADM | BE_PRIV_DEVCFG | \ 1676 BE_PRIV_DEVSEC) 1677 #define MIN_PRIVILEGES BE_PRIV_DEFAULT 1678 1679 struct be_cmd_priv_map { 1680 u8 opcode; 1681 u8 subsystem; 1682 u32 priv_mask; 1683 }; 1684 1685 struct be_cmd_req_get_fn_privileges { 1686 struct be_cmd_req_hdr hdr; 1687 u32 rsvd; 1688 }; 1689 1690 struct be_cmd_resp_get_fn_privileges { 1691 struct be_cmd_resp_hdr hdr; 1692 u32 privilege_mask; 1693 }; 1694 1695 struct be_cmd_req_set_fn_privileges { 1696 struct be_cmd_req_hdr hdr; 1697 u32 privileges; /* Used by BE3, SH-R */ 1698 u32 privileges_lancer; /* Used by Lancer */ 1699 }; 1700 1701 /******************** GET/SET_MACLIST **************************/ 1702 #define BE_MAX_MAC 64 1703 struct be_cmd_req_get_mac_list { 1704 struct be_cmd_req_hdr hdr; 1705 u8 mac_type; 1706 u8 perm_override; 1707 u16 iface_id; 1708 u32 mac_id; 1709 u32 rsvd[3]; 1710 } __packed; 1711 1712 struct get_list_macaddr { 1713 u16 mac_addr_size; 1714 union { 1715 u8 macaddr[6]; 1716 struct { 1717 u8 rsvd[2]; 1718 u32 mac_id; 1719 } __packed s_mac_id; 1720 } __packed mac_addr_id; 1721 } __packed; 1722 1723 struct be_cmd_resp_get_mac_list { 1724 struct be_cmd_resp_hdr hdr; 1725 struct get_list_macaddr fd_macaddr; /* Factory default mac */ 1726 struct get_list_macaddr macid_macaddr; /* soft mac */ 1727 u8 true_mac_count; 1728 u8 pseudo_mac_count; 1729 u8 mac_list_size; 1730 u8 rsvd; 1731 /* perm override mac */ 1732 struct get_list_macaddr macaddr_list[BE_MAX_MAC]; 1733 } __packed; 1734 1735 struct be_cmd_req_set_mac_list { 1736 struct be_cmd_req_hdr hdr; 1737 u8 mac_count; 1738 u8 rsvd1; 1739 u16 rsvd2; 1740 struct macaddr mac[BE_MAX_MAC]; 1741 } __packed; 1742 1743 /*********************** HSW Config ***********************/ 1744 #define PORT_FWD_TYPE_VEPA 0x3 1745 #define PORT_FWD_TYPE_VEB 0x2 1746 1747 struct amap_set_hsw_context { 1748 u8 interface_id[16]; 1749 u8 rsvd0[14]; 1750 u8 pvid_valid; 1751 u8 pport; 1752 u8 rsvd1[6]; 1753 u8 port_fwd_type[3]; 1754 u8 rsvd2[7]; 1755 u8 pvid[16]; 1756 u8 rsvd3[32]; 1757 u8 rsvd4[32]; 1758 u8 rsvd5[32]; 1759 } __packed; 1760 1761 struct be_cmd_req_set_hsw_config { 1762 struct be_cmd_req_hdr hdr; 1763 u8 context[sizeof(struct amap_set_hsw_context) / 8]; 1764 } __packed; 1765 1766 struct amap_get_hsw_req_context { 1767 u8 interface_id[16]; 1768 u8 rsvd0[14]; 1769 u8 pvid_valid; 1770 u8 pport; 1771 } __packed; 1772 1773 struct amap_get_hsw_resp_context { 1774 u8 rsvd0[6]; 1775 u8 port_fwd_type[3]; 1776 u8 rsvd1[7]; 1777 u8 pvid[16]; 1778 u8 rsvd2[32]; 1779 u8 rsvd3[32]; 1780 u8 rsvd4[32]; 1781 } __packed; 1782 1783 struct be_cmd_req_get_hsw_config { 1784 struct be_cmd_req_hdr hdr; 1785 u8 context[sizeof(struct amap_get_hsw_req_context) / 8]; 1786 } __packed; 1787 1788 struct be_cmd_resp_get_hsw_config { 1789 struct be_cmd_resp_hdr hdr; 1790 u8 context[sizeof(struct amap_get_hsw_resp_context) / 8]; 1791 u32 rsvd; 1792 }; 1793 1794 /******************* get port names ***************/ 1795 struct be_cmd_req_get_port_name { 1796 struct be_cmd_req_hdr hdr; 1797 u32 rsvd0; 1798 }; 1799 1800 struct be_cmd_resp_get_port_name { 1801 struct be_cmd_req_hdr hdr; 1802 u8 port_name[4]; 1803 }; 1804 1805 /*************** HW Stats Get v1 **********************************/ 1806 #define BE_TXP_SW_SZ 48 1807 struct be_port_rxf_stats_v1 { 1808 u32 rsvd0[12]; 1809 u32 rx_crc_errors; 1810 u32 rx_alignment_symbol_errors; 1811 u32 rx_pause_frames; 1812 u32 rx_priority_pause_frames; 1813 u32 rx_control_frames; 1814 u32 rx_in_range_errors; 1815 u32 rx_out_range_errors; 1816 u32 rx_frame_too_long; 1817 u32 rx_address_filtered; 1818 u32 rx_dropped_too_small; 1819 u32 rx_dropped_too_short; 1820 u32 rx_dropped_header_too_small; 1821 u32 rx_dropped_tcp_length; 1822 u32 rx_dropped_runt; 1823 u32 rsvd1[10]; 1824 u32 rx_ip_checksum_errs; 1825 u32 rx_tcp_checksum_errs; 1826 u32 rx_udp_checksum_errs; 1827 u32 rsvd2[7]; 1828 u32 rx_switched_unicast_packets; 1829 u32 rx_switched_multicast_packets; 1830 u32 rx_switched_broadcast_packets; 1831 u32 rsvd3[3]; 1832 u32 tx_pauseframes; 1833 u32 tx_priority_pauseframes; 1834 u32 tx_controlframes; 1835 u32 rsvd4[10]; 1836 u32 rxpp_fifo_overflow_drop; 1837 u32 rx_input_fifo_overflow_drop; 1838 u32 pmem_fifo_overflow_drop; 1839 u32 jabber_events; 1840 u32 rsvd5[3]; 1841 }; 1842 1843 1844 struct be_rxf_stats_v1 { 1845 struct be_port_rxf_stats_v1 port[4]; 1846 u32 rsvd0[2]; 1847 u32 rx_drops_no_pbuf; 1848 u32 rx_drops_no_txpb; 1849 u32 rx_drops_no_erx_descr; 1850 u32 rx_drops_no_tpre_descr; 1851 u32 rsvd1[6]; 1852 u32 rx_drops_too_many_frags; 1853 u32 rx_drops_invalid_ring; 1854 u32 forwarded_packets; 1855 u32 rx_drops_mtu; 1856 u32 rsvd2[14]; 1857 }; 1858 1859 struct be_erx_stats_v1 { 1860 u32 rx_drops_no_fragments[68]; /* dwordS 0 to 67*/ 1861 u32 rsvd[4]; 1862 }; 1863 1864 struct be_port_rxf_stats_v2 { 1865 u32 rsvd0[10]; 1866 u32 roce_bytes_received_lsd; 1867 u32 roce_bytes_received_msd; 1868 u32 rsvd1[5]; 1869 u32 roce_frames_received; 1870 u32 rx_crc_errors; 1871 u32 rx_alignment_symbol_errors; 1872 u32 rx_pause_frames; 1873 u32 rx_priority_pause_frames; 1874 u32 rx_control_frames; 1875 u32 rx_in_range_errors; 1876 u32 rx_out_range_errors; 1877 u32 rx_frame_too_long; 1878 u32 rx_address_filtered; 1879 u32 rx_dropped_too_small; 1880 u32 rx_dropped_too_short; 1881 u32 rx_dropped_header_too_small; 1882 u32 rx_dropped_tcp_length; 1883 u32 rx_dropped_runt; 1884 u32 rsvd2[10]; 1885 u32 rx_ip_checksum_errs; 1886 u32 rx_tcp_checksum_errs; 1887 u32 rx_udp_checksum_errs; 1888 u32 rsvd3[7]; 1889 u32 rx_switched_unicast_packets; 1890 u32 rx_switched_multicast_packets; 1891 u32 rx_switched_broadcast_packets; 1892 u32 rsvd4[3]; 1893 u32 tx_pauseframes; 1894 u32 tx_priority_pauseframes; 1895 u32 tx_controlframes; 1896 u32 rsvd5[10]; 1897 u32 rxpp_fifo_overflow_drop; 1898 u32 rx_input_fifo_overflow_drop; 1899 u32 pmem_fifo_overflow_drop; 1900 u32 jabber_events; 1901 u32 rsvd6[3]; 1902 u32 rx_drops_payload_size; 1903 u32 rx_drops_clipped_header; 1904 u32 rx_drops_crc; 1905 u32 roce_drops_payload_len; 1906 u32 roce_drops_crc; 1907 u32 rsvd7[19]; 1908 }; 1909 1910 struct be_rxf_stats_v2 { 1911 struct be_port_rxf_stats_v2 port[4]; 1912 u32 rsvd0[2]; 1913 u32 rx_drops_no_pbuf; 1914 u32 rx_drops_no_txpb; 1915 u32 rx_drops_no_erx_descr; 1916 u32 rx_drops_no_tpre_descr; 1917 u32 rsvd1[6]; 1918 u32 rx_drops_too_many_frags; 1919 u32 rx_drops_invalid_ring; 1920 u32 forwarded_packets; 1921 u32 rx_drops_mtu; 1922 u32 rsvd2[35]; 1923 }; 1924 1925 struct be_hw_stats_v1 { 1926 struct be_rxf_stats_v1 rxf; 1927 u32 rsvd0[BE_TXP_SW_SZ]; 1928 struct be_erx_stats_v1 erx; 1929 struct be_pmem_stats pmem; 1930 u32 rsvd1[18]; 1931 }; 1932 1933 struct be_cmd_req_get_stats_v1 { 1934 struct be_cmd_req_hdr hdr; 1935 u8 rsvd[sizeof(struct be_hw_stats_v1)]; 1936 }; 1937 1938 struct be_cmd_resp_get_stats_v1 { 1939 struct be_cmd_resp_hdr hdr; 1940 struct be_hw_stats_v1 hw_stats; 1941 }; 1942 1943 struct be_erx_stats_v2 { 1944 u32 rx_drops_no_fragments[136]; /* dwordS 0 to 135*/ 1945 u32 rsvd[3]; 1946 }; 1947 1948 struct be_hw_stats_v2 { 1949 struct be_rxf_stats_v2 rxf; 1950 u32 rsvd0[BE_TXP_SW_SZ]; 1951 struct be_erx_stats_v2 erx; 1952 struct be_pmem_stats pmem; 1953 u32 rsvd1[18]; 1954 }; 1955 1956 struct be_cmd_req_get_stats_v2 { 1957 struct be_cmd_req_hdr hdr; 1958 u8 rsvd[sizeof(struct be_hw_stats_v2)]; 1959 }; 1960 1961 struct be_cmd_resp_get_stats_v2 { 1962 struct be_cmd_resp_hdr hdr; 1963 struct be_hw_stats_v2 hw_stats; 1964 }; 1965 1966 /************** get fat capabilites *******************/ 1967 #define MAX_MODULES 27 1968 #define MAX_MODES 4 1969 #define MODE_UART 0 1970 #define FW_LOG_LEVEL_DEFAULT 48 1971 #define FW_LOG_LEVEL_FATAL 64 1972 1973 struct ext_fat_mode { 1974 u8 mode; 1975 u8 rsvd0; 1976 u16 port_mask; 1977 u32 dbg_lvl; 1978 u64 fun_mask; 1979 } __packed; 1980 1981 struct ext_fat_modules { 1982 u8 modules_str[32]; 1983 u32 modules_id; 1984 u32 num_modes; 1985 struct ext_fat_mode trace_lvl[MAX_MODES]; 1986 } __packed; 1987 1988 struct be_fat_conf_params { 1989 u32 max_log_entries; 1990 u32 log_entry_size; 1991 u8 log_type; 1992 u8 max_log_funs; 1993 u8 max_log_ports; 1994 u8 rsvd0; 1995 u32 supp_modes; 1996 u32 num_modules; 1997 struct ext_fat_modules module[MAX_MODULES]; 1998 } __packed; 1999 2000 struct be_cmd_req_get_ext_fat_caps { 2001 struct be_cmd_req_hdr hdr; 2002 u32 parameter_type; 2003 }; 2004 2005 struct be_cmd_resp_get_ext_fat_caps { 2006 struct be_cmd_resp_hdr hdr; 2007 struct be_fat_conf_params get_params; 2008 }; 2009 2010 struct be_cmd_req_set_ext_fat_caps { 2011 struct be_cmd_req_hdr hdr; 2012 struct be_fat_conf_params set_params; 2013 }; 2014 2015 #define RESOURCE_DESC_SIZE_V0 72 2016 #define RESOURCE_DESC_SIZE_V1 88 2017 #define PCIE_RESOURCE_DESC_TYPE_V0 0x40 2018 #define NIC_RESOURCE_DESC_TYPE_V0 0x41 2019 #define PCIE_RESOURCE_DESC_TYPE_V1 0x50 2020 #define NIC_RESOURCE_DESC_TYPE_V1 0x51 2021 #define PORT_RESOURCE_DESC_TYPE_V1 0x55 2022 #define MAX_RESOURCE_DESC 264 2023 2024 #define VFT_SHIFT 3 /* VF template */ 2025 #define IMM_SHIFT 6 /* Immediate */ 2026 #define NOSV_SHIFT 7 /* No save */ 2027 2028 struct be_res_desc_hdr { 2029 u8 desc_type; 2030 u8 desc_len; 2031 } __packed; 2032 2033 struct be_port_res_desc { 2034 struct be_res_desc_hdr hdr; 2035 u8 rsvd0; 2036 u8 flags; 2037 u8 link_num; 2038 u8 mc_type; 2039 u16 rsvd1; 2040 2041 #define NV_TYPE_MASK 0x3 /* bits 0-1 */ 2042 #define NV_TYPE_DISABLED 1 2043 #define NV_TYPE_VXLAN 3 2044 #define SOCVID_SHIFT 2 /* Strip outer vlan */ 2045 #define RCVID_SHIFT 4 /* Report vlan */ 2046 u8 nv_flags; 2047 u8 rsvd2; 2048 __le16 nv_port; /* vxlan/gre port */ 2049 u32 rsvd3[19]; 2050 } __packed; 2051 2052 struct be_pcie_res_desc { 2053 struct be_res_desc_hdr hdr; 2054 u8 rsvd0; 2055 u8 flags; 2056 u16 rsvd1; 2057 u8 pf_num; 2058 u8 rsvd2; 2059 u32 rsvd3; 2060 u8 sriov_state; 2061 u8 pf_state; 2062 u8 pf_type; 2063 u8 rsvd4; 2064 u16 num_vfs; 2065 u16 rsvd5; 2066 u32 rsvd6[17]; 2067 } __packed; 2068 2069 struct be_nic_res_desc { 2070 struct be_res_desc_hdr hdr; 2071 u8 rsvd1; 2072 2073 #define QUN_SHIFT 4 /* QoS is in absolute units */ 2074 u8 flags; 2075 u8 vf_num; 2076 u8 rsvd2; 2077 u8 pf_num; 2078 u8 rsvd3; 2079 u16 unicast_mac_count; 2080 u8 rsvd4[6]; 2081 u16 mcc_count; 2082 u16 vlan_count; 2083 u16 mcast_mac_count; 2084 u16 txq_count; 2085 u16 rq_count; 2086 u16 rssq_count; 2087 u16 lro_count; 2088 u16 cq_count; 2089 u16 toe_conn_count; 2090 u16 eq_count; 2091 u16 vlan_id; 2092 u16 iface_count; 2093 u32 cap_flags; 2094 u8 link_param; 2095 u8 rsvd6; 2096 u16 channel_id_param; 2097 u32 bw_min; 2098 u32 bw_max; 2099 u8 acpi_params; 2100 u8 wol_param; 2101 u16 rsvd7; 2102 u16 tunnel_iface_count; 2103 u16 direct_tenant_iface_count; 2104 u32 rsvd8[6]; 2105 } __packed; 2106 2107 /************ Multi-Channel type ***********/ 2108 enum mc_type { 2109 MC_NONE = 0x01, 2110 UMC = 0x02, 2111 FLEX10 = 0x03, 2112 vNIC1 = 0x04, 2113 nPAR = 0x05, 2114 UFP = 0x06, 2115 vNIC2 = 0x07 2116 }; 2117 2118 /* Is BE in a multi-channel mode */ 2119 static inline bool be_is_mc(struct be_adapter *adapter) 2120 { 2121 return adapter->mc_type > MC_NONE; 2122 } 2123 2124 struct be_cmd_req_get_func_config { 2125 struct be_cmd_req_hdr hdr; 2126 }; 2127 2128 struct be_cmd_resp_get_func_config { 2129 struct be_cmd_resp_hdr hdr; 2130 u32 desc_count; 2131 u8 func_param[MAX_RESOURCE_DESC * RESOURCE_DESC_SIZE_V1]; 2132 }; 2133 2134 #define ACTIVE_PROFILE_TYPE 0x2 2135 struct be_cmd_req_get_profile_config { 2136 struct be_cmd_req_hdr hdr; 2137 u8 rsvd; 2138 u8 type; 2139 u16 rsvd1; 2140 }; 2141 2142 struct be_cmd_resp_get_profile_config { 2143 struct be_cmd_resp_hdr hdr; 2144 u32 desc_count; 2145 u8 func_param[MAX_RESOURCE_DESC * RESOURCE_DESC_SIZE_V1]; 2146 }; 2147 2148 struct be_cmd_req_set_profile_config { 2149 struct be_cmd_req_hdr hdr; 2150 u32 rsvd; 2151 u32 desc_count; 2152 u8 desc[2 * RESOURCE_DESC_SIZE_V1]; 2153 } __packed; 2154 2155 struct be_cmd_req_get_active_profile { 2156 struct be_cmd_req_hdr hdr; 2157 u32 rsvd; 2158 } __packed; 2159 2160 struct be_cmd_resp_get_active_profile { 2161 struct be_cmd_resp_hdr hdr; 2162 u16 active_profile_id; 2163 u16 next_profile_id; 2164 } __packed; 2165 2166 struct be_cmd_enable_disable_vf { 2167 struct be_cmd_req_hdr hdr; 2168 u8 enable; 2169 u8 rsvd[3]; 2170 }; 2171 2172 struct be_cmd_req_intr_set { 2173 struct be_cmd_req_hdr hdr; 2174 u8 intr_enabled; 2175 u8 rsvd[3]; 2176 }; 2177 2178 static inline bool check_privilege(struct be_adapter *adapter, u32 flags) 2179 { 2180 return flags & adapter->cmd_privileges ? true : false; 2181 } 2182 2183 /************** Get IFACE LIST *******************/ 2184 struct be_if_desc { 2185 u32 if_id; 2186 u32 cap_flags; 2187 u32 en_flags; 2188 }; 2189 2190 struct be_cmd_req_get_iface_list { 2191 struct be_cmd_req_hdr hdr; 2192 }; 2193 2194 struct be_cmd_resp_get_iface_list { 2195 struct be_cmd_req_hdr hdr; 2196 u32 if_cnt; 2197 struct be_if_desc if_desc; 2198 }; 2199 2200 /*************** Set logical link ********************/ 2201 #define PLINK_TRACK_SHIFT 8 2202 struct be_cmd_req_set_ll_link { 2203 struct be_cmd_req_hdr hdr; 2204 u32 link_config; /* Bit 0: UP_DOWN, Bit 9: PLINK */ 2205 }; 2206 2207 /************** Manage IFACE Filters *******************/ 2208 #define OP_CONVERT_NORMAL_TO_TUNNEL 0 2209 #define OP_CONVERT_TUNNEL_TO_NORMAL 1 2210 2211 struct be_cmd_req_manage_iface_filters { 2212 struct be_cmd_req_hdr hdr; 2213 u8 op; 2214 u8 rsvd0; 2215 u8 flags; 2216 u8 rsvd1; 2217 u32 tunnel_iface_id; 2218 u32 target_iface_id; 2219 u8 mac[6]; 2220 u16 vlan_tag; 2221 u32 tenant_id; 2222 u32 filter_id; 2223 u32 cap_flags; 2224 u32 cap_control_flags; 2225 } __packed; 2226 2227 int be_pci_fnum_get(struct be_adapter *adapter); 2228 int be_fw_wait_ready(struct be_adapter *adapter); 2229 int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr, 2230 bool permanent, u32 if_handle, u32 pmac_id); 2231 int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr, u32 if_id, 2232 u32 *pmac_id, u32 domain); 2233 int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, int pmac_id, 2234 u32 domain); 2235 int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags, 2236 u32 *if_handle, u32 domain); 2237 int be_cmd_if_destroy(struct be_adapter *adapter, int if_handle, u32 domain); 2238 int be_cmd_eq_create(struct be_adapter *adapter, struct be_eq_obj *eqo); 2239 int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq, 2240 struct be_queue_info *eq, bool no_delay, 2241 int num_cqe_dma_coalesce); 2242 int be_cmd_mccq_create(struct be_adapter *adapter, struct be_queue_info *mccq, 2243 struct be_queue_info *cq); 2244 int be_cmd_txq_create(struct be_adapter *adapter, struct be_tx_obj *txo); 2245 int be_cmd_rxq_create(struct be_adapter *adapter, struct be_queue_info *rxq, 2246 u16 cq_id, u16 frag_size, u32 if_id, u32 rss, u8 *rss_id); 2247 int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q, 2248 int type); 2249 int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q); 2250 int be_cmd_link_status_query(struct be_adapter *adapter, u16 *link_speed, 2251 u8 *link_status, u32 dom); 2252 int be_cmd_reset(struct be_adapter *adapter); 2253 int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd); 2254 int lancer_cmd_get_pport_stats(struct be_adapter *adapter, 2255 struct be_dma_mem *nonemb_cmd); 2256 int be_cmd_get_fw_ver(struct be_adapter *adapter); 2257 int be_cmd_modify_eqd(struct be_adapter *adapter, struct be_set_eqd *, int num); 2258 int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array, 2259 u32 num); 2260 int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 status); 2261 int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc); 2262 int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc); 2263 int be_cmd_query_fw_cfg(struct be_adapter *adapter); 2264 int be_cmd_reset_function(struct be_adapter *adapter); 2265 int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable, 2266 u32 rss_hash_opts, u16 table_size, const u8 *rss_hkey); 2267 int be_process_mcc(struct be_adapter *adapter); 2268 int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num, u8 beacon, 2269 u8 status, u8 state); 2270 int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, 2271 u32 *state); 2272 int be_cmd_read_port_transceiver_data(struct be_adapter *adapter, 2273 u8 page_num, u8 *data); 2274 int be_cmd_query_cable_type(struct be_adapter *adapter); 2275 int be_cmd_query_sfp_info(struct be_adapter *adapter); 2276 int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd, 2277 u32 flash_oper, u32 flash_opcode, u32 img_offset, 2278 u32 buf_size); 2279 int lancer_cmd_write_object(struct be_adapter *adapter, struct be_dma_mem *cmd, 2280 u32 data_size, u32 data_offset, 2281 const char *obj_name, u32 *data_written, 2282 u8 *change_status, u8 *addn_status); 2283 int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd, 2284 u32 data_size, u32 data_offset, const char *obj_name, 2285 u32 *data_read, u32 *eof, u8 *addn_status); 2286 int lancer_cmd_delete_object(struct be_adapter *adapter, const char *obj_name); 2287 int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc, 2288 u16 img_optype, u32 img_offset, u32 crc_offset); 2289 int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac, 2290 struct be_dma_mem *nonemb_cmd); 2291 int be_cmd_fw_init(struct be_adapter *adapter); 2292 int be_cmd_fw_clean(struct be_adapter *adapter); 2293 void be_async_mcc_enable(struct be_adapter *adapter); 2294 void be_async_mcc_disable(struct be_adapter *adapter); 2295 int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num, 2296 u32 loopback_type, u32 pkt_size, u32 num_pkts, 2297 u64 pattern); 2298 int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern, u32 byte_cnt, 2299 struct be_dma_mem *cmd); 2300 int be_cmd_get_seeprom_data(struct be_adapter *adapter, 2301 struct be_dma_mem *nonemb_cmd); 2302 int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num, 2303 u8 loopback_type, u8 enable); 2304 int be_cmd_get_phy_info(struct be_adapter *adapter); 2305 int be_cmd_config_qos(struct be_adapter *adapter, u32 max_rate, 2306 u16 link_speed, u8 domain); 2307 void be_detect_error(struct be_adapter *adapter); 2308 int be_cmd_get_die_temperature(struct be_adapter *adapter); 2309 int be_cmd_get_cntl_attributes(struct be_adapter *adapter); 2310 int be_cmd_req_native_mode(struct be_adapter *adapter); 2311 int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size); 2312 int be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf); 2313 int be_cmd_get_fn_privileges(struct be_adapter *adapter, u32 *privilege, 2314 u32 domain); 2315 int be_cmd_set_fn_privileges(struct be_adapter *adapter, u32 privileges, 2316 u32 vf_num); 2317 int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac, 2318 bool *pmac_id_active, u32 *pmac_id, 2319 u32 if_handle, u8 domain); 2320 int be_cmd_get_active_mac(struct be_adapter *adapter, u32 pmac_id, u8 *mac, 2321 u32 if_handle, bool active, u32 domain); 2322 int be_cmd_get_perm_mac(struct be_adapter *adapter, u8 *mac); 2323 int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array, u8 mac_count, 2324 u32 domain); 2325 int be_cmd_set_mac(struct be_adapter *adapter, u8 *mac, int if_id, u32 dom); 2326 int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid, u32 domain, 2327 u16 intf_id, u16 hsw_mode); 2328 int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid, u32 domain, 2329 u16 intf_id, u8 *mode); 2330 int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter); 2331 int be_cmd_set_fw_log_level(struct be_adapter *adapter, u32 level); 2332 int be_cmd_get_fw_log_level(struct be_adapter *adapter); 2333 int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter, 2334 struct be_dma_mem *cmd); 2335 int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter, 2336 struct be_dma_mem *cmd, 2337 struct be_fat_conf_params *cfgs); 2338 int lancer_physdev_ctrl(struct be_adapter *adapter, u32 mask); 2339 int lancer_initiate_dump(struct be_adapter *adapter); 2340 int lancer_delete_dump(struct be_adapter *adapter); 2341 bool dump_present(struct be_adapter *adapter); 2342 int lancer_test_and_set_rdy_state(struct be_adapter *adapter); 2343 int be_cmd_query_port_name(struct be_adapter *adapter); 2344 int be_cmd_get_func_config(struct be_adapter *adapter, 2345 struct be_resources *res); 2346 int be_cmd_get_profile_config(struct be_adapter *adapter, 2347 struct be_resources *res, u8 domain); 2348 int be_cmd_get_active_profile(struct be_adapter *adapter, u16 *profile); 2349 int be_cmd_get_if_id(struct be_adapter *adapter, struct be_vf_cfg *vf_cfg, 2350 int vf_num); 2351 int be_cmd_enable_vf(struct be_adapter *adapter, u8 domain); 2352 int be_cmd_intr_set(struct be_adapter *adapter, bool intr_enable); 2353 int be_cmd_set_logical_link_config(struct be_adapter *adapter, 2354 int link_state, u8 domain); 2355 int be_cmd_set_vxlan_port(struct be_adapter *adapter, __be16 port); 2356 int be_cmd_manage_iface(struct be_adapter *adapter, u32 iface, u8 op); 2357 int be_cmd_set_sriov_config(struct be_adapter *adapter, 2358 struct be_resources res, u16 num_vfs); 2359