1 /*
2  * Copyright (C) 2005 - 2013 Emulex
3  * All rights reserved.
4  *
5  * This program is free software; you can redistribute it and/or
6  * modify it under the terms of the GNU General Public License version 2
7  * as published by the Free Software Foundation.  The full GNU General
8  * Public License is included in this distribution in the file called COPYING.
9  *
10  * Contact Information:
11  * linux-drivers@emulex.com
12  *
13  * Emulex
14  * 3333 Susan Street
15  * Costa Mesa, CA 92626
16  */
17 
18 /*
19  * The driver sends configuration and managements command requests to the
20  * firmware in the BE. These requests are communicated to the processor
21  * using Work Request Blocks (WRBs) submitted to the MCC-WRB ring or via one
22  * WRB inside a MAILBOX.
23  * The commands are serviced by the ARM processor in the BladeEngine's MPU.
24  */
25 
26 struct be_sge {
27 	u32 pa_lo;
28 	u32 pa_hi;
29 	u32 len;
30 };
31 
32 #define MCC_WRB_EMBEDDED_MASK	1 	/* bit 0 of dword 0*/
33 #define MCC_WRB_SGE_CNT_SHIFT	3	/* bits 3 - 7 of dword 0 */
34 #define MCC_WRB_SGE_CNT_MASK	0x1F	/* bits 3 - 7 of dword 0 */
35 struct be_mcc_wrb {
36 	u32 embedded;		/* dword 0 */
37 	u32 payload_length;	/* dword 1 */
38 	u32 tag0;		/* dword 2 */
39 	u32 tag1;		/* dword 3 */
40 	u32 rsvd;		/* dword 4 */
41 	union {
42 		u8 embedded_payload[236]; /* used by embedded cmds */
43 		struct be_sge sgl[19];    /* used by non-embedded cmds */
44 	} payload;
45 };
46 
47 #define CQE_FLAGS_VALID_MASK 		(1 << 31)
48 #define CQE_FLAGS_ASYNC_MASK 		(1 << 30)
49 #define CQE_FLAGS_COMPLETED_MASK 	(1 << 28)
50 #define CQE_FLAGS_CONSUMED_MASK 	(1 << 27)
51 
52 /* Completion Status */
53 enum {
54 	MCC_STATUS_SUCCESS = 0,
55 	MCC_STATUS_FAILED = 1,
56 	MCC_STATUS_ILLEGAL_REQUEST = 2,
57 	MCC_STATUS_ILLEGAL_FIELD = 3,
58 	MCC_STATUS_INSUFFICIENT_BUFFER = 4,
59 	MCC_STATUS_UNAUTHORIZED_REQUEST = 5,
60 	MCC_STATUS_NOT_SUPPORTED = 66
61 };
62 
63 #define MCC_ADDL_STS_INSUFFICIENT_RESOURCES	0x16
64 
65 #define CQE_STATUS_COMPL_MASK		0xFFFF
66 #define CQE_STATUS_COMPL_SHIFT		0	/* bits 0 - 15 */
67 #define CQE_STATUS_EXTD_MASK		0xFFFF
68 #define CQE_STATUS_EXTD_SHIFT		16	/* bits 16 - 31 */
69 
70 struct be_mcc_compl {
71 	u32 status;		/* dword 0 */
72 	u32 tag0;		/* dword 1 */
73 	u32 tag1;		/* dword 2 */
74 	u32 flags;		/* dword 3 */
75 };
76 
77 /* When the async bit of mcc_compl is set, the last 4 bytes of
78  * mcc_compl is interpreted as follows:
79  */
80 #define ASYNC_TRAILER_EVENT_CODE_SHIFT	8	/* bits 8 - 15 */
81 #define ASYNC_TRAILER_EVENT_CODE_MASK	0xFF
82 #define ASYNC_TRAILER_EVENT_TYPE_SHIFT	16
83 #define ASYNC_TRAILER_EVENT_TYPE_MASK	0xFF
84 #define ASYNC_EVENT_CODE_LINK_STATE	0x1
85 #define ASYNC_EVENT_CODE_GRP_5		0x5
86 #define ASYNC_EVENT_QOS_SPEED		0x1
87 #define ASYNC_EVENT_COS_PRIORITY	0x2
88 #define ASYNC_EVENT_PVID_STATE		0x3
89 #define ASYNC_EVENT_CODE_QNQ		0x6
90 #define ASYNC_DEBUG_EVENT_TYPE_QNQ	1
91 
92 struct be_async_event_trailer {
93 	u32 code;
94 };
95 
96 enum {
97 	LINK_DOWN	= 0x0,
98 	LINK_UP		= 0x1
99 };
100 #define LINK_STATUS_MASK			0x1
101 #define LOGICAL_LINK_STATUS_MASK		0x2
102 
103 /* When the event code of an async trailer is link-state, the mcc_compl
104  * must be interpreted as follows
105  */
106 struct be_async_event_link_state {
107 	u8 physical_port;
108 	u8 port_link_status;
109 	u8 port_duplex;
110 	u8 port_speed;
111 	u8 port_fault;
112 	u8 rsvd0[7];
113 	struct be_async_event_trailer trailer;
114 } __packed;
115 
116 /* When the event code of an async trailer is GRP-5 and event_type is QOS_SPEED
117  * the mcc_compl must be interpreted as follows
118  */
119 struct be_async_event_grp5_qos_link_speed {
120 	u8 physical_port;
121 	u8 rsvd[5];
122 	u16 qos_link_speed;
123 	u32 event_tag;
124 	struct be_async_event_trailer trailer;
125 } __packed;
126 
127 /* When the event code of an async trailer is GRP5 and event type is
128  * CoS-Priority, the mcc_compl must be interpreted as follows
129  */
130 struct be_async_event_grp5_cos_priority {
131 	u8 physical_port;
132 	u8 available_priority_bmap;
133 	u8 reco_default_priority;
134 	u8 valid;
135 	u8 rsvd0;
136 	u8 event_tag;
137 	struct be_async_event_trailer trailer;
138 } __packed;
139 
140 /* When the event code of an async trailer is GRP5 and event type is
141  * PVID state, the mcc_compl must be interpreted as follows
142  */
143 struct be_async_event_grp5_pvid_state {
144 	u8 enabled;
145 	u8 rsvd0;
146 	u16 tag;
147 	u32 event_tag;
148 	u32 rsvd1;
149 	struct be_async_event_trailer trailer;
150 } __packed;
151 
152 /* async event indicating outer VLAN tag in QnQ */
153 struct be_async_event_qnq {
154 	u8 valid;	/* Indicates if outer VLAN is valid */
155 	u8 rsvd0;
156 	u16 vlan_tag;
157 	u32 event_tag;
158 	u8 rsvd1[4];
159 	struct be_async_event_trailer trailer;
160 } __packed;
161 
162 struct be_mcc_mailbox {
163 	struct be_mcc_wrb wrb;
164 	struct be_mcc_compl compl;
165 };
166 
167 #define CMD_SUBSYSTEM_COMMON	0x1
168 #define CMD_SUBSYSTEM_ETH 	0x3
169 #define CMD_SUBSYSTEM_LOWLEVEL  0xb
170 
171 #define OPCODE_COMMON_NTWK_MAC_QUERY			1
172 #define OPCODE_COMMON_NTWK_MAC_SET			2
173 #define OPCODE_COMMON_NTWK_MULTICAST_SET		3
174 #define OPCODE_COMMON_NTWK_VLAN_CONFIG  		4
175 #define OPCODE_COMMON_NTWK_LINK_STATUS_QUERY		5
176 #define OPCODE_COMMON_READ_FLASHROM			6
177 #define OPCODE_COMMON_WRITE_FLASHROM			7
178 #define OPCODE_COMMON_CQ_CREATE				12
179 #define OPCODE_COMMON_EQ_CREATE				13
180 #define OPCODE_COMMON_MCC_CREATE			21
181 #define OPCODE_COMMON_SET_QOS				28
182 #define OPCODE_COMMON_MCC_CREATE_EXT			90
183 #define OPCODE_COMMON_SEEPROM_READ			30
184 #define OPCODE_COMMON_GET_CNTL_ATTRIBUTES               32
185 #define OPCODE_COMMON_NTWK_RX_FILTER    		34
186 #define OPCODE_COMMON_GET_FW_VERSION			35
187 #define OPCODE_COMMON_SET_FLOW_CONTROL			36
188 #define OPCODE_COMMON_GET_FLOW_CONTROL			37
189 #define OPCODE_COMMON_SET_FRAME_SIZE			39
190 #define OPCODE_COMMON_MODIFY_EQ_DELAY			41
191 #define OPCODE_COMMON_FIRMWARE_CONFIG			42
192 #define OPCODE_COMMON_NTWK_INTERFACE_CREATE 		50
193 #define OPCODE_COMMON_NTWK_INTERFACE_DESTROY 		51
194 #define OPCODE_COMMON_MCC_DESTROY        		53
195 #define OPCODE_COMMON_CQ_DESTROY        		54
196 #define OPCODE_COMMON_EQ_DESTROY        		55
197 #define OPCODE_COMMON_QUERY_FIRMWARE_CONFIG		58
198 #define OPCODE_COMMON_NTWK_PMAC_ADD			59
199 #define OPCODE_COMMON_NTWK_PMAC_DEL			60
200 #define OPCODE_COMMON_FUNCTION_RESET			61
201 #define OPCODE_COMMON_MANAGE_FAT			68
202 #define OPCODE_COMMON_ENABLE_DISABLE_BEACON		69
203 #define OPCODE_COMMON_GET_BEACON_STATE			70
204 #define OPCODE_COMMON_READ_TRANSRECV_DATA		73
205 #define OPCODE_COMMON_GET_PORT_NAME			77
206 #define OPCODE_COMMON_SET_INTERRUPT_ENABLE		89
207 #define OPCODE_COMMON_SET_FN_PRIVILEGES			100
208 #define OPCODE_COMMON_GET_PHY_DETAILS			102
209 #define OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP		103
210 #define OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES	121
211 #define OPCODE_COMMON_GET_EXT_FAT_CAPABILITES		125
212 #define OPCODE_COMMON_SET_EXT_FAT_CAPABILITES		126
213 #define OPCODE_COMMON_GET_MAC_LIST			147
214 #define OPCODE_COMMON_SET_MAC_LIST			148
215 #define OPCODE_COMMON_GET_HSW_CONFIG			152
216 #define OPCODE_COMMON_GET_FUNC_CONFIG			160
217 #define OPCODE_COMMON_GET_PROFILE_CONFIG		164
218 #define OPCODE_COMMON_SET_PROFILE_CONFIG		165
219 #define OPCODE_COMMON_GET_ACTIVE_PROFILE		167
220 #define OPCODE_COMMON_SET_HSW_CONFIG			153
221 #define OPCODE_COMMON_GET_FN_PRIVILEGES			170
222 #define OPCODE_COMMON_READ_OBJECT			171
223 #define OPCODE_COMMON_WRITE_OBJECT			172
224 #define OPCODE_COMMON_GET_IFACE_LIST			194
225 #define OPCODE_COMMON_ENABLE_DISABLE_VF			196
226 
227 #define OPCODE_ETH_RSS_CONFIG				1
228 #define OPCODE_ETH_ACPI_CONFIG				2
229 #define OPCODE_ETH_PROMISCUOUS				3
230 #define OPCODE_ETH_GET_STATISTICS			4
231 #define OPCODE_ETH_TX_CREATE				7
232 #define OPCODE_ETH_RX_CREATE            		8
233 #define OPCODE_ETH_TX_DESTROY           		9
234 #define OPCODE_ETH_RX_DESTROY           		10
235 #define OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG		12
236 #define OPCODE_ETH_GET_PPORT_STATS			18
237 
238 #define OPCODE_LOWLEVEL_HOST_DDR_DMA                    17
239 #define OPCODE_LOWLEVEL_LOOPBACK_TEST                   18
240 #define OPCODE_LOWLEVEL_SET_LOOPBACK_MODE		19
241 
242 struct be_cmd_req_hdr {
243 	u8 opcode;		/* dword 0 */
244 	u8 subsystem;		/* dword 0 */
245 	u8 port_number;		/* dword 0 */
246 	u8 domain;		/* dword 0 */
247 	u32 timeout;		/* dword 1 */
248 	u32 request_length;	/* dword 2 */
249 	u8 version;		/* dword 3 */
250 	u8 rsvd[3];		/* dword 3 */
251 };
252 
253 #define RESP_HDR_INFO_OPCODE_SHIFT	0	/* bits 0 - 7 */
254 #define RESP_HDR_INFO_SUBSYS_SHIFT	8 	/* bits 8 - 15 */
255 struct be_cmd_resp_hdr {
256 	u8 opcode;		/* dword 0 */
257 	u8 subsystem;		/* dword 0 */
258 	u8 rsvd[2];		/* dword 0 */
259 	u8 status;		/* dword 1 */
260 	u8 add_status;		/* dword 1 */
261 	u8 rsvd1[2];		/* dword 1 */
262 	u32 response_length;	/* dword 2 */
263 	u32 actual_resp_len;	/* dword 3 */
264 };
265 
266 struct phys_addr {
267 	u32 lo;
268 	u32 hi;
269 };
270 
271 /**************************
272  * BE Command definitions *
273  **************************/
274 
275 /* Pseudo amap definition in which each bit of the actual structure is defined
276  * as a byte: used to calculate offset/shift/mask of each field */
277 struct amap_eq_context {
278 	u8 cidx[13];		/* dword 0*/
279 	u8 rsvd0[3];		/* dword 0*/
280 	u8 epidx[13];		/* dword 0*/
281 	u8 valid;		/* dword 0*/
282 	u8 rsvd1;		/* dword 0*/
283 	u8 size;		/* dword 0*/
284 	u8 pidx[13];		/* dword 1*/
285 	u8 rsvd2[3];		/* dword 1*/
286 	u8 pd[10];		/* dword 1*/
287 	u8 count[3];		/* dword 1*/
288 	u8 solevent;		/* dword 1*/
289 	u8 stalled;		/* dword 1*/
290 	u8 armed;		/* dword 1*/
291 	u8 rsvd3[4];		/* dword 2*/
292 	u8 func[8];		/* dword 2*/
293 	u8 rsvd4;		/* dword 2*/
294 	u8 delaymult[10];	/* dword 2*/
295 	u8 rsvd5[2];		/* dword 2*/
296 	u8 phase[2];		/* dword 2*/
297 	u8 nodelay;		/* dword 2*/
298 	u8 rsvd6[4];		/* dword 2*/
299 	u8 rsvd7[32];		/* dword 3*/
300 } __packed;
301 
302 struct be_cmd_req_eq_create {
303 	struct be_cmd_req_hdr hdr;
304 	u16 num_pages;		/* sword */
305 	u16 rsvd0;		/* sword */
306 	u8 context[sizeof(struct amap_eq_context) / 8];
307 	struct phys_addr pages[8];
308 } __packed;
309 
310 struct be_cmd_resp_eq_create {
311 	struct be_cmd_resp_hdr resp_hdr;
312 	u16 eq_id;		/* sword */
313 	u16 msix_idx;		/* available only in v2 */
314 } __packed;
315 
316 /******************** Mac query ***************************/
317 enum {
318 	MAC_ADDRESS_TYPE_STORAGE = 0x0,
319 	MAC_ADDRESS_TYPE_NETWORK = 0x1,
320 	MAC_ADDRESS_TYPE_PD = 0x2,
321 	MAC_ADDRESS_TYPE_MANAGEMENT = 0x3
322 };
323 
324 struct mac_addr {
325 	u16 size_of_struct;
326 	u8 addr[ETH_ALEN];
327 } __packed;
328 
329 struct be_cmd_req_mac_query {
330 	struct be_cmd_req_hdr hdr;
331 	u8 type;
332 	u8 permanent;
333 	u16 if_id;
334 	u32 pmac_id;
335 } __packed;
336 
337 struct be_cmd_resp_mac_query {
338 	struct be_cmd_resp_hdr hdr;
339 	struct mac_addr mac;
340 };
341 
342 /******************** PMac Add ***************************/
343 struct be_cmd_req_pmac_add {
344 	struct be_cmd_req_hdr hdr;
345 	u32 if_id;
346 	u8 mac_address[ETH_ALEN];
347 	u8 rsvd0[2];
348 } __packed;
349 
350 struct be_cmd_resp_pmac_add {
351 	struct be_cmd_resp_hdr hdr;
352 	u32 pmac_id;
353 };
354 
355 /******************** PMac Del ***************************/
356 struct be_cmd_req_pmac_del {
357 	struct be_cmd_req_hdr hdr;
358 	u32 if_id;
359 	u32 pmac_id;
360 };
361 
362 /******************** Create CQ ***************************/
363 /* Pseudo amap definition in which each bit of the actual structure is defined
364  * as a byte: used to calculate offset/shift/mask of each field */
365 struct amap_cq_context_be {
366 	u8 cidx[11];		/* dword 0*/
367 	u8 rsvd0;		/* dword 0*/
368 	u8 coalescwm[2];	/* dword 0*/
369 	u8 nodelay;		/* dword 0*/
370 	u8 epidx[11];		/* dword 0*/
371 	u8 rsvd1;		/* dword 0*/
372 	u8 count[2];		/* dword 0*/
373 	u8 valid;		/* dword 0*/
374 	u8 solevent;		/* dword 0*/
375 	u8 eventable;		/* dword 0*/
376 	u8 pidx[11];		/* dword 1*/
377 	u8 rsvd2;		/* dword 1*/
378 	u8 pd[10];		/* dword 1*/
379 	u8 eqid[8];		/* dword 1*/
380 	u8 stalled;		/* dword 1*/
381 	u8 armed;		/* dword 1*/
382 	u8 rsvd3[4];		/* dword 2*/
383 	u8 func[8];		/* dword 2*/
384 	u8 rsvd4[20];		/* dword 2*/
385 	u8 rsvd5[32];		/* dword 3*/
386 } __packed;
387 
388 struct amap_cq_context_v2 {
389 	u8 rsvd0[12];		/* dword 0*/
390 	u8 coalescwm[2];	/* dword 0*/
391 	u8 nodelay;		/* dword 0*/
392 	u8 rsvd1[12];		/* dword 0*/
393 	u8 count[2];		/* dword 0*/
394 	u8 valid;		/* dword 0*/
395 	u8 rsvd2;		/* dword 0*/
396 	u8 eventable;		/* dword 0*/
397 	u8 eqid[16];		/* dword 1*/
398 	u8 rsvd3[15];		/* dword 1*/
399 	u8 armed;		/* dword 1*/
400 	u8 rsvd4[32];		/* dword 2*/
401 	u8 rsvd5[32];		/* dword 3*/
402 } __packed;
403 
404 struct be_cmd_req_cq_create {
405 	struct be_cmd_req_hdr hdr;
406 	u16 num_pages;
407 	u8 page_size;
408 	u8 rsvd0;
409 	u8 context[sizeof(struct amap_cq_context_be) / 8];
410 	struct phys_addr pages[8];
411 } __packed;
412 
413 
414 struct be_cmd_resp_cq_create {
415 	struct be_cmd_resp_hdr hdr;
416 	u16 cq_id;
417 	u16 rsvd0;
418 } __packed;
419 
420 struct be_cmd_req_get_fat {
421 	struct be_cmd_req_hdr hdr;
422 	u32 fat_operation;
423 	u32 read_log_offset;
424 	u32 read_log_length;
425 	u32 data_buffer_size;
426 	u32 data_buffer[1];
427 } __packed;
428 
429 struct be_cmd_resp_get_fat {
430 	struct be_cmd_resp_hdr hdr;
431 	u32 log_size;
432 	u32 read_log_length;
433 	u32 rsvd[2];
434 	u32 data_buffer[1];
435 } __packed;
436 
437 
438 /******************** Create MCCQ ***************************/
439 /* Pseudo amap definition in which each bit of the actual structure is defined
440  * as a byte: used to calculate offset/shift/mask of each field */
441 struct amap_mcc_context_be {
442 	u8 con_index[14];
443 	u8 rsvd0[2];
444 	u8 ring_size[4];
445 	u8 fetch_wrb;
446 	u8 fetch_r2t;
447 	u8 cq_id[10];
448 	u8 prod_index[14];
449 	u8 fid[8];
450 	u8 pdid[9];
451 	u8 valid;
452 	u8 rsvd1[32];
453 	u8 rsvd2[32];
454 } __packed;
455 
456 struct amap_mcc_context_v1 {
457 	u8 async_cq_id[16];
458 	u8 ring_size[4];
459 	u8 rsvd0[12];
460 	u8 rsvd1[31];
461 	u8 valid;
462 	u8 async_cq_valid[1];
463 	u8 rsvd2[31];
464 	u8 rsvd3[32];
465 } __packed;
466 
467 struct be_cmd_req_mcc_create {
468 	struct be_cmd_req_hdr hdr;
469 	u16 num_pages;
470 	u16 cq_id;
471 	u8 context[sizeof(struct amap_mcc_context_be) / 8];
472 	struct phys_addr pages[8];
473 } __packed;
474 
475 struct be_cmd_req_mcc_ext_create {
476 	struct be_cmd_req_hdr hdr;
477 	u16 num_pages;
478 	u16 cq_id;
479 	u32 async_event_bitmap[1];
480 	u8 context[sizeof(struct amap_mcc_context_v1) / 8];
481 	struct phys_addr pages[8];
482 } __packed;
483 
484 struct be_cmd_resp_mcc_create {
485 	struct be_cmd_resp_hdr hdr;
486 	u16 id;
487 	u16 rsvd0;
488 } __packed;
489 
490 /******************** Create TxQ ***************************/
491 #define BE_ETH_TX_RING_TYPE_STANDARD    	2
492 #define BE_ULP1_NUM				1
493 
494 struct be_cmd_req_eth_tx_create {
495 	struct be_cmd_req_hdr hdr;
496 	u8 num_pages;
497 	u8 ulp_num;
498 	u16 type;
499 	u16 if_id;
500 	u8 queue_size;
501 	u8 rsvd0;
502 	u32 rsvd1;
503 	u16 cq_id;
504 	u16 rsvd2;
505 	u32 rsvd3[13];
506 	struct phys_addr pages[8];
507 } __packed;
508 
509 struct be_cmd_resp_eth_tx_create {
510 	struct be_cmd_resp_hdr hdr;
511 	u16 cid;
512 	u16 rid;
513 	u32 db_offset;
514 	u32 rsvd0[4];
515 } __packed;
516 
517 /******************** Create RxQ ***************************/
518 struct be_cmd_req_eth_rx_create {
519 	struct be_cmd_req_hdr hdr;
520 	u16 cq_id;
521 	u8 frag_size;
522 	u8 num_pages;
523 	struct phys_addr pages[2];
524 	u32 interface_id;
525 	u16 max_frame_size;
526 	u16 rsvd0;
527 	u32 rss_queue;
528 } __packed;
529 
530 struct be_cmd_resp_eth_rx_create {
531 	struct be_cmd_resp_hdr hdr;
532 	u16 id;
533 	u8 rss_id;
534 	u8 rsvd0;
535 } __packed;
536 
537 /******************** Q Destroy  ***************************/
538 /* Type of Queue to be destroyed */
539 enum {
540 	QTYPE_EQ = 1,
541 	QTYPE_CQ,
542 	QTYPE_TXQ,
543 	QTYPE_RXQ,
544 	QTYPE_MCCQ
545 };
546 
547 struct be_cmd_req_q_destroy {
548 	struct be_cmd_req_hdr hdr;
549 	u16 id;
550 	u16 bypass_flush;	/* valid only for rx q destroy */
551 } __packed;
552 
553 /************ I/f Create (it's actually I/f Config Create)**********/
554 
555 /* Capability flags for the i/f */
556 enum be_if_flags {
557 	BE_IF_FLAGS_RSS = 0x4,
558 	BE_IF_FLAGS_PROMISCUOUS = 0x8,
559 	BE_IF_FLAGS_BROADCAST = 0x10,
560 	BE_IF_FLAGS_UNTAGGED = 0x20,
561 	BE_IF_FLAGS_ULP = 0x40,
562 	BE_IF_FLAGS_VLAN_PROMISCUOUS = 0x80,
563 	BE_IF_FLAGS_VLAN = 0x100,
564 	BE_IF_FLAGS_MCAST_PROMISCUOUS = 0x200,
565 	BE_IF_FLAGS_PASS_L2_ERRORS = 0x400,
566 	BE_IF_FLAGS_PASS_L3L4_ERRORS = 0x800,
567 	BE_IF_FLAGS_MULTICAST = 0x1000
568 };
569 
570 #define BE_IF_CAP_FLAGS_WANT (BE_IF_FLAGS_RSS | BE_IF_FLAGS_PROMISCUOUS |\
571 			 BE_IF_FLAGS_BROADCAST | BE_IF_FLAGS_VLAN_PROMISCUOUS |\
572 			 BE_IF_FLAGS_VLAN | BE_IF_FLAGS_MCAST_PROMISCUOUS |\
573 			 BE_IF_FLAGS_PASS_L3L4_ERRORS | BE_IF_FLAGS_MULTICAST |\
574 			 BE_IF_FLAGS_UNTAGGED)
575 
576 /* An RX interface is an object with one or more MAC addresses and
577  * filtering capabilities. */
578 struct be_cmd_req_if_create {
579 	struct be_cmd_req_hdr hdr;
580 	u32 version;		/* ignore currently */
581 	u32 capability_flags;
582 	u32 enable_flags;
583 	u8 mac_addr[ETH_ALEN];
584 	u8 rsvd0;
585 	u8 pmac_invalid; /* if set, don't attach the mac addr to the i/f */
586 	u32 vlan_tag;	 /* not used currently */
587 } __packed;
588 
589 struct be_cmd_resp_if_create {
590 	struct be_cmd_resp_hdr hdr;
591 	u32 interface_id;
592 	u32 pmac_id;
593 };
594 
595 /****** I/f Destroy(it's actually I/f Config Destroy )**********/
596 struct be_cmd_req_if_destroy {
597 	struct be_cmd_req_hdr hdr;
598 	u32 interface_id;
599 };
600 
601 /*************** HW Stats Get **********************************/
602 struct be_port_rxf_stats_v0 {
603 	u32 rx_bytes_lsd;	/* dword 0*/
604 	u32 rx_bytes_msd;	/* dword 1*/
605 	u32 rx_total_frames;	/* dword 2*/
606 	u32 rx_unicast_frames;	/* dword 3*/
607 	u32 rx_multicast_frames;	/* dword 4*/
608 	u32 rx_broadcast_frames;	/* dword 5*/
609 	u32 rx_crc_errors;	/* dword 6*/
610 	u32 rx_alignment_symbol_errors;	/* dword 7*/
611 	u32 rx_pause_frames;	/* dword 8*/
612 	u32 rx_control_frames;	/* dword 9*/
613 	u32 rx_in_range_errors;	/* dword 10*/
614 	u32 rx_out_range_errors;	/* dword 11*/
615 	u32 rx_frame_too_long;	/* dword 12*/
616 	u32 rx_address_filtered;	/* dword 13*/
617 	u32 rx_vlan_filtered;	/* dword 14*/
618 	u32 rx_dropped_too_small;	/* dword 15*/
619 	u32 rx_dropped_too_short;	/* dword 16*/
620 	u32 rx_dropped_header_too_small;	/* dword 17*/
621 	u32 rx_dropped_tcp_length;	/* dword 18*/
622 	u32 rx_dropped_runt;	/* dword 19*/
623 	u32 rx_64_byte_packets;	/* dword 20*/
624 	u32 rx_65_127_byte_packets;	/* dword 21*/
625 	u32 rx_128_256_byte_packets;	/* dword 22*/
626 	u32 rx_256_511_byte_packets;	/* dword 23*/
627 	u32 rx_512_1023_byte_packets;	/* dword 24*/
628 	u32 rx_1024_1518_byte_packets;	/* dword 25*/
629 	u32 rx_1519_2047_byte_packets;	/* dword 26*/
630 	u32 rx_2048_4095_byte_packets;	/* dword 27*/
631 	u32 rx_4096_8191_byte_packets;	/* dword 28*/
632 	u32 rx_8192_9216_byte_packets;	/* dword 29*/
633 	u32 rx_ip_checksum_errs;	/* dword 30*/
634 	u32 rx_tcp_checksum_errs;	/* dword 31*/
635 	u32 rx_udp_checksum_errs;	/* dword 32*/
636 	u32 rx_non_rss_packets;	/* dword 33*/
637 	u32 rx_ipv4_packets;	/* dword 34*/
638 	u32 rx_ipv6_packets;	/* dword 35*/
639 	u32 rx_ipv4_bytes_lsd;	/* dword 36*/
640 	u32 rx_ipv4_bytes_msd;	/* dword 37*/
641 	u32 rx_ipv6_bytes_lsd;	/* dword 38*/
642 	u32 rx_ipv6_bytes_msd;	/* dword 39*/
643 	u32 rx_chute1_packets;	/* dword 40*/
644 	u32 rx_chute2_packets;	/* dword 41*/
645 	u32 rx_chute3_packets;	/* dword 42*/
646 	u32 rx_management_packets;	/* dword 43*/
647 	u32 rx_switched_unicast_packets;	/* dword 44*/
648 	u32 rx_switched_multicast_packets;	/* dword 45*/
649 	u32 rx_switched_broadcast_packets;	/* dword 46*/
650 	u32 tx_bytes_lsd;	/* dword 47*/
651 	u32 tx_bytes_msd;	/* dword 48*/
652 	u32 tx_unicastframes;	/* dword 49*/
653 	u32 tx_multicastframes;	/* dword 50*/
654 	u32 tx_broadcastframes;	/* dword 51*/
655 	u32 tx_pauseframes;	/* dword 52*/
656 	u32 tx_controlframes;	/* dword 53*/
657 	u32 tx_64_byte_packets;	/* dword 54*/
658 	u32 tx_65_127_byte_packets;	/* dword 55*/
659 	u32 tx_128_256_byte_packets;	/* dword 56*/
660 	u32 tx_256_511_byte_packets;	/* dword 57*/
661 	u32 tx_512_1023_byte_packets;	/* dword 58*/
662 	u32 tx_1024_1518_byte_packets;	/* dword 59*/
663 	u32 tx_1519_2047_byte_packets;	/* dword 60*/
664 	u32 tx_2048_4095_byte_packets;	/* dword 61*/
665 	u32 tx_4096_8191_byte_packets;	/* dword 62*/
666 	u32 tx_8192_9216_byte_packets;	/* dword 63*/
667 	u32 rx_fifo_overflow;	/* dword 64*/
668 	u32 rx_input_fifo_overflow;	/* dword 65*/
669 };
670 
671 struct be_rxf_stats_v0 {
672 	struct be_port_rxf_stats_v0 port[2];
673 	u32 rx_drops_no_pbuf;	/* dword 132*/
674 	u32 rx_drops_no_txpb;	/* dword 133*/
675 	u32 rx_drops_no_erx_descr;	/* dword 134*/
676 	u32 rx_drops_no_tpre_descr;	/* dword 135*/
677 	u32 management_rx_port_packets;	/* dword 136*/
678 	u32 management_rx_port_bytes;	/* dword 137*/
679 	u32 management_rx_port_pause_frames;	/* dword 138*/
680 	u32 management_rx_port_errors;	/* dword 139*/
681 	u32 management_tx_port_packets;	/* dword 140*/
682 	u32 management_tx_port_bytes;	/* dword 141*/
683 	u32 management_tx_port_pause;	/* dword 142*/
684 	u32 management_rx_port_rxfifo_overflow;	/* dword 143*/
685 	u32 rx_drops_too_many_frags;	/* dword 144*/
686 	u32 rx_drops_invalid_ring;	/* dword 145*/
687 	u32 forwarded_packets;	/* dword 146*/
688 	u32 rx_drops_mtu;	/* dword 147*/
689 	u32 rsvd0[7];
690 	u32 port0_jabber_events;
691 	u32 port1_jabber_events;
692 	u32 rsvd1[6];
693 };
694 
695 struct be_erx_stats_v0 {
696 	u32 rx_drops_no_fragments[44];     /* dwordS 0 to 43*/
697 	u32 rsvd[4];
698 };
699 
700 struct be_pmem_stats {
701 	u32 eth_red_drops;
702 	u32 rsvd[5];
703 };
704 
705 struct be_hw_stats_v0 {
706 	struct be_rxf_stats_v0 rxf;
707 	u32 rsvd[48];
708 	struct be_erx_stats_v0 erx;
709 	struct be_pmem_stats pmem;
710 };
711 
712 struct be_cmd_req_get_stats_v0 {
713 	struct be_cmd_req_hdr hdr;
714 	u8 rsvd[sizeof(struct be_hw_stats_v0)];
715 };
716 
717 struct be_cmd_resp_get_stats_v0 {
718 	struct be_cmd_resp_hdr hdr;
719 	struct be_hw_stats_v0 hw_stats;
720 };
721 
722 struct lancer_pport_stats {
723 	u32 tx_packets_lo;
724 	u32 tx_packets_hi;
725 	u32 tx_unicast_packets_lo;
726 	u32 tx_unicast_packets_hi;
727 	u32 tx_multicast_packets_lo;
728 	u32 tx_multicast_packets_hi;
729 	u32 tx_broadcast_packets_lo;
730 	u32 tx_broadcast_packets_hi;
731 	u32 tx_bytes_lo;
732 	u32 tx_bytes_hi;
733 	u32 tx_unicast_bytes_lo;
734 	u32 tx_unicast_bytes_hi;
735 	u32 tx_multicast_bytes_lo;
736 	u32 tx_multicast_bytes_hi;
737 	u32 tx_broadcast_bytes_lo;
738 	u32 tx_broadcast_bytes_hi;
739 	u32 tx_discards_lo;
740 	u32 tx_discards_hi;
741 	u32 tx_errors_lo;
742 	u32 tx_errors_hi;
743 	u32 tx_pause_frames_lo;
744 	u32 tx_pause_frames_hi;
745 	u32 tx_pause_on_frames_lo;
746 	u32 tx_pause_on_frames_hi;
747 	u32 tx_pause_off_frames_lo;
748 	u32 tx_pause_off_frames_hi;
749 	u32 tx_internal_mac_errors_lo;
750 	u32 tx_internal_mac_errors_hi;
751 	u32 tx_control_frames_lo;
752 	u32 tx_control_frames_hi;
753 	u32 tx_packets_64_bytes_lo;
754 	u32 tx_packets_64_bytes_hi;
755 	u32 tx_packets_65_to_127_bytes_lo;
756 	u32 tx_packets_65_to_127_bytes_hi;
757 	u32 tx_packets_128_to_255_bytes_lo;
758 	u32 tx_packets_128_to_255_bytes_hi;
759 	u32 tx_packets_256_to_511_bytes_lo;
760 	u32 tx_packets_256_to_511_bytes_hi;
761 	u32 tx_packets_512_to_1023_bytes_lo;
762 	u32 tx_packets_512_to_1023_bytes_hi;
763 	u32 tx_packets_1024_to_1518_bytes_lo;
764 	u32 tx_packets_1024_to_1518_bytes_hi;
765 	u32 tx_packets_1519_to_2047_bytes_lo;
766 	u32 tx_packets_1519_to_2047_bytes_hi;
767 	u32 tx_packets_2048_to_4095_bytes_lo;
768 	u32 tx_packets_2048_to_4095_bytes_hi;
769 	u32 tx_packets_4096_to_8191_bytes_lo;
770 	u32 tx_packets_4096_to_8191_bytes_hi;
771 	u32 tx_packets_8192_to_9216_bytes_lo;
772 	u32 tx_packets_8192_to_9216_bytes_hi;
773 	u32 tx_lso_packets_lo;
774 	u32 tx_lso_packets_hi;
775 	u32 rx_packets_lo;
776 	u32 rx_packets_hi;
777 	u32 rx_unicast_packets_lo;
778 	u32 rx_unicast_packets_hi;
779 	u32 rx_multicast_packets_lo;
780 	u32 rx_multicast_packets_hi;
781 	u32 rx_broadcast_packets_lo;
782 	u32 rx_broadcast_packets_hi;
783 	u32 rx_bytes_lo;
784 	u32 rx_bytes_hi;
785 	u32 rx_unicast_bytes_lo;
786 	u32 rx_unicast_bytes_hi;
787 	u32 rx_multicast_bytes_lo;
788 	u32 rx_multicast_bytes_hi;
789 	u32 rx_broadcast_bytes_lo;
790 	u32 rx_broadcast_bytes_hi;
791 	u32 rx_unknown_protos;
792 	u32 rsvd_69; /* Word 69 is reserved */
793 	u32 rx_discards_lo;
794 	u32 rx_discards_hi;
795 	u32 rx_errors_lo;
796 	u32 rx_errors_hi;
797 	u32 rx_crc_errors_lo;
798 	u32 rx_crc_errors_hi;
799 	u32 rx_alignment_errors_lo;
800 	u32 rx_alignment_errors_hi;
801 	u32 rx_symbol_errors_lo;
802 	u32 rx_symbol_errors_hi;
803 	u32 rx_pause_frames_lo;
804 	u32 rx_pause_frames_hi;
805 	u32 rx_pause_on_frames_lo;
806 	u32 rx_pause_on_frames_hi;
807 	u32 rx_pause_off_frames_lo;
808 	u32 rx_pause_off_frames_hi;
809 	u32 rx_frames_too_long_lo;
810 	u32 rx_frames_too_long_hi;
811 	u32 rx_internal_mac_errors_lo;
812 	u32 rx_internal_mac_errors_hi;
813 	u32 rx_undersize_packets;
814 	u32 rx_oversize_packets;
815 	u32 rx_fragment_packets;
816 	u32 rx_jabbers;
817 	u32 rx_control_frames_lo;
818 	u32 rx_control_frames_hi;
819 	u32 rx_control_frames_unknown_opcode_lo;
820 	u32 rx_control_frames_unknown_opcode_hi;
821 	u32 rx_in_range_errors;
822 	u32 rx_out_of_range_errors;
823 	u32 rx_address_filtered;
824 	u32 rx_vlan_filtered;
825 	u32 rx_dropped_too_small;
826 	u32 rx_dropped_too_short;
827 	u32 rx_dropped_header_too_small;
828 	u32 rx_dropped_invalid_tcp_length;
829 	u32 rx_dropped_runt;
830 	u32 rx_ip_checksum_errors;
831 	u32 rx_tcp_checksum_errors;
832 	u32 rx_udp_checksum_errors;
833 	u32 rx_non_rss_packets;
834 	u32 rsvd_111;
835 	u32 rx_ipv4_packets_lo;
836 	u32 rx_ipv4_packets_hi;
837 	u32 rx_ipv6_packets_lo;
838 	u32 rx_ipv6_packets_hi;
839 	u32 rx_ipv4_bytes_lo;
840 	u32 rx_ipv4_bytes_hi;
841 	u32 rx_ipv6_bytes_lo;
842 	u32 rx_ipv6_bytes_hi;
843 	u32 rx_nic_packets_lo;
844 	u32 rx_nic_packets_hi;
845 	u32 rx_tcp_packets_lo;
846 	u32 rx_tcp_packets_hi;
847 	u32 rx_iscsi_packets_lo;
848 	u32 rx_iscsi_packets_hi;
849 	u32 rx_management_packets_lo;
850 	u32 rx_management_packets_hi;
851 	u32 rx_switched_unicast_packets_lo;
852 	u32 rx_switched_unicast_packets_hi;
853 	u32 rx_switched_multicast_packets_lo;
854 	u32 rx_switched_multicast_packets_hi;
855 	u32 rx_switched_broadcast_packets_lo;
856 	u32 rx_switched_broadcast_packets_hi;
857 	u32 num_forwards_lo;
858 	u32 num_forwards_hi;
859 	u32 rx_fifo_overflow;
860 	u32 rx_input_fifo_overflow;
861 	u32 rx_drops_too_many_frags_lo;
862 	u32 rx_drops_too_many_frags_hi;
863 	u32 rx_drops_invalid_queue;
864 	u32 rsvd_141;
865 	u32 rx_drops_mtu_lo;
866 	u32 rx_drops_mtu_hi;
867 	u32 rx_packets_64_bytes_lo;
868 	u32 rx_packets_64_bytes_hi;
869 	u32 rx_packets_65_to_127_bytes_lo;
870 	u32 rx_packets_65_to_127_bytes_hi;
871 	u32 rx_packets_128_to_255_bytes_lo;
872 	u32 rx_packets_128_to_255_bytes_hi;
873 	u32 rx_packets_256_to_511_bytes_lo;
874 	u32 rx_packets_256_to_511_bytes_hi;
875 	u32 rx_packets_512_to_1023_bytes_lo;
876 	u32 rx_packets_512_to_1023_bytes_hi;
877 	u32 rx_packets_1024_to_1518_bytes_lo;
878 	u32 rx_packets_1024_to_1518_bytes_hi;
879 	u32 rx_packets_1519_to_2047_bytes_lo;
880 	u32 rx_packets_1519_to_2047_bytes_hi;
881 	u32 rx_packets_2048_to_4095_bytes_lo;
882 	u32 rx_packets_2048_to_4095_bytes_hi;
883 	u32 rx_packets_4096_to_8191_bytes_lo;
884 	u32 rx_packets_4096_to_8191_bytes_hi;
885 	u32 rx_packets_8192_to_9216_bytes_lo;
886 	u32 rx_packets_8192_to_9216_bytes_hi;
887 };
888 
889 struct pport_stats_params {
890 	u16 pport_num;
891 	u8 rsvd;
892 	u8 reset_stats;
893 };
894 
895 struct lancer_cmd_req_pport_stats {
896 	struct be_cmd_req_hdr hdr;
897 	union {
898 		struct pport_stats_params params;
899 		u8 rsvd[sizeof(struct lancer_pport_stats)];
900 	} cmd_params;
901 };
902 
903 struct lancer_cmd_resp_pport_stats {
904 	struct be_cmd_resp_hdr hdr;
905 	struct lancer_pport_stats pport_stats;
906 };
907 
908 static inline struct lancer_pport_stats*
909 	pport_stats_from_cmd(struct be_adapter *adapter)
910 {
911 	struct lancer_cmd_resp_pport_stats *cmd = adapter->stats_cmd.va;
912 	return &cmd->pport_stats;
913 }
914 
915 struct be_cmd_req_get_cntl_addnl_attribs {
916 	struct be_cmd_req_hdr hdr;
917 	u8 rsvd[8];
918 };
919 
920 struct be_cmd_resp_get_cntl_addnl_attribs {
921 	struct be_cmd_resp_hdr hdr;
922 	u16 ipl_file_number;
923 	u8 ipl_file_version;
924 	u8 rsvd0;
925 	u8 on_die_temperature; /* in degrees centigrade*/
926 	u8 rsvd1[3];
927 };
928 
929 struct be_cmd_req_vlan_config {
930 	struct be_cmd_req_hdr hdr;
931 	u8 interface_id;
932 	u8 promiscuous;
933 	u8 untagged;
934 	u8 num_vlan;
935 	u16 normal_vlan[64];
936 } __packed;
937 
938 /******************* RX FILTER ******************************/
939 #define BE_MAX_MC		64 /* set mcast promisc if > 64 */
940 struct macaddr {
941 	u8 byte[ETH_ALEN];
942 };
943 
944 struct be_cmd_req_rx_filter {
945 	struct be_cmd_req_hdr hdr;
946 	u32 global_flags_mask;
947 	u32 global_flags;
948 	u32 if_flags_mask;
949 	u32 if_flags;
950 	u32 if_id;
951 	u32 mcast_num;
952 	struct macaddr mcast_mac[BE_MAX_MC];
953 };
954 
955 /******************** Link Status Query *******************/
956 struct be_cmd_req_link_status {
957 	struct be_cmd_req_hdr hdr;
958 	u32 rsvd;
959 };
960 
961 enum {
962 	PHY_LINK_DUPLEX_NONE = 0x0,
963 	PHY_LINK_DUPLEX_HALF = 0x1,
964 	PHY_LINK_DUPLEX_FULL = 0x2
965 };
966 
967 enum {
968 	PHY_LINK_SPEED_ZERO = 0x0, 	/* => No link */
969 	PHY_LINK_SPEED_10MBPS = 0x1,
970 	PHY_LINK_SPEED_100MBPS = 0x2,
971 	PHY_LINK_SPEED_1GBPS = 0x3,
972 	PHY_LINK_SPEED_10GBPS = 0x4,
973 	PHY_LINK_SPEED_20GBPS = 0x5,
974 	PHY_LINK_SPEED_25GBPS = 0x6,
975 	PHY_LINK_SPEED_40GBPS = 0x7
976 };
977 
978 struct be_cmd_resp_link_status {
979 	struct be_cmd_resp_hdr hdr;
980 	u8 physical_port;
981 	u8 mac_duplex;
982 	u8 mac_speed;
983 	u8 mac_fault;
984 	u8 mgmt_mac_duplex;
985 	u8 mgmt_mac_speed;
986 	u16 link_speed;
987 	u8 logical_link_status;
988 	u8 rsvd1[3];
989 } __packed;
990 
991 /******************** Port Identification ***************************/
992 /*    Identifies the type of port attached to NIC     */
993 struct be_cmd_req_port_type {
994 	struct be_cmd_req_hdr hdr;
995 	u32 page_num;
996 	u32 port;
997 };
998 
999 enum {
1000 	TR_PAGE_A0 = 0xa0,
1001 	TR_PAGE_A2 = 0xa2
1002 };
1003 
1004 struct be_cmd_resp_port_type {
1005 	struct be_cmd_resp_hdr hdr;
1006 	u32 page_num;
1007 	u32 port;
1008 	struct data {
1009 		u8 identifier;
1010 		u8 identifier_ext;
1011 		u8 connector;
1012 		u8 transceiver[8];
1013 		u8 rsvd0[3];
1014 		u8 length_km;
1015 		u8 length_hm;
1016 		u8 length_om1;
1017 		u8 length_om2;
1018 		u8 length_cu;
1019 		u8 length_cu_m;
1020 		u8 vendor_name[16];
1021 		u8 rsvd;
1022 		u8 vendor_oui[3];
1023 		u8 vendor_pn[16];
1024 		u8 vendor_rev[4];
1025 	} data;
1026 };
1027 
1028 /******************** Get FW Version *******************/
1029 struct be_cmd_req_get_fw_version {
1030 	struct be_cmd_req_hdr hdr;
1031 	u8 rsvd0[FW_VER_LEN];
1032 	u8 rsvd1[FW_VER_LEN];
1033 } __packed;
1034 
1035 struct be_cmd_resp_get_fw_version {
1036 	struct be_cmd_resp_hdr hdr;
1037 	u8 firmware_version_string[FW_VER_LEN];
1038 	u8 fw_on_flash_version_string[FW_VER_LEN];
1039 } __packed;
1040 
1041 /******************** Set Flow Contrl *******************/
1042 struct be_cmd_req_set_flow_control {
1043 	struct be_cmd_req_hdr hdr;
1044 	u16 tx_flow_control;
1045 	u16 rx_flow_control;
1046 } __packed;
1047 
1048 /******************** Get Flow Contrl *******************/
1049 struct be_cmd_req_get_flow_control {
1050 	struct be_cmd_req_hdr hdr;
1051 	u32 rsvd;
1052 };
1053 
1054 struct be_cmd_resp_get_flow_control {
1055 	struct be_cmd_resp_hdr hdr;
1056 	u16 tx_flow_control;
1057 	u16 rx_flow_control;
1058 } __packed;
1059 
1060 /******************** Modify EQ Delay *******************/
1061 struct be_set_eqd {
1062 	u32 eq_id;
1063 	u32 phase;
1064 	u32 delay_multiplier;
1065 };
1066 
1067 struct be_cmd_req_modify_eq_delay {
1068 	struct be_cmd_req_hdr hdr;
1069 	u32 num_eq;
1070 	struct be_set_eqd set_eqd[MAX_EVT_QS];
1071 } __packed;
1072 
1073 struct be_cmd_resp_modify_eq_delay {
1074 	struct be_cmd_resp_hdr hdr;
1075 	u32 rsvd0;
1076 } __packed;
1077 
1078 /******************** Get FW Config *******************/
1079 /* The HW can come up in either of the following multi-channel modes
1080  * based on the skew/IPL.
1081  */
1082 #define RDMA_ENABLED				0x4
1083 #define FLEX10_MODE				0x400
1084 #define VNIC_MODE				0x20000
1085 #define UMC_ENABLED				0x1000000
1086 struct be_cmd_req_query_fw_cfg {
1087 	struct be_cmd_req_hdr hdr;
1088 	u32 rsvd[31];
1089 };
1090 
1091 struct be_cmd_resp_query_fw_cfg {
1092 	struct be_cmd_resp_hdr hdr;
1093 	u32 be_config_number;
1094 	u32 asic_revision;
1095 	u32 phys_port;
1096 	u32 function_mode;
1097 	u32 rsvd[26];
1098 	u32 function_caps;
1099 };
1100 
1101 /* Is BE in a multi-channel mode */
1102 static inline bool be_is_mc(struct be_adapter *adapter)
1103 {
1104 	return adapter->function_mode & FLEX10_MODE ||
1105 		adapter->function_mode & VNIC_MODE ||
1106 		adapter->function_mode & UMC_ENABLED;
1107 }
1108 
1109 /******************** RSS Config ****************************************/
1110 /* RSS type		Input parameters used to compute RX hash
1111  * RSS_ENABLE_IPV4	SRC IPv4, DST IPv4
1112  * RSS_ENABLE_TCP_IPV4	SRC IPv4, DST IPv4, TCP SRC PORT, TCP DST PORT
1113  * RSS_ENABLE_IPV6	SRC IPv6, DST IPv6
1114  * RSS_ENABLE_TCP_IPV6	SRC IPv6, DST IPv6, TCP SRC PORT, TCP DST PORT
1115  * RSS_ENABLE_UDP_IPV4	SRC IPv4, DST IPv4, UDP SRC PORT, UDP DST PORT
1116  * RSS_ENABLE_UDP_IPV6	SRC IPv6, DST IPv6, UDP SRC PORT, UDP DST PORT
1117  *
1118  * When multiple RSS types are enabled, HW picks the best hash policy
1119  * based on the type of the received packet.
1120  */
1121 #define RSS_ENABLE_NONE				0x0
1122 #define RSS_ENABLE_IPV4				0x1
1123 #define RSS_ENABLE_TCP_IPV4			0x2
1124 #define RSS_ENABLE_IPV6				0x4
1125 #define RSS_ENABLE_TCP_IPV6			0x8
1126 #define RSS_ENABLE_UDP_IPV4			0x10
1127 #define RSS_ENABLE_UDP_IPV6			0x20
1128 
1129 #define L3_RSS_FLAGS				(RXH_IP_DST | RXH_IP_SRC)
1130 #define L4_RSS_FLAGS				(RXH_L4_B_0_1 | RXH_L4_B_2_3)
1131 
1132 struct be_cmd_req_rss_config {
1133 	struct be_cmd_req_hdr hdr;
1134 	u32 if_id;
1135 	u16 enable_rss;
1136 	u16 cpu_table_size_log2;
1137 	u32 hash[10];
1138 	u8 cpu_table[128];
1139 	u8 flush;
1140 	u8 rsvd0[3];
1141 };
1142 
1143 /******************** Port Beacon ***************************/
1144 
1145 #define BEACON_STATE_ENABLED		0x1
1146 #define BEACON_STATE_DISABLED		0x0
1147 
1148 struct be_cmd_req_enable_disable_beacon {
1149 	struct be_cmd_req_hdr hdr;
1150 	u8  port_num;
1151 	u8  beacon_state;
1152 	u8  beacon_duration;
1153 	u8  status_duration;
1154 } __packed;
1155 
1156 struct be_cmd_resp_enable_disable_beacon {
1157 	struct be_cmd_resp_hdr resp_hdr;
1158 	u32 rsvd0;
1159 } __packed;
1160 
1161 struct be_cmd_req_get_beacon_state {
1162 	struct be_cmd_req_hdr hdr;
1163 	u8  port_num;
1164 	u8  rsvd0;
1165 	u16 rsvd1;
1166 } __packed;
1167 
1168 struct be_cmd_resp_get_beacon_state {
1169 	struct be_cmd_resp_hdr resp_hdr;
1170 	u8 beacon_state;
1171 	u8 rsvd0[3];
1172 } __packed;
1173 
1174 /****************** Firmware Flash ******************/
1175 struct flashrom_params {
1176 	u32 op_code;
1177 	u32 op_type;
1178 	u32 data_buf_size;
1179 	u32 offset;
1180 };
1181 
1182 struct be_cmd_write_flashrom {
1183 	struct be_cmd_req_hdr hdr;
1184 	struct flashrom_params params;
1185 	u8 data_buf[32768];
1186 	u8 rsvd[4];
1187 } __packed;
1188 
1189 /* cmd to read flash crc */
1190 struct be_cmd_read_flash_crc {
1191 	struct be_cmd_req_hdr hdr;
1192 	struct flashrom_params params;
1193 	u8 crc[4];
1194 	u8 rsvd[4];
1195 };
1196 /**************** Lancer Firmware Flash ************/
1197 struct amap_lancer_write_obj_context {
1198 	u8 write_length[24];
1199 	u8 reserved1[7];
1200 	u8 eof;
1201 } __packed;
1202 
1203 struct lancer_cmd_req_write_object {
1204 	struct be_cmd_req_hdr hdr;
1205 	u8 context[sizeof(struct amap_lancer_write_obj_context) / 8];
1206 	u32 write_offset;
1207 	u8 object_name[104];
1208 	u32 descriptor_count;
1209 	u32 buf_len;
1210 	u32 addr_low;
1211 	u32 addr_high;
1212 };
1213 
1214 #define LANCER_NO_RESET_NEEDED		0x00
1215 #define LANCER_FW_RESET_NEEDED		0x02
1216 struct lancer_cmd_resp_write_object {
1217 	u8 opcode;
1218 	u8 subsystem;
1219 	u8 rsvd1[2];
1220 	u8 status;
1221 	u8 additional_status;
1222 	u8 rsvd2[2];
1223 	u32 resp_len;
1224 	u32 actual_resp_len;
1225 	u32 actual_write_len;
1226 	u8 change_status;
1227 	u8 rsvd3[3];
1228 };
1229 
1230 /************************ Lancer Read FW info **************/
1231 #define LANCER_READ_FILE_CHUNK			(32*1024)
1232 #define LANCER_READ_FILE_EOF_MASK		0x80000000
1233 
1234 #define LANCER_FW_DUMP_FILE			"/dbg/dump.bin"
1235 #define LANCER_VPD_PF_FILE			"/vpd/ntr_pf.vpd"
1236 #define LANCER_VPD_VF_FILE			"/vpd/ntr_vf.vpd"
1237 
1238 struct lancer_cmd_req_read_object {
1239 	struct be_cmd_req_hdr hdr;
1240 	u32 desired_read_len;
1241 	u32 read_offset;
1242 	u8 object_name[104];
1243 	u32 descriptor_count;
1244 	u32 buf_len;
1245 	u32 addr_low;
1246 	u32 addr_high;
1247 };
1248 
1249 struct lancer_cmd_resp_read_object {
1250 	u8 opcode;
1251 	u8 subsystem;
1252 	u8 rsvd1[2];
1253 	u8 status;
1254 	u8 additional_status;
1255 	u8 rsvd2[2];
1256 	u32 resp_len;
1257 	u32 actual_resp_len;
1258 	u32 actual_read_len;
1259 	u32 eof;
1260 };
1261 
1262 /************************ WOL *******************************/
1263 struct be_cmd_req_acpi_wol_magic_config{
1264 	struct be_cmd_req_hdr hdr;
1265 	u32 rsvd0[145];
1266 	u8 magic_mac[6];
1267 	u8 rsvd2[2];
1268 } __packed;
1269 
1270 struct be_cmd_req_acpi_wol_magic_config_v1 {
1271 	struct be_cmd_req_hdr hdr;
1272 	u8 rsvd0[2];
1273 	u8 query_options;
1274 	u8 rsvd1[5];
1275 	u32 rsvd2[288];
1276 	u8 magic_mac[6];
1277 	u8 rsvd3[22];
1278 } __packed;
1279 
1280 struct be_cmd_resp_acpi_wol_magic_config_v1 {
1281 	struct be_cmd_resp_hdr hdr;
1282 	u8 rsvd0[2];
1283 	u8 wol_settings;
1284 	u8 rsvd1[5];
1285 	u32 rsvd2[295];
1286 } __packed;
1287 
1288 #define BE_GET_WOL_CAP			2
1289 
1290 #define BE_WOL_CAP			0x1
1291 #define BE_PME_D0_CAP			0x8
1292 #define BE_PME_D1_CAP			0x10
1293 #define BE_PME_D2_CAP			0x20
1294 #define BE_PME_D3HOT_CAP		0x40
1295 #define BE_PME_D3COLD_CAP		0x80
1296 
1297 /********************** LoopBack test *********************/
1298 struct be_cmd_req_loopback_test {
1299 	struct be_cmd_req_hdr hdr;
1300 	u32 loopback_type;
1301 	u32 num_pkts;
1302 	u64 pattern;
1303 	u32 src_port;
1304 	u32 dest_port;
1305 	u32 pkt_size;
1306 };
1307 
1308 struct be_cmd_resp_loopback_test {
1309 	struct be_cmd_resp_hdr resp_hdr;
1310 	u32    status;
1311 	u32    num_txfer;
1312 	u32    num_rx;
1313 	u32    miscomp_off;
1314 	u32    ticks_compl;
1315 };
1316 
1317 struct be_cmd_req_set_lmode {
1318 	struct be_cmd_req_hdr hdr;
1319 	u8 src_port;
1320 	u8 dest_port;
1321 	u8 loopback_type;
1322 	u8 loopback_state;
1323 };
1324 
1325 struct be_cmd_resp_set_lmode {
1326 	struct be_cmd_resp_hdr resp_hdr;
1327 	u8 rsvd0[4];
1328 };
1329 
1330 /********************** DDR DMA test *********************/
1331 struct be_cmd_req_ddrdma_test {
1332 	struct be_cmd_req_hdr hdr;
1333 	u64 pattern;
1334 	u32 byte_count;
1335 	u32 rsvd0;
1336 	u8  snd_buff[4096];
1337 	u8  rsvd1[4096];
1338 };
1339 
1340 struct be_cmd_resp_ddrdma_test {
1341 	struct be_cmd_resp_hdr hdr;
1342 	u64 pattern;
1343 	u32 byte_cnt;
1344 	u32 snd_err;
1345 	u8  rsvd0[4096];
1346 	u8  rcv_buff[4096];
1347 };
1348 
1349 /*********************** SEEPROM Read ***********************/
1350 
1351 #define BE_READ_SEEPROM_LEN 1024
1352 struct be_cmd_req_seeprom_read {
1353 	struct be_cmd_req_hdr hdr;
1354 	u8 rsvd0[BE_READ_SEEPROM_LEN];
1355 };
1356 
1357 struct be_cmd_resp_seeprom_read {
1358 	struct be_cmd_req_hdr hdr;
1359 	u8 seeprom_data[BE_READ_SEEPROM_LEN];
1360 };
1361 
1362 enum {
1363 	PHY_TYPE_CX4_10GB = 0,
1364 	PHY_TYPE_XFP_10GB,
1365 	PHY_TYPE_SFP_1GB,
1366 	PHY_TYPE_SFP_PLUS_10GB,
1367 	PHY_TYPE_KR_10GB,
1368 	PHY_TYPE_KX4_10GB,
1369 	PHY_TYPE_BASET_10GB,
1370 	PHY_TYPE_BASET_1GB,
1371 	PHY_TYPE_BASEX_1GB,
1372 	PHY_TYPE_SGMII,
1373 	PHY_TYPE_DISABLED = 255
1374 };
1375 
1376 #define BE_SUPPORTED_SPEED_NONE		0
1377 #define BE_SUPPORTED_SPEED_10MBPS	1
1378 #define BE_SUPPORTED_SPEED_100MBPS	2
1379 #define BE_SUPPORTED_SPEED_1GBPS	4
1380 #define BE_SUPPORTED_SPEED_10GBPS	8
1381 
1382 #define BE_AN_EN			0x2
1383 #define BE_PAUSE_SYM_EN			0x80
1384 
1385 /* MAC speed valid values */
1386 #define SPEED_DEFAULT  0x0
1387 #define SPEED_FORCED_10GB  0x1
1388 #define SPEED_FORCED_1GB  0x2
1389 #define SPEED_AUTONEG_10GB  0x3
1390 #define SPEED_AUTONEG_1GB  0x4
1391 #define SPEED_AUTONEG_100MB  0x5
1392 #define SPEED_AUTONEG_10GB_1GB 0x6
1393 #define SPEED_AUTONEG_10GB_1GB_100MB 0x7
1394 #define SPEED_AUTONEG_1GB_100MB  0x8
1395 #define SPEED_AUTONEG_10MB  0x9
1396 #define SPEED_AUTONEG_1GB_100MB_10MB 0xa
1397 #define SPEED_AUTONEG_100MB_10MB 0xb
1398 #define SPEED_FORCED_100MB  0xc
1399 #define SPEED_FORCED_10MB  0xd
1400 
1401 struct be_cmd_req_get_phy_info {
1402 	struct be_cmd_req_hdr hdr;
1403 	u8 rsvd0[24];
1404 };
1405 
1406 struct be_phy_info {
1407 	u16 phy_type;
1408 	u16 interface_type;
1409 	u32 misc_params;
1410 	u16 ext_phy_details;
1411 	u16 rsvd;
1412 	u16 auto_speeds_supported;
1413 	u16 fixed_speeds_supported;
1414 	u32 future_use[2];
1415 };
1416 
1417 struct be_cmd_resp_get_phy_info {
1418 	struct be_cmd_req_hdr hdr;
1419 	struct be_phy_info phy_info;
1420 };
1421 
1422 /*********************** Set QOS ***********************/
1423 
1424 #define BE_QOS_BITS_NIC				1
1425 
1426 struct be_cmd_req_set_qos {
1427 	struct be_cmd_req_hdr hdr;
1428 	u32 valid_bits;
1429 	u32 max_bps_nic;
1430 	u32 rsvd[7];
1431 };
1432 
1433 struct be_cmd_resp_set_qos {
1434 	struct be_cmd_resp_hdr hdr;
1435 	u32 rsvd;
1436 };
1437 
1438 /*********************** Controller Attributes ***********************/
1439 struct be_cmd_req_cntl_attribs {
1440 	struct be_cmd_req_hdr hdr;
1441 };
1442 
1443 struct be_cmd_resp_cntl_attribs {
1444 	struct be_cmd_resp_hdr hdr;
1445 	struct mgmt_controller_attrib attribs;
1446 };
1447 
1448 /*********************** Set driver function ***********************/
1449 #define CAPABILITY_SW_TIMESTAMPS	2
1450 #define CAPABILITY_BE3_NATIVE_ERX_API	4
1451 
1452 struct be_cmd_req_set_func_cap {
1453 	struct be_cmd_req_hdr hdr;
1454 	u32 valid_cap_flags;
1455 	u32 cap_flags;
1456 	u8 rsvd[212];
1457 };
1458 
1459 struct be_cmd_resp_set_func_cap {
1460 	struct be_cmd_resp_hdr hdr;
1461 	u32 valid_cap_flags;
1462 	u32 cap_flags;
1463 	u8 rsvd[212];
1464 };
1465 
1466 /*********************** Function Privileges ***********************/
1467 enum {
1468 	BE_PRIV_DEFAULT = 0x1,
1469 	BE_PRIV_LNKQUERY = 0x2,
1470 	BE_PRIV_LNKSTATS = 0x4,
1471 	BE_PRIV_LNKMGMT = 0x8,
1472 	BE_PRIV_LNKDIAG = 0x10,
1473 	BE_PRIV_UTILQUERY = 0x20,
1474 	BE_PRIV_FILTMGMT = 0x40,
1475 	BE_PRIV_IFACEMGMT = 0x80,
1476 	BE_PRIV_VHADM = 0x100,
1477 	BE_PRIV_DEVCFG = 0x200,
1478 	BE_PRIV_DEVSEC = 0x400
1479 };
1480 #define MAX_PRIVILEGES		(BE_PRIV_VHADM | BE_PRIV_DEVCFG | \
1481 				 BE_PRIV_DEVSEC)
1482 #define MIN_PRIVILEGES		BE_PRIV_DEFAULT
1483 
1484 struct be_cmd_priv_map {
1485 	u8 opcode;
1486 	u8 subsystem;
1487 	u32 priv_mask;
1488 };
1489 
1490 struct be_cmd_req_get_fn_privileges {
1491 	struct be_cmd_req_hdr hdr;
1492 	u32 rsvd;
1493 };
1494 
1495 struct be_cmd_resp_get_fn_privileges {
1496 	struct be_cmd_resp_hdr hdr;
1497 	u32 privilege_mask;
1498 };
1499 
1500 struct be_cmd_req_set_fn_privileges {
1501 	struct be_cmd_req_hdr hdr;
1502 	u32 privileges;		/* Used by BE3, SH-R */
1503 	u32 privileges_lancer;	/* Used by Lancer */
1504 };
1505 
1506 /******************** GET/SET_MACLIST  **************************/
1507 #define BE_MAX_MAC			64
1508 struct be_cmd_req_get_mac_list {
1509 	struct be_cmd_req_hdr hdr;
1510 	u8 mac_type;
1511 	u8 perm_override;
1512 	u16 iface_id;
1513 	u32 mac_id;
1514 	u32 rsvd[3];
1515 } __packed;
1516 
1517 struct get_list_macaddr {
1518 	u16 mac_addr_size;
1519 	union {
1520 		u8 macaddr[6];
1521 		struct {
1522 			u8 rsvd[2];
1523 			u32 mac_id;
1524 		} __packed s_mac_id;
1525 	} __packed mac_addr_id;
1526 } __packed;
1527 
1528 struct be_cmd_resp_get_mac_list {
1529 	struct be_cmd_resp_hdr hdr;
1530 	struct get_list_macaddr fd_macaddr; /* Factory default mac */
1531 	struct get_list_macaddr macid_macaddr; /* soft mac */
1532 	u8 true_mac_count;
1533 	u8 pseudo_mac_count;
1534 	u8 mac_list_size;
1535 	u8 rsvd;
1536 	/* perm override mac */
1537 	struct get_list_macaddr macaddr_list[BE_MAX_MAC];
1538 } __packed;
1539 
1540 struct be_cmd_req_set_mac_list {
1541 	struct be_cmd_req_hdr hdr;
1542 	u8 mac_count;
1543 	u8 rsvd1;
1544 	u16 rsvd2;
1545 	struct macaddr mac[BE_MAX_MAC];
1546 } __packed;
1547 
1548 /*********************** HSW Config ***********************/
1549 #define PORT_FWD_TYPE_VEPA		0x3
1550 #define PORT_FWD_TYPE_VEB		0x2
1551 
1552 struct amap_set_hsw_context {
1553 	u8 interface_id[16];
1554 	u8 rsvd0[14];
1555 	u8 pvid_valid;
1556 	u8 pport;
1557 	u8 rsvd1[6];
1558 	u8 port_fwd_type[3];
1559 	u8 rsvd2[7];
1560 	u8 pvid[16];
1561 	u8 rsvd3[32];
1562 	u8 rsvd4[32];
1563 	u8 rsvd5[32];
1564 } __packed;
1565 
1566 struct be_cmd_req_set_hsw_config {
1567 	struct be_cmd_req_hdr hdr;
1568 	u8 context[sizeof(struct amap_set_hsw_context) / 8];
1569 } __packed;
1570 
1571 struct be_cmd_resp_set_hsw_config {
1572 	struct be_cmd_resp_hdr hdr;
1573 	u32 rsvd;
1574 };
1575 
1576 struct amap_get_hsw_req_context {
1577 	u8 interface_id[16];
1578 	u8 rsvd0[14];
1579 	u8 pvid_valid;
1580 	u8 pport;
1581 } __packed;
1582 
1583 struct amap_get_hsw_resp_context {
1584 	u8 rsvd0[6];
1585 	u8 port_fwd_type[3];
1586 	u8 rsvd1[7];
1587 	u8 pvid[16];
1588 	u8 rsvd2[32];
1589 	u8 rsvd3[32];
1590 	u8 rsvd4[32];
1591 } __packed;
1592 
1593 struct be_cmd_req_get_hsw_config {
1594 	struct be_cmd_req_hdr hdr;
1595 	u8 context[sizeof(struct amap_get_hsw_req_context) / 8];
1596 } __packed;
1597 
1598 struct be_cmd_resp_get_hsw_config {
1599 	struct be_cmd_resp_hdr hdr;
1600 	u8 context[sizeof(struct amap_get_hsw_resp_context) / 8];
1601 	u32 rsvd;
1602 };
1603 
1604 /******************* get port names ***************/
1605 struct be_cmd_req_get_port_name {
1606 	struct be_cmd_req_hdr hdr;
1607 	u32 rsvd0;
1608 };
1609 
1610 struct be_cmd_resp_get_port_name {
1611 	struct be_cmd_req_hdr hdr;
1612 	u8 port_name[4];
1613 };
1614 
1615 /*************** HW Stats Get v1 **********************************/
1616 #define BE_TXP_SW_SZ			48
1617 struct be_port_rxf_stats_v1 {
1618 	u32 rsvd0[12];
1619 	u32 rx_crc_errors;
1620 	u32 rx_alignment_symbol_errors;
1621 	u32 rx_pause_frames;
1622 	u32 rx_priority_pause_frames;
1623 	u32 rx_control_frames;
1624 	u32 rx_in_range_errors;
1625 	u32 rx_out_range_errors;
1626 	u32 rx_frame_too_long;
1627 	u32 rx_address_filtered;
1628 	u32 rx_dropped_too_small;
1629 	u32 rx_dropped_too_short;
1630 	u32 rx_dropped_header_too_small;
1631 	u32 rx_dropped_tcp_length;
1632 	u32 rx_dropped_runt;
1633 	u32 rsvd1[10];
1634 	u32 rx_ip_checksum_errs;
1635 	u32 rx_tcp_checksum_errs;
1636 	u32 rx_udp_checksum_errs;
1637 	u32 rsvd2[7];
1638 	u32 rx_switched_unicast_packets;
1639 	u32 rx_switched_multicast_packets;
1640 	u32 rx_switched_broadcast_packets;
1641 	u32 rsvd3[3];
1642 	u32 tx_pauseframes;
1643 	u32 tx_priority_pauseframes;
1644 	u32 tx_controlframes;
1645 	u32 rsvd4[10];
1646 	u32 rxpp_fifo_overflow_drop;
1647 	u32 rx_input_fifo_overflow_drop;
1648 	u32 pmem_fifo_overflow_drop;
1649 	u32 jabber_events;
1650 	u32 rsvd5[3];
1651 };
1652 
1653 
1654 struct be_rxf_stats_v1 {
1655 	struct be_port_rxf_stats_v1 port[4];
1656 	u32 rsvd0[2];
1657 	u32 rx_drops_no_pbuf;
1658 	u32 rx_drops_no_txpb;
1659 	u32 rx_drops_no_erx_descr;
1660 	u32 rx_drops_no_tpre_descr;
1661 	u32 rsvd1[6];
1662 	u32 rx_drops_too_many_frags;
1663 	u32 rx_drops_invalid_ring;
1664 	u32 forwarded_packets;
1665 	u32 rx_drops_mtu;
1666 	u32 rsvd2[14];
1667 };
1668 
1669 struct be_erx_stats_v1 {
1670 	u32 rx_drops_no_fragments[68];     /* dwordS 0 to 67*/
1671 	u32 rsvd[4];
1672 };
1673 
1674 struct be_port_rxf_stats_v2 {
1675 	u32 rsvd0[10];
1676 	u32 roce_bytes_received_lsd;
1677 	u32 roce_bytes_received_msd;
1678 	u32 rsvd1[5];
1679 	u32 roce_frames_received;
1680 	u32 rx_crc_errors;
1681 	u32 rx_alignment_symbol_errors;
1682 	u32 rx_pause_frames;
1683 	u32 rx_priority_pause_frames;
1684 	u32 rx_control_frames;
1685 	u32 rx_in_range_errors;
1686 	u32 rx_out_range_errors;
1687 	u32 rx_frame_too_long;
1688 	u32 rx_address_filtered;
1689 	u32 rx_dropped_too_small;
1690 	u32 rx_dropped_too_short;
1691 	u32 rx_dropped_header_too_small;
1692 	u32 rx_dropped_tcp_length;
1693 	u32 rx_dropped_runt;
1694 	u32 rsvd2[10];
1695 	u32 rx_ip_checksum_errs;
1696 	u32 rx_tcp_checksum_errs;
1697 	u32 rx_udp_checksum_errs;
1698 	u32 rsvd3[7];
1699 	u32 rx_switched_unicast_packets;
1700 	u32 rx_switched_multicast_packets;
1701 	u32 rx_switched_broadcast_packets;
1702 	u32 rsvd4[3];
1703 	u32 tx_pauseframes;
1704 	u32 tx_priority_pauseframes;
1705 	u32 tx_controlframes;
1706 	u32 rsvd5[10];
1707 	u32 rxpp_fifo_overflow_drop;
1708 	u32 rx_input_fifo_overflow_drop;
1709 	u32 pmem_fifo_overflow_drop;
1710 	u32 jabber_events;
1711 	u32 rsvd6[3];
1712 	u32 rx_drops_payload_size;
1713 	u32 rx_drops_clipped_header;
1714 	u32 rx_drops_crc;
1715 	u32 roce_drops_payload_len;
1716 	u32 roce_drops_crc;
1717 	u32 rsvd7[19];
1718 };
1719 
1720 struct be_rxf_stats_v2 {
1721 	struct be_port_rxf_stats_v2 port[4];
1722 	u32 rsvd0[2];
1723 	u32 rx_drops_no_pbuf;
1724 	u32 rx_drops_no_txpb;
1725 	u32 rx_drops_no_erx_descr;
1726 	u32 rx_drops_no_tpre_descr;
1727 	u32 rsvd1[6];
1728 	u32 rx_drops_too_many_frags;
1729 	u32 rx_drops_invalid_ring;
1730 	u32 forwarded_packets;
1731 	u32 rx_drops_mtu;
1732 	u32 rsvd2[35];
1733 };
1734 
1735 struct be_hw_stats_v1 {
1736 	struct be_rxf_stats_v1 rxf;
1737 	u32 rsvd0[BE_TXP_SW_SZ];
1738 	struct be_erx_stats_v1 erx;
1739 	struct be_pmem_stats pmem;
1740 	u32 rsvd1[18];
1741 };
1742 
1743 struct be_cmd_req_get_stats_v1 {
1744 	struct be_cmd_req_hdr hdr;
1745 	u8 rsvd[sizeof(struct be_hw_stats_v1)];
1746 };
1747 
1748 struct be_cmd_resp_get_stats_v1 {
1749 	struct be_cmd_resp_hdr hdr;
1750 	struct be_hw_stats_v1 hw_stats;
1751 };
1752 
1753 struct be_erx_stats_v2 {
1754 	u32 rx_drops_no_fragments[136];     /* dwordS 0 to 135*/
1755 	u32 rsvd[3];
1756 };
1757 
1758 struct be_hw_stats_v2 {
1759 	struct be_rxf_stats_v2 rxf;
1760 	u32 rsvd0[BE_TXP_SW_SZ];
1761 	struct be_erx_stats_v2 erx;
1762 	struct be_pmem_stats pmem;
1763 	u32 rsvd1[18];
1764 };
1765 
1766 struct be_cmd_req_get_stats_v2 {
1767 	struct be_cmd_req_hdr hdr;
1768 	u8 rsvd[sizeof(struct be_hw_stats_v2)];
1769 };
1770 
1771 struct be_cmd_resp_get_stats_v2 {
1772 	struct be_cmd_resp_hdr hdr;
1773 	struct be_hw_stats_v2 hw_stats;
1774 };
1775 
1776 /************** get fat capabilites *******************/
1777 #define MAX_MODULES 27
1778 #define MAX_MODES 4
1779 #define MODE_UART 0
1780 #define FW_LOG_LEVEL_DEFAULT 48
1781 #define FW_LOG_LEVEL_FATAL 64
1782 
1783 struct ext_fat_mode {
1784 	u8 mode;
1785 	u8 rsvd0;
1786 	u16 port_mask;
1787 	u32 dbg_lvl;
1788 	u64 fun_mask;
1789 } __packed;
1790 
1791 struct ext_fat_modules {
1792 	u8 modules_str[32];
1793 	u32 modules_id;
1794 	u32 num_modes;
1795 	struct ext_fat_mode trace_lvl[MAX_MODES];
1796 } __packed;
1797 
1798 struct be_fat_conf_params {
1799 	u32 max_log_entries;
1800 	u32 log_entry_size;
1801 	u8 log_type;
1802 	u8 max_log_funs;
1803 	u8 max_log_ports;
1804 	u8 rsvd0;
1805 	u32 supp_modes;
1806 	u32 num_modules;
1807 	struct ext_fat_modules module[MAX_MODULES];
1808 } __packed;
1809 
1810 struct be_cmd_req_get_ext_fat_caps {
1811 	struct be_cmd_req_hdr hdr;
1812 	u32 parameter_type;
1813 };
1814 
1815 struct be_cmd_resp_get_ext_fat_caps {
1816 	struct be_cmd_resp_hdr hdr;
1817 	struct be_fat_conf_params get_params;
1818 };
1819 
1820 struct be_cmd_req_set_ext_fat_caps {
1821 	struct be_cmd_req_hdr hdr;
1822 	struct be_fat_conf_params set_params;
1823 };
1824 
1825 #define RESOURCE_DESC_SIZE_V0			72
1826 #define RESOURCE_DESC_SIZE_V1			88
1827 #define PCIE_RESOURCE_DESC_TYPE_V0		0x40
1828 #define NIC_RESOURCE_DESC_TYPE_V0		0x41
1829 #define PCIE_RESOURCE_DESC_TYPE_V1		0x50
1830 #define NIC_RESOURCE_DESC_TYPE_V1		0x51
1831 #define MAX_RESOURCE_DESC			264
1832 
1833 /* QOS unit number */
1834 #define QUN					4
1835 /* Immediate */
1836 #define IMM					6
1837 /* No save */
1838 #define NOSV					7
1839 
1840 struct be_res_desc_hdr {
1841 	u8 desc_type;
1842 	u8 desc_len;
1843 } __packed;
1844 
1845 struct be_pcie_res_desc {
1846 	struct be_res_desc_hdr hdr;
1847 	u8 rsvd0;
1848 	u8 flags;
1849 	u16 rsvd1;
1850 	u8 pf_num;
1851 	u8 rsvd2;
1852 	u32 rsvd3;
1853 	u8 sriov_state;
1854 	u8 pf_state;
1855 	u8 pf_type;
1856 	u8 rsvd4;
1857 	u16 num_vfs;
1858 	u16 rsvd5;
1859 	u32 rsvd6[17];
1860 } __packed;
1861 
1862 struct be_nic_res_desc {
1863 	struct be_res_desc_hdr hdr;
1864 	u8 rsvd1;
1865 	u8 flags;
1866 	u8 vf_num;
1867 	u8 rsvd2;
1868 	u8 pf_num;
1869 	u8 rsvd3;
1870 	u16 unicast_mac_count;
1871 	u8 rsvd4[6];
1872 	u16 mcc_count;
1873 	u16 vlan_count;
1874 	u16 mcast_mac_count;
1875 	u16 txq_count;
1876 	u16 rq_count;
1877 	u16 rssq_count;
1878 	u16 lro_count;
1879 	u16 cq_count;
1880 	u16 toe_conn_count;
1881 	u16 eq_count;
1882 	u32 rsvd5;
1883 	u32 cap_flags;
1884 	u8 link_param;
1885 	u8 rsvd6[3];
1886 	u32 bw_min;
1887 	u32 bw_max;
1888 	u8 acpi_params;
1889 	u8 wol_param;
1890 	u16 rsvd7;
1891 	u32 rsvd8[7];
1892 } __packed;
1893 
1894 struct be_cmd_req_get_func_config {
1895 	struct be_cmd_req_hdr hdr;
1896 };
1897 
1898 struct be_cmd_resp_get_func_config {
1899 	struct be_cmd_resp_hdr hdr;
1900 	u32 desc_count;
1901 	u8 func_param[MAX_RESOURCE_DESC * RESOURCE_DESC_SIZE_V1];
1902 };
1903 
1904 #define ACTIVE_PROFILE_TYPE			0x2
1905 struct be_cmd_req_get_profile_config {
1906 	struct be_cmd_req_hdr hdr;
1907 	u8 rsvd;
1908 	u8 type;
1909 	u16 rsvd1;
1910 };
1911 
1912 struct be_cmd_resp_get_profile_config {
1913 	struct be_cmd_resp_hdr hdr;
1914 	u32 desc_count;
1915 	u8 func_param[MAX_RESOURCE_DESC * RESOURCE_DESC_SIZE_V1];
1916 };
1917 
1918 struct be_cmd_req_set_profile_config {
1919 	struct be_cmd_req_hdr hdr;
1920 	u32 rsvd;
1921 	u32 desc_count;
1922 	struct be_nic_res_desc nic_desc;
1923 };
1924 
1925 struct be_cmd_resp_set_profile_config {
1926 	struct be_cmd_resp_hdr hdr;
1927 };
1928 
1929 struct be_cmd_req_get_active_profile {
1930 	struct be_cmd_req_hdr hdr;
1931 	u32 rsvd;
1932 } __packed;
1933 
1934 struct be_cmd_resp_get_active_profile {
1935 	struct be_cmd_resp_hdr hdr;
1936 	u16 active_profile_id;
1937 	u16 next_profile_id;
1938 } __packed;
1939 
1940 struct be_cmd_enable_disable_vf {
1941 	struct be_cmd_req_hdr hdr;
1942 	u8 enable;
1943 	u8 rsvd[3];
1944 };
1945 
1946 struct be_cmd_req_intr_set {
1947 	struct be_cmd_req_hdr hdr;
1948 	u8 intr_enabled;
1949 	u8 rsvd[3];
1950 };
1951 
1952 static inline bool check_privilege(struct be_adapter *adapter, u32 flags)
1953 {
1954 	return flags & adapter->cmd_privileges ? true : false;
1955 }
1956 
1957 /************** Get IFACE LIST *******************/
1958 struct be_if_desc {
1959 	u32 if_id;
1960 	u32 cap_flags;
1961 	u32 en_flags;
1962 };
1963 
1964 struct be_cmd_req_get_iface_list {
1965 	struct be_cmd_req_hdr hdr;
1966 };
1967 
1968 struct be_cmd_resp_get_iface_list {
1969 	struct be_cmd_req_hdr hdr;
1970 	u32 if_cnt;
1971 	struct be_if_desc if_desc;
1972 };
1973 
1974 int be_pci_fnum_get(struct be_adapter *adapter);
1975 int be_fw_wait_ready(struct be_adapter *adapter);
1976 int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
1977 			  bool permanent, u32 if_handle, u32 pmac_id);
1978 int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr, u32 if_id,
1979 		    u32 *pmac_id, u32 domain);
1980 int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, int pmac_id,
1981 		    u32 domain);
1982 int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
1983 		     u32 *if_handle, u32 domain);
1984 int be_cmd_if_destroy(struct be_adapter *adapter, int if_handle, u32 domain);
1985 int be_cmd_eq_create(struct be_adapter *adapter, struct be_eq_obj *eqo);
1986 int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq,
1987 		     struct be_queue_info *eq, bool no_delay,
1988 		     int num_cqe_dma_coalesce);
1989 int be_cmd_mccq_create(struct be_adapter *adapter, struct be_queue_info *mccq,
1990 		       struct be_queue_info *cq);
1991 int be_cmd_txq_create(struct be_adapter *adapter, struct be_tx_obj *txo);
1992 int be_cmd_rxq_create(struct be_adapter *adapter, struct be_queue_info *rxq,
1993 		      u16 cq_id, u16 frag_size, u32 if_id, u32 rss, u8 *rss_id);
1994 int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
1995 		     int type);
1996 int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q);
1997 int be_cmd_link_status_query(struct be_adapter *adapter, u16 *link_speed,
1998 			     u8 *link_status, u32 dom);
1999 int be_cmd_reset(struct be_adapter *adapter);
2000 int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd);
2001 int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
2002 			       struct be_dma_mem *nonemb_cmd);
2003 int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver,
2004 		      char *fw_on_flash);
2005 int be_cmd_modify_eqd(struct be_adapter *adapter, struct be_set_eqd *, int num);
2006 int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
2007 		       u32 num, bool promiscuous);
2008 int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 status);
2009 int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc);
2010 int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc);
2011 int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num,
2012 			u32 *function_mode, u32 *function_caps, u16 *asic_rev);
2013 int be_cmd_reset_function(struct be_adapter *adapter);
2014 int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable,
2015 		      u32 rss_hash_opts, u16 table_size);
2016 int be_process_mcc(struct be_adapter *adapter);
2017 int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num, u8 beacon,
2018 			    u8 status, u8 state);
2019 int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num,
2020 			    u32 *state);
2021 int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
2022 			  u32 flash_oper, u32 flash_opcode, u32 buf_size);
2023 int lancer_cmd_write_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
2024 			    u32 data_size, u32 data_offset,
2025 			    const char *obj_name, u32 *data_written,
2026 			    u8 *change_status, u8 *addn_status);
2027 int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
2028 			   u32 data_size, u32 data_offset, const char *obj_name,
2029 			   u32 *data_read, u32 *eof, u8 *addn_status);
2030 int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
2031 			 int offset);
2032 int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
2033 			    struct be_dma_mem *nonemb_cmd);
2034 int be_cmd_fw_init(struct be_adapter *adapter);
2035 int be_cmd_fw_clean(struct be_adapter *adapter);
2036 void be_async_mcc_enable(struct be_adapter *adapter);
2037 void be_async_mcc_disable(struct be_adapter *adapter);
2038 int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
2039 			 u32 loopback_type, u32 pkt_size, u32 num_pkts,
2040 			 u64 pattern);
2041 int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern, u32 byte_cnt,
2042 			struct be_dma_mem *cmd);
2043 int be_cmd_get_seeprom_data(struct be_adapter *adapter,
2044 			    struct be_dma_mem *nonemb_cmd);
2045 int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
2046 			u8 loopback_type, u8 enable);
2047 int be_cmd_get_phy_info(struct be_adapter *adapter);
2048 int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain);
2049 void be_detect_error(struct be_adapter *adapter);
2050 int be_cmd_get_die_temperature(struct be_adapter *adapter);
2051 int be_cmd_get_cntl_attributes(struct be_adapter *adapter);
2052 int be_cmd_req_native_mode(struct be_adapter *adapter);
2053 int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size);
2054 void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf);
2055 int be_cmd_get_fn_privileges(struct be_adapter *adapter, u32 *privilege,
2056 			     u32 domain);
2057 int be_cmd_set_fn_privileges(struct be_adapter *adapter, u32 privileges,
2058 			     u32 vf_num);
2059 int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac,
2060 			     bool *pmac_id_active, u32 *pmac_id,
2061 			     u32 if_handle, u8 domain);
2062 int be_cmd_get_active_mac(struct be_adapter *adapter, u32 pmac_id, u8 *mac,
2063 			  u32 if_handle, bool active, u32 domain);
2064 int be_cmd_get_perm_mac(struct be_adapter *adapter, u8 *mac);
2065 int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array, u8 mac_count,
2066 			u32 domain);
2067 int be_cmd_set_mac(struct be_adapter *adapter, u8 *mac, int if_id, u32 dom);
2068 int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid, u32 domain,
2069 			  u16 intf_id, u16 hsw_mode);
2070 int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid, u32 domain,
2071 			  u16 intf_id, u8 *mode);
2072 int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter);
2073 int be_cmd_set_fw_log_level(struct be_adapter *adapter, u32 level);
2074 int be_cmd_get_fw_log_level(struct be_adapter *adapter);
2075 int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter,
2076 				   struct be_dma_mem *cmd);
2077 int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter,
2078 				   struct be_dma_mem *cmd,
2079 				   struct be_fat_conf_params *cfgs);
2080 int lancer_physdev_ctrl(struct be_adapter *adapter, u32 mask);
2081 int lancer_initiate_dump(struct be_adapter *adapter);
2082 bool dump_present(struct be_adapter *adapter);
2083 int lancer_test_and_set_rdy_state(struct be_adapter *adapter);
2084 int be_cmd_query_port_name(struct be_adapter *adapter, u8 *port_name);
2085 int be_cmd_get_func_config(struct be_adapter *adapter,
2086 			   struct be_resources *res);
2087 int be_cmd_get_profile_config(struct be_adapter *adapter,
2088 			      struct be_resources *res, u8 domain);
2089 int be_cmd_set_profile_config(struct be_adapter *adapter, u32 bps, u8 domain);
2090 int be_cmd_get_active_profile(struct be_adapter *adapter, u16 *profile);
2091 int be_cmd_get_if_id(struct be_adapter *adapter, struct be_vf_cfg *vf_cfg,
2092 		     int vf_num);
2093 int be_cmd_enable_vf(struct be_adapter *adapter, u8 domain);
2094 int be_cmd_intr_set(struct be_adapter *adapter, bool intr_enable);
2095