1 /* 2 * Copyright (C) 2005 - 2015 Emulex 3 * All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License version 2 7 * as published by the Free Software Foundation. The full GNU General 8 * Public License is included in this distribution in the file called COPYING. 9 * 10 * Contact Information: 11 * linux-drivers@emulex.com 12 * 13 * Emulex 14 * 3333 Susan Street 15 * Costa Mesa, CA 92626 16 */ 17 18 /* 19 * The driver sends configuration and managements command requests to the 20 * firmware in the BE. These requests are communicated to the processor 21 * using Work Request Blocks (WRBs) submitted to the MCC-WRB ring or via one 22 * WRB inside a MAILBOX. 23 * The commands are serviced by the ARM processor in the BladeEngine's MPU. 24 */ 25 26 struct be_sge { 27 u32 pa_lo; 28 u32 pa_hi; 29 u32 len; 30 }; 31 32 #define MCC_WRB_EMBEDDED_MASK 1 /* bit 0 of dword 0*/ 33 #define MCC_WRB_SGE_CNT_SHIFT 3 /* bits 3 - 7 of dword 0 */ 34 #define MCC_WRB_SGE_CNT_MASK 0x1F /* bits 3 - 7 of dword 0 */ 35 struct be_mcc_wrb { 36 u32 embedded; /* dword 0 */ 37 u32 payload_length; /* dword 1 */ 38 u32 tag0; /* dword 2 */ 39 u32 tag1; /* dword 3 */ 40 u32 rsvd; /* dword 4 */ 41 union { 42 u8 embedded_payload[236]; /* used by embedded cmds */ 43 struct be_sge sgl[19]; /* used by non-embedded cmds */ 44 } payload; 45 }; 46 47 #define CQE_FLAGS_VALID_MASK BIT(31) 48 #define CQE_FLAGS_ASYNC_MASK BIT(30) 49 #define CQE_FLAGS_COMPLETED_MASK BIT(28) 50 #define CQE_FLAGS_CONSUMED_MASK BIT(27) 51 52 /* Completion Status */ 53 enum mcc_base_status { 54 MCC_STATUS_SUCCESS = 0, 55 MCC_STATUS_FAILED = 1, 56 MCC_STATUS_ILLEGAL_REQUEST = 2, 57 MCC_STATUS_ILLEGAL_FIELD = 3, 58 MCC_STATUS_INSUFFICIENT_BUFFER = 4, 59 MCC_STATUS_UNAUTHORIZED_REQUEST = 5, 60 MCC_STATUS_NOT_SUPPORTED = 66, 61 MCC_STATUS_FEATURE_NOT_SUPPORTED = 68 62 }; 63 64 /* Additional status */ 65 enum mcc_addl_status { 66 MCC_ADDL_STATUS_INSUFFICIENT_RESOURCES = 0x16, 67 MCC_ADDL_STATUS_FLASH_IMAGE_CRC_MISMATCH = 0x4d, 68 MCC_ADDL_STATUS_TOO_MANY_INTERFACES = 0x4a, 69 MCC_ADDL_STATUS_INSUFFICIENT_VLANS = 0xab, 70 MCC_ADDL_STATUS_INVALID_SIGNATURE = 0x56, 71 MCC_ADDL_STATUS_MISSING_SIGNATURE = 0x57, 72 MCC_ADDL_STATUS_INSUFFICIENT_PRIVILEGES = 0x60 73 }; 74 75 #define CQE_BASE_STATUS_MASK 0xFFFF 76 #define CQE_BASE_STATUS_SHIFT 0 /* bits 0 - 15 */ 77 #define CQE_ADDL_STATUS_MASK 0xFF 78 #define CQE_ADDL_STATUS_SHIFT 16 /* bits 16 - 31 */ 79 80 #define base_status(status) \ 81 ((enum mcc_base_status) \ 82 (status > 0 ? (status & CQE_BASE_STATUS_MASK) : 0)) 83 #define addl_status(status) \ 84 ((enum mcc_addl_status) \ 85 (status > 0 ? (status >> CQE_ADDL_STATUS_SHIFT) & \ 86 CQE_ADDL_STATUS_MASK : 0)) 87 88 struct be_mcc_compl { 89 u32 status; /* dword 0 */ 90 u32 tag0; /* dword 1 */ 91 u32 tag1; /* dword 2 */ 92 u32 flags; /* dword 3 */ 93 }; 94 95 /* When the async bit of mcc_compl flags is set, flags 96 * is interpreted as follows: 97 */ 98 #define ASYNC_EVENT_CODE_SHIFT 8 /* bits 8 - 15 */ 99 #define ASYNC_EVENT_CODE_MASK 0xFF 100 #define ASYNC_EVENT_TYPE_SHIFT 16 101 #define ASYNC_EVENT_TYPE_MASK 0xFF 102 #define ASYNC_EVENT_CODE_LINK_STATE 0x1 103 #define ASYNC_EVENT_CODE_GRP_5 0x5 104 #define ASYNC_EVENT_QOS_SPEED 0x1 105 #define ASYNC_EVENT_COS_PRIORITY 0x2 106 #define ASYNC_EVENT_PVID_STATE 0x3 107 #define ASYNC_EVENT_CODE_QNQ 0x6 108 #define ASYNC_DEBUG_EVENT_TYPE_QNQ 1 109 #define ASYNC_EVENT_CODE_SLIPORT 0x11 110 #define ASYNC_EVENT_PORT_MISCONFIG 0x9 111 #define ASYNC_EVENT_FW_CONTROL 0x5 112 113 enum { 114 LINK_DOWN = 0x0, 115 LINK_UP = 0x1 116 }; 117 #define LINK_STATUS_MASK 0x1 118 #define LOGICAL_LINK_STATUS_MASK 0x2 119 120 /* When the event code of compl->flags is link-state, the mcc_compl 121 * must be interpreted as follows 122 */ 123 struct be_async_event_link_state { 124 u8 physical_port; 125 u8 port_link_status; 126 u8 port_duplex; 127 u8 port_speed; 128 u8 port_fault; 129 u8 rsvd0[7]; 130 u32 flags; 131 } __packed; 132 133 /* When the event code of compl->flags is GRP-5 and event_type is QOS_SPEED 134 * the mcc_compl must be interpreted as follows 135 */ 136 struct be_async_event_grp5_qos_link_speed { 137 u8 physical_port; 138 u8 rsvd[5]; 139 u16 qos_link_speed; 140 u32 event_tag; 141 u32 flags; 142 } __packed; 143 144 /* When the event code of compl->flags is GRP5 and event type is 145 * CoS-Priority, the mcc_compl must be interpreted as follows 146 */ 147 struct be_async_event_grp5_cos_priority { 148 u8 physical_port; 149 u8 available_priority_bmap; 150 u8 reco_default_priority; 151 u8 valid; 152 u8 rsvd0; 153 u8 event_tag; 154 u32 flags; 155 } __packed; 156 157 /* When the event code of compl->flags is GRP5 and event type is 158 * PVID state, the mcc_compl must be interpreted as follows 159 */ 160 struct be_async_event_grp5_pvid_state { 161 u8 enabled; 162 u8 rsvd0; 163 u16 tag; 164 u32 event_tag; 165 u32 rsvd1; 166 u32 flags; 167 } __packed; 168 169 /* async event indicating outer VLAN tag in QnQ */ 170 struct be_async_event_qnq { 171 u8 valid; /* Indicates if outer VLAN is valid */ 172 u8 rsvd0; 173 u16 vlan_tag; 174 u32 event_tag; 175 u8 rsvd1[4]; 176 u32 flags; 177 } __packed; 178 179 enum { 180 BE_PHY_FUNCTIONAL = 0, 181 BE_PHY_NOT_PRESENT = 1, 182 BE_PHY_DIFF_MEDIA = 2, 183 BE_PHY_INCOMPATIBLE = 3, 184 BE_PHY_UNQUALIFIED = 4, 185 BE_PHY_UNCERTIFIED = 5 186 }; 187 188 #define PHY_STATE_MSG_SEVERITY 0x6 189 #define PHY_STATE_OPER 0x1 190 #define PHY_STATE_INFO_VALID 0x80 191 #define PHY_STATE_OPER_MSG_NONE 0x2 192 #define DEFAULT_MSG_SEVERITY 0x1 193 194 #define be_phy_state_unknown(phy_state) (phy_state > BE_PHY_UNCERTIFIED) 195 #define be_phy_unqualified(phy_state) \ 196 (phy_state == BE_PHY_UNQUALIFIED || \ 197 phy_state == BE_PHY_UNCERTIFIED) 198 #define be_phy_misconfigured(phy_state) \ 199 (phy_state == BE_PHY_INCOMPATIBLE || \ 200 phy_state == BE_PHY_UNQUALIFIED || \ 201 phy_state == BE_PHY_UNCERTIFIED) 202 203 extern char *be_misconfig_evt_port_state[]; 204 205 /* async event indicating misconfigured port */ 206 struct be_async_event_misconfig_port { 207 /* DATA_WORD1: 208 * phy state of port 0: bits 7 - 0 209 * phy state of port 1: bits 15 - 8 210 * phy state of port 2: bits 23 - 16 211 * phy state of port 3: bits 31 - 24 212 */ 213 u32 event_data_word1; 214 /* DATA_WORD2: 215 * phy state info of port 0: bits 7 - 0 216 * phy state info of port 1: bits 15 - 8 217 * phy state info of port 2: bits 23 - 16 218 * phy state info of port 3: bits 31 - 24 219 * 220 * PHY STATE INFO: 221 * Link operability :bit 0 222 * Message severity :bit 2 - 1 223 * Rsvd :bits 6 - 3 224 * phy state info valid :bit 7 225 */ 226 u32 event_data_word2; 227 u32 rsvd0; 228 u32 flags; 229 } __packed; 230 231 #define BMC_FILT_BROADCAST_ARP BIT(0) 232 #define BMC_FILT_BROADCAST_DHCP_CLIENT BIT(1) 233 #define BMC_FILT_BROADCAST_DHCP_SERVER BIT(2) 234 #define BMC_FILT_BROADCAST_NET_BIOS BIT(3) 235 #define BMC_FILT_BROADCAST BIT(7) 236 #define BMC_FILT_MULTICAST_IPV6_NEIGH_ADVER BIT(8) 237 #define BMC_FILT_MULTICAST_IPV6_RA BIT(9) 238 #define BMC_FILT_MULTICAST_IPV6_RAS BIT(10) 239 #define BMC_FILT_MULTICAST BIT(15) 240 struct be_async_fw_control { 241 u32 event_data_word1; 242 u32 event_data_word2; 243 u32 evt_tag; 244 u32 event_data_word4; 245 } __packed; 246 247 struct be_mcc_mailbox { 248 struct be_mcc_wrb wrb; 249 struct be_mcc_compl compl; 250 }; 251 252 #define CMD_SUBSYSTEM_COMMON 0x1 253 #define CMD_SUBSYSTEM_ETH 0x3 254 #define CMD_SUBSYSTEM_LOWLEVEL 0xb 255 256 #define OPCODE_COMMON_NTWK_MAC_QUERY 1 257 #define OPCODE_COMMON_NTWK_MAC_SET 2 258 #define OPCODE_COMMON_NTWK_MULTICAST_SET 3 259 #define OPCODE_COMMON_NTWK_VLAN_CONFIG 4 260 #define OPCODE_COMMON_NTWK_LINK_STATUS_QUERY 5 261 #define OPCODE_COMMON_READ_FLASHROM 6 262 #define OPCODE_COMMON_WRITE_FLASHROM 7 263 #define OPCODE_COMMON_CQ_CREATE 12 264 #define OPCODE_COMMON_EQ_CREATE 13 265 #define OPCODE_COMMON_MCC_CREATE 21 266 #define OPCODE_COMMON_SET_QOS 28 267 #define OPCODE_COMMON_MCC_CREATE_EXT 90 268 #define OPCODE_COMMON_SEEPROM_READ 30 269 #define OPCODE_COMMON_GET_CNTL_ATTRIBUTES 32 270 #define OPCODE_COMMON_NTWK_RX_FILTER 34 271 #define OPCODE_COMMON_GET_FW_VERSION 35 272 #define OPCODE_COMMON_SET_FLOW_CONTROL 36 273 #define OPCODE_COMMON_GET_FLOW_CONTROL 37 274 #define OPCODE_COMMON_SET_FRAME_SIZE 39 275 #define OPCODE_COMMON_MODIFY_EQ_DELAY 41 276 #define OPCODE_COMMON_FIRMWARE_CONFIG 42 277 #define OPCODE_COMMON_NTWK_INTERFACE_CREATE 50 278 #define OPCODE_COMMON_NTWK_INTERFACE_DESTROY 51 279 #define OPCODE_COMMON_MCC_DESTROY 53 280 #define OPCODE_COMMON_CQ_DESTROY 54 281 #define OPCODE_COMMON_EQ_DESTROY 55 282 #define OPCODE_COMMON_QUERY_FIRMWARE_CONFIG 58 283 #define OPCODE_COMMON_NTWK_PMAC_ADD 59 284 #define OPCODE_COMMON_NTWK_PMAC_DEL 60 285 #define OPCODE_COMMON_FUNCTION_RESET 61 286 #define OPCODE_COMMON_MANAGE_FAT 68 287 #define OPCODE_COMMON_ENABLE_DISABLE_BEACON 69 288 #define OPCODE_COMMON_GET_BEACON_STATE 70 289 #define OPCODE_COMMON_READ_TRANSRECV_DATA 73 290 #define OPCODE_COMMON_GET_PORT_NAME 77 291 #define OPCODE_COMMON_SET_LOGICAL_LINK_CONFIG 80 292 #define OPCODE_COMMON_SET_INTERRUPT_ENABLE 89 293 #define OPCODE_COMMON_SET_FN_PRIVILEGES 100 294 #define OPCODE_COMMON_GET_PHY_DETAILS 102 295 #define OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP 103 296 #define OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES 121 297 #define OPCODE_COMMON_GET_EXT_FAT_CAPABILITES 125 298 #define OPCODE_COMMON_SET_EXT_FAT_CAPABILITES 126 299 #define OPCODE_COMMON_GET_MAC_LIST 147 300 #define OPCODE_COMMON_SET_MAC_LIST 148 301 #define OPCODE_COMMON_GET_HSW_CONFIG 152 302 #define OPCODE_COMMON_GET_FUNC_CONFIG 160 303 #define OPCODE_COMMON_GET_PROFILE_CONFIG 164 304 #define OPCODE_COMMON_SET_PROFILE_CONFIG 165 305 #define OPCODE_COMMON_GET_ACTIVE_PROFILE 167 306 #define OPCODE_COMMON_SET_HSW_CONFIG 153 307 #define OPCODE_COMMON_GET_FN_PRIVILEGES 170 308 #define OPCODE_COMMON_READ_OBJECT 171 309 #define OPCODE_COMMON_WRITE_OBJECT 172 310 #define OPCODE_COMMON_DELETE_OBJECT 174 311 #define OPCODE_COMMON_MANAGE_IFACE_FILTERS 193 312 #define OPCODE_COMMON_GET_IFACE_LIST 194 313 #define OPCODE_COMMON_ENABLE_DISABLE_VF 196 314 315 #define OPCODE_ETH_RSS_CONFIG 1 316 #define OPCODE_ETH_ACPI_CONFIG 2 317 #define OPCODE_ETH_PROMISCUOUS 3 318 #define OPCODE_ETH_GET_STATISTICS 4 319 #define OPCODE_ETH_TX_CREATE 7 320 #define OPCODE_ETH_RX_CREATE 8 321 #define OPCODE_ETH_TX_DESTROY 9 322 #define OPCODE_ETH_RX_DESTROY 10 323 #define OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG 12 324 #define OPCODE_ETH_GET_PPORT_STATS 18 325 326 #define OPCODE_LOWLEVEL_HOST_DDR_DMA 17 327 #define OPCODE_LOWLEVEL_LOOPBACK_TEST 18 328 #define OPCODE_LOWLEVEL_SET_LOOPBACK_MODE 19 329 330 struct be_cmd_req_hdr { 331 u8 opcode; /* dword 0 */ 332 u8 subsystem; /* dword 0 */ 333 u8 port_number; /* dword 0 */ 334 u8 domain; /* dword 0 */ 335 u32 timeout; /* dword 1 */ 336 u32 request_length; /* dword 2 */ 337 u8 version; /* dword 3 */ 338 u8 rsvd[3]; /* dword 3 */ 339 }; 340 341 #define RESP_HDR_INFO_OPCODE_SHIFT 0 /* bits 0 - 7 */ 342 #define RESP_HDR_INFO_SUBSYS_SHIFT 8 /* bits 8 - 15 */ 343 struct be_cmd_resp_hdr { 344 u8 opcode; /* dword 0 */ 345 u8 subsystem; /* dword 0 */ 346 u8 rsvd[2]; /* dword 0 */ 347 u8 base_status; /* dword 1 */ 348 u8 addl_status; /* dword 1 */ 349 u8 rsvd1[2]; /* dword 1 */ 350 u32 response_length; /* dword 2 */ 351 u32 actual_resp_len; /* dword 3 */ 352 }; 353 354 struct phys_addr { 355 u32 lo; 356 u32 hi; 357 }; 358 359 /************************** 360 * BE Command definitions * 361 **************************/ 362 363 /* Pseudo amap definition in which each bit of the actual structure is defined 364 * as a byte: used to calculate offset/shift/mask of each field */ 365 struct amap_eq_context { 366 u8 cidx[13]; /* dword 0*/ 367 u8 rsvd0[3]; /* dword 0*/ 368 u8 epidx[13]; /* dword 0*/ 369 u8 valid; /* dword 0*/ 370 u8 rsvd1; /* dword 0*/ 371 u8 size; /* dword 0*/ 372 u8 pidx[13]; /* dword 1*/ 373 u8 rsvd2[3]; /* dword 1*/ 374 u8 pd[10]; /* dword 1*/ 375 u8 count[3]; /* dword 1*/ 376 u8 solevent; /* dword 1*/ 377 u8 stalled; /* dword 1*/ 378 u8 armed; /* dword 1*/ 379 u8 rsvd3[4]; /* dword 2*/ 380 u8 func[8]; /* dword 2*/ 381 u8 rsvd4; /* dword 2*/ 382 u8 delaymult[10]; /* dword 2*/ 383 u8 rsvd5[2]; /* dword 2*/ 384 u8 phase[2]; /* dword 2*/ 385 u8 nodelay; /* dword 2*/ 386 u8 rsvd6[4]; /* dword 2*/ 387 u8 rsvd7[32]; /* dword 3*/ 388 } __packed; 389 390 struct be_cmd_req_eq_create { 391 struct be_cmd_req_hdr hdr; 392 u16 num_pages; /* sword */ 393 u16 rsvd0; /* sword */ 394 u8 context[sizeof(struct amap_eq_context) / 8]; 395 struct phys_addr pages[8]; 396 } __packed; 397 398 struct be_cmd_resp_eq_create { 399 struct be_cmd_resp_hdr resp_hdr; 400 u16 eq_id; /* sword */ 401 u16 msix_idx; /* available only in v2 */ 402 } __packed; 403 404 /******************** Mac query ***************************/ 405 enum { 406 MAC_ADDRESS_TYPE_STORAGE = 0x0, 407 MAC_ADDRESS_TYPE_NETWORK = 0x1, 408 MAC_ADDRESS_TYPE_PD = 0x2, 409 MAC_ADDRESS_TYPE_MANAGEMENT = 0x3 410 }; 411 412 struct mac_addr { 413 u16 size_of_struct; 414 u8 addr[ETH_ALEN]; 415 } __packed; 416 417 struct be_cmd_req_mac_query { 418 struct be_cmd_req_hdr hdr; 419 u8 type; 420 u8 permanent; 421 u16 if_id; 422 u32 pmac_id; 423 } __packed; 424 425 struct be_cmd_resp_mac_query { 426 struct be_cmd_resp_hdr hdr; 427 struct mac_addr mac; 428 }; 429 430 /******************** PMac Add ***************************/ 431 struct be_cmd_req_pmac_add { 432 struct be_cmd_req_hdr hdr; 433 u32 if_id; 434 u8 mac_address[ETH_ALEN]; 435 u8 rsvd0[2]; 436 } __packed; 437 438 struct be_cmd_resp_pmac_add { 439 struct be_cmd_resp_hdr hdr; 440 u32 pmac_id; 441 }; 442 443 /******************** PMac Del ***************************/ 444 struct be_cmd_req_pmac_del { 445 struct be_cmd_req_hdr hdr; 446 u32 if_id; 447 u32 pmac_id; 448 }; 449 450 /******************** Create CQ ***************************/ 451 /* Pseudo amap definition in which each bit of the actual structure is defined 452 * as a byte: used to calculate offset/shift/mask of each field */ 453 struct amap_cq_context_be { 454 u8 cidx[11]; /* dword 0*/ 455 u8 rsvd0; /* dword 0*/ 456 u8 coalescwm[2]; /* dword 0*/ 457 u8 nodelay; /* dword 0*/ 458 u8 epidx[11]; /* dword 0*/ 459 u8 rsvd1; /* dword 0*/ 460 u8 count[2]; /* dword 0*/ 461 u8 valid; /* dword 0*/ 462 u8 solevent; /* dword 0*/ 463 u8 eventable; /* dword 0*/ 464 u8 pidx[11]; /* dword 1*/ 465 u8 rsvd2; /* dword 1*/ 466 u8 pd[10]; /* dword 1*/ 467 u8 eqid[8]; /* dword 1*/ 468 u8 stalled; /* dword 1*/ 469 u8 armed; /* dword 1*/ 470 u8 rsvd3[4]; /* dword 2*/ 471 u8 func[8]; /* dword 2*/ 472 u8 rsvd4[20]; /* dword 2*/ 473 u8 rsvd5[32]; /* dword 3*/ 474 } __packed; 475 476 struct amap_cq_context_v2 { 477 u8 rsvd0[12]; /* dword 0*/ 478 u8 coalescwm[2]; /* dword 0*/ 479 u8 nodelay; /* dword 0*/ 480 u8 rsvd1[12]; /* dword 0*/ 481 u8 count[2]; /* dword 0*/ 482 u8 valid; /* dword 0*/ 483 u8 rsvd2; /* dword 0*/ 484 u8 eventable; /* dword 0*/ 485 u8 eqid[16]; /* dword 1*/ 486 u8 rsvd3[15]; /* dword 1*/ 487 u8 armed; /* dword 1*/ 488 u8 rsvd4[32]; /* dword 2*/ 489 u8 rsvd5[32]; /* dword 3*/ 490 } __packed; 491 492 struct be_cmd_req_cq_create { 493 struct be_cmd_req_hdr hdr; 494 u16 num_pages; 495 u8 page_size; 496 u8 rsvd0; 497 u8 context[sizeof(struct amap_cq_context_be) / 8]; 498 struct phys_addr pages[8]; 499 } __packed; 500 501 502 struct be_cmd_resp_cq_create { 503 struct be_cmd_resp_hdr hdr; 504 u16 cq_id; 505 u16 rsvd0; 506 } __packed; 507 508 struct be_cmd_req_get_fat { 509 struct be_cmd_req_hdr hdr; 510 u32 fat_operation; 511 u32 read_log_offset; 512 u32 read_log_length; 513 u32 data_buffer_size; 514 u32 data_buffer[1]; 515 } __packed; 516 517 struct be_cmd_resp_get_fat { 518 struct be_cmd_resp_hdr hdr; 519 u32 log_size; 520 u32 read_log_length; 521 u32 rsvd[2]; 522 u32 data_buffer[1]; 523 } __packed; 524 525 526 /******************** Create MCCQ ***************************/ 527 /* Pseudo amap definition in which each bit of the actual structure is defined 528 * as a byte: used to calculate offset/shift/mask of each field */ 529 struct amap_mcc_context_be { 530 u8 con_index[14]; 531 u8 rsvd0[2]; 532 u8 ring_size[4]; 533 u8 fetch_wrb; 534 u8 fetch_r2t; 535 u8 cq_id[10]; 536 u8 prod_index[14]; 537 u8 fid[8]; 538 u8 pdid[9]; 539 u8 valid; 540 u8 rsvd1[32]; 541 u8 rsvd2[32]; 542 } __packed; 543 544 struct amap_mcc_context_v1 { 545 u8 async_cq_id[16]; 546 u8 ring_size[4]; 547 u8 rsvd0[12]; 548 u8 rsvd1[31]; 549 u8 valid; 550 u8 async_cq_valid[1]; 551 u8 rsvd2[31]; 552 u8 rsvd3[32]; 553 } __packed; 554 555 struct be_cmd_req_mcc_create { 556 struct be_cmd_req_hdr hdr; 557 u16 num_pages; 558 u16 cq_id; 559 u8 context[sizeof(struct amap_mcc_context_be) / 8]; 560 struct phys_addr pages[8]; 561 } __packed; 562 563 struct be_cmd_req_mcc_ext_create { 564 struct be_cmd_req_hdr hdr; 565 u16 num_pages; 566 u16 cq_id; 567 u32 async_event_bitmap[1]; 568 u8 context[sizeof(struct amap_mcc_context_v1) / 8]; 569 struct phys_addr pages[8]; 570 } __packed; 571 572 struct be_cmd_resp_mcc_create { 573 struct be_cmd_resp_hdr hdr; 574 u16 id; 575 u16 rsvd0; 576 } __packed; 577 578 /******************** Create TxQ ***************************/ 579 #define BE_ETH_TX_RING_TYPE_STANDARD 2 580 #define BE_ULP1_NUM 1 581 582 struct be_cmd_req_eth_tx_create { 583 struct be_cmd_req_hdr hdr; 584 u8 num_pages; 585 u8 ulp_num; 586 u16 type; 587 u16 if_id; 588 u8 queue_size; 589 u8 rsvd0; 590 u32 rsvd1; 591 u16 cq_id; 592 u16 rsvd2; 593 u32 rsvd3[13]; 594 struct phys_addr pages[8]; 595 } __packed; 596 597 struct be_cmd_resp_eth_tx_create { 598 struct be_cmd_resp_hdr hdr; 599 u16 cid; 600 u16 rid; 601 u32 db_offset; 602 u32 rsvd0[4]; 603 } __packed; 604 605 /******************** Create RxQ ***************************/ 606 struct be_cmd_req_eth_rx_create { 607 struct be_cmd_req_hdr hdr; 608 u16 cq_id; 609 u8 frag_size; 610 u8 num_pages; 611 struct phys_addr pages[2]; 612 u32 interface_id; 613 u16 max_frame_size; 614 u16 rsvd0; 615 u32 rss_queue; 616 } __packed; 617 618 struct be_cmd_resp_eth_rx_create { 619 struct be_cmd_resp_hdr hdr; 620 u16 id; 621 u8 rss_id; 622 u8 rsvd0; 623 } __packed; 624 625 /******************** Q Destroy ***************************/ 626 /* Type of Queue to be destroyed */ 627 enum { 628 QTYPE_EQ = 1, 629 QTYPE_CQ, 630 QTYPE_TXQ, 631 QTYPE_RXQ, 632 QTYPE_MCCQ 633 }; 634 635 struct be_cmd_req_q_destroy { 636 struct be_cmd_req_hdr hdr; 637 u16 id; 638 u16 bypass_flush; /* valid only for rx q destroy */ 639 } __packed; 640 641 /************ I/f Create (it's actually I/f Config Create)**********/ 642 643 /* Capability flags for the i/f */ 644 enum be_if_flags { 645 BE_IF_FLAGS_RSS = 0x4, 646 BE_IF_FLAGS_PROMISCUOUS = 0x8, 647 BE_IF_FLAGS_BROADCAST = 0x10, 648 BE_IF_FLAGS_UNTAGGED = 0x20, 649 BE_IF_FLAGS_ULP = 0x40, 650 BE_IF_FLAGS_VLAN_PROMISCUOUS = 0x80, 651 BE_IF_FLAGS_VLAN = 0x100, 652 BE_IF_FLAGS_MCAST_PROMISCUOUS = 0x200, 653 BE_IF_FLAGS_PASS_L2_ERRORS = 0x400, 654 BE_IF_FLAGS_PASS_L3L4_ERRORS = 0x800, 655 BE_IF_FLAGS_MULTICAST = 0x1000, 656 BE_IF_FLAGS_DEFQ_RSS = 0x1000000 657 }; 658 659 #define BE_IF_CAP_FLAGS_WANT (BE_IF_FLAGS_RSS | BE_IF_FLAGS_PROMISCUOUS |\ 660 BE_IF_FLAGS_BROADCAST | BE_IF_FLAGS_VLAN_PROMISCUOUS |\ 661 BE_IF_FLAGS_VLAN | BE_IF_FLAGS_MCAST_PROMISCUOUS |\ 662 BE_IF_FLAGS_PASS_L3L4_ERRORS | BE_IF_FLAGS_MULTICAST |\ 663 BE_IF_FLAGS_UNTAGGED | BE_IF_FLAGS_DEFQ_RSS) 664 665 #define BE_IF_FLAGS_ALL_PROMISCUOUS (BE_IF_FLAGS_PROMISCUOUS | \ 666 BE_IF_FLAGS_VLAN_PROMISCUOUS |\ 667 BE_IF_FLAGS_MCAST_PROMISCUOUS) 668 669 #define BE_IF_FILT_FLAGS_BASIC (BE_IF_FLAGS_BROADCAST | \ 670 BE_IF_FLAGS_PASS_L3L4_ERRORS | \ 671 BE_IF_FLAGS_UNTAGGED) 672 673 #define BE_IF_ALL_FILT_FLAGS (BE_IF_FILT_FLAGS_BASIC | \ 674 BE_IF_FLAGS_MULTICAST | \ 675 BE_IF_FLAGS_ALL_PROMISCUOUS) 676 677 /* An RX interface is an object with one or more MAC addresses and 678 * filtering capabilities. */ 679 struct be_cmd_req_if_create { 680 struct be_cmd_req_hdr hdr; 681 u32 version; /* ignore currently */ 682 u32 capability_flags; 683 u32 enable_flags; 684 u8 mac_addr[ETH_ALEN]; 685 u8 rsvd0; 686 u8 pmac_invalid; /* if set, don't attach the mac addr to the i/f */ 687 u32 vlan_tag; /* not used currently */ 688 } __packed; 689 690 struct be_cmd_resp_if_create { 691 struct be_cmd_resp_hdr hdr; 692 u32 interface_id; 693 u32 pmac_id; 694 }; 695 696 /****** I/f Destroy(it's actually I/f Config Destroy )**********/ 697 struct be_cmd_req_if_destroy { 698 struct be_cmd_req_hdr hdr; 699 u32 interface_id; 700 }; 701 702 /*************** HW Stats Get **********************************/ 703 struct be_port_rxf_stats_v0 { 704 u32 rx_bytes_lsd; /* dword 0*/ 705 u32 rx_bytes_msd; /* dword 1*/ 706 u32 rx_total_frames; /* dword 2*/ 707 u32 rx_unicast_frames; /* dword 3*/ 708 u32 rx_multicast_frames; /* dword 4*/ 709 u32 rx_broadcast_frames; /* dword 5*/ 710 u32 rx_crc_errors; /* dword 6*/ 711 u32 rx_alignment_symbol_errors; /* dword 7*/ 712 u32 rx_pause_frames; /* dword 8*/ 713 u32 rx_control_frames; /* dword 9*/ 714 u32 rx_in_range_errors; /* dword 10*/ 715 u32 rx_out_range_errors; /* dword 11*/ 716 u32 rx_frame_too_long; /* dword 12*/ 717 u32 rx_address_filtered; /* dword 13*/ 718 u32 rx_vlan_filtered; /* dword 14*/ 719 u32 rx_dropped_too_small; /* dword 15*/ 720 u32 rx_dropped_too_short; /* dword 16*/ 721 u32 rx_dropped_header_too_small; /* dword 17*/ 722 u32 rx_dropped_tcp_length; /* dword 18*/ 723 u32 rx_dropped_runt; /* dword 19*/ 724 u32 rx_64_byte_packets; /* dword 20*/ 725 u32 rx_65_127_byte_packets; /* dword 21*/ 726 u32 rx_128_256_byte_packets; /* dword 22*/ 727 u32 rx_256_511_byte_packets; /* dword 23*/ 728 u32 rx_512_1023_byte_packets; /* dword 24*/ 729 u32 rx_1024_1518_byte_packets; /* dword 25*/ 730 u32 rx_1519_2047_byte_packets; /* dword 26*/ 731 u32 rx_2048_4095_byte_packets; /* dword 27*/ 732 u32 rx_4096_8191_byte_packets; /* dword 28*/ 733 u32 rx_8192_9216_byte_packets; /* dword 29*/ 734 u32 rx_ip_checksum_errs; /* dword 30*/ 735 u32 rx_tcp_checksum_errs; /* dword 31*/ 736 u32 rx_udp_checksum_errs; /* dword 32*/ 737 u32 rx_non_rss_packets; /* dword 33*/ 738 u32 rx_ipv4_packets; /* dword 34*/ 739 u32 rx_ipv6_packets; /* dword 35*/ 740 u32 rx_ipv4_bytes_lsd; /* dword 36*/ 741 u32 rx_ipv4_bytes_msd; /* dword 37*/ 742 u32 rx_ipv6_bytes_lsd; /* dword 38*/ 743 u32 rx_ipv6_bytes_msd; /* dword 39*/ 744 u32 rx_chute1_packets; /* dword 40*/ 745 u32 rx_chute2_packets; /* dword 41*/ 746 u32 rx_chute3_packets; /* dword 42*/ 747 u32 rx_management_packets; /* dword 43*/ 748 u32 rx_switched_unicast_packets; /* dword 44*/ 749 u32 rx_switched_multicast_packets; /* dword 45*/ 750 u32 rx_switched_broadcast_packets; /* dword 46*/ 751 u32 tx_bytes_lsd; /* dword 47*/ 752 u32 tx_bytes_msd; /* dword 48*/ 753 u32 tx_unicastframes; /* dword 49*/ 754 u32 tx_multicastframes; /* dword 50*/ 755 u32 tx_broadcastframes; /* dword 51*/ 756 u32 tx_pauseframes; /* dword 52*/ 757 u32 tx_controlframes; /* dword 53*/ 758 u32 tx_64_byte_packets; /* dword 54*/ 759 u32 tx_65_127_byte_packets; /* dword 55*/ 760 u32 tx_128_256_byte_packets; /* dword 56*/ 761 u32 tx_256_511_byte_packets; /* dword 57*/ 762 u32 tx_512_1023_byte_packets; /* dword 58*/ 763 u32 tx_1024_1518_byte_packets; /* dword 59*/ 764 u32 tx_1519_2047_byte_packets; /* dword 60*/ 765 u32 tx_2048_4095_byte_packets; /* dword 61*/ 766 u32 tx_4096_8191_byte_packets; /* dword 62*/ 767 u32 tx_8192_9216_byte_packets; /* dword 63*/ 768 u32 rx_fifo_overflow; /* dword 64*/ 769 u32 rx_input_fifo_overflow; /* dword 65*/ 770 }; 771 772 struct be_rxf_stats_v0 { 773 struct be_port_rxf_stats_v0 port[2]; 774 u32 rx_drops_no_pbuf; /* dword 132*/ 775 u32 rx_drops_no_txpb; /* dword 133*/ 776 u32 rx_drops_no_erx_descr; /* dword 134*/ 777 u32 rx_drops_no_tpre_descr; /* dword 135*/ 778 u32 management_rx_port_packets; /* dword 136*/ 779 u32 management_rx_port_bytes; /* dword 137*/ 780 u32 management_rx_port_pause_frames; /* dword 138*/ 781 u32 management_rx_port_errors; /* dword 139*/ 782 u32 management_tx_port_packets; /* dword 140*/ 783 u32 management_tx_port_bytes; /* dword 141*/ 784 u32 management_tx_port_pause; /* dword 142*/ 785 u32 management_rx_port_rxfifo_overflow; /* dword 143*/ 786 u32 rx_drops_too_many_frags; /* dword 144*/ 787 u32 rx_drops_invalid_ring; /* dword 145*/ 788 u32 forwarded_packets; /* dword 146*/ 789 u32 rx_drops_mtu; /* dword 147*/ 790 u32 rsvd0[7]; 791 u32 port0_jabber_events; 792 u32 port1_jabber_events; 793 u32 rsvd1[6]; 794 }; 795 796 struct be_erx_stats_v0 { 797 u32 rx_drops_no_fragments[44]; /* dwordS 0 to 43*/ 798 u32 rsvd[4]; 799 }; 800 801 struct be_pmem_stats { 802 u32 eth_red_drops; 803 u32 rsvd[5]; 804 }; 805 806 struct be_hw_stats_v0 { 807 struct be_rxf_stats_v0 rxf; 808 u32 rsvd[48]; 809 struct be_erx_stats_v0 erx; 810 struct be_pmem_stats pmem; 811 }; 812 813 struct be_cmd_req_get_stats_v0 { 814 struct be_cmd_req_hdr hdr; 815 u8 rsvd[sizeof(struct be_hw_stats_v0)]; 816 }; 817 818 struct be_cmd_resp_get_stats_v0 { 819 struct be_cmd_resp_hdr hdr; 820 struct be_hw_stats_v0 hw_stats; 821 }; 822 823 struct lancer_pport_stats { 824 u32 tx_packets_lo; 825 u32 tx_packets_hi; 826 u32 tx_unicast_packets_lo; 827 u32 tx_unicast_packets_hi; 828 u32 tx_multicast_packets_lo; 829 u32 tx_multicast_packets_hi; 830 u32 tx_broadcast_packets_lo; 831 u32 tx_broadcast_packets_hi; 832 u32 tx_bytes_lo; 833 u32 tx_bytes_hi; 834 u32 tx_unicast_bytes_lo; 835 u32 tx_unicast_bytes_hi; 836 u32 tx_multicast_bytes_lo; 837 u32 tx_multicast_bytes_hi; 838 u32 tx_broadcast_bytes_lo; 839 u32 tx_broadcast_bytes_hi; 840 u32 tx_discards_lo; 841 u32 tx_discards_hi; 842 u32 tx_errors_lo; 843 u32 tx_errors_hi; 844 u32 tx_pause_frames_lo; 845 u32 tx_pause_frames_hi; 846 u32 tx_pause_on_frames_lo; 847 u32 tx_pause_on_frames_hi; 848 u32 tx_pause_off_frames_lo; 849 u32 tx_pause_off_frames_hi; 850 u32 tx_internal_mac_errors_lo; 851 u32 tx_internal_mac_errors_hi; 852 u32 tx_control_frames_lo; 853 u32 tx_control_frames_hi; 854 u32 tx_packets_64_bytes_lo; 855 u32 tx_packets_64_bytes_hi; 856 u32 tx_packets_65_to_127_bytes_lo; 857 u32 tx_packets_65_to_127_bytes_hi; 858 u32 tx_packets_128_to_255_bytes_lo; 859 u32 tx_packets_128_to_255_bytes_hi; 860 u32 tx_packets_256_to_511_bytes_lo; 861 u32 tx_packets_256_to_511_bytes_hi; 862 u32 tx_packets_512_to_1023_bytes_lo; 863 u32 tx_packets_512_to_1023_bytes_hi; 864 u32 tx_packets_1024_to_1518_bytes_lo; 865 u32 tx_packets_1024_to_1518_bytes_hi; 866 u32 tx_packets_1519_to_2047_bytes_lo; 867 u32 tx_packets_1519_to_2047_bytes_hi; 868 u32 tx_packets_2048_to_4095_bytes_lo; 869 u32 tx_packets_2048_to_4095_bytes_hi; 870 u32 tx_packets_4096_to_8191_bytes_lo; 871 u32 tx_packets_4096_to_8191_bytes_hi; 872 u32 tx_packets_8192_to_9216_bytes_lo; 873 u32 tx_packets_8192_to_9216_bytes_hi; 874 u32 tx_lso_packets_lo; 875 u32 tx_lso_packets_hi; 876 u32 rx_packets_lo; 877 u32 rx_packets_hi; 878 u32 rx_unicast_packets_lo; 879 u32 rx_unicast_packets_hi; 880 u32 rx_multicast_packets_lo; 881 u32 rx_multicast_packets_hi; 882 u32 rx_broadcast_packets_lo; 883 u32 rx_broadcast_packets_hi; 884 u32 rx_bytes_lo; 885 u32 rx_bytes_hi; 886 u32 rx_unicast_bytes_lo; 887 u32 rx_unicast_bytes_hi; 888 u32 rx_multicast_bytes_lo; 889 u32 rx_multicast_bytes_hi; 890 u32 rx_broadcast_bytes_lo; 891 u32 rx_broadcast_bytes_hi; 892 u32 rx_unknown_protos; 893 u32 rsvd_69; /* Word 69 is reserved */ 894 u32 rx_discards_lo; 895 u32 rx_discards_hi; 896 u32 rx_errors_lo; 897 u32 rx_errors_hi; 898 u32 rx_crc_errors_lo; 899 u32 rx_crc_errors_hi; 900 u32 rx_alignment_errors_lo; 901 u32 rx_alignment_errors_hi; 902 u32 rx_symbol_errors_lo; 903 u32 rx_symbol_errors_hi; 904 u32 rx_pause_frames_lo; 905 u32 rx_pause_frames_hi; 906 u32 rx_pause_on_frames_lo; 907 u32 rx_pause_on_frames_hi; 908 u32 rx_pause_off_frames_lo; 909 u32 rx_pause_off_frames_hi; 910 u32 rx_frames_too_long_lo; 911 u32 rx_frames_too_long_hi; 912 u32 rx_internal_mac_errors_lo; 913 u32 rx_internal_mac_errors_hi; 914 u32 rx_undersize_packets; 915 u32 rx_oversize_packets; 916 u32 rx_fragment_packets; 917 u32 rx_jabbers; 918 u32 rx_control_frames_lo; 919 u32 rx_control_frames_hi; 920 u32 rx_control_frames_unknown_opcode_lo; 921 u32 rx_control_frames_unknown_opcode_hi; 922 u32 rx_in_range_errors; 923 u32 rx_out_of_range_errors; 924 u32 rx_address_filtered; 925 u32 rx_vlan_filtered; 926 u32 rx_dropped_too_small; 927 u32 rx_dropped_too_short; 928 u32 rx_dropped_header_too_small; 929 u32 rx_dropped_invalid_tcp_length; 930 u32 rx_dropped_runt; 931 u32 rx_ip_checksum_errors; 932 u32 rx_tcp_checksum_errors; 933 u32 rx_udp_checksum_errors; 934 u32 rx_non_rss_packets; 935 u32 rsvd_111; 936 u32 rx_ipv4_packets_lo; 937 u32 rx_ipv4_packets_hi; 938 u32 rx_ipv6_packets_lo; 939 u32 rx_ipv6_packets_hi; 940 u32 rx_ipv4_bytes_lo; 941 u32 rx_ipv4_bytes_hi; 942 u32 rx_ipv6_bytes_lo; 943 u32 rx_ipv6_bytes_hi; 944 u32 rx_nic_packets_lo; 945 u32 rx_nic_packets_hi; 946 u32 rx_tcp_packets_lo; 947 u32 rx_tcp_packets_hi; 948 u32 rx_iscsi_packets_lo; 949 u32 rx_iscsi_packets_hi; 950 u32 rx_management_packets_lo; 951 u32 rx_management_packets_hi; 952 u32 rx_switched_unicast_packets_lo; 953 u32 rx_switched_unicast_packets_hi; 954 u32 rx_switched_multicast_packets_lo; 955 u32 rx_switched_multicast_packets_hi; 956 u32 rx_switched_broadcast_packets_lo; 957 u32 rx_switched_broadcast_packets_hi; 958 u32 num_forwards_lo; 959 u32 num_forwards_hi; 960 u32 rx_fifo_overflow; 961 u32 rx_input_fifo_overflow; 962 u32 rx_drops_too_many_frags_lo; 963 u32 rx_drops_too_many_frags_hi; 964 u32 rx_drops_invalid_queue; 965 u32 rsvd_141; 966 u32 rx_drops_mtu_lo; 967 u32 rx_drops_mtu_hi; 968 u32 rx_packets_64_bytes_lo; 969 u32 rx_packets_64_bytes_hi; 970 u32 rx_packets_65_to_127_bytes_lo; 971 u32 rx_packets_65_to_127_bytes_hi; 972 u32 rx_packets_128_to_255_bytes_lo; 973 u32 rx_packets_128_to_255_bytes_hi; 974 u32 rx_packets_256_to_511_bytes_lo; 975 u32 rx_packets_256_to_511_bytes_hi; 976 u32 rx_packets_512_to_1023_bytes_lo; 977 u32 rx_packets_512_to_1023_bytes_hi; 978 u32 rx_packets_1024_to_1518_bytes_lo; 979 u32 rx_packets_1024_to_1518_bytes_hi; 980 u32 rx_packets_1519_to_2047_bytes_lo; 981 u32 rx_packets_1519_to_2047_bytes_hi; 982 u32 rx_packets_2048_to_4095_bytes_lo; 983 u32 rx_packets_2048_to_4095_bytes_hi; 984 u32 rx_packets_4096_to_8191_bytes_lo; 985 u32 rx_packets_4096_to_8191_bytes_hi; 986 u32 rx_packets_8192_to_9216_bytes_lo; 987 u32 rx_packets_8192_to_9216_bytes_hi; 988 }; 989 990 struct pport_stats_params { 991 u16 pport_num; 992 u8 rsvd; 993 u8 reset_stats; 994 }; 995 996 struct lancer_cmd_req_pport_stats { 997 struct be_cmd_req_hdr hdr; 998 union { 999 struct pport_stats_params params; 1000 u8 rsvd[sizeof(struct lancer_pport_stats)]; 1001 } cmd_params; 1002 }; 1003 1004 struct lancer_cmd_resp_pport_stats { 1005 struct be_cmd_resp_hdr hdr; 1006 struct lancer_pport_stats pport_stats; 1007 }; 1008 1009 static inline struct lancer_pport_stats* 1010 pport_stats_from_cmd(struct be_adapter *adapter) 1011 { 1012 struct lancer_cmd_resp_pport_stats *cmd = adapter->stats_cmd.va; 1013 return &cmd->pport_stats; 1014 } 1015 1016 struct be_cmd_req_get_cntl_addnl_attribs { 1017 struct be_cmd_req_hdr hdr; 1018 u8 rsvd[8]; 1019 }; 1020 1021 struct be_cmd_resp_get_cntl_addnl_attribs { 1022 struct be_cmd_resp_hdr hdr; 1023 u16 ipl_file_number; 1024 u8 ipl_file_version; 1025 u8 rsvd0; 1026 u8 on_die_temperature; /* in degrees centigrade*/ 1027 u8 rsvd1[3]; 1028 }; 1029 1030 struct be_cmd_req_vlan_config { 1031 struct be_cmd_req_hdr hdr; 1032 u8 interface_id; 1033 u8 promiscuous; 1034 u8 untagged; 1035 u8 num_vlan; 1036 u16 normal_vlan[64]; 1037 } __packed; 1038 1039 /******************* RX FILTER ******************************/ 1040 #define BE_MAX_MC 64 /* set mcast promisc if > 64 */ 1041 struct macaddr { 1042 u8 byte[ETH_ALEN]; 1043 }; 1044 1045 struct be_cmd_req_rx_filter { 1046 struct be_cmd_req_hdr hdr; 1047 u32 global_flags_mask; 1048 u32 global_flags; 1049 u32 if_flags_mask; 1050 u32 if_flags; 1051 u32 if_id; 1052 u32 mcast_num; 1053 struct macaddr mcast_mac[BE_MAX_MC]; 1054 }; 1055 1056 /******************** Link Status Query *******************/ 1057 struct be_cmd_req_link_status { 1058 struct be_cmd_req_hdr hdr; 1059 u32 rsvd; 1060 }; 1061 1062 enum { 1063 PHY_LINK_DUPLEX_NONE = 0x0, 1064 PHY_LINK_DUPLEX_HALF = 0x1, 1065 PHY_LINK_DUPLEX_FULL = 0x2 1066 }; 1067 1068 enum { 1069 PHY_LINK_SPEED_ZERO = 0x0, /* => No link */ 1070 PHY_LINK_SPEED_10MBPS = 0x1, 1071 PHY_LINK_SPEED_100MBPS = 0x2, 1072 PHY_LINK_SPEED_1GBPS = 0x3, 1073 PHY_LINK_SPEED_10GBPS = 0x4, 1074 PHY_LINK_SPEED_20GBPS = 0x5, 1075 PHY_LINK_SPEED_25GBPS = 0x6, 1076 PHY_LINK_SPEED_40GBPS = 0x7 1077 }; 1078 1079 struct be_cmd_resp_link_status { 1080 struct be_cmd_resp_hdr hdr; 1081 u8 physical_port; 1082 u8 mac_duplex; 1083 u8 mac_speed; 1084 u8 mac_fault; 1085 u8 mgmt_mac_duplex; 1086 u8 mgmt_mac_speed; 1087 u16 link_speed; 1088 u8 logical_link_status; 1089 u8 rsvd1[3]; 1090 } __packed; 1091 1092 /******************** Port Identification ***************************/ 1093 /* Identifies the type of port attached to NIC */ 1094 struct be_cmd_req_port_type { 1095 struct be_cmd_req_hdr hdr; 1096 __le32 page_num; 1097 __le32 port; 1098 }; 1099 1100 enum { 1101 TR_PAGE_A0 = 0xa0, 1102 TR_PAGE_A2 = 0xa2 1103 }; 1104 1105 /* From SFF-8436 QSFP+ spec */ 1106 #define QSFP_PLUS_CABLE_TYPE_OFFSET 0x83 1107 #define QSFP_PLUS_CR4_CABLE 0x8 1108 #define QSFP_PLUS_SR4_CABLE 0x4 1109 #define QSFP_PLUS_LR4_CABLE 0x2 1110 1111 /* From SFF-8472 spec */ 1112 #define SFP_PLUS_SFF_8472_COMP 0x5E 1113 #define SFP_PLUS_CABLE_TYPE_OFFSET 0x8 1114 #define SFP_PLUS_COPPER_CABLE 0x4 1115 #define SFP_VENDOR_NAME_OFFSET 0x14 1116 #define SFP_VENDOR_PN_OFFSET 0x28 1117 1118 #define PAGE_DATA_LEN 256 1119 struct be_cmd_resp_port_type { 1120 struct be_cmd_resp_hdr hdr; 1121 u32 page_num; 1122 u32 port; 1123 u8 page_data[PAGE_DATA_LEN]; 1124 }; 1125 1126 /******************** Get FW Version *******************/ 1127 struct be_cmd_req_get_fw_version { 1128 struct be_cmd_req_hdr hdr; 1129 u8 rsvd0[FW_VER_LEN]; 1130 u8 rsvd1[FW_VER_LEN]; 1131 } __packed; 1132 1133 struct be_cmd_resp_get_fw_version { 1134 struct be_cmd_resp_hdr hdr; 1135 u8 firmware_version_string[FW_VER_LEN]; 1136 u8 fw_on_flash_version_string[FW_VER_LEN]; 1137 } __packed; 1138 1139 /******************** Set Flow Contrl *******************/ 1140 struct be_cmd_req_set_flow_control { 1141 struct be_cmd_req_hdr hdr; 1142 u16 tx_flow_control; 1143 u16 rx_flow_control; 1144 } __packed; 1145 1146 /******************** Get Flow Contrl *******************/ 1147 struct be_cmd_req_get_flow_control { 1148 struct be_cmd_req_hdr hdr; 1149 u32 rsvd; 1150 }; 1151 1152 struct be_cmd_resp_get_flow_control { 1153 struct be_cmd_resp_hdr hdr; 1154 u16 tx_flow_control; 1155 u16 rx_flow_control; 1156 } __packed; 1157 1158 /******************** Modify EQ Delay *******************/ 1159 struct be_set_eqd { 1160 u32 eq_id; 1161 u32 phase; 1162 u32 delay_multiplier; 1163 }; 1164 1165 struct be_cmd_req_modify_eq_delay { 1166 struct be_cmd_req_hdr hdr; 1167 u32 num_eq; 1168 struct be_set_eqd set_eqd[MAX_EVT_QS]; 1169 } __packed; 1170 1171 /******************** Get FW Config *******************/ 1172 /* The HW can come up in either of the following multi-channel modes 1173 * based on the skew/IPL. 1174 */ 1175 #define RDMA_ENABLED 0x4 1176 #define QNQ_MODE 0x400 1177 #define VNIC_MODE 0x20000 1178 #define UMC_ENABLED 0x1000000 1179 struct be_cmd_req_query_fw_cfg { 1180 struct be_cmd_req_hdr hdr; 1181 u32 rsvd[31]; 1182 }; 1183 1184 struct be_cmd_resp_query_fw_cfg { 1185 struct be_cmd_resp_hdr hdr; 1186 u32 be_config_number; 1187 u32 asic_revision; 1188 u32 phys_port; 1189 u32 function_mode; 1190 u32 rsvd[26]; 1191 u32 function_caps; 1192 }; 1193 1194 /******************** RSS Config ****************************************/ 1195 /* RSS type Input parameters used to compute RX hash 1196 * RSS_ENABLE_IPV4 SRC IPv4, DST IPv4 1197 * RSS_ENABLE_TCP_IPV4 SRC IPv4, DST IPv4, TCP SRC PORT, TCP DST PORT 1198 * RSS_ENABLE_IPV6 SRC IPv6, DST IPv6 1199 * RSS_ENABLE_TCP_IPV6 SRC IPv6, DST IPv6, TCP SRC PORT, TCP DST PORT 1200 * RSS_ENABLE_UDP_IPV4 SRC IPv4, DST IPv4, UDP SRC PORT, UDP DST PORT 1201 * RSS_ENABLE_UDP_IPV6 SRC IPv6, DST IPv6, UDP SRC PORT, UDP DST PORT 1202 * 1203 * When multiple RSS types are enabled, HW picks the best hash policy 1204 * based on the type of the received packet. 1205 */ 1206 #define RSS_ENABLE_NONE 0x0 1207 #define RSS_ENABLE_IPV4 0x1 1208 #define RSS_ENABLE_TCP_IPV4 0x2 1209 #define RSS_ENABLE_IPV6 0x4 1210 #define RSS_ENABLE_TCP_IPV6 0x8 1211 #define RSS_ENABLE_UDP_IPV4 0x10 1212 #define RSS_ENABLE_UDP_IPV6 0x20 1213 1214 #define L3_RSS_FLAGS (RXH_IP_DST | RXH_IP_SRC) 1215 #define L4_RSS_FLAGS (RXH_L4_B_0_1 | RXH_L4_B_2_3) 1216 1217 struct be_cmd_req_rss_config { 1218 struct be_cmd_req_hdr hdr; 1219 u32 if_id; 1220 u16 enable_rss; 1221 u16 cpu_table_size_log2; 1222 u32 hash[10]; 1223 u8 cpu_table[128]; 1224 u8 flush; 1225 u8 rsvd0[3]; 1226 }; 1227 1228 /******************** Port Beacon ***************************/ 1229 1230 #define BEACON_STATE_ENABLED 0x1 1231 #define BEACON_STATE_DISABLED 0x0 1232 1233 struct be_cmd_req_enable_disable_beacon { 1234 struct be_cmd_req_hdr hdr; 1235 u8 port_num; 1236 u8 beacon_state; 1237 u8 beacon_duration; 1238 u8 status_duration; 1239 } __packed; 1240 1241 struct be_cmd_req_get_beacon_state { 1242 struct be_cmd_req_hdr hdr; 1243 u8 port_num; 1244 u8 rsvd0; 1245 u16 rsvd1; 1246 } __packed; 1247 1248 struct be_cmd_resp_get_beacon_state { 1249 struct be_cmd_resp_hdr resp_hdr; 1250 u8 beacon_state; 1251 u8 rsvd0[3]; 1252 } __packed; 1253 1254 /* Flashrom related descriptors */ 1255 #define MAX_FLASH_COMP 32 1256 1257 /* Optypes of each component in the UFI */ 1258 enum { 1259 OPTYPE_ISCSI_ACTIVE = 0, 1260 OPTYPE_REDBOOT = 1, 1261 OPTYPE_BIOS = 2, 1262 OPTYPE_PXE_BIOS = 3, 1263 OPTYPE_OFFSET_SPECIFIED = 7, 1264 OPTYPE_FCOE_BIOS = 8, 1265 OPTYPE_ISCSI_BACKUP = 9, 1266 OPTYPE_FCOE_FW_ACTIVE = 10, 1267 OPTYPE_FCOE_FW_BACKUP = 11, 1268 OPTYPE_NCSI_FW = 13, 1269 OPTYPE_REDBOOT_DIR = 18, 1270 OPTYPE_REDBOOT_CONFIG = 19, 1271 OPTYPE_SH_PHY_FW = 21, 1272 OPTYPE_FLASHISM_JUMPVECTOR = 22, 1273 OPTYPE_UFI_DIR = 23, 1274 OPTYPE_PHY_FW = 99 1275 }; 1276 1277 /* Maximum sizes of components in BE2 FW UFI */ 1278 enum { 1279 BE2_BIOS_COMP_MAX_SIZE = 0x40000, 1280 BE2_REDBOOT_COMP_MAX_SIZE = 0x40000, 1281 BE2_COMP_MAX_SIZE = 0x140000 1282 }; 1283 1284 /* Maximum sizes of components in BE3 FW UFI */ 1285 enum { 1286 BE3_NCSI_COMP_MAX_SIZE = 0x40000, 1287 BE3_PHY_FW_COMP_MAX_SIZE = 0x40000, 1288 BE3_BIOS_COMP_MAX_SIZE = 0x80000, 1289 BE3_REDBOOT_COMP_MAX_SIZE = 0x100000, 1290 BE3_COMP_MAX_SIZE = 0x200000 1291 }; 1292 1293 /* Offsets for components in BE2 FW UFI */ 1294 enum { 1295 BE2_REDBOOT_START = 0x8000, 1296 BE2_FCOE_BIOS_START = 0x80000, 1297 BE2_ISCSI_PRIMARY_IMAGE_START = 0x100000, 1298 BE2_ISCSI_BACKUP_IMAGE_START = 0x240000, 1299 BE2_FCOE_PRIMARY_IMAGE_START = 0x380000, 1300 BE2_FCOE_BACKUP_IMAGE_START = 0x4c0000, 1301 BE2_ISCSI_BIOS_START = 0x700000, 1302 BE2_PXE_BIOS_START = 0x780000 1303 }; 1304 1305 /* Offsets for components in BE3 FW UFI */ 1306 enum { 1307 BE3_REDBOOT_START = 0x40000, 1308 BE3_PHY_FW_START = 0x140000, 1309 BE3_ISCSI_PRIMARY_IMAGE_START = 0x200000, 1310 BE3_ISCSI_BACKUP_IMAGE_START = 0x400000, 1311 BE3_FCOE_PRIMARY_IMAGE_START = 0x600000, 1312 BE3_FCOE_BACKUP_IMAGE_START = 0x800000, 1313 BE3_ISCSI_BIOS_START = 0xc00000, 1314 BE3_PXE_BIOS_START = 0xc80000, 1315 BE3_FCOE_BIOS_START = 0xd00000, 1316 BE3_NCSI_START = 0xf40000 1317 }; 1318 1319 /* Component entry types */ 1320 enum { 1321 IMAGE_NCSI = 0x10, 1322 IMAGE_OPTION_ROM_PXE = 0x20, 1323 IMAGE_OPTION_ROM_FCOE = 0x21, 1324 IMAGE_OPTION_ROM_ISCSI = 0x22, 1325 IMAGE_FLASHISM_JUMPVECTOR = 0x30, 1326 IMAGE_FIRMWARE_ISCSI = 0xa0, 1327 IMAGE_FIRMWARE_FCOE = 0xa2, 1328 IMAGE_FIRMWARE_BACKUP_ISCSI = 0xb0, 1329 IMAGE_FIRMWARE_BACKUP_FCOE = 0xb2, 1330 IMAGE_FIRMWARE_PHY = 0xc0, 1331 IMAGE_REDBOOT_DIR = 0xd0, 1332 IMAGE_REDBOOT_CONFIG = 0xd1, 1333 IMAGE_UFI_DIR = 0xd2, 1334 IMAGE_BOOT_CODE = 0xe2 1335 }; 1336 1337 struct controller_id { 1338 u32 vendor; 1339 u32 device; 1340 u32 subvendor; 1341 u32 subdevice; 1342 }; 1343 1344 struct flash_comp { 1345 unsigned long offset; 1346 int optype; 1347 int size; 1348 int img_type; 1349 }; 1350 1351 struct image_hdr { 1352 u32 imageid; 1353 u32 imageoffset; 1354 u32 imagelength; 1355 u32 image_checksum; 1356 u8 image_version[32]; 1357 }; 1358 1359 struct flash_file_hdr_g2 { 1360 u8 sign[32]; 1361 u32 cksum; 1362 u32 antidote; 1363 struct controller_id cont_id; 1364 u32 file_len; 1365 u32 chunk_num; 1366 u32 total_chunks; 1367 u32 num_imgs; 1368 u8 build[24]; 1369 }; 1370 1371 /* First letter of the build version of the image */ 1372 #define BLD_STR_UFI_TYPE_BE2 '2' 1373 #define BLD_STR_UFI_TYPE_BE3 '3' 1374 #define BLD_STR_UFI_TYPE_SH '4' 1375 1376 struct flash_file_hdr_g3 { 1377 u8 sign[52]; 1378 u8 ufi_version[4]; 1379 u32 file_len; 1380 u32 cksum; 1381 u32 antidote; 1382 u32 num_imgs; 1383 u8 build[24]; 1384 u8 asic_type_rev; 1385 u8 rsvd[31]; 1386 }; 1387 1388 struct flash_section_hdr { 1389 u32 format_rev; 1390 u32 cksum; 1391 u32 antidote; 1392 u32 num_images; 1393 u8 id_string[128]; 1394 u32 rsvd[4]; 1395 } __packed; 1396 1397 struct flash_section_hdr_g2 { 1398 u32 format_rev; 1399 u32 cksum; 1400 u32 antidote; 1401 u32 build_num; 1402 u8 id_string[128]; 1403 u32 rsvd[8]; 1404 } __packed; 1405 1406 struct flash_section_entry { 1407 u32 type; 1408 u32 offset; 1409 u32 pad_size; 1410 u32 image_size; 1411 u32 cksum; 1412 u32 entry_point; 1413 u16 optype; 1414 u16 rsvd0; 1415 u32 rsvd1; 1416 u8 ver_data[32]; 1417 } __packed; 1418 1419 struct flash_section_info { 1420 u8 cookie[32]; 1421 struct flash_section_hdr fsec_hdr; 1422 struct flash_section_entry fsec_entry[32]; 1423 } __packed; 1424 1425 struct flash_section_info_g2 { 1426 u8 cookie[32]; 1427 struct flash_section_hdr_g2 fsec_hdr; 1428 struct flash_section_entry fsec_entry[32]; 1429 } __packed; 1430 1431 /****************** Firmware Flash ******************/ 1432 #define FLASHROM_OPER_FLASH 1 1433 #define FLASHROM_OPER_SAVE 2 1434 #define FLASHROM_OPER_REPORT 4 1435 #define FLASHROM_OPER_PHY_FLASH 9 1436 #define FLASHROM_OPER_PHY_SAVE 10 1437 1438 struct flashrom_params { 1439 u32 op_code; 1440 u32 op_type; 1441 u32 data_buf_size; 1442 u32 offset; 1443 }; 1444 1445 struct be_cmd_write_flashrom { 1446 struct be_cmd_req_hdr hdr; 1447 struct flashrom_params params; 1448 u8 data_buf[32768]; 1449 u8 rsvd[4]; 1450 } __packed; 1451 1452 /* cmd to read flash crc */ 1453 struct be_cmd_read_flash_crc { 1454 struct be_cmd_req_hdr hdr; 1455 struct flashrom_params params; 1456 u8 crc[4]; 1457 u8 rsvd[4]; 1458 } __packed; 1459 1460 /**************** Lancer Firmware Flash ************/ 1461 #define LANCER_FW_DOWNLOAD_CHUNK (32 * 1024) 1462 #define LANCER_FW_DOWNLOAD_LOCATION "/prg" 1463 1464 struct amap_lancer_write_obj_context { 1465 u8 write_length[24]; 1466 u8 reserved1[7]; 1467 u8 eof; 1468 } __packed; 1469 1470 struct lancer_cmd_req_write_object { 1471 struct be_cmd_req_hdr hdr; 1472 u8 context[sizeof(struct amap_lancer_write_obj_context) / 8]; 1473 u32 write_offset; 1474 u8 object_name[104]; 1475 u32 descriptor_count; 1476 u32 buf_len; 1477 u32 addr_low; 1478 u32 addr_high; 1479 }; 1480 1481 #define LANCER_NO_RESET_NEEDED 0x00 1482 #define LANCER_FW_RESET_NEEDED 0x02 1483 struct lancer_cmd_resp_write_object { 1484 u8 opcode; 1485 u8 subsystem; 1486 u8 rsvd1[2]; 1487 u8 status; 1488 u8 additional_status; 1489 u8 rsvd2[2]; 1490 u32 resp_len; 1491 u32 actual_resp_len; 1492 u32 actual_write_len; 1493 u8 change_status; 1494 u8 rsvd3[3]; 1495 }; 1496 1497 /************************ Lancer Read FW info **************/ 1498 #define LANCER_READ_FILE_CHUNK (32*1024) 1499 #define LANCER_READ_FILE_EOF_MASK 0x80000000 1500 1501 #define LANCER_FW_DUMP_FILE "/dbg/dump.bin" 1502 #define LANCER_VPD_PF_FILE "/vpd/ntr_pf.vpd" 1503 #define LANCER_VPD_VF_FILE "/vpd/ntr_vf.vpd" 1504 1505 struct lancer_cmd_req_read_object { 1506 struct be_cmd_req_hdr hdr; 1507 u32 desired_read_len; 1508 u32 read_offset; 1509 u8 object_name[104]; 1510 u32 descriptor_count; 1511 u32 buf_len; 1512 u32 addr_low; 1513 u32 addr_high; 1514 }; 1515 1516 struct lancer_cmd_resp_read_object { 1517 u8 opcode; 1518 u8 subsystem; 1519 u8 rsvd1[2]; 1520 u8 status; 1521 u8 additional_status; 1522 u8 rsvd2[2]; 1523 u32 resp_len; 1524 u32 actual_resp_len; 1525 u32 actual_read_len; 1526 u32 eof; 1527 }; 1528 1529 struct lancer_cmd_req_delete_object { 1530 struct be_cmd_req_hdr hdr; 1531 u32 rsvd1; 1532 u32 rsvd2; 1533 u8 object_name[104]; 1534 }; 1535 1536 /************************ WOL *******************************/ 1537 struct be_cmd_req_acpi_wol_magic_config{ 1538 struct be_cmd_req_hdr hdr; 1539 u32 rsvd0[145]; 1540 u8 magic_mac[6]; 1541 u8 rsvd2[2]; 1542 } __packed; 1543 1544 struct be_cmd_req_acpi_wol_magic_config_v1 { 1545 struct be_cmd_req_hdr hdr; 1546 u8 rsvd0[2]; 1547 u8 query_options; 1548 u8 rsvd1[5]; 1549 u32 rsvd2[288]; 1550 u8 magic_mac[6]; 1551 u8 rsvd3[22]; 1552 } __packed; 1553 1554 struct be_cmd_resp_acpi_wol_magic_config_v1 { 1555 struct be_cmd_resp_hdr hdr; 1556 u8 rsvd0[2]; 1557 u8 wol_settings; 1558 u8 rsvd1[5]; 1559 u32 rsvd2[295]; 1560 } __packed; 1561 1562 #define BE_GET_WOL_CAP 2 1563 1564 #define BE_WOL_CAP 0x1 1565 #define BE_PME_D0_CAP 0x8 1566 #define BE_PME_D1_CAP 0x10 1567 #define BE_PME_D2_CAP 0x20 1568 #define BE_PME_D3HOT_CAP 0x40 1569 #define BE_PME_D3COLD_CAP 0x80 1570 1571 /********************** LoopBack test *********************/ 1572 #define SET_LB_MODE_TIMEOUT 12000 1573 1574 struct be_cmd_req_loopback_test { 1575 struct be_cmd_req_hdr hdr; 1576 u32 loopback_type; 1577 u32 num_pkts; 1578 u64 pattern; 1579 u32 src_port; 1580 u32 dest_port; 1581 u32 pkt_size; 1582 }; 1583 1584 struct be_cmd_resp_loopback_test { 1585 struct be_cmd_resp_hdr resp_hdr; 1586 u32 status; 1587 u32 num_txfer; 1588 u32 num_rx; 1589 u32 miscomp_off; 1590 u32 ticks_compl; 1591 }; 1592 1593 struct be_cmd_req_set_lmode { 1594 struct be_cmd_req_hdr hdr; 1595 u8 src_port; 1596 u8 dest_port; 1597 u8 loopback_type; 1598 u8 loopback_state; 1599 }; 1600 1601 /********************** DDR DMA test *********************/ 1602 struct be_cmd_req_ddrdma_test { 1603 struct be_cmd_req_hdr hdr; 1604 u64 pattern; 1605 u32 byte_count; 1606 u32 rsvd0; 1607 u8 snd_buff[4096]; 1608 u8 rsvd1[4096]; 1609 }; 1610 1611 struct be_cmd_resp_ddrdma_test { 1612 struct be_cmd_resp_hdr hdr; 1613 u64 pattern; 1614 u32 byte_cnt; 1615 u32 snd_err; 1616 u8 rsvd0[4096]; 1617 u8 rcv_buff[4096]; 1618 }; 1619 1620 /*********************** SEEPROM Read ***********************/ 1621 1622 #define BE_READ_SEEPROM_LEN 1024 1623 struct be_cmd_req_seeprom_read { 1624 struct be_cmd_req_hdr hdr; 1625 u8 rsvd0[BE_READ_SEEPROM_LEN]; 1626 }; 1627 1628 struct be_cmd_resp_seeprom_read { 1629 struct be_cmd_req_hdr hdr; 1630 u8 seeprom_data[BE_READ_SEEPROM_LEN]; 1631 }; 1632 1633 enum { 1634 PHY_TYPE_CX4_10GB = 0, 1635 PHY_TYPE_XFP_10GB, 1636 PHY_TYPE_SFP_1GB, 1637 PHY_TYPE_SFP_PLUS_10GB, 1638 PHY_TYPE_KR_10GB, 1639 PHY_TYPE_KX4_10GB, 1640 PHY_TYPE_BASET_10GB, 1641 PHY_TYPE_BASET_1GB, 1642 PHY_TYPE_BASEX_1GB, 1643 PHY_TYPE_SGMII, 1644 PHY_TYPE_QSFP, 1645 PHY_TYPE_KR4_40GB, 1646 PHY_TYPE_KR2_20GB, 1647 PHY_TYPE_TN_8022, 1648 PHY_TYPE_DISABLED = 255 1649 }; 1650 1651 #define BE_SUPPORTED_SPEED_NONE 0 1652 #define BE_SUPPORTED_SPEED_10MBPS 1 1653 #define BE_SUPPORTED_SPEED_100MBPS 2 1654 #define BE_SUPPORTED_SPEED_1GBPS 4 1655 #define BE_SUPPORTED_SPEED_10GBPS 8 1656 #define BE_SUPPORTED_SPEED_20GBPS 0x10 1657 #define BE_SUPPORTED_SPEED_40GBPS 0x20 1658 1659 #define BE_AN_EN 0x2 1660 #define BE_PAUSE_SYM_EN 0x80 1661 1662 /* MAC speed valid values */ 1663 #define SPEED_DEFAULT 0x0 1664 #define SPEED_FORCED_10GB 0x1 1665 #define SPEED_FORCED_1GB 0x2 1666 #define SPEED_AUTONEG_10GB 0x3 1667 #define SPEED_AUTONEG_1GB 0x4 1668 #define SPEED_AUTONEG_100MB 0x5 1669 #define SPEED_AUTONEG_10GB_1GB 0x6 1670 #define SPEED_AUTONEG_10GB_1GB_100MB 0x7 1671 #define SPEED_AUTONEG_1GB_100MB 0x8 1672 #define SPEED_AUTONEG_10MB 0x9 1673 #define SPEED_AUTONEG_1GB_100MB_10MB 0xa 1674 #define SPEED_AUTONEG_100MB_10MB 0xb 1675 #define SPEED_FORCED_100MB 0xc 1676 #define SPEED_FORCED_10MB 0xd 1677 1678 struct be_cmd_req_get_phy_info { 1679 struct be_cmd_req_hdr hdr; 1680 u8 rsvd0[24]; 1681 }; 1682 1683 struct be_phy_info { 1684 u16 phy_type; 1685 u16 interface_type; 1686 u32 misc_params; 1687 u16 ext_phy_details; 1688 u16 rsvd; 1689 u16 auto_speeds_supported; 1690 u16 fixed_speeds_supported; 1691 u32 future_use[2]; 1692 }; 1693 1694 struct be_cmd_resp_get_phy_info { 1695 struct be_cmd_req_hdr hdr; 1696 struct be_phy_info phy_info; 1697 }; 1698 1699 /*********************** Set QOS ***********************/ 1700 1701 #define BE_QOS_BITS_NIC 1 1702 1703 struct be_cmd_req_set_qos { 1704 struct be_cmd_req_hdr hdr; 1705 u32 valid_bits; 1706 u32 max_bps_nic; 1707 u32 rsvd[7]; 1708 }; 1709 1710 /*********************** Controller Attributes ***********************/ 1711 struct mgmt_hba_attribs { 1712 u32 rsvd0[24]; 1713 u8 controller_model_number[32]; 1714 u32 rsvd1[16]; 1715 u32 controller_serial_number[8]; 1716 u32 rsvd2[55]; 1717 u8 rsvd3[3]; 1718 u8 phy_port; 1719 u32 rsvd4[13]; 1720 } __packed; 1721 1722 struct mgmt_controller_attrib { 1723 struct mgmt_hba_attribs hba_attribs; 1724 u32 rsvd0[10]; 1725 } __packed; 1726 1727 struct be_cmd_req_cntl_attribs { 1728 struct be_cmd_req_hdr hdr; 1729 }; 1730 1731 struct be_cmd_resp_cntl_attribs { 1732 struct be_cmd_resp_hdr hdr; 1733 struct mgmt_controller_attrib attribs; 1734 }; 1735 1736 /*********************** Set driver function ***********************/ 1737 #define CAPABILITY_SW_TIMESTAMPS 2 1738 #define CAPABILITY_BE3_NATIVE_ERX_API 4 1739 1740 struct be_cmd_req_set_func_cap { 1741 struct be_cmd_req_hdr hdr; 1742 u32 valid_cap_flags; 1743 u32 cap_flags; 1744 u8 rsvd[212]; 1745 }; 1746 1747 struct be_cmd_resp_set_func_cap { 1748 struct be_cmd_resp_hdr hdr; 1749 u32 valid_cap_flags; 1750 u32 cap_flags; 1751 u8 rsvd[212]; 1752 }; 1753 1754 /*********************** Function Privileges ***********************/ 1755 enum { 1756 BE_PRIV_DEFAULT = 0x1, 1757 BE_PRIV_LNKQUERY = 0x2, 1758 BE_PRIV_LNKSTATS = 0x4, 1759 BE_PRIV_LNKMGMT = 0x8, 1760 BE_PRIV_LNKDIAG = 0x10, 1761 BE_PRIV_UTILQUERY = 0x20, 1762 BE_PRIV_FILTMGMT = 0x40, 1763 BE_PRIV_IFACEMGMT = 0x80, 1764 BE_PRIV_VHADM = 0x100, 1765 BE_PRIV_DEVCFG = 0x200, 1766 BE_PRIV_DEVSEC = 0x400 1767 }; 1768 #define MAX_PRIVILEGES (BE_PRIV_VHADM | BE_PRIV_DEVCFG | \ 1769 BE_PRIV_DEVSEC) 1770 #define MIN_PRIVILEGES BE_PRIV_DEFAULT 1771 1772 struct be_cmd_priv_map { 1773 u8 opcode; 1774 u8 subsystem; 1775 u32 priv_mask; 1776 }; 1777 1778 struct be_cmd_req_get_fn_privileges { 1779 struct be_cmd_req_hdr hdr; 1780 u32 rsvd; 1781 }; 1782 1783 struct be_cmd_resp_get_fn_privileges { 1784 struct be_cmd_resp_hdr hdr; 1785 u32 privilege_mask; 1786 }; 1787 1788 struct be_cmd_req_set_fn_privileges { 1789 struct be_cmd_req_hdr hdr; 1790 u32 privileges; /* Used by BE3, SH-R */ 1791 u32 privileges_lancer; /* Used by Lancer */ 1792 }; 1793 1794 /******************** GET/SET_MACLIST **************************/ 1795 #define BE_MAX_MAC 64 1796 struct be_cmd_req_get_mac_list { 1797 struct be_cmd_req_hdr hdr; 1798 u8 mac_type; 1799 u8 perm_override; 1800 u16 iface_id; 1801 u32 mac_id; 1802 u32 rsvd[3]; 1803 } __packed; 1804 1805 struct get_list_macaddr { 1806 u16 mac_addr_size; 1807 union { 1808 u8 macaddr[6]; 1809 struct { 1810 u8 rsvd[2]; 1811 u32 mac_id; 1812 } __packed s_mac_id; 1813 } __packed mac_addr_id; 1814 } __packed; 1815 1816 struct be_cmd_resp_get_mac_list { 1817 struct be_cmd_resp_hdr hdr; 1818 struct get_list_macaddr fd_macaddr; /* Factory default mac */ 1819 struct get_list_macaddr macid_macaddr; /* soft mac */ 1820 u8 true_mac_count; 1821 u8 pseudo_mac_count; 1822 u8 mac_list_size; 1823 u8 rsvd; 1824 /* perm override mac */ 1825 struct get_list_macaddr macaddr_list[BE_MAX_MAC]; 1826 } __packed; 1827 1828 struct be_cmd_req_set_mac_list { 1829 struct be_cmd_req_hdr hdr; 1830 u8 mac_count; 1831 u8 rsvd1; 1832 u16 rsvd2; 1833 struct macaddr mac[BE_MAX_MAC]; 1834 } __packed; 1835 1836 /*********************** HSW Config ***********************/ 1837 #define PORT_FWD_TYPE_VEPA 0x3 1838 #define PORT_FWD_TYPE_VEB 0x2 1839 #define PORT_FWD_TYPE_PASSTHRU 0x1 1840 1841 #define ENABLE_MAC_SPOOFCHK 0x2 1842 #define DISABLE_MAC_SPOOFCHK 0x3 1843 1844 struct amap_set_hsw_context { 1845 u8 interface_id[16]; 1846 u8 rsvd0[8]; 1847 u8 mac_spoofchk[2]; 1848 u8 rsvd1[4]; 1849 u8 pvid_valid; 1850 u8 pport; 1851 u8 rsvd2[6]; 1852 u8 port_fwd_type[3]; 1853 u8 rsvd3[5]; 1854 u8 vlan_spoofchk[2]; 1855 u8 pvid[16]; 1856 u8 rsvd4[32]; 1857 u8 rsvd5[32]; 1858 u8 rsvd6[32]; 1859 } __packed; 1860 1861 struct be_cmd_req_set_hsw_config { 1862 struct be_cmd_req_hdr hdr; 1863 u8 context[sizeof(struct amap_set_hsw_context) / 8]; 1864 } __packed; 1865 1866 struct amap_get_hsw_req_context { 1867 u8 interface_id[16]; 1868 u8 rsvd0[14]; 1869 u8 pvid_valid; 1870 u8 pport; 1871 } __packed; 1872 1873 struct amap_get_hsw_resp_context { 1874 u8 rsvd0[6]; 1875 u8 port_fwd_type[3]; 1876 u8 rsvd1[5]; 1877 u8 spoofchk; 1878 u8 rsvd2; 1879 u8 pvid[16]; 1880 u8 rsvd3[32]; 1881 u8 rsvd4[32]; 1882 u8 rsvd5[32]; 1883 } __packed; 1884 1885 struct be_cmd_req_get_hsw_config { 1886 struct be_cmd_req_hdr hdr; 1887 u8 context[sizeof(struct amap_get_hsw_req_context) / 8]; 1888 } __packed; 1889 1890 struct be_cmd_resp_get_hsw_config { 1891 struct be_cmd_resp_hdr hdr; 1892 u8 context[sizeof(struct amap_get_hsw_resp_context) / 8]; 1893 u32 rsvd; 1894 }; 1895 1896 /******************* get port names ***************/ 1897 struct be_cmd_req_get_port_name { 1898 struct be_cmd_req_hdr hdr; 1899 u32 rsvd0; 1900 }; 1901 1902 struct be_cmd_resp_get_port_name { 1903 struct be_cmd_req_hdr hdr; 1904 u8 port_name[4]; 1905 }; 1906 1907 /*************** HW Stats Get v1 **********************************/ 1908 #define BE_TXP_SW_SZ 48 1909 struct be_port_rxf_stats_v1 { 1910 u32 rsvd0[12]; 1911 u32 rx_crc_errors; 1912 u32 rx_alignment_symbol_errors; 1913 u32 rx_pause_frames; 1914 u32 rx_priority_pause_frames; 1915 u32 rx_control_frames; 1916 u32 rx_in_range_errors; 1917 u32 rx_out_range_errors; 1918 u32 rx_frame_too_long; 1919 u32 rx_address_filtered; 1920 u32 rx_dropped_too_small; 1921 u32 rx_dropped_too_short; 1922 u32 rx_dropped_header_too_small; 1923 u32 rx_dropped_tcp_length; 1924 u32 rx_dropped_runt; 1925 u32 rsvd1[10]; 1926 u32 rx_ip_checksum_errs; 1927 u32 rx_tcp_checksum_errs; 1928 u32 rx_udp_checksum_errs; 1929 u32 rsvd2[7]; 1930 u32 rx_switched_unicast_packets; 1931 u32 rx_switched_multicast_packets; 1932 u32 rx_switched_broadcast_packets; 1933 u32 rsvd3[3]; 1934 u32 tx_pauseframes; 1935 u32 tx_priority_pauseframes; 1936 u32 tx_controlframes; 1937 u32 rsvd4[10]; 1938 u32 rxpp_fifo_overflow_drop; 1939 u32 rx_input_fifo_overflow_drop; 1940 u32 pmem_fifo_overflow_drop; 1941 u32 jabber_events; 1942 u32 rsvd5[3]; 1943 }; 1944 1945 1946 struct be_rxf_stats_v1 { 1947 struct be_port_rxf_stats_v1 port[4]; 1948 u32 rsvd0[2]; 1949 u32 rx_drops_no_pbuf; 1950 u32 rx_drops_no_txpb; 1951 u32 rx_drops_no_erx_descr; 1952 u32 rx_drops_no_tpre_descr; 1953 u32 rsvd1[6]; 1954 u32 rx_drops_too_many_frags; 1955 u32 rx_drops_invalid_ring; 1956 u32 forwarded_packets; 1957 u32 rx_drops_mtu; 1958 u32 rsvd2[14]; 1959 }; 1960 1961 struct be_erx_stats_v1 { 1962 u32 rx_drops_no_fragments[68]; /* dwordS 0 to 67*/ 1963 u32 rsvd[4]; 1964 }; 1965 1966 struct be_port_rxf_stats_v2 { 1967 u32 rsvd0[10]; 1968 u32 roce_bytes_received_lsd; 1969 u32 roce_bytes_received_msd; 1970 u32 rsvd1[5]; 1971 u32 roce_frames_received; 1972 u32 rx_crc_errors; 1973 u32 rx_alignment_symbol_errors; 1974 u32 rx_pause_frames; 1975 u32 rx_priority_pause_frames; 1976 u32 rx_control_frames; 1977 u32 rx_in_range_errors; 1978 u32 rx_out_range_errors; 1979 u32 rx_frame_too_long; 1980 u32 rx_address_filtered; 1981 u32 rx_dropped_too_small; 1982 u32 rx_dropped_too_short; 1983 u32 rx_dropped_header_too_small; 1984 u32 rx_dropped_tcp_length; 1985 u32 rx_dropped_runt; 1986 u32 rsvd2[10]; 1987 u32 rx_ip_checksum_errs; 1988 u32 rx_tcp_checksum_errs; 1989 u32 rx_udp_checksum_errs; 1990 u32 rsvd3[7]; 1991 u32 rx_switched_unicast_packets; 1992 u32 rx_switched_multicast_packets; 1993 u32 rx_switched_broadcast_packets; 1994 u32 rsvd4[3]; 1995 u32 tx_pauseframes; 1996 u32 tx_priority_pauseframes; 1997 u32 tx_controlframes; 1998 u32 rsvd5[10]; 1999 u32 rxpp_fifo_overflow_drop; 2000 u32 rx_input_fifo_overflow_drop; 2001 u32 pmem_fifo_overflow_drop; 2002 u32 jabber_events; 2003 u32 rsvd6[3]; 2004 u32 rx_drops_payload_size; 2005 u32 rx_drops_clipped_header; 2006 u32 rx_drops_crc; 2007 u32 roce_drops_payload_len; 2008 u32 roce_drops_crc; 2009 u32 rsvd7[19]; 2010 }; 2011 2012 struct be_rxf_stats_v2 { 2013 struct be_port_rxf_stats_v2 port[4]; 2014 u32 rsvd0[2]; 2015 u32 rx_drops_no_pbuf; 2016 u32 rx_drops_no_txpb; 2017 u32 rx_drops_no_erx_descr; 2018 u32 rx_drops_no_tpre_descr; 2019 u32 rsvd1[6]; 2020 u32 rx_drops_too_many_frags; 2021 u32 rx_drops_invalid_ring; 2022 u32 forwarded_packets; 2023 u32 rx_drops_mtu; 2024 u32 rsvd2[35]; 2025 }; 2026 2027 struct be_hw_stats_v1 { 2028 struct be_rxf_stats_v1 rxf; 2029 u32 rsvd0[BE_TXP_SW_SZ]; 2030 struct be_erx_stats_v1 erx; 2031 struct be_pmem_stats pmem; 2032 u32 rsvd1[18]; 2033 }; 2034 2035 struct be_cmd_req_get_stats_v1 { 2036 struct be_cmd_req_hdr hdr; 2037 u8 rsvd[sizeof(struct be_hw_stats_v1)]; 2038 }; 2039 2040 struct be_cmd_resp_get_stats_v1 { 2041 struct be_cmd_resp_hdr hdr; 2042 struct be_hw_stats_v1 hw_stats; 2043 }; 2044 2045 struct be_erx_stats_v2 { 2046 u32 rx_drops_no_fragments[136]; /* dwordS 0 to 135*/ 2047 u32 rsvd[3]; 2048 }; 2049 2050 struct be_hw_stats_v2 { 2051 struct be_rxf_stats_v2 rxf; 2052 u32 rsvd0[BE_TXP_SW_SZ]; 2053 struct be_erx_stats_v2 erx; 2054 struct be_pmem_stats pmem; 2055 u32 rsvd1[18]; 2056 }; 2057 2058 struct be_cmd_req_get_stats_v2 { 2059 struct be_cmd_req_hdr hdr; 2060 u8 rsvd[sizeof(struct be_hw_stats_v2)]; 2061 }; 2062 2063 struct be_cmd_resp_get_stats_v2 { 2064 struct be_cmd_resp_hdr hdr; 2065 struct be_hw_stats_v2 hw_stats; 2066 }; 2067 2068 /************** get fat capabilites *******************/ 2069 #define MAX_MODULES 27 2070 #define MAX_MODES 4 2071 #define MODE_UART 0 2072 #define FW_LOG_LEVEL_DEFAULT 48 2073 #define FW_LOG_LEVEL_FATAL 64 2074 2075 struct ext_fat_mode { 2076 u8 mode; 2077 u8 rsvd0; 2078 u16 port_mask; 2079 u32 dbg_lvl; 2080 u64 fun_mask; 2081 } __packed; 2082 2083 struct ext_fat_modules { 2084 u8 modules_str[32]; 2085 u32 modules_id; 2086 u32 num_modes; 2087 struct ext_fat_mode trace_lvl[MAX_MODES]; 2088 } __packed; 2089 2090 struct be_fat_conf_params { 2091 u32 max_log_entries; 2092 u32 log_entry_size; 2093 u8 log_type; 2094 u8 max_log_funs; 2095 u8 max_log_ports; 2096 u8 rsvd0; 2097 u32 supp_modes; 2098 u32 num_modules; 2099 struct ext_fat_modules module[MAX_MODULES]; 2100 } __packed; 2101 2102 struct be_cmd_req_get_ext_fat_caps { 2103 struct be_cmd_req_hdr hdr; 2104 u32 parameter_type; 2105 }; 2106 2107 struct be_cmd_resp_get_ext_fat_caps { 2108 struct be_cmd_resp_hdr hdr; 2109 struct be_fat_conf_params get_params; 2110 }; 2111 2112 struct be_cmd_req_set_ext_fat_caps { 2113 struct be_cmd_req_hdr hdr; 2114 struct be_fat_conf_params set_params; 2115 }; 2116 2117 #define RESOURCE_DESC_SIZE_V0 72 2118 #define RESOURCE_DESC_SIZE_V1 88 2119 #define PCIE_RESOURCE_DESC_TYPE_V0 0x40 2120 #define NIC_RESOURCE_DESC_TYPE_V0 0x41 2121 #define PCIE_RESOURCE_DESC_TYPE_V1 0x50 2122 #define NIC_RESOURCE_DESC_TYPE_V1 0x51 2123 #define PORT_RESOURCE_DESC_TYPE_V1 0x55 2124 #define MAX_RESOURCE_DESC 264 2125 2126 #define IF_CAPS_FLAGS_VALID_SHIFT 0 /* IF caps valid */ 2127 #define VFT_SHIFT 3 /* VF template */ 2128 #define IMM_SHIFT 6 /* Immediate */ 2129 #define NOSV_SHIFT 7 /* No save */ 2130 2131 struct be_res_desc_hdr { 2132 u8 desc_type; 2133 u8 desc_len; 2134 } __packed; 2135 2136 struct be_port_res_desc { 2137 struct be_res_desc_hdr hdr; 2138 u8 rsvd0; 2139 u8 flags; 2140 u8 link_num; 2141 u8 mc_type; 2142 u16 rsvd1; 2143 2144 #define NV_TYPE_MASK 0x3 /* bits 0-1 */ 2145 #define NV_TYPE_DISABLED 1 2146 #define NV_TYPE_VXLAN 3 2147 #define SOCVID_SHIFT 2 /* Strip outer vlan */ 2148 #define RCVID_SHIFT 4 /* Report vlan */ 2149 #define PF_NUM_IGNORE 255 2150 u8 nv_flags; 2151 u8 rsvd2; 2152 __le16 nv_port; /* vxlan/gre port */ 2153 u32 rsvd3[19]; 2154 } __packed; 2155 2156 struct be_pcie_res_desc { 2157 struct be_res_desc_hdr hdr; 2158 u8 rsvd0; 2159 u8 flags; 2160 u16 rsvd1; 2161 u8 pf_num; 2162 u8 rsvd2; 2163 u32 rsvd3; 2164 u8 sriov_state; 2165 u8 pf_state; 2166 u8 pf_type; 2167 u8 rsvd4; 2168 u16 num_vfs; 2169 u16 rsvd5; 2170 u32 rsvd6[17]; 2171 } __packed; 2172 2173 struct be_nic_res_desc { 2174 struct be_res_desc_hdr hdr; 2175 u8 rsvd1; 2176 2177 #define QUN_SHIFT 4 /* QoS is in absolute units */ 2178 u8 flags; 2179 u8 vf_num; 2180 u8 rsvd2; 2181 u8 pf_num; 2182 u8 rsvd3; 2183 u16 unicast_mac_count; 2184 u8 rsvd4[6]; 2185 u16 mcc_count; 2186 u16 vlan_count; 2187 u16 mcast_mac_count; 2188 u16 txq_count; 2189 u16 rq_count; 2190 u16 rssq_count; 2191 u16 lro_count; 2192 u16 cq_count; 2193 u16 toe_conn_count; 2194 u16 eq_count; 2195 u16 vlan_id; 2196 u16 iface_count; 2197 u32 cap_flags; 2198 u8 link_param; 2199 u8 rsvd6; 2200 u16 channel_id_param; 2201 u32 bw_min; 2202 u32 bw_max; 2203 u8 acpi_params; 2204 u8 wol_param; 2205 u16 rsvd7; 2206 u16 tunnel_iface_count; 2207 u16 direct_tenant_iface_count; 2208 u32 rsvd8[6]; 2209 } __packed; 2210 2211 /************ Multi-Channel type ***********/ 2212 enum mc_type { 2213 MC_NONE = 0x01, 2214 UMC = 0x02, 2215 FLEX10 = 0x03, 2216 vNIC1 = 0x04, 2217 nPAR = 0x05, 2218 UFP = 0x06, 2219 vNIC2 = 0x07 2220 }; 2221 2222 /* Is BE in a multi-channel mode */ 2223 static inline bool be_is_mc(struct be_adapter *adapter) 2224 { 2225 return adapter->mc_type > MC_NONE; 2226 } 2227 2228 struct be_cmd_req_get_func_config { 2229 struct be_cmd_req_hdr hdr; 2230 }; 2231 2232 struct be_cmd_resp_get_func_config { 2233 struct be_cmd_resp_hdr hdr; 2234 u32 desc_count; 2235 u8 func_param[MAX_RESOURCE_DESC * RESOURCE_DESC_SIZE_V1]; 2236 }; 2237 2238 enum { 2239 RESOURCE_LIMITS, 2240 RESOURCE_MODIFIABLE 2241 }; 2242 2243 struct be_cmd_req_get_profile_config { 2244 struct be_cmd_req_hdr hdr; 2245 u8 rsvd; 2246 #define ACTIVE_PROFILE_TYPE 0x2 2247 #define QUERY_MODIFIABLE_FIELDS_TYPE BIT(3) 2248 u8 type; 2249 u16 rsvd1; 2250 }; 2251 2252 struct be_cmd_resp_get_profile_config { 2253 struct be_cmd_resp_hdr hdr; 2254 __le16 desc_count; 2255 u16 rsvd; 2256 u8 func_param[MAX_RESOURCE_DESC * RESOURCE_DESC_SIZE_V1]; 2257 }; 2258 2259 #define FIELD_MODIFIABLE 0xFFFF 2260 struct be_cmd_req_set_profile_config { 2261 struct be_cmd_req_hdr hdr; 2262 u32 rsvd; 2263 u32 desc_count; 2264 u8 desc[2 * RESOURCE_DESC_SIZE_V1]; 2265 } __packed; 2266 2267 struct be_cmd_req_get_active_profile { 2268 struct be_cmd_req_hdr hdr; 2269 u32 rsvd; 2270 } __packed; 2271 2272 struct be_cmd_resp_get_active_profile { 2273 struct be_cmd_resp_hdr hdr; 2274 u16 active_profile_id; 2275 u16 next_profile_id; 2276 } __packed; 2277 2278 struct be_cmd_enable_disable_vf { 2279 struct be_cmd_req_hdr hdr; 2280 u8 enable; 2281 u8 rsvd[3]; 2282 }; 2283 2284 struct be_cmd_req_intr_set { 2285 struct be_cmd_req_hdr hdr; 2286 u8 intr_enabled; 2287 u8 rsvd[3]; 2288 }; 2289 2290 static inline bool check_privilege(struct be_adapter *adapter, u32 flags) 2291 { 2292 return flags & adapter->cmd_privileges ? true : false; 2293 } 2294 2295 /************** Get IFACE LIST *******************/ 2296 struct be_if_desc { 2297 u32 if_id; 2298 u32 cap_flags; 2299 u32 en_flags; 2300 }; 2301 2302 struct be_cmd_req_get_iface_list { 2303 struct be_cmd_req_hdr hdr; 2304 }; 2305 2306 struct be_cmd_resp_get_iface_list { 2307 struct be_cmd_req_hdr hdr; 2308 u32 if_cnt; 2309 struct be_if_desc if_desc; 2310 }; 2311 2312 /*************** Set logical link ********************/ 2313 #define PLINK_ENABLE BIT(0) 2314 #define PLINK_TRACK BIT(8) 2315 struct be_cmd_req_set_ll_link { 2316 struct be_cmd_req_hdr hdr; 2317 u32 link_config; /* Bit 0: UP_DOWN, Bit 9: PLINK */ 2318 }; 2319 2320 /************** Manage IFACE Filters *******************/ 2321 #define OP_CONVERT_NORMAL_TO_TUNNEL 0 2322 #define OP_CONVERT_TUNNEL_TO_NORMAL 1 2323 2324 struct be_cmd_req_manage_iface_filters { 2325 struct be_cmd_req_hdr hdr; 2326 u8 op; 2327 u8 rsvd0; 2328 u8 flags; 2329 u8 rsvd1; 2330 u32 tunnel_iface_id; 2331 u32 target_iface_id; 2332 u8 mac[6]; 2333 u16 vlan_tag; 2334 u32 tenant_id; 2335 u32 filter_id; 2336 u32 cap_flags; 2337 u32 cap_control_flags; 2338 } __packed; 2339 2340 int be_pci_fnum_get(struct be_adapter *adapter); 2341 int be_fw_wait_ready(struct be_adapter *adapter); 2342 int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr, 2343 bool permanent, u32 if_handle, u32 pmac_id); 2344 int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr, u32 if_id, 2345 u32 *pmac_id, u32 domain); 2346 int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, int pmac_id, 2347 u32 domain); 2348 int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags, 2349 u32 *if_handle, u32 domain); 2350 int be_cmd_if_destroy(struct be_adapter *adapter, int if_handle, u32 domain); 2351 int be_cmd_eq_create(struct be_adapter *adapter, struct be_eq_obj *eqo); 2352 int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq, 2353 struct be_queue_info *eq, bool no_delay, 2354 int num_cqe_dma_coalesce); 2355 int be_cmd_mccq_create(struct be_adapter *adapter, struct be_queue_info *mccq, 2356 struct be_queue_info *cq); 2357 int be_cmd_txq_create(struct be_adapter *adapter, struct be_tx_obj *txo); 2358 int be_cmd_rxq_create(struct be_adapter *adapter, struct be_queue_info *rxq, 2359 u16 cq_id, u16 frag_size, u32 if_id, u32 rss, u8 *rss_id); 2360 int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q, 2361 int type); 2362 int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q); 2363 int be_cmd_link_status_query(struct be_adapter *adapter, u16 *link_speed, 2364 u8 *link_status, u32 dom); 2365 int be_cmd_reset(struct be_adapter *adapter); 2366 int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd); 2367 int lancer_cmd_get_pport_stats(struct be_adapter *adapter, 2368 struct be_dma_mem *nonemb_cmd); 2369 int be_cmd_get_fw_ver(struct be_adapter *adapter); 2370 int be_cmd_modify_eqd(struct be_adapter *adapter, struct be_set_eqd *, int num); 2371 int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array, 2372 u32 num, u32 domain); 2373 int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 status); 2374 int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc); 2375 int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc); 2376 int be_cmd_query_fw_cfg(struct be_adapter *adapter); 2377 int be_cmd_reset_function(struct be_adapter *adapter); 2378 int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable, 2379 u32 rss_hash_opts, u16 table_size, const u8 *rss_hkey); 2380 int be_process_mcc(struct be_adapter *adapter); 2381 int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num, u8 beacon, 2382 u8 status, u8 state); 2383 int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, 2384 u32 *state); 2385 int be_cmd_read_port_transceiver_data(struct be_adapter *adapter, 2386 u8 page_num, u8 *data); 2387 int be_cmd_query_cable_type(struct be_adapter *adapter); 2388 int be_cmd_query_sfp_info(struct be_adapter *adapter); 2389 int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd, 2390 u32 data_size, u32 data_offset, const char *obj_name, 2391 u32 *data_read, u32 *eof, u8 *addn_status); 2392 int lancer_fw_download(struct be_adapter *adapter, const struct firmware *fw); 2393 int be_fw_download(struct be_adapter *adapter, const struct firmware *fw); 2394 int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac, 2395 struct be_dma_mem *nonemb_cmd); 2396 int be_cmd_fw_init(struct be_adapter *adapter); 2397 int be_cmd_fw_clean(struct be_adapter *adapter); 2398 void be_async_mcc_enable(struct be_adapter *adapter); 2399 void be_async_mcc_disable(struct be_adapter *adapter); 2400 int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num, 2401 u32 loopback_type, u32 pkt_size, u32 num_pkts, 2402 u64 pattern); 2403 int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern, u32 byte_cnt, 2404 struct be_dma_mem *cmd); 2405 int be_cmd_get_seeprom_data(struct be_adapter *adapter, 2406 struct be_dma_mem *nonemb_cmd); 2407 int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num, 2408 u8 loopback_type, u8 enable); 2409 int be_cmd_get_phy_info(struct be_adapter *adapter); 2410 int be_cmd_config_qos(struct be_adapter *adapter, u32 max_rate, 2411 u16 link_speed, u8 domain); 2412 void be_detect_error(struct be_adapter *adapter); 2413 int be_cmd_get_die_temperature(struct be_adapter *adapter); 2414 int be_cmd_get_cntl_attributes(struct be_adapter *adapter); 2415 int be_cmd_get_fat_dump_len(struct be_adapter *adapter, u32 *dump_size); 2416 int be_cmd_get_fat_dump(struct be_adapter *adapter, u32 buf_len, void *buf); 2417 int be_cmd_req_native_mode(struct be_adapter *adapter); 2418 int be_cmd_get_fn_privileges(struct be_adapter *adapter, u32 *privilege, 2419 u32 domain); 2420 int be_cmd_set_fn_privileges(struct be_adapter *adapter, u32 privileges, 2421 u32 vf_num); 2422 int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac, 2423 bool *pmac_id_active, u32 *pmac_id, 2424 u32 if_handle, u8 domain); 2425 int be_cmd_get_active_mac(struct be_adapter *adapter, u32 pmac_id, u8 *mac, 2426 u32 if_handle, bool active, u32 domain); 2427 int be_cmd_get_perm_mac(struct be_adapter *adapter, u8 *mac); 2428 int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array, u8 mac_count, 2429 u32 domain); 2430 int be_cmd_set_mac(struct be_adapter *adapter, u8 *mac, int if_id, u32 dom); 2431 int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid, u32 domain, 2432 u16 intf_id, u16 hsw_mode, u8 spoofchk); 2433 int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid, u32 domain, 2434 u16 intf_id, u8 *mode, bool *spoofchk); 2435 int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter); 2436 int be_cmd_set_fw_log_level(struct be_adapter *adapter, u32 level); 2437 int be_cmd_get_fw_log_level(struct be_adapter *adapter); 2438 int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter, 2439 struct be_dma_mem *cmd); 2440 int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter, 2441 struct be_dma_mem *cmd, 2442 struct be_fat_conf_params *cfgs); 2443 int lancer_physdev_ctrl(struct be_adapter *adapter, u32 mask); 2444 int lancer_initiate_dump(struct be_adapter *adapter); 2445 int lancer_delete_dump(struct be_adapter *adapter); 2446 bool dump_present(struct be_adapter *adapter); 2447 int lancer_test_and_set_rdy_state(struct be_adapter *adapter); 2448 int be_cmd_query_port_name(struct be_adapter *adapter); 2449 int be_cmd_get_func_config(struct be_adapter *adapter, 2450 struct be_resources *res); 2451 int be_cmd_get_profile_config(struct be_adapter *adapter, 2452 struct be_resources *res, u8 query, u8 domain); 2453 int be_cmd_get_active_profile(struct be_adapter *adapter, u16 *profile); 2454 int be_cmd_get_if_id(struct be_adapter *adapter, struct be_vf_cfg *vf_cfg, 2455 int vf_num); 2456 int be_cmd_enable_vf(struct be_adapter *adapter, u8 domain); 2457 int be_cmd_intr_set(struct be_adapter *adapter, bool intr_enable); 2458 int be_cmd_set_logical_link_config(struct be_adapter *adapter, 2459 int link_state, u8 domain); 2460 int be_cmd_set_vxlan_port(struct be_adapter *adapter, __be16 port); 2461 int be_cmd_manage_iface(struct be_adapter *adapter, u32 iface, u8 op); 2462 int be_cmd_set_sriov_config(struct be_adapter *adapter, 2463 struct be_resources res, u16 num_vfs, 2464 u16 num_vf_qs); 2465