1 /* 2 * Copyright (C) 2005 - 2016 Broadcom 3 * All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License version 2 7 * as published by the Free Software Foundation. The full GNU General 8 * Public License is included in this distribution in the file called COPYING. 9 * 10 * Contact Information: 11 * linux-drivers@emulex.com 12 * 13 * Emulex 14 * 3333 Susan Street 15 * Costa Mesa, CA 92626 16 */ 17 18 /* 19 * The driver sends configuration and managements command requests to the 20 * firmware in the BE. These requests are communicated to the processor 21 * using Work Request Blocks (WRBs) submitted to the MCC-WRB ring or via one 22 * WRB inside a MAILBOX. 23 * The commands are serviced by the ARM processor in the BladeEngine's MPU. 24 */ 25 26 struct be_sge { 27 u32 pa_lo; 28 u32 pa_hi; 29 u32 len; 30 }; 31 32 #define MCC_WRB_EMBEDDED_MASK 1 /* bit 0 of dword 0*/ 33 #define MCC_WRB_SGE_CNT_SHIFT 3 /* bits 3 - 7 of dword 0 */ 34 #define MCC_WRB_SGE_CNT_MASK 0x1F /* bits 3 - 7 of dword 0 */ 35 struct be_mcc_wrb { 36 u32 embedded; /* dword 0 */ 37 u32 payload_length; /* dword 1 */ 38 u32 tag0; /* dword 2 */ 39 u32 tag1; /* dword 3 */ 40 u32 rsvd; /* dword 4 */ 41 union { 42 u8 embedded_payload[236]; /* used by embedded cmds */ 43 struct be_sge sgl[19]; /* used by non-embedded cmds */ 44 } payload; 45 }; 46 47 #define CQE_FLAGS_VALID_MASK BIT(31) 48 #define CQE_FLAGS_ASYNC_MASK BIT(30) 49 #define CQE_FLAGS_COMPLETED_MASK BIT(28) 50 #define CQE_FLAGS_CONSUMED_MASK BIT(27) 51 52 /* Completion Status */ 53 enum mcc_base_status { 54 MCC_STATUS_SUCCESS = 0, 55 MCC_STATUS_FAILED = 1, 56 MCC_STATUS_ILLEGAL_REQUEST = 2, 57 MCC_STATUS_ILLEGAL_FIELD = 3, 58 MCC_STATUS_INSUFFICIENT_BUFFER = 4, 59 MCC_STATUS_UNAUTHORIZED_REQUEST = 5, 60 MCC_STATUS_NOT_SUPPORTED = 66, 61 MCC_STATUS_FEATURE_NOT_SUPPORTED = 68, 62 MCC_STATUS_INVALID_LENGTH = 116 63 }; 64 65 /* Additional status */ 66 enum mcc_addl_status { 67 MCC_ADDL_STATUS_INSUFFICIENT_RESOURCES = 0x16, 68 MCC_ADDL_STATUS_FLASH_IMAGE_CRC_MISMATCH = 0x4d, 69 MCC_ADDL_STATUS_TOO_MANY_INTERFACES = 0x4a, 70 MCC_ADDL_STATUS_INSUFFICIENT_VLANS = 0xab, 71 MCC_ADDL_STATUS_INVALID_SIGNATURE = 0x56, 72 MCC_ADDL_STATUS_MISSING_SIGNATURE = 0x57, 73 MCC_ADDL_STATUS_INSUFFICIENT_PRIVILEGES = 0x60 74 }; 75 76 #define CQE_BASE_STATUS_MASK 0xFFFF 77 #define CQE_BASE_STATUS_SHIFT 0 /* bits 0 - 15 */ 78 #define CQE_ADDL_STATUS_MASK 0xFF 79 #define CQE_ADDL_STATUS_SHIFT 16 /* bits 16 - 31 */ 80 81 #define base_status(status) \ 82 ((enum mcc_base_status) \ 83 (status > 0 ? (status & CQE_BASE_STATUS_MASK) : 0)) 84 #define addl_status(status) \ 85 ((enum mcc_addl_status) \ 86 (status > 0 ? (status >> CQE_ADDL_STATUS_SHIFT) & \ 87 CQE_ADDL_STATUS_MASK : 0)) 88 89 struct be_mcc_compl { 90 u32 status; /* dword 0 */ 91 u32 tag0; /* dword 1 */ 92 u32 tag1; /* dword 2 */ 93 u32 flags; /* dword 3 */ 94 }; 95 96 /* When the async bit of mcc_compl flags is set, flags 97 * is interpreted as follows: 98 */ 99 #define ASYNC_EVENT_CODE_SHIFT 8 /* bits 8 - 15 */ 100 #define ASYNC_EVENT_CODE_MASK 0xFF 101 #define ASYNC_EVENT_TYPE_SHIFT 16 102 #define ASYNC_EVENT_TYPE_MASK 0xFF 103 #define ASYNC_EVENT_CODE_LINK_STATE 0x1 104 #define ASYNC_EVENT_CODE_GRP_5 0x5 105 #define ASYNC_EVENT_QOS_SPEED 0x1 106 #define ASYNC_EVENT_COS_PRIORITY 0x2 107 #define ASYNC_EVENT_PVID_STATE 0x3 108 #define ASYNC_EVENT_CODE_QNQ 0x6 109 #define ASYNC_DEBUG_EVENT_TYPE_QNQ 1 110 #define ASYNC_EVENT_CODE_SLIPORT 0x11 111 #define ASYNC_EVENT_PORT_MISCONFIG 0x9 112 #define ASYNC_EVENT_FW_CONTROL 0x5 113 114 enum { 115 LINK_DOWN = 0x0, 116 LINK_UP = 0x1 117 }; 118 #define LINK_STATUS_MASK 0x1 119 #define LOGICAL_LINK_STATUS_MASK 0x2 120 121 /* When the event code of compl->flags is link-state, the mcc_compl 122 * must be interpreted as follows 123 */ 124 struct be_async_event_link_state { 125 u8 physical_port; 126 u8 port_link_status; 127 u8 port_duplex; 128 u8 port_speed; 129 u8 port_fault; 130 u8 rsvd0[7]; 131 u32 flags; 132 } __packed; 133 134 /* When the event code of compl->flags is GRP-5 and event_type is QOS_SPEED 135 * the mcc_compl must be interpreted as follows 136 */ 137 struct be_async_event_grp5_qos_link_speed { 138 u8 physical_port; 139 u8 rsvd[5]; 140 u16 qos_link_speed; 141 u32 event_tag; 142 u32 flags; 143 } __packed; 144 145 /* When the event code of compl->flags is GRP5 and event type is 146 * CoS-Priority, the mcc_compl must be interpreted as follows 147 */ 148 struct be_async_event_grp5_cos_priority { 149 u8 physical_port; 150 u8 available_priority_bmap; 151 u8 reco_default_priority; 152 u8 valid; 153 u8 rsvd0; 154 u8 event_tag; 155 u32 flags; 156 } __packed; 157 158 /* When the event code of compl->flags is GRP5 and event type is 159 * PVID state, the mcc_compl must be interpreted as follows 160 */ 161 struct be_async_event_grp5_pvid_state { 162 u8 enabled; 163 u8 rsvd0; 164 u16 tag; 165 u32 event_tag; 166 u32 rsvd1; 167 u32 flags; 168 } __packed; 169 170 /* async event indicating outer VLAN tag in QnQ */ 171 struct be_async_event_qnq { 172 u8 valid; /* Indicates if outer VLAN is valid */ 173 u8 rsvd0; 174 u16 vlan_tag; 175 u32 event_tag; 176 u8 rsvd1[4]; 177 u32 flags; 178 } __packed; 179 180 enum { 181 BE_PHY_FUNCTIONAL = 0, 182 BE_PHY_NOT_PRESENT = 1, 183 BE_PHY_DIFF_MEDIA = 2, 184 BE_PHY_INCOMPATIBLE = 3, 185 BE_PHY_UNQUALIFIED = 4, 186 BE_PHY_UNCERTIFIED = 5 187 }; 188 189 #define PHY_STATE_MSG_SEVERITY 0x6 190 #define PHY_STATE_OPER 0x1 191 #define PHY_STATE_INFO_VALID 0x80 192 #define PHY_STATE_OPER_MSG_NONE 0x2 193 #define DEFAULT_MSG_SEVERITY 0x1 194 195 #define be_phy_state_unknown(phy_state) (phy_state > BE_PHY_UNCERTIFIED) 196 #define be_phy_unqualified(phy_state) \ 197 (phy_state == BE_PHY_UNQUALIFIED || \ 198 phy_state == BE_PHY_UNCERTIFIED) 199 #define be_phy_misconfigured(phy_state) \ 200 (phy_state == BE_PHY_INCOMPATIBLE || \ 201 phy_state == BE_PHY_UNQUALIFIED || \ 202 phy_state == BE_PHY_UNCERTIFIED) 203 204 extern const char * const be_misconfig_evt_port_state[]; 205 206 /* async event indicating misconfigured port */ 207 struct be_async_event_misconfig_port { 208 /* DATA_WORD1: 209 * phy state of port 0: bits 7 - 0 210 * phy state of port 1: bits 15 - 8 211 * phy state of port 2: bits 23 - 16 212 * phy state of port 3: bits 31 - 24 213 */ 214 u32 event_data_word1; 215 /* DATA_WORD2: 216 * phy state info of port 0: bits 7 - 0 217 * phy state info of port 1: bits 15 - 8 218 * phy state info of port 2: bits 23 - 16 219 * phy state info of port 3: bits 31 - 24 220 * 221 * PHY STATE INFO: 222 * Link operability :bit 0 223 * Message severity :bit 2 - 1 224 * Rsvd :bits 6 - 3 225 * phy state info valid :bit 7 226 */ 227 u32 event_data_word2; 228 u32 rsvd0; 229 u32 flags; 230 } __packed; 231 232 #define BMC_FILT_BROADCAST_ARP BIT(0) 233 #define BMC_FILT_BROADCAST_DHCP_CLIENT BIT(1) 234 #define BMC_FILT_BROADCAST_DHCP_SERVER BIT(2) 235 #define BMC_FILT_BROADCAST_NET_BIOS BIT(3) 236 #define BMC_FILT_BROADCAST BIT(7) 237 #define BMC_FILT_MULTICAST_IPV6_NEIGH_ADVER BIT(8) 238 #define BMC_FILT_MULTICAST_IPV6_RA BIT(9) 239 #define BMC_FILT_MULTICAST_IPV6_RAS BIT(10) 240 #define BMC_FILT_MULTICAST BIT(15) 241 struct be_async_fw_control { 242 u32 event_data_word1; 243 u32 event_data_word2; 244 u32 evt_tag; 245 u32 event_data_word4; 246 } __packed; 247 248 struct be_mcc_mailbox { 249 struct be_mcc_wrb wrb; 250 struct be_mcc_compl compl; 251 }; 252 253 #define CMD_SUBSYSTEM_COMMON 0x1 254 #define CMD_SUBSYSTEM_ETH 0x3 255 #define CMD_SUBSYSTEM_LOWLEVEL 0xb 256 257 #define OPCODE_COMMON_NTWK_MAC_QUERY 1 258 #define OPCODE_COMMON_NTWK_MAC_SET 2 259 #define OPCODE_COMMON_NTWK_MULTICAST_SET 3 260 #define OPCODE_COMMON_NTWK_VLAN_CONFIG 4 261 #define OPCODE_COMMON_NTWK_LINK_STATUS_QUERY 5 262 #define OPCODE_COMMON_READ_FLASHROM 6 263 #define OPCODE_COMMON_WRITE_FLASHROM 7 264 #define OPCODE_COMMON_CQ_CREATE 12 265 #define OPCODE_COMMON_EQ_CREATE 13 266 #define OPCODE_COMMON_MCC_CREATE 21 267 #define OPCODE_COMMON_SET_QOS 28 268 #define OPCODE_COMMON_MCC_CREATE_EXT 90 269 #define OPCODE_COMMON_SEEPROM_READ 30 270 #define OPCODE_COMMON_GET_CNTL_ATTRIBUTES 32 271 #define OPCODE_COMMON_NTWK_RX_FILTER 34 272 #define OPCODE_COMMON_GET_FW_VERSION 35 273 #define OPCODE_COMMON_SET_FLOW_CONTROL 36 274 #define OPCODE_COMMON_GET_FLOW_CONTROL 37 275 #define OPCODE_COMMON_SET_FRAME_SIZE 39 276 #define OPCODE_COMMON_MODIFY_EQ_DELAY 41 277 #define OPCODE_COMMON_FIRMWARE_CONFIG 42 278 #define OPCODE_COMMON_NTWK_INTERFACE_CREATE 50 279 #define OPCODE_COMMON_NTWK_INTERFACE_DESTROY 51 280 #define OPCODE_COMMON_MCC_DESTROY 53 281 #define OPCODE_COMMON_CQ_DESTROY 54 282 #define OPCODE_COMMON_EQ_DESTROY 55 283 #define OPCODE_COMMON_QUERY_FIRMWARE_CONFIG 58 284 #define OPCODE_COMMON_NTWK_PMAC_ADD 59 285 #define OPCODE_COMMON_NTWK_PMAC_DEL 60 286 #define OPCODE_COMMON_FUNCTION_RESET 61 287 #define OPCODE_COMMON_MANAGE_FAT 68 288 #define OPCODE_COMMON_ENABLE_DISABLE_BEACON 69 289 #define OPCODE_COMMON_GET_BEACON_STATE 70 290 #define OPCODE_COMMON_READ_TRANSRECV_DATA 73 291 #define OPCODE_COMMON_GET_PORT_NAME 77 292 #define OPCODE_COMMON_SET_LOGICAL_LINK_CONFIG 80 293 #define OPCODE_COMMON_SET_INTERRUPT_ENABLE 89 294 #define OPCODE_COMMON_SET_FN_PRIVILEGES 100 295 #define OPCODE_COMMON_GET_PHY_DETAILS 102 296 #define OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP 103 297 #define OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES 121 298 #define OPCODE_COMMON_GET_EXT_FAT_CAPABILITIES 125 299 #define OPCODE_COMMON_SET_EXT_FAT_CAPABILITIES 126 300 #define OPCODE_COMMON_GET_MAC_LIST 147 301 #define OPCODE_COMMON_SET_MAC_LIST 148 302 #define OPCODE_COMMON_GET_HSW_CONFIG 152 303 #define OPCODE_COMMON_GET_FUNC_CONFIG 160 304 #define OPCODE_COMMON_GET_PROFILE_CONFIG 164 305 #define OPCODE_COMMON_SET_PROFILE_CONFIG 165 306 #define OPCODE_COMMON_GET_ACTIVE_PROFILE 167 307 #define OPCODE_COMMON_SET_HSW_CONFIG 153 308 #define OPCODE_COMMON_GET_FN_PRIVILEGES 170 309 #define OPCODE_COMMON_READ_OBJECT 171 310 #define OPCODE_COMMON_WRITE_OBJECT 172 311 #define OPCODE_COMMON_DELETE_OBJECT 174 312 #define OPCODE_COMMON_SET_FEATURES 191 313 #define OPCODE_COMMON_MANAGE_IFACE_FILTERS 193 314 #define OPCODE_COMMON_GET_IFACE_LIST 194 315 #define OPCODE_COMMON_ENABLE_DISABLE_VF 196 316 317 #define OPCODE_ETH_RSS_CONFIG 1 318 #define OPCODE_ETH_ACPI_CONFIG 2 319 #define OPCODE_ETH_PROMISCUOUS 3 320 #define OPCODE_ETH_GET_STATISTICS 4 321 #define OPCODE_ETH_TX_CREATE 7 322 #define OPCODE_ETH_RX_CREATE 8 323 #define OPCODE_ETH_TX_DESTROY 9 324 #define OPCODE_ETH_RX_DESTROY 10 325 #define OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG 12 326 #define OPCODE_ETH_GET_PPORT_STATS 18 327 328 #define OPCODE_LOWLEVEL_HOST_DDR_DMA 17 329 #define OPCODE_LOWLEVEL_LOOPBACK_TEST 18 330 #define OPCODE_LOWLEVEL_SET_LOOPBACK_MODE 19 331 332 struct be_cmd_req_hdr { 333 u8 opcode; /* dword 0 */ 334 u8 subsystem; /* dword 0 */ 335 u8 port_number; /* dword 0 */ 336 u8 domain; /* dword 0 */ 337 u32 timeout; /* dword 1 */ 338 u32 request_length; /* dword 2 */ 339 u8 version; /* dword 3 */ 340 u8 rsvd[3]; /* dword 3 */ 341 }; 342 343 #define RESP_HDR_INFO_OPCODE_SHIFT 0 /* bits 0 - 7 */ 344 #define RESP_HDR_INFO_SUBSYS_SHIFT 8 /* bits 8 - 15 */ 345 struct be_cmd_resp_hdr { 346 u8 opcode; /* dword 0 */ 347 u8 subsystem; /* dword 0 */ 348 u8 rsvd[2]; /* dword 0 */ 349 u8 base_status; /* dword 1 */ 350 u8 addl_status; /* dword 1 */ 351 u8 rsvd1[2]; /* dword 1 */ 352 u32 response_length; /* dword 2 */ 353 u32 actual_resp_len; /* dword 3 */ 354 }; 355 356 struct phys_addr { 357 u32 lo; 358 u32 hi; 359 }; 360 361 /************************** 362 * BE Command definitions * 363 **************************/ 364 365 /* Pseudo amap definition in which each bit of the actual structure is defined 366 * as a byte: used to calculate offset/shift/mask of each field */ 367 struct amap_eq_context { 368 u8 cidx[13]; /* dword 0*/ 369 u8 rsvd0[3]; /* dword 0*/ 370 u8 epidx[13]; /* dword 0*/ 371 u8 valid; /* dword 0*/ 372 u8 rsvd1; /* dword 0*/ 373 u8 size; /* dword 0*/ 374 u8 pidx[13]; /* dword 1*/ 375 u8 rsvd2[3]; /* dword 1*/ 376 u8 pd[10]; /* dword 1*/ 377 u8 count[3]; /* dword 1*/ 378 u8 solevent; /* dword 1*/ 379 u8 stalled; /* dword 1*/ 380 u8 armed; /* dword 1*/ 381 u8 rsvd3[4]; /* dword 2*/ 382 u8 func[8]; /* dword 2*/ 383 u8 rsvd4; /* dword 2*/ 384 u8 delaymult[10]; /* dword 2*/ 385 u8 rsvd5[2]; /* dword 2*/ 386 u8 phase[2]; /* dword 2*/ 387 u8 nodelay; /* dword 2*/ 388 u8 rsvd6[4]; /* dword 2*/ 389 u8 rsvd7[32]; /* dword 3*/ 390 } __packed; 391 392 struct be_cmd_req_eq_create { 393 struct be_cmd_req_hdr hdr; 394 u16 num_pages; /* sword */ 395 u16 rsvd0; /* sword */ 396 u8 context[sizeof(struct amap_eq_context) / 8]; 397 struct phys_addr pages[8]; 398 } __packed; 399 400 struct be_cmd_resp_eq_create { 401 struct be_cmd_resp_hdr resp_hdr; 402 u16 eq_id; /* sword */ 403 u16 msix_idx; /* available only in v2 */ 404 } __packed; 405 406 /******************** Mac query ***************************/ 407 enum { 408 MAC_ADDRESS_TYPE_STORAGE = 0x0, 409 MAC_ADDRESS_TYPE_NETWORK = 0x1, 410 MAC_ADDRESS_TYPE_PD = 0x2, 411 MAC_ADDRESS_TYPE_MANAGEMENT = 0x3 412 }; 413 414 struct mac_addr { 415 u16 size_of_struct; 416 u8 addr[ETH_ALEN]; 417 } __packed; 418 419 struct be_cmd_req_mac_query { 420 struct be_cmd_req_hdr hdr; 421 u8 type; 422 u8 permanent; 423 u16 if_id; 424 u32 pmac_id; 425 } __packed; 426 427 struct be_cmd_resp_mac_query { 428 struct be_cmd_resp_hdr hdr; 429 struct mac_addr mac; 430 }; 431 432 /******************** PMac Add ***************************/ 433 struct be_cmd_req_pmac_add { 434 struct be_cmd_req_hdr hdr; 435 u32 if_id; 436 u8 mac_address[ETH_ALEN]; 437 u8 rsvd0[2]; 438 } __packed; 439 440 struct be_cmd_resp_pmac_add { 441 struct be_cmd_resp_hdr hdr; 442 u32 pmac_id; 443 }; 444 445 /******************** PMac Del ***************************/ 446 struct be_cmd_req_pmac_del { 447 struct be_cmd_req_hdr hdr; 448 u32 if_id; 449 u32 pmac_id; 450 }; 451 452 /******************** Create CQ ***************************/ 453 /* Pseudo amap definition in which each bit of the actual structure is defined 454 * as a byte: used to calculate offset/shift/mask of each field */ 455 struct amap_cq_context_be { 456 u8 cidx[11]; /* dword 0*/ 457 u8 rsvd0; /* dword 0*/ 458 u8 coalescwm[2]; /* dword 0*/ 459 u8 nodelay; /* dword 0*/ 460 u8 epidx[11]; /* dword 0*/ 461 u8 rsvd1; /* dword 0*/ 462 u8 count[2]; /* dword 0*/ 463 u8 valid; /* dword 0*/ 464 u8 solevent; /* dword 0*/ 465 u8 eventable; /* dword 0*/ 466 u8 pidx[11]; /* dword 1*/ 467 u8 rsvd2; /* dword 1*/ 468 u8 pd[10]; /* dword 1*/ 469 u8 eqid[8]; /* dword 1*/ 470 u8 stalled; /* dword 1*/ 471 u8 armed; /* dword 1*/ 472 u8 rsvd3[4]; /* dword 2*/ 473 u8 func[8]; /* dword 2*/ 474 u8 rsvd4[20]; /* dword 2*/ 475 u8 rsvd5[32]; /* dword 3*/ 476 } __packed; 477 478 struct amap_cq_context_v2 { 479 u8 rsvd0[12]; /* dword 0*/ 480 u8 coalescwm[2]; /* dword 0*/ 481 u8 nodelay; /* dword 0*/ 482 u8 rsvd1[12]; /* dword 0*/ 483 u8 count[2]; /* dword 0*/ 484 u8 valid; /* dword 0*/ 485 u8 rsvd2; /* dword 0*/ 486 u8 eventable; /* dword 0*/ 487 u8 eqid[16]; /* dword 1*/ 488 u8 rsvd3[15]; /* dword 1*/ 489 u8 armed; /* dword 1*/ 490 u8 rsvd4[32]; /* dword 2*/ 491 u8 rsvd5[32]; /* dword 3*/ 492 } __packed; 493 494 struct be_cmd_req_cq_create { 495 struct be_cmd_req_hdr hdr; 496 u16 num_pages; 497 u8 page_size; 498 u8 rsvd0; 499 u8 context[sizeof(struct amap_cq_context_be) / 8]; 500 struct phys_addr pages[8]; 501 } __packed; 502 503 504 struct be_cmd_resp_cq_create { 505 struct be_cmd_resp_hdr hdr; 506 u16 cq_id; 507 u16 rsvd0; 508 } __packed; 509 510 struct be_cmd_req_get_fat { 511 struct be_cmd_req_hdr hdr; 512 u32 fat_operation; 513 u32 read_log_offset; 514 u32 read_log_length; 515 u32 data_buffer_size; 516 u32 data_buffer[1]; 517 } __packed; 518 519 struct be_cmd_resp_get_fat { 520 struct be_cmd_resp_hdr hdr; 521 u32 log_size; 522 u32 read_log_length; 523 u32 rsvd[2]; 524 u32 data_buffer[1]; 525 } __packed; 526 527 528 /******************** Create MCCQ ***************************/ 529 /* Pseudo amap definition in which each bit of the actual structure is defined 530 * as a byte: used to calculate offset/shift/mask of each field */ 531 struct amap_mcc_context_be { 532 u8 con_index[14]; 533 u8 rsvd0[2]; 534 u8 ring_size[4]; 535 u8 fetch_wrb; 536 u8 fetch_r2t; 537 u8 cq_id[10]; 538 u8 prod_index[14]; 539 u8 fid[8]; 540 u8 pdid[9]; 541 u8 valid; 542 u8 rsvd1[32]; 543 u8 rsvd2[32]; 544 } __packed; 545 546 struct amap_mcc_context_v1 { 547 u8 async_cq_id[16]; 548 u8 ring_size[4]; 549 u8 rsvd0[12]; 550 u8 rsvd1[31]; 551 u8 valid; 552 u8 async_cq_valid[1]; 553 u8 rsvd2[31]; 554 u8 rsvd3[32]; 555 } __packed; 556 557 struct be_cmd_req_mcc_create { 558 struct be_cmd_req_hdr hdr; 559 u16 num_pages; 560 u16 cq_id; 561 u8 context[sizeof(struct amap_mcc_context_be) / 8]; 562 struct phys_addr pages[8]; 563 } __packed; 564 565 struct be_cmd_req_mcc_ext_create { 566 struct be_cmd_req_hdr hdr; 567 u16 num_pages; 568 u16 cq_id; 569 u32 async_event_bitmap[1]; 570 u8 context[sizeof(struct amap_mcc_context_v1) / 8]; 571 struct phys_addr pages[8]; 572 } __packed; 573 574 struct be_cmd_resp_mcc_create { 575 struct be_cmd_resp_hdr hdr; 576 u16 id; 577 u16 rsvd0; 578 } __packed; 579 580 /******************** Create TxQ ***************************/ 581 #define BE_ETH_TX_RING_TYPE_STANDARD 2 582 #define BE_ULP1_NUM 1 583 584 struct be_cmd_req_eth_tx_create { 585 struct be_cmd_req_hdr hdr; 586 u8 num_pages; 587 u8 ulp_num; 588 u16 type; 589 u16 if_id; 590 u8 queue_size; 591 u8 rsvd0; 592 u32 rsvd1; 593 u16 cq_id; 594 u16 rsvd2; 595 u32 rsvd3[13]; 596 struct phys_addr pages[8]; 597 } __packed; 598 599 struct be_cmd_resp_eth_tx_create { 600 struct be_cmd_resp_hdr hdr; 601 u16 cid; 602 u16 rid; 603 u32 db_offset; 604 u32 rsvd0[4]; 605 } __packed; 606 607 /******************** Create RxQ ***************************/ 608 struct be_cmd_req_eth_rx_create { 609 struct be_cmd_req_hdr hdr; 610 u16 cq_id; 611 u8 frag_size; 612 u8 num_pages; 613 struct phys_addr pages[2]; 614 u32 interface_id; 615 u16 max_frame_size; 616 u16 rsvd0; 617 u32 rss_queue; 618 } __packed; 619 620 struct be_cmd_resp_eth_rx_create { 621 struct be_cmd_resp_hdr hdr; 622 u16 id; 623 u8 rss_id; 624 u8 rsvd0; 625 } __packed; 626 627 /******************** Q Destroy ***************************/ 628 /* Type of Queue to be destroyed */ 629 enum { 630 QTYPE_EQ = 1, 631 QTYPE_CQ, 632 QTYPE_TXQ, 633 QTYPE_RXQ, 634 QTYPE_MCCQ 635 }; 636 637 struct be_cmd_req_q_destroy { 638 struct be_cmd_req_hdr hdr; 639 u16 id; 640 u16 bypass_flush; /* valid only for rx q destroy */ 641 } __packed; 642 643 /************ I/f Create (it's actually I/f Config Create)**********/ 644 645 /* Capability flags for the i/f */ 646 enum be_if_flags { 647 BE_IF_FLAGS_RSS = 0x4, 648 BE_IF_FLAGS_PROMISCUOUS = 0x8, 649 BE_IF_FLAGS_BROADCAST = 0x10, 650 BE_IF_FLAGS_UNTAGGED = 0x20, 651 BE_IF_FLAGS_ULP = 0x40, 652 BE_IF_FLAGS_VLAN_PROMISCUOUS = 0x80, 653 BE_IF_FLAGS_VLAN = 0x100, 654 BE_IF_FLAGS_MCAST_PROMISCUOUS = 0x200, 655 BE_IF_FLAGS_PASS_L2_ERRORS = 0x400, 656 BE_IF_FLAGS_PASS_L3L4_ERRORS = 0x800, 657 BE_IF_FLAGS_MULTICAST = 0x1000, 658 BE_IF_FLAGS_DEFQ_RSS = 0x1000000 659 }; 660 661 #define BE_IF_CAP_FLAGS_WANT (BE_IF_FLAGS_RSS | BE_IF_FLAGS_PROMISCUOUS |\ 662 BE_IF_FLAGS_BROADCAST | BE_IF_FLAGS_VLAN_PROMISCUOUS |\ 663 BE_IF_FLAGS_VLAN | BE_IF_FLAGS_MCAST_PROMISCUOUS |\ 664 BE_IF_FLAGS_PASS_L3L4_ERRORS | BE_IF_FLAGS_MULTICAST |\ 665 BE_IF_FLAGS_UNTAGGED | BE_IF_FLAGS_DEFQ_RSS) 666 667 #define BE_IF_FLAGS_ALL_PROMISCUOUS (BE_IF_FLAGS_PROMISCUOUS | \ 668 BE_IF_FLAGS_VLAN_PROMISCUOUS |\ 669 BE_IF_FLAGS_MCAST_PROMISCUOUS) 670 671 #define BE_IF_FILT_FLAGS_BASIC (BE_IF_FLAGS_BROADCAST | \ 672 BE_IF_FLAGS_PASS_L3L4_ERRORS | \ 673 BE_IF_FLAGS_UNTAGGED) 674 675 #define BE_IF_ALL_FILT_FLAGS (BE_IF_FILT_FLAGS_BASIC | \ 676 BE_IF_FLAGS_MULTICAST | \ 677 BE_IF_FLAGS_ALL_PROMISCUOUS) 678 679 /* An RX interface is an object with one or more MAC addresses and 680 * filtering capabilities. */ 681 struct be_cmd_req_if_create { 682 struct be_cmd_req_hdr hdr; 683 u32 version; /* ignore currently */ 684 u32 capability_flags; 685 u32 enable_flags; 686 u8 mac_addr[ETH_ALEN]; 687 u8 rsvd0; 688 u8 pmac_invalid; /* if set, don't attach the mac addr to the i/f */ 689 u32 vlan_tag; /* not used currently */ 690 } __packed; 691 692 struct be_cmd_resp_if_create { 693 struct be_cmd_resp_hdr hdr; 694 u32 interface_id; 695 u32 pmac_id; 696 }; 697 698 /****** I/f Destroy(it's actually I/f Config Destroy )**********/ 699 struct be_cmd_req_if_destroy { 700 struct be_cmd_req_hdr hdr; 701 u32 interface_id; 702 }; 703 704 /*************** HW Stats Get **********************************/ 705 struct be_port_rxf_stats_v0 { 706 u32 rx_bytes_lsd; /* dword 0*/ 707 u32 rx_bytes_msd; /* dword 1*/ 708 u32 rx_total_frames; /* dword 2*/ 709 u32 rx_unicast_frames; /* dword 3*/ 710 u32 rx_multicast_frames; /* dword 4*/ 711 u32 rx_broadcast_frames; /* dword 5*/ 712 u32 rx_crc_errors; /* dword 6*/ 713 u32 rx_alignment_symbol_errors; /* dword 7*/ 714 u32 rx_pause_frames; /* dword 8*/ 715 u32 rx_control_frames; /* dword 9*/ 716 u32 rx_in_range_errors; /* dword 10*/ 717 u32 rx_out_range_errors; /* dword 11*/ 718 u32 rx_frame_too_long; /* dword 12*/ 719 u32 rx_address_filtered; /* dword 13*/ 720 u32 rx_vlan_filtered; /* dword 14*/ 721 u32 rx_dropped_too_small; /* dword 15*/ 722 u32 rx_dropped_too_short; /* dword 16*/ 723 u32 rx_dropped_header_too_small; /* dword 17*/ 724 u32 rx_dropped_tcp_length; /* dword 18*/ 725 u32 rx_dropped_runt; /* dword 19*/ 726 u32 rx_64_byte_packets; /* dword 20*/ 727 u32 rx_65_127_byte_packets; /* dword 21*/ 728 u32 rx_128_256_byte_packets; /* dword 22*/ 729 u32 rx_256_511_byte_packets; /* dword 23*/ 730 u32 rx_512_1023_byte_packets; /* dword 24*/ 731 u32 rx_1024_1518_byte_packets; /* dword 25*/ 732 u32 rx_1519_2047_byte_packets; /* dword 26*/ 733 u32 rx_2048_4095_byte_packets; /* dword 27*/ 734 u32 rx_4096_8191_byte_packets; /* dword 28*/ 735 u32 rx_8192_9216_byte_packets; /* dword 29*/ 736 u32 rx_ip_checksum_errs; /* dword 30*/ 737 u32 rx_tcp_checksum_errs; /* dword 31*/ 738 u32 rx_udp_checksum_errs; /* dword 32*/ 739 u32 rx_non_rss_packets; /* dword 33*/ 740 u32 rx_ipv4_packets; /* dword 34*/ 741 u32 rx_ipv6_packets; /* dword 35*/ 742 u32 rx_ipv4_bytes_lsd; /* dword 36*/ 743 u32 rx_ipv4_bytes_msd; /* dword 37*/ 744 u32 rx_ipv6_bytes_lsd; /* dword 38*/ 745 u32 rx_ipv6_bytes_msd; /* dword 39*/ 746 u32 rx_chute1_packets; /* dword 40*/ 747 u32 rx_chute2_packets; /* dword 41*/ 748 u32 rx_chute3_packets; /* dword 42*/ 749 u32 rx_management_packets; /* dword 43*/ 750 u32 rx_switched_unicast_packets; /* dword 44*/ 751 u32 rx_switched_multicast_packets; /* dword 45*/ 752 u32 rx_switched_broadcast_packets; /* dword 46*/ 753 u32 tx_bytes_lsd; /* dword 47*/ 754 u32 tx_bytes_msd; /* dword 48*/ 755 u32 tx_unicastframes; /* dword 49*/ 756 u32 tx_multicastframes; /* dword 50*/ 757 u32 tx_broadcastframes; /* dword 51*/ 758 u32 tx_pauseframes; /* dword 52*/ 759 u32 tx_controlframes; /* dword 53*/ 760 u32 tx_64_byte_packets; /* dword 54*/ 761 u32 tx_65_127_byte_packets; /* dword 55*/ 762 u32 tx_128_256_byte_packets; /* dword 56*/ 763 u32 tx_256_511_byte_packets; /* dword 57*/ 764 u32 tx_512_1023_byte_packets; /* dword 58*/ 765 u32 tx_1024_1518_byte_packets; /* dword 59*/ 766 u32 tx_1519_2047_byte_packets; /* dword 60*/ 767 u32 tx_2048_4095_byte_packets; /* dword 61*/ 768 u32 tx_4096_8191_byte_packets; /* dword 62*/ 769 u32 tx_8192_9216_byte_packets; /* dword 63*/ 770 u32 rx_fifo_overflow; /* dword 64*/ 771 u32 rx_input_fifo_overflow; /* dword 65*/ 772 }; 773 774 struct be_rxf_stats_v0 { 775 struct be_port_rxf_stats_v0 port[2]; 776 u32 rx_drops_no_pbuf; /* dword 132*/ 777 u32 rx_drops_no_txpb; /* dword 133*/ 778 u32 rx_drops_no_erx_descr; /* dword 134*/ 779 u32 rx_drops_no_tpre_descr; /* dword 135*/ 780 u32 management_rx_port_packets; /* dword 136*/ 781 u32 management_rx_port_bytes; /* dword 137*/ 782 u32 management_rx_port_pause_frames; /* dword 138*/ 783 u32 management_rx_port_errors; /* dword 139*/ 784 u32 management_tx_port_packets; /* dword 140*/ 785 u32 management_tx_port_bytes; /* dword 141*/ 786 u32 management_tx_port_pause; /* dword 142*/ 787 u32 management_rx_port_rxfifo_overflow; /* dword 143*/ 788 u32 rx_drops_too_many_frags; /* dword 144*/ 789 u32 rx_drops_invalid_ring; /* dword 145*/ 790 u32 forwarded_packets; /* dword 146*/ 791 u32 rx_drops_mtu; /* dword 147*/ 792 u32 rsvd0[7]; 793 u32 port0_jabber_events; 794 u32 port1_jabber_events; 795 u32 rsvd1[6]; 796 }; 797 798 struct be_erx_stats_v0 { 799 u32 rx_drops_no_fragments[44]; /* dwordS 0 to 43*/ 800 u32 rsvd[4]; 801 }; 802 803 struct be_pmem_stats { 804 u32 eth_red_drops; 805 u32 rsvd[5]; 806 }; 807 808 struct be_hw_stats_v0 { 809 struct be_rxf_stats_v0 rxf; 810 u32 rsvd[48]; 811 struct be_erx_stats_v0 erx; 812 struct be_pmem_stats pmem; 813 }; 814 815 struct be_cmd_req_get_stats_v0 { 816 struct be_cmd_req_hdr hdr; 817 u8 rsvd[sizeof(struct be_hw_stats_v0)]; 818 }; 819 820 struct be_cmd_resp_get_stats_v0 { 821 struct be_cmd_resp_hdr hdr; 822 struct be_hw_stats_v0 hw_stats; 823 }; 824 825 struct lancer_pport_stats { 826 u32 tx_packets_lo; 827 u32 tx_packets_hi; 828 u32 tx_unicast_packets_lo; 829 u32 tx_unicast_packets_hi; 830 u32 tx_multicast_packets_lo; 831 u32 tx_multicast_packets_hi; 832 u32 tx_broadcast_packets_lo; 833 u32 tx_broadcast_packets_hi; 834 u32 tx_bytes_lo; 835 u32 tx_bytes_hi; 836 u32 tx_unicast_bytes_lo; 837 u32 tx_unicast_bytes_hi; 838 u32 tx_multicast_bytes_lo; 839 u32 tx_multicast_bytes_hi; 840 u32 tx_broadcast_bytes_lo; 841 u32 tx_broadcast_bytes_hi; 842 u32 tx_discards_lo; 843 u32 tx_discards_hi; 844 u32 tx_errors_lo; 845 u32 tx_errors_hi; 846 u32 tx_pause_frames_lo; 847 u32 tx_pause_frames_hi; 848 u32 tx_pause_on_frames_lo; 849 u32 tx_pause_on_frames_hi; 850 u32 tx_pause_off_frames_lo; 851 u32 tx_pause_off_frames_hi; 852 u32 tx_internal_mac_errors_lo; 853 u32 tx_internal_mac_errors_hi; 854 u32 tx_control_frames_lo; 855 u32 tx_control_frames_hi; 856 u32 tx_packets_64_bytes_lo; 857 u32 tx_packets_64_bytes_hi; 858 u32 tx_packets_65_to_127_bytes_lo; 859 u32 tx_packets_65_to_127_bytes_hi; 860 u32 tx_packets_128_to_255_bytes_lo; 861 u32 tx_packets_128_to_255_bytes_hi; 862 u32 tx_packets_256_to_511_bytes_lo; 863 u32 tx_packets_256_to_511_bytes_hi; 864 u32 tx_packets_512_to_1023_bytes_lo; 865 u32 tx_packets_512_to_1023_bytes_hi; 866 u32 tx_packets_1024_to_1518_bytes_lo; 867 u32 tx_packets_1024_to_1518_bytes_hi; 868 u32 tx_packets_1519_to_2047_bytes_lo; 869 u32 tx_packets_1519_to_2047_bytes_hi; 870 u32 tx_packets_2048_to_4095_bytes_lo; 871 u32 tx_packets_2048_to_4095_bytes_hi; 872 u32 tx_packets_4096_to_8191_bytes_lo; 873 u32 tx_packets_4096_to_8191_bytes_hi; 874 u32 tx_packets_8192_to_9216_bytes_lo; 875 u32 tx_packets_8192_to_9216_bytes_hi; 876 u32 tx_lso_packets_lo; 877 u32 tx_lso_packets_hi; 878 u32 rx_packets_lo; 879 u32 rx_packets_hi; 880 u32 rx_unicast_packets_lo; 881 u32 rx_unicast_packets_hi; 882 u32 rx_multicast_packets_lo; 883 u32 rx_multicast_packets_hi; 884 u32 rx_broadcast_packets_lo; 885 u32 rx_broadcast_packets_hi; 886 u32 rx_bytes_lo; 887 u32 rx_bytes_hi; 888 u32 rx_unicast_bytes_lo; 889 u32 rx_unicast_bytes_hi; 890 u32 rx_multicast_bytes_lo; 891 u32 rx_multicast_bytes_hi; 892 u32 rx_broadcast_bytes_lo; 893 u32 rx_broadcast_bytes_hi; 894 u32 rx_unknown_protos; 895 u32 rsvd_69; /* Word 69 is reserved */ 896 u32 rx_discards_lo; 897 u32 rx_discards_hi; 898 u32 rx_errors_lo; 899 u32 rx_errors_hi; 900 u32 rx_crc_errors_lo; 901 u32 rx_crc_errors_hi; 902 u32 rx_alignment_errors_lo; 903 u32 rx_alignment_errors_hi; 904 u32 rx_symbol_errors_lo; 905 u32 rx_symbol_errors_hi; 906 u32 rx_pause_frames_lo; 907 u32 rx_pause_frames_hi; 908 u32 rx_pause_on_frames_lo; 909 u32 rx_pause_on_frames_hi; 910 u32 rx_pause_off_frames_lo; 911 u32 rx_pause_off_frames_hi; 912 u32 rx_frames_too_long_lo; 913 u32 rx_frames_too_long_hi; 914 u32 rx_internal_mac_errors_lo; 915 u32 rx_internal_mac_errors_hi; 916 u32 rx_undersize_packets; 917 u32 rx_oversize_packets; 918 u32 rx_fragment_packets; 919 u32 rx_jabbers; 920 u32 rx_control_frames_lo; 921 u32 rx_control_frames_hi; 922 u32 rx_control_frames_unknown_opcode_lo; 923 u32 rx_control_frames_unknown_opcode_hi; 924 u32 rx_in_range_errors; 925 u32 rx_out_of_range_errors; 926 u32 rx_address_filtered; 927 u32 rx_vlan_filtered; 928 u32 rx_dropped_too_small; 929 u32 rx_dropped_too_short; 930 u32 rx_dropped_header_too_small; 931 u32 rx_dropped_invalid_tcp_length; 932 u32 rx_dropped_runt; 933 u32 rx_ip_checksum_errors; 934 u32 rx_tcp_checksum_errors; 935 u32 rx_udp_checksum_errors; 936 u32 rx_non_rss_packets; 937 u32 rsvd_111; 938 u32 rx_ipv4_packets_lo; 939 u32 rx_ipv4_packets_hi; 940 u32 rx_ipv6_packets_lo; 941 u32 rx_ipv6_packets_hi; 942 u32 rx_ipv4_bytes_lo; 943 u32 rx_ipv4_bytes_hi; 944 u32 rx_ipv6_bytes_lo; 945 u32 rx_ipv6_bytes_hi; 946 u32 rx_nic_packets_lo; 947 u32 rx_nic_packets_hi; 948 u32 rx_tcp_packets_lo; 949 u32 rx_tcp_packets_hi; 950 u32 rx_iscsi_packets_lo; 951 u32 rx_iscsi_packets_hi; 952 u32 rx_management_packets_lo; 953 u32 rx_management_packets_hi; 954 u32 rx_switched_unicast_packets_lo; 955 u32 rx_switched_unicast_packets_hi; 956 u32 rx_switched_multicast_packets_lo; 957 u32 rx_switched_multicast_packets_hi; 958 u32 rx_switched_broadcast_packets_lo; 959 u32 rx_switched_broadcast_packets_hi; 960 u32 num_forwards_lo; 961 u32 num_forwards_hi; 962 u32 rx_fifo_overflow; 963 u32 rx_input_fifo_overflow; 964 u32 rx_drops_too_many_frags_lo; 965 u32 rx_drops_too_many_frags_hi; 966 u32 rx_drops_invalid_queue; 967 u32 rsvd_141; 968 u32 rx_drops_mtu_lo; 969 u32 rx_drops_mtu_hi; 970 u32 rx_packets_64_bytes_lo; 971 u32 rx_packets_64_bytes_hi; 972 u32 rx_packets_65_to_127_bytes_lo; 973 u32 rx_packets_65_to_127_bytes_hi; 974 u32 rx_packets_128_to_255_bytes_lo; 975 u32 rx_packets_128_to_255_bytes_hi; 976 u32 rx_packets_256_to_511_bytes_lo; 977 u32 rx_packets_256_to_511_bytes_hi; 978 u32 rx_packets_512_to_1023_bytes_lo; 979 u32 rx_packets_512_to_1023_bytes_hi; 980 u32 rx_packets_1024_to_1518_bytes_lo; 981 u32 rx_packets_1024_to_1518_bytes_hi; 982 u32 rx_packets_1519_to_2047_bytes_lo; 983 u32 rx_packets_1519_to_2047_bytes_hi; 984 u32 rx_packets_2048_to_4095_bytes_lo; 985 u32 rx_packets_2048_to_4095_bytes_hi; 986 u32 rx_packets_4096_to_8191_bytes_lo; 987 u32 rx_packets_4096_to_8191_bytes_hi; 988 u32 rx_packets_8192_to_9216_bytes_lo; 989 u32 rx_packets_8192_to_9216_bytes_hi; 990 }; 991 992 struct pport_stats_params { 993 u16 pport_num; 994 u8 rsvd; 995 u8 reset_stats; 996 }; 997 998 struct lancer_cmd_req_pport_stats { 999 struct be_cmd_req_hdr hdr; 1000 union { 1001 struct pport_stats_params params; 1002 u8 rsvd[sizeof(struct lancer_pport_stats)]; 1003 } cmd_params; 1004 }; 1005 1006 struct lancer_cmd_resp_pport_stats { 1007 struct be_cmd_resp_hdr hdr; 1008 struct lancer_pport_stats pport_stats; 1009 }; 1010 1011 static inline struct lancer_pport_stats* 1012 pport_stats_from_cmd(struct be_adapter *adapter) 1013 { 1014 struct lancer_cmd_resp_pport_stats *cmd = adapter->stats_cmd.va; 1015 return &cmd->pport_stats; 1016 } 1017 1018 struct be_cmd_req_get_cntl_addnl_attribs { 1019 struct be_cmd_req_hdr hdr; 1020 u8 rsvd[8]; 1021 }; 1022 1023 struct be_cmd_resp_get_cntl_addnl_attribs { 1024 struct be_cmd_resp_hdr hdr; 1025 u16 ipl_file_number; 1026 u8 ipl_file_version; 1027 u8 rsvd0; 1028 u8 on_die_temperature; /* in degrees centigrade*/ 1029 u8 rsvd1[3]; 1030 }; 1031 1032 struct be_cmd_req_vlan_config { 1033 struct be_cmd_req_hdr hdr; 1034 u8 interface_id; 1035 u8 promiscuous; 1036 u8 untagged; 1037 u8 num_vlan; 1038 u16 normal_vlan[64]; 1039 } __packed; 1040 1041 /******************* RX FILTER ******************************/ 1042 #define BE_MAX_MC 64 /* set mcast promisc if > 64 */ 1043 struct macaddr { 1044 u8 byte[ETH_ALEN]; 1045 }; 1046 1047 struct be_cmd_req_rx_filter { 1048 struct be_cmd_req_hdr hdr; 1049 u32 global_flags_mask; 1050 u32 global_flags; 1051 u32 if_flags_mask; 1052 u32 if_flags; 1053 u32 if_id; 1054 u32 mcast_num; 1055 struct macaddr mcast_mac[BE_MAX_MC]; 1056 }; 1057 1058 /******************** Link Status Query *******************/ 1059 struct be_cmd_req_link_status { 1060 struct be_cmd_req_hdr hdr; 1061 u32 rsvd; 1062 }; 1063 1064 enum { 1065 PHY_LINK_DUPLEX_NONE = 0x0, 1066 PHY_LINK_DUPLEX_HALF = 0x1, 1067 PHY_LINK_DUPLEX_FULL = 0x2 1068 }; 1069 1070 enum { 1071 PHY_LINK_SPEED_ZERO = 0x0, /* => No link */ 1072 PHY_LINK_SPEED_10MBPS = 0x1, 1073 PHY_LINK_SPEED_100MBPS = 0x2, 1074 PHY_LINK_SPEED_1GBPS = 0x3, 1075 PHY_LINK_SPEED_10GBPS = 0x4, 1076 PHY_LINK_SPEED_20GBPS = 0x5, 1077 PHY_LINK_SPEED_25GBPS = 0x6, 1078 PHY_LINK_SPEED_40GBPS = 0x7 1079 }; 1080 1081 struct be_cmd_resp_link_status { 1082 struct be_cmd_resp_hdr hdr; 1083 u8 physical_port; 1084 u8 mac_duplex; 1085 u8 mac_speed; 1086 u8 mac_fault; 1087 u8 mgmt_mac_duplex; 1088 u8 mgmt_mac_speed; 1089 u16 link_speed; 1090 u8 logical_link_status; 1091 u8 rsvd1[3]; 1092 } __packed; 1093 1094 /******************** Port Identification ***************************/ 1095 /* Identifies the type of port attached to NIC */ 1096 struct be_cmd_req_port_type { 1097 struct be_cmd_req_hdr hdr; 1098 __le32 page_num; 1099 __le32 port; 1100 }; 1101 1102 enum { 1103 TR_PAGE_A0 = 0xa0, 1104 TR_PAGE_A2 = 0xa2 1105 }; 1106 1107 /* From SFF-8436 QSFP+ spec */ 1108 #define QSFP_PLUS_CABLE_TYPE_OFFSET 0x83 1109 #define QSFP_PLUS_CR4_CABLE 0x8 1110 #define QSFP_PLUS_SR4_CABLE 0x4 1111 #define QSFP_PLUS_LR4_CABLE 0x2 1112 1113 /* From SFF-8472 spec */ 1114 #define SFP_PLUS_SFF_8472_COMP 0x5E 1115 #define SFP_PLUS_CABLE_TYPE_OFFSET 0x8 1116 #define SFP_PLUS_COPPER_CABLE 0x4 1117 #define SFP_VENDOR_NAME_OFFSET 0x14 1118 #define SFP_VENDOR_PN_OFFSET 0x28 1119 1120 #define PAGE_DATA_LEN 256 1121 struct be_cmd_resp_port_type { 1122 struct be_cmd_resp_hdr hdr; 1123 u32 page_num; 1124 u32 port; 1125 u8 page_data[PAGE_DATA_LEN]; 1126 }; 1127 1128 /******************** Get FW Version *******************/ 1129 struct be_cmd_req_get_fw_version { 1130 struct be_cmd_req_hdr hdr; 1131 u8 rsvd0[FW_VER_LEN]; 1132 u8 rsvd1[FW_VER_LEN]; 1133 } __packed; 1134 1135 struct be_cmd_resp_get_fw_version { 1136 struct be_cmd_resp_hdr hdr; 1137 u8 firmware_version_string[FW_VER_LEN]; 1138 u8 fw_on_flash_version_string[FW_VER_LEN]; 1139 } __packed; 1140 1141 /******************** Set Flow Contrl *******************/ 1142 struct be_cmd_req_set_flow_control { 1143 struct be_cmd_req_hdr hdr; 1144 u16 tx_flow_control; 1145 u16 rx_flow_control; 1146 } __packed; 1147 1148 /******************** Get Flow Contrl *******************/ 1149 struct be_cmd_req_get_flow_control { 1150 struct be_cmd_req_hdr hdr; 1151 u32 rsvd; 1152 }; 1153 1154 struct be_cmd_resp_get_flow_control { 1155 struct be_cmd_resp_hdr hdr; 1156 u16 tx_flow_control; 1157 u16 rx_flow_control; 1158 } __packed; 1159 1160 /******************** Modify EQ Delay *******************/ 1161 struct be_set_eqd { 1162 u32 eq_id; 1163 u32 phase; 1164 u32 delay_multiplier; 1165 }; 1166 1167 struct be_cmd_req_modify_eq_delay { 1168 struct be_cmd_req_hdr hdr; 1169 u32 num_eq; 1170 struct be_set_eqd set_eqd[MAX_EVT_QS]; 1171 } __packed; 1172 1173 /******************** Get FW Config *******************/ 1174 /* The HW can come up in either of the following multi-channel modes 1175 * based on the skew/IPL. 1176 */ 1177 #define RDMA_ENABLED 0x4 1178 #define QNQ_MODE 0x400 1179 #define VNIC_MODE 0x20000 1180 #define UMC_ENABLED 0x1000000 1181 struct be_cmd_req_query_fw_cfg { 1182 struct be_cmd_req_hdr hdr; 1183 u32 rsvd[31]; 1184 }; 1185 1186 struct be_cmd_resp_query_fw_cfg { 1187 struct be_cmd_resp_hdr hdr; 1188 u32 be_config_number; 1189 u32 asic_revision; 1190 u32 phys_port; 1191 u32 function_mode; 1192 u32 rsvd[26]; 1193 u32 function_caps; 1194 }; 1195 1196 /******************** RSS Config ****************************************/ 1197 /* RSS type Input parameters used to compute RX hash 1198 * RSS_ENABLE_IPV4 SRC IPv4, DST IPv4 1199 * RSS_ENABLE_TCP_IPV4 SRC IPv4, DST IPv4, TCP SRC PORT, TCP DST PORT 1200 * RSS_ENABLE_IPV6 SRC IPv6, DST IPv6 1201 * RSS_ENABLE_TCP_IPV6 SRC IPv6, DST IPv6, TCP SRC PORT, TCP DST PORT 1202 * RSS_ENABLE_UDP_IPV4 SRC IPv4, DST IPv4, UDP SRC PORT, UDP DST PORT 1203 * RSS_ENABLE_UDP_IPV6 SRC IPv6, DST IPv6, UDP SRC PORT, UDP DST PORT 1204 * 1205 * When multiple RSS types are enabled, HW picks the best hash policy 1206 * based on the type of the received packet. 1207 */ 1208 #define RSS_ENABLE_NONE 0x0 1209 #define RSS_ENABLE_IPV4 0x1 1210 #define RSS_ENABLE_TCP_IPV4 0x2 1211 #define RSS_ENABLE_IPV6 0x4 1212 #define RSS_ENABLE_TCP_IPV6 0x8 1213 #define RSS_ENABLE_UDP_IPV4 0x10 1214 #define RSS_ENABLE_UDP_IPV6 0x20 1215 1216 #define L3_RSS_FLAGS (RXH_IP_DST | RXH_IP_SRC) 1217 #define L4_RSS_FLAGS (RXH_L4_B_0_1 | RXH_L4_B_2_3) 1218 1219 struct be_cmd_req_rss_config { 1220 struct be_cmd_req_hdr hdr; 1221 u32 if_id; 1222 u16 enable_rss; 1223 u16 cpu_table_size_log2; 1224 u32 hash[10]; 1225 u8 cpu_table[128]; 1226 u8 flush; 1227 u8 rsvd0[3]; 1228 }; 1229 1230 /******************** Port Beacon ***************************/ 1231 1232 #define BEACON_STATE_ENABLED 0x1 1233 #define BEACON_STATE_DISABLED 0x0 1234 1235 struct be_cmd_req_enable_disable_beacon { 1236 struct be_cmd_req_hdr hdr; 1237 u8 port_num; 1238 u8 beacon_state; 1239 u8 beacon_duration; 1240 u8 status_duration; 1241 } __packed; 1242 1243 struct be_cmd_req_get_beacon_state { 1244 struct be_cmd_req_hdr hdr; 1245 u8 port_num; 1246 u8 rsvd0; 1247 u16 rsvd1; 1248 } __packed; 1249 1250 struct be_cmd_resp_get_beacon_state { 1251 struct be_cmd_resp_hdr resp_hdr; 1252 u8 beacon_state; 1253 u8 rsvd0[3]; 1254 } __packed; 1255 1256 /* Flashrom related descriptors */ 1257 #define MAX_FLASH_COMP 32 1258 1259 /* Optypes of each component in the UFI */ 1260 enum { 1261 OPTYPE_ISCSI_ACTIVE = 0, 1262 OPTYPE_REDBOOT = 1, 1263 OPTYPE_BIOS = 2, 1264 OPTYPE_PXE_BIOS = 3, 1265 OPTYPE_OFFSET_SPECIFIED = 7, 1266 OPTYPE_FCOE_BIOS = 8, 1267 OPTYPE_ISCSI_BACKUP = 9, 1268 OPTYPE_FCOE_FW_ACTIVE = 10, 1269 OPTYPE_FCOE_FW_BACKUP = 11, 1270 OPTYPE_NCSI_FW = 13, 1271 OPTYPE_REDBOOT_DIR = 18, 1272 OPTYPE_REDBOOT_CONFIG = 19, 1273 OPTYPE_SH_PHY_FW = 21, 1274 OPTYPE_FLASHISM_JUMPVECTOR = 22, 1275 OPTYPE_UFI_DIR = 23, 1276 OPTYPE_PHY_FW = 99 1277 }; 1278 1279 /* Maximum sizes of components in BE2 FW UFI */ 1280 enum { 1281 BE2_BIOS_COMP_MAX_SIZE = 0x40000, 1282 BE2_REDBOOT_COMP_MAX_SIZE = 0x40000, 1283 BE2_COMP_MAX_SIZE = 0x140000 1284 }; 1285 1286 /* Maximum sizes of components in BE3 FW UFI */ 1287 enum { 1288 BE3_NCSI_COMP_MAX_SIZE = 0x40000, 1289 BE3_PHY_FW_COMP_MAX_SIZE = 0x40000, 1290 BE3_BIOS_COMP_MAX_SIZE = 0x80000, 1291 BE3_REDBOOT_COMP_MAX_SIZE = 0x100000, 1292 BE3_COMP_MAX_SIZE = 0x200000 1293 }; 1294 1295 /* Offsets for components in BE2 FW UFI */ 1296 enum { 1297 BE2_REDBOOT_START = 0x8000, 1298 BE2_FCOE_BIOS_START = 0x80000, 1299 BE2_ISCSI_PRIMARY_IMAGE_START = 0x100000, 1300 BE2_ISCSI_BACKUP_IMAGE_START = 0x240000, 1301 BE2_FCOE_PRIMARY_IMAGE_START = 0x380000, 1302 BE2_FCOE_BACKUP_IMAGE_START = 0x4c0000, 1303 BE2_ISCSI_BIOS_START = 0x700000, 1304 BE2_PXE_BIOS_START = 0x780000 1305 }; 1306 1307 /* Offsets for components in BE3 FW UFI */ 1308 enum { 1309 BE3_REDBOOT_START = 0x40000, 1310 BE3_PHY_FW_START = 0x140000, 1311 BE3_ISCSI_PRIMARY_IMAGE_START = 0x200000, 1312 BE3_ISCSI_BACKUP_IMAGE_START = 0x400000, 1313 BE3_FCOE_PRIMARY_IMAGE_START = 0x600000, 1314 BE3_FCOE_BACKUP_IMAGE_START = 0x800000, 1315 BE3_ISCSI_BIOS_START = 0xc00000, 1316 BE3_PXE_BIOS_START = 0xc80000, 1317 BE3_FCOE_BIOS_START = 0xd00000, 1318 BE3_NCSI_START = 0xf40000 1319 }; 1320 1321 /* Component entry types */ 1322 enum { 1323 IMAGE_NCSI = 0x10, 1324 IMAGE_OPTION_ROM_PXE = 0x20, 1325 IMAGE_OPTION_ROM_FCOE = 0x21, 1326 IMAGE_OPTION_ROM_ISCSI = 0x22, 1327 IMAGE_FLASHISM_JUMPVECTOR = 0x30, 1328 IMAGE_FIRMWARE_ISCSI = 0xa0, 1329 IMAGE_FIRMWARE_FCOE = 0xa2, 1330 IMAGE_FIRMWARE_BACKUP_ISCSI = 0xb0, 1331 IMAGE_FIRMWARE_BACKUP_FCOE = 0xb2, 1332 IMAGE_FIRMWARE_PHY = 0xc0, 1333 IMAGE_REDBOOT_DIR = 0xd0, 1334 IMAGE_REDBOOT_CONFIG = 0xd1, 1335 IMAGE_UFI_DIR = 0xd2, 1336 IMAGE_BOOT_CODE = 0xe2 1337 }; 1338 1339 struct controller_id { 1340 u32 vendor; 1341 u32 device; 1342 u32 subvendor; 1343 u32 subdevice; 1344 }; 1345 1346 struct flash_comp { 1347 unsigned long offset; 1348 int optype; 1349 int size; 1350 int img_type; 1351 }; 1352 1353 struct image_hdr { 1354 u32 imageid; 1355 u32 imageoffset; 1356 u32 imagelength; 1357 u32 image_checksum; 1358 u8 image_version[32]; 1359 }; 1360 1361 struct flash_file_hdr_g2 { 1362 u8 sign[32]; 1363 u32 cksum; 1364 u32 antidote; 1365 struct controller_id cont_id; 1366 u32 file_len; 1367 u32 chunk_num; 1368 u32 total_chunks; 1369 u32 num_imgs; 1370 u8 build[24]; 1371 }; 1372 1373 /* First letter of the build version of the image */ 1374 #define BLD_STR_UFI_TYPE_BE2 '2' 1375 #define BLD_STR_UFI_TYPE_BE3 '3' 1376 #define BLD_STR_UFI_TYPE_SH '4' 1377 1378 struct flash_file_hdr_g3 { 1379 u8 sign[52]; 1380 u8 ufi_version[4]; 1381 u32 file_len; 1382 u32 cksum; 1383 u32 antidote; 1384 u32 num_imgs; 1385 u8 build[24]; 1386 u8 asic_type_rev; 1387 u8 rsvd[31]; 1388 }; 1389 1390 struct flash_section_hdr { 1391 u32 format_rev; 1392 u32 cksum; 1393 u32 antidote; 1394 u32 num_images; 1395 u8 id_string[128]; 1396 u32 rsvd[4]; 1397 } __packed; 1398 1399 struct flash_section_hdr_g2 { 1400 u32 format_rev; 1401 u32 cksum; 1402 u32 antidote; 1403 u32 build_num; 1404 u8 id_string[128]; 1405 u32 rsvd[8]; 1406 } __packed; 1407 1408 struct flash_section_entry { 1409 u32 type; 1410 u32 offset; 1411 u32 pad_size; 1412 u32 image_size; 1413 u32 cksum; 1414 u32 entry_point; 1415 u16 optype; 1416 u16 rsvd0; 1417 u32 rsvd1; 1418 u8 ver_data[32]; 1419 } __packed; 1420 1421 struct flash_section_info { 1422 u8 cookie[32]; 1423 struct flash_section_hdr fsec_hdr; 1424 struct flash_section_entry fsec_entry[32]; 1425 } __packed; 1426 1427 struct flash_section_info_g2 { 1428 u8 cookie[32]; 1429 struct flash_section_hdr_g2 fsec_hdr; 1430 struct flash_section_entry fsec_entry[32]; 1431 } __packed; 1432 1433 /****************** Firmware Flash ******************/ 1434 #define FLASHROM_OPER_FLASH 1 1435 #define FLASHROM_OPER_SAVE 2 1436 #define FLASHROM_OPER_REPORT 4 1437 #define FLASHROM_OPER_PHY_FLASH 9 1438 #define FLASHROM_OPER_PHY_SAVE 10 1439 1440 struct flashrom_params { 1441 u32 op_code; 1442 u32 op_type; 1443 u32 data_buf_size; 1444 u32 offset; 1445 }; 1446 1447 struct be_cmd_write_flashrom { 1448 struct be_cmd_req_hdr hdr; 1449 struct flashrom_params params; 1450 u8 data_buf[32768]; 1451 u8 rsvd[4]; 1452 } __packed; 1453 1454 /* cmd to read flash crc */ 1455 struct be_cmd_read_flash_crc { 1456 struct be_cmd_req_hdr hdr; 1457 struct flashrom_params params; 1458 u8 crc[4]; 1459 u8 rsvd[4]; 1460 } __packed; 1461 1462 /**************** Lancer Firmware Flash ************/ 1463 #define LANCER_FW_DOWNLOAD_CHUNK (32 * 1024) 1464 #define LANCER_FW_DOWNLOAD_LOCATION "/prg" 1465 1466 struct amap_lancer_write_obj_context { 1467 u8 write_length[24]; 1468 u8 reserved1[7]; 1469 u8 eof; 1470 } __packed; 1471 1472 struct lancer_cmd_req_write_object { 1473 struct be_cmd_req_hdr hdr; 1474 u8 context[sizeof(struct amap_lancer_write_obj_context) / 8]; 1475 u32 write_offset; 1476 u8 object_name[104]; 1477 u32 descriptor_count; 1478 u32 buf_len; 1479 u32 addr_low; 1480 u32 addr_high; 1481 }; 1482 1483 #define LANCER_NO_RESET_NEEDED 0x00 1484 #define LANCER_FW_RESET_NEEDED 0x02 1485 struct lancer_cmd_resp_write_object { 1486 u8 opcode; 1487 u8 subsystem; 1488 u8 rsvd1[2]; 1489 u8 status; 1490 u8 additional_status; 1491 u8 rsvd2[2]; 1492 u32 resp_len; 1493 u32 actual_resp_len; 1494 u32 actual_write_len; 1495 u8 change_status; 1496 u8 rsvd3[3]; 1497 }; 1498 1499 /************************ Lancer Read FW info **************/ 1500 #define LANCER_READ_FILE_CHUNK (32*1024) 1501 #define LANCER_READ_FILE_EOF_MASK 0x80000000 1502 1503 #define LANCER_FW_DUMP_FILE "/dbg/dump.bin" 1504 #define LANCER_VPD_PF_FILE "/vpd/ntr_pf.vpd" 1505 #define LANCER_VPD_VF_FILE "/vpd/ntr_vf.vpd" 1506 1507 struct lancer_cmd_req_read_object { 1508 struct be_cmd_req_hdr hdr; 1509 u32 desired_read_len; 1510 u32 read_offset; 1511 u8 object_name[104]; 1512 u32 descriptor_count; 1513 u32 buf_len; 1514 u32 addr_low; 1515 u32 addr_high; 1516 }; 1517 1518 struct lancer_cmd_resp_read_object { 1519 u8 opcode; 1520 u8 subsystem; 1521 u8 rsvd1[2]; 1522 u8 status; 1523 u8 additional_status; 1524 u8 rsvd2[2]; 1525 u32 resp_len; 1526 u32 actual_resp_len; 1527 u32 actual_read_len; 1528 u32 eof; 1529 }; 1530 1531 struct lancer_cmd_req_delete_object { 1532 struct be_cmd_req_hdr hdr; 1533 u32 rsvd1; 1534 u32 rsvd2; 1535 u8 object_name[104]; 1536 }; 1537 1538 /************************ WOL *******************************/ 1539 struct be_cmd_req_acpi_wol_magic_config{ 1540 struct be_cmd_req_hdr hdr; 1541 u32 rsvd0[145]; 1542 u8 magic_mac[6]; 1543 u8 rsvd2[2]; 1544 } __packed; 1545 1546 struct be_cmd_req_acpi_wol_magic_config_v1 { 1547 struct be_cmd_req_hdr hdr; 1548 u8 rsvd0[2]; 1549 u8 query_options; 1550 u8 rsvd1[5]; 1551 u32 rsvd2[288]; 1552 u8 magic_mac[6]; 1553 u8 rsvd3[22]; 1554 } __packed; 1555 1556 struct be_cmd_resp_acpi_wol_magic_config_v1 { 1557 struct be_cmd_resp_hdr hdr; 1558 u8 rsvd0[2]; 1559 u8 wol_settings; 1560 u8 rsvd1[5]; 1561 u32 rsvd2[288]; 1562 u8 magic_mac[6]; 1563 u8 rsvd3[22]; 1564 } __packed; 1565 1566 #define BE_GET_WOL_CAP 2 1567 1568 #define BE_WOL_CAP 0x1 1569 #define BE_PME_D0_CAP 0x8 1570 #define BE_PME_D1_CAP 0x10 1571 #define BE_PME_D2_CAP 0x20 1572 #define BE_PME_D3HOT_CAP 0x40 1573 #define BE_PME_D3COLD_CAP 0x80 1574 1575 /********************** LoopBack test *********************/ 1576 #define SET_LB_MODE_TIMEOUT 12000 1577 1578 struct be_cmd_req_loopback_test { 1579 struct be_cmd_req_hdr hdr; 1580 u32 loopback_type; 1581 u32 num_pkts; 1582 u64 pattern; 1583 u32 src_port; 1584 u32 dest_port; 1585 u32 pkt_size; 1586 }; 1587 1588 struct be_cmd_resp_loopback_test { 1589 struct be_cmd_resp_hdr resp_hdr; 1590 u32 status; 1591 u32 num_txfer; 1592 u32 num_rx; 1593 u32 miscomp_off; 1594 u32 ticks_compl; 1595 }; 1596 1597 struct be_cmd_req_set_lmode { 1598 struct be_cmd_req_hdr hdr; 1599 u8 src_port; 1600 u8 dest_port; 1601 u8 loopback_type; 1602 u8 loopback_state; 1603 }; 1604 1605 /********************** DDR DMA test *********************/ 1606 struct be_cmd_req_ddrdma_test { 1607 struct be_cmd_req_hdr hdr; 1608 u64 pattern; 1609 u32 byte_count; 1610 u32 rsvd0; 1611 u8 snd_buff[4096]; 1612 u8 rsvd1[4096]; 1613 }; 1614 1615 struct be_cmd_resp_ddrdma_test { 1616 struct be_cmd_resp_hdr hdr; 1617 u64 pattern; 1618 u32 byte_cnt; 1619 u32 snd_err; 1620 u8 rsvd0[4096]; 1621 u8 rcv_buff[4096]; 1622 }; 1623 1624 /*********************** SEEPROM Read ***********************/ 1625 1626 #define BE_READ_SEEPROM_LEN 1024 1627 struct be_cmd_req_seeprom_read { 1628 struct be_cmd_req_hdr hdr; 1629 u8 rsvd0[BE_READ_SEEPROM_LEN]; 1630 }; 1631 1632 struct be_cmd_resp_seeprom_read { 1633 struct be_cmd_req_hdr hdr; 1634 u8 seeprom_data[BE_READ_SEEPROM_LEN]; 1635 }; 1636 1637 enum { 1638 PHY_TYPE_CX4_10GB = 0, 1639 PHY_TYPE_XFP_10GB, 1640 PHY_TYPE_SFP_1GB, 1641 PHY_TYPE_SFP_PLUS_10GB, 1642 PHY_TYPE_KR_10GB, 1643 PHY_TYPE_KX4_10GB, 1644 PHY_TYPE_BASET_10GB, 1645 PHY_TYPE_BASET_1GB, 1646 PHY_TYPE_BASEX_1GB, 1647 PHY_TYPE_SGMII, 1648 PHY_TYPE_QSFP, 1649 PHY_TYPE_KR4_40GB, 1650 PHY_TYPE_KR2_20GB, 1651 PHY_TYPE_TN_8022, 1652 PHY_TYPE_DISABLED = 255 1653 }; 1654 1655 #define BE_SUPPORTED_SPEED_NONE 0 1656 #define BE_SUPPORTED_SPEED_10MBPS 1 1657 #define BE_SUPPORTED_SPEED_100MBPS 2 1658 #define BE_SUPPORTED_SPEED_1GBPS 4 1659 #define BE_SUPPORTED_SPEED_10GBPS 8 1660 #define BE_SUPPORTED_SPEED_20GBPS 0x10 1661 #define BE_SUPPORTED_SPEED_40GBPS 0x20 1662 1663 #define BE_AN_EN 0x2 1664 #define BE_PAUSE_SYM_EN 0x80 1665 1666 /* MAC speed valid values */ 1667 #define SPEED_DEFAULT 0x0 1668 #define SPEED_FORCED_10GB 0x1 1669 #define SPEED_FORCED_1GB 0x2 1670 #define SPEED_AUTONEG_10GB 0x3 1671 #define SPEED_AUTONEG_1GB 0x4 1672 #define SPEED_AUTONEG_100MB 0x5 1673 #define SPEED_AUTONEG_10GB_1GB 0x6 1674 #define SPEED_AUTONEG_10GB_1GB_100MB 0x7 1675 #define SPEED_AUTONEG_1GB_100MB 0x8 1676 #define SPEED_AUTONEG_10MB 0x9 1677 #define SPEED_AUTONEG_1GB_100MB_10MB 0xa 1678 #define SPEED_AUTONEG_100MB_10MB 0xb 1679 #define SPEED_FORCED_100MB 0xc 1680 #define SPEED_FORCED_10MB 0xd 1681 1682 struct be_cmd_req_get_phy_info { 1683 struct be_cmd_req_hdr hdr; 1684 u8 rsvd0[24]; 1685 }; 1686 1687 struct be_phy_info { 1688 u16 phy_type; 1689 u16 interface_type; 1690 u32 misc_params; 1691 u16 ext_phy_details; 1692 u16 rsvd; 1693 u16 auto_speeds_supported; 1694 u16 fixed_speeds_supported; 1695 u32 future_use[2]; 1696 }; 1697 1698 struct be_cmd_resp_get_phy_info { 1699 struct be_cmd_req_hdr hdr; 1700 struct be_phy_info phy_info; 1701 }; 1702 1703 /*********************** Set QOS ***********************/ 1704 1705 #define BE_QOS_BITS_NIC 1 1706 1707 struct be_cmd_req_set_qos { 1708 struct be_cmd_req_hdr hdr; 1709 u32 valid_bits; 1710 u32 max_bps_nic; 1711 u32 rsvd[7]; 1712 }; 1713 1714 /*********************** Controller Attributes ***********************/ 1715 struct mgmt_hba_attribs { 1716 u32 rsvd0[24]; 1717 u8 controller_model_number[32]; 1718 u32 rsvd1[16]; 1719 u32 controller_serial_number[8]; 1720 u32 rsvd2[55]; 1721 u8 rsvd3[3]; 1722 u8 phy_port; 1723 u32 rsvd4[15]; 1724 u8 rsvd5[2]; 1725 u8 pci_funcnum; 1726 u8 rsvd6; 1727 u32 rsvd7[6]; 1728 } __packed; 1729 1730 struct mgmt_controller_attrib { 1731 struct mgmt_hba_attribs hba_attribs; 1732 u32 rsvd0[10]; 1733 } __packed; 1734 1735 struct be_cmd_req_cntl_attribs { 1736 struct be_cmd_req_hdr hdr; 1737 }; 1738 1739 struct be_cmd_resp_cntl_attribs { 1740 struct be_cmd_resp_hdr hdr; 1741 struct mgmt_controller_attrib attribs; 1742 }; 1743 1744 /*********************** Set driver function ***********************/ 1745 #define CAPABILITY_SW_TIMESTAMPS 2 1746 #define CAPABILITY_BE3_NATIVE_ERX_API 4 1747 1748 struct be_cmd_req_set_func_cap { 1749 struct be_cmd_req_hdr hdr; 1750 u32 valid_cap_flags; 1751 u32 cap_flags; 1752 u8 rsvd[212]; 1753 }; 1754 1755 struct be_cmd_resp_set_func_cap { 1756 struct be_cmd_resp_hdr hdr; 1757 u32 valid_cap_flags; 1758 u32 cap_flags; 1759 u8 rsvd[212]; 1760 }; 1761 1762 /*********************** Function Privileges ***********************/ 1763 enum { 1764 BE_PRIV_DEFAULT = 0x1, 1765 BE_PRIV_LNKQUERY = 0x2, 1766 BE_PRIV_LNKSTATS = 0x4, 1767 BE_PRIV_LNKMGMT = 0x8, 1768 BE_PRIV_LNKDIAG = 0x10, 1769 BE_PRIV_UTILQUERY = 0x20, 1770 BE_PRIV_FILTMGMT = 0x40, 1771 BE_PRIV_IFACEMGMT = 0x80, 1772 BE_PRIV_VHADM = 0x100, 1773 BE_PRIV_DEVCFG = 0x200, 1774 BE_PRIV_DEVSEC = 0x400 1775 }; 1776 #define MAX_PRIVILEGES (BE_PRIV_VHADM | BE_PRIV_DEVCFG | \ 1777 BE_PRIV_DEVSEC) 1778 #define MIN_PRIVILEGES BE_PRIV_DEFAULT 1779 1780 struct be_cmd_priv_map { 1781 u8 opcode; 1782 u8 subsystem; 1783 u32 priv_mask; 1784 }; 1785 1786 struct be_cmd_req_get_fn_privileges { 1787 struct be_cmd_req_hdr hdr; 1788 u32 rsvd; 1789 }; 1790 1791 struct be_cmd_resp_get_fn_privileges { 1792 struct be_cmd_resp_hdr hdr; 1793 u32 privilege_mask; 1794 }; 1795 1796 struct be_cmd_req_set_fn_privileges { 1797 struct be_cmd_req_hdr hdr; 1798 u32 privileges; /* Used by BE3, SH-R */ 1799 u32 privileges_lancer; /* Used by Lancer */ 1800 }; 1801 1802 /******************** GET/SET_MACLIST **************************/ 1803 #define BE_MAX_MAC 64 1804 struct be_cmd_req_get_mac_list { 1805 struct be_cmd_req_hdr hdr; 1806 u8 mac_type; 1807 u8 perm_override; 1808 u16 iface_id; 1809 u32 mac_id; 1810 u32 rsvd[3]; 1811 } __packed; 1812 1813 struct get_list_macaddr { 1814 u16 mac_addr_size; 1815 union { 1816 u8 macaddr[6]; 1817 struct { 1818 u8 rsvd[2]; 1819 u32 mac_id; 1820 } __packed s_mac_id; 1821 } __packed mac_addr_id; 1822 } __packed; 1823 1824 struct be_cmd_resp_get_mac_list { 1825 struct be_cmd_resp_hdr hdr; 1826 struct get_list_macaddr fd_macaddr; /* Factory default mac */ 1827 struct get_list_macaddr macid_macaddr; /* soft mac */ 1828 u8 true_mac_count; 1829 u8 pseudo_mac_count; 1830 u8 mac_list_size; 1831 u8 rsvd; 1832 /* perm override mac */ 1833 struct get_list_macaddr macaddr_list[BE_MAX_MAC]; 1834 } __packed; 1835 1836 struct be_cmd_req_set_mac_list { 1837 struct be_cmd_req_hdr hdr; 1838 u8 mac_count; 1839 u8 rsvd1; 1840 u16 rsvd2; 1841 struct macaddr mac[BE_MAX_MAC]; 1842 } __packed; 1843 1844 /*********************** HSW Config ***********************/ 1845 #define PORT_FWD_TYPE_VEPA 0x3 1846 #define PORT_FWD_TYPE_VEB 0x2 1847 #define PORT_FWD_TYPE_PASSTHRU 0x1 1848 1849 #define ENABLE_MAC_SPOOFCHK 0x2 1850 #define DISABLE_MAC_SPOOFCHK 0x3 1851 1852 struct amap_set_hsw_context { 1853 u8 interface_id[16]; 1854 u8 rsvd0[8]; 1855 u8 mac_spoofchk[2]; 1856 u8 rsvd1[4]; 1857 u8 pvid_valid; 1858 u8 pport; 1859 u8 rsvd2[6]; 1860 u8 port_fwd_type[3]; 1861 u8 rsvd3[5]; 1862 u8 vlan_spoofchk[2]; 1863 u8 pvid[16]; 1864 u8 rsvd4[32]; 1865 u8 rsvd5[32]; 1866 u8 rsvd6[32]; 1867 } __packed; 1868 1869 struct be_cmd_req_set_hsw_config { 1870 struct be_cmd_req_hdr hdr; 1871 u8 context[sizeof(struct amap_set_hsw_context) / 8]; 1872 } __packed; 1873 1874 struct amap_get_hsw_req_context { 1875 u8 interface_id[16]; 1876 u8 rsvd0[14]; 1877 u8 pvid_valid; 1878 u8 pport; 1879 } __packed; 1880 1881 struct amap_get_hsw_resp_context { 1882 u8 rsvd0[6]; 1883 u8 port_fwd_type[3]; 1884 u8 rsvd1[5]; 1885 u8 spoofchk; 1886 u8 rsvd2; 1887 u8 pvid[16]; 1888 u8 rsvd3[32]; 1889 u8 rsvd4[32]; 1890 u8 rsvd5[32]; 1891 } __packed; 1892 1893 struct be_cmd_req_get_hsw_config { 1894 struct be_cmd_req_hdr hdr; 1895 u8 context[sizeof(struct amap_get_hsw_req_context) / 8]; 1896 } __packed; 1897 1898 struct be_cmd_resp_get_hsw_config { 1899 struct be_cmd_resp_hdr hdr; 1900 u8 context[sizeof(struct amap_get_hsw_resp_context) / 8]; 1901 u32 rsvd; 1902 }; 1903 1904 /******************* get port names ***************/ 1905 struct be_cmd_req_get_port_name { 1906 struct be_cmd_req_hdr hdr; 1907 u32 rsvd0; 1908 }; 1909 1910 struct be_cmd_resp_get_port_name { 1911 struct be_cmd_req_hdr hdr; 1912 u8 port_name[4]; 1913 }; 1914 1915 /*************** HW Stats Get v1 **********************************/ 1916 #define BE_TXP_SW_SZ 48 1917 struct be_port_rxf_stats_v1 { 1918 u32 rsvd0[12]; 1919 u32 rx_crc_errors; 1920 u32 rx_alignment_symbol_errors; 1921 u32 rx_pause_frames; 1922 u32 rx_priority_pause_frames; 1923 u32 rx_control_frames; 1924 u32 rx_in_range_errors; 1925 u32 rx_out_range_errors; 1926 u32 rx_frame_too_long; 1927 u32 rx_address_filtered; 1928 u32 rx_dropped_too_small; 1929 u32 rx_dropped_too_short; 1930 u32 rx_dropped_header_too_small; 1931 u32 rx_dropped_tcp_length; 1932 u32 rx_dropped_runt; 1933 u32 rsvd1[10]; 1934 u32 rx_ip_checksum_errs; 1935 u32 rx_tcp_checksum_errs; 1936 u32 rx_udp_checksum_errs; 1937 u32 rsvd2[7]; 1938 u32 rx_switched_unicast_packets; 1939 u32 rx_switched_multicast_packets; 1940 u32 rx_switched_broadcast_packets; 1941 u32 rsvd3[3]; 1942 u32 tx_pauseframes; 1943 u32 tx_priority_pauseframes; 1944 u32 tx_controlframes; 1945 u32 rsvd4[10]; 1946 u32 rxpp_fifo_overflow_drop; 1947 u32 rx_input_fifo_overflow_drop; 1948 u32 pmem_fifo_overflow_drop; 1949 u32 jabber_events; 1950 u32 rsvd5[3]; 1951 }; 1952 1953 1954 struct be_rxf_stats_v1 { 1955 struct be_port_rxf_stats_v1 port[4]; 1956 u32 rsvd0[2]; 1957 u32 rx_drops_no_pbuf; 1958 u32 rx_drops_no_txpb; 1959 u32 rx_drops_no_erx_descr; 1960 u32 rx_drops_no_tpre_descr; 1961 u32 rsvd1[6]; 1962 u32 rx_drops_too_many_frags; 1963 u32 rx_drops_invalid_ring; 1964 u32 forwarded_packets; 1965 u32 rx_drops_mtu; 1966 u32 rsvd2[14]; 1967 }; 1968 1969 struct be_erx_stats_v1 { 1970 u32 rx_drops_no_fragments[68]; /* dwordS 0 to 67*/ 1971 u32 rsvd[4]; 1972 }; 1973 1974 struct be_port_rxf_stats_v2 { 1975 u32 rsvd0[10]; 1976 u32 roce_bytes_received_lsd; 1977 u32 roce_bytes_received_msd; 1978 u32 rsvd1[5]; 1979 u32 roce_frames_received; 1980 u32 rx_crc_errors; 1981 u32 rx_alignment_symbol_errors; 1982 u32 rx_pause_frames; 1983 u32 rx_priority_pause_frames; 1984 u32 rx_control_frames; 1985 u32 rx_in_range_errors; 1986 u32 rx_out_range_errors; 1987 u32 rx_frame_too_long; 1988 u32 rx_address_filtered; 1989 u32 rx_dropped_too_small; 1990 u32 rx_dropped_too_short; 1991 u32 rx_dropped_header_too_small; 1992 u32 rx_dropped_tcp_length; 1993 u32 rx_dropped_runt; 1994 u32 rsvd2[10]; 1995 u32 rx_ip_checksum_errs; 1996 u32 rx_tcp_checksum_errs; 1997 u32 rx_udp_checksum_errs; 1998 u32 rsvd3[7]; 1999 u32 rx_switched_unicast_packets; 2000 u32 rx_switched_multicast_packets; 2001 u32 rx_switched_broadcast_packets; 2002 u32 rsvd4[3]; 2003 u32 tx_pauseframes; 2004 u32 tx_priority_pauseframes; 2005 u32 tx_controlframes; 2006 u32 rsvd5[10]; 2007 u32 rxpp_fifo_overflow_drop; 2008 u32 rx_input_fifo_overflow_drop; 2009 u32 pmem_fifo_overflow_drop; 2010 u32 jabber_events; 2011 u32 rsvd6[3]; 2012 u32 rx_drops_payload_size; 2013 u32 rx_drops_clipped_header; 2014 u32 rx_drops_crc; 2015 u32 roce_drops_payload_len; 2016 u32 roce_drops_crc; 2017 u32 rsvd7[19]; 2018 }; 2019 2020 struct be_rxf_stats_v2 { 2021 struct be_port_rxf_stats_v2 port[4]; 2022 u32 rsvd0[2]; 2023 u32 rx_drops_no_pbuf; 2024 u32 rx_drops_no_txpb; 2025 u32 rx_drops_no_erx_descr; 2026 u32 rx_drops_no_tpre_descr; 2027 u32 rsvd1[6]; 2028 u32 rx_drops_too_many_frags; 2029 u32 rx_drops_invalid_ring; 2030 u32 forwarded_packets; 2031 u32 rx_drops_mtu; 2032 u32 rsvd2[35]; 2033 }; 2034 2035 struct be_hw_stats_v1 { 2036 struct be_rxf_stats_v1 rxf; 2037 u32 rsvd0[BE_TXP_SW_SZ]; 2038 struct be_erx_stats_v1 erx; 2039 struct be_pmem_stats pmem; 2040 u32 rsvd1[18]; 2041 }; 2042 2043 struct be_cmd_req_get_stats_v1 { 2044 struct be_cmd_req_hdr hdr; 2045 u8 rsvd[sizeof(struct be_hw_stats_v1)]; 2046 }; 2047 2048 struct be_cmd_resp_get_stats_v1 { 2049 struct be_cmd_resp_hdr hdr; 2050 struct be_hw_stats_v1 hw_stats; 2051 }; 2052 2053 struct be_erx_stats_v2 { 2054 u32 rx_drops_no_fragments[136]; /* dwordS 0 to 135*/ 2055 u32 rsvd[3]; 2056 }; 2057 2058 struct be_hw_stats_v2 { 2059 struct be_rxf_stats_v2 rxf; 2060 u32 rsvd0[BE_TXP_SW_SZ]; 2061 struct be_erx_stats_v2 erx; 2062 struct be_pmem_stats pmem; 2063 u32 rsvd1[18]; 2064 }; 2065 2066 struct be_cmd_req_get_stats_v2 { 2067 struct be_cmd_req_hdr hdr; 2068 u8 rsvd[sizeof(struct be_hw_stats_v2)]; 2069 }; 2070 2071 struct be_cmd_resp_get_stats_v2 { 2072 struct be_cmd_resp_hdr hdr; 2073 struct be_hw_stats_v2 hw_stats; 2074 }; 2075 2076 /************** get fat capabilites *******************/ 2077 #define MAX_MODULES 27 2078 #define MAX_MODES 4 2079 #define MODE_UART 0 2080 #define FW_LOG_LEVEL_DEFAULT 48 2081 #define FW_LOG_LEVEL_FATAL 64 2082 2083 struct ext_fat_mode { 2084 u8 mode; 2085 u8 rsvd0; 2086 u16 port_mask; 2087 u32 dbg_lvl; 2088 u64 fun_mask; 2089 } __packed; 2090 2091 struct ext_fat_modules { 2092 u8 modules_str[32]; 2093 u32 modules_id; 2094 u32 num_modes; 2095 struct ext_fat_mode trace_lvl[MAX_MODES]; 2096 } __packed; 2097 2098 struct be_fat_conf_params { 2099 u32 max_log_entries; 2100 u32 log_entry_size; 2101 u8 log_type; 2102 u8 max_log_funs; 2103 u8 max_log_ports; 2104 u8 rsvd0; 2105 u32 supp_modes; 2106 u32 num_modules; 2107 struct ext_fat_modules module[MAX_MODULES]; 2108 } __packed; 2109 2110 struct be_cmd_req_get_ext_fat_caps { 2111 struct be_cmd_req_hdr hdr; 2112 u32 parameter_type; 2113 }; 2114 2115 struct be_cmd_resp_get_ext_fat_caps { 2116 struct be_cmd_resp_hdr hdr; 2117 struct be_fat_conf_params get_params; 2118 }; 2119 2120 struct be_cmd_req_set_ext_fat_caps { 2121 struct be_cmd_req_hdr hdr; 2122 struct be_fat_conf_params set_params; 2123 }; 2124 2125 #define RESOURCE_DESC_SIZE_V0 72 2126 #define RESOURCE_DESC_SIZE_V1 88 2127 #define PCIE_RESOURCE_DESC_TYPE_V0 0x40 2128 #define NIC_RESOURCE_DESC_TYPE_V0 0x41 2129 #define PCIE_RESOURCE_DESC_TYPE_V1 0x50 2130 #define NIC_RESOURCE_DESC_TYPE_V1 0x51 2131 #define PORT_RESOURCE_DESC_TYPE_V1 0x55 2132 #define MAX_RESOURCE_DESC 264 2133 2134 #define IF_CAPS_FLAGS_VALID_SHIFT 0 /* IF caps valid */ 2135 #define VFT_SHIFT 3 /* VF template */ 2136 #define IMM_SHIFT 6 /* Immediate */ 2137 #define NOSV_SHIFT 7 /* No save */ 2138 2139 #define MISSION_NIC 1 2140 #define MISSION_RDMA 8 2141 2142 struct be_res_desc_hdr { 2143 u8 desc_type; 2144 u8 desc_len; 2145 } __packed; 2146 2147 struct be_port_res_desc { 2148 struct be_res_desc_hdr hdr; 2149 u8 rsvd0; 2150 u8 flags; 2151 u8 link_num; 2152 u8 mc_type; 2153 u16 rsvd1; 2154 2155 #define NV_TYPE_MASK 0x3 /* bits 0-1 */ 2156 #define NV_TYPE_DISABLED 1 2157 #define NV_TYPE_VXLAN 3 2158 #define SOCVID_SHIFT 2 /* Strip outer vlan */ 2159 #define RCVID_SHIFT 4 /* Report vlan */ 2160 #define PF_NUM_IGNORE 255 2161 u8 nv_flags; 2162 u8 rsvd2; 2163 __le16 nv_port; /* vxlan/gre port */ 2164 u32 rsvd3[19]; 2165 } __packed; 2166 2167 struct be_pcie_res_desc { 2168 struct be_res_desc_hdr hdr; 2169 u8 rsvd0; 2170 u8 flags; 2171 u16 rsvd1; 2172 u8 pf_num; 2173 u8 rsvd2; 2174 u32 rsvd3; 2175 u8 sriov_state; 2176 u8 pf_state; 2177 u8 pf_type; 2178 u8 rsvd4; 2179 u16 num_vfs; 2180 u16 rsvd5; 2181 u32 rsvd6[17]; 2182 } __packed; 2183 2184 struct be_nic_res_desc { 2185 struct be_res_desc_hdr hdr; 2186 u8 rsvd1; 2187 2188 #define QUN_SHIFT 4 /* QoS is in absolute units */ 2189 u8 flags; 2190 u8 vf_num; 2191 u8 rsvd2; 2192 u8 pf_num; 2193 u8 rsvd3; 2194 u16 unicast_mac_count; 2195 u8 rsvd4[6]; 2196 u16 mcc_count; 2197 u16 vlan_count; 2198 u16 mcast_mac_count; 2199 u16 txq_count; 2200 u16 rq_count; 2201 u16 rssq_count; 2202 u16 lro_count; 2203 u16 cq_count; 2204 u16 toe_conn_count; 2205 u16 eq_count; 2206 u16 vlan_id; 2207 u16 iface_count; 2208 u32 cap_flags; 2209 u8 link_param; 2210 u8 rsvd6; 2211 u16 channel_id_param; 2212 u32 bw_min; 2213 u32 bw_max; 2214 u8 acpi_params; 2215 u8 wol_param; 2216 u16 rsvd7; 2217 u16 tunnel_iface_count; 2218 u16 direct_tenant_iface_count; 2219 u32 rsvd8[6]; 2220 } __packed; 2221 2222 /************ Multi-Channel type ***********/ 2223 enum mc_type { 2224 MC_NONE = 0x01, 2225 UMC = 0x02, 2226 FLEX10 = 0x03, 2227 vNIC1 = 0x04, 2228 nPAR = 0x05, 2229 UFP = 0x06, 2230 vNIC2 = 0x07 2231 }; 2232 2233 /* Is BE in a multi-channel mode */ 2234 static inline bool be_is_mc(struct be_adapter *adapter) 2235 { 2236 return adapter->mc_type > MC_NONE; 2237 } 2238 2239 struct be_cmd_req_get_func_config { 2240 struct be_cmd_req_hdr hdr; 2241 }; 2242 2243 struct be_cmd_resp_get_func_config { 2244 struct be_cmd_resp_hdr hdr; 2245 u32 desc_count; 2246 u8 func_param[MAX_RESOURCE_DESC * RESOURCE_DESC_SIZE_V1]; 2247 }; 2248 2249 enum { 2250 RESOURCE_LIMITS, 2251 RESOURCE_MODIFIABLE 2252 }; 2253 2254 struct be_cmd_req_get_profile_config { 2255 struct be_cmd_req_hdr hdr; 2256 u8 rsvd; 2257 #define ACTIVE_PROFILE_TYPE 0x2 2258 #define SAVED_PROFILE_TYPE 0x0 2259 #define QUERY_MODIFIABLE_FIELDS_TYPE BIT(3) 2260 u8 type; 2261 u16 rsvd1; 2262 }; 2263 2264 struct be_cmd_resp_get_profile_config { 2265 struct be_cmd_resp_hdr hdr; 2266 __le16 desc_count; 2267 u16 rsvd; 2268 u8 func_param[MAX_RESOURCE_DESC * RESOURCE_DESC_SIZE_V1]; 2269 }; 2270 2271 #define FIELD_MODIFIABLE 0xFFFF 2272 struct be_cmd_req_set_profile_config { 2273 struct be_cmd_req_hdr hdr; 2274 u32 rsvd; 2275 u32 desc_count; 2276 u8 desc[2 * RESOURCE_DESC_SIZE_V1]; 2277 } __packed; 2278 2279 struct be_cmd_req_get_active_profile { 2280 struct be_cmd_req_hdr hdr; 2281 u32 rsvd; 2282 } __packed; 2283 2284 struct be_cmd_resp_get_active_profile { 2285 struct be_cmd_resp_hdr hdr; 2286 u16 active_profile_id; 2287 u16 next_profile_id; 2288 } __packed; 2289 2290 struct be_cmd_enable_disable_vf { 2291 struct be_cmd_req_hdr hdr; 2292 u8 enable; 2293 u8 rsvd[3]; 2294 }; 2295 2296 struct be_cmd_req_intr_set { 2297 struct be_cmd_req_hdr hdr; 2298 u8 intr_enabled; 2299 u8 rsvd[3]; 2300 }; 2301 2302 static inline bool check_privilege(struct be_adapter *adapter, u32 flags) 2303 { 2304 return flags & adapter->cmd_privileges ? true : false; 2305 } 2306 2307 /************** Get IFACE LIST *******************/ 2308 struct be_if_desc { 2309 u32 if_id; 2310 u32 cap_flags; 2311 u32 en_flags; 2312 }; 2313 2314 struct be_cmd_req_get_iface_list { 2315 struct be_cmd_req_hdr hdr; 2316 }; 2317 2318 struct be_cmd_resp_get_iface_list { 2319 struct be_cmd_req_hdr hdr; 2320 u32 if_cnt; 2321 struct be_if_desc if_desc; 2322 }; 2323 2324 /************** Set Features *******************/ 2325 #define BE_FEATURE_UE_RECOVERY 0x10 2326 #define BE_UE_RECOVERY_UER_MASK 0x1 2327 2328 struct be_req_ue_recovery { 2329 u32 uer; 2330 u32 rsvd; 2331 }; 2332 2333 struct be_cmd_req_set_features { 2334 struct be_cmd_req_hdr hdr; 2335 u32 features; 2336 u32 parameter_len; 2337 union { 2338 struct be_req_ue_recovery req; 2339 u32 rsvd[2]; 2340 } parameter; 2341 }; 2342 2343 struct be_resp_ue_recovery { 2344 u32 uer; 2345 u16 ue2rp; 2346 u16 ue2sr; 2347 }; 2348 2349 struct be_cmd_resp_set_features { 2350 struct be_cmd_resp_hdr hdr; 2351 u32 features; 2352 u32 parameter_len; 2353 union { 2354 struct be_resp_ue_recovery resp; 2355 u32 rsvd[2]; 2356 } parameter; 2357 }; 2358 2359 /*************** Set logical link ********************/ 2360 #define PLINK_ENABLE BIT(0) 2361 #define PLINK_TRACK BIT(8) 2362 struct be_cmd_req_set_ll_link { 2363 struct be_cmd_req_hdr hdr; 2364 u32 link_config; /* Bit 0: UP_DOWN, Bit 9: PLINK */ 2365 }; 2366 2367 /************** Manage IFACE Filters *******************/ 2368 #define OP_CONVERT_NORMAL_TO_TUNNEL 0 2369 #define OP_CONVERT_TUNNEL_TO_NORMAL 1 2370 2371 struct be_cmd_req_manage_iface_filters { 2372 struct be_cmd_req_hdr hdr; 2373 u8 op; 2374 u8 rsvd0; 2375 u8 flags; 2376 u8 rsvd1; 2377 u32 tunnel_iface_id; 2378 u32 target_iface_id; 2379 u8 mac[6]; 2380 u16 vlan_tag; 2381 u32 tenant_id; 2382 u32 filter_id; 2383 u32 cap_flags; 2384 u32 cap_control_flags; 2385 } __packed; 2386 2387 u16 be_POST_stage_get(struct be_adapter *adapter); 2388 int be_pci_fnum_get(struct be_adapter *adapter); 2389 int be_fw_wait_ready(struct be_adapter *adapter); 2390 int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr, 2391 bool permanent, u32 if_handle, u32 pmac_id); 2392 int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr, u32 if_id, 2393 u32 *pmac_id, u32 domain); 2394 int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, int pmac_id, 2395 u32 domain); 2396 int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags, 2397 u32 *if_handle, u32 domain); 2398 int be_cmd_if_destroy(struct be_adapter *adapter, int if_handle, u32 domain); 2399 int be_cmd_eq_create(struct be_adapter *adapter, struct be_eq_obj *eqo); 2400 int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq, 2401 struct be_queue_info *eq, bool no_delay, 2402 int num_cqe_dma_coalesce); 2403 int be_cmd_mccq_create(struct be_adapter *adapter, struct be_queue_info *mccq, 2404 struct be_queue_info *cq); 2405 int be_cmd_txq_create(struct be_adapter *adapter, struct be_tx_obj *txo); 2406 int be_cmd_rxq_create(struct be_adapter *adapter, struct be_queue_info *rxq, 2407 u16 cq_id, u16 frag_size, u32 if_id, u32 rss, u8 *rss_id); 2408 int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q, 2409 int type); 2410 int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q); 2411 int be_cmd_link_status_query(struct be_adapter *adapter, u16 *link_speed, 2412 u8 *link_status, u32 dom); 2413 int be_cmd_reset(struct be_adapter *adapter); 2414 int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd); 2415 int lancer_cmd_get_pport_stats(struct be_adapter *adapter, 2416 struct be_dma_mem *nonemb_cmd); 2417 int be_cmd_get_fw_ver(struct be_adapter *adapter); 2418 int be_cmd_modify_eqd(struct be_adapter *adapter, struct be_set_eqd *, int num); 2419 int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array, 2420 u32 num, u32 domain); 2421 int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 status); 2422 int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc); 2423 int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc); 2424 int be_cmd_query_fw_cfg(struct be_adapter *adapter); 2425 int be_cmd_reset_function(struct be_adapter *adapter); 2426 int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable, 2427 u32 rss_hash_opts, u16 table_size, const u8 *rss_hkey); 2428 int be_process_mcc(struct be_adapter *adapter); 2429 int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num, u8 beacon, 2430 u8 status, u8 state); 2431 int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, 2432 u32 *state); 2433 int be_cmd_read_port_transceiver_data(struct be_adapter *adapter, 2434 u8 page_num, u8 *data); 2435 int be_cmd_query_cable_type(struct be_adapter *adapter); 2436 int be_cmd_query_sfp_info(struct be_adapter *adapter); 2437 int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd, 2438 u32 data_size, u32 data_offset, const char *obj_name, 2439 u32 *data_read, u32 *eof, u8 *addn_status); 2440 int lancer_fw_download(struct be_adapter *adapter, const struct firmware *fw); 2441 int be_fw_download(struct be_adapter *adapter, const struct firmware *fw); 2442 int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac, 2443 struct be_dma_mem *nonemb_cmd); 2444 int be_cmd_fw_init(struct be_adapter *adapter); 2445 int be_cmd_fw_clean(struct be_adapter *adapter); 2446 void be_async_mcc_enable(struct be_adapter *adapter); 2447 void be_async_mcc_disable(struct be_adapter *adapter); 2448 int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num, 2449 u32 loopback_type, u32 pkt_size, u32 num_pkts, 2450 u64 pattern); 2451 int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern, u32 byte_cnt, 2452 struct be_dma_mem *cmd); 2453 int be_cmd_get_seeprom_data(struct be_adapter *adapter, 2454 struct be_dma_mem *nonemb_cmd); 2455 int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num, 2456 u8 loopback_type, u8 enable); 2457 int be_cmd_get_phy_info(struct be_adapter *adapter); 2458 int be_cmd_config_qos(struct be_adapter *adapter, u32 max_rate, 2459 u16 link_speed, u8 domain); 2460 void be_detect_error(struct be_adapter *adapter); 2461 int be_cmd_get_die_temperature(struct be_adapter *adapter); 2462 int be_cmd_get_cntl_attributes(struct be_adapter *adapter); 2463 int be_cmd_get_fat_dump_len(struct be_adapter *adapter, u32 *dump_size); 2464 int be_cmd_get_fat_dump(struct be_adapter *adapter, u32 buf_len, void *buf); 2465 int be_cmd_req_native_mode(struct be_adapter *adapter); 2466 int be_cmd_get_fn_privileges(struct be_adapter *adapter, u32 *privilege, 2467 u32 domain); 2468 int be_cmd_set_fn_privileges(struct be_adapter *adapter, u32 privileges, 2469 u32 vf_num); 2470 int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac, 2471 bool *pmac_id_active, u32 *pmac_id, 2472 u32 if_handle, u8 domain); 2473 int be_cmd_get_active_mac(struct be_adapter *adapter, u32 pmac_id, u8 *mac, 2474 u32 if_handle, bool active, u32 domain); 2475 int be_cmd_get_perm_mac(struct be_adapter *adapter, u8 *mac); 2476 int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array, u8 mac_count, 2477 u32 domain); 2478 int be_cmd_set_mac(struct be_adapter *adapter, u8 *mac, int if_id, u32 dom); 2479 int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid, u32 domain, 2480 u16 intf_id, u16 hsw_mode, u8 spoofchk); 2481 int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid, u32 domain, 2482 u16 intf_id, u8 *mode, bool *spoofchk); 2483 int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter); 2484 int be_cmd_set_fw_log_level(struct be_adapter *adapter, u32 level); 2485 int be_cmd_get_fw_log_level(struct be_adapter *adapter); 2486 int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter, 2487 struct be_dma_mem *cmd); 2488 int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter, 2489 struct be_dma_mem *cmd, 2490 struct be_fat_conf_params *cfgs); 2491 int lancer_physdev_ctrl(struct be_adapter *adapter, u32 mask); 2492 int lancer_initiate_dump(struct be_adapter *adapter); 2493 int lancer_delete_dump(struct be_adapter *adapter); 2494 bool dump_present(struct be_adapter *adapter); 2495 int lancer_test_and_set_rdy_state(struct be_adapter *adapter); 2496 int be_cmd_query_port_name(struct be_adapter *adapter); 2497 int be_cmd_get_func_config(struct be_adapter *adapter, 2498 struct be_resources *res); 2499 int be_cmd_get_profile_config(struct be_adapter *adapter, 2500 struct be_resources *res, 2501 struct be_port_resources *port_res, 2502 u8 profile_type, u8 query, u8 domain); 2503 int be_cmd_get_active_profile(struct be_adapter *adapter, u16 *profile); 2504 int be_cmd_get_if_id(struct be_adapter *adapter, struct be_vf_cfg *vf_cfg, 2505 int vf_num); 2506 int be_cmd_enable_vf(struct be_adapter *adapter, u8 domain); 2507 int be_cmd_intr_set(struct be_adapter *adapter, bool intr_enable); 2508 int be_cmd_set_logical_link_config(struct be_adapter *adapter, 2509 int link_state, u8 domain); 2510 int be_cmd_set_vxlan_port(struct be_adapter *adapter, __be16 port); 2511 int be_cmd_manage_iface(struct be_adapter *adapter, u32 iface, u8 op); 2512 int be_cmd_set_sriov_config(struct be_adapter *adapter, 2513 struct be_resources res, u16 num_vfs, 2514 struct be_resources *vft_res); 2515 int be_cmd_set_features(struct be_adapter *adapter); 2516