19aebddd1SJeff Kirsher /* 29aebddd1SJeff Kirsher * Copyright (C) 2005 - 2011 Emulex 39aebddd1SJeff Kirsher * All rights reserved. 49aebddd1SJeff Kirsher * 59aebddd1SJeff Kirsher * This program is free software; you can redistribute it and/or 69aebddd1SJeff Kirsher * modify it under the terms of the GNU General Public License version 2 79aebddd1SJeff Kirsher * as published by the Free Software Foundation. The full GNU General 89aebddd1SJeff Kirsher * Public License is included in this distribution in the file called COPYING. 99aebddd1SJeff Kirsher * 109aebddd1SJeff Kirsher * Contact Information: 119aebddd1SJeff Kirsher * linux-drivers@emulex.com 129aebddd1SJeff Kirsher * 139aebddd1SJeff Kirsher * Emulex 149aebddd1SJeff Kirsher * 3333 Susan Street 159aebddd1SJeff Kirsher * Costa Mesa, CA 92626 169aebddd1SJeff Kirsher */ 179aebddd1SJeff Kirsher 189aebddd1SJeff Kirsher /* 199aebddd1SJeff Kirsher * The driver sends configuration and managements command requests to the 209aebddd1SJeff Kirsher * firmware in the BE. These requests are communicated to the processor 219aebddd1SJeff Kirsher * using Work Request Blocks (WRBs) submitted to the MCC-WRB ring or via one 229aebddd1SJeff Kirsher * WRB inside a MAILBOX. 239aebddd1SJeff Kirsher * The commands are serviced by the ARM processor in the BladeEngine's MPU. 249aebddd1SJeff Kirsher */ 259aebddd1SJeff Kirsher 269aebddd1SJeff Kirsher struct be_sge { 279aebddd1SJeff Kirsher u32 pa_lo; 289aebddd1SJeff Kirsher u32 pa_hi; 299aebddd1SJeff Kirsher u32 len; 309aebddd1SJeff Kirsher }; 319aebddd1SJeff Kirsher 329aebddd1SJeff Kirsher #define MCC_WRB_EMBEDDED_MASK 1 /* bit 0 of dword 0*/ 339aebddd1SJeff Kirsher #define MCC_WRB_SGE_CNT_SHIFT 3 /* bits 3 - 7 of dword 0 */ 349aebddd1SJeff Kirsher #define MCC_WRB_SGE_CNT_MASK 0x1F /* bits 3 - 7 of dword 0 */ 359aebddd1SJeff Kirsher struct be_mcc_wrb { 369aebddd1SJeff Kirsher u32 embedded; /* dword 0 */ 379aebddd1SJeff Kirsher u32 payload_length; /* dword 1 */ 389aebddd1SJeff Kirsher u32 tag0; /* dword 2 */ 399aebddd1SJeff Kirsher u32 tag1; /* dword 3 */ 409aebddd1SJeff Kirsher u32 rsvd; /* dword 4 */ 419aebddd1SJeff Kirsher union { 429aebddd1SJeff Kirsher u8 embedded_payload[236]; /* used by embedded cmds */ 439aebddd1SJeff Kirsher struct be_sge sgl[19]; /* used by non-embedded cmds */ 449aebddd1SJeff Kirsher } payload; 459aebddd1SJeff Kirsher }; 469aebddd1SJeff Kirsher 479aebddd1SJeff Kirsher #define CQE_FLAGS_VALID_MASK (1 << 31) 489aebddd1SJeff Kirsher #define CQE_FLAGS_ASYNC_MASK (1 << 30) 499aebddd1SJeff Kirsher #define CQE_FLAGS_COMPLETED_MASK (1 << 28) 509aebddd1SJeff Kirsher #define CQE_FLAGS_CONSUMED_MASK (1 << 27) 519aebddd1SJeff Kirsher 529aebddd1SJeff Kirsher /* Completion Status */ 539aebddd1SJeff Kirsher enum { 549aebddd1SJeff Kirsher MCC_STATUS_SUCCESS = 0, 559aebddd1SJeff Kirsher MCC_STATUS_FAILED = 1, 569aebddd1SJeff Kirsher MCC_STATUS_ILLEGAL_REQUEST = 2, 579aebddd1SJeff Kirsher MCC_STATUS_ILLEGAL_FIELD = 3, 589aebddd1SJeff Kirsher MCC_STATUS_INSUFFICIENT_BUFFER = 4, 599aebddd1SJeff Kirsher MCC_STATUS_UNAUTHORIZED_REQUEST = 5, 609aebddd1SJeff Kirsher MCC_STATUS_NOT_SUPPORTED = 66 619aebddd1SJeff Kirsher }; 629aebddd1SJeff Kirsher 639aebddd1SJeff Kirsher #define CQE_STATUS_COMPL_MASK 0xFFFF 649aebddd1SJeff Kirsher #define CQE_STATUS_COMPL_SHIFT 0 /* bits 0 - 15 */ 659aebddd1SJeff Kirsher #define CQE_STATUS_EXTD_MASK 0xFFFF 669aebddd1SJeff Kirsher #define CQE_STATUS_EXTD_SHIFT 16 /* bits 16 - 31 */ 679aebddd1SJeff Kirsher 689aebddd1SJeff Kirsher struct be_mcc_compl { 699aebddd1SJeff Kirsher u32 status; /* dword 0 */ 709aebddd1SJeff Kirsher u32 tag0; /* dword 1 */ 719aebddd1SJeff Kirsher u32 tag1; /* dword 2 */ 729aebddd1SJeff Kirsher u32 flags; /* dword 3 */ 739aebddd1SJeff Kirsher }; 749aebddd1SJeff Kirsher 759aebddd1SJeff Kirsher /* When the async bit of mcc_compl is set, the last 4 bytes of 769aebddd1SJeff Kirsher * mcc_compl is interpreted as follows: 779aebddd1SJeff Kirsher */ 789aebddd1SJeff Kirsher #define ASYNC_TRAILER_EVENT_CODE_SHIFT 8 /* bits 8 - 15 */ 799aebddd1SJeff Kirsher #define ASYNC_TRAILER_EVENT_CODE_MASK 0xFF 809aebddd1SJeff Kirsher #define ASYNC_TRAILER_EVENT_TYPE_SHIFT 16 819aebddd1SJeff Kirsher #define ASYNC_TRAILER_EVENT_TYPE_MASK 0xFF 829aebddd1SJeff Kirsher #define ASYNC_EVENT_CODE_LINK_STATE 0x1 839aebddd1SJeff Kirsher #define ASYNC_EVENT_CODE_GRP_5 0x5 849aebddd1SJeff Kirsher #define ASYNC_EVENT_QOS_SPEED 0x1 859aebddd1SJeff Kirsher #define ASYNC_EVENT_COS_PRIORITY 0x2 869aebddd1SJeff Kirsher #define ASYNC_EVENT_PVID_STATE 0x3 879aebddd1SJeff Kirsher struct be_async_event_trailer { 889aebddd1SJeff Kirsher u32 code; 899aebddd1SJeff Kirsher }; 909aebddd1SJeff Kirsher 919aebddd1SJeff Kirsher enum { 929aebddd1SJeff Kirsher LINK_DOWN = 0x0, 939aebddd1SJeff Kirsher LINK_UP = 0x1 949aebddd1SJeff Kirsher }; 959aebddd1SJeff Kirsher #define LINK_STATUS_MASK 0x1 962e177a5cSPadmanabh Ratnakar #define LOGICAL_LINK_STATUS_MASK 0x2 979aebddd1SJeff Kirsher 989aebddd1SJeff Kirsher /* When the event code of an async trailer is link-state, the mcc_compl 999aebddd1SJeff Kirsher * must be interpreted as follows 1009aebddd1SJeff Kirsher */ 1019aebddd1SJeff Kirsher struct be_async_event_link_state { 1029aebddd1SJeff Kirsher u8 physical_port; 1039aebddd1SJeff Kirsher u8 port_link_status; 1049aebddd1SJeff Kirsher u8 port_duplex; 1059aebddd1SJeff Kirsher u8 port_speed; 1069aebddd1SJeff Kirsher u8 port_fault; 1079aebddd1SJeff Kirsher u8 rsvd0[7]; 1089aebddd1SJeff Kirsher struct be_async_event_trailer trailer; 1099aebddd1SJeff Kirsher } __packed; 1109aebddd1SJeff Kirsher 1119aebddd1SJeff Kirsher /* When the event code of an async trailer is GRP-5 and event_type is QOS_SPEED 1129aebddd1SJeff Kirsher * the mcc_compl must be interpreted as follows 1139aebddd1SJeff Kirsher */ 1149aebddd1SJeff Kirsher struct be_async_event_grp5_qos_link_speed { 1159aebddd1SJeff Kirsher u8 physical_port; 1169aebddd1SJeff Kirsher u8 rsvd[5]; 1179aebddd1SJeff Kirsher u16 qos_link_speed; 1189aebddd1SJeff Kirsher u32 event_tag; 1199aebddd1SJeff Kirsher struct be_async_event_trailer trailer; 1209aebddd1SJeff Kirsher } __packed; 1219aebddd1SJeff Kirsher 1229aebddd1SJeff Kirsher /* When the event code of an async trailer is GRP5 and event type is 1239aebddd1SJeff Kirsher * CoS-Priority, the mcc_compl must be interpreted as follows 1249aebddd1SJeff Kirsher */ 1259aebddd1SJeff Kirsher struct be_async_event_grp5_cos_priority { 1269aebddd1SJeff Kirsher u8 physical_port; 1279aebddd1SJeff Kirsher u8 available_priority_bmap; 1289aebddd1SJeff Kirsher u8 reco_default_priority; 1299aebddd1SJeff Kirsher u8 valid; 1309aebddd1SJeff Kirsher u8 rsvd0; 1319aebddd1SJeff Kirsher u8 event_tag; 1329aebddd1SJeff Kirsher struct be_async_event_trailer trailer; 1339aebddd1SJeff Kirsher } __packed; 1349aebddd1SJeff Kirsher 1359aebddd1SJeff Kirsher /* When the event code of an async trailer is GRP5 and event type is 1369aebddd1SJeff Kirsher * PVID state, the mcc_compl must be interpreted as follows 1379aebddd1SJeff Kirsher */ 1389aebddd1SJeff Kirsher struct be_async_event_grp5_pvid_state { 1399aebddd1SJeff Kirsher u8 enabled; 1409aebddd1SJeff Kirsher u8 rsvd0; 1419aebddd1SJeff Kirsher u16 tag; 1429aebddd1SJeff Kirsher u32 event_tag; 1439aebddd1SJeff Kirsher u32 rsvd1; 1449aebddd1SJeff Kirsher struct be_async_event_trailer trailer; 1459aebddd1SJeff Kirsher } __packed; 1469aebddd1SJeff Kirsher 1479aebddd1SJeff Kirsher struct be_mcc_mailbox { 1489aebddd1SJeff Kirsher struct be_mcc_wrb wrb; 1499aebddd1SJeff Kirsher struct be_mcc_compl compl; 1509aebddd1SJeff Kirsher }; 1519aebddd1SJeff Kirsher 1529aebddd1SJeff Kirsher #define CMD_SUBSYSTEM_COMMON 0x1 1539aebddd1SJeff Kirsher #define CMD_SUBSYSTEM_ETH 0x3 1549aebddd1SJeff Kirsher #define CMD_SUBSYSTEM_LOWLEVEL 0xb 1559aebddd1SJeff Kirsher 1569aebddd1SJeff Kirsher #define OPCODE_COMMON_NTWK_MAC_QUERY 1 1579aebddd1SJeff Kirsher #define OPCODE_COMMON_NTWK_MAC_SET 2 1589aebddd1SJeff Kirsher #define OPCODE_COMMON_NTWK_MULTICAST_SET 3 1599aebddd1SJeff Kirsher #define OPCODE_COMMON_NTWK_VLAN_CONFIG 4 1609aebddd1SJeff Kirsher #define OPCODE_COMMON_NTWK_LINK_STATUS_QUERY 5 1619aebddd1SJeff Kirsher #define OPCODE_COMMON_READ_FLASHROM 6 1629aebddd1SJeff Kirsher #define OPCODE_COMMON_WRITE_FLASHROM 7 1639aebddd1SJeff Kirsher #define OPCODE_COMMON_CQ_CREATE 12 1649aebddd1SJeff Kirsher #define OPCODE_COMMON_EQ_CREATE 13 1659aebddd1SJeff Kirsher #define OPCODE_COMMON_MCC_CREATE 21 1669aebddd1SJeff Kirsher #define OPCODE_COMMON_SET_QOS 28 1679aebddd1SJeff Kirsher #define OPCODE_COMMON_MCC_CREATE_EXT 90 1689aebddd1SJeff Kirsher #define OPCODE_COMMON_SEEPROM_READ 30 1699aebddd1SJeff Kirsher #define OPCODE_COMMON_GET_CNTL_ATTRIBUTES 32 1709aebddd1SJeff Kirsher #define OPCODE_COMMON_NTWK_RX_FILTER 34 1719aebddd1SJeff Kirsher #define OPCODE_COMMON_GET_FW_VERSION 35 1729aebddd1SJeff Kirsher #define OPCODE_COMMON_SET_FLOW_CONTROL 36 1739aebddd1SJeff Kirsher #define OPCODE_COMMON_GET_FLOW_CONTROL 37 1749aebddd1SJeff Kirsher #define OPCODE_COMMON_SET_FRAME_SIZE 39 1759aebddd1SJeff Kirsher #define OPCODE_COMMON_MODIFY_EQ_DELAY 41 1769aebddd1SJeff Kirsher #define OPCODE_COMMON_FIRMWARE_CONFIG 42 1779aebddd1SJeff Kirsher #define OPCODE_COMMON_NTWK_INTERFACE_CREATE 50 1789aebddd1SJeff Kirsher #define OPCODE_COMMON_NTWK_INTERFACE_DESTROY 51 1799aebddd1SJeff Kirsher #define OPCODE_COMMON_MCC_DESTROY 53 1809aebddd1SJeff Kirsher #define OPCODE_COMMON_CQ_DESTROY 54 1819aebddd1SJeff Kirsher #define OPCODE_COMMON_EQ_DESTROY 55 1829aebddd1SJeff Kirsher #define OPCODE_COMMON_QUERY_FIRMWARE_CONFIG 58 1839aebddd1SJeff Kirsher #define OPCODE_COMMON_NTWK_PMAC_ADD 59 1849aebddd1SJeff Kirsher #define OPCODE_COMMON_NTWK_PMAC_DEL 60 1859aebddd1SJeff Kirsher #define OPCODE_COMMON_FUNCTION_RESET 61 1869aebddd1SJeff Kirsher #define OPCODE_COMMON_MANAGE_FAT 68 1879aebddd1SJeff Kirsher #define OPCODE_COMMON_ENABLE_DISABLE_BEACON 69 1889aebddd1SJeff Kirsher #define OPCODE_COMMON_GET_BEACON_STATE 70 1899aebddd1SJeff Kirsher #define OPCODE_COMMON_READ_TRANSRECV_DATA 73 190b4e32a71SPadmanabh Ratnakar #define OPCODE_COMMON_GET_PORT_NAME 77 1919aebddd1SJeff Kirsher #define OPCODE_COMMON_GET_PHY_DETAILS 102 1929aebddd1SJeff Kirsher #define OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP 103 1939aebddd1SJeff Kirsher #define OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES 121 194941a77d5SSomnath Kotur #define OPCODE_COMMON_GET_EXT_FAT_CAPABILITES 125 195941a77d5SSomnath Kotur #define OPCODE_COMMON_SET_EXT_FAT_CAPABILITES 126 196590c391dSPadmanabh Ratnakar #define OPCODE_COMMON_GET_MAC_LIST 147 197590c391dSPadmanabh Ratnakar #define OPCODE_COMMON_SET_MAC_LIST 148 198f1f3ee1bSAjit Khaparde #define OPCODE_COMMON_GET_HSW_CONFIG 152 199f1f3ee1bSAjit Khaparde #define OPCODE_COMMON_SET_HSW_CONFIG 153 200de49bd5aSPadmanabh Ratnakar #define OPCODE_COMMON_READ_OBJECT 171 2019aebddd1SJeff Kirsher #define OPCODE_COMMON_WRITE_OBJECT 172 2029aebddd1SJeff Kirsher 2039aebddd1SJeff Kirsher #define OPCODE_ETH_RSS_CONFIG 1 2049aebddd1SJeff Kirsher #define OPCODE_ETH_ACPI_CONFIG 2 2059aebddd1SJeff Kirsher #define OPCODE_ETH_PROMISCUOUS 3 2069aebddd1SJeff Kirsher #define OPCODE_ETH_GET_STATISTICS 4 2079aebddd1SJeff Kirsher #define OPCODE_ETH_TX_CREATE 7 2089aebddd1SJeff Kirsher #define OPCODE_ETH_RX_CREATE 8 2099aebddd1SJeff Kirsher #define OPCODE_ETH_TX_DESTROY 9 2109aebddd1SJeff Kirsher #define OPCODE_ETH_RX_DESTROY 10 2119aebddd1SJeff Kirsher #define OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG 12 2129aebddd1SJeff Kirsher #define OPCODE_ETH_GET_PPORT_STATS 18 2139aebddd1SJeff Kirsher 2149aebddd1SJeff Kirsher #define OPCODE_LOWLEVEL_HOST_DDR_DMA 17 2159aebddd1SJeff Kirsher #define OPCODE_LOWLEVEL_LOOPBACK_TEST 18 2169aebddd1SJeff Kirsher #define OPCODE_LOWLEVEL_SET_LOOPBACK_MODE 19 2179aebddd1SJeff Kirsher 2189aebddd1SJeff Kirsher struct be_cmd_req_hdr { 2199aebddd1SJeff Kirsher u8 opcode; /* dword 0 */ 2209aebddd1SJeff Kirsher u8 subsystem; /* dword 0 */ 2219aebddd1SJeff Kirsher u8 port_number; /* dword 0 */ 2229aebddd1SJeff Kirsher u8 domain; /* dword 0 */ 2239aebddd1SJeff Kirsher u32 timeout; /* dword 1 */ 2249aebddd1SJeff Kirsher u32 request_length; /* dword 2 */ 2259aebddd1SJeff Kirsher u8 version; /* dword 3 */ 2269aebddd1SJeff Kirsher u8 rsvd[3]; /* dword 3 */ 2279aebddd1SJeff Kirsher }; 2289aebddd1SJeff Kirsher 2299aebddd1SJeff Kirsher #define RESP_HDR_INFO_OPCODE_SHIFT 0 /* bits 0 - 7 */ 2309aebddd1SJeff Kirsher #define RESP_HDR_INFO_SUBSYS_SHIFT 8 /* bits 8 - 15 */ 2319aebddd1SJeff Kirsher struct be_cmd_resp_hdr { 232652bf646SPadmanabh Ratnakar u8 opcode; /* dword 0 */ 233652bf646SPadmanabh Ratnakar u8 subsystem; /* dword 0 */ 234652bf646SPadmanabh Ratnakar u8 rsvd[2]; /* dword 0 */ 235652bf646SPadmanabh Ratnakar u8 status; /* dword 1 */ 236652bf646SPadmanabh Ratnakar u8 add_status; /* dword 1 */ 237652bf646SPadmanabh Ratnakar u8 rsvd1[2]; /* dword 1 */ 2389aebddd1SJeff Kirsher u32 response_length; /* dword 2 */ 2399aebddd1SJeff Kirsher u32 actual_resp_len; /* dword 3 */ 2409aebddd1SJeff Kirsher }; 2419aebddd1SJeff Kirsher 2429aebddd1SJeff Kirsher struct phys_addr { 2439aebddd1SJeff Kirsher u32 lo; 2449aebddd1SJeff Kirsher u32 hi; 2459aebddd1SJeff Kirsher }; 2469aebddd1SJeff Kirsher 2479aebddd1SJeff Kirsher /************************** 2489aebddd1SJeff Kirsher * BE Command definitions * 2499aebddd1SJeff Kirsher **************************/ 2509aebddd1SJeff Kirsher 2519aebddd1SJeff Kirsher /* Pseudo amap definition in which each bit of the actual structure is defined 2529aebddd1SJeff Kirsher * as a byte: used to calculate offset/shift/mask of each field */ 2539aebddd1SJeff Kirsher struct amap_eq_context { 2549aebddd1SJeff Kirsher u8 cidx[13]; /* dword 0*/ 2559aebddd1SJeff Kirsher u8 rsvd0[3]; /* dword 0*/ 2569aebddd1SJeff Kirsher u8 epidx[13]; /* dword 0*/ 2579aebddd1SJeff Kirsher u8 valid; /* dword 0*/ 2589aebddd1SJeff Kirsher u8 rsvd1; /* dword 0*/ 2599aebddd1SJeff Kirsher u8 size; /* dword 0*/ 2609aebddd1SJeff Kirsher u8 pidx[13]; /* dword 1*/ 2619aebddd1SJeff Kirsher u8 rsvd2[3]; /* dword 1*/ 2629aebddd1SJeff Kirsher u8 pd[10]; /* dword 1*/ 2639aebddd1SJeff Kirsher u8 count[3]; /* dword 1*/ 2649aebddd1SJeff Kirsher u8 solevent; /* dword 1*/ 2659aebddd1SJeff Kirsher u8 stalled; /* dword 1*/ 2669aebddd1SJeff Kirsher u8 armed; /* dword 1*/ 2679aebddd1SJeff Kirsher u8 rsvd3[4]; /* dword 2*/ 2689aebddd1SJeff Kirsher u8 func[8]; /* dword 2*/ 2699aebddd1SJeff Kirsher u8 rsvd4; /* dword 2*/ 2709aebddd1SJeff Kirsher u8 delaymult[10]; /* dword 2*/ 2719aebddd1SJeff Kirsher u8 rsvd5[2]; /* dword 2*/ 2729aebddd1SJeff Kirsher u8 phase[2]; /* dword 2*/ 2739aebddd1SJeff Kirsher u8 nodelay; /* dword 2*/ 2749aebddd1SJeff Kirsher u8 rsvd6[4]; /* dword 2*/ 2759aebddd1SJeff Kirsher u8 rsvd7[32]; /* dword 3*/ 2769aebddd1SJeff Kirsher } __packed; 2779aebddd1SJeff Kirsher 2789aebddd1SJeff Kirsher struct be_cmd_req_eq_create { 2799aebddd1SJeff Kirsher struct be_cmd_req_hdr hdr; 2809aebddd1SJeff Kirsher u16 num_pages; /* sword */ 2819aebddd1SJeff Kirsher u16 rsvd0; /* sword */ 2829aebddd1SJeff Kirsher u8 context[sizeof(struct amap_eq_context) / 8]; 2839aebddd1SJeff Kirsher struct phys_addr pages[8]; 2849aebddd1SJeff Kirsher } __packed; 2859aebddd1SJeff Kirsher 2869aebddd1SJeff Kirsher struct be_cmd_resp_eq_create { 2879aebddd1SJeff Kirsher struct be_cmd_resp_hdr resp_hdr; 2889aebddd1SJeff Kirsher u16 eq_id; /* sword */ 2899aebddd1SJeff Kirsher u16 rsvd0; /* sword */ 2909aebddd1SJeff Kirsher } __packed; 2919aebddd1SJeff Kirsher 2929aebddd1SJeff Kirsher /******************** Mac query ***************************/ 2939aebddd1SJeff Kirsher enum { 2949aebddd1SJeff Kirsher MAC_ADDRESS_TYPE_STORAGE = 0x0, 2959aebddd1SJeff Kirsher MAC_ADDRESS_TYPE_NETWORK = 0x1, 2969aebddd1SJeff Kirsher MAC_ADDRESS_TYPE_PD = 0x2, 2979aebddd1SJeff Kirsher MAC_ADDRESS_TYPE_MANAGEMENT = 0x3 2989aebddd1SJeff Kirsher }; 2999aebddd1SJeff Kirsher 3009aebddd1SJeff Kirsher struct mac_addr { 3019aebddd1SJeff Kirsher u16 size_of_struct; 3029aebddd1SJeff Kirsher u8 addr[ETH_ALEN]; 3039aebddd1SJeff Kirsher } __packed; 3049aebddd1SJeff Kirsher 3059aebddd1SJeff Kirsher struct be_cmd_req_mac_query { 3069aebddd1SJeff Kirsher struct be_cmd_req_hdr hdr; 3079aebddd1SJeff Kirsher u8 type; 3089aebddd1SJeff Kirsher u8 permanent; 3099aebddd1SJeff Kirsher u16 if_id; 310590c391dSPadmanabh Ratnakar u32 pmac_id; 3119aebddd1SJeff Kirsher } __packed; 3129aebddd1SJeff Kirsher 3139aebddd1SJeff Kirsher struct be_cmd_resp_mac_query { 3149aebddd1SJeff Kirsher struct be_cmd_resp_hdr hdr; 3159aebddd1SJeff Kirsher struct mac_addr mac; 3169aebddd1SJeff Kirsher }; 3179aebddd1SJeff Kirsher 3189aebddd1SJeff Kirsher /******************** PMac Add ***************************/ 3199aebddd1SJeff Kirsher struct be_cmd_req_pmac_add { 3209aebddd1SJeff Kirsher struct be_cmd_req_hdr hdr; 3219aebddd1SJeff Kirsher u32 if_id; 3229aebddd1SJeff Kirsher u8 mac_address[ETH_ALEN]; 3239aebddd1SJeff Kirsher u8 rsvd0[2]; 3249aebddd1SJeff Kirsher } __packed; 3259aebddd1SJeff Kirsher 3269aebddd1SJeff Kirsher struct be_cmd_resp_pmac_add { 3279aebddd1SJeff Kirsher struct be_cmd_resp_hdr hdr; 3289aebddd1SJeff Kirsher u32 pmac_id; 3299aebddd1SJeff Kirsher }; 3309aebddd1SJeff Kirsher 3319aebddd1SJeff Kirsher /******************** PMac Del ***************************/ 3329aebddd1SJeff Kirsher struct be_cmd_req_pmac_del { 3339aebddd1SJeff Kirsher struct be_cmd_req_hdr hdr; 3349aebddd1SJeff Kirsher u32 if_id; 3359aebddd1SJeff Kirsher u32 pmac_id; 3369aebddd1SJeff Kirsher }; 3379aebddd1SJeff Kirsher 3389aebddd1SJeff Kirsher /******************** Create CQ ***************************/ 3399aebddd1SJeff Kirsher /* Pseudo amap definition in which each bit of the actual structure is defined 3409aebddd1SJeff Kirsher * as a byte: used to calculate offset/shift/mask of each field */ 3419aebddd1SJeff Kirsher struct amap_cq_context_be { 3429aebddd1SJeff Kirsher u8 cidx[11]; /* dword 0*/ 3439aebddd1SJeff Kirsher u8 rsvd0; /* dword 0*/ 3449aebddd1SJeff Kirsher u8 coalescwm[2]; /* dword 0*/ 3459aebddd1SJeff Kirsher u8 nodelay; /* dword 0*/ 3469aebddd1SJeff Kirsher u8 epidx[11]; /* dword 0*/ 3479aebddd1SJeff Kirsher u8 rsvd1; /* dword 0*/ 3489aebddd1SJeff Kirsher u8 count[2]; /* dword 0*/ 3499aebddd1SJeff Kirsher u8 valid; /* dword 0*/ 3509aebddd1SJeff Kirsher u8 solevent; /* dword 0*/ 3519aebddd1SJeff Kirsher u8 eventable; /* dword 0*/ 3529aebddd1SJeff Kirsher u8 pidx[11]; /* dword 1*/ 3539aebddd1SJeff Kirsher u8 rsvd2; /* dword 1*/ 3549aebddd1SJeff Kirsher u8 pd[10]; /* dword 1*/ 3559aebddd1SJeff Kirsher u8 eqid[8]; /* dword 1*/ 3569aebddd1SJeff Kirsher u8 stalled; /* dword 1*/ 3579aebddd1SJeff Kirsher u8 armed; /* dword 1*/ 3589aebddd1SJeff Kirsher u8 rsvd3[4]; /* dword 2*/ 3599aebddd1SJeff Kirsher u8 func[8]; /* dword 2*/ 3609aebddd1SJeff Kirsher u8 rsvd4[20]; /* dword 2*/ 3619aebddd1SJeff Kirsher u8 rsvd5[32]; /* dword 3*/ 3629aebddd1SJeff Kirsher } __packed; 3639aebddd1SJeff Kirsher 3649aebddd1SJeff Kirsher struct amap_cq_context_lancer { 3659aebddd1SJeff Kirsher u8 rsvd0[12]; /* dword 0*/ 3669aebddd1SJeff Kirsher u8 coalescwm[2]; /* dword 0*/ 3679aebddd1SJeff Kirsher u8 nodelay; /* dword 0*/ 3689aebddd1SJeff Kirsher u8 rsvd1[12]; /* dword 0*/ 3699aebddd1SJeff Kirsher u8 count[2]; /* dword 0*/ 3709aebddd1SJeff Kirsher u8 valid; /* dword 0*/ 3719aebddd1SJeff Kirsher u8 rsvd2; /* dword 0*/ 3729aebddd1SJeff Kirsher u8 eventable; /* dword 0*/ 3739aebddd1SJeff Kirsher u8 eqid[16]; /* dword 1*/ 3749aebddd1SJeff Kirsher u8 rsvd3[15]; /* dword 1*/ 3759aebddd1SJeff Kirsher u8 armed; /* dword 1*/ 3769aebddd1SJeff Kirsher u8 rsvd4[32]; /* dword 2*/ 3779aebddd1SJeff Kirsher u8 rsvd5[32]; /* dword 3*/ 3789aebddd1SJeff Kirsher } __packed; 3799aebddd1SJeff Kirsher 3809aebddd1SJeff Kirsher struct be_cmd_req_cq_create { 3819aebddd1SJeff Kirsher struct be_cmd_req_hdr hdr; 3829aebddd1SJeff Kirsher u16 num_pages; 3839aebddd1SJeff Kirsher u8 page_size; 3849aebddd1SJeff Kirsher u8 rsvd0; 3859aebddd1SJeff Kirsher u8 context[sizeof(struct amap_cq_context_be) / 8]; 3869aebddd1SJeff Kirsher struct phys_addr pages[8]; 3879aebddd1SJeff Kirsher } __packed; 3889aebddd1SJeff Kirsher 3899aebddd1SJeff Kirsher 3909aebddd1SJeff Kirsher struct be_cmd_resp_cq_create { 3919aebddd1SJeff Kirsher struct be_cmd_resp_hdr hdr; 3929aebddd1SJeff Kirsher u16 cq_id; 3939aebddd1SJeff Kirsher u16 rsvd0; 3949aebddd1SJeff Kirsher } __packed; 3959aebddd1SJeff Kirsher 3969aebddd1SJeff Kirsher struct be_cmd_req_get_fat { 3979aebddd1SJeff Kirsher struct be_cmd_req_hdr hdr; 3989aebddd1SJeff Kirsher u32 fat_operation; 3999aebddd1SJeff Kirsher u32 read_log_offset; 4009aebddd1SJeff Kirsher u32 read_log_length; 4019aebddd1SJeff Kirsher u32 data_buffer_size; 4029aebddd1SJeff Kirsher u32 data_buffer[1]; 4039aebddd1SJeff Kirsher } __packed; 4049aebddd1SJeff Kirsher 4059aebddd1SJeff Kirsher struct be_cmd_resp_get_fat { 4069aebddd1SJeff Kirsher struct be_cmd_resp_hdr hdr; 4079aebddd1SJeff Kirsher u32 log_size; 4089aebddd1SJeff Kirsher u32 read_log_length; 4099aebddd1SJeff Kirsher u32 rsvd[2]; 4109aebddd1SJeff Kirsher u32 data_buffer[1]; 4119aebddd1SJeff Kirsher } __packed; 4129aebddd1SJeff Kirsher 4139aebddd1SJeff Kirsher 4149aebddd1SJeff Kirsher /******************** Create MCCQ ***************************/ 4159aebddd1SJeff Kirsher /* Pseudo amap definition in which each bit of the actual structure is defined 4169aebddd1SJeff Kirsher * as a byte: used to calculate offset/shift/mask of each field */ 4179aebddd1SJeff Kirsher struct amap_mcc_context_be { 4189aebddd1SJeff Kirsher u8 con_index[14]; 4199aebddd1SJeff Kirsher u8 rsvd0[2]; 4209aebddd1SJeff Kirsher u8 ring_size[4]; 4219aebddd1SJeff Kirsher u8 fetch_wrb; 4229aebddd1SJeff Kirsher u8 fetch_r2t; 4239aebddd1SJeff Kirsher u8 cq_id[10]; 4249aebddd1SJeff Kirsher u8 prod_index[14]; 4259aebddd1SJeff Kirsher u8 fid[8]; 4269aebddd1SJeff Kirsher u8 pdid[9]; 4279aebddd1SJeff Kirsher u8 valid; 4289aebddd1SJeff Kirsher u8 rsvd1[32]; 4299aebddd1SJeff Kirsher u8 rsvd2[32]; 4309aebddd1SJeff Kirsher } __packed; 4319aebddd1SJeff Kirsher 4329aebddd1SJeff Kirsher struct amap_mcc_context_lancer { 4339aebddd1SJeff Kirsher u8 async_cq_id[16]; 4349aebddd1SJeff Kirsher u8 ring_size[4]; 4359aebddd1SJeff Kirsher u8 rsvd0[12]; 4369aebddd1SJeff Kirsher u8 rsvd1[31]; 4379aebddd1SJeff Kirsher u8 valid; 4389aebddd1SJeff Kirsher u8 async_cq_valid[1]; 4399aebddd1SJeff Kirsher u8 rsvd2[31]; 4409aebddd1SJeff Kirsher u8 rsvd3[32]; 4419aebddd1SJeff Kirsher } __packed; 4429aebddd1SJeff Kirsher 4439aebddd1SJeff Kirsher struct be_cmd_req_mcc_create { 4449aebddd1SJeff Kirsher struct be_cmd_req_hdr hdr; 4459aebddd1SJeff Kirsher u16 num_pages; 4469aebddd1SJeff Kirsher u16 cq_id; 4479aebddd1SJeff Kirsher u8 context[sizeof(struct amap_mcc_context_be) / 8]; 4489aebddd1SJeff Kirsher struct phys_addr pages[8]; 4499aebddd1SJeff Kirsher } __packed; 4509aebddd1SJeff Kirsher 4519aebddd1SJeff Kirsher struct be_cmd_req_mcc_ext_create { 4529aebddd1SJeff Kirsher struct be_cmd_req_hdr hdr; 4539aebddd1SJeff Kirsher u16 num_pages; 4549aebddd1SJeff Kirsher u16 cq_id; 4559aebddd1SJeff Kirsher u32 async_event_bitmap[1]; 4569aebddd1SJeff Kirsher u8 context[sizeof(struct amap_mcc_context_be) / 8]; 4579aebddd1SJeff Kirsher struct phys_addr pages[8]; 4589aebddd1SJeff Kirsher } __packed; 4599aebddd1SJeff Kirsher 4609aebddd1SJeff Kirsher struct be_cmd_resp_mcc_create { 4619aebddd1SJeff Kirsher struct be_cmd_resp_hdr hdr; 4629aebddd1SJeff Kirsher u16 id; 4639aebddd1SJeff Kirsher u16 rsvd0; 4649aebddd1SJeff Kirsher } __packed; 4659aebddd1SJeff Kirsher 4669aebddd1SJeff Kirsher /******************** Create TxQ ***************************/ 4679aebddd1SJeff Kirsher #define BE_ETH_TX_RING_TYPE_STANDARD 2 4689aebddd1SJeff Kirsher #define BE_ULP1_NUM 1 4699aebddd1SJeff Kirsher 4709aebddd1SJeff Kirsher /* Pseudo amap definition in which each bit of the actual structure is defined 4719aebddd1SJeff Kirsher * as a byte: used to calculate offset/shift/mask of each field */ 4729aebddd1SJeff Kirsher struct amap_tx_context { 4739aebddd1SJeff Kirsher u8 if_id[16]; /* dword 0 */ 4749aebddd1SJeff Kirsher u8 tx_ring_size[4]; /* dword 0 */ 4759aebddd1SJeff Kirsher u8 rsvd1[26]; /* dword 0 */ 4769aebddd1SJeff Kirsher u8 pci_func_id[8]; /* dword 1 */ 4779aebddd1SJeff Kirsher u8 rsvd2[9]; /* dword 1 */ 4789aebddd1SJeff Kirsher u8 ctx_valid; /* dword 1 */ 4799aebddd1SJeff Kirsher u8 cq_id_send[16]; /* dword 2 */ 4809aebddd1SJeff Kirsher u8 rsvd3[16]; /* dword 2 */ 4819aebddd1SJeff Kirsher u8 rsvd4[32]; /* dword 3 */ 4829aebddd1SJeff Kirsher u8 rsvd5[32]; /* dword 4 */ 4839aebddd1SJeff Kirsher u8 rsvd6[32]; /* dword 5 */ 4849aebddd1SJeff Kirsher u8 rsvd7[32]; /* dword 6 */ 4859aebddd1SJeff Kirsher u8 rsvd8[32]; /* dword 7 */ 4869aebddd1SJeff Kirsher u8 rsvd9[32]; /* dword 8 */ 4879aebddd1SJeff Kirsher u8 rsvd10[32]; /* dword 9 */ 4889aebddd1SJeff Kirsher u8 rsvd11[32]; /* dword 10 */ 4899aebddd1SJeff Kirsher u8 rsvd12[32]; /* dword 11 */ 4909aebddd1SJeff Kirsher u8 rsvd13[32]; /* dword 12 */ 4919aebddd1SJeff Kirsher u8 rsvd14[32]; /* dword 13 */ 4929aebddd1SJeff Kirsher u8 rsvd15[32]; /* dword 14 */ 4939aebddd1SJeff Kirsher u8 rsvd16[32]; /* dword 15 */ 4949aebddd1SJeff Kirsher } __packed; 4959aebddd1SJeff Kirsher 4969aebddd1SJeff Kirsher struct be_cmd_req_eth_tx_create { 4979aebddd1SJeff Kirsher struct be_cmd_req_hdr hdr; 4989aebddd1SJeff Kirsher u8 num_pages; 4999aebddd1SJeff Kirsher u8 ulp_num; 5009aebddd1SJeff Kirsher u8 type; 5019aebddd1SJeff Kirsher u8 bound_port; 5029aebddd1SJeff Kirsher u8 context[sizeof(struct amap_tx_context) / 8]; 5039aebddd1SJeff Kirsher struct phys_addr pages[8]; 5049aebddd1SJeff Kirsher } __packed; 5059aebddd1SJeff Kirsher 5069aebddd1SJeff Kirsher struct be_cmd_resp_eth_tx_create { 5079aebddd1SJeff Kirsher struct be_cmd_resp_hdr hdr; 5089aebddd1SJeff Kirsher u16 cid; 5099aebddd1SJeff Kirsher u16 rsvd0; 5109aebddd1SJeff Kirsher } __packed; 5119aebddd1SJeff Kirsher 5129aebddd1SJeff Kirsher /******************** Create RxQ ***************************/ 5139aebddd1SJeff Kirsher struct be_cmd_req_eth_rx_create { 5149aebddd1SJeff Kirsher struct be_cmd_req_hdr hdr; 5159aebddd1SJeff Kirsher u16 cq_id; 5169aebddd1SJeff Kirsher u8 frag_size; 5179aebddd1SJeff Kirsher u8 num_pages; 5189aebddd1SJeff Kirsher struct phys_addr pages[2]; 5199aebddd1SJeff Kirsher u32 interface_id; 5209aebddd1SJeff Kirsher u16 max_frame_size; 5219aebddd1SJeff Kirsher u16 rsvd0; 5229aebddd1SJeff Kirsher u32 rss_queue; 5239aebddd1SJeff Kirsher } __packed; 5249aebddd1SJeff Kirsher 5259aebddd1SJeff Kirsher struct be_cmd_resp_eth_rx_create { 5269aebddd1SJeff Kirsher struct be_cmd_resp_hdr hdr; 5279aebddd1SJeff Kirsher u16 id; 5289aebddd1SJeff Kirsher u8 rss_id; 5299aebddd1SJeff Kirsher u8 rsvd0; 5309aebddd1SJeff Kirsher } __packed; 5319aebddd1SJeff Kirsher 5329aebddd1SJeff Kirsher /******************** Q Destroy ***************************/ 5339aebddd1SJeff Kirsher /* Type of Queue to be destroyed */ 5349aebddd1SJeff Kirsher enum { 5359aebddd1SJeff Kirsher QTYPE_EQ = 1, 5369aebddd1SJeff Kirsher QTYPE_CQ, 5379aebddd1SJeff Kirsher QTYPE_TXQ, 5389aebddd1SJeff Kirsher QTYPE_RXQ, 5399aebddd1SJeff Kirsher QTYPE_MCCQ 5409aebddd1SJeff Kirsher }; 5419aebddd1SJeff Kirsher 5429aebddd1SJeff Kirsher struct be_cmd_req_q_destroy { 5439aebddd1SJeff Kirsher struct be_cmd_req_hdr hdr; 5449aebddd1SJeff Kirsher u16 id; 5459aebddd1SJeff Kirsher u16 bypass_flush; /* valid only for rx q destroy */ 5469aebddd1SJeff Kirsher } __packed; 5479aebddd1SJeff Kirsher 5489aebddd1SJeff Kirsher /************ I/f Create (it's actually I/f Config Create)**********/ 5499aebddd1SJeff Kirsher 5509aebddd1SJeff Kirsher /* Capability flags for the i/f */ 5519aebddd1SJeff Kirsher enum be_if_flags { 5529aebddd1SJeff Kirsher BE_IF_FLAGS_RSS = 0x4, 5539aebddd1SJeff Kirsher BE_IF_FLAGS_PROMISCUOUS = 0x8, 5549aebddd1SJeff Kirsher BE_IF_FLAGS_BROADCAST = 0x10, 5559aebddd1SJeff Kirsher BE_IF_FLAGS_UNTAGGED = 0x20, 5569aebddd1SJeff Kirsher BE_IF_FLAGS_ULP = 0x40, 5579aebddd1SJeff Kirsher BE_IF_FLAGS_VLAN_PROMISCUOUS = 0x80, 5589aebddd1SJeff Kirsher BE_IF_FLAGS_VLAN = 0x100, 5599aebddd1SJeff Kirsher BE_IF_FLAGS_MCAST_PROMISCUOUS = 0x200, 5609aebddd1SJeff Kirsher BE_IF_FLAGS_PASS_L2_ERRORS = 0x400, 5619aebddd1SJeff Kirsher BE_IF_FLAGS_PASS_L3L4_ERRORS = 0x800, 5629aebddd1SJeff Kirsher BE_IF_FLAGS_MULTICAST = 0x1000 5639aebddd1SJeff Kirsher }; 5649aebddd1SJeff Kirsher 5659aebddd1SJeff Kirsher /* An RX interface is an object with one or more MAC addresses and 5669aebddd1SJeff Kirsher * filtering capabilities. */ 5679aebddd1SJeff Kirsher struct be_cmd_req_if_create { 5689aebddd1SJeff Kirsher struct be_cmd_req_hdr hdr; 5699aebddd1SJeff Kirsher u32 version; /* ignore currently */ 5709aebddd1SJeff Kirsher u32 capability_flags; 5719aebddd1SJeff Kirsher u32 enable_flags; 5729aebddd1SJeff Kirsher u8 mac_addr[ETH_ALEN]; 5739aebddd1SJeff Kirsher u8 rsvd0; 5749aebddd1SJeff Kirsher u8 pmac_invalid; /* if set, don't attach the mac addr to the i/f */ 5759aebddd1SJeff Kirsher u32 vlan_tag; /* not used currently */ 5769aebddd1SJeff Kirsher } __packed; 5779aebddd1SJeff Kirsher 5789aebddd1SJeff Kirsher struct be_cmd_resp_if_create { 5799aebddd1SJeff Kirsher struct be_cmd_resp_hdr hdr; 5809aebddd1SJeff Kirsher u32 interface_id; 5819aebddd1SJeff Kirsher u32 pmac_id; 5829aebddd1SJeff Kirsher }; 5839aebddd1SJeff Kirsher 5849aebddd1SJeff Kirsher /****** I/f Destroy(it's actually I/f Config Destroy )**********/ 5859aebddd1SJeff Kirsher struct be_cmd_req_if_destroy { 5869aebddd1SJeff Kirsher struct be_cmd_req_hdr hdr; 5879aebddd1SJeff Kirsher u32 interface_id; 5889aebddd1SJeff Kirsher }; 5899aebddd1SJeff Kirsher 5909aebddd1SJeff Kirsher /*************** HW Stats Get **********************************/ 5919aebddd1SJeff Kirsher struct be_port_rxf_stats_v0 { 5929aebddd1SJeff Kirsher u32 rx_bytes_lsd; /* dword 0*/ 5939aebddd1SJeff Kirsher u32 rx_bytes_msd; /* dword 1*/ 5949aebddd1SJeff Kirsher u32 rx_total_frames; /* dword 2*/ 5959aebddd1SJeff Kirsher u32 rx_unicast_frames; /* dword 3*/ 5969aebddd1SJeff Kirsher u32 rx_multicast_frames; /* dword 4*/ 5979aebddd1SJeff Kirsher u32 rx_broadcast_frames; /* dword 5*/ 5989aebddd1SJeff Kirsher u32 rx_crc_errors; /* dword 6*/ 5999aebddd1SJeff Kirsher u32 rx_alignment_symbol_errors; /* dword 7*/ 6009aebddd1SJeff Kirsher u32 rx_pause_frames; /* dword 8*/ 6019aebddd1SJeff Kirsher u32 rx_control_frames; /* dword 9*/ 6029aebddd1SJeff Kirsher u32 rx_in_range_errors; /* dword 10*/ 6039aebddd1SJeff Kirsher u32 rx_out_range_errors; /* dword 11*/ 6049aebddd1SJeff Kirsher u32 rx_frame_too_long; /* dword 12*/ 605d45b9d39SSathya Perla u32 rx_address_mismatch_drops; /* dword 13*/ 606d45b9d39SSathya Perla u32 rx_vlan_mismatch_drops; /* dword 14*/ 6079aebddd1SJeff Kirsher u32 rx_dropped_too_small; /* dword 15*/ 6089aebddd1SJeff Kirsher u32 rx_dropped_too_short; /* dword 16*/ 6099aebddd1SJeff Kirsher u32 rx_dropped_header_too_small; /* dword 17*/ 6109aebddd1SJeff Kirsher u32 rx_dropped_tcp_length; /* dword 18*/ 6119aebddd1SJeff Kirsher u32 rx_dropped_runt; /* dword 19*/ 6129aebddd1SJeff Kirsher u32 rx_64_byte_packets; /* dword 20*/ 6139aebddd1SJeff Kirsher u32 rx_65_127_byte_packets; /* dword 21*/ 6149aebddd1SJeff Kirsher u32 rx_128_256_byte_packets; /* dword 22*/ 6159aebddd1SJeff Kirsher u32 rx_256_511_byte_packets; /* dword 23*/ 6169aebddd1SJeff Kirsher u32 rx_512_1023_byte_packets; /* dword 24*/ 6179aebddd1SJeff Kirsher u32 rx_1024_1518_byte_packets; /* dword 25*/ 6189aebddd1SJeff Kirsher u32 rx_1519_2047_byte_packets; /* dword 26*/ 6199aebddd1SJeff Kirsher u32 rx_2048_4095_byte_packets; /* dword 27*/ 6209aebddd1SJeff Kirsher u32 rx_4096_8191_byte_packets; /* dword 28*/ 6219aebddd1SJeff Kirsher u32 rx_8192_9216_byte_packets; /* dword 29*/ 6229aebddd1SJeff Kirsher u32 rx_ip_checksum_errs; /* dword 30*/ 6239aebddd1SJeff Kirsher u32 rx_tcp_checksum_errs; /* dword 31*/ 6249aebddd1SJeff Kirsher u32 rx_udp_checksum_errs; /* dword 32*/ 6259aebddd1SJeff Kirsher u32 rx_non_rss_packets; /* dword 33*/ 6269aebddd1SJeff Kirsher u32 rx_ipv4_packets; /* dword 34*/ 6279aebddd1SJeff Kirsher u32 rx_ipv6_packets; /* dword 35*/ 6289aebddd1SJeff Kirsher u32 rx_ipv4_bytes_lsd; /* dword 36*/ 6299aebddd1SJeff Kirsher u32 rx_ipv4_bytes_msd; /* dword 37*/ 6309aebddd1SJeff Kirsher u32 rx_ipv6_bytes_lsd; /* dword 38*/ 6319aebddd1SJeff Kirsher u32 rx_ipv6_bytes_msd; /* dword 39*/ 6329aebddd1SJeff Kirsher u32 rx_chute1_packets; /* dword 40*/ 6339aebddd1SJeff Kirsher u32 rx_chute2_packets; /* dword 41*/ 6349aebddd1SJeff Kirsher u32 rx_chute3_packets; /* dword 42*/ 6359aebddd1SJeff Kirsher u32 rx_management_packets; /* dword 43*/ 6369aebddd1SJeff Kirsher u32 rx_switched_unicast_packets; /* dword 44*/ 6379aebddd1SJeff Kirsher u32 rx_switched_multicast_packets; /* dword 45*/ 6389aebddd1SJeff Kirsher u32 rx_switched_broadcast_packets; /* dword 46*/ 6399aebddd1SJeff Kirsher u32 tx_bytes_lsd; /* dword 47*/ 6409aebddd1SJeff Kirsher u32 tx_bytes_msd; /* dword 48*/ 6419aebddd1SJeff Kirsher u32 tx_unicastframes; /* dword 49*/ 6429aebddd1SJeff Kirsher u32 tx_multicastframes; /* dword 50*/ 6439aebddd1SJeff Kirsher u32 tx_broadcastframes; /* dword 51*/ 6449aebddd1SJeff Kirsher u32 tx_pauseframes; /* dword 52*/ 6459aebddd1SJeff Kirsher u32 tx_controlframes; /* dword 53*/ 6469aebddd1SJeff Kirsher u32 tx_64_byte_packets; /* dword 54*/ 6479aebddd1SJeff Kirsher u32 tx_65_127_byte_packets; /* dword 55*/ 6489aebddd1SJeff Kirsher u32 tx_128_256_byte_packets; /* dword 56*/ 6499aebddd1SJeff Kirsher u32 tx_256_511_byte_packets; /* dword 57*/ 6509aebddd1SJeff Kirsher u32 tx_512_1023_byte_packets; /* dword 58*/ 6519aebddd1SJeff Kirsher u32 tx_1024_1518_byte_packets; /* dword 59*/ 6529aebddd1SJeff Kirsher u32 tx_1519_2047_byte_packets; /* dword 60*/ 6539aebddd1SJeff Kirsher u32 tx_2048_4095_byte_packets; /* dword 61*/ 6549aebddd1SJeff Kirsher u32 tx_4096_8191_byte_packets; /* dword 62*/ 6559aebddd1SJeff Kirsher u32 tx_8192_9216_byte_packets; /* dword 63*/ 6569aebddd1SJeff Kirsher u32 rx_fifo_overflow; /* dword 64*/ 6579aebddd1SJeff Kirsher u32 rx_input_fifo_overflow; /* dword 65*/ 6589aebddd1SJeff Kirsher }; 6599aebddd1SJeff Kirsher 6609aebddd1SJeff Kirsher struct be_rxf_stats_v0 { 6619aebddd1SJeff Kirsher struct be_port_rxf_stats_v0 port[2]; 6629aebddd1SJeff Kirsher u32 rx_drops_no_pbuf; /* dword 132*/ 6639aebddd1SJeff Kirsher u32 rx_drops_no_txpb; /* dword 133*/ 6649aebddd1SJeff Kirsher u32 rx_drops_no_erx_descr; /* dword 134*/ 6659aebddd1SJeff Kirsher u32 rx_drops_no_tpre_descr; /* dword 135*/ 6669aebddd1SJeff Kirsher u32 management_rx_port_packets; /* dword 136*/ 6679aebddd1SJeff Kirsher u32 management_rx_port_bytes; /* dword 137*/ 6689aebddd1SJeff Kirsher u32 management_rx_port_pause_frames; /* dword 138*/ 6699aebddd1SJeff Kirsher u32 management_rx_port_errors; /* dword 139*/ 6709aebddd1SJeff Kirsher u32 management_tx_port_packets; /* dword 140*/ 6719aebddd1SJeff Kirsher u32 management_tx_port_bytes; /* dword 141*/ 6729aebddd1SJeff Kirsher u32 management_tx_port_pause; /* dword 142*/ 6739aebddd1SJeff Kirsher u32 management_rx_port_rxfifo_overflow; /* dword 143*/ 6749aebddd1SJeff Kirsher u32 rx_drops_too_many_frags; /* dword 144*/ 6759aebddd1SJeff Kirsher u32 rx_drops_invalid_ring; /* dword 145*/ 6769aebddd1SJeff Kirsher u32 forwarded_packets; /* dword 146*/ 6779aebddd1SJeff Kirsher u32 rx_drops_mtu; /* dword 147*/ 6789aebddd1SJeff Kirsher u32 rsvd0[7]; 6799aebddd1SJeff Kirsher u32 port0_jabber_events; 6809aebddd1SJeff Kirsher u32 port1_jabber_events; 6819aebddd1SJeff Kirsher u32 rsvd1[6]; 6829aebddd1SJeff Kirsher }; 6839aebddd1SJeff Kirsher 6849aebddd1SJeff Kirsher struct be_erx_stats_v0 { 6859aebddd1SJeff Kirsher u32 rx_drops_no_fragments[44]; /* dwordS 0 to 43*/ 6869aebddd1SJeff Kirsher u32 rsvd[4]; 6879aebddd1SJeff Kirsher }; 6889aebddd1SJeff Kirsher 6899aebddd1SJeff Kirsher struct be_pmem_stats { 6909aebddd1SJeff Kirsher u32 eth_red_drops; 6919aebddd1SJeff Kirsher u32 rsvd[5]; 6929aebddd1SJeff Kirsher }; 6939aebddd1SJeff Kirsher 6949aebddd1SJeff Kirsher struct be_hw_stats_v0 { 6959aebddd1SJeff Kirsher struct be_rxf_stats_v0 rxf; 6969aebddd1SJeff Kirsher u32 rsvd[48]; 6979aebddd1SJeff Kirsher struct be_erx_stats_v0 erx; 6989aebddd1SJeff Kirsher struct be_pmem_stats pmem; 6999aebddd1SJeff Kirsher }; 7009aebddd1SJeff Kirsher 7019aebddd1SJeff Kirsher struct be_cmd_req_get_stats_v0 { 7029aebddd1SJeff Kirsher struct be_cmd_req_hdr hdr; 7039aebddd1SJeff Kirsher u8 rsvd[sizeof(struct be_hw_stats_v0)]; 7049aebddd1SJeff Kirsher }; 7059aebddd1SJeff Kirsher 7069aebddd1SJeff Kirsher struct be_cmd_resp_get_stats_v0 { 7079aebddd1SJeff Kirsher struct be_cmd_resp_hdr hdr; 7089aebddd1SJeff Kirsher struct be_hw_stats_v0 hw_stats; 7099aebddd1SJeff Kirsher }; 7109aebddd1SJeff Kirsher 7119aebddd1SJeff Kirsher struct lancer_pport_stats { 7129aebddd1SJeff Kirsher u32 tx_packets_lo; 7139aebddd1SJeff Kirsher u32 tx_packets_hi; 7149aebddd1SJeff Kirsher u32 tx_unicast_packets_lo; 7159aebddd1SJeff Kirsher u32 tx_unicast_packets_hi; 7169aebddd1SJeff Kirsher u32 tx_multicast_packets_lo; 7179aebddd1SJeff Kirsher u32 tx_multicast_packets_hi; 7189aebddd1SJeff Kirsher u32 tx_broadcast_packets_lo; 7199aebddd1SJeff Kirsher u32 tx_broadcast_packets_hi; 7209aebddd1SJeff Kirsher u32 tx_bytes_lo; 7219aebddd1SJeff Kirsher u32 tx_bytes_hi; 7229aebddd1SJeff Kirsher u32 tx_unicast_bytes_lo; 7239aebddd1SJeff Kirsher u32 tx_unicast_bytes_hi; 7249aebddd1SJeff Kirsher u32 tx_multicast_bytes_lo; 7259aebddd1SJeff Kirsher u32 tx_multicast_bytes_hi; 7269aebddd1SJeff Kirsher u32 tx_broadcast_bytes_lo; 7279aebddd1SJeff Kirsher u32 tx_broadcast_bytes_hi; 7289aebddd1SJeff Kirsher u32 tx_discards_lo; 7299aebddd1SJeff Kirsher u32 tx_discards_hi; 7309aebddd1SJeff Kirsher u32 tx_errors_lo; 7319aebddd1SJeff Kirsher u32 tx_errors_hi; 7329aebddd1SJeff Kirsher u32 tx_pause_frames_lo; 7339aebddd1SJeff Kirsher u32 tx_pause_frames_hi; 7349aebddd1SJeff Kirsher u32 tx_pause_on_frames_lo; 7359aebddd1SJeff Kirsher u32 tx_pause_on_frames_hi; 7369aebddd1SJeff Kirsher u32 tx_pause_off_frames_lo; 7379aebddd1SJeff Kirsher u32 tx_pause_off_frames_hi; 7389aebddd1SJeff Kirsher u32 tx_internal_mac_errors_lo; 7399aebddd1SJeff Kirsher u32 tx_internal_mac_errors_hi; 7409aebddd1SJeff Kirsher u32 tx_control_frames_lo; 7419aebddd1SJeff Kirsher u32 tx_control_frames_hi; 7429aebddd1SJeff Kirsher u32 tx_packets_64_bytes_lo; 7439aebddd1SJeff Kirsher u32 tx_packets_64_bytes_hi; 7449aebddd1SJeff Kirsher u32 tx_packets_65_to_127_bytes_lo; 7459aebddd1SJeff Kirsher u32 tx_packets_65_to_127_bytes_hi; 7469aebddd1SJeff Kirsher u32 tx_packets_128_to_255_bytes_lo; 7479aebddd1SJeff Kirsher u32 tx_packets_128_to_255_bytes_hi; 7489aebddd1SJeff Kirsher u32 tx_packets_256_to_511_bytes_lo; 7499aebddd1SJeff Kirsher u32 tx_packets_256_to_511_bytes_hi; 7509aebddd1SJeff Kirsher u32 tx_packets_512_to_1023_bytes_lo; 7519aebddd1SJeff Kirsher u32 tx_packets_512_to_1023_bytes_hi; 7529aebddd1SJeff Kirsher u32 tx_packets_1024_to_1518_bytes_lo; 7539aebddd1SJeff Kirsher u32 tx_packets_1024_to_1518_bytes_hi; 7549aebddd1SJeff Kirsher u32 tx_packets_1519_to_2047_bytes_lo; 7559aebddd1SJeff Kirsher u32 tx_packets_1519_to_2047_bytes_hi; 7569aebddd1SJeff Kirsher u32 tx_packets_2048_to_4095_bytes_lo; 7579aebddd1SJeff Kirsher u32 tx_packets_2048_to_4095_bytes_hi; 7589aebddd1SJeff Kirsher u32 tx_packets_4096_to_8191_bytes_lo; 7599aebddd1SJeff Kirsher u32 tx_packets_4096_to_8191_bytes_hi; 7609aebddd1SJeff Kirsher u32 tx_packets_8192_to_9216_bytes_lo; 7619aebddd1SJeff Kirsher u32 tx_packets_8192_to_9216_bytes_hi; 7629aebddd1SJeff Kirsher u32 tx_lso_packets_lo; 7639aebddd1SJeff Kirsher u32 tx_lso_packets_hi; 7649aebddd1SJeff Kirsher u32 rx_packets_lo; 7659aebddd1SJeff Kirsher u32 rx_packets_hi; 7669aebddd1SJeff Kirsher u32 rx_unicast_packets_lo; 7679aebddd1SJeff Kirsher u32 rx_unicast_packets_hi; 7689aebddd1SJeff Kirsher u32 rx_multicast_packets_lo; 7699aebddd1SJeff Kirsher u32 rx_multicast_packets_hi; 7709aebddd1SJeff Kirsher u32 rx_broadcast_packets_lo; 7719aebddd1SJeff Kirsher u32 rx_broadcast_packets_hi; 7729aebddd1SJeff Kirsher u32 rx_bytes_lo; 7739aebddd1SJeff Kirsher u32 rx_bytes_hi; 7749aebddd1SJeff Kirsher u32 rx_unicast_bytes_lo; 7759aebddd1SJeff Kirsher u32 rx_unicast_bytes_hi; 7769aebddd1SJeff Kirsher u32 rx_multicast_bytes_lo; 7779aebddd1SJeff Kirsher u32 rx_multicast_bytes_hi; 7789aebddd1SJeff Kirsher u32 rx_broadcast_bytes_lo; 7799aebddd1SJeff Kirsher u32 rx_broadcast_bytes_hi; 7809aebddd1SJeff Kirsher u32 rx_unknown_protos; 7819aebddd1SJeff Kirsher u32 rsvd_69; /* Word 69 is reserved */ 7829aebddd1SJeff Kirsher u32 rx_discards_lo; 7839aebddd1SJeff Kirsher u32 rx_discards_hi; 7849aebddd1SJeff Kirsher u32 rx_errors_lo; 7859aebddd1SJeff Kirsher u32 rx_errors_hi; 7869aebddd1SJeff Kirsher u32 rx_crc_errors_lo; 7879aebddd1SJeff Kirsher u32 rx_crc_errors_hi; 7889aebddd1SJeff Kirsher u32 rx_alignment_errors_lo; 7899aebddd1SJeff Kirsher u32 rx_alignment_errors_hi; 7909aebddd1SJeff Kirsher u32 rx_symbol_errors_lo; 7919aebddd1SJeff Kirsher u32 rx_symbol_errors_hi; 7929aebddd1SJeff Kirsher u32 rx_pause_frames_lo; 7939aebddd1SJeff Kirsher u32 rx_pause_frames_hi; 7949aebddd1SJeff Kirsher u32 rx_pause_on_frames_lo; 7959aebddd1SJeff Kirsher u32 rx_pause_on_frames_hi; 7969aebddd1SJeff Kirsher u32 rx_pause_off_frames_lo; 7979aebddd1SJeff Kirsher u32 rx_pause_off_frames_hi; 7989aebddd1SJeff Kirsher u32 rx_frames_too_long_lo; 7999aebddd1SJeff Kirsher u32 rx_frames_too_long_hi; 8009aebddd1SJeff Kirsher u32 rx_internal_mac_errors_lo; 8019aebddd1SJeff Kirsher u32 rx_internal_mac_errors_hi; 8029aebddd1SJeff Kirsher u32 rx_undersize_packets; 8039aebddd1SJeff Kirsher u32 rx_oversize_packets; 8049aebddd1SJeff Kirsher u32 rx_fragment_packets; 8059aebddd1SJeff Kirsher u32 rx_jabbers; 8069aebddd1SJeff Kirsher u32 rx_control_frames_lo; 8079aebddd1SJeff Kirsher u32 rx_control_frames_hi; 8089aebddd1SJeff Kirsher u32 rx_control_frames_unknown_opcode_lo; 8099aebddd1SJeff Kirsher u32 rx_control_frames_unknown_opcode_hi; 8109aebddd1SJeff Kirsher u32 rx_in_range_errors; 8119aebddd1SJeff Kirsher u32 rx_out_of_range_errors; 812d45b9d39SSathya Perla u32 rx_address_mismatch_drops; 813d45b9d39SSathya Perla u32 rx_vlan_mismatch_drops; 8149aebddd1SJeff Kirsher u32 rx_dropped_too_small; 8159aebddd1SJeff Kirsher u32 rx_dropped_too_short; 8169aebddd1SJeff Kirsher u32 rx_dropped_header_too_small; 8179aebddd1SJeff Kirsher u32 rx_dropped_invalid_tcp_length; 8189aebddd1SJeff Kirsher u32 rx_dropped_runt; 8199aebddd1SJeff Kirsher u32 rx_ip_checksum_errors; 8209aebddd1SJeff Kirsher u32 rx_tcp_checksum_errors; 8219aebddd1SJeff Kirsher u32 rx_udp_checksum_errors; 8229aebddd1SJeff Kirsher u32 rx_non_rss_packets; 8239aebddd1SJeff Kirsher u32 rsvd_111; 8249aebddd1SJeff Kirsher u32 rx_ipv4_packets_lo; 8259aebddd1SJeff Kirsher u32 rx_ipv4_packets_hi; 8269aebddd1SJeff Kirsher u32 rx_ipv6_packets_lo; 8279aebddd1SJeff Kirsher u32 rx_ipv6_packets_hi; 8289aebddd1SJeff Kirsher u32 rx_ipv4_bytes_lo; 8299aebddd1SJeff Kirsher u32 rx_ipv4_bytes_hi; 8309aebddd1SJeff Kirsher u32 rx_ipv6_bytes_lo; 8319aebddd1SJeff Kirsher u32 rx_ipv6_bytes_hi; 8329aebddd1SJeff Kirsher u32 rx_nic_packets_lo; 8339aebddd1SJeff Kirsher u32 rx_nic_packets_hi; 8349aebddd1SJeff Kirsher u32 rx_tcp_packets_lo; 8359aebddd1SJeff Kirsher u32 rx_tcp_packets_hi; 8369aebddd1SJeff Kirsher u32 rx_iscsi_packets_lo; 8379aebddd1SJeff Kirsher u32 rx_iscsi_packets_hi; 8389aebddd1SJeff Kirsher u32 rx_management_packets_lo; 8399aebddd1SJeff Kirsher u32 rx_management_packets_hi; 8409aebddd1SJeff Kirsher u32 rx_switched_unicast_packets_lo; 8419aebddd1SJeff Kirsher u32 rx_switched_unicast_packets_hi; 8429aebddd1SJeff Kirsher u32 rx_switched_multicast_packets_lo; 8439aebddd1SJeff Kirsher u32 rx_switched_multicast_packets_hi; 8449aebddd1SJeff Kirsher u32 rx_switched_broadcast_packets_lo; 8459aebddd1SJeff Kirsher u32 rx_switched_broadcast_packets_hi; 8469aebddd1SJeff Kirsher u32 num_forwards_lo; 8479aebddd1SJeff Kirsher u32 num_forwards_hi; 8489aebddd1SJeff Kirsher u32 rx_fifo_overflow; 8499aebddd1SJeff Kirsher u32 rx_input_fifo_overflow; 8509aebddd1SJeff Kirsher u32 rx_drops_too_many_frags_lo; 8519aebddd1SJeff Kirsher u32 rx_drops_too_many_frags_hi; 8529aebddd1SJeff Kirsher u32 rx_drops_invalid_queue; 8539aebddd1SJeff Kirsher u32 rsvd_141; 8549aebddd1SJeff Kirsher u32 rx_drops_mtu_lo; 8559aebddd1SJeff Kirsher u32 rx_drops_mtu_hi; 8569aebddd1SJeff Kirsher u32 rx_packets_64_bytes_lo; 8579aebddd1SJeff Kirsher u32 rx_packets_64_bytes_hi; 8589aebddd1SJeff Kirsher u32 rx_packets_65_to_127_bytes_lo; 8599aebddd1SJeff Kirsher u32 rx_packets_65_to_127_bytes_hi; 8609aebddd1SJeff Kirsher u32 rx_packets_128_to_255_bytes_lo; 8619aebddd1SJeff Kirsher u32 rx_packets_128_to_255_bytes_hi; 8629aebddd1SJeff Kirsher u32 rx_packets_256_to_511_bytes_lo; 8639aebddd1SJeff Kirsher u32 rx_packets_256_to_511_bytes_hi; 8649aebddd1SJeff Kirsher u32 rx_packets_512_to_1023_bytes_lo; 8659aebddd1SJeff Kirsher u32 rx_packets_512_to_1023_bytes_hi; 8669aebddd1SJeff Kirsher u32 rx_packets_1024_to_1518_bytes_lo; 8679aebddd1SJeff Kirsher u32 rx_packets_1024_to_1518_bytes_hi; 8689aebddd1SJeff Kirsher u32 rx_packets_1519_to_2047_bytes_lo; 8699aebddd1SJeff Kirsher u32 rx_packets_1519_to_2047_bytes_hi; 8709aebddd1SJeff Kirsher u32 rx_packets_2048_to_4095_bytes_lo; 8719aebddd1SJeff Kirsher u32 rx_packets_2048_to_4095_bytes_hi; 8729aebddd1SJeff Kirsher u32 rx_packets_4096_to_8191_bytes_lo; 8739aebddd1SJeff Kirsher u32 rx_packets_4096_to_8191_bytes_hi; 8749aebddd1SJeff Kirsher u32 rx_packets_8192_to_9216_bytes_lo; 8759aebddd1SJeff Kirsher u32 rx_packets_8192_to_9216_bytes_hi; 8769aebddd1SJeff Kirsher }; 8779aebddd1SJeff Kirsher 8789aebddd1SJeff Kirsher struct pport_stats_params { 8799aebddd1SJeff Kirsher u16 pport_num; 8809aebddd1SJeff Kirsher u8 rsvd; 8819aebddd1SJeff Kirsher u8 reset_stats; 8829aebddd1SJeff Kirsher }; 8839aebddd1SJeff Kirsher 8849aebddd1SJeff Kirsher struct lancer_cmd_req_pport_stats { 8859aebddd1SJeff Kirsher struct be_cmd_req_hdr hdr; 8869aebddd1SJeff Kirsher union { 8879aebddd1SJeff Kirsher struct pport_stats_params params; 8889aebddd1SJeff Kirsher u8 rsvd[sizeof(struct lancer_pport_stats)]; 8899aebddd1SJeff Kirsher } cmd_params; 8909aebddd1SJeff Kirsher }; 8919aebddd1SJeff Kirsher 8929aebddd1SJeff Kirsher struct lancer_cmd_resp_pport_stats { 8939aebddd1SJeff Kirsher struct be_cmd_resp_hdr hdr; 8949aebddd1SJeff Kirsher struct lancer_pport_stats pport_stats; 8959aebddd1SJeff Kirsher }; 8969aebddd1SJeff Kirsher 8979aebddd1SJeff Kirsher static inline struct lancer_pport_stats* 8989aebddd1SJeff Kirsher pport_stats_from_cmd(struct be_adapter *adapter) 8999aebddd1SJeff Kirsher { 9009aebddd1SJeff Kirsher struct lancer_cmd_resp_pport_stats *cmd = adapter->stats_cmd.va; 9019aebddd1SJeff Kirsher return &cmd->pport_stats; 9029aebddd1SJeff Kirsher } 9039aebddd1SJeff Kirsher 9049aebddd1SJeff Kirsher struct be_cmd_req_get_cntl_addnl_attribs { 9059aebddd1SJeff Kirsher struct be_cmd_req_hdr hdr; 9069aebddd1SJeff Kirsher u8 rsvd[8]; 9079aebddd1SJeff Kirsher }; 9089aebddd1SJeff Kirsher 9099aebddd1SJeff Kirsher struct be_cmd_resp_get_cntl_addnl_attribs { 9109aebddd1SJeff Kirsher struct be_cmd_resp_hdr hdr; 9119aebddd1SJeff Kirsher u16 ipl_file_number; 9129aebddd1SJeff Kirsher u8 ipl_file_version; 9139aebddd1SJeff Kirsher u8 rsvd0; 9149aebddd1SJeff Kirsher u8 on_die_temperature; /* in degrees centigrade*/ 9159aebddd1SJeff Kirsher u8 rsvd1[3]; 9169aebddd1SJeff Kirsher }; 9179aebddd1SJeff Kirsher 9189aebddd1SJeff Kirsher struct be_cmd_req_vlan_config { 9199aebddd1SJeff Kirsher struct be_cmd_req_hdr hdr; 9209aebddd1SJeff Kirsher u8 interface_id; 9219aebddd1SJeff Kirsher u8 promiscuous; 9229aebddd1SJeff Kirsher u8 untagged; 9239aebddd1SJeff Kirsher u8 num_vlan; 9249aebddd1SJeff Kirsher u16 normal_vlan[64]; 9259aebddd1SJeff Kirsher } __packed; 9269aebddd1SJeff Kirsher 9279aebddd1SJeff Kirsher /******************* RX FILTER ******************************/ 9289aebddd1SJeff Kirsher #define BE_MAX_MC 64 /* set mcast promisc if > 64 */ 9299aebddd1SJeff Kirsher struct macaddr { 9309aebddd1SJeff Kirsher u8 byte[ETH_ALEN]; 9319aebddd1SJeff Kirsher }; 9329aebddd1SJeff Kirsher 9339aebddd1SJeff Kirsher struct be_cmd_req_rx_filter { 9349aebddd1SJeff Kirsher struct be_cmd_req_hdr hdr; 9359aebddd1SJeff Kirsher u32 global_flags_mask; 9369aebddd1SJeff Kirsher u32 global_flags; 9379aebddd1SJeff Kirsher u32 if_flags_mask; 9389aebddd1SJeff Kirsher u32 if_flags; 9399aebddd1SJeff Kirsher u32 if_id; 9409aebddd1SJeff Kirsher u32 mcast_num; 9419aebddd1SJeff Kirsher struct macaddr mcast_mac[BE_MAX_MC]; 9429aebddd1SJeff Kirsher }; 9439aebddd1SJeff Kirsher 9449aebddd1SJeff Kirsher /******************** Link Status Query *******************/ 9459aebddd1SJeff Kirsher struct be_cmd_req_link_status { 9469aebddd1SJeff Kirsher struct be_cmd_req_hdr hdr; 9479aebddd1SJeff Kirsher u32 rsvd; 9489aebddd1SJeff Kirsher }; 9499aebddd1SJeff Kirsher 9509aebddd1SJeff Kirsher enum { 9519aebddd1SJeff Kirsher PHY_LINK_DUPLEX_NONE = 0x0, 9529aebddd1SJeff Kirsher PHY_LINK_DUPLEX_HALF = 0x1, 9539aebddd1SJeff Kirsher PHY_LINK_DUPLEX_FULL = 0x2 9549aebddd1SJeff Kirsher }; 9559aebddd1SJeff Kirsher 9569aebddd1SJeff Kirsher enum { 9579aebddd1SJeff Kirsher PHY_LINK_SPEED_ZERO = 0x0, /* => No link */ 9589aebddd1SJeff Kirsher PHY_LINK_SPEED_10MBPS = 0x1, 9599aebddd1SJeff Kirsher PHY_LINK_SPEED_100MBPS = 0x2, 9609aebddd1SJeff Kirsher PHY_LINK_SPEED_1GBPS = 0x3, 9619aebddd1SJeff Kirsher PHY_LINK_SPEED_10GBPS = 0x4 9629aebddd1SJeff Kirsher }; 9639aebddd1SJeff Kirsher 9649aebddd1SJeff Kirsher struct be_cmd_resp_link_status { 9659aebddd1SJeff Kirsher struct be_cmd_resp_hdr hdr; 9669aebddd1SJeff Kirsher u8 physical_port; 9679aebddd1SJeff Kirsher u8 mac_duplex; 9689aebddd1SJeff Kirsher u8 mac_speed; 9699aebddd1SJeff Kirsher u8 mac_fault; 9709aebddd1SJeff Kirsher u8 mgmt_mac_duplex; 9719aebddd1SJeff Kirsher u8 mgmt_mac_speed; 9729aebddd1SJeff Kirsher u16 link_speed; 973b236916aSAjit Khaparde u8 logical_link_status; 974b236916aSAjit Khaparde u8 rsvd1[3]; 9759aebddd1SJeff Kirsher } __packed; 9769aebddd1SJeff Kirsher 9779aebddd1SJeff Kirsher /******************** Port Identification ***************************/ 9789aebddd1SJeff Kirsher /* Identifies the type of port attached to NIC */ 9799aebddd1SJeff Kirsher struct be_cmd_req_port_type { 9809aebddd1SJeff Kirsher struct be_cmd_req_hdr hdr; 9819aebddd1SJeff Kirsher u32 page_num; 9829aebddd1SJeff Kirsher u32 port; 9839aebddd1SJeff Kirsher }; 9849aebddd1SJeff Kirsher 9859aebddd1SJeff Kirsher enum { 9869aebddd1SJeff Kirsher TR_PAGE_A0 = 0xa0, 9879aebddd1SJeff Kirsher TR_PAGE_A2 = 0xa2 9889aebddd1SJeff Kirsher }; 9899aebddd1SJeff Kirsher 9909aebddd1SJeff Kirsher struct be_cmd_resp_port_type { 9919aebddd1SJeff Kirsher struct be_cmd_resp_hdr hdr; 9929aebddd1SJeff Kirsher u32 page_num; 9939aebddd1SJeff Kirsher u32 port; 9949aebddd1SJeff Kirsher struct data { 9959aebddd1SJeff Kirsher u8 identifier; 9969aebddd1SJeff Kirsher u8 identifier_ext; 9979aebddd1SJeff Kirsher u8 connector; 9989aebddd1SJeff Kirsher u8 transceiver[8]; 9999aebddd1SJeff Kirsher u8 rsvd0[3]; 10009aebddd1SJeff Kirsher u8 length_km; 10019aebddd1SJeff Kirsher u8 length_hm; 10029aebddd1SJeff Kirsher u8 length_om1; 10039aebddd1SJeff Kirsher u8 length_om2; 10049aebddd1SJeff Kirsher u8 length_cu; 10059aebddd1SJeff Kirsher u8 length_cu_m; 10069aebddd1SJeff Kirsher u8 vendor_name[16]; 10079aebddd1SJeff Kirsher u8 rsvd; 10089aebddd1SJeff Kirsher u8 vendor_oui[3]; 10099aebddd1SJeff Kirsher u8 vendor_pn[16]; 10109aebddd1SJeff Kirsher u8 vendor_rev[4]; 10119aebddd1SJeff Kirsher } data; 10129aebddd1SJeff Kirsher }; 10139aebddd1SJeff Kirsher 10149aebddd1SJeff Kirsher /******************** Get FW Version *******************/ 10159aebddd1SJeff Kirsher struct be_cmd_req_get_fw_version { 10169aebddd1SJeff Kirsher struct be_cmd_req_hdr hdr; 10179aebddd1SJeff Kirsher u8 rsvd0[FW_VER_LEN]; 10189aebddd1SJeff Kirsher u8 rsvd1[FW_VER_LEN]; 10199aebddd1SJeff Kirsher } __packed; 10209aebddd1SJeff Kirsher 10219aebddd1SJeff Kirsher struct be_cmd_resp_get_fw_version { 10229aebddd1SJeff Kirsher struct be_cmd_resp_hdr hdr; 10239aebddd1SJeff Kirsher u8 firmware_version_string[FW_VER_LEN]; 10249aebddd1SJeff Kirsher u8 fw_on_flash_version_string[FW_VER_LEN]; 10259aebddd1SJeff Kirsher } __packed; 10269aebddd1SJeff Kirsher 10279aebddd1SJeff Kirsher /******************** Set Flow Contrl *******************/ 10289aebddd1SJeff Kirsher struct be_cmd_req_set_flow_control { 10299aebddd1SJeff Kirsher struct be_cmd_req_hdr hdr; 10309aebddd1SJeff Kirsher u16 tx_flow_control; 10319aebddd1SJeff Kirsher u16 rx_flow_control; 10329aebddd1SJeff Kirsher } __packed; 10339aebddd1SJeff Kirsher 10349aebddd1SJeff Kirsher /******************** Get Flow Contrl *******************/ 10359aebddd1SJeff Kirsher struct be_cmd_req_get_flow_control { 10369aebddd1SJeff Kirsher struct be_cmd_req_hdr hdr; 10379aebddd1SJeff Kirsher u32 rsvd; 10389aebddd1SJeff Kirsher }; 10399aebddd1SJeff Kirsher 10409aebddd1SJeff Kirsher struct be_cmd_resp_get_flow_control { 10419aebddd1SJeff Kirsher struct be_cmd_resp_hdr hdr; 10429aebddd1SJeff Kirsher u16 tx_flow_control; 10439aebddd1SJeff Kirsher u16 rx_flow_control; 10449aebddd1SJeff Kirsher } __packed; 10459aebddd1SJeff Kirsher 10469aebddd1SJeff Kirsher /******************** Modify EQ Delay *******************/ 10479aebddd1SJeff Kirsher struct be_cmd_req_modify_eq_delay { 10489aebddd1SJeff Kirsher struct be_cmd_req_hdr hdr; 10499aebddd1SJeff Kirsher u32 num_eq; 10509aebddd1SJeff Kirsher struct { 10519aebddd1SJeff Kirsher u32 eq_id; 10529aebddd1SJeff Kirsher u32 phase; 10539aebddd1SJeff Kirsher u32 delay_multiplier; 10549aebddd1SJeff Kirsher } delay[8]; 10559aebddd1SJeff Kirsher } __packed; 10569aebddd1SJeff Kirsher 10579aebddd1SJeff Kirsher struct be_cmd_resp_modify_eq_delay { 10589aebddd1SJeff Kirsher struct be_cmd_resp_hdr hdr; 10599aebddd1SJeff Kirsher u32 rsvd0; 10609aebddd1SJeff Kirsher } __packed; 10619aebddd1SJeff Kirsher 10629aebddd1SJeff Kirsher /******************** Get FW Config *******************/ 10639aebddd1SJeff Kirsher #define BE_FUNCTION_CAPS_RSS 0x2 1064752961a1SSathya Perla /* The HW can come up in either of the following multi-channel modes 1065752961a1SSathya Perla * based on the skew/IPL. 1066752961a1SSathya Perla */ 1067045508a8SParav Pandit #define RDMA_ENABLED 0x4 1068752961a1SSathya Perla #define FLEX10_MODE 0x400 1069752961a1SSathya Perla #define VNIC_MODE 0x20000 1070752961a1SSathya Perla #define UMC_ENABLED 0x1000000 10719aebddd1SJeff Kirsher struct be_cmd_req_query_fw_cfg { 10729aebddd1SJeff Kirsher struct be_cmd_req_hdr hdr; 10739aebddd1SJeff Kirsher u32 rsvd[31]; 10749aebddd1SJeff Kirsher }; 10759aebddd1SJeff Kirsher 10769aebddd1SJeff Kirsher struct be_cmd_resp_query_fw_cfg { 10779aebddd1SJeff Kirsher struct be_cmd_resp_hdr hdr; 10789aebddd1SJeff Kirsher u32 be_config_number; 10799aebddd1SJeff Kirsher u32 asic_revision; 10809aebddd1SJeff Kirsher u32 phys_port; 10819aebddd1SJeff Kirsher u32 function_mode; 10829aebddd1SJeff Kirsher u32 rsvd[26]; 10839aebddd1SJeff Kirsher u32 function_caps; 10849aebddd1SJeff Kirsher }; 10859aebddd1SJeff Kirsher 108673dea398SPadmanabh Ratnakar /******************** RSS Config ****************************************/ 108773dea398SPadmanabh Ratnakar /* RSS type Input parameters used to compute RX hash 108873dea398SPadmanabh Ratnakar * RSS_ENABLE_IPV4 SRC IPv4, DST IPv4 108973dea398SPadmanabh Ratnakar * RSS_ENABLE_TCP_IPV4 SRC IPv4, DST IPv4, TCP SRC PORT, TCP DST PORT 109073dea398SPadmanabh Ratnakar * RSS_ENABLE_IPV6 SRC IPv6, DST IPv6 109173dea398SPadmanabh Ratnakar * RSS_ENABLE_TCP_IPV6 SRC IPv6, DST IPv6, TCP SRC PORT, TCP DST PORT 109273dea398SPadmanabh Ratnakar * RSS_ENABLE_UDP_IPV4 SRC IPv4, DST IPv4, UDP SRC PORT, UDP DST PORT 109373dea398SPadmanabh Ratnakar * RSS_ENABLE_UDP_IPV6 SRC IPv6, DST IPv6, UDP SRC PORT, UDP DST PORT 109473dea398SPadmanabh Ratnakar * 109573dea398SPadmanabh Ratnakar * When multiple RSS types are enabled, HW picks the best hash policy 109673dea398SPadmanabh Ratnakar * based on the type of the received packet. 109773dea398SPadmanabh Ratnakar */ 10989aebddd1SJeff Kirsher #define RSS_ENABLE_NONE 0x0 10999aebddd1SJeff Kirsher #define RSS_ENABLE_IPV4 0x1 11009aebddd1SJeff Kirsher #define RSS_ENABLE_TCP_IPV4 0x2 11019aebddd1SJeff Kirsher #define RSS_ENABLE_IPV6 0x4 11029aebddd1SJeff Kirsher #define RSS_ENABLE_TCP_IPV6 0x8 1103d3bd3a5eSPadmanabh Ratnakar #define RSS_ENABLE_UDP_IPV4 0x10 1104d3bd3a5eSPadmanabh Ratnakar #define RSS_ENABLE_UDP_IPV6 0x20 11059aebddd1SJeff Kirsher 11069aebddd1SJeff Kirsher struct be_cmd_req_rss_config { 11079aebddd1SJeff Kirsher struct be_cmd_req_hdr hdr; 11089aebddd1SJeff Kirsher u32 if_id; 11099aebddd1SJeff Kirsher u16 enable_rss; 11109aebddd1SJeff Kirsher u16 cpu_table_size_log2; 11119aebddd1SJeff Kirsher u32 hash[10]; 11129aebddd1SJeff Kirsher u8 cpu_table[128]; 11139aebddd1SJeff Kirsher u8 flush; 11149aebddd1SJeff Kirsher u8 rsvd0[3]; 11159aebddd1SJeff Kirsher }; 11169aebddd1SJeff Kirsher 11179aebddd1SJeff Kirsher /******************** Port Beacon ***************************/ 11189aebddd1SJeff Kirsher 11199aebddd1SJeff Kirsher #define BEACON_STATE_ENABLED 0x1 11209aebddd1SJeff Kirsher #define BEACON_STATE_DISABLED 0x0 11219aebddd1SJeff Kirsher 11229aebddd1SJeff Kirsher struct be_cmd_req_enable_disable_beacon { 11239aebddd1SJeff Kirsher struct be_cmd_req_hdr hdr; 11249aebddd1SJeff Kirsher u8 port_num; 11259aebddd1SJeff Kirsher u8 beacon_state; 11269aebddd1SJeff Kirsher u8 beacon_duration; 11279aebddd1SJeff Kirsher u8 status_duration; 11289aebddd1SJeff Kirsher } __packed; 11299aebddd1SJeff Kirsher 11309aebddd1SJeff Kirsher struct be_cmd_resp_enable_disable_beacon { 11319aebddd1SJeff Kirsher struct be_cmd_resp_hdr resp_hdr; 11329aebddd1SJeff Kirsher u32 rsvd0; 11339aebddd1SJeff Kirsher } __packed; 11349aebddd1SJeff Kirsher 11359aebddd1SJeff Kirsher struct be_cmd_req_get_beacon_state { 11369aebddd1SJeff Kirsher struct be_cmd_req_hdr hdr; 11379aebddd1SJeff Kirsher u8 port_num; 11389aebddd1SJeff Kirsher u8 rsvd0; 11399aebddd1SJeff Kirsher u16 rsvd1; 11409aebddd1SJeff Kirsher } __packed; 11419aebddd1SJeff Kirsher 11429aebddd1SJeff Kirsher struct be_cmd_resp_get_beacon_state { 11439aebddd1SJeff Kirsher struct be_cmd_resp_hdr resp_hdr; 11449aebddd1SJeff Kirsher u8 beacon_state; 11459aebddd1SJeff Kirsher u8 rsvd0[3]; 11469aebddd1SJeff Kirsher } __packed; 11479aebddd1SJeff Kirsher 11489aebddd1SJeff Kirsher /****************** Firmware Flash ******************/ 11499aebddd1SJeff Kirsher struct flashrom_params { 11509aebddd1SJeff Kirsher u32 op_code; 11519aebddd1SJeff Kirsher u32 op_type; 11529aebddd1SJeff Kirsher u32 data_buf_size; 11539aebddd1SJeff Kirsher u32 offset; 11549aebddd1SJeff Kirsher u8 data_buf[4]; 11559aebddd1SJeff Kirsher }; 11569aebddd1SJeff Kirsher 11579aebddd1SJeff Kirsher struct be_cmd_write_flashrom { 11589aebddd1SJeff Kirsher struct be_cmd_req_hdr hdr; 11599aebddd1SJeff Kirsher struct flashrom_params params; 11609aebddd1SJeff Kirsher }; 11619aebddd1SJeff Kirsher 11629aebddd1SJeff Kirsher /**************** Lancer Firmware Flash ************/ 11639aebddd1SJeff Kirsher struct amap_lancer_write_obj_context { 11649aebddd1SJeff Kirsher u8 write_length[24]; 11659aebddd1SJeff Kirsher u8 reserved1[7]; 11669aebddd1SJeff Kirsher u8 eof; 11679aebddd1SJeff Kirsher } __packed; 11689aebddd1SJeff Kirsher 11699aebddd1SJeff Kirsher struct lancer_cmd_req_write_object { 11709aebddd1SJeff Kirsher struct be_cmd_req_hdr hdr; 11719aebddd1SJeff Kirsher u8 context[sizeof(struct amap_lancer_write_obj_context) / 8]; 11729aebddd1SJeff Kirsher u32 write_offset; 11739aebddd1SJeff Kirsher u8 object_name[104]; 11749aebddd1SJeff Kirsher u32 descriptor_count; 11759aebddd1SJeff Kirsher u32 buf_len; 11769aebddd1SJeff Kirsher u32 addr_low; 11779aebddd1SJeff Kirsher u32 addr_high; 11789aebddd1SJeff Kirsher }; 11799aebddd1SJeff Kirsher 1180f67ef7baSPadmanabh Ratnakar #define LANCER_NO_RESET_NEEDED 0x00 1181f67ef7baSPadmanabh Ratnakar #define LANCER_FW_RESET_NEEDED 0x02 11829aebddd1SJeff Kirsher struct lancer_cmd_resp_write_object { 11839aebddd1SJeff Kirsher u8 opcode; 11849aebddd1SJeff Kirsher u8 subsystem; 11859aebddd1SJeff Kirsher u8 rsvd1[2]; 11869aebddd1SJeff Kirsher u8 status; 11879aebddd1SJeff Kirsher u8 additional_status; 11889aebddd1SJeff Kirsher u8 rsvd2[2]; 11899aebddd1SJeff Kirsher u32 resp_len; 11909aebddd1SJeff Kirsher u32 actual_resp_len; 11919aebddd1SJeff Kirsher u32 actual_write_len; 1192f67ef7baSPadmanabh Ratnakar u8 change_status; 1193f67ef7baSPadmanabh Ratnakar u8 rsvd3[3]; 11949aebddd1SJeff Kirsher }; 11959aebddd1SJeff Kirsher 1196de49bd5aSPadmanabh Ratnakar /************************ Lancer Read FW info **************/ 1197de49bd5aSPadmanabh Ratnakar #define LANCER_READ_FILE_CHUNK (32*1024) 1198de49bd5aSPadmanabh Ratnakar #define LANCER_READ_FILE_EOF_MASK 0x80000000 1199de49bd5aSPadmanabh Ratnakar 1200de49bd5aSPadmanabh Ratnakar #define LANCER_FW_DUMP_FILE "/dbg/dump.bin" 1201af5875bdSPadmanabh Ratnakar #define LANCER_VPD_PF_FILE "/vpd/ntr_pf.vpd" 1202af5875bdSPadmanabh Ratnakar #define LANCER_VPD_VF_FILE "/vpd/ntr_vf.vpd" 1203de49bd5aSPadmanabh Ratnakar 1204de49bd5aSPadmanabh Ratnakar struct lancer_cmd_req_read_object { 1205de49bd5aSPadmanabh Ratnakar struct be_cmd_req_hdr hdr; 1206de49bd5aSPadmanabh Ratnakar u32 desired_read_len; 1207de49bd5aSPadmanabh Ratnakar u32 read_offset; 1208de49bd5aSPadmanabh Ratnakar u8 object_name[104]; 1209de49bd5aSPadmanabh Ratnakar u32 descriptor_count; 1210de49bd5aSPadmanabh Ratnakar u32 buf_len; 1211de49bd5aSPadmanabh Ratnakar u32 addr_low; 1212de49bd5aSPadmanabh Ratnakar u32 addr_high; 1213de49bd5aSPadmanabh Ratnakar }; 1214de49bd5aSPadmanabh Ratnakar 1215de49bd5aSPadmanabh Ratnakar struct lancer_cmd_resp_read_object { 1216de49bd5aSPadmanabh Ratnakar u8 opcode; 1217de49bd5aSPadmanabh Ratnakar u8 subsystem; 1218de49bd5aSPadmanabh Ratnakar u8 rsvd1[2]; 1219de49bd5aSPadmanabh Ratnakar u8 status; 1220de49bd5aSPadmanabh Ratnakar u8 additional_status; 1221de49bd5aSPadmanabh Ratnakar u8 rsvd2[2]; 1222de49bd5aSPadmanabh Ratnakar u32 resp_len; 1223de49bd5aSPadmanabh Ratnakar u32 actual_resp_len; 1224de49bd5aSPadmanabh Ratnakar u32 actual_read_len; 1225de49bd5aSPadmanabh Ratnakar u32 eof; 1226de49bd5aSPadmanabh Ratnakar }; 1227de49bd5aSPadmanabh Ratnakar 12289aebddd1SJeff Kirsher /************************ WOL *******************************/ 12299aebddd1SJeff Kirsher struct be_cmd_req_acpi_wol_magic_config{ 12309aebddd1SJeff Kirsher struct be_cmd_req_hdr hdr; 12319aebddd1SJeff Kirsher u32 rsvd0[145]; 12329aebddd1SJeff Kirsher u8 magic_mac[6]; 12339aebddd1SJeff Kirsher u8 rsvd2[2]; 12349aebddd1SJeff Kirsher } __packed; 12359aebddd1SJeff Kirsher 12364762f6ceSAjit Khaparde struct be_cmd_req_acpi_wol_magic_config_v1 { 12374762f6ceSAjit Khaparde struct be_cmd_req_hdr hdr; 12384762f6ceSAjit Khaparde u8 rsvd0[2]; 12394762f6ceSAjit Khaparde u8 query_options; 12404762f6ceSAjit Khaparde u8 rsvd1[5]; 12414762f6ceSAjit Khaparde u32 rsvd2[288]; 12424762f6ceSAjit Khaparde u8 magic_mac[6]; 12434762f6ceSAjit Khaparde u8 rsvd3[22]; 12444762f6ceSAjit Khaparde } __packed; 12454762f6ceSAjit Khaparde 12464762f6ceSAjit Khaparde struct be_cmd_resp_acpi_wol_magic_config_v1 { 12474762f6ceSAjit Khaparde struct be_cmd_resp_hdr hdr; 12484762f6ceSAjit Khaparde u8 rsvd0[2]; 12494762f6ceSAjit Khaparde u8 wol_settings; 12504762f6ceSAjit Khaparde u8 rsvd1[5]; 12514762f6ceSAjit Khaparde u32 rsvd2[295]; 12524762f6ceSAjit Khaparde } __packed; 12534762f6ceSAjit Khaparde 12544762f6ceSAjit Khaparde #define BE_GET_WOL_CAP 2 12554762f6ceSAjit Khaparde 12564762f6ceSAjit Khaparde #define BE_WOL_CAP 0x1 12574762f6ceSAjit Khaparde #define BE_PME_D0_CAP 0x8 12584762f6ceSAjit Khaparde #define BE_PME_D1_CAP 0x10 12594762f6ceSAjit Khaparde #define BE_PME_D2_CAP 0x20 12604762f6ceSAjit Khaparde #define BE_PME_D3HOT_CAP 0x40 12614762f6ceSAjit Khaparde #define BE_PME_D3COLD_CAP 0x80 12624762f6ceSAjit Khaparde 12639aebddd1SJeff Kirsher /********************** LoopBack test *********************/ 12649aebddd1SJeff Kirsher struct be_cmd_req_loopback_test { 12659aebddd1SJeff Kirsher struct be_cmd_req_hdr hdr; 12669aebddd1SJeff Kirsher u32 loopback_type; 12679aebddd1SJeff Kirsher u32 num_pkts; 12689aebddd1SJeff Kirsher u64 pattern; 12699aebddd1SJeff Kirsher u32 src_port; 12709aebddd1SJeff Kirsher u32 dest_port; 12719aebddd1SJeff Kirsher u32 pkt_size; 12729aebddd1SJeff Kirsher }; 12739aebddd1SJeff Kirsher 12749aebddd1SJeff Kirsher struct be_cmd_resp_loopback_test { 12759aebddd1SJeff Kirsher struct be_cmd_resp_hdr resp_hdr; 12769aebddd1SJeff Kirsher u32 status; 12779aebddd1SJeff Kirsher u32 num_txfer; 12789aebddd1SJeff Kirsher u32 num_rx; 12799aebddd1SJeff Kirsher u32 miscomp_off; 12809aebddd1SJeff Kirsher u32 ticks_compl; 12819aebddd1SJeff Kirsher }; 12829aebddd1SJeff Kirsher 12839aebddd1SJeff Kirsher struct be_cmd_req_set_lmode { 12849aebddd1SJeff Kirsher struct be_cmd_req_hdr hdr; 12859aebddd1SJeff Kirsher u8 src_port; 12869aebddd1SJeff Kirsher u8 dest_port; 12879aebddd1SJeff Kirsher u8 loopback_type; 12889aebddd1SJeff Kirsher u8 loopback_state; 12899aebddd1SJeff Kirsher }; 12909aebddd1SJeff Kirsher 12919aebddd1SJeff Kirsher struct be_cmd_resp_set_lmode { 12929aebddd1SJeff Kirsher struct be_cmd_resp_hdr resp_hdr; 12939aebddd1SJeff Kirsher u8 rsvd0[4]; 12949aebddd1SJeff Kirsher }; 12959aebddd1SJeff Kirsher 12969aebddd1SJeff Kirsher /********************** DDR DMA test *********************/ 12979aebddd1SJeff Kirsher struct be_cmd_req_ddrdma_test { 12989aebddd1SJeff Kirsher struct be_cmd_req_hdr hdr; 12999aebddd1SJeff Kirsher u64 pattern; 13009aebddd1SJeff Kirsher u32 byte_count; 13019aebddd1SJeff Kirsher u32 rsvd0; 13029aebddd1SJeff Kirsher u8 snd_buff[4096]; 13039aebddd1SJeff Kirsher u8 rsvd1[4096]; 13049aebddd1SJeff Kirsher }; 13059aebddd1SJeff Kirsher 13069aebddd1SJeff Kirsher struct be_cmd_resp_ddrdma_test { 13079aebddd1SJeff Kirsher struct be_cmd_resp_hdr hdr; 13089aebddd1SJeff Kirsher u64 pattern; 13099aebddd1SJeff Kirsher u32 byte_cnt; 13109aebddd1SJeff Kirsher u32 snd_err; 13119aebddd1SJeff Kirsher u8 rsvd0[4096]; 13129aebddd1SJeff Kirsher u8 rcv_buff[4096]; 13139aebddd1SJeff Kirsher }; 13149aebddd1SJeff Kirsher 13159aebddd1SJeff Kirsher /*********************** SEEPROM Read ***********************/ 13169aebddd1SJeff Kirsher 13179aebddd1SJeff Kirsher #define BE_READ_SEEPROM_LEN 1024 13189aebddd1SJeff Kirsher struct be_cmd_req_seeprom_read { 13199aebddd1SJeff Kirsher struct be_cmd_req_hdr hdr; 13209aebddd1SJeff Kirsher u8 rsvd0[BE_READ_SEEPROM_LEN]; 13219aebddd1SJeff Kirsher }; 13229aebddd1SJeff Kirsher 13239aebddd1SJeff Kirsher struct be_cmd_resp_seeprom_read { 13249aebddd1SJeff Kirsher struct be_cmd_req_hdr hdr; 13259aebddd1SJeff Kirsher u8 seeprom_data[BE_READ_SEEPROM_LEN]; 13269aebddd1SJeff Kirsher }; 13279aebddd1SJeff Kirsher 13289aebddd1SJeff Kirsher enum { 13299aebddd1SJeff Kirsher PHY_TYPE_CX4_10GB = 0, 13309aebddd1SJeff Kirsher PHY_TYPE_XFP_10GB, 13319aebddd1SJeff Kirsher PHY_TYPE_SFP_1GB, 13329aebddd1SJeff Kirsher PHY_TYPE_SFP_PLUS_10GB, 13339aebddd1SJeff Kirsher PHY_TYPE_KR_10GB, 13349aebddd1SJeff Kirsher PHY_TYPE_KX4_10GB, 13359aebddd1SJeff Kirsher PHY_TYPE_BASET_10GB, 13369aebddd1SJeff Kirsher PHY_TYPE_BASET_1GB, 133742f11cf2SAjit Khaparde PHY_TYPE_BASEX_1GB, 133842f11cf2SAjit Khaparde PHY_TYPE_SGMII, 13399aebddd1SJeff Kirsher PHY_TYPE_DISABLED = 255 13409aebddd1SJeff Kirsher }; 13419aebddd1SJeff Kirsher 134242f11cf2SAjit Khaparde #define BE_SUPPORTED_SPEED_NONE 0 134342f11cf2SAjit Khaparde #define BE_SUPPORTED_SPEED_10MBPS 1 134442f11cf2SAjit Khaparde #define BE_SUPPORTED_SPEED_100MBPS 2 134542f11cf2SAjit Khaparde #define BE_SUPPORTED_SPEED_1GBPS 4 134642f11cf2SAjit Khaparde #define BE_SUPPORTED_SPEED_10GBPS 8 134742f11cf2SAjit Khaparde 134842f11cf2SAjit Khaparde #define BE_AN_EN 0x2 134942f11cf2SAjit Khaparde #define BE_PAUSE_SYM_EN 0x80 135042f11cf2SAjit Khaparde 135142f11cf2SAjit Khaparde /* MAC speed valid values */ 135242f11cf2SAjit Khaparde #define SPEED_DEFAULT 0x0 135342f11cf2SAjit Khaparde #define SPEED_FORCED_10GB 0x1 135442f11cf2SAjit Khaparde #define SPEED_FORCED_1GB 0x2 135542f11cf2SAjit Khaparde #define SPEED_AUTONEG_10GB 0x3 135642f11cf2SAjit Khaparde #define SPEED_AUTONEG_1GB 0x4 135742f11cf2SAjit Khaparde #define SPEED_AUTONEG_100MB 0x5 135842f11cf2SAjit Khaparde #define SPEED_AUTONEG_10GB_1GB 0x6 135942f11cf2SAjit Khaparde #define SPEED_AUTONEG_10GB_1GB_100MB 0x7 136042f11cf2SAjit Khaparde #define SPEED_AUTONEG_1GB_100MB 0x8 136142f11cf2SAjit Khaparde #define SPEED_AUTONEG_10MB 0x9 136242f11cf2SAjit Khaparde #define SPEED_AUTONEG_1GB_100MB_10MB 0xa 136342f11cf2SAjit Khaparde #define SPEED_AUTONEG_100MB_10MB 0xb 136442f11cf2SAjit Khaparde #define SPEED_FORCED_100MB 0xc 136542f11cf2SAjit Khaparde #define SPEED_FORCED_10MB 0xd 136642f11cf2SAjit Khaparde 13679aebddd1SJeff Kirsher struct be_cmd_req_get_phy_info { 13689aebddd1SJeff Kirsher struct be_cmd_req_hdr hdr; 13699aebddd1SJeff Kirsher u8 rsvd0[24]; 13709aebddd1SJeff Kirsher }; 13719aebddd1SJeff Kirsher 13729aebddd1SJeff Kirsher struct be_phy_info { 13739aebddd1SJeff Kirsher u16 phy_type; 13749aebddd1SJeff Kirsher u16 interface_type; 13759aebddd1SJeff Kirsher u32 misc_params; 137642f11cf2SAjit Khaparde u16 ext_phy_details; 137742f11cf2SAjit Khaparde u16 rsvd; 137842f11cf2SAjit Khaparde u16 auto_speeds_supported; 137942f11cf2SAjit Khaparde u16 fixed_speeds_supported; 138042f11cf2SAjit Khaparde u32 future_use[2]; 13819aebddd1SJeff Kirsher }; 13829aebddd1SJeff Kirsher 13839aebddd1SJeff Kirsher struct be_cmd_resp_get_phy_info { 13849aebddd1SJeff Kirsher struct be_cmd_req_hdr hdr; 13859aebddd1SJeff Kirsher struct be_phy_info phy_info; 13869aebddd1SJeff Kirsher }; 13879aebddd1SJeff Kirsher 13889aebddd1SJeff Kirsher /*********************** Set QOS ***********************/ 13899aebddd1SJeff Kirsher 13909aebddd1SJeff Kirsher #define BE_QOS_BITS_NIC 1 13919aebddd1SJeff Kirsher 13929aebddd1SJeff Kirsher struct be_cmd_req_set_qos { 13939aebddd1SJeff Kirsher struct be_cmd_req_hdr hdr; 13949aebddd1SJeff Kirsher u32 valid_bits; 13959aebddd1SJeff Kirsher u32 max_bps_nic; 13969aebddd1SJeff Kirsher u32 rsvd[7]; 13979aebddd1SJeff Kirsher }; 13989aebddd1SJeff Kirsher 13999aebddd1SJeff Kirsher struct be_cmd_resp_set_qos { 14009aebddd1SJeff Kirsher struct be_cmd_resp_hdr hdr; 14019aebddd1SJeff Kirsher u32 rsvd; 14029aebddd1SJeff Kirsher }; 14039aebddd1SJeff Kirsher 14049aebddd1SJeff Kirsher /*********************** Controller Attributes ***********************/ 14059aebddd1SJeff Kirsher struct be_cmd_req_cntl_attribs { 14069aebddd1SJeff Kirsher struct be_cmd_req_hdr hdr; 14079aebddd1SJeff Kirsher }; 14089aebddd1SJeff Kirsher 14099aebddd1SJeff Kirsher struct be_cmd_resp_cntl_attribs { 14109aebddd1SJeff Kirsher struct be_cmd_resp_hdr hdr; 14119aebddd1SJeff Kirsher struct mgmt_controller_attrib attribs; 14129aebddd1SJeff Kirsher }; 14139aebddd1SJeff Kirsher 14149aebddd1SJeff Kirsher /*********************** Set driver function ***********************/ 14159aebddd1SJeff Kirsher #define CAPABILITY_SW_TIMESTAMPS 2 14169aebddd1SJeff Kirsher #define CAPABILITY_BE3_NATIVE_ERX_API 4 14179aebddd1SJeff Kirsher 14189aebddd1SJeff Kirsher struct be_cmd_req_set_func_cap { 14199aebddd1SJeff Kirsher struct be_cmd_req_hdr hdr; 14209aebddd1SJeff Kirsher u32 valid_cap_flags; 14219aebddd1SJeff Kirsher u32 cap_flags; 14229aebddd1SJeff Kirsher u8 rsvd[212]; 14239aebddd1SJeff Kirsher }; 14249aebddd1SJeff Kirsher 14259aebddd1SJeff Kirsher struct be_cmd_resp_set_func_cap { 14269aebddd1SJeff Kirsher struct be_cmd_resp_hdr hdr; 14279aebddd1SJeff Kirsher u32 valid_cap_flags; 14289aebddd1SJeff Kirsher u32 cap_flags; 14299aebddd1SJeff Kirsher u8 rsvd[212]; 14309aebddd1SJeff Kirsher }; 14319aebddd1SJeff Kirsher 1432590c391dSPadmanabh Ratnakar /******************** GET/SET_MACLIST **************************/ 1433590c391dSPadmanabh Ratnakar #define BE_MAX_MAC 64 1434590c391dSPadmanabh Ratnakar struct be_cmd_req_get_mac_list { 1435590c391dSPadmanabh Ratnakar struct be_cmd_req_hdr hdr; 1436e5e1ee89SPadmanabh Ratnakar u8 mac_type; 1437e5e1ee89SPadmanabh Ratnakar u8 perm_override; 1438e5e1ee89SPadmanabh Ratnakar u16 iface_id; 1439e5e1ee89SPadmanabh Ratnakar u32 mac_id; 1440e5e1ee89SPadmanabh Ratnakar u32 rsvd[3]; 1441e5e1ee89SPadmanabh Ratnakar } __packed; 1442e5e1ee89SPadmanabh Ratnakar 1443e5e1ee89SPadmanabh Ratnakar struct get_list_macaddr { 1444e5e1ee89SPadmanabh Ratnakar u16 mac_addr_size; 1445e5e1ee89SPadmanabh Ratnakar union { 1446e5e1ee89SPadmanabh Ratnakar u8 macaddr[6]; 1447e5e1ee89SPadmanabh Ratnakar struct { 1448e5e1ee89SPadmanabh Ratnakar u8 rsvd[2]; 1449e5e1ee89SPadmanabh Ratnakar u32 mac_id; 1450e5e1ee89SPadmanabh Ratnakar } __packed s_mac_id; 1451e5e1ee89SPadmanabh Ratnakar } __packed mac_addr_id; 1452590c391dSPadmanabh Ratnakar } __packed; 1453590c391dSPadmanabh Ratnakar 1454590c391dSPadmanabh Ratnakar struct be_cmd_resp_get_mac_list { 1455590c391dSPadmanabh Ratnakar struct be_cmd_resp_hdr hdr; 1456e5e1ee89SPadmanabh Ratnakar struct get_list_macaddr fd_macaddr; /* Factory default mac */ 1457e5e1ee89SPadmanabh Ratnakar struct get_list_macaddr macid_macaddr; /* soft mac */ 1458e5e1ee89SPadmanabh Ratnakar u8 true_mac_count; 1459e5e1ee89SPadmanabh Ratnakar u8 pseudo_mac_count; 1460e5e1ee89SPadmanabh Ratnakar u8 mac_list_size; 1461e5e1ee89SPadmanabh Ratnakar u8 rsvd; 1462e5e1ee89SPadmanabh Ratnakar /* perm override mac */ 1463e5e1ee89SPadmanabh Ratnakar struct get_list_macaddr macaddr_list[BE_MAX_MAC]; 1464590c391dSPadmanabh Ratnakar } __packed; 1465590c391dSPadmanabh Ratnakar 1466590c391dSPadmanabh Ratnakar struct be_cmd_req_set_mac_list { 1467590c391dSPadmanabh Ratnakar struct be_cmd_req_hdr hdr; 1468590c391dSPadmanabh Ratnakar u8 mac_count; 1469590c391dSPadmanabh Ratnakar u8 rsvd1; 1470590c391dSPadmanabh Ratnakar u16 rsvd2; 1471590c391dSPadmanabh Ratnakar struct macaddr mac[BE_MAX_MAC]; 1472590c391dSPadmanabh Ratnakar } __packed; 1473590c391dSPadmanabh Ratnakar 1474f1f3ee1bSAjit Khaparde /*********************** HSW Config ***********************/ 1475f1f3ee1bSAjit Khaparde struct amap_set_hsw_context { 1476f1f3ee1bSAjit Khaparde u8 interface_id[16]; 1477f1f3ee1bSAjit Khaparde u8 rsvd0[14]; 1478f1f3ee1bSAjit Khaparde u8 pvid_valid; 1479f1f3ee1bSAjit Khaparde u8 rsvd1; 1480f1f3ee1bSAjit Khaparde u8 rsvd2[16]; 1481f1f3ee1bSAjit Khaparde u8 pvid[16]; 1482f1f3ee1bSAjit Khaparde u8 rsvd3[32]; 1483f1f3ee1bSAjit Khaparde u8 rsvd4[32]; 1484f1f3ee1bSAjit Khaparde u8 rsvd5[32]; 1485f1f3ee1bSAjit Khaparde } __packed; 1486f1f3ee1bSAjit Khaparde 1487f1f3ee1bSAjit Khaparde struct be_cmd_req_set_hsw_config { 1488f1f3ee1bSAjit Khaparde struct be_cmd_req_hdr hdr; 1489f1f3ee1bSAjit Khaparde u8 context[sizeof(struct amap_set_hsw_context) / 8]; 1490f1f3ee1bSAjit Khaparde } __packed; 1491f1f3ee1bSAjit Khaparde 1492f1f3ee1bSAjit Khaparde struct be_cmd_resp_set_hsw_config { 1493f1f3ee1bSAjit Khaparde struct be_cmd_resp_hdr hdr; 1494f1f3ee1bSAjit Khaparde u32 rsvd; 1495f1f3ee1bSAjit Khaparde }; 1496f1f3ee1bSAjit Khaparde 1497f1f3ee1bSAjit Khaparde struct amap_get_hsw_req_context { 1498f1f3ee1bSAjit Khaparde u8 interface_id[16]; 1499f1f3ee1bSAjit Khaparde u8 rsvd0[14]; 1500f1f3ee1bSAjit Khaparde u8 pvid_valid; 1501f1f3ee1bSAjit Khaparde u8 pport; 1502f1f3ee1bSAjit Khaparde } __packed; 1503f1f3ee1bSAjit Khaparde 1504f1f3ee1bSAjit Khaparde struct amap_get_hsw_resp_context { 1505f1f3ee1bSAjit Khaparde u8 rsvd1[16]; 1506f1f3ee1bSAjit Khaparde u8 pvid[16]; 1507f1f3ee1bSAjit Khaparde u8 rsvd2[32]; 1508f1f3ee1bSAjit Khaparde u8 rsvd3[32]; 1509f1f3ee1bSAjit Khaparde u8 rsvd4[32]; 1510f1f3ee1bSAjit Khaparde } __packed; 1511f1f3ee1bSAjit Khaparde 1512f1f3ee1bSAjit Khaparde struct be_cmd_req_get_hsw_config { 1513f1f3ee1bSAjit Khaparde struct be_cmd_req_hdr hdr; 1514f1f3ee1bSAjit Khaparde u8 context[sizeof(struct amap_get_hsw_req_context) / 8]; 1515f1f3ee1bSAjit Khaparde } __packed; 1516f1f3ee1bSAjit Khaparde 1517f1f3ee1bSAjit Khaparde struct be_cmd_resp_get_hsw_config { 1518f1f3ee1bSAjit Khaparde struct be_cmd_resp_hdr hdr; 1519f1f3ee1bSAjit Khaparde u8 context[sizeof(struct amap_get_hsw_resp_context) / 8]; 1520f1f3ee1bSAjit Khaparde u32 rsvd; 1521f1f3ee1bSAjit Khaparde }; 1522f1f3ee1bSAjit Khaparde 1523b4e32a71SPadmanabh Ratnakar /******************* get port names ***************/ 1524b4e32a71SPadmanabh Ratnakar struct be_cmd_req_get_port_name { 1525b4e32a71SPadmanabh Ratnakar struct be_cmd_req_hdr hdr; 1526b4e32a71SPadmanabh Ratnakar u32 rsvd0; 1527b4e32a71SPadmanabh Ratnakar }; 1528b4e32a71SPadmanabh Ratnakar 1529b4e32a71SPadmanabh Ratnakar struct be_cmd_resp_get_port_name { 1530b4e32a71SPadmanabh Ratnakar struct be_cmd_req_hdr hdr; 1531b4e32a71SPadmanabh Ratnakar u8 port_name[4]; 1532b4e32a71SPadmanabh Ratnakar }; 1533b4e32a71SPadmanabh Ratnakar 15349aebddd1SJeff Kirsher /*************** HW Stats Get v1 **********************************/ 15359aebddd1SJeff Kirsher #define BE_TXP_SW_SZ 48 15369aebddd1SJeff Kirsher struct be_port_rxf_stats_v1 { 15379aebddd1SJeff Kirsher u32 rsvd0[12]; 15389aebddd1SJeff Kirsher u32 rx_crc_errors; 15399aebddd1SJeff Kirsher u32 rx_alignment_symbol_errors; 15409aebddd1SJeff Kirsher u32 rx_pause_frames; 15419aebddd1SJeff Kirsher u32 rx_priority_pause_frames; 15429aebddd1SJeff Kirsher u32 rx_control_frames; 15439aebddd1SJeff Kirsher u32 rx_in_range_errors; 15449aebddd1SJeff Kirsher u32 rx_out_range_errors; 15459aebddd1SJeff Kirsher u32 rx_frame_too_long; 1546d45b9d39SSathya Perla u32 rx_address_mismatch_drops; 15479aebddd1SJeff Kirsher u32 rx_dropped_too_small; 15489aebddd1SJeff Kirsher u32 rx_dropped_too_short; 15499aebddd1SJeff Kirsher u32 rx_dropped_header_too_small; 15509aebddd1SJeff Kirsher u32 rx_dropped_tcp_length; 15519aebddd1SJeff Kirsher u32 rx_dropped_runt; 15529aebddd1SJeff Kirsher u32 rsvd1[10]; 15539aebddd1SJeff Kirsher u32 rx_ip_checksum_errs; 15549aebddd1SJeff Kirsher u32 rx_tcp_checksum_errs; 15559aebddd1SJeff Kirsher u32 rx_udp_checksum_errs; 15569aebddd1SJeff Kirsher u32 rsvd2[7]; 15579aebddd1SJeff Kirsher u32 rx_switched_unicast_packets; 15589aebddd1SJeff Kirsher u32 rx_switched_multicast_packets; 15599aebddd1SJeff Kirsher u32 rx_switched_broadcast_packets; 15609aebddd1SJeff Kirsher u32 rsvd3[3]; 15619aebddd1SJeff Kirsher u32 tx_pauseframes; 15629aebddd1SJeff Kirsher u32 tx_priority_pauseframes; 15639aebddd1SJeff Kirsher u32 tx_controlframes; 15649aebddd1SJeff Kirsher u32 rsvd4[10]; 15659aebddd1SJeff Kirsher u32 rxpp_fifo_overflow_drop; 15669aebddd1SJeff Kirsher u32 rx_input_fifo_overflow_drop; 15679aebddd1SJeff Kirsher u32 pmem_fifo_overflow_drop; 15689aebddd1SJeff Kirsher u32 jabber_events; 15699aebddd1SJeff Kirsher u32 rsvd5[3]; 15709aebddd1SJeff Kirsher }; 15719aebddd1SJeff Kirsher 15729aebddd1SJeff Kirsher 15739aebddd1SJeff Kirsher struct be_rxf_stats_v1 { 15749aebddd1SJeff Kirsher struct be_port_rxf_stats_v1 port[4]; 15759aebddd1SJeff Kirsher u32 rsvd0[2]; 15769aebddd1SJeff Kirsher u32 rx_drops_no_pbuf; 15779aebddd1SJeff Kirsher u32 rx_drops_no_txpb; 15789aebddd1SJeff Kirsher u32 rx_drops_no_erx_descr; 15799aebddd1SJeff Kirsher u32 rx_drops_no_tpre_descr; 15809aebddd1SJeff Kirsher u32 rsvd1[6]; 15819aebddd1SJeff Kirsher u32 rx_drops_too_many_frags; 15829aebddd1SJeff Kirsher u32 rx_drops_invalid_ring; 15839aebddd1SJeff Kirsher u32 forwarded_packets; 15849aebddd1SJeff Kirsher u32 rx_drops_mtu; 15859aebddd1SJeff Kirsher u32 rsvd2[14]; 15869aebddd1SJeff Kirsher }; 15879aebddd1SJeff Kirsher 15889aebddd1SJeff Kirsher struct be_erx_stats_v1 { 15899aebddd1SJeff Kirsher u32 rx_drops_no_fragments[68]; /* dwordS 0 to 67*/ 15909aebddd1SJeff Kirsher u32 rsvd[4]; 15919aebddd1SJeff Kirsher }; 15929aebddd1SJeff Kirsher 15939aebddd1SJeff Kirsher struct be_hw_stats_v1 { 15949aebddd1SJeff Kirsher struct be_rxf_stats_v1 rxf; 15959aebddd1SJeff Kirsher u32 rsvd0[BE_TXP_SW_SZ]; 15969aebddd1SJeff Kirsher struct be_erx_stats_v1 erx; 15979aebddd1SJeff Kirsher struct be_pmem_stats pmem; 15980b3f0e7aSVasundhara Volam u32 rsvd1[18]; 15999aebddd1SJeff Kirsher }; 16009aebddd1SJeff Kirsher 16019aebddd1SJeff Kirsher struct be_cmd_req_get_stats_v1 { 16029aebddd1SJeff Kirsher struct be_cmd_req_hdr hdr; 16039aebddd1SJeff Kirsher u8 rsvd[sizeof(struct be_hw_stats_v1)]; 16049aebddd1SJeff Kirsher }; 16059aebddd1SJeff Kirsher 16069aebddd1SJeff Kirsher struct be_cmd_resp_get_stats_v1 { 16079aebddd1SJeff Kirsher struct be_cmd_resp_hdr hdr; 16089aebddd1SJeff Kirsher struct be_hw_stats_v1 hw_stats; 16099aebddd1SJeff Kirsher }; 16109aebddd1SJeff Kirsher 16119aebddd1SJeff Kirsher static inline void *hw_stats_from_cmd(struct be_adapter *adapter) 16129aebddd1SJeff Kirsher { 16139aebddd1SJeff Kirsher if (adapter->generation == BE_GEN3) { 16149aebddd1SJeff Kirsher struct be_cmd_resp_get_stats_v1 *cmd = adapter->stats_cmd.va; 16159aebddd1SJeff Kirsher 16169aebddd1SJeff Kirsher return &cmd->hw_stats; 16179aebddd1SJeff Kirsher } else { 16189aebddd1SJeff Kirsher struct be_cmd_resp_get_stats_v0 *cmd = adapter->stats_cmd.va; 16199aebddd1SJeff Kirsher 16209aebddd1SJeff Kirsher return &cmd->hw_stats; 16219aebddd1SJeff Kirsher } 16229aebddd1SJeff Kirsher } 16239aebddd1SJeff Kirsher 16249aebddd1SJeff Kirsher static inline void *be_erx_stats_from_cmd(struct be_adapter *adapter) 16259aebddd1SJeff Kirsher { 16269aebddd1SJeff Kirsher if (adapter->generation == BE_GEN3) { 16279aebddd1SJeff Kirsher struct be_hw_stats_v1 *hw_stats = hw_stats_from_cmd(adapter); 16289aebddd1SJeff Kirsher 16299aebddd1SJeff Kirsher return &hw_stats->erx; 16309aebddd1SJeff Kirsher } else { 16319aebddd1SJeff Kirsher struct be_hw_stats_v0 *hw_stats = hw_stats_from_cmd(adapter); 16329aebddd1SJeff Kirsher 16339aebddd1SJeff Kirsher return &hw_stats->erx; 16349aebddd1SJeff Kirsher } 16359aebddd1SJeff Kirsher } 16369aebddd1SJeff Kirsher 1637941a77d5SSomnath Kotur 1638941a77d5SSomnath Kotur /************** get fat capabilites *******************/ 1639941a77d5SSomnath Kotur #define MAX_MODULES 27 1640941a77d5SSomnath Kotur #define MAX_MODES 4 1641941a77d5SSomnath Kotur #define MODE_UART 0 1642941a77d5SSomnath Kotur #define FW_LOG_LEVEL_DEFAULT 48 1643941a77d5SSomnath Kotur #define FW_LOG_LEVEL_FATAL 64 1644941a77d5SSomnath Kotur 1645941a77d5SSomnath Kotur struct ext_fat_mode { 1646941a77d5SSomnath Kotur u8 mode; 1647941a77d5SSomnath Kotur u8 rsvd0; 1648941a77d5SSomnath Kotur u16 port_mask; 1649941a77d5SSomnath Kotur u32 dbg_lvl; 1650941a77d5SSomnath Kotur u64 fun_mask; 1651941a77d5SSomnath Kotur } __packed; 1652941a77d5SSomnath Kotur 1653941a77d5SSomnath Kotur struct ext_fat_modules { 1654941a77d5SSomnath Kotur u8 modules_str[32]; 1655941a77d5SSomnath Kotur u32 modules_id; 1656941a77d5SSomnath Kotur u32 num_modes; 1657941a77d5SSomnath Kotur struct ext_fat_mode trace_lvl[MAX_MODES]; 1658941a77d5SSomnath Kotur } __packed; 1659941a77d5SSomnath Kotur 1660941a77d5SSomnath Kotur struct be_fat_conf_params { 1661941a77d5SSomnath Kotur u32 max_log_entries; 1662941a77d5SSomnath Kotur u32 log_entry_size; 1663941a77d5SSomnath Kotur u8 log_type; 1664941a77d5SSomnath Kotur u8 max_log_funs; 1665941a77d5SSomnath Kotur u8 max_log_ports; 1666941a77d5SSomnath Kotur u8 rsvd0; 1667941a77d5SSomnath Kotur u32 supp_modes; 1668941a77d5SSomnath Kotur u32 num_modules; 1669941a77d5SSomnath Kotur struct ext_fat_modules module[MAX_MODULES]; 1670941a77d5SSomnath Kotur } __packed; 1671941a77d5SSomnath Kotur 1672941a77d5SSomnath Kotur struct be_cmd_req_get_ext_fat_caps { 1673941a77d5SSomnath Kotur struct be_cmd_req_hdr hdr; 1674941a77d5SSomnath Kotur u32 parameter_type; 1675941a77d5SSomnath Kotur }; 1676941a77d5SSomnath Kotur 1677941a77d5SSomnath Kotur struct be_cmd_resp_get_ext_fat_caps { 1678941a77d5SSomnath Kotur struct be_cmd_resp_hdr hdr; 1679941a77d5SSomnath Kotur struct be_fat_conf_params get_params; 1680941a77d5SSomnath Kotur }; 1681941a77d5SSomnath Kotur 1682941a77d5SSomnath Kotur struct be_cmd_req_set_ext_fat_caps { 1683941a77d5SSomnath Kotur struct be_cmd_req_hdr hdr; 1684941a77d5SSomnath Kotur struct be_fat_conf_params set_params; 1685941a77d5SSomnath Kotur }; 1686941a77d5SSomnath Kotur 16879aebddd1SJeff Kirsher extern int be_pci_fnum_get(struct be_adapter *adapter); 1688bf99e50dSPadmanabh Ratnakar extern int be_fw_wait_ready(struct be_adapter *adapter); 16899aebddd1SJeff Kirsher extern int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr, 1690590c391dSPadmanabh Ratnakar u8 type, bool permanent, u32 if_handle, u32 pmac_id); 16919aebddd1SJeff Kirsher extern int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr, 16929aebddd1SJeff Kirsher u32 if_id, u32 *pmac_id, u32 domain); 16939aebddd1SJeff Kirsher extern int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, 169430128031SSathya Perla int pmac_id, u32 domain); 16959aebddd1SJeff Kirsher extern int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, 16961578e777SPadmanabh Ratnakar u32 en_flags, u32 *if_handle, u32 domain); 169730128031SSathya Perla extern int be_cmd_if_destroy(struct be_adapter *adapter, int if_handle, 16989aebddd1SJeff Kirsher u32 domain); 16999aebddd1SJeff Kirsher extern int be_cmd_eq_create(struct be_adapter *adapter, 17009aebddd1SJeff Kirsher struct be_queue_info *eq, int eq_delay); 17019aebddd1SJeff Kirsher extern int be_cmd_cq_create(struct be_adapter *adapter, 17029aebddd1SJeff Kirsher struct be_queue_info *cq, struct be_queue_info *eq, 170310ef9ab4SSathya Perla bool no_delay, int num_cqe_dma_coalesce); 17049aebddd1SJeff Kirsher extern int be_cmd_mccq_create(struct be_adapter *adapter, 17059aebddd1SJeff Kirsher struct be_queue_info *mccq, 17069aebddd1SJeff Kirsher struct be_queue_info *cq); 17079aebddd1SJeff Kirsher extern int be_cmd_txq_create(struct be_adapter *adapter, 17089aebddd1SJeff Kirsher struct be_queue_info *txq, 17099aebddd1SJeff Kirsher struct be_queue_info *cq); 17109aebddd1SJeff Kirsher extern int be_cmd_rxq_create(struct be_adapter *adapter, 17119aebddd1SJeff Kirsher struct be_queue_info *rxq, u16 cq_id, 171210ef9ab4SSathya Perla u16 frag_size, u32 if_id, u32 rss, u8 *rss_id); 17139aebddd1SJeff Kirsher extern int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q, 17149aebddd1SJeff Kirsher int type); 17159aebddd1SJeff Kirsher extern int be_cmd_rxq_destroy(struct be_adapter *adapter, 17169aebddd1SJeff Kirsher struct be_queue_info *q); 1717b236916aSAjit Khaparde extern int be_cmd_link_status_query(struct be_adapter *adapter, u8 *mac_speed, 1718b236916aSAjit Khaparde u16 *link_speed, u8 *link_status, u32 dom); 17199aebddd1SJeff Kirsher extern int be_cmd_reset(struct be_adapter *adapter); 17209aebddd1SJeff Kirsher extern int be_cmd_get_stats(struct be_adapter *adapter, 17219aebddd1SJeff Kirsher struct be_dma_mem *nonemb_cmd); 17229aebddd1SJeff Kirsher extern int lancer_cmd_get_pport_stats(struct be_adapter *adapter, 17239aebddd1SJeff Kirsher struct be_dma_mem *nonemb_cmd); 172404b71175SSathya Perla extern int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver, 172504b71175SSathya Perla char *fw_on_flash); 17269aebddd1SJeff Kirsher 17279aebddd1SJeff Kirsher extern int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd); 17289aebddd1SJeff Kirsher extern int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, 17299aebddd1SJeff Kirsher u16 *vtag_array, u32 num, bool untagged, 17309aebddd1SJeff Kirsher bool promiscuous); 17319aebddd1SJeff Kirsher extern int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 status); 17329aebddd1SJeff Kirsher extern int be_cmd_set_flow_control(struct be_adapter *adapter, 17339aebddd1SJeff Kirsher u32 tx_fc, u32 rx_fc); 17349aebddd1SJeff Kirsher extern int be_cmd_get_flow_control(struct be_adapter *adapter, 17359aebddd1SJeff Kirsher u32 *tx_fc, u32 *rx_fc); 17369aebddd1SJeff Kirsher extern int be_cmd_query_fw_cfg(struct be_adapter *adapter, 17379aebddd1SJeff Kirsher u32 *port_num, u32 *function_mode, u32 *function_caps); 17389aebddd1SJeff Kirsher extern int be_cmd_reset_function(struct be_adapter *adapter); 17399aebddd1SJeff Kirsher extern int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable, 17409aebddd1SJeff Kirsher u16 table_size); 174110ef9ab4SSathya Perla extern int be_process_mcc(struct be_adapter *adapter); 17429aebddd1SJeff Kirsher extern int be_cmd_set_beacon_state(struct be_adapter *adapter, 17439aebddd1SJeff Kirsher u8 port_num, u8 beacon, u8 status, u8 state); 17449aebddd1SJeff Kirsher extern int be_cmd_get_beacon_state(struct be_adapter *adapter, 17459aebddd1SJeff Kirsher u8 port_num, u32 *state); 17469aebddd1SJeff Kirsher extern int be_cmd_write_flashrom(struct be_adapter *adapter, 17479aebddd1SJeff Kirsher struct be_dma_mem *cmd, u32 flash_oper, 17489aebddd1SJeff Kirsher u32 flash_opcode, u32 buf_size); 17499aebddd1SJeff Kirsher extern int lancer_cmd_write_object(struct be_adapter *adapter, 17509aebddd1SJeff Kirsher struct be_dma_mem *cmd, 17519aebddd1SJeff Kirsher u32 data_size, u32 data_offset, 17529aebddd1SJeff Kirsher const char *obj_name, 1753f67ef7baSPadmanabh Ratnakar u32 *data_written, u8 *change_status, 1754f67ef7baSPadmanabh Ratnakar u8 *addn_status); 1755de49bd5aSPadmanabh Ratnakar int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd, 1756de49bd5aSPadmanabh Ratnakar u32 data_size, u32 data_offset, const char *obj_name, 1757de49bd5aSPadmanabh Ratnakar u32 *data_read, u32 *eof, u8 *addn_status); 17589aebddd1SJeff Kirsher int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc, 17599aebddd1SJeff Kirsher int offset); 17609aebddd1SJeff Kirsher extern int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac, 17619aebddd1SJeff Kirsher struct be_dma_mem *nonemb_cmd); 17629aebddd1SJeff Kirsher extern int be_cmd_fw_init(struct be_adapter *adapter); 17639aebddd1SJeff Kirsher extern int be_cmd_fw_clean(struct be_adapter *adapter); 17649aebddd1SJeff Kirsher extern void be_async_mcc_enable(struct be_adapter *adapter); 17659aebddd1SJeff Kirsher extern void be_async_mcc_disable(struct be_adapter *adapter); 17669aebddd1SJeff Kirsher extern int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num, 17679aebddd1SJeff Kirsher u32 loopback_type, u32 pkt_size, 17689aebddd1SJeff Kirsher u32 num_pkts, u64 pattern); 17699aebddd1SJeff Kirsher extern int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern, 17709aebddd1SJeff Kirsher u32 byte_cnt, struct be_dma_mem *cmd); 17719aebddd1SJeff Kirsher extern int be_cmd_get_seeprom_data(struct be_adapter *adapter, 17729aebddd1SJeff Kirsher struct be_dma_mem *nonemb_cmd); 17739aebddd1SJeff Kirsher extern int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num, 17749aebddd1SJeff Kirsher u8 loopback_type, u8 enable); 177542f11cf2SAjit Khaparde extern int be_cmd_get_phy_info(struct be_adapter *adapter); 17769aebddd1SJeff Kirsher extern int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain); 1777f67ef7baSPadmanabh Ratnakar extern void be_detect_error(struct be_adapter *adapter); 17789aebddd1SJeff Kirsher extern int be_cmd_get_die_temperature(struct be_adapter *adapter); 17799aebddd1SJeff Kirsher extern int be_cmd_get_cntl_attributes(struct be_adapter *adapter); 17809aebddd1SJeff Kirsher extern int be_cmd_req_native_mode(struct be_adapter *adapter); 17819aebddd1SJeff Kirsher extern int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size); 17829aebddd1SJeff Kirsher extern void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf); 17831578e777SPadmanabh Ratnakar extern int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac, 17841578e777SPadmanabh Ratnakar bool *pmac_id_active, u32 *pmac_id, 17851578e777SPadmanabh Ratnakar u8 domain); 1786590c391dSPadmanabh Ratnakar extern int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array, 1787590c391dSPadmanabh Ratnakar u8 mac_count, u32 domain); 1788f1f3ee1bSAjit Khaparde extern int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid, 1789f1f3ee1bSAjit Khaparde u32 domain, u16 intf_id); 1790f1f3ee1bSAjit Khaparde extern int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid, 1791f1f3ee1bSAjit Khaparde u32 domain, u16 intf_id); 17924762f6ceSAjit Khaparde extern int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter); 1793941a77d5SSomnath Kotur extern int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter, 1794941a77d5SSomnath Kotur struct be_dma_mem *cmd); 1795941a77d5SSomnath Kotur extern int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter, 1796941a77d5SSomnath Kotur struct be_dma_mem *cmd, 1797941a77d5SSomnath Kotur struct be_fat_conf_params *cfgs); 1798bf99e50dSPadmanabh Ratnakar extern int lancer_wait_ready(struct be_adapter *adapter); 1799bf99e50dSPadmanabh Ratnakar extern int lancer_test_and_set_rdy_state(struct be_adapter *adapter); 1800b4e32a71SPadmanabh Ratnakar extern int be_cmd_query_port_name(struct be_adapter *adapter, u8 *port_name); 18019aebddd1SJeff Kirsher 1802