1 /* 2 * Copyright (C) 2005 - 2015 Emulex 3 * All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License version 2 7 * as published by the Free Software Foundation. The full GNU General 8 * Public License is included in this distribution in the file called COPYING. 9 * 10 * Contact Information: 11 * linux-drivers@emulex.com 12 * 13 * Emulex 14 * 3333 Susan Street 15 * Costa Mesa, CA 92626 16 */ 17 18 #include <linux/module.h> 19 #include "be.h" 20 #include "be_cmds.h" 21 22 static char *be_port_misconfig_evt_desc[] = { 23 "A valid SFP module detected", 24 "Optics faulted/ incorrectly installed/ not installed.", 25 "Optics of two types installed.", 26 "Incompatible optics.", 27 "Unknown port SFP status" 28 }; 29 30 static char *be_port_misconfig_remedy_desc[] = { 31 "", 32 "Reseat optics. If issue not resolved, replace", 33 "Remove one optic or install matching pair of optics", 34 "Replace with compatible optics for card to function", 35 "" 36 }; 37 38 static struct be_cmd_priv_map cmd_priv_map[] = { 39 { 40 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, 41 CMD_SUBSYSTEM_ETH, 42 BE_PRIV_LNKMGMT | BE_PRIV_VHADM | 43 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC 44 }, 45 { 46 OPCODE_COMMON_GET_FLOW_CONTROL, 47 CMD_SUBSYSTEM_COMMON, 48 BE_PRIV_LNKQUERY | BE_PRIV_VHADM | 49 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC 50 }, 51 { 52 OPCODE_COMMON_SET_FLOW_CONTROL, 53 CMD_SUBSYSTEM_COMMON, 54 BE_PRIV_LNKMGMT | BE_PRIV_VHADM | 55 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC 56 }, 57 { 58 OPCODE_ETH_GET_PPORT_STATS, 59 CMD_SUBSYSTEM_ETH, 60 BE_PRIV_LNKMGMT | BE_PRIV_VHADM | 61 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC 62 }, 63 { 64 OPCODE_COMMON_GET_PHY_DETAILS, 65 CMD_SUBSYSTEM_COMMON, 66 BE_PRIV_LNKMGMT | BE_PRIV_VHADM | 67 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC 68 } 69 }; 70 71 static bool be_cmd_allowed(struct be_adapter *adapter, u8 opcode, u8 subsystem) 72 { 73 int i; 74 int num_entries = sizeof(cmd_priv_map)/sizeof(struct be_cmd_priv_map); 75 u32 cmd_privileges = adapter->cmd_privileges; 76 77 for (i = 0; i < num_entries; i++) 78 if (opcode == cmd_priv_map[i].opcode && 79 subsystem == cmd_priv_map[i].subsystem) 80 if (!(cmd_privileges & cmd_priv_map[i].priv_mask)) 81 return false; 82 83 return true; 84 } 85 86 static inline void *embedded_payload(struct be_mcc_wrb *wrb) 87 { 88 return wrb->payload.embedded_payload; 89 } 90 91 static int be_mcc_notify(struct be_adapter *adapter) 92 { 93 struct be_queue_info *mccq = &adapter->mcc_obj.q; 94 u32 val = 0; 95 96 if (be_check_error(adapter, BE_ERROR_ANY)) 97 return -EIO; 98 99 val |= mccq->id & DB_MCCQ_RING_ID_MASK; 100 val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT; 101 102 wmb(); 103 iowrite32(val, adapter->db + DB_MCCQ_OFFSET); 104 105 return 0; 106 } 107 108 /* To check if valid bit is set, check the entire word as we don't know 109 * the endianness of the data (old entry is host endian while a new entry is 110 * little endian) */ 111 static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl) 112 { 113 u32 flags; 114 115 if (compl->flags != 0) { 116 flags = le32_to_cpu(compl->flags); 117 if (flags & CQE_FLAGS_VALID_MASK) { 118 compl->flags = flags; 119 return true; 120 } 121 } 122 return false; 123 } 124 125 /* Need to reset the entire word that houses the valid bit */ 126 static inline void be_mcc_compl_use(struct be_mcc_compl *compl) 127 { 128 compl->flags = 0; 129 } 130 131 static struct be_cmd_resp_hdr *be_decode_resp_hdr(u32 tag0, u32 tag1) 132 { 133 unsigned long addr; 134 135 addr = tag1; 136 addr = ((addr << 16) << 16) | tag0; 137 return (void *)addr; 138 } 139 140 static bool be_skip_err_log(u8 opcode, u16 base_status, u16 addl_status) 141 { 142 if (base_status == MCC_STATUS_NOT_SUPPORTED || 143 base_status == MCC_STATUS_ILLEGAL_REQUEST || 144 addl_status == MCC_ADDL_STATUS_TOO_MANY_INTERFACES || 145 addl_status == MCC_ADDL_STATUS_INSUFFICIENT_VLANS || 146 (opcode == OPCODE_COMMON_WRITE_FLASHROM && 147 (base_status == MCC_STATUS_ILLEGAL_FIELD || 148 addl_status == MCC_ADDL_STATUS_FLASH_IMAGE_CRC_MISMATCH))) 149 return true; 150 else 151 return false; 152 } 153 154 /* Place holder for all the async MCC cmds wherein the caller is not in a busy 155 * loop (has not issued be_mcc_notify_wait()) 156 */ 157 static void be_async_cmd_process(struct be_adapter *adapter, 158 struct be_mcc_compl *compl, 159 struct be_cmd_resp_hdr *resp_hdr) 160 { 161 enum mcc_base_status base_status = base_status(compl->status); 162 u8 opcode = 0, subsystem = 0; 163 164 if (resp_hdr) { 165 opcode = resp_hdr->opcode; 166 subsystem = resp_hdr->subsystem; 167 } 168 169 if (opcode == OPCODE_LOWLEVEL_LOOPBACK_TEST && 170 subsystem == CMD_SUBSYSTEM_LOWLEVEL) { 171 complete(&adapter->et_cmd_compl); 172 return; 173 } 174 175 if (opcode == OPCODE_LOWLEVEL_SET_LOOPBACK_MODE && 176 subsystem == CMD_SUBSYSTEM_LOWLEVEL) { 177 complete(&adapter->et_cmd_compl); 178 return; 179 } 180 181 if ((opcode == OPCODE_COMMON_WRITE_FLASHROM || 182 opcode == OPCODE_COMMON_WRITE_OBJECT) && 183 subsystem == CMD_SUBSYSTEM_COMMON) { 184 adapter->flash_status = compl->status; 185 complete(&adapter->et_cmd_compl); 186 return; 187 } 188 189 if ((opcode == OPCODE_ETH_GET_STATISTICS || 190 opcode == OPCODE_ETH_GET_PPORT_STATS) && 191 subsystem == CMD_SUBSYSTEM_ETH && 192 base_status == MCC_STATUS_SUCCESS) { 193 be_parse_stats(adapter); 194 adapter->stats_cmd_sent = false; 195 return; 196 } 197 198 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES && 199 subsystem == CMD_SUBSYSTEM_COMMON) { 200 if (base_status == MCC_STATUS_SUCCESS) { 201 struct be_cmd_resp_get_cntl_addnl_attribs *resp = 202 (void *)resp_hdr; 203 adapter->hwmon_info.be_on_die_temp = 204 resp->on_die_temperature; 205 } else { 206 adapter->be_get_temp_freq = 0; 207 adapter->hwmon_info.be_on_die_temp = 208 BE_INVALID_DIE_TEMP; 209 } 210 return; 211 } 212 } 213 214 static int be_mcc_compl_process(struct be_adapter *adapter, 215 struct be_mcc_compl *compl) 216 { 217 enum mcc_base_status base_status; 218 enum mcc_addl_status addl_status; 219 struct be_cmd_resp_hdr *resp_hdr; 220 u8 opcode = 0, subsystem = 0; 221 222 /* Just swap the status to host endian; mcc tag is opaquely copied 223 * from mcc_wrb */ 224 be_dws_le_to_cpu(compl, 4); 225 226 base_status = base_status(compl->status); 227 addl_status = addl_status(compl->status); 228 229 resp_hdr = be_decode_resp_hdr(compl->tag0, compl->tag1); 230 if (resp_hdr) { 231 opcode = resp_hdr->opcode; 232 subsystem = resp_hdr->subsystem; 233 } 234 235 be_async_cmd_process(adapter, compl, resp_hdr); 236 237 if (base_status != MCC_STATUS_SUCCESS && 238 !be_skip_err_log(opcode, base_status, addl_status)) { 239 if (base_status == MCC_STATUS_UNAUTHORIZED_REQUEST) { 240 dev_warn(&adapter->pdev->dev, 241 "VF is not privileged to issue opcode %d-%d\n", 242 opcode, subsystem); 243 } else { 244 dev_err(&adapter->pdev->dev, 245 "opcode %d-%d failed:status %d-%d\n", 246 opcode, subsystem, base_status, addl_status); 247 } 248 } 249 return compl->status; 250 } 251 252 /* Link state evt is a string of bytes; no need for endian swapping */ 253 static void be_async_link_state_process(struct be_adapter *adapter, 254 struct be_mcc_compl *compl) 255 { 256 struct be_async_event_link_state *evt = 257 (struct be_async_event_link_state *)compl; 258 259 /* When link status changes, link speed must be re-queried from FW */ 260 adapter->phy.link_speed = -1; 261 262 /* On BEx the FW does not send a separate link status 263 * notification for physical and logical link. 264 * On other chips just process the logical link 265 * status notification 266 */ 267 if (!BEx_chip(adapter) && 268 !(evt->port_link_status & LOGICAL_LINK_STATUS_MASK)) 269 return; 270 271 /* For the initial link status do not rely on the ASYNC event as 272 * it may not be received in some cases. 273 */ 274 if (adapter->flags & BE_FLAGS_LINK_STATUS_INIT) 275 be_link_status_update(adapter, 276 evt->port_link_status & LINK_STATUS_MASK); 277 } 278 279 static void be_async_port_misconfig_event_process(struct be_adapter *adapter, 280 struct be_mcc_compl *compl) 281 { 282 struct be_async_event_misconfig_port *evt = 283 (struct be_async_event_misconfig_port *)compl; 284 u32 sfp_mismatch_evt = le32_to_cpu(evt->event_data_word1); 285 struct device *dev = &adapter->pdev->dev; 286 u8 port_misconfig_evt; 287 288 port_misconfig_evt = 289 ((sfp_mismatch_evt >> (adapter->hba_port_num * 8)) & 0xff); 290 291 /* Log an error message that would allow a user to determine 292 * whether the SFPs have an issue 293 */ 294 dev_info(dev, "Port %c: %s %s", adapter->port_name, 295 be_port_misconfig_evt_desc[port_misconfig_evt], 296 be_port_misconfig_remedy_desc[port_misconfig_evt]); 297 298 if (port_misconfig_evt == INCOMPATIBLE_SFP) 299 adapter->flags |= BE_FLAGS_EVT_INCOMPATIBLE_SFP; 300 } 301 302 /* Grp5 CoS Priority evt */ 303 static void be_async_grp5_cos_priority_process(struct be_adapter *adapter, 304 struct be_mcc_compl *compl) 305 { 306 struct be_async_event_grp5_cos_priority *evt = 307 (struct be_async_event_grp5_cos_priority *)compl; 308 309 if (evt->valid) { 310 adapter->vlan_prio_bmap = evt->available_priority_bmap; 311 adapter->recommended_prio_bits = 312 evt->reco_default_priority << VLAN_PRIO_SHIFT; 313 } 314 } 315 316 /* Grp5 QOS Speed evt: qos_link_speed is in units of 10 Mbps */ 317 static void be_async_grp5_qos_speed_process(struct be_adapter *adapter, 318 struct be_mcc_compl *compl) 319 { 320 struct be_async_event_grp5_qos_link_speed *evt = 321 (struct be_async_event_grp5_qos_link_speed *)compl; 322 323 if (adapter->phy.link_speed >= 0 && 324 evt->physical_port == adapter->port_num) 325 adapter->phy.link_speed = le16_to_cpu(evt->qos_link_speed) * 10; 326 } 327 328 /*Grp5 PVID evt*/ 329 static void be_async_grp5_pvid_state_process(struct be_adapter *adapter, 330 struct be_mcc_compl *compl) 331 { 332 struct be_async_event_grp5_pvid_state *evt = 333 (struct be_async_event_grp5_pvid_state *)compl; 334 335 if (evt->enabled) { 336 adapter->pvid = le16_to_cpu(evt->tag) & VLAN_VID_MASK; 337 dev_info(&adapter->pdev->dev, "LPVID: %d\n", adapter->pvid); 338 } else { 339 adapter->pvid = 0; 340 } 341 } 342 343 #define MGMT_ENABLE_MASK 0x4 344 static void be_async_grp5_fw_control_process(struct be_adapter *adapter, 345 struct be_mcc_compl *compl) 346 { 347 struct be_async_fw_control *evt = (struct be_async_fw_control *)compl; 348 u32 evt_dw1 = le32_to_cpu(evt->event_data_word1); 349 350 if (evt_dw1 & MGMT_ENABLE_MASK) { 351 adapter->flags |= BE_FLAGS_OS2BMC; 352 adapter->bmc_filt_mask = le32_to_cpu(evt->event_data_word2); 353 } else { 354 adapter->flags &= ~BE_FLAGS_OS2BMC; 355 } 356 } 357 358 static void be_async_grp5_evt_process(struct be_adapter *adapter, 359 struct be_mcc_compl *compl) 360 { 361 u8 event_type = (compl->flags >> ASYNC_EVENT_TYPE_SHIFT) & 362 ASYNC_EVENT_TYPE_MASK; 363 364 switch (event_type) { 365 case ASYNC_EVENT_COS_PRIORITY: 366 be_async_grp5_cos_priority_process(adapter, compl); 367 break; 368 case ASYNC_EVENT_QOS_SPEED: 369 be_async_grp5_qos_speed_process(adapter, compl); 370 break; 371 case ASYNC_EVENT_PVID_STATE: 372 be_async_grp5_pvid_state_process(adapter, compl); 373 break; 374 /* Async event to disable/enable os2bmc and/or mac-learning */ 375 case ASYNC_EVENT_FW_CONTROL: 376 be_async_grp5_fw_control_process(adapter, compl); 377 break; 378 default: 379 break; 380 } 381 } 382 383 static void be_async_dbg_evt_process(struct be_adapter *adapter, 384 struct be_mcc_compl *cmp) 385 { 386 u8 event_type = 0; 387 struct be_async_event_qnq *evt = (struct be_async_event_qnq *)cmp; 388 389 event_type = (cmp->flags >> ASYNC_EVENT_TYPE_SHIFT) & 390 ASYNC_EVENT_TYPE_MASK; 391 392 switch (event_type) { 393 case ASYNC_DEBUG_EVENT_TYPE_QNQ: 394 if (evt->valid) 395 adapter->qnq_vid = le16_to_cpu(evt->vlan_tag); 396 adapter->flags |= BE_FLAGS_QNQ_ASYNC_EVT_RCVD; 397 break; 398 default: 399 dev_warn(&adapter->pdev->dev, "Unknown debug event 0x%x!\n", 400 event_type); 401 break; 402 } 403 } 404 405 static void be_async_sliport_evt_process(struct be_adapter *adapter, 406 struct be_mcc_compl *cmp) 407 { 408 u8 event_type = (cmp->flags >> ASYNC_EVENT_TYPE_SHIFT) & 409 ASYNC_EVENT_TYPE_MASK; 410 411 if (event_type == ASYNC_EVENT_PORT_MISCONFIG) 412 be_async_port_misconfig_event_process(adapter, cmp); 413 } 414 415 static inline bool is_link_state_evt(u32 flags) 416 { 417 return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) == 418 ASYNC_EVENT_CODE_LINK_STATE; 419 } 420 421 static inline bool is_grp5_evt(u32 flags) 422 { 423 return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) == 424 ASYNC_EVENT_CODE_GRP_5; 425 } 426 427 static inline bool is_dbg_evt(u32 flags) 428 { 429 return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) == 430 ASYNC_EVENT_CODE_QNQ; 431 } 432 433 static inline bool is_sliport_evt(u32 flags) 434 { 435 return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) == 436 ASYNC_EVENT_CODE_SLIPORT; 437 } 438 439 static void be_mcc_event_process(struct be_adapter *adapter, 440 struct be_mcc_compl *compl) 441 { 442 if (is_link_state_evt(compl->flags)) 443 be_async_link_state_process(adapter, compl); 444 else if (is_grp5_evt(compl->flags)) 445 be_async_grp5_evt_process(adapter, compl); 446 else if (is_dbg_evt(compl->flags)) 447 be_async_dbg_evt_process(adapter, compl); 448 else if (is_sliport_evt(compl->flags)) 449 be_async_sliport_evt_process(adapter, compl); 450 } 451 452 static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter) 453 { 454 struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq; 455 struct be_mcc_compl *compl = queue_tail_node(mcc_cq); 456 457 if (be_mcc_compl_is_new(compl)) { 458 queue_tail_inc(mcc_cq); 459 return compl; 460 } 461 return NULL; 462 } 463 464 void be_async_mcc_enable(struct be_adapter *adapter) 465 { 466 spin_lock_bh(&adapter->mcc_cq_lock); 467 468 be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0); 469 adapter->mcc_obj.rearm_cq = true; 470 471 spin_unlock_bh(&adapter->mcc_cq_lock); 472 } 473 474 void be_async_mcc_disable(struct be_adapter *adapter) 475 { 476 spin_lock_bh(&adapter->mcc_cq_lock); 477 478 adapter->mcc_obj.rearm_cq = false; 479 be_cq_notify(adapter, adapter->mcc_obj.cq.id, false, 0); 480 481 spin_unlock_bh(&adapter->mcc_cq_lock); 482 } 483 484 int be_process_mcc(struct be_adapter *adapter) 485 { 486 struct be_mcc_compl *compl; 487 int num = 0, status = 0; 488 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj; 489 490 spin_lock(&adapter->mcc_cq_lock); 491 492 while ((compl = be_mcc_compl_get(adapter))) { 493 if (compl->flags & CQE_FLAGS_ASYNC_MASK) { 494 be_mcc_event_process(adapter, compl); 495 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) { 496 status = be_mcc_compl_process(adapter, compl); 497 atomic_dec(&mcc_obj->q.used); 498 } 499 be_mcc_compl_use(compl); 500 num++; 501 } 502 503 if (num) 504 be_cq_notify(adapter, mcc_obj->cq.id, mcc_obj->rearm_cq, num); 505 506 spin_unlock(&adapter->mcc_cq_lock); 507 return status; 508 } 509 510 /* Wait till no more pending mcc requests are present */ 511 static int be_mcc_wait_compl(struct be_adapter *adapter) 512 { 513 #define mcc_timeout 120000 /* 12s timeout */ 514 int i, status = 0; 515 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj; 516 517 for (i = 0; i < mcc_timeout; i++) { 518 if (be_check_error(adapter, BE_ERROR_ANY)) 519 return -EIO; 520 521 local_bh_disable(); 522 status = be_process_mcc(adapter); 523 local_bh_enable(); 524 525 if (atomic_read(&mcc_obj->q.used) == 0) 526 break; 527 udelay(100); 528 } 529 if (i == mcc_timeout) { 530 dev_err(&adapter->pdev->dev, "FW not responding\n"); 531 be_set_error(adapter, BE_ERROR_FW); 532 return -EIO; 533 } 534 return status; 535 } 536 537 /* Notify MCC requests and wait for completion */ 538 static int be_mcc_notify_wait(struct be_adapter *adapter) 539 { 540 int status; 541 struct be_mcc_wrb *wrb; 542 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj; 543 u16 index = mcc_obj->q.head; 544 struct be_cmd_resp_hdr *resp; 545 546 index_dec(&index, mcc_obj->q.len); 547 wrb = queue_index_node(&mcc_obj->q, index); 548 549 resp = be_decode_resp_hdr(wrb->tag0, wrb->tag1); 550 551 status = be_mcc_notify(adapter); 552 if (status) 553 goto out; 554 555 status = be_mcc_wait_compl(adapter); 556 if (status == -EIO) 557 goto out; 558 559 status = (resp->base_status | 560 ((resp->addl_status & CQE_ADDL_STATUS_MASK) << 561 CQE_ADDL_STATUS_SHIFT)); 562 out: 563 return status; 564 } 565 566 static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db) 567 { 568 int msecs = 0; 569 u32 ready; 570 571 do { 572 if (be_check_error(adapter, BE_ERROR_ANY)) 573 return -EIO; 574 575 ready = ioread32(db); 576 if (ready == 0xffffffff) 577 return -1; 578 579 ready &= MPU_MAILBOX_DB_RDY_MASK; 580 if (ready) 581 break; 582 583 if (msecs > 4000) { 584 dev_err(&adapter->pdev->dev, "FW not responding\n"); 585 be_set_error(adapter, BE_ERROR_FW); 586 be_detect_error(adapter); 587 return -1; 588 } 589 590 msleep(1); 591 msecs++; 592 } while (true); 593 594 return 0; 595 } 596 597 /* 598 * Insert the mailbox address into the doorbell in two steps 599 * Polls on the mbox doorbell till a command completion (or a timeout) occurs 600 */ 601 static int be_mbox_notify_wait(struct be_adapter *adapter) 602 { 603 int status; 604 u32 val = 0; 605 void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET; 606 struct be_dma_mem *mbox_mem = &adapter->mbox_mem; 607 struct be_mcc_mailbox *mbox = mbox_mem->va; 608 struct be_mcc_compl *compl = &mbox->compl; 609 610 /* wait for ready to be set */ 611 status = be_mbox_db_ready_wait(adapter, db); 612 if (status != 0) 613 return status; 614 615 val |= MPU_MAILBOX_DB_HI_MASK; 616 /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */ 617 val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2; 618 iowrite32(val, db); 619 620 /* wait for ready to be set */ 621 status = be_mbox_db_ready_wait(adapter, db); 622 if (status != 0) 623 return status; 624 625 val = 0; 626 /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */ 627 val |= (u32)(mbox_mem->dma >> 4) << 2; 628 iowrite32(val, db); 629 630 status = be_mbox_db_ready_wait(adapter, db); 631 if (status != 0) 632 return status; 633 634 /* A cq entry has been made now */ 635 if (be_mcc_compl_is_new(compl)) { 636 status = be_mcc_compl_process(adapter, &mbox->compl); 637 be_mcc_compl_use(compl); 638 if (status) 639 return status; 640 } else { 641 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n"); 642 return -1; 643 } 644 return 0; 645 } 646 647 static u16 be_POST_stage_get(struct be_adapter *adapter) 648 { 649 u32 sem; 650 651 if (BEx_chip(adapter)) 652 sem = ioread32(adapter->csr + SLIPORT_SEMAPHORE_OFFSET_BEx); 653 else 654 pci_read_config_dword(adapter->pdev, 655 SLIPORT_SEMAPHORE_OFFSET_SH, &sem); 656 657 return sem & POST_STAGE_MASK; 658 } 659 660 static int lancer_wait_ready(struct be_adapter *adapter) 661 { 662 #define SLIPORT_READY_TIMEOUT 30 663 u32 sliport_status; 664 int i; 665 666 for (i = 0; i < SLIPORT_READY_TIMEOUT; i++) { 667 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET); 668 if (sliport_status & SLIPORT_STATUS_RDY_MASK) 669 return 0; 670 671 if (sliport_status & SLIPORT_STATUS_ERR_MASK && 672 !(sliport_status & SLIPORT_STATUS_RN_MASK)) 673 return -EIO; 674 675 msleep(1000); 676 } 677 678 return sliport_status ? : -1; 679 } 680 681 int be_fw_wait_ready(struct be_adapter *adapter) 682 { 683 u16 stage; 684 int status, timeout = 0; 685 struct device *dev = &adapter->pdev->dev; 686 687 if (lancer_chip(adapter)) { 688 status = lancer_wait_ready(adapter); 689 if (status) { 690 stage = status; 691 goto err; 692 } 693 return 0; 694 } 695 696 do { 697 /* There's no means to poll POST state on BE2/3 VFs */ 698 if (BEx_chip(adapter) && be_virtfn(adapter)) 699 return 0; 700 701 stage = be_POST_stage_get(adapter); 702 if (stage == POST_STAGE_ARMFW_RDY) 703 return 0; 704 705 dev_info(dev, "Waiting for POST, %ds elapsed\n", timeout); 706 if (msleep_interruptible(2000)) { 707 dev_err(dev, "Waiting for POST aborted\n"); 708 return -EINTR; 709 } 710 timeout += 2; 711 } while (timeout < 60); 712 713 err: 714 dev_err(dev, "POST timeout; stage=%#x\n", stage); 715 return -ETIMEDOUT; 716 } 717 718 static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb) 719 { 720 return &wrb->payload.sgl[0]; 721 } 722 723 static inline void fill_wrb_tags(struct be_mcc_wrb *wrb, unsigned long addr) 724 { 725 wrb->tag0 = addr & 0xFFFFFFFF; 726 wrb->tag1 = upper_32_bits(addr); 727 } 728 729 /* Don't touch the hdr after it's prepared */ 730 /* mem will be NULL for embedded commands */ 731 static void be_wrb_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr, 732 u8 subsystem, u8 opcode, int cmd_len, 733 struct be_mcc_wrb *wrb, 734 struct be_dma_mem *mem) 735 { 736 struct be_sge *sge; 737 738 req_hdr->opcode = opcode; 739 req_hdr->subsystem = subsystem; 740 req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr)); 741 req_hdr->version = 0; 742 fill_wrb_tags(wrb, (ulong) req_hdr); 743 wrb->payload_length = cmd_len; 744 if (mem) { 745 wrb->embedded |= (1 & MCC_WRB_SGE_CNT_MASK) << 746 MCC_WRB_SGE_CNT_SHIFT; 747 sge = nonembedded_sgl(wrb); 748 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma)); 749 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF); 750 sge->len = cpu_to_le32(mem->size); 751 } else 752 wrb->embedded |= MCC_WRB_EMBEDDED_MASK; 753 be_dws_cpu_to_le(wrb, 8); 754 } 755 756 static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages, 757 struct be_dma_mem *mem) 758 { 759 int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages); 760 u64 dma = (u64)mem->dma; 761 762 for (i = 0; i < buf_pages; i++) { 763 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF); 764 pages[i].hi = cpu_to_le32(upper_32_bits(dma)); 765 dma += PAGE_SIZE_4K; 766 } 767 } 768 769 static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter) 770 { 771 struct be_dma_mem *mbox_mem = &adapter->mbox_mem; 772 struct be_mcc_wrb *wrb 773 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb; 774 memset(wrb, 0, sizeof(*wrb)); 775 return wrb; 776 } 777 778 static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter) 779 { 780 struct be_queue_info *mccq = &adapter->mcc_obj.q; 781 struct be_mcc_wrb *wrb; 782 783 if (!mccq->created) 784 return NULL; 785 786 if (atomic_read(&mccq->used) >= mccq->len) 787 return NULL; 788 789 wrb = queue_head_node(mccq); 790 queue_head_inc(mccq); 791 atomic_inc(&mccq->used); 792 memset(wrb, 0, sizeof(*wrb)); 793 return wrb; 794 } 795 796 static bool use_mcc(struct be_adapter *adapter) 797 { 798 return adapter->mcc_obj.q.created; 799 } 800 801 /* Must be used only in process context */ 802 static int be_cmd_lock(struct be_adapter *adapter) 803 { 804 if (use_mcc(adapter)) { 805 spin_lock_bh(&adapter->mcc_lock); 806 return 0; 807 } else { 808 return mutex_lock_interruptible(&adapter->mbox_lock); 809 } 810 } 811 812 /* Must be used only in process context */ 813 static void be_cmd_unlock(struct be_adapter *adapter) 814 { 815 if (use_mcc(adapter)) 816 spin_unlock_bh(&adapter->mcc_lock); 817 else 818 return mutex_unlock(&adapter->mbox_lock); 819 } 820 821 static struct be_mcc_wrb *be_cmd_copy(struct be_adapter *adapter, 822 struct be_mcc_wrb *wrb) 823 { 824 struct be_mcc_wrb *dest_wrb; 825 826 if (use_mcc(adapter)) { 827 dest_wrb = wrb_from_mccq(adapter); 828 if (!dest_wrb) 829 return NULL; 830 } else { 831 dest_wrb = wrb_from_mbox(adapter); 832 } 833 834 memcpy(dest_wrb, wrb, sizeof(*wrb)); 835 if (wrb->embedded & cpu_to_le32(MCC_WRB_EMBEDDED_MASK)) 836 fill_wrb_tags(dest_wrb, (ulong) embedded_payload(wrb)); 837 838 return dest_wrb; 839 } 840 841 /* Must be used only in process context */ 842 static int be_cmd_notify_wait(struct be_adapter *adapter, 843 struct be_mcc_wrb *wrb) 844 { 845 struct be_mcc_wrb *dest_wrb; 846 int status; 847 848 status = be_cmd_lock(adapter); 849 if (status) 850 return status; 851 852 dest_wrb = be_cmd_copy(adapter, wrb); 853 if (!dest_wrb) { 854 status = -EBUSY; 855 goto unlock; 856 } 857 858 if (use_mcc(adapter)) 859 status = be_mcc_notify_wait(adapter); 860 else 861 status = be_mbox_notify_wait(adapter); 862 863 if (!status) 864 memcpy(wrb, dest_wrb, sizeof(*wrb)); 865 866 unlock: 867 be_cmd_unlock(adapter); 868 return status; 869 } 870 871 /* Tell fw we're about to start firing cmds by writing a 872 * special pattern across the wrb hdr; uses mbox 873 */ 874 int be_cmd_fw_init(struct be_adapter *adapter) 875 { 876 u8 *wrb; 877 int status; 878 879 if (lancer_chip(adapter)) 880 return 0; 881 882 if (mutex_lock_interruptible(&adapter->mbox_lock)) 883 return -1; 884 885 wrb = (u8 *)wrb_from_mbox(adapter); 886 *wrb++ = 0xFF; 887 *wrb++ = 0x12; 888 *wrb++ = 0x34; 889 *wrb++ = 0xFF; 890 *wrb++ = 0xFF; 891 *wrb++ = 0x56; 892 *wrb++ = 0x78; 893 *wrb = 0xFF; 894 895 status = be_mbox_notify_wait(adapter); 896 897 mutex_unlock(&adapter->mbox_lock); 898 return status; 899 } 900 901 /* Tell fw we're done with firing cmds by writing a 902 * special pattern across the wrb hdr; uses mbox 903 */ 904 int be_cmd_fw_clean(struct be_adapter *adapter) 905 { 906 u8 *wrb; 907 int status; 908 909 if (lancer_chip(adapter)) 910 return 0; 911 912 if (mutex_lock_interruptible(&adapter->mbox_lock)) 913 return -1; 914 915 wrb = (u8 *)wrb_from_mbox(adapter); 916 *wrb++ = 0xFF; 917 *wrb++ = 0xAA; 918 *wrb++ = 0xBB; 919 *wrb++ = 0xFF; 920 *wrb++ = 0xFF; 921 *wrb++ = 0xCC; 922 *wrb++ = 0xDD; 923 *wrb = 0xFF; 924 925 status = be_mbox_notify_wait(adapter); 926 927 mutex_unlock(&adapter->mbox_lock); 928 return status; 929 } 930 931 int be_cmd_eq_create(struct be_adapter *adapter, struct be_eq_obj *eqo) 932 { 933 struct be_mcc_wrb *wrb; 934 struct be_cmd_req_eq_create *req; 935 struct be_dma_mem *q_mem = &eqo->q.dma_mem; 936 int status, ver = 0; 937 938 if (mutex_lock_interruptible(&adapter->mbox_lock)) 939 return -1; 940 941 wrb = wrb_from_mbox(adapter); 942 req = embedded_payload(wrb); 943 944 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 945 OPCODE_COMMON_EQ_CREATE, sizeof(*req), wrb, 946 NULL); 947 948 /* Support for EQ_CREATEv2 available only SH-R onwards */ 949 if (!(BEx_chip(adapter) || lancer_chip(adapter))) 950 ver = 2; 951 952 req->hdr.version = ver; 953 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size)); 954 955 AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1); 956 /* 4byte eqe*/ 957 AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0); 958 AMAP_SET_BITS(struct amap_eq_context, count, req->context, 959 __ilog2_u32(eqo->q.len / 256)); 960 be_dws_cpu_to_le(req->context, sizeof(req->context)); 961 962 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); 963 964 status = be_mbox_notify_wait(adapter); 965 if (!status) { 966 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb); 967 968 eqo->q.id = le16_to_cpu(resp->eq_id); 969 eqo->msix_idx = 970 (ver == 2) ? le16_to_cpu(resp->msix_idx) : eqo->idx; 971 eqo->q.created = true; 972 } 973 974 mutex_unlock(&adapter->mbox_lock); 975 return status; 976 } 977 978 /* Use MCC */ 979 int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr, 980 bool permanent, u32 if_handle, u32 pmac_id) 981 { 982 struct be_mcc_wrb *wrb; 983 struct be_cmd_req_mac_query *req; 984 int status; 985 986 spin_lock_bh(&adapter->mcc_lock); 987 988 wrb = wrb_from_mccq(adapter); 989 if (!wrb) { 990 status = -EBUSY; 991 goto err; 992 } 993 req = embedded_payload(wrb); 994 995 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 996 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req), wrb, 997 NULL); 998 req->type = MAC_ADDRESS_TYPE_NETWORK; 999 if (permanent) { 1000 req->permanent = 1; 1001 } else { 1002 req->if_id = cpu_to_le16((u16)if_handle); 1003 req->pmac_id = cpu_to_le32(pmac_id); 1004 req->permanent = 0; 1005 } 1006 1007 status = be_mcc_notify_wait(adapter); 1008 if (!status) { 1009 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb); 1010 1011 memcpy(mac_addr, resp->mac.addr, ETH_ALEN); 1012 } 1013 1014 err: 1015 spin_unlock_bh(&adapter->mcc_lock); 1016 return status; 1017 } 1018 1019 /* Uses synchronous MCCQ */ 1020 int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr, 1021 u32 if_id, u32 *pmac_id, u32 domain) 1022 { 1023 struct be_mcc_wrb *wrb; 1024 struct be_cmd_req_pmac_add *req; 1025 int status; 1026 1027 spin_lock_bh(&adapter->mcc_lock); 1028 1029 wrb = wrb_from_mccq(adapter); 1030 if (!wrb) { 1031 status = -EBUSY; 1032 goto err; 1033 } 1034 req = embedded_payload(wrb); 1035 1036 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1037 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req), wrb, 1038 NULL); 1039 1040 req->hdr.domain = domain; 1041 req->if_id = cpu_to_le32(if_id); 1042 memcpy(req->mac_address, mac_addr, ETH_ALEN); 1043 1044 status = be_mcc_notify_wait(adapter); 1045 if (!status) { 1046 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb); 1047 1048 *pmac_id = le32_to_cpu(resp->pmac_id); 1049 } 1050 1051 err: 1052 spin_unlock_bh(&adapter->mcc_lock); 1053 1054 if (status == MCC_STATUS_UNAUTHORIZED_REQUEST) 1055 status = -EPERM; 1056 1057 return status; 1058 } 1059 1060 /* Uses synchronous MCCQ */ 1061 int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, int pmac_id, u32 dom) 1062 { 1063 struct be_mcc_wrb *wrb; 1064 struct be_cmd_req_pmac_del *req; 1065 int status; 1066 1067 if (pmac_id == -1) 1068 return 0; 1069 1070 spin_lock_bh(&adapter->mcc_lock); 1071 1072 wrb = wrb_from_mccq(adapter); 1073 if (!wrb) { 1074 status = -EBUSY; 1075 goto err; 1076 } 1077 req = embedded_payload(wrb); 1078 1079 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1080 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req), 1081 wrb, NULL); 1082 1083 req->hdr.domain = dom; 1084 req->if_id = cpu_to_le32(if_id); 1085 req->pmac_id = cpu_to_le32(pmac_id); 1086 1087 status = be_mcc_notify_wait(adapter); 1088 1089 err: 1090 spin_unlock_bh(&adapter->mcc_lock); 1091 return status; 1092 } 1093 1094 /* Uses Mbox */ 1095 int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq, 1096 struct be_queue_info *eq, bool no_delay, int coalesce_wm) 1097 { 1098 struct be_mcc_wrb *wrb; 1099 struct be_cmd_req_cq_create *req; 1100 struct be_dma_mem *q_mem = &cq->dma_mem; 1101 void *ctxt; 1102 int status; 1103 1104 if (mutex_lock_interruptible(&adapter->mbox_lock)) 1105 return -1; 1106 1107 wrb = wrb_from_mbox(adapter); 1108 req = embedded_payload(wrb); 1109 ctxt = &req->context; 1110 1111 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1112 OPCODE_COMMON_CQ_CREATE, sizeof(*req), wrb, 1113 NULL); 1114 1115 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size)); 1116 1117 if (BEx_chip(adapter)) { 1118 AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt, 1119 coalesce_wm); 1120 AMAP_SET_BITS(struct amap_cq_context_be, nodelay, 1121 ctxt, no_delay); 1122 AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt, 1123 __ilog2_u32(cq->len / 256)); 1124 AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1); 1125 AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1); 1126 AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id); 1127 } else { 1128 req->hdr.version = 2; 1129 req->page_size = 1; /* 1 for 4K */ 1130 1131 /* coalesce-wm field in this cmd is not relevant to Lancer. 1132 * Lancer uses COMMON_MODIFY_CQ to set this field 1133 */ 1134 if (!lancer_chip(adapter)) 1135 AMAP_SET_BITS(struct amap_cq_context_v2, coalescwm, 1136 ctxt, coalesce_wm); 1137 AMAP_SET_BITS(struct amap_cq_context_v2, nodelay, ctxt, 1138 no_delay); 1139 AMAP_SET_BITS(struct amap_cq_context_v2, count, ctxt, 1140 __ilog2_u32(cq->len / 256)); 1141 AMAP_SET_BITS(struct amap_cq_context_v2, valid, ctxt, 1); 1142 AMAP_SET_BITS(struct amap_cq_context_v2, eventable, ctxt, 1); 1143 AMAP_SET_BITS(struct amap_cq_context_v2, eqid, ctxt, eq->id); 1144 } 1145 1146 be_dws_cpu_to_le(ctxt, sizeof(req->context)); 1147 1148 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); 1149 1150 status = be_mbox_notify_wait(adapter); 1151 if (!status) { 1152 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb); 1153 1154 cq->id = le16_to_cpu(resp->cq_id); 1155 cq->created = true; 1156 } 1157 1158 mutex_unlock(&adapter->mbox_lock); 1159 1160 return status; 1161 } 1162 1163 static u32 be_encoded_q_len(int q_len) 1164 { 1165 u32 len_encoded = fls(q_len); /* log2(len) + 1 */ 1166 1167 if (len_encoded == 16) 1168 len_encoded = 0; 1169 return len_encoded; 1170 } 1171 1172 static int be_cmd_mccq_ext_create(struct be_adapter *adapter, 1173 struct be_queue_info *mccq, 1174 struct be_queue_info *cq) 1175 { 1176 struct be_mcc_wrb *wrb; 1177 struct be_cmd_req_mcc_ext_create *req; 1178 struct be_dma_mem *q_mem = &mccq->dma_mem; 1179 void *ctxt; 1180 int status; 1181 1182 if (mutex_lock_interruptible(&adapter->mbox_lock)) 1183 return -1; 1184 1185 wrb = wrb_from_mbox(adapter); 1186 req = embedded_payload(wrb); 1187 ctxt = &req->context; 1188 1189 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1190 OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req), wrb, 1191 NULL); 1192 1193 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size)); 1194 if (BEx_chip(adapter)) { 1195 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1); 1196 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt, 1197 be_encoded_q_len(mccq->len)); 1198 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id); 1199 } else { 1200 req->hdr.version = 1; 1201 req->cq_id = cpu_to_le16(cq->id); 1202 1203 AMAP_SET_BITS(struct amap_mcc_context_v1, ring_size, ctxt, 1204 be_encoded_q_len(mccq->len)); 1205 AMAP_SET_BITS(struct amap_mcc_context_v1, valid, ctxt, 1); 1206 AMAP_SET_BITS(struct amap_mcc_context_v1, async_cq_id, 1207 ctxt, cq->id); 1208 AMAP_SET_BITS(struct amap_mcc_context_v1, async_cq_valid, 1209 ctxt, 1); 1210 } 1211 1212 /* Subscribe to Link State, Sliport Event and Group 5 Events 1213 * (bits 1, 5 and 17 set) 1214 */ 1215 req->async_event_bitmap[0] = 1216 cpu_to_le32(BIT(ASYNC_EVENT_CODE_LINK_STATE) | 1217 BIT(ASYNC_EVENT_CODE_GRP_5) | 1218 BIT(ASYNC_EVENT_CODE_QNQ) | 1219 BIT(ASYNC_EVENT_CODE_SLIPORT)); 1220 1221 be_dws_cpu_to_le(ctxt, sizeof(req->context)); 1222 1223 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); 1224 1225 status = be_mbox_notify_wait(adapter); 1226 if (!status) { 1227 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb); 1228 1229 mccq->id = le16_to_cpu(resp->id); 1230 mccq->created = true; 1231 } 1232 mutex_unlock(&adapter->mbox_lock); 1233 1234 return status; 1235 } 1236 1237 static int be_cmd_mccq_org_create(struct be_adapter *adapter, 1238 struct be_queue_info *mccq, 1239 struct be_queue_info *cq) 1240 { 1241 struct be_mcc_wrb *wrb; 1242 struct be_cmd_req_mcc_create *req; 1243 struct be_dma_mem *q_mem = &mccq->dma_mem; 1244 void *ctxt; 1245 int status; 1246 1247 if (mutex_lock_interruptible(&adapter->mbox_lock)) 1248 return -1; 1249 1250 wrb = wrb_from_mbox(adapter); 1251 req = embedded_payload(wrb); 1252 ctxt = &req->context; 1253 1254 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1255 OPCODE_COMMON_MCC_CREATE, sizeof(*req), wrb, 1256 NULL); 1257 1258 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size)); 1259 1260 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1); 1261 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt, 1262 be_encoded_q_len(mccq->len)); 1263 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id); 1264 1265 be_dws_cpu_to_le(ctxt, sizeof(req->context)); 1266 1267 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); 1268 1269 status = be_mbox_notify_wait(adapter); 1270 if (!status) { 1271 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb); 1272 1273 mccq->id = le16_to_cpu(resp->id); 1274 mccq->created = true; 1275 } 1276 1277 mutex_unlock(&adapter->mbox_lock); 1278 return status; 1279 } 1280 1281 int be_cmd_mccq_create(struct be_adapter *adapter, 1282 struct be_queue_info *mccq, struct be_queue_info *cq) 1283 { 1284 int status; 1285 1286 status = be_cmd_mccq_ext_create(adapter, mccq, cq); 1287 if (status && BEx_chip(adapter)) { 1288 dev_warn(&adapter->pdev->dev, "Upgrade to F/W ver 2.102.235.0 " 1289 "or newer to avoid conflicting priorities between NIC " 1290 "and FCoE traffic"); 1291 status = be_cmd_mccq_org_create(adapter, mccq, cq); 1292 } 1293 return status; 1294 } 1295 1296 int be_cmd_txq_create(struct be_adapter *adapter, struct be_tx_obj *txo) 1297 { 1298 struct be_mcc_wrb wrb = {0}; 1299 struct be_cmd_req_eth_tx_create *req; 1300 struct be_queue_info *txq = &txo->q; 1301 struct be_queue_info *cq = &txo->cq; 1302 struct be_dma_mem *q_mem = &txq->dma_mem; 1303 int status, ver = 0; 1304 1305 req = embedded_payload(&wrb); 1306 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, 1307 OPCODE_ETH_TX_CREATE, sizeof(*req), &wrb, NULL); 1308 1309 if (lancer_chip(adapter)) { 1310 req->hdr.version = 1; 1311 } else if (BEx_chip(adapter)) { 1312 if (adapter->function_caps & BE_FUNCTION_CAPS_SUPER_NIC) 1313 req->hdr.version = 2; 1314 } else { /* For SH */ 1315 req->hdr.version = 2; 1316 } 1317 1318 if (req->hdr.version > 0) 1319 req->if_id = cpu_to_le16(adapter->if_handle); 1320 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size); 1321 req->ulp_num = BE_ULP1_NUM; 1322 req->type = BE_ETH_TX_RING_TYPE_STANDARD; 1323 req->cq_id = cpu_to_le16(cq->id); 1324 req->queue_size = be_encoded_q_len(txq->len); 1325 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); 1326 ver = req->hdr.version; 1327 1328 status = be_cmd_notify_wait(adapter, &wrb); 1329 if (!status) { 1330 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(&wrb); 1331 1332 txq->id = le16_to_cpu(resp->cid); 1333 if (ver == 2) 1334 txo->db_offset = le32_to_cpu(resp->db_offset); 1335 else 1336 txo->db_offset = DB_TXULP1_OFFSET; 1337 txq->created = true; 1338 } 1339 1340 return status; 1341 } 1342 1343 /* Uses MCC */ 1344 int be_cmd_rxq_create(struct be_adapter *adapter, 1345 struct be_queue_info *rxq, u16 cq_id, u16 frag_size, 1346 u32 if_id, u32 rss, u8 *rss_id) 1347 { 1348 struct be_mcc_wrb *wrb; 1349 struct be_cmd_req_eth_rx_create *req; 1350 struct be_dma_mem *q_mem = &rxq->dma_mem; 1351 int status; 1352 1353 spin_lock_bh(&adapter->mcc_lock); 1354 1355 wrb = wrb_from_mccq(adapter); 1356 if (!wrb) { 1357 status = -EBUSY; 1358 goto err; 1359 } 1360 req = embedded_payload(wrb); 1361 1362 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, 1363 OPCODE_ETH_RX_CREATE, sizeof(*req), wrb, NULL); 1364 1365 req->cq_id = cpu_to_le16(cq_id); 1366 req->frag_size = fls(frag_size) - 1; 1367 req->num_pages = 2; 1368 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); 1369 req->interface_id = cpu_to_le32(if_id); 1370 req->max_frame_size = cpu_to_le16(BE_MAX_JUMBO_FRAME_SIZE); 1371 req->rss_queue = cpu_to_le32(rss); 1372 1373 status = be_mcc_notify_wait(adapter); 1374 if (!status) { 1375 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb); 1376 1377 rxq->id = le16_to_cpu(resp->id); 1378 rxq->created = true; 1379 *rss_id = resp->rss_id; 1380 } 1381 1382 err: 1383 spin_unlock_bh(&adapter->mcc_lock); 1384 return status; 1385 } 1386 1387 /* Generic destroyer function for all types of queues 1388 * Uses Mbox 1389 */ 1390 int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q, 1391 int queue_type) 1392 { 1393 struct be_mcc_wrb *wrb; 1394 struct be_cmd_req_q_destroy *req; 1395 u8 subsys = 0, opcode = 0; 1396 int status; 1397 1398 if (mutex_lock_interruptible(&adapter->mbox_lock)) 1399 return -1; 1400 1401 wrb = wrb_from_mbox(adapter); 1402 req = embedded_payload(wrb); 1403 1404 switch (queue_type) { 1405 case QTYPE_EQ: 1406 subsys = CMD_SUBSYSTEM_COMMON; 1407 opcode = OPCODE_COMMON_EQ_DESTROY; 1408 break; 1409 case QTYPE_CQ: 1410 subsys = CMD_SUBSYSTEM_COMMON; 1411 opcode = OPCODE_COMMON_CQ_DESTROY; 1412 break; 1413 case QTYPE_TXQ: 1414 subsys = CMD_SUBSYSTEM_ETH; 1415 opcode = OPCODE_ETH_TX_DESTROY; 1416 break; 1417 case QTYPE_RXQ: 1418 subsys = CMD_SUBSYSTEM_ETH; 1419 opcode = OPCODE_ETH_RX_DESTROY; 1420 break; 1421 case QTYPE_MCCQ: 1422 subsys = CMD_SUBSYSTEM_COMMON; 1423 opcode = OPCODE_COMMON_MCC_DESTROY; 1424 break; 1425 default: 1426 BUG(); 1427 } 1428 1429 be_wrb_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req), wrb, 1430 NULL); 1431 req->id = cpu_to_le16(q->id); 1432 1433 status = be_mbox_notify_wait(adapter); 1434 q->created = false; 1435 1436 mutex_unlock(&adapter->mbox_lock); 1437 return status; 1438 } 1439 1440 /* Uses MCC */ 1441 int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q) 1442 { 1443 struct be_mcc_wrb *wrb; 1444 struct be_cmd_req_q_destroy *req; 1445 int status; 1446 1447 spin_lock_bh(&adapter->mcc_lock); 1448 1449 wrb = wrb_from_mccq(adapter); 1450 if (!wrb) { 1451 status = -EBUSY; 1452 goto err; 1453 } 1454 req = embedded_payload(wrb); 1455 1456 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, 1457 OPCODE_ETH_RX_DESTROY, sizeof(*req), wrb, NULL); 1458 req->id = cpu_to_le16(q->id); 1459 1460 status = be_mcc_notify_wait(adapter); 1461 q->created = false; 1462 1463 err: 1464 spin_unlock_bh(&adapter->mcc_lock); 1465 return status; 1466 } 1467 1468 /* Create an rx filtering policy configuration on an i/f 1469 * Will use MBOX only if MCCQ has not been created. 1470 */ 1471 int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags, 1472 u32 *if_handle, u32 domain) 1473 { 1474 struct be_mcc_wrb wrb = {0}; 1475 struct be_cmd_req_if_create *req; 1476 int status; 1477 1478 req = embedded_payload(&wrb); 1479 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1480 OPCODE_COMMON_NTWK_INTERFACE_CREATE, 1481 sizeof(*req), &wrb, NULL); 1482 req->hdr.domain = domain; 1483 req->capability_flags = cpu_to_le32(cap_flags); 1484 req->enable_flags = cpu_to_le32(en_flags); 1485 req->pmac_invalid = true; 1486 1487 status = be_cmd_notify_wait(adapter, &wrb); 1488 if (!status) { 1489 struct be_cmd_resp_if_create *resp = embedded_payload(&wrb); 1490 1491 *if_handle = le32_to_cpu(resp->interface_id); 1492 1493 /* Hack to retrieve VF's pmac-id on BE3 */ 1494 if (BE3_chip(adapter) && be_virtfn(adapter)) 1495 adapter->pmac_id[0] = le32_to_cpu(resp->pmac_id); 1496 } 1497 return status; 1498 } 1499 1500 /* Uses MCCQ */ 1501 int be_cmd_if_destroy(struct be_adapter *adapter, int interface_id, u32 domain) 1502 { 1503 struct be_mcc_wrb *wrb; 1504 struct be_cmd_req_if_destroy *req; 1505 int status; 1506 1507 if (interface_id == -1) 1508 return 0; 1509 1510 spin_lock_bh(&adapter->mcc_lock); 1511 1512 wrb = wrb_from_mccq(adapter); 1513 if (!wrb) { 1514 status = -EBUSY; 1515 goto err; 1516 } 1517 req = embedded_payload(wrb); 1518 1519 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1520 OPCODE_COMMON_NTWK_INTERFACE_DESTROY, 1521 sizeof(*req), wrb, NULL); 1522 req->hdr.domain = domain; 1523 req->interface_id = cpu_to_le32(interface_id); 1524 1525 status = be_mcc_notify_wait(adapter); 1526 err: 1527 spin_unlock_bh(&adapter->mcc_lock); 1528 return status; 1529 } 1530 1531 /* Get stats is a non embedded command: the request is not embedded inside 1532 * WRB but is a separate dma memory block 1533 * Uses asynchronous MCC 1534 */ 1535 int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd) 1536 { 1537 struct be_mcc_wrb *wrb; 1538 struct be_cmd_req_hdr *hdr; 1539 int status = 0; 1540 1541 spin_lock_bh(&adapter->mcc_lock); 1542 1543 wrb = wrb_from_mccq(adapter); 1544 if (!wrb) { 1545 status = -EBUSY; 1546 goto err; 1547 } 1548 hdr = nonemb_cmd->va; 1549 1550 be_wrb_cmd_hdr_prepare(hdr, CMD_SUBSYSTEM_ETH, 1551 OPCODE_ETH_GET_STATISTICS, nonemb_cmd->size, wrb, 1552 nonemb_cmd); 1553 1554 /* version 1 of the cmd is not supported only by BE2 */ 1555 if (BE2_chip(adapter)) 1556 hdr->version = 0; 1557 if (BE3_chip(adapter) || lancer_chip(adapter)) 1558 hdr->version = 1; 1559 else 1560 hdr->version = 2; 1561 1562 status = be_mcc_notify(adapter); 1563 if (status) 1564 goto err; 1565 1566 adapter->stats_cmd_sent = true; 1567 1568 err: 1569 spin_unlock_bh(&adapter->mcc_lock); 1570 return status; 1571 } 1572 1573 /* Lancer Stats */ 1574 int lancer_cmd_get_pport_stats(struct be_adapter *adapter, 1575 struct be_dma_mem *nonemb_cmd) 1576 { 1577 struct be_mcc_wrb *wrb; 1578 struct lancer_cmd_req_pport_stats *req; 1579 int status = 0; 1580 1581 if (!be_cmd_allowed(adapter, OPCODE_ETH_GET_PPORT_STATS, 1582 CMD_SUBSYSTEM_ETH)) 1583 return -EPERM; 1584 1585 spin_lock_bh(&adapter->mcc_lock); 1586 1587 wrb = wrb_from_mccq(adapter); 1588 if (!wrb) { 1589 status = -EBUSY; 1590 goto err; 1591 } 1592 req = nonemb_cmd->va; 1593 1594 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, 1595 OPCODE_ETH_GET_PPORT_STATS, nonemb_cmd->size, 1596 wrb, nonemb_cmd); 1597 1598 req->cmd_params.params.pport_num = cpu_to_le16(adapter->hba_port_num); 1599 req->cmd_params.params.reset_stats = 0; 1600 1601 status = be_mcc_notify(adapter); 1602 if (status) 1603 goto err; 1604 1605 adapter->stats_cmd_sent = true; 1606 1607 err: 1608 spin_unlock_bh(&adapter->mcc_lock); 1609 return status; 1610 } 1611 1612 static int be_mac_to_link_speed(int mac_speed) 1613 { 1614 switch (mac_speed) { 1615 case PHY_LINK_SPEED_ZERO: 1616 return 0; 1617 case PHY_LINK_SPEED_10MBPS: 1618 return 10; 1619 case PHY_LINK_SPEED_100MBPS: 1620 return 100; 1621 case PHY_LINK_SPEED_1GBPS: 1622 return 1000; 1623 case PHY_LINK_SPEED_10GBPS: 1624 return 10000; 1625 case PHY_LINK_SPEED_20GBPS: 1626 return 20000; 1627 case PHY_LINK_SPEED_25GBPS: 1628 return 25000; 1629 case PHY_LINK_SPEED_40GBPS: 1630 return 40000; 1631 } 1632 return 0; 1633 } 1634 1635 /* Uses synchronous mcc 1636 * Returns link_speed in Mbps 1637 */ 1638 int be_cmd_link_status_query(struct be_adapter *adapter, u16 *link_speed, 1639 u8 *link_status, u32 dom) 1640 { 1641 struct be_mcc_wrb *wrb; 1642 struct be_cmd_req_link_status *req; 1643 int status; 1644 1645 spin_lock_bh(&adapter->mcc_lock); 1646 1647 if (link_status) 1648 *link_status = LINK_DOWN; 1649 1650 wrb = wrb_from_mccq(adapter); 1651 if (!wrb) { 1652 status = -EBUSY; 1653 goto err; 1654 } 1655 req = embedded_payload(wrb); 1656 1657 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1658 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, 1659 sizeof(*req), wrb, NULL); 1660 1661 /* version 1 of the cmd is not supported only by BE2 */ 1662 if (!BE2_chip(adapter)) 1663 req->hdr.version = 1; 1664 1665 req->hdr.domain = dom; 1666 1667 status = be_mcc_notify_wait(adapter); 1668 if (!status) { 1669 struct be_cmd_resp_link_status *resp = embedded_payload(wrb); 1670 1671 if (link_speed) { 1672 *link_speed = resp->link_speed ? 1673 le16_to_cpu(resp->link_speed) * 10 : 1674 be_mac_to_link_speed(resp->mac_speed); 1675 1676 if (!resp->logical_link_status) 1677 *link_speed = 0; 1678 } 1679 if (link_status) 1680 *link_status = resp->logical_link_status; 1681 } 1682 1683 err: 1684 spin_unlock_bh(&adapter->mcc_lock); 1685 return status; 1686 } 1687 1688 /* Uses synchronous mcc */ 1689 int be_cmd_get_die_temperature(struct be_adapter *adapter) 1690 { 1691 struct be_mcc_wrb *wrb; 1692 struct be_cmd_req_get_cntl_addnl_attribs *req; 1693 int status = 0; 1694 1695 spin_lock_bh(&adapter->mcc_lock); 1696 1697 wrb = wrb_from_mccq(adapter); 1698 if (!wrb) { 1699 status = -EBUSY; 1700 goto err; 1701 } 1702 req = embedded_payload(wrb); 1703 1704 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1705 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES, 1706 sizeof(*req), wrb, NULL); 1707 1708 status = be_mcc_notify(adapter); 1709 err: 1710 spin_unlock_bh(&adapter->mcc_lock); 1711 return status; 1712 } 1713 1714 /* Uses synchronous mcc */ 1715 int be_cmd_get_fat_dump_len(struct be_adapter *adapter, u32 *dump_size) 1716 { 1717 struct be_mcc_wrb wrb = {0}; 1718 struct be_cmd_req_get_fat *req; 1719 int status; 1720 1721 req = embedded_payload(&wrb); 1722 1723 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1724 OPCODE_COMMON_MANAGE_FAT, sizeof(*req), 1725 &wrb, NULL); 1726 req->fat_operation = cpu_to_le32(QUERY_FAT); 1727 status = be_cmd_notify_wait(adapter, &wrb); 1728 if (!status) { 1729 struct be_cmd_resp_get_fat *resp = embedded_payload(&wrb); 1730 1731 if (dump_size && resp->log_size) 1732 *dump_size = le32_to_cpu(resp->log_size) - 1733 sizeof(u32); 1734 } 1735 return status; 1736 } 1737 1738 int be_cmd_get_fat_dump(struct be_adapter *adapter, u32 buf_len, void *buf) 1739 { 1740 struct be_dma_mem get_fat_cmd; 1741 struct be_mcc_wrb *wrb; 1742 struct be_cmd_req_get_fat *req; 1743 u32 offset = 0, total_size, buf_size, 1744 log_offset = sizeof(u32), payload_len; 1745 int status; 1746 1747 if (buf_len == 0) 1748 return 0; 1749 1750 total_size = buf_len; 1751 1752 get_fat_cmd.size = sizeof(struct be_cmd_req_get_fat) + 60*1024; 1753 get_fat_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, 1754 get_fat_cmd.size, 1755 &get_fat_cmd.dma, GFP_ATOMIC); 1756 if (!get_fat_cmd.va) 1757 return -ENOMEM; 1758 1759 spin_lock_bh(&adapter->mcc_lock); 1760 1761 while (total_size) { 1762 buf_size = min(total_size, (u32)60*1024); 1763 total_size -= buf_size; 1764 1765 wrb = wrb_from_mccq(adapter); 1766 if (!wrb) { 1767 status = -EBUSY; 1768 goto err; 1769 } 1770 req = get_fat_cmd.va; 1771 1772 payload_len = sizeof(struct be_cmd_req_get_fat) + buf_size; 1773 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1774 OPCODE_COMMON_MANAGE_FAT, payload_len, 1775 wrb, &get_fat_cmd); 1776 1777 req->fat_operation = cpu_to_le32(RETRIEVE_FAT); 1778 req->read_log_offset = cpu_to_le32(log_offset); 1779 req->read_log_length = cpu_to_le32(buf_size); 1780 req->data_buffer_size = cpu_to_le32(buf_size); 1781 1782 status = be_mcc_notify_wait(adapter); 1783 if (!status) { 1784 struct be_cmd_resp_get_fat *resp = get_fat_cmd.va; 1785 1786 memcpy(buf + offset, 1787 resp->data_buffer, 1788 le32_to_cpu(resp->read_log_length)); 1789 } else { 1790 dev_err(&adapter->pdev->dev, "FAT Table Retrieve error\n"); 1791 goto err; 1792 } 1793 offset += buf_size; 1794 log_offset += buf_size; 1795 } 1796 err: 1797 dma_free_coherent(&adapter->pdev->dev, get_fat_cmd.size, 1798 get_fat_cmd.va, get_fat_cmd.dma); 1799 spin_unlock_bh(&adapter->mcc_lock); 1800 return status; 1801 } 1802 1803 /* Uses synchronous mcc */ 1804 int be_cmd_get_fw_ver(struct be_adapter *adapter) 1805 { 1806 struct be_mcc_wrb *wrb; 1807 struct be_cmd_req_get_fw_version *req; 1808 int status; 1809 1810 spin_lock_bh(&adapter->mcc_lock); 1811 1812 wrb = wrb_from_mccq(adapter); 1813 if (!wrb) { 1814 status = -EBUSY; 1815 goto err; 1816 } 1817 1818 req = embedded_payload(wrb); 1819 1820 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1821 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req), wrb, 1822 NULL); 1823 status = be_mcc_notify_wait(adapter); 1824 if (!status) { 1825 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb); 1826 1827 strlcpy(adapter->fw_ver, resp->firmware_version_string, 1828 sizeof(adapter->fw_ver)); 1829 strlcpy(adapter->fw_on_flash, resp->fw_on_flash_version_string, 1830 sizeof(adapter->fw_on_flash)); 1831 } 1832 err: 1833 spin_unlock_bh(&adapter->mcc_lock); 1834 return status; 1835 } 1836 1837 /* set the EQ delay interval of an EQ to specified value 1838 * Uses async mcc 1839 */ 1840 static int __be_cmd_modify_eqd(struct be_adapter *adapter, 1841 struct be_set_eqd *set_eqd, int num) 1842 { 1843 struct be_mcc_wrb *wrb; 1844 struct be_cmd_req_modify_eq_delay *req; 1845 int status = 0, i; 1846 1847 spin_lock_bh(&adapter->mcc_lock); 1848 1849 wrb = wrb_from_mccq(adapter); 1850 if (!wrb) { 1851 status = -EBUSY; 1852 goto err; 1853 } 1854 req = embedded_payload(wrb); 1855 1856 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1857 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req), wrb, 1858 NULL); 1859 1860 req->num_eq = cpu_to_le32(num); 1861 for (i = 0; i < num; i++) { 1862 req->set_eqd[i].eq_id = cpu_to_le32(set_eqd[i].eq_id); 1863 req->set_eqd[i].phase = 0; 1864 req->set_eqd[i].delay_multiplier = 1865 cpu_to_le32(set_eqd[i].delay_multiplier); 1866 } 1867 1868 status = be_mcc_notify(adapter); 1869 err: 1870 spin_unlock_bh(&adapter->mcc_lock); 1871 return status; 1872 } 1873 1874 int be_cmd_modify_eqd(struct be_adapter *adapter, struct be_set_eqd *set_eqd, 1875 int num) 1876 { 1877 int num_eqs, i = 0; 1878 1879 while (num) { 1880 num_eqs = min(num, 8); 1881 __be_cmd_modify_eqd(adapter, &set_eqd[i], num_eqs); 1882 i += num_eqs; 1883 num -= num_eqs; 1884 } 1885 1886 return 0; 1887 } 1888 1889 /* Uses sycnhronous mcc */ 1890 int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array, 1891 u32 num, u32 domain) 1892 { 1893 struct be_mcc_wrb *wrb; 1894 struct be_cmd_req_vlan_config *req; 1895 int status; 1896 1897 spin_lock_bh(&adapter->mcc_lock); 1898 1899 wrb = wrb_from_mccq(adapter); 1900 if (!wrb) { 1901 status = -EBUSY; 1902 goto err; 1903 } 1904 req = embedded_payload(wrb); 1905 1906 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1907 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req), 1908 wrb, NULL); 1909 req->hdr.domain = domain; 1910 1911 req->interface_id = if_id; 1912 req->untagged = BE_IF_FLAGS_UNTAGGED & be_if_cap_flags(adapter) ? 1 : 0; 1913 req->num_vlan = num; 1914 memcpy(req->normal_vlan, vtag_array, 1915 req->num_vlan * sizeof(vtag_array[0])); 1916 1917 status = be_mcc_notify_wait(adapter); 1918 err: 1919 spin_unlock_bh(&adapter->mcc_lock); 1920 return status; 1921 } 1922 1923 static int __be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value) 1924 { 1925 struct be_mcc_wrb *wrb; 1926 struct be_dma_mem *mem = &adapter->rx_filter; 1927 struct be_cmd_req_rx_filter *req = mem->va; 1928 int status; 1929 1930 spin_lock_bh(&adapter->mcc_lock); 1931 1932 wrb = wrb_from_mccq(adapter); 1933 if (!wrb) { 1934 status = -EBUSY; 1935 goto err; 1936 } 1937 memset(req, 0, sizeof(*req)); 1938 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1939 OPCODE_COMMON_NTWK_RX_FILTER, sizeof(*req), 1940 wrb, mem); 1941 1942 req->if_id = cpu_to_le32(adapter->if_handle); 1943 req->if_flags_mask = cpu_to_le32(flags); 1944 req->if_flags = (value == ON) ? req->if_flags_mask : 0; 1945 1946 if (flags & BE_IF_FLAGS_MULTICAST) { 1947 struct netdev_hw_addr *ha; 1948 int i = 0; 1949 1950 /* Reset mcast promisc mode if already set by setting mask 1951 * and not setting flags field 1952 */ 1953 req->if_flags_mask |= 1954 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS & 1955 be_if_cap_flags(adapter)); 1956 req->mcast_num = cpu_to_le32(netdev_mc_count(adapter->netdev)); 1957 netdev_for_each_mc_addr(ha, adapter->netdev) 1958 memcpy(req->mcast_mac[i++].byte, ha->addr, ETH_ALEN); 1959 } 1960 1961 status = be_mcc_notify_wait(adapter); 1962 err: 1963 spin_unlock_bh(&adapter->mcc_lock); 1964 return status; 1965 } 1966 1967 int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value) 1968 { 1969 struct device *dev = &adapter->pdev->dev; 1970 1971 if ((flags & be_if_cap_flags(adapter)) != flags) { 1972 dev_warn(dev, "Cannot set rx filter flags 0x%x\n", flags); 1973 dev_warn(dev, "Interface is capable of 0x%x flags only\n", 1974 be_if_cap_flags(adapter)); 1975 } 1976 flags &= be_if_cap_flags(adapter); 1977 if (!flags) 1978 return -ENOTSUPP; 1979 1980 return __be_cmd_rx_filter(adapter, flags, value); 1981 } 1982 1983 /* Uses synchrounous mcc */ 1984 int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc) 1985 { 1986 struct be_mcc_wrb *wrb; 1987 struct be_cmd_req_set_flow_control *req; 1988 int status; 1989 1990 if (!be_cmd_allowed(adapter, OPCODE_COMMON_SET_FLOW_CONTROL, 1991 CMD_SUBSYSTEM_COMMON)) 1992 return -EPERM; 1993 1994 spin_lock_bh(&adapter->mcc_lock); 1995 1996 wrb = wrb_from_mccq(adapter); 1997 if (!wrb) { 1998 status = -EBUSY; 1999 goto err; 2000 } 2001 req = embedded_payload(wrb); 2002 2003 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2004 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req), 2005 wrb, NULL); 2006 2007 req->hdr.version = 1; 2008 req->tx_flow_control = cpu_to_le16((u16)tx_fc); 2009 req->rx_flow_control = cpu_to_le16((u16)rx_fc); 2010 2011 status = be_mcc_notify_wait(adapter); 2012 2013 err: 2014 spin_unlock_bh(&adapter->mcc_lock); 2015 2016 if (base_status(status) == MCC_STATUS_FEATURE_NOT_SUPPORTED) 2017 return -EOPNOTSUPP; 2018 2019 return status; 2020 } 2021 2022 /* Uses sycn mcc */ 2023 int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc) 2024 { 2025 struct be_mcc_wrb *wrb; 2026 struct be_cmd_req_get_flow_control *req; 2027 int status; 2028 2029 if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_FLOW_CONTROL, 2030 CMD_SUBSYSTEM_COMMON)) 2031 return -EPERM; 2032 2033 spin_lock_bh(&adapter->mcc_lock); 2034 2035 wrb = wrb_from_mccq(adapter); 2036 if (!wrb) { 2037 status = -EBUSY; 2038 goto err; 2039 } 2040 req = embedded_payload(wrb); 2041 2042 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2043 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req), 2044 wrb, NULL); 2045 2046 status = be_mcc_notify_wait(adapter); 2047 if (!status) { 2048 struct be_cmd_resp_get_flow_control *resp = 2049 embedded_payload(wrb); 2050 2051 *tx_fc = le16_to_cpu(resp->tx_flow_control); 2052 *rx_fc = le16_to_cpu(resp->rx_flow_control); 2053 } 2054 2055 err: 2056 spin_unlock_bh(&adapter->mcc_lock); 2057 return status; 2058 } 2059 2060 /* Uses mbox */ 2061 int be_cmd_query_fw_cfg(struct be_adapter *adapter) 2062 { 2063 struct be_mcc_wrb *wrb; 2064 struct be_cmd_req_query_fw_cfg *req; 2065 int status; 2066 2067 if (mutex_lock_interruptible(&adapter->mbox_lock)) 2068 return -1; 2069 2070 wrb = wrb_from_mbox(adapter); 2071 req = embedded_payload(wrb); 2072 2073 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2074 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, 2075 sizeof(*req), wrb, NULL); 2076 2077 status = be_mbox_notify_wait(adapter); 2078 if (!status) { 2079 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb); 2080 2081 adapter->port_num = le32_to_cpu(resp->phys_port); 2082 adapter->function_mode = le32_to_cpu(resp->function_mode); 2083 adapter->function_caps = le32_to_cpu(resp->function_caps); 2084 adapter->asic_rev = le32_to_cpu(resp->asic_revision) & 0xFF; 2085 dev_info(&adapter->pdev->dev, 2086 "FW config: function_mode=0x%x, function_caps=0x%x\n", 2087 adapter->function_mode, adapter->function_caps); 2088 } 2089 2090 mutex_unlock(&adapter->mbox_lock); 2091 return status; 2092 } 2093 2094 /* Uses mbox */ 2095 int be_cmd_reset_function(struct be_adapter *adapter) 2096 { 2097 struct be_mcc_wrb *wrb; 2098 struct be_cmd_req_hdr *req; 2099 int status; 2100 2101 if (lancer_chip(adapter)) { 2102 iowrite32(SLI_PORT_CONTROL_IP_MASK, 2103 adapter->db + SLIPORT_CONTROL_OFFSET); 2104 status = lancer_wait_ready(adapter); 2105 if (status) 2106 dev_err(&adapter->pdev->dev, 2107 "Adapter in non recoverable error\n"); 2108 return status; 2109 } 2110 2111 if (mutex_lock_interruptible(&adapter->mbox_lock)) 2112 return -1; 2113 2114 wrb = wrb_from_mbox(adapter); 2115 req = embedded_payload(wrb); 2116 2117 be_wrb_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON, 2118 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req), wrb, 2119 NULL); 2120 2121 status = be_mbox_notify_wait(adapter); 2122 2123 mutex_unlock(&adapter->mbox_lock); 2124 return status; 2125 } 2126 2127 int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable, 2128 u32 rss_hash_opts, u16 table_size, const u8 *rss_hkey) 2129 { 2130 struct be_mcc_wrb *wrb; 2131 struct be_cmd_req_rss_config *req; 2132 int status; 2133 2134 if (!(be_if_cap_flags(adapter) & BE_IF_FLAGS_RSS)) 2135 return 0; 2136 2137 spin_lock_bh(&adapter->mcc_lock); 2138 2139 wrb = wrb_from_mccq(adapter); 2140 if (!wrb) { 2141 status = -EBUSY; 2142 goto err; 2143 } 2144 req = embedded_payload(wrb); 2145 2146 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, 2147 OPCODE_ETH_RSS_CONFIG, sizeof(*req), wrb, NULL); 2148 2149 req->if_id = cpu_to_le32(adapter->if_handle); 2150 req->enable_rss = cpu_to_le16(rss_hash_opts); 2151 req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1); 2152 2153 if (!BEx_chip(adapter)) 2154 req->hdr.version = 1; 2155 2156 memcpy(req->cpu_table, rsstable, table_size); 2157 memcpy(req->hash, rss_hkey, RSS_HASH_KEY_LEN); 2158 be_dws_cpu_to_le(req->hash, sizeof(req->hash)); 2159 2160 status = be_mcc_notify_wait(adapter); 2161 err: 2162 spin_unlock_bh(&adapter->mcc_lock); 2163 return status; 2164 } 2165 2166 /* Uses sync mcc */ 2167 int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num, 2168 u8 bcn, u8 sts, u8 state) 2169 { 2170 struct be_mcc_wrb *wrb; 2171 struct be_cmd_req_enable_disable_beacon *req; 2172 int status; 2173 2174 spin_lock_bh(&adapter->mcc_lock); 2175 2176 wrb = wrb_from_mccq(adapter); 2177 if (!wrb) { 2178 status = -EBUSY; 2179 goto err; 2180 } 2181 req = embedded_payload(wrb); 2182 2183 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2184 OPCODE_COMMON_ENABLE_DISABLE_BEACON, 2185 sizeof(*req), wrb, NULL); 2186 2187 req->port_num = port_num; 2188 req->beacon_state = state; 2189 req->beacon_duration = bcn; 2190 req->status_duration = sts; 2191 2192 status = be_mcc_notify_wait(adapter); 2193 2194 err: 2195 spin_unlock_bh(&adapter->mcc_lock); 2196 return status; 2197 } 2198 2199 /* Uses sync mcc */ 2200 int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state) 2201 { 2202 struct be_mcc_wrb *wrb; 2203 struct be_cmd_req_get_beacon_state *req; 2204 int status; 2205 2206 spin_lock_bh(&adapter->mcc_lock); 2207 2208 wrb = wrb_from_mccq(adapter); 2209 if (!wrb) { 2210 status = -EBUSY; 2211 goto err; 2212 } 2213 req = embedded_payload(wrb); 2214 2215 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2216 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req), 2217 wrb, NULL); 2218 2219 req->port_num = port_num; 2220 2221 status = be_mcc_notify_wait(adapter); 2222 if (!status) { 2223 struct be_cmd_resp_get_beacon_state *resp = 2224 embedded_payload(wrb); 2225 2226 *state = resp->beacon_state; 2227 } 2228 2229 err: 2230 spin_unlock_bh(&adapter->mcc_lock); 2231 return status; 2232 } 2233 2234 /* Uses sync mcc */ 2235 int be_cmd_read_port_transceiver_data(struct be_adapter *adapter, 2236 u8 page_num, u8 *data) 2237 { 2238 struct be_dma_mem cmd; 2239 struct be_mcc_wrb *wrb; 2240 struct be_cmd_req_port_type *req; 2241 int status; 2242 2243 if (page_num > TR_PAGE_A2) 2244 return -EINVAL; 2245 2246 cmd.size = sizeof(struct be_cmd_resp_port_type); 2247 cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma, 2248 GFP_ATOMIC); 2249 if (!cmd.va) { 2250 dev_err(&adapter->pdev->dev, "Memory allocation failed\n"); 2251 return -ENOMEM; 2252 } 2253 2254 spin_lock_bh(&adapter->mcc_lock); 2255 2256 wrb = wrb_from_mccq(adapter); 2257 if (!wrb) { 2258 status = -EBUSY; 2259 goto err; 2260 } 2261 req = cmd.va; 2262 2263 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2264 OPCODE_COMMON_READ_TRANSRECV_DATA, 2265 cmd.size, wrb, &cmd); 2266 2267 req->port = cpu_to_le32(adapter->hba_port_num); 2268 req->page_num = cpu_to_le32(page_num); 2269 status = be_mcc_notify_wait(adapter); 2270 if (!status) { 2271 struct be_cmd_resp_port_type *resp = cmd.va; 2272 2273 memcpy(data, resp->page_data, PAGE_DATA_LEN); 2274 } 2275 err: 2276 spin_unlock_bh(&adapter->mcc_lock); 2277 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, cmd.dma); 2278 return status; 2279 } 2280 2281 static int lancer_cmd_write_object(struct be_adapter *adapter, 2282 struct be_dma_mem *cmd, u32 data_size, 2283 u32 data_offset, const char *obj_name, 2284 u32 *data_written, u8 *change_status, 2285 u8 *addn_status) 2286 { 2287 struct be_mcc_wrb *wrb; 2288 struct lancer_cmd_req_write_object *req; 2289 struct lancer_cmd_resp_write_object *resp; 2290 void *ctxt = NULL; 2291 int status; 2292 2293 spin_lock_bh(&adapter->mcc_lock); 2294 adapter->flash_status = 0; 2295 2296 wrb = wrb_from_mccq(adapter); 2297 if (!wrb) { 2298 status = -EBUSY; 2299 goto err_unlock; 2300 } 2301 2302 req = embedded_payload(wrb); 2303 2304 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2305 OPCODE_COMMON_WRITE_OBJECT, 2306 sizeof(struct lancer_cmd_req_write_object), wrb, 2307 NULL); 2308 2309 ctxt = &req->context; 2310 AMAP_SET_BITS(struct amap_lancer_write_obj_context, 2311 write_length, ctxt, data_size); 2312 2313 if (data_size == 0) 2314 AMAP_SET_BITS(struct amap_lancer_write_obj_context, 2315 eof, ctxt, 1); 2316 else 2317 AMAP_SET_BITS(struct amap_lancer_write_obj_context, 2318 eof, ctxt, 0); 2319 2320 be_dws_cpu_to_le(ctxt, sizeof(req->context)); 2321 req->write_offset = cpu_to_le32(data_offset); 2322 strlcpy(req->object_name, obj_name, sizeof(req->object_name)); 2323 req->descriptor_count = cpu_to_le32(1); 2324 req->buf_len = cpu_to_le32(data_size); 2325 req->addr_low = cpu_to_le32((cmd->dma + 2326 sizeof(struct lancer_cmd_req_write_object)) 2327 & 0xFFFFFFFF); 2328 req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma + 2329 sizeof(struct lancer_cmd_req_write_object))); 2330 2331 status = be_mcc_notify(adapter); 2332 if (status) 2333 goto err_unlock; 2334 2335 spin_unlock_bh(&adapter->mcc_lock); 2336 2337 if (!wait_for_completion_timeout(&adapter->et_cmd_compl, 2338 msecs_to_jiffies(60000))) 2339 status = -ETIMEDOUT; 2340 else 2341 status = adapter->flash_status; 2342 2343 resp = embedded_payload(wrb); 2344 if (!status) { 2345 *data_written = le32_to_cpu(resp->actual_write_len); 2346 *change_status = resp->change_status; 2347 } else { 2348 *addn_status = resp->additional_status; 2349 } 2350 2351 return status; 2352 2353 err_unlock: 2354 spin_unlock_bh(&adapter->mcc_lock); 2355 return status; 2356 } 2357 2358 int be_cmd_query_cable_type(struct be_adapter *adapter) 2359 { 2360 u8 page_data[PAGE_DATA_LEN]; 2361 int status; 2362 2363 status = be_cmd_read_port_transceiver_data(adapter, TR_PAGE_A0, 2364 page_data); 2365 if (!status) { 2366 switch (adapter->phy.interface_type) { 2367 case PHY_TYPE_QSFP: 2368 adapter->phy.cable_type = 2369 page_data[QSFP_PLUS_CABLE_TYPE_OFFSET]; 2370 break; 2371 case PHY_TYPE_SFP_PLUS_10GB: 2372 adapter->phy.cable_type = 2373 page_data[SFP_PLUS_CABLE_TYPE_OFFSET]; 2374 break; 2375 default: 2376 adapter->phy.cable_type = 0; 2377 break; 2378 } 2379 } 2380 return status; 2381 } 2382 2383 int be_cmd_query_sfp_info(struct be_adapter *adapter) 2384 { 2385 u8 page_data[PAGE_DATA_LEN]; 2386 int status; 2387 2388 status = be_cmd_read_port_transceiver_data(adapter, TR_PAGE_A0, 2389 page_data); 2390 if (!status) { 2391 strlcpy(adapter->phy.vendor_name, page_data + 2392 SFP_VENDOR_NAME_OFFSET, SFP_VENDOR_NAME_LEN - 1); 2393 strlcpy(adapter->phy.vendor_pn, 2394 page_data + SFP_VENDOR_PN_OFFSET, 2395 SFP_VENDOR_NAME_LEN - 1); 2396 } 2397 2398 return status; 2399 } 2400 2401 static int lancer_cmd_delete_object(struct be_adapter *adapter, 2402 const char *obj_name) 2403 { 2404 struct lancer_cmd_req_delete_object *req; 2405 struct be_mcc_wrb *wrb; 2406 int status; 2407 2408 spin_lock_bh(&adapter->mcc_lock); 2409 2410 wrb = wrb_from_mccq(adapter); 2411 if (!wrb) { 2412 status = -EBUSY; 2413 goto err; 2414 } 2415 2416 req = embedded_payload(wrb); 2417 2418 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2419 OPCODE_COMMON_DELETE_OBJECT, 2420 sizeof(*req), wrb, NULL); 2421 2422 strlcpy(req->object_name, obj_name, sizeof(req->object_name)); 2423 2424 status = be_mcc_notify_wait(adapter); 2425 err: 2426 spin_unlock_bh(&adapter->mcc_lock); 2427 return status; 2428 } 2429 2430 int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd, 2431 u32 data_size, u32 data_offset, const char *obj_name, 2432 u32 *data_read, u32 *eof, u8 *addn_status) 2433 { 2434 struct be_mcc_wrb *wrb; 2435 struct lancer_cmd_req_read_object *req; 2436 struct lancer_cmd_resp_read_object *resp; 2437 int status; 2438 2439 spin_lock_bh(&adapter->mcc_lock); 2440 2441 wrb = wrb_from_mccq(adapter); 2442 if (!wrb) { 2443 status = -EBUSY; 2444 goto err_unlock; 2445 } 2446 2447 req = embedded_payload(wrb); 2448 2449 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2450 OPCODE_COMMON_READ_OBJECT, 2451 sizeof(struct lancer_cmd_req_read_object), wrb, 2452 NULL); 2453 2454 req->desired_read_len = cpu_to_le32(data_size); 2455 req->read_offset = cpu_to_le32(data_offset); 2456 strcpy(req->object_name, obj_name); 2457 req->descriptor_count = cpu_to_le32(1); 2458 req->buf_len = cpu_to_le32(data_size); 2459 req->addr_low = cpu_to_le32((cmd->dma & 0xFFFFFFFF)); 2460 req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma)); 2461 2462 status = be_mcc_notify_wait(adapter); 2463 2464 resp = embedded_payload(wrb); 2465 if (!status) { 2466 *data_read = le32_to_cpu(resp->actual_read_len); 2467 *eof = le32_to_cpu(resp->eof); 2468 } else { 2469 *addn_status = resp->additional_status; 2470 } 2471 2472 err_unlock: 2473 spin_unlock_bh(&adapter->mcc_lock); 2474 return status; 2475 } 2476 2477 static int be_cmd_write_flashrom(struct be_adapter *adapter, 2478 struct be_dma_mem *cmd, u32 flash_type, 2479 u32 flash_opcode, u32 img_offset, u32 buf_size) 2480 { 2481 struct be_mcc_wrb *wrb; 2482 struct be_cmd_write_flashrom *req; 2483 int status; 2484 2485 spin_lock_bh(&adapter->mcc_lock); 2486 adapter->flash_status = 0; 2487 2488 wrb = wrb_from_mccq(adapter); 2489 if (!wrb) { 2490 status = -EBUSY; 2491 goto err_unlock; 2492 } 2493 req = cmd->va; 2494 2495 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2496 OPCODE_COMMON_WRITE_FLASHROM, cmd->size, wrb, 2497 cmd); 2498 2499 req->params.op_type = cpu_to_le32(flash_type); 2500 if (flash_type == OPTYPE_OFFSET_SPECIFIED) 2501 req->params.offset = cpu_to_le32(img_offset); 2502 2503 req->params.op_code = cpu_to_le32(flash_opcode); 2504 req->params.data_buf_size = cpu_to_le32(buf_size); 2505 2506 status = be_mcc_notify(adapter); 2507 if (status) 2508 goto err_unlock; 2509 2510 spin_unlock_bh(&adapter->mcc_lock); 2511 2512 if (!wait_for_completion_timeout(&adapter->et_cmd_compl, 2513 msecs_to_jiffies(40000))) 2514 status = -ETIMEDOUT; 2515 else 2516 status = adapter->flash_status; 2517 2518 return status; 2519 2520 err_unlock: 2521 spin_unlock_bh(&adapter->mcc_lock); 2522 return status; 2523 } 2524 2525 static int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc, 2526 u16 img_optype, u32 img_offset, u32 crc_offset) 2527 { 2528 struct be_cmd_read_flash_crc *req; 2529 struct be_mcc_wrb *wrb; 2530 int status; 2531 2532 spin_lock_bh(&adapter->mcc_lock); 2533 2534 wrb = wrb_from_mccq(adapter); 2535 if (!wrb) { 2536 status = -EBUSY; 2537 goto err; 2538 } 2539 req = embedded_payload(wrb); 2540 2541 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2542 OPCODE_COMMON_READ_FLASHROM, sizeof(*req), 2543 wrb, NULL); 2544 2545 req->params.op_type = cpu_to_le32(img_optype); 2546 if (img_optype == OPTYPE_OFFSET_SPECIFIED) 2547 req->params.offset = cpu_to_le32(img_offset + crc_offset); 2548 else 2549 req->params.offset = cpu_to_le32(crc_offset); 2550 2551 req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT); 2552 req->params.data_buf_size = cpu_to_le32(0x4); 2553 2554 status = be_mcc_notify_wait(adapter); 2555 if (!status) 2556 memcpy(flashed_crc, req->crc, 4); 2557 2558 err: 2559 spin_unlock_bh(&adapter->mcc_lock); 2560 return status; 2561 } 2562 2563 static char flash_cookie[2][16] = {"*** SE FLAS", "H DIRECTORY *** "}; 2564 2565 static bool phy_flashing_required(struct be_adapter *adapter) 2566 { 2567 return (adapter->phy.phy_type == PHY_TYPE_TN_8022 && 2568 adapter->phy.interface_type == PHY_TYPE_BASET_10GB); 2569 } 2570 2571 static bool is_comp_in_ufi(struct be_adapter *adapter, 2572 struct flash_section_info *fsec, int type) 2573 { 2574 int i = 0, img_type = 0; 2575 struct flash_section_info_g2 *fsec_g2 = NULL; 2576 2577 if (BE2_chip(adapter)) 2578 fsec_g2 = (struct flash_section_info_g2 *)fsec; 2579 2580 for (i = 0; i < MAX_FLASH_COMP; i++) { 2581 if (fsec_g2) 2582 img_type = le32_to_cpu(fsec_g2->fsec_entry[i].type); 2583 else 2584 img_type = le32_to_cpu(fsec->fsec_entry[i].type); 2585 2586 if (img_type == type) 2587 return true; 2588 } 2589 return false; 2590 } 2591 2592 static struct flash_section_info *get_fsec_info(struct be_adapter *adapter, 2593 int header_size, 2594 const struct firmware *fw) 2595 { 2596 struct flash_section_info *fsec = NULL; 2597 const u8 *p = fw->data; 2598 2599 p += header_size; 2600 while (p < (fw->data + fw->size)) { 2601 fsec = (struct flash_section_info *)p; 2602 if (!memcmp(flash_cookie, fsec->cookie, sizeof(flash_cookie))) 2603 return fsec; 2604 p += 32; 2605 } 2606 return NULL; 2607 } 2608 2609 static int be_check_flash_crc(struct be_adapter *adapter, const u8 *p, 2610 u32 img_offset, u32 img_size, int hdr_size, 2611 u16 img_optype, bool *crc_match) 2612 { 2613 u32 crc_offset; 2614 int status; 2615 u8 crc[4]; 2616 2617 status = be_cmd_get_flash_crc(adapter, crc, img_optype, img_offset, 2618 img_size - 4); 2619 if (status) 2620 return status; 2621 2622 crc_offset = hdr_size + img_offset + img_size - 4; 2623 2624 /* Skip flashing, if crc of flashed region matches */ 2625 if (!memcmp(crc, p + crc_offset, 4)) 2626 *crc_match = true; 2627 else 2628 *crc_match = false; 2629 2630 return status; 2631 } 2632 2633 static int be_flash(struct be_adapter *adapter, const u8 *img, 2634 struct be_dma_mem *flash_cmd, int optype, int img_size, 2635 u32 img_offset) 2636 { 2637 u32 flash_op, num_bytes, total_bytes = img_size, bytes_sent = 0; 2638 struct be_cmd_write_flashrom *req = flash_cmd->va; 2639 int status; 2640 2641 while (total_bytes) { 2642 num_bytes = min_t(u32, 32 * 1024, total_bytes); 2643 2644 total_bytes -= num_bytes; 2645 2646 if (!total_bytes) { 2647 if (optype == OPTYPE_PHY_FW) 2648 flash_op = FLASHROM_OPER_PHY_FLASH; 2649 else 2650 flash_op = FLASHROM_OPER_FLASH; 2651 } else { 2652 if (optype == OPTYPE_PHY_FW) 2653 flash_op = FLASHROM_OPER_PHY_SAVE; 2654 else 2655 flash_op = FLASHROM_OPER_SAVE; 2656 } 2657 2658 memcpy(req->data_buf, img, num_bytes); 2659 img += num_bytes; 2660 status = be_cmd_write_flashrom(adapter, flash_cmd, optype, 2661 flash_op, img_offset + 2662 bytes_sent, num_bytes); 2663 if (base_status(status) == MCC_STATUS_ILLEGAL_REQUEST && 2664 optype == OPTYPE_PHY_FW) 2665 break; 2666 else if (status) 2667 return status; 2668 2669 bytes_sent += num_bytes; 2670 } 2671 return 0; 2672 } 2673 2674 /* For BE2, BE3 and BE3-R */ 2675 static int be_flash_BEx(struct be_adapter *adapter, 2676 const struct firmware *fw, 2677 struct be_dma_mem *flash_cmd, int num_of_images) 2678 { 2679 int img_hdrs_size = (num_of_images * sizeof(struct image_hdr)); 2680 struct device *dev = &adapter->pdev->dev; 2681 struct flash_section_info *fsec = NULL; 2682 int status, i, filehdr_size, num_comp; 2683 const struct flash_comp *pflashcomp; 2684 bool crc_match; 2685 const u8 *p; 2686 2687 struct flash_comp gen3_flash_types[] = { 2688 { BE3_ISCSI_PRIMARY_IMAGE_START, OPTYPE_ISCSI_ACTIVE, 2689 BE3_COMP_MAX_SIZE, IMAGE_FIRMWARE_ISCSI}, 2690 { BE3_REDBOOT_START, OPTYPE_REDBOOT, 2691 BE3_REDBOOT_COMP_MAX_SIZE, IMAGE_BOOT_CODE}, 2692 { BE3_ISCSI_BIOS_START, OPTYPE_BIOS, 2693 BE3_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_ISCSI}, 2694 { BE3_PXE_BIOS_START, OPTYPE_PXE_BIOS, 2695 BE3_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_PXE}, 2696 { BE3_FCOE_BIOS_START, OPTYPE_FCOE_BIOS, 2697 BE3_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_FCOE}, 2698 { BE3_ISCSI_BACKUP_IMAGE_START, OPTYPE_ISCSI_BACKUP, 2699 BE3_COMP_MAX_SIZE, IMAGE_FIRMWARE_BACKUP_ISCSI}, 2700 { BE3_FCOE_PRIMARY_IMAGE_START, OPTYPE_FCOE_FW_ACTIVE, 2701 BE3_COMP_MAX_SIZE, IMAGE_FIRMWARE_FCOE}, 2702 { BE3_FCOE_BACKUP_IMAGE_START, OPTYPE_FCOE_FW_BACKUP, 2703 BE3_COMP_MAX_SIZE, IMAGE_FIRMWARE_BACKUP_FCOE}, 2704 { BE3_NCSI_START, OPTYPE_NCSI_FW, 2705 BE3_NCSI_COMP_MAX_SIZE, IMAGE_NCSI}, 2706 { BE3_PHY_FW_START, OPTYPE_PHY_FW, 2707 BE3_PHY_FW_COMP_MAX_SIZE, IMAGE_FIRMWARE_PHY} 2708 }; 2709 2710 struct flash_comp gen2_flash_types[] = { 2711 { BE2_ISCSI_PRIMARY_IMAGE_START, OPTYPE_ISCSI_ACTIVE, 2712 BE2_COMP_MAX_SIZE, IMAGE_FIRMWARE_ISCSI}, 2713 { BE2_REDBOOT_START, OPTYPE_REDBOOT, 2714 BE2_REDBOOT_COMP_MAX_SIZE, IMAGE_BOOT_CODE}, 2715 { BE2_ISCSI_BIOS_START, OPTYPE_BIOS, 2716 BE2_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_ISCSI}, 2717 { BE2_PXE_BIOS_START, OPTYPE_PXE_BIOS, 2718 BE2_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_PXE}, 2719 { BE2_FCOE_BIOS_START, OPTYPE_FCOE_BIOS, 2720 BE2_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_FCOE}, 2721 { BE2_ISCSI_BACKUP_IMAGE_START, OPTYPE_ISCSI_BACKUP, 2722 BE2_COMP_MAX_SIZE, IMAGE_FIRMWARE_BACKUP_ISCSI}, 2723 { BE2_FCOE_PRIMARY_IMAGE_START, OPTYPE_FCOE_FW_ACTIVE, 2724 BE2_COMP_MAX_SIZE, IMAGE_FIRMWARE_FCOE}, 2725 { BE2_FCOE_BACKUP_IMAGE_START, OPTYPE_FCOE_FW_BACKUP, 2726 BE2_COMP_MAX_SIZE, IMAGE_FIRMWARE_BACKUP_FCOE} 2727 }; 2728 2729 if (BE3_chip(adapter)) { 2730 pflashcomp = gen3_flash_types; 2731 filehdr_size = sizeof(struct flash_file_hdr_g3); 2732 num_comp = ARRAY_SIZE(gen3_flash_types); 2733 } else { 2734 pflashcomp = gen2_flash_types; 2735 filehdr_size = sizeof(struct flash_file_hdr_g2); 2736 num_comp = ARRAY_SIZE(gen2_flash_types); 2737 img_hdrs_size = 0; 2738 } 2739 2740 /* Get flash section info*/ 2741 fsec = get_fsec_info(adapter, filehdr_size + img_hdrs_size, fw); 2742 if (!fsec) { 2743 dev_err(dev, "Invalid Cookie. FW image may be corrupted\n"); 2744 return -1; 2745 } 2746 for (i = 0; i < num_comp; i++) { 2747 if (!is_comp_in_ufi(adapter, fsec, pflashcomp[i].img_type)) 2748 continue; 2749 2750 if ((pflashcomp[i].optype == OPTYPE_NCSI_FW) && 2751 memcmp(adapter->fw_ver, "3.102.148.0", 11) < 0) 2752 continue; 2753 2754 if (pflashcomp[i].optype == OPTYPE_PHY_FW && 2755 !phy_flashing_required(adapter)) 2756 continue; 2757 2758 if (pflashcomp[i].optype == OPTYPE_REDBOOT) { 2759 status = be_check_flash_crc(adapter, fw->data, 2760 pflashcomp[i].offset, 2761 pflashcomp[i].size, 2762 filehdr_size + 2763 img_hdrs_size, 2764 OPTYPE_REDBOOT, &crc_match); 2765 if (status) { 2766 dev_err(dev, 2767 "Could not get CRC for 0x%x region\n", 2768 pflashcomp[i].optype); 2769 continue; 2770 } 2771 2772 if (crc_match) 2773 continue; 2774 } 2775 2776 p = fw->data + filehdr_size + pflashcomp[i].offset + 2777 img_hdrs_size; 2778 if (p + pflashcomp[i].size > fw->data + fw->size) 2779 return -1; 2780 2781 status = be_flash(adapter, p, flash_cmd, pflashcomp[i].optype, 2782 pflashcomp[i].size, 0); 2783 if (status) { 2784 dev_err(dev, "Flashing section type 0x%x failed\n", 2785 pflashcomp[i].img_type); 2786 return status; 2787 } 2788 } 2789 return 0; 2790 } 2791 2792 static u16 be_get_img_optype(struct flash_section_entry fsec_entry) 2793 { 2794 u32 img_type = le32_to_cpu(fsec_entry.type); 2795 u16 img_optype = le16_to_cpu(fsec_entry.optype); 2796 2797 if (img_optype != 0xFFFF) 2798 return img_optype; 2799 2800 switch (img_type) { 2801 case IMAGE_FIRMWARE_ISCSI: 2802 img_optype = OPTYPE_ISCSI_ACTIVE; 2803 break; 2804 case IMAGE_BOOT_CODE: 2805 img_optype = OPTYPE_REDBOOT; 2806 break; 2807 case IMAGE_OPTION_ROM_ISCSI: 2808 img_optype = OPTYPE_BIOS; 2809 break; 2810 case IMAGE_OPTION_ROM_PXE: 2811 img_optype = OPTYPE_PXE_BIOS; 2812 break; 2813 case IMAGE_OPTION_ROM_FCOE: 2814 img_optype = OPTYPE_FCOE_BIOS; 2815 break; 2816 case IMAGE_FIRMWARE_BACKUP_ISCSI: 2817 img_optype = OPTYPE_ISCSI_BACKUP; 2818 break; 2819 case IMAGE_NCSI: 2820 img_optype = OPTYPE_NCSI_FW; 2821 break; 2822 case IMAGE_FLASHISM_JUMPVECTOR: 2823 img_optype = OPTYPE_FLASHISM_JUMPVECTOR; 2824 break; 2825 case IMAGE_FIRMWARE_PHY: 2826 img_optype = OPTYPE_SH_PHY_FW; 2827 break; 2828 case IMAGE_REDBOOT_DIR: 2829 img_optype = OPTYPE_REDBOOT_DIR; 2830 break; 2831 case IMAGE_REDBOOT_CONFIG: 2832 img_optype = OPTYPE_REDBOOT_CONFIG; 2833 break; 2834 case IMAGE_UFI_DIR: 2835 img_optype = OPTYPE_UFI_DIR; 2836 break; 2837 default: 2838 break; 2839 } 2840 2841 return img_optype; 2842 } 2843 2844 static int be_flash_skyhawk(struct be_adapter *adapter, 2845 const struct firmware *fw, 2846 struct be_dma_mem *flash_cmd, int num_of_images) 2847 { 2848 int img_hdrs_size = num_of_images * sizeof(struct image_hdr); 2849 bool crc_match, old_fw_img, flash_offset_support = true; 2850 struct device *dev = &adapter->pdev->dev; 2851 struct flash_section_info *fsec = NULL; 2852 u32 img_offset, img_size, img_type; 2853 u16 img_optype, flash_optype; 2854 int status, i, filehdr_size; 2855 const u8 *p; 2856 2857 filehdr_size = sizeof(struct flash_file_hdr_g3); 2858 fsec = get_fsec_info(adapter, filehdr_size + img_hdrs_size, fw); 2859 if (!fsec) { 2860 dev_err(dev, "Invalid Cookie. FW image may be corrupted\n"); 2861 return -EINVAL; 2862 } 2863 2864 retry_flash: 2865 for (i = 0; i < le32_to_cpu(fsec->fsec_hdr.num_images); i++) { 2866 img_offset = le32_to_cpu(fsec->fsec_entry[i].offset); 2867 img_size = le32_to_cpu(fsec->fsec_entry[i].pad_size); 2868 img_type = le32_to_cpu(fsec->fsec_entry[i].type); 2869 img_optype = be_get_img_optype(fsec->fsec_entry[i]); 2870 old_fw_img = fsec->fsec_entry[i].optype == 0xFFFF; 2871 2872 if (img_optype == 0xFFFF) 2873 continue; 2874 2875 if (flash_offset_support) 2876 flash_optype = OPTYPE_OFFSET_SPECIFIED; 2877 else 2878 flash_optype = img_optype; 2879 2880 /* Don't bother verifying CRC if an old FW image is being 2881 * flashed 2882 */ 2883 if (old_fw_img) 2884 goto flash; 2885 2886 status = be_check_flash_crc(adapter, fw->data, img_offset, 2887 img_size, filehdr_size + 2888 img_hdrs_size, flash_optype, 2889 &crc_match); 2890 if (base_status(status) == MCC_STATUS_ILLEGAL_REQUEST || 2891 base_status(status) == MCC_STATUS_ILLEGAL_FIELD) { 2892 /* The current FW image on the card does not support 2893 * OFFSET based flashing. Retry using older mechanism 2894 * of OPTYPE based flashing 2895 */ 2896 if (flash_optype == OPTYPE_OFFSET_SPECIFIED) { 2897 flash_offset_support = false; 2898 goto retry_flash; 2899 } 2900 2901 /* The current FW image on the card does not recognize 2902 * the new FLASH op_type. The FW download is partially 2903 * complete. Reboot the server now to enable FW image 2904 * to recognize the new FLASH op_type. To complete the 2905 * remaining process, download the same FW again after 2906 * the reboot. 2907 */ 2908 dev_err(dev, "Flash incomplete. Reset the server\n"); 2909 dev_err(dev, "Download FW image again after reset\n"); 2910 return -EAGAIN; 2911 } else if (status) { 2912 dev_err(dev, "Could not get CRC for 0x%x region\n", 2913 img_optype); 2914 return -EFAULT; 2915 } 2916 2917 if (crc_match) 2918 continue; 2919 2920 flash: 2921 p = fw->data + filehdr_size + img_offset + img_hdrs_size; 2922 if (p + img_size > fw->data + fw->size) 2923 return -1; 2924 2925 status = be_flash(adapter, p, flash_cmd, flash_optype, img_size, 2926 img_offset); 2927 2928 /* The current FW image on the card does not support OFFSET 2929 * based flashing. Retry using older mechanism of OPTYPE based 2930 * flashing 2931 */ 2932 if (base_status(status) == MCC_STATUS_ILLEGAL_FIELD && 2933 flash_optype == OPTYPE_OFFSET_SPECIFIED) { 2934 flash_offset_support = false; 2935 goto retry_flash; 2936 } 2937 2938 /* For old FW images ignore ILLEGAL_FIELD error or errors on 2939 * UFI_DIR region 2940 */ 2941 if (old_fw_img && 2942 (base_status(status) == MCC_STATUS_ILLEGAL_FIELD || 2943 (img_optype == OPTYPE_UFI_DIR && 2944 base_status(status) == MCC_STATUS_FAILED))) { 2945 continue; 2946 } else if (status) { 2947 dev_err(dev, "Flashing section type 0x%x failed\n", 2948 img_type); 2949 2950 switch (addl_status(status)) { 2951 case MCC_ADDL_STATUS_MISSING_SIGNATURE: 2952 dev_err(dev, 2953 "Digital signature missing in FW\n"); 2954 return -EINVAL; 2955 case MCC_ADDL_STATUS_INVALID_SIGNATURE: 2956 dev_err(dev, 2957 "Invalid digital signature in FW\n"); 2958 return -EINVAL; 2959 default: 2960 return -EFAULT; 2961 } 2962 } 2963 } 2964 return 0; 2965 } 2966 2967 int lancer_fw_download(struct be_adapter *adapter, 2968 const struct firmware *fw) 2969 { 2970 struct device *dev = &adapter->pdev->dev; 2971 struct be_dma_mem flash_cmd; 2972 const u8 *data_ptr = NULL; 2973 u8 *dest_image_ptr = NULL; 2974 size_t image_size = 0; 2975 u32 chunk_size = 0; 2976 u32 data_written = 0; 2977 u32 offset = 0; 2978 int status = 0; 2979 u8 add_status = 0; 2980 u8 change_status; 2981 2982 if (!IS_ALIGNED(fw->size, sizeof(u32))) { 2983 dev_err(dev, "FW image size should be multiple of 4\n"); 2984 return -EINVAL; 2985 } 2986 2987 flash_cmd.size = sizeof(struct lancer_cmd_req_write_object) 2988 + LANCER_FW_DOWNLOAD_CHUNK; 2989 flash_cmd.va = dma_zalloc_coherent(dev, flash_cmd.size, 2990 &flash_cmd.dma, GFP_KERNEL); 2991 if (!flash_cmd.va) 2992 return -ENOMEM; 2993 2994 dest_image_ptr = flash_cmd.va + 2995 sizeof(struct lancer_cmd_req_write_object); 2996 image_size = fw->size; 2997 data_ptr = fw->data; 2998 2999 while (image_size) { 3000 chunk_size = min_t(u32, image_size, LANCER_FW_DOWNLOAD_CHUNK); 3001 3002 /* Copy the image chunk content. */ 3003 memcpy(dest_image_ptr, data_ptr, chunk_size); 3004 3005 status = lancer_cmd_write_object(adapter, &flash_cmd, 3006 chunk_size, offset, 3007 LANCER_FW_DOWNLOAD_LOCATION, 3008 &data_written, &change_status, 3009 &add_status); 3010 if (status) 3011 break; 3012 3013 offset += data_written; 3014 data_ptr += data_written; 3015 image_size -= data_written; 3016 } 3017 3018 if (!status) { 3019 /* Commit the FW written */ 3020 status = lancer_cmd_write_object(adapter, &flash_cmd, 3021 0, offset, 3022 LANCER_FW_DOWNLOAD_LOCATION, 3023 &data_written, &change_status, 3024 &add_status); 3025 } 3026 3027 dma_free_coherent(dev, flash_cmd.size, flash_cmd.va, flash_cmd.dma); 3028 if (status) { 3029 dev_err(dev, "Firmware load error\n"); 3030 return be_cmd_status(status); 3031 } 3032 3033 dev_info(dev, "Firmware flashed successfully\n"); 3034 3035 if (change_status == LANCER_FW_RESET_NEEDED) { 3036 dev_info(dev, "Resetting adapter to activate new FW\n"); 3037 status = lancer_physdev_ctrl(adapter, 3038 PHYSDEV_CONTROL_FW_RESET_MASK); 3039 if (status) { 3040 dev_err(dev, "Adapter busy, could not reset FW\n"); 3041 dev_err(dev, "Reboot server to activate new FW\n"); 3042 } 3043 } else if (change_status != LANCER_NO_RESET_NEEDED) { 3044 dev_info(dev, "Reboot server to activate new FW\n"); 3045 } 3046 3047 return 0; 3048 } 3049 3050 /* Check if the flash image file is compatible with the adapter that 3051 * is being flashed. 3052 */ 3053 static bool be_check_ufi_compatibility(struct be_adapter *adapter, 3054 struct flash_file_hdr_g3 *fhdr) 3055 { 3056 if (!fhdr) { 3057 dev_err(&adapter->pdev->dev, "Invalid FW UFI file"); 3058 return false; 3059 } 3060 3061 /* First letter of the build version is used to identify 3062 * which chip this image file is meant for. 3063 */ 3064 switch (fhdr->build[0]) { 3065 case BLD_STR_UFI_TYPE_SH: 3066 if (!skyhawk_chip(adapter)) 3067 return false; 3068 break; 3069 case BLD_STR_UFI_TYPE_BE3: 3070 if (!BE3_chip(adapter)) 3071 return false; 3072 break; 3073 case BLD_STR_UFI_TYPE_BE2: 3074 if (!BE2_chip(adapter)) 3075 return false; 3076 break; 3077 default: 3078 return false; 3079 } 3080 3081 /* In BE3 FW images the "asic_type_rev" field doesn't track the 3082 * asic_rev of the chips it is compatible with. 3083 * When asic_type_rev is 0 the image is compatible only with 3084 * pre-BE3-R chips (asic_rev < 0x10) 3085 */ 3086 if (BEx_chip(adapter) && fhdr->asic_type_rev == 0) 3087 return adapter->asic_rev < 0x10; 3088 else 3089 return (fhdr->asic_type_rev >= adapter->asic_rev); 3090 } 3091 3092 int be_fw_download(struct be_adapter *adapter, const struct firmware *fw) 3093 { 3094 struct device *dev = &adapter->pdev->dev; 3095 struct flash_file_hdr_g3 *fhdr3; 3096 struct image_hdr *img_hdr_ptr; 3097 int status = 0, i, num_imgs; 3098 struct be_dma_mem flash_cmd; 3099 3100 fhdr3 = (struct flash_file_hdr_g3 *)fw->data; 3101 if (!be_check_ufi_compatibility(adapter, fhdr3)) { 3102 dev_err(dev, "Flash image is not compatible with adapter\n"); 3103 return -EINVAL; 3104 } 3105 3106 flash_cmd.size = sizeof(struct be_cmd_write_flashrom); 3107 flash_cmd.va = dma_zalloc_coherent(dev, flash_cmd.size, &flash_cmd.dma, 3108 GFP_KERNEL); 3109 if (!flash_cmd.va) 3110 return -ENOMEM; 3111 3112 num_imgs = le32_to_cpu(fhdr3->num_imgs); 3113 for (i = 0; i < num_imgs; i++) { 3114 img_hdr_ptr = (struct image_hdr *)(fw->data + 3115 (sizeof(struct flash_file_hdr_g3) + 3116 i * sizeof(struct image_hdr))); 3117 if (!BE2_chip(adapter) && 3118 le32_to_cpu(img_hdr_ptr->imageid) != 1) 3119 continue; 3120 3121 if (skyhawk_chip(adapter)) 3122 status = be_flash_skyhawk(adapter, fw, &flash_cmd, 3123 num_imgs); 3124 else 3125 status = be_flash_BEx(adapter, fw, &flash_cmd, 3126 num_imgs); 3127 } 3128 3129 dma_free_coherent(dev, flash_cmd.size, flash_cmd.va, flash_cmd.dma); 3130 if (!status) 3131 dev_info(dev, "Firmware flashed successfully\n"); 3132 3133 return status; 3134 } 3135 3136 int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac, 3137 struct be_dma_mem *nonemb_cmd) 3138 { 3139 struct be_mcc_wrb *wrb; 3140 struct be_cmd_req_acpi_wol_magic_config *req; 3141 int status; 3142 3143 spin_lock_bh(&adapter->mcc_lock); 3144 3145 wrb = wrb_from_mccq(adapter); 3146 if (!wrb) { 3147 status = -EBUSY; 3148 goto err; 3149 } 3150 req = nonemb_cmd->va; 3151 3152 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, 3153 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req), 3154 wrb, nonemb_cmd); 3155 memcpy(req->magic_mac, mac, ETH_ALEN); 3156 3157 status = be_mcc_notify_wait(adapter); 3158 3159 err: 3160 spin_unlock_bh(&adapter->mcc_lock); 3161 return status; 3162 } 3163 3164 int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num, 3165 u8 loopback_type, u8 enable) 3166 { 3167 struct be_mcc_wrb *wrb; 3168 struct be_cmd_req_set_lmode *req; 3169 int status; 3170 3171 spin_lock_bh(&adapter->mcc_lock); 3172 3173 wrb = wrb_from_mccq(adapter); 3174 if (!wrb) { 3175 status = -EBUSY; 3176 goto err_unlock; 3177 } 3178 3179 req = embedded_payload(wrb); 3180 3181 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL, 3182 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE, sizeof(*req), 3183 wrb, NULL); 3184 3185 req->src_port = port_num; 3186 req->dest_port = port_num; 3187 req->loopback_type = loopback_type; 3188 req->loopback_state = enable; 3189 3190 status = be_mcc_notify(adapter); 3191 if (status) 3192 goto err_unlock; 3193 3194 spin_unlock_bh(&adapter->mcc_lock); 3195 3196 if (!wait_for_completion_timeout(&adapter->et_cmd_compl, 3197 msecs_to_jiffies(SET_LB_MODE_TIMEOUT))) 3198 status = -ETIMEDOUT; 3199 3200 return status; 3201 3202 err_unlock: 3203 spin_unlock_bh(&adapter->mcc_lock); 3204 return status; 3205 } 3206 3207 int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num, 3208 u32 loopback_type, u32 pkt_size, u32 num_pkts, 3209 u64 pattern) 3210 { 3211 struct be_mcc_wrb *wrb; 3212 struct be_cmd_req_loopback_test *req; 3213 struct be_cmd_resp_loopback_test *resp; 3214 int status; 3215 3216 spin_lock_bh(&adapter->mcc_lock); 3217 3218 wrb = wrb_from_mccq(adapter); 3219 if (!wrb) { 3220 status = -EBUSY; 3221 goto err; 3222 } 3223 3224 req = embedded_payload(wrb); 3225 3226 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL, 3227 OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req), wrb, 3228 NULL); 3229 3230 req->hdr.timeout = cpu_to_le32(15); 3231 req->pattern = cpu_to_le64(pattern); 3232 req->src_port = cpu_to_le32(port_num); 3233 req->dest_port = cpu_to_le32(port_num); 3234 req->pkt_size = cpu_to_le32(pkt_size); 3235 req->num_pkts = cpu_to_le32(num_pkts); 3236 req->loopback_type = cpu_to_le32(loopback_type); 3237 3238 status = be_mcc_notify(adapter); 3239 if (status) 3240 goto err; 3241 3242 spin_unlock_bh(&adapter->mcc_lock); 3243 3244 wait_for_completion(&adapter->et_cmd_compl); 3245 resp = embedded_payload(wrb); 3246 status = le32_to_cpu(resp->status); 3247 3248 return status; 3249 err: 3250 spin_unlock_bh(&adapter->mcc_lock); 3251 return status; 3252 } 3253 3254 int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern, 3255 u32 byte_cnt, struct be_dma_mem *cmd) 3256 { 3257 struct be_mcc_wrb *wrb; 3258 struct be_cmd_req_ddrdma_test *req; 3259 int status; 3260 int i, j = 0; 3261 3262 spin_lock_bh(&adapter->mcc_lock); 3263 3264 wrb = wrb_from_mccq(adapter); 3265 if (!wrb) { 3266 status = -EBUSY; 3267 goto err; 3268 } 3269 req = cmd->va; 3270 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL, 3271 OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size, wrb, 3272 cmd); 3273 3274 req->pattern = cpu_to_le64(pattern); 3275 req->byte_count = cpu_to_le32(byte_cnt); 3276 for (i = 0; i < byte_cnt; i++) { 3277 req->snd_buff[i] = (u8)(pattern >> (j*8)); 3278 j++; 3279 if (j > 7) 3280 j = 0; 3281 } 3282 3283 status = be_mcc_notify_wait(adapter); 3284 3285 if (!status) { 3286 struct be_cmd_resp_ddrdma_test *resp; 3287 3288 resp = cmd->va; 3289 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) || 3290 resp->snd_err) { 3291 status = -1; 3292 } 3293 } 3294 3295 err: 3296 spin_unlock_bh(&adapter->mcc_lock); 3297 return status; 3298 } 3299 3300 int be_cmd_get_seeprom_data(struct be_adapter *adapter, 3301 struct be_dma_mem *nonemb_cmd) 3302 { 3303 struct be_mcc_wrb *wrb; 3304 struct be_cmd_req_seeprom_read *req; 3305 int status; 3306 3307 spin_lock_bh(&adapter->mcc_lock); 3308 3309 wrb = wrb_from_mccq(adapter); 3310 if (!wrb) { 3311 status = -EBUSY; 3312 goto err; 3313 } 3314 req = nonemb_cmd->va; 3315 3316 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 3317 OPCODE_COMMON_SEEPROM_READ, sizeof(*req), wrb, 3318 nonemb_cmd); 3319 3320 status = be_mcc_notify_wait(adapter); 3321 3322 err: 3323 spin_unlock_bh(&adapter->mcc_lock); 3324 return status; 3325 } 3326 3327 int be_cmd_get_phy_info(struct be_adapter *adapter) 3328 { 3329 struct be_mcc_wrb *wrb; 3330 struct be_cmd_req_get_phy_info *req; 3331 struct be_dma_mem cmd; 3332 int status; 3333 3334 if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_PHY_DETAILS, 3335 CMD_SUBSYSTEM_COMMON)) 3336 return -EPERM; 3337 3338 spin_lock_bh(&adapter->mcc_lock); 3339 3340 wrb = wrb_from_mccq(adapter); 3341 if (!wrb) { 3342 status = -EBUSY; 3343 goto err; 3344 } 3345 cmd.size = sizeof(struct be_cmd_req_get_phy_info); 3346 cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma, 3347 GFP_ATOMIC); 3348 if (!cmd.va) { 3349 dev_err(&adapter->pdev->dev, "Memory alloc failure\n"); 3350 status = -ENOMEM; 3351 goto err; 3352 } 3353 3354 req = cmd.va; 3355 3356 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 3357 OPCODE_COMMON_GET_PHY_DETAILS, sizeof(*req), 3358 wrb, &cmd); 3359 3360 status = be_mcc_notify_wait(adapter); 3361 if (!status) { 3362 struct be_phy_info *resp_phy_info = 3363 cmd.va + sizeof(struct be_cmd_req_hdr); 3364 3365 adapter->phy.phy_type = le16_to_cpu(resp_phy_info->phy_type); 3366 adapter->phy.interface_type = 3367 le16_to_cpu(resp_phy_info->interface_type); 3368 adapter->phy.auto_speeds_supported = 3369 le16_to_cpu(resp_phy_info->auto_speeds_supported); 3370 adapter->phy.fixed_speeds_supported = 3371 le16_to_cpu(resp_phy_info->fixed_speeds_supported); 3372 adapter->phy.misc_params = 3373 le32_to_cpu(resp_phy_info->misc_params); 3374 3375 if (BE2_chip(adapter)) { 3376 adapter->phy.fixed_speeds_supported = 3377 BE_SUPPORTED_SPEED_10GBPS | 3378 BE_SUPPORTED_SPEED_1GBPS; 3379 } 3380 } 3381 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, cmd.dma); 3382 err: 3383 spin_unlock_bh(&adapter->mcc_lock); 3384 return status; 3385 } 3386 3387 static int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain) 3388 { 3389 struct be_mcc_wrb *wrb; 3390 struct be_cmd_req_set_qos *req; 3391 int status; 3392 3393 spin_lock_bh(&adapter->mcc_lock); 3394 3395 wrb = wrb_from_mccq(adapter); 3396 if (!wrb) { 3397 status = -EBUSY; 3398 goto err; 3399 } 3400 3401 req = embedded_payload(wrb); 3402 3403 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 3404 OPCODE_COMMON_SET_QOS, sizeof(*req), wrb, NULL); 3405 3406 req->hdr.domain = domain; 3407 req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC); 3408 req->max_bps_nic = cpu_to_le32(bps); 3409 3410 status = be_mcc_notify_wait(adapter); 3411 3412 err: 3413 spin_unlock_bh(&adapter->mcc_lock); 3414 return status; 3415 } 3416 3417 int be_cmd_get_cntl_attributes(struct be_adapter *adapter) 3418 { 3419 struct be_mcc_wrb *wrb; 3420 struct be_cmd_req_cntl_attribs *req; 3421 struct be_cmd_resp_cntl_attribs *resp; 3422 int status, i; 3423 int payload_len = max(sizeof(*req), sizeof(*resp)); 3424 struct mgmt_controller_attrib *attribs; 3425 struct be_dma_mem attribs_cmd; 3426 u32 *serial_num; 3427 3428 if (mutex_lock_interruptible(&adapter->mbox_lock)) 3429 return -1; 3430 3431 memset(&attribs_cmd, 0, sizeof(struct be_dma_mem)); 3432 attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs); 3433 attribs_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, 3434 attribs_cmd.size, 3435 &attribs_cmd.dma, GFP_ATOMIC); 3436 if (!attribs_cmd.va) { 3437 dev_err(&adapter->pdev->dev, "Memory allocation failure\n"); 3438 status = -ENOMEM; 3439 goto err; 3440 } 3441 3442 wrb = wrb_from_mbox(adapter); 3443 if (!wrb) { 3444 status = -EBUSY; 3445 goto err; 3446 } 3447 req = attribs_cmd.va; 3448 3449 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 3450 OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len, 3451 wrb, &attribs_cmd); 3452 3453 status = be_mbox_notify_wait(adapter); 3454 if (!status) { 3455 attribs = attribs_cmd.va + sizeof(struct be_cmd_resp_hdr); 3456 adapter->hba_port_num = attribs->hba_attribs.phy_port; 3457 serial_num = attribs->hba_attribs.controller_serial_number; 3458 for (i = 0; i < CNTL_SERIAL_NUM_WORDS; i++) 3459 adapter->serial_num[i] = le32_to_cpu(serial_num[i]) & 3460 (BIT_MASK(16) - 1); 3461 } 3462 3463 err: 3464 mutex_unlock(&adapter->mbox_lock); 3465 if (attribs_cmd.va) 3466 dma_free_coherent(&adapter->pdev->dev, attribs_cmd.size, 3467 attribs_cmd.va, attribs_cmd.dma); 3468 return status; 3469 } 3470 3471 /* Uses mbox */ 3472 int be_cmd_req_native_mode(struct be_adapter *adapter) 3473 { 3474 struct be_mcc_wrb *wrb; 3475 struct be_cmd_req_set_func_cap *req; 3476 int status; 3477 3478 if (mutex_lock_interruptible(&adapter->mbox_lock)) 3479 return -1; 3480 3481 wrb = wrb_from_mbox(adapter); 3482 if (!wrb) { 3483 status = -EBUSY; 3484 goto err; 3485 } 3486 3487 req = embedded_payload(wrb); 3488 3489 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 3490 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP, 3491 sizeof(*req), wrb, NULL); 3492 3493 req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS | 3494 CAPABILITY_BE3_NATIVE_ERX_API); 3495 req->cap_flags = cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API); 3496 3497 status = be_mbox_notify_wait(adapter); 3498 if (!status) { 3499 struct be_cmd_resp_set_func_cap *resp = embedded_payload(wrb); 3500 3501 adapter->be3_native = le32_to_cpu(resp->cap_flags) & 3502 CAPABILITY_BE3_NATIVE_ERX_API; 3503 if (!adapter->be3_native) 3504 dev_warn(&adapter->pdev->dev, 3505 "adapter not in advanced mode\n"); 3506 } 3507 err: 3508 mutex_unlock(&adapter->mbox_lock); 3509 return status; 3510 } 3511 3512 /* Get privilege(s) for a function */ 3513 int be_cmd_get_fn_privileges(struct be_adapter *adapter, u32 *privilege, 3514 u32 domain) 3515 { 3516 struct be_mcc_wrb *wrb; 3517 struct be_cmd_req_get_fn_privileges *req; 3518 int status; 3519 3520 spin_lock_bh(&adapter->mcc_lock); 3521 3522 wrb = wrb_from_mccq(adapter); 3523 if (!wrb) { 3524 status = -EBUSY; 3525 goto err; 3526 } 3527 3528 req = embedded_payload(wrb); 3529 3530 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 3531 OPCODE_COMMON_GET_FN_PRIVILEGES, sizeof(*req), 3532 wrb, NULL); 3533 3534 req->hdr.domain = domain; 3535 3536 status = be_mcc_notify_wait(adapter); 3537 if (!status) { 3538 struct be_cmd_resp_get_fn_privileges *resp = 3539 embedded_payload(wrb); 3540 3541 *privilege = le32_to_cpu(resp->privilege_mask); 3542 3543 /* In UMC mode FW does not return right privileges. 3544 * Override with correct privilege equivalent to PF. 3545 */ 3546 if (BEx_chip(adapter) && be_is_mc(adapter) && 3547 be_physfn(adapter)) 3548 *privilege = MAX_PRIVILEGES; 3549 } 3550 3551 err: 3552 spin_unlock_bh(&adapter->mcc_lock); 3553 return status; 3554 } 3555 3556 /* Set privilege(s) for a function */ 3557 int be_cmd_set_fn_privileges(struct be_adapter *adapter, u32 privileges, 3558 u32 domain) 3559 { 3560 struct be_mcc_wrb *wrb; 3561 struct be_cmd_req_set_fn_privileges *req; 3562 int status; 3563 3564 spin_lock_bh(&adapter->mcc_lock); 3565 3566 wrb = wrb_from_mccq(adapter); 3567 if (!wrb) { 3568 status = -EBUSY; 3569 goto err; 3570 } 3571 3572 req = embedded_payload(wrb); 3573 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 3574 OPCODE_COMMON_SET_FN_PRIVILEGES, sizeof(*req), 3575 wrb, NULL); 3576 req->hdr.domain = domain; 3577 if (lancer_chip(adapter)) 3578 req->privileges_lancer = cpu_to_le32(privileges); 3579 else 3580 req->privileges = cpu_to_le32(privileges); 3581 3582 status = be_mcc_notify_wait(adapter); 3583 err: 3584 spin_unlock_bh(&adapter->mcc_lock); 3585 return status; 3586 } 3587 3588 /* pmac_id_valid: true => pmac_id is supplied and MAC address is requested. 3589 * pmac_id_valid: false => pmac_id or MAC address is requested. 3590 * If pmac_id is returned, pmac_id_valid is returned as true 3591 */ 3592 int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac, 3593 bool *pmac_id_valid, u32 *pmac_id, u32 if_handle, 3594 u8 domain) 3595 { 3596 struct be_mcc_wrb *wrb; 3597 struct be_cmd_req_get_mac_list *req; 3598 int status; 3599 int mac_count; 3600 struct be_dma_mem get_mac_list_cmd; 3601 int i; 3602 3603 memset(&get_mac_list_cmd, 0, sizeof(struct be_dma_mem)); 3604 get_mac_list_cmd.size = sizeof(struct be_cmd_resp_get_mac_list); 3605 get_mac_list_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, 3606 get_mac_list_cmd.size, 3607 &get_mac_list_cmd.dma, 3608 GFP_ATOMIC); 3609 3610 if (!get_mac_list_cmd.va) { 3611 dev_err(&adapter->pdev->dev, 3612 "Memory allocation failure during GET_MAC_LIST\n"); 3613 return -ENOMEM; 3614 } 3615 3616 spin_lock_bh(&adapter->mcc_lock); 3617 3618 wrb = wrb_from_mccq(adapter); 3619 if (!wrb) { 3620 status = -EBUSY; 3621 goto out; 3622 } 3623 3624 req = get_mac_list_cmd.va; 3625 3626 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 3627 OPCODE_COMMON_GET_MAC_LIST, 3628 get_mac_list_cmd.size, wrb, &get_mac_list_cmd); 3629 req->hdr.domain = domain; 3630 req->mac_type = MAC_ADDRESS_TYPE_NETWORK; 3631 if (*pmac_id_valid) { 3632 req->mac_id = cpu_to_le32(*pmac_id); 3633 req->iface_id = cpu_to_le16(if_handle); 3634 req->perm_override = 0; 3635 } else { 3636 req->perm_override = 1; 3637 } 3638 3639 status = be_mcc_notify_wait(adapter); 3640 if (!status) { 3641 struct be_cmd_resp_get_mac_list *resp = 3642 get_mac_list_cmd.va; 3643 3644 if (*pmac_id_valid) { 3645 memcpy(mac, resp->macid_macaddr.mac_addr_id.macaddr, 3646 ETH_ALEN); 3647 goto out; 3648 } 3649 3650 mac_count = resp->true_mac_count + resp->pseudo_mac_count; 3651 /* Mac list returned could contain one or more active mac_ids 3652 * or one or more true or pseudo permanent mac addresses. 3653 * If an active mac_id is present, return first active mac_id 3654 * found. 3655 */ 3656 for (i = 0; i < mac_count; i++) { 3657 struct get_list_macaddr *mac_entry; 3658 u16 mac_addr_size; 3659 u32 mac_id; 3660 3661 mac_entry = &resp->macaddr_list[i]; 3662 mac_addr_size = le16_to_cpu(mac_entry->mac_addr_size); 3663 /* mac_id is a 32 bit value and mac_addr size 3664 * is 6 bytes 3665 */ 3666 if (mac_addr_size == sizeof(u32)) { 3667 *pmac_id_valid = true; 3668 mac_id = mac_entry->mac_addr_id.s_mac_id.mac_id; 3669 *pmac_id = le32_to_cpu(mac_id); 3670 goto out; 3671 } 3672 } 3673 /* If no active mac_id found, return first mac addr */ 3674 *pmac_id_valid = false; 3675 memcpy(mac, resp->macaddr_list[0].mac_addr_id.macaddr, 3676 ETH_ALEN); 3677 } 3678 3679 out: 3680 spin_unlock_bh(&adapter->mcc_lock); 3681 dma_free_coherent(&adapter->pdev->dev, get_mac_list_cmd.size, 3682 get_mac_list_cmd.va, get_mac_list_cmd.dma); 3683 return status; 3684 } 3685 3686 int be_cmd_get_active_mac(struct be_adapter *adapter, u32 curr_pmac_id, 3687 u8 *mac, u32 if_handle, bool active, u32 domain) 3688 { 3689 if (!active) 3690 be_cmd_get_mac_from_list(adapter, mac, &active, &curr_pmac_id, 3691 if_handle, domain); 3692 if (BEx_chip(adapter)) 3693 return be_cmd_mac_addr_query(adapter, mac, false, 3694 if_handle, curr_pmac_id); 3695 else 3696 /* Fetch the MAC address using pmac_id */ 3697 return be_cmd_get_mac_from_list(adapter, mac, &active, 3698 &curr_pmac_id, 3699 if_handle, domain); 3700 } 3701 3702 int be_cmd_get_perm_mac(struct be_adapter *adapter, u8 *mac) 3703 { 3704 int status; 3705 bool pmac_valid = false; 3706 3707 eth_zero_addr(mac); 3708 3709 if (BEx_chip(adapter)) { 3710 if (be_physfn(adapter)) 3711 status = be_cmd_mac_addr_query(adapter, mac, true, 0, 3712 0); 3713 else 3714 status = be_cmd_mac_addr_query(adapter, mac, false, 3715 adapter->if_handle, 0); 3716 } else { 3717 status = be_cmd_get_mac_from_list(adapter, mac, &pmac_valid, 3718 NULL, adapter->if_handle, 0); 3719 } 3720 3721 return status; 3722 } 3723 3724 /* Uses synchronous MCCQ */ 3725 int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array, 3726 u8 mac_count, u32 domain) 3727 { 3728 struct be_mcc_wrb *wrb; 3729 struct be_cmd_req_set_mac_list *req; 3730 int status; 3731 struct be_dma_mem cmd; 3732 3733 memset(&cmd, 0, sizeof(struct be_dma_mem)); 3734 cmd.size = sizeof(struct be_cmd_req_set_mac_list); 3735 cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma, 3736 GFP_KERNEL); 3737 if (!cmd.va) 3738 return -ENOMEM; 3739 3740 spin_lock_bh(&adapter->mcc_lock); 3741 3742 wrb = wrb_from_mccq(adapter); 3743 if (!wrb) { 3744 status = -EBUSY; 3745 goto err; 3746 } 3747 3748 req = cmd.va; 3749 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 3750 OPCODE_COMMON_SET_MAC_LIST, sizeof(*req), 3751 wrb, &cmd); 3752 3753 req->hdr.domain = domain; 3754 req->mac_count = mac_count; 3755 if (mac_count) 3756 memcpy(req->mac, mac_array, ETH_ALEN*mac_count); 3757 3758 status = be_mcc_notify_wait(adapter); 3759 3760 err: 3761 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, cmd.dma); 3762 spin_unlock_bh(&adapter->mcc_lock); 3763 return status; 3764 } 3765 3766 /* Wrapper to delete any active MACs and provision the new mac. 3767 * Changes to MAC_LIST are allowed iff none of the MAC addresses in the 3768 * current list are active. 3769 */ 3770 int be_cmd_set_mac(struct be_adapter *adapter, u8 *mac, int if_id, u32 dom) 3771 { 3772 bool active_mac = false; 3773 u8 old_mac[ETH_ALEN]; 3774 u32 pmac_id; 3775 int status; 3776 3777 status = be_cmd_get_mac_from_list(adapter, old_mac, &active_mac, 3778 &pmac_id, if_id, dom); 3779 3780 if (!status && active_mac) 3781 be_cmd_pmac_del(adapter, if_id, pmac_id, dom); 3782 3783 return be_cmd_set_mac_list(adapter, mac, mac ? 1 : 0, dom); 3784 } 3785 3786 int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid, 3787 u32 domain, u16 intf_id, u16 hsw_mode, u8 spoofchk) 3788 { 3789 struct be_mcc_wrb *wrb; 3790 struct be_cmd_req_set_hsw_config *req; 3791 void *ctxt; 3792 int status; 3793 3794 spin_lock_bh(&adapter->mcc_lock); 3795 3796 wrb = wrb_from_mccq(adapter); 3797 if (!wrb) { 3798 status = -EBUSY; 3799 goto err; 3800 } 3801 3802 req = embedded_payload(wrb); 3803 ctxt = &req->context; 3804 3805 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 3806 OPCODE_COMMON_SET_HSW_CONFIG, sizeof(*req), wrb, 3807 NULL); 3808 3809 req->hdr.domain = domain; 3810 AMAP_SET_BITS(struct amap_set_hsw_context, interface_id, ctxt, intf_id); 3811 if (pvid) { 3812 AMAP_SET_BITS(struct amap_set_hsw_context, pvid_valid, ctxt, 1); 3813 AMAP_SET_BITS(struct amap_set_hsw_context, pvid, ctxt, pvid); 3814 } 3815 if (!BEx_chip(adapter) && hsw_mode) { 3816 AMAP_SET_BITS(struct amap_set_hsw_context, interface_id, 3817 ctxt, adapter->hba_port_num); 3818 AMAP_SET_BITS(struct amap_set_hsw_context, pport, ctxt, 1); 3819 AMAP_SET_BITS(struct amap_set_hsw_context, port_fwd_type, 3820 ctxt, hsw_mode); 3821 } 3822 3823 /* Enable/disable both mac and vlan spoof checking */ 3824 if (!BEx_chip(adapter) && spoofchk) { 3825 AMAP_SET_BITS(struct amap_set_hsw_context, mac_spoofchk, 3826 ctxt, spoofchk); 3827 AMAP_SET_BITS(struct amap_set_hsw_context, vlan_spoofchk, 3828 ctxt, spoofchk); 3829 } 3830 3831 be_dws_cpu_to_le(req->context, sizeof(req->context)); 3832 status = be_mcc_notify_wait(adapter); 3833 3834 err: 3835 spin_unlock_bh(&adapter->mcc_lock); 3836 return status; 3837 } 3838 3839 /* Get Hyper switch config */ 3840 int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid, 3841 u32 domain, u16 intf_id, u8 *mode, bool *spoofchk) 3842 { 3843 struct be_mcc_wrb *wrb; 3844 struct be_cmd_req_get_hsw_config *req; 3845 void *ctxt; 3846 int status; 3847 u16 vid; 3848 3849 spin_lock_bh(&adapter->mcc_lock); 3850 3851 wrb = wrb_from_mccq(adapter); 3852 if (!wrb) { 3853 status = -EBUSY; 3854 goto err; 3855 } 3856 3857 req = embedded_payload(wrb); 3858 ctxt = &req->context; 3859 3860 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 3861 OPCODE_COMMON_GET_HSW_CONFIG, sizeof(*req), wrb, 3862 NULL); 3863 3864 req->hdr.domain = domain; 3865 AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id, 3866 ctxt, intf_id); 3867 AMAP_SET_BITS(struct amap_get_hsw_req_context, pvid_valid, ctxt, 1); 3868 3869 if (!BEx_chip(adapter) && mode) { 3870 AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id, 3871 ctxt, adapter->hba_port_num); 3872 AMAP_SET_BITS(struct amap_get_hsw_req_context, pport, ctxt, 1); 3873 } 3874 be_dws_cpu_to_le(req->context, sizeof(req->context)); 3875 3876 status = be_mcc_notify_wait(adapter); 3877 if (!status) { 3878 struct be_cmd_resp_get_hsw_config *resp = 3879 embedded_payload(wrb); 3880 3881 be_dws_le_to_cpu(&resp->context, sizeof(resp->context)); 3882 vid = AMAP_GET_BITS(struct amap_get_hsw_resp_context, 3883 pvid, &resp->context); 3884 if (pvid) 3885 *pvid = le16_to_cpu(vid); 3886 if (mode) 3887 *mode = AMAP_GET_BITS(struct amap_get_hsw_resp_context, 3888 port_fwd_type, &resp->context); 3889 if (spoofchk) 3890 *spoofchk = 3891 AMAP_GET_BITS(struct amap_get_hsw_resp_context, 3892 spoofchk, &resp->context); 3893 } 3894 3895 err: 3896 spin_unlock_bh(&adapter->mcc_lock); 3897 return status; 3898 } 3899 3900 static bool be_is_wol_excluded(struct be_adapter *adapter) 3901 { 3902 struct pci_dev *pdev = adapter->pdev; 3903 3904 if (be_virtfn(adapter)) 3905 return true; 3906 3907 switch (pdev->subsystem_device) { 3908 case OC_SUBSYS_DEVICE_ID1: 3909 case OC_SUBSYS_DEVICE_ID2: 3910 case OC_SUBSYS_DEVICE_ID3: 3911 case OC_SUBSYS_DEVICE_ID4: 3912 return true; 3913 default: 3914 return false; 3915 } 3916 } 3917 3918 int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter) 3919 { 3920 struct be_mcc_wrb *wrb; 3921 struct be_cmd_req_acpi_wol_magic_config_v1 *req; 3922 int status = 0; 3923 struct be_dma_mem cmd; 3924 3925 if (!be_cmd_allowed(adapter, OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, 3926 CMD_SUBSYSTEM_ETH)) 3927 return -EPERM; 3928 3929 if (be_is_wol_excluded(adapter)) 3930 return status; 3931 3932 if (mutex_lock_interruptible(&adapter->mbox_lock)) 3933 return -1; 3934 3935 memset(&cmd, 0, sizeof(struct be_dma_mem)); 3936 cmd.size = sizeof(struct be_cmd_resp_acpi_wol_magic_config_v1); 3937 cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma, 3938 GFP_ATOMIC); 3939 if (!cmd.va) { 3940 dev_err(&adapter->pdev->dev, "Memory allocation failure\n"); 3941 status = -ENOMEM; 3942 goto err; 3943 } 3944 3945 wrb = wrb_from_mbox(adapter); 3946 if (!wrb) { 3947 status = -EBUSY; 3948 goto err; 3949 } 3950 3951 req = cmd.va; 3952 3953 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, 3954 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, 3955 sizeof(*req), wrb, &cmd); 3956 3957 req->hdr.version = 1; 3958 req->query_options = BE_GET_WOL_CAP; 3959 3960 status = be_mbox_notify_wait(adapter); 3961 if (!status) { 3962 struct be_cmd_resp_acpi_wol_magic_config_v1 *resp; 3963 3964 resp = (struct be_cmd_resp_acpi_wol_magic_config_v1 *)cmd.va; 3965 3966 adapter->wol_cap = resp->wol_settings; 3967 if (adapter->wol_cap & BE_WOL_CAP) 3968 adapter->wol_en = true; 3969 } 3970 err: 3971 mutex_unlock(&adapter->mbox_lock); 3972 if (cmd.va) 3973 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, 3974 cmd.dma); 3975 return status; 3976 3977 } 3978 3979 int be_cmd_set_fw_log_level(struct be_adapter *adapter, u32 level) 3980 { 3981 struct be_dma_mem extfat_cmd; 3982 struct be_fat_conf_params *cfgs; 3983 int status; 3984 int i, j; 3985 3986 memset(&extfat_cmd, 0, sizeof(struct be_dma_mem)); 3987 extfat_cmd.size = sizeof(struct be_cmd_resp_get_ext_fat_caps); 3988 extfat_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, 3989 extfat_cmd.size, &extfat_cmd.dma, 3990 GFP_ATOMIC); 3991 if (!extfat_cmd.va) 3992 return -ENOMEM; 3993 3994 status = be_cmd_get_ext_fat_capabilites(adapter, &extfat_cmd); 3995 if (status) 3996 goto err; 3997 3998 cfgs = (struct be_fat_conf_params *) 3999 (extfat_cmd.va + sizeof(struct be_cmd_resp_hdr)); 4000 for (i = 0; i < le32_to_cpu(cfgs->num_modules); i++) { 4001 u32 num_modes = le32_to_cpu(cfgs->module[i].num_modes); 4002 4003 for (j = 0; j < num_modes; j++) { 4004 if (cfgs->module[i].trace_lvl[j].mode == MODE_UART) 4005 cfgs->module[i].trace_lvl[j].dbg_lvl = 4006 cpu_to_le32(level); 4007 } 4008 } 4009 4010 status = be_cmd_set_ext_fat_capabilites(adapter, &extfat_cmd, cfgs); 4011 err: 4012 dma_free_coherent(&adapter->pdev->dev, extfat_cmd.size, extfat_cmd.va, 4013 extfat_cmd.dma); 4014 return status; 4015 } 4016 4017 int be_cmd_get_fw_log_level(struct be_adapter *adapter) 4018 { 4019 struct be_dma_mem extfat_cmd; 4020 struct be_fat_conf_params *cfgs; 4021 int status, j; 4022 int level = 0; 4023 4024 memset(&extfat_cmd, 0, sizeof(struct be_dma_mem)); 4025 extfat_cmd.size = sizeof(struct be_cmd_resp_get_ext_fat_caps); 4026 extfat_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, 4027 extfat_cmd.size, &extfat_cmd.dma, 4028 GFP_ATOMIC); 4029 4030 if (!extfat_cmd.va) { 4031 dev_err(&adapter->pdev->dev, "%s: Memory allocation failure\n", 4032 __func__); 4033 goto err; 4034 } 4035 4036 status = be_cmd_get_ext_fat_capabilites(adapter, &extfat_cmd); 4037 if (!status) { 4038 cfgs = (struct be_fat_conf_params *)(extfat_cmd.va + 4039 sizeof(struct be_cmd_resp_hdr)); 4040 4041 for (j = 0; j < le32_to_cpu(cfgs->module[0].num_modes); j++) { 4042 if (cfgs->module[0].trace_lvl[j].mode == MODE_UART) 4043 level = cfgs->module[0].trace_lvl[j].dbg_lvl; 4044 } 4045 } 4046 dma_free_coherent(&adapter->pdev->dev, extfat_cmd.size, extfat_cmd.va, 4047 extfat_cmd.dma); 4048 err: 4049 return level; 4050 } 4051 4052 int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter, 4053 struct be_dma_mem *cmd) 4054 { 4055 struct be_mcc_wrb *wrb; 4056 struct be_cmd_req_get_ext_fat_caps *req; 4057 int status; 4058 4059 if (mutex_lock_interruptible(&adapter->mbox_lock)) 4060 return -1; 4061 4062 wrb = wrb_from_mbox(adapter); 4063 if (!wrb) { 4064 status = -EBUSY; 4065 goto err; 4066 } 4067 4068 req = cmd->va; 4069 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 4070 OPCODE_COMMON_GET_EXT_FAT_CAPABILITES, 4071 cmd->size, wrb, cmd); 4072 req->parameter_type = cpu_to_le32(1); 4073 4074 status = be_mbox_notify_wait(adapter); 4075 err: 4076 mutex_unlock(&adapter->mbox_lock); 4077 return status; 4078 } 4079 4080 int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter, 4081 struct be_dma_mem *cmd, 4082 struct be_fat_conf_params *configs) 4083 { 4084 struct be_mcc_wrb *wrb; 4085 struct be_cmd_req_set_ext_fat_caps *req; 4086 int status; 4087 4088 spin_lock_bh(&adapter->mcc_lock); 4089 4090 wrb = wrb_from_mccq(adapter); 4091 if (!wrb) { 4092 status = -EBUSY; 4093 goto err; 4094 } 4095 4096 req = cmd->va; 4097 memcpy(&req->set_params, configs, sizeof(struct be_fat_conf_params)); 4098 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 4099 OPCODE_COMMON_SET_EXT_FAT_CAPABILITES, 4100 cmd->size, wrb, cmd); 4101 4102 status = be_mcc_notify_wait(adapter); 4103 err: 4104 spin_unlock_bh(&adapter->mcc_lock); 4105 return status; 4106 } 4107 4108 int be_cmd_query_port_name(struct be_adapter *adapter) 4109 { 4110 struct be_cmd_req_get_port_name *req; 4111 struct be_mcc_wrb *wrb; 4112 int status; 4113 4114 if (mutex_lock_interruptible(&adapter->mbox_lock)) 4115 return -1; 4116 4117 wrb = wrb_from_mbox(adapter); 4118 req = embedded_payload(wrb); 4119 4120 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 4121 OPCODE_COMMON_GET_PORT_NAME, sizeof(*req), wrb, 4122 NULL); 4123 if (!BEx_chip(adapter)) 4124 req->hdr.version = 1; 4125 4126 status = be_mbox_notify_wait(adapter); 4127 if (!status) { 4128 struct be_cmd_resp_get_port_name *resp = embedded_payload(wrb); 4129 4130 adapter->port_name = resp->port_name[adapter->hba_port_num]; 4131 } else { 4132 adapter->port_name = adapter->hba_port_num + '0'; 4133 } 4134 4135 mutex_unlock(&adapter->mbox_lock); 4136 return status; 4137 } 4138 4139 /* When more than 1 NIC descriptor is present in the descriptor list, 4140 * the caller must specify the pf_num to obtain the NIC descriptor 4141 * corresponding to its pci function. 4142 * get_vft must be true when the caller wants the VF-template desc of the 4143 * PF-pool. 4144 * The pf_num should be set to PF_NUM_IGNORE when the caller knows 4145 * that only it's NIC descriptor is present in the descriptor list. 4146 */ 4147 static struct be_nic_res_desc *be_get_nic_desc(u8 *buf, u32 desc_count, 4148 bool get_vft, u8 pf_num) 4149 { 4150 struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf; 4151 struct be_nic_res_desc *nic; 4152 int i; 4153 4154 for (i = 0; i < desc_count; i++) { 4155 if (hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V0 || 4156 hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V1) { 4157 nic = (struct be_nic_res_desc *)hdr; 4158 4159 if ((pf_num == PF_NUM_IGNORE || 4160 nic->pf_num == pf_num) && 4161 (!get_vft || nic->flags & BIT(VFT_SHIFT))) 4162 return nic; 4163 } 4164 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0; 4165 hdr = (void *)hdr + hdr->desc_len; 4166 } 4167 return NULL; 4168 } 4169 4170 static struct be_nic_res_desc *be_get_vft_desc(u8 *buf, u32 desc_count, 4171 u8 pf_num) 4172 { 4173 return be_get_nic_desc(buf, desc_count, true, pf_num); 4174 } 4175 4176 static struct be_nic_res_desc *be_get_func_nic_desc(u8 *buf, u32 desc_count, 4177 u8 pf_num) 4178 { 4179 return be_get_nic_desc(buf, desc_count, false, pf_num); 4180 } 4181 4182 static struct be_pcie_res_desc *be_get_pcie_desc(u8 *buf, u32 desc_count, 4183 u8 pf_num) 4184 { 4185 struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf; 4186 struct be_pcie_res_desc *pcie; 4187 int i; 4188 4189 for (i = 0; i < desc_count; i++) { 4190 if (hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V0 || 4191 hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V1) { 4192 pcie = (struct be_pcie_res_desc *)hdr; 4193 if (pcie->pf_num == pf_num) 4194 return pcie; 4195 } 4196 4197 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0; 4198 hdr = (void *)hdr + hdr->desc_len; 4199 } 4200 return NULL; 4201 } 4202 4203 static struct be_port_res_desc *be_get_port_desc(u8 *buf, u32 desc_count) 4204 { 4205 struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf; 4206 int i; 4207 4208 for (i = 0; i < desc_count; i++) { 4209 if (hdr->desc_type == PORT_RESOURCE_DESC_TYPE_V1) 4210 return (struct be_port_res_desc *)hdr; 4211 4212 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0; 4213 hdr = (void *)hdr + hdr->desc_len; 4214 } 4215 return NULL; 4216 } 4217 4218 static void be_copy_nic_desc(struct be_resources *res, 4219 struct be_nic_res_desc *desc) 4220 { 4221 res->max_uc_mac = le16_to_cpu(desc->unicast_mac_count); 4222 res->max_vlans = le16_to_cpu(desc->vlan_count); 4223 res->max_mcast_mac = le16_to_cpu(desc->mcast_mac_count); 4224 res->max_tx_qs = le16_to_cpu(desc->txq_count); 4225 res->max_rss_qs = le16_to_cpu(desc->rssq_count); 4226 res->max_rx_qs = le16_to_cpu(desc->rq_count); 4227 res->max_evt_qs = le16_to_cpu(desc->eq_count); 4228 res->max_cq_count = le16_to_cpu(desc->cq_count); 4229 res->max_iface_count = le16_to_cpu(desc->iface_count); 4230 res->max_mcc_count = le16_to_cpu(desc->mcc_count); 4231 /* Clear flags that driver is not interested in */ 4232 res->if_cap_flags = le32_to_cpu(desc->cap_flags) & 4233 BE_IF_CAP_FLAGS_WANT; 4234 } 4235 4236 /* Uses Mbox */ 4237 int be_cmd_get_func_config(struct be_adapter *adapter, struct be_resources *res) 4238 { 4239 struct be_mcc_wrb *wrb; 4240 struct be_cmd_req_get_func_config *req; 4241 int status; 4242 struct be_dma_mem cmd; 4243 4244 if (mutex_lock_interruptible(&adapter->mbox_lock)) 4245 return -1; 4246 4247 memset(&cmd, 0, sizeof(struct be_dma_mem)); 4248 cmd.size = sizeof(struct be_cmd_resp_get_func_config); 4249 cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma, 4250 GFP_ATOMIC); 4251 if (!cmd.va) { 4252 dev_err(&adapter->pdev->dev, "Memory alloc failure\n"); 4253 status = -ENOMEM; 4254 goto err; 4255 } 4256 4257 wrb = wrb_from_mbox(adapter); 4258 if (!wrb) { 4259 status = -EBUSY; 4260 goto err; 4261 } 4262 4263 req = cmd.va; 4264 4265 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 4266 OPCODE_COMMON_GET_FUNC_CONFIG, 4267 cmd.size, wrb, &cmd); 4268 4269 if (skyhawk_chip(adapter)) 4270 req->hdr.version = 1; 4271 4272 status = be_mbox_notify_wait(adapter); 4273 if (!status) { 4274 struct be_cmd_resp_get_func_config *resp = cmd.va; 4275 u32 desc_count = le32_to_cpu(resp->desc_count); 4276 struct be_nic_res_desc *desc; 4277 4278 /* GET_FUNC_CONFIG returns resource descriptors of the 4279 * current function only. So, pf_num should be set to 4280 * PF_NUM_IGNORE. 4281 */ 4282 desc = be_get_func_nic_desc(resp->func_param, desc_count, 4283 PF_NUM_IGNORE); 4284 if (!desc) { 4285 status = -EINVAL; 4286 goto err; 4287 } 4288 4289 /* Store pf_num & vf_num for later use in GET_PROFILE_CONFIG */ 4290 adapter->pf_num = desc->pf_num; 4291 adapter->vf_num = desc->vf_num; 4292 4293 if (res) 4294 be_copy_nic_desc(res, desc); 4295 } 4296 err: 4297 mutex_unlock(&adapter->mbox_lock); 4298 if (cmd.va) 4299 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, 4300 cmd.dma); 4301 return status; 4302 } 4303 4304 /* Will use MBOX only if MCCQ has not been created */ 4305 int be_cmd_get_profile_config(struct be_adapter *adapter, 4306 struct be_resources *res, u8 query, u8 domain) 4307 { 4308 struct be_cmd_resp_get_profile_config *resp; 4309 struct be_cmd_req_get_profile_config *req; 4310 struct be_nic_res_desc *vf_res; 4311 struct be_pcie_res_desc *pcie; 4312 struct be_port_res_desc *port; 4313 struct be_nic_res_desc *nic; 4314 struct be_mcc_wrb wrb = {0}; 4315 struct be_dma_mem cmd; 4316 u16 desc_count; 4317 int status; 4318 4319 memset(&cmd, 0, sizeof(struct be_dma_mem)); 4320 cmd.size = sizeof(struct be_cmd_resp_get_profile_config); 4321 cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma, 4322 GFP_ATOMIC); 4323 if (!cmd.va) 4324 return -ENOMEM; 4325 4326 req = cmd.va; 4327 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 4328 OPCODE_COMMON_GET_PROFILE_CONFIG, 4329 cmd.size, &wrb, &cmd); 4330 4331 if (!lancer_chip(adapter)) 4332 req->hdr.version = 1; 4333 req->type = ACTIVE_PROFILE_TYPE; 4334 req->hdr.domain = domain; 4335 4336 /* When QUERY_MODIFIABLE_FIELDS_TYPE bit is set, cmd returns the 4337 * descriptors with all bits set to "1" for the fields which can be 4338 * modified using SET_PROFILE_CONFIG cmd. 4339 */ 4340 if (query == RESOURCE_MODIFIABLE) 4341 req->type |= QUERY_MODIFIABLE_FIELDS_TYPE; 4342 4343 status = be_cmd_notify_wait(adapter, &wrb); 4344 if (status) 4345 goto err; 4346 4347 resp = cmd.va; 4348 desc_count = le16_to_cpu(resp->desc_count); 4349 4350 pcie = be_get_pcie_desc(resp->func_param, desc_count, 4351 adapter->pf_num); 4352 if (pcie) 4353 res->max_vfs = le16_to_cpu(pcie->num_vfs); 4354 4355 port = be_get_port_desc(resp->func_param, desc_count); 4356 if (port) 4357 adapter->mc_type = port->mc_type; 4358 4359 nic = be_get_func_nic_desc(resp->func_param, desc_count, 4360 adapter->pf_num); 4361 if (nic) 4362 be_copy_nic_desc(res, nic); 4363 4364 vf_res = be_get_vft_desc(resp->func_param, desc_count, 4365 adapter->pf_num); 4366 if (vf_res) 4367 res->vf_if_cap_flags = vf_res->cap_flags; 4368 err: 4369 if (cmd.va) 4370 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, 4371 cmd.dma); 4372 return status; 4373 } 4374 4375 /* Will use MBOX only if MCCQ has not been created */ 4376 static int be_cmd_set_profile_config(struct be_adapter *adapter, void *desc, 4377 int size, int count, u8 version, u8 domain) 4378 { 4379 struct be_cmd_req_set_profile_config *req; 4380 struct be_mcc_wrb wrb = {0}; 4381 struct be_dma_mem cmd; 4382 int status; 4383 4384 memset(&cmd, 0, sizeof(struct be_dma_mem)); 4385 cmd.size = sizeof(struct be_cmd_req_set_profile_config); 4386 cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma, 4387 GFP_ATOMIC); 4388 if (!cmd.va) 4389 return -ENOMEM; 4390 4391 req = cmd.va; 4392 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 4393 OPCODE_COMMON_SET_PROFILE_CONFIG, cmd.size, 4394 &wrb, &cmd); 4395 req->hdr.version = version; 4396 req->hdr.domain = domain; 4397 req->desc_count = cpu_to_le32(count); 4398 memcpy(req->desc, desc, size); 4399 4400 status = be_cmd_notify_wait(adapter, &wrb); 4401 4402 if (cmd.va) 4403 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, 4404 cmd.dma); 4405 return status; 4406 } 4407 4408 /* Mark all fields invalid */ 4409 static void be_reset_nic_desc(struct be_nic_res_desc *nic) 4410 { 4411 memset(nic, 0, sizeof(*nic)); 4412 nic->unicast_mac_count = 0xFFFF; 4413 nic->mcc_count = 0xFFFF; 4414 nic->vlan_count = 0xFFFF; 4415 nic->mcast_mac_count = 0xFFFF; 4416 nic->txq_count = 0xFFFF; 4417 nic->rq_count = 0xFFFF; 4418 nic->rssq_count = 0xFFFF; 4419 nic->lro_count = 0xFFFF; 4420 nic->cq_count = 0xFFFF; 4421 nic->toe_conn_count = 0xFFFF; 4422 nic->eq_count = 0xFFFF; 4423 nic->iface_count = 0xFFFF; 4424 nic->link_param = 0xFF; 4425 nic->channel_id_param = cpu_to_le16(0xF000); 4426 nic->acpi_params = 0xFF; 4427 nic->wol_param = 0x0F; 4428 nic->tunnel_iface_count = 0xFFFF; 4429 nic->direct_tenant_iface_count = 0xFFFF; 4430 nic->bw_min = 0xFFFFFFFF; 4431 nic->bw_max = 0xFFFFFFFF; 4432 } 4433 4434 /* Mark all fields invalid */ 4435 static void be_reset_pcie_desc(struct be_pcie_res_desc *pcie) 4436 { 4437 memset(pcie, 0, sizeof(*pcie)); 4438 pcie->sriov_state = 0xFF; 4439 pcie->pf_state = 0xFF; 4440 pcie->pf_type = 0xFF; 4441 pcie->num_vfs = 0xFFFF; 4442 } 4443 4444 int be_cmd_config_qos(struct be_adapter *adapter, u32 max_rate, u16 link_speed, 4445 u8 domain) 4446 { 4447 struct be_nic_res_desc nic_desc; 4448 u32 bw_percent; 4449 u16 version = 0; 4450 4451 if (BE3_chip(adapter)) 4452 return be_cmd_set_qos(adapter, max_rate / 10, domain); 4453 4454 be_reset_nic_desc(&nic_desc); 4455 nic_desc.pf_num = adapter->pf_num; 4456 nic_desc.vf_num = domain; 4457 nic_desc.bw_min = 0; 4458 if (lancer_chip(adapter)) { 4459 nic_desc.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V0; 4460 nic_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V0; 4461 nic_desc.flags = (1 << QUN_SHIFT) | (1 << IMM_SHIFT) | 4462 (1 << NOSV_SHIFT); 4463 nic_desc.bw_max = cpu_to_le32(max_rate / 10); 4464 } else { 4465 version = 1; 4466 nic_desc.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V1; 4467 nic_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V1; 4468 nic_desc.flags = (1 << IMM_SHIFT) | (1 << NOSV_SHIFT); 4469 bw_percent = max_rate ? (max_rate * 100) / link_speed : 100; 4470 nic_desc.bw_max = cpu_to_le32(bw_percent); 4471 } 4472 4473 return be_cmd_set_profile_config(adapter, &nic_desc, 4474 nic_desc.hdr.desc_len, 4475 1, version, domain); 4476 } 4477 4478 static void be_fill_vf_res_template(struct be_adapter *adapter, 4479 struct be_resources pool_res, 4480 u16 num_vfs, u16 num_vf_qs, 4481 struct be_nic_res_desc *nic_vft) 4482 { 4483 u32 vf_if_cap_flags = pool_res.vf_if_cap_flags; 4484 struct be_resources res_mod = {0}; 4485 4486 /* Resource with fields set to all '1's by GET_PROFILE_CONFIG cmd, 4487 * which are modifiable using SET_PROFILE_CONFIG cmd. 4488 */ 4489 be_cmd_get_profile_config(adapter, &res_mod, RESOURCE_MODIFIABLE, 0); 4490 4491 /* If RSS IFACE capability flags are modifiable for a VF, set the 4492 * capability flag as valid and set RSS and DEFQ_RSS IFACE flags if 4493 * more than 1 RSSQ is available for a VF. 4494 * Otherwise, provision only 1 queue pair for VF. 4495 */ 4496 if (res_mod.vf_if_cap_flags & BE_IF_FLAGS_RSS) { 4497 nic_vft->flags |= BIT(IF_CAPS_FLAGS_VALID_SHIFT); 4498 if (num_vf_qs > 1) { 4499 vf_if_cap_flags |= BE_IF_FLAGS_RSS; 4500 if (pool_res.if_cap_flags & BE_IF_FLAGS_DEFQ_RSS) 4501 vf_if_cap_flags |= BE_IF_FLAGS_DEFQ_RSS; 4502 } else { 4503 vf_if_cap_flags &= ~(BE_IF_FLAGS_RSS | 4504 BE_IF_FLAGS_DEFQ_RSS); 4505 } 4506 } else { 4507 num_vf_qs = 1; 4508 } 4509 4510 if (res_mod.vf_if_cap_flags & BE_IF_FLAGS_VLAN_PROMISCUOUS) { 4511 nic_vft->flags |= BIT(IF_CAPS_FLAGS_VALID_SHIFT); 4512 vf_if_cap_flags &= ~BE_IF_FLAGS_VLAN_PROMISCUOUS; 4513 } 4514 4515 nic_vft->cap_flags = cpu_to_le32(vf_if_cap_flags); 4516 nic_vft->rq_count = cpu_to_le16(num_vf_qs); 4517 nic_vft->txq_count = cpu_to_le16(num_vf_qs); 4518 nic_vft->rssq_count = cpu_to_le16(num_vf_qs); 4519 nic_vft->cq_count = cpu_to_le16(pool_res.max_cq_count / 4520 (num_vfs + 1)); 4521 4522 /* Distribute unicast MACs, VLANs, IFACE count and MCCQ count equally 4523 * among the PF and it's VFs, if the fields are changeable 4524 */ 4525 if (res_mod.max_uc_mac == FIELD_MODIFIABLE) 4526 nic_vft->unicast_mac_count = cpu_to_le16(pool_res.max_uc_mac / 4527 (num_vfs + 1)); 4528 4529 if (res_mod.max_vlans == FIELD_MODIFIABLE) 4530 nic_vft->vlan_count = cpu_to_le16(pool_res.max_vlans / 4531 (num_vfs + 1)); 4532 4533 if (res_mod.max_iface_count == FIELD_MODIFIABLE) 4534 nic_vft->iface_count = cpu_to_le16(pool_res.max_iface_count / 4535 (num_vfs + 1)); 4536 4537 if (res_mod.max_mcc_count == FIELD_MODIFIABLE) 4538 nic_vft->mcc_count = cpu_to_le16(pool_res.max_mcc_count / 4539 (num_vfs + 1)); 4540 } 4541 4542 int be_cmd_set_sriov_config(struct be_adapter *adapter, 4543 struct be_resources pool_res, u16 num_vfs, 4544 u16 num_vf_qs) 4545 { 4546 struct { 4547 struct be_pcie_res_desc pcie; 4548 struct be_nic_res_desc nic_vft; 4549 } __packed desc; 4550 4551 /* PF PCIE descriptor */ 4552 be_reset_pcie_desc(&desc.pcie); 4553 desc.pcie.hdr.desc_type = PCIE_RESOURCE_DESC_TYPE_V1; 4554 desc.pcie.hdr.desc_len = RESOURCE_DESC_SIZE_V1; 4555 desc.pcie.flags = BIT(IMM_SHIFT) | BIT(NOSV_SHIFT); 4556 desc.pcie.pf_num = adapter->pdev->devfn; 4557 desc.pcie.sriov_state = num_vfs ? 1 : 0; 4558 desc.pcie.num_vfs = cpu_to_le16(num_vfs); 4559 4560 /* VF NIC Template descriptor */ 4561 be_reset_nic_desc(&desc.nic_vft); 4562 desc.nic_vft.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V1; 4563 desc.nic_vft.hdr.desc_len = RESOURCE_DESC_SIZE_V1; 4564 desc.nic_vft.flags = BIT(VFT_SHIFT) | BIT(IMM_SHIFT) | BIT(NOSV_SHIFT); 4565 desc.nic_vft.pf_num = adapter->pdev->devfn; 4566 desc.nic_vft.vf_num = 0; 4567 4568 be_fill_vf_res_template(adapter, pool_res, num_vfs, num_vf_qs, 4569 &desc.nic_vft); 4570 4571 return be_cmd_set_profile_config(adapter, &desc, 4572 2 * RESOURCE_DESC_SIZE_V1, 2, 1, 0); 4573 } 4574 4575 int be_cmd_manage_iface(struct be_adapter *adapter, u32 iface, u8 op) 4576 { 4577 struct be_mcc_wrb *wrb; 4578 struct be_cmd_req_manage_iface_filters *req; 4579 int status; 4580 4581 if (iface == 0xFFFFFFFF) 4582 return -1; 4583 4584 spin_lock_bh(&adapter->mcc_lock); 4585 4586 wrb = wrb_from_mccq(adapter); 4587 if (!wrb) { 4588 status = -EBUSY; 4589 goto err; 4590 } 4591 req = embedded_payload(wrb); 4592 4593 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 4594 OPCODE_COMMON_MANAGE_IFACE_FILTERS, sizeof(*req), 4595 wrb, NULL); 4596 req->op = op; 4597 req->target_iface_id = cpu_to_le32(iface); 4598 4599 status = be_mcc_notify_wait(adapter); 4600 err: 4601 spin_unlock_bh(&adapter->mcc_lock); 4602 return status; 4603 } 4604 4605 int be_cmd_set_vxlan_port(struct be_adapter *adapter, __be16 port) 4606 { 4607 struct be_port_res_desc port_desc; 4608 4609 memset(&port_desc, 0, sizeof(port_desc)); 4610 port_desc.hdr.desc_type = PORT_RESOURCE_DESC_TYPE_V1; 4611 port_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V1; 4612 port_desc.flags = (1 << IMM_SHIFT) | (1 << NOSV_SHIFT); 4613 port_desc.link_num = adapter->hba_port_num; 4614 if (port) { 4615 port_desc.nv_flags = NV_TYPE_VXLAN | (1 << SOCVID_SHIFT) | 4616 (1 << RCVID_SHIFT); 4617 port_desc.nv_port = swab16(port); 4618 } else { 4619 port_desc.nv_flags = NV_TYPE_DISABLED; 4620 port_desc.nv_port = 0; 4621 } 4622 4623 return be_cmd_set_profile_config(adapter, &port_desc, 4624 RESOURCE_DESC_SIZE_V1, 1, 1, 0); 4625 } 4626 4627 int be_cmd_get_if_id(struct be_adapter *adapter, struct be_vf_cfg *vf_cfg, 4628 int vf_num) 4629 { 4630 struct be_mcc_wrb *wrb; 4631 struct be_cmd_req_get_iface_list *req; 4632 struct be_cmd_resp_get_iface_list *resp; 4633 int status; 4634 4635 spin_lock_bh(&adapter->mcc_lock); 4636 4637 wrb = wrb_from_mccq(adapter); 4638 if (!wrb) { 4639 status = -EBUSY; 4640 goto err; 4641 } 4642 req = embedded_payload(wrb); 4643 4644 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 4645 OPCODE_COMMON_GET_IFACE_LIST, sizeof(*resp), 4646 wrb, NULL); 4647 req->hdr.domain = vf_num + 1; 4648 4649 status = be_mcc_notify_wait(adapter); 4650 if (!status) { 4651 resp = (struct be_cmd_resp_get_iface_list *)req; 4652 vf_cfg->if_handle = le32_to_cpu(resp->if_desc.if_id); 4653 } 4654 4655 err: 4656 spin_unlock_bh(&adapter->mcc_lock); 4657 return status; 4658 } 4659 4660 static int lancer_wait_idle(struct be_adapter *adapter) 4661 { 4662 #define SLIPORT_IDLE_TIMEOUT 30 4663 u32 reg_val; 4664 int status = 0, i; 4665 4666 for (i = 0; i < SLIPORT_IDLE_TIMEOUT; i++) { 4667 reg_val = ioread32(adapter->db + PHYSDEV_CONTROL_OFFSET); 4668 if ((reg_val & PHYSDEV_CONTROL_INP_MASK) == 0) 4669 break; 4670 4671 ssleep(1); 4672 } 4673 4674 if (i == SLIPORT_IDLE_TIMEOUT) 4675 status = -1; 4676 4677 return status; 4678 } 4679 4680 int lancer_physdev_ctrl(struct be_adapter *adapter, u32 mask) 4681 { 4682 int status = 0; 4683 4684 status = lancer_wait_idle(adapter); 4685 if (status) 4686 return status; 4687 4688 iowrite32(mask, adapter->db + PHYSDEV_CONTROL_OFFSET); 4689 4690 return status; 4691 } 4692 4693 /* Routine to check whether dump image is present or not */ 4694 bool dump_present(struct be_adapter *adapter) 4695 { 4696 u32 sliport_status = 0; 4697 4698 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET); 4699 return !!(sliport_status & SLIPORT_STATUS_DIP_MASK); 4700 } 4701 4702 int lancer_initiate_dump(struct be_adapter *adapter) 4703 { 4704 struct device *dev = &adapter->pdev->dev; 4705 int status; 4706 4707 if (dump_present(adapter)) { 4708 dev_info(dev, "Previous dump not cleared, not forcing dump\n"); 4709 return -EEXIST; 4710 } 4711 4712 /* give firmware reset and diagnostic dump */ 4713 status = lancer_physdev_ctrl(adapter, PHYSDEV_CONTROL_FW_RESET_MASK | 4714 PHYSDEV_CONTROL_DD_MASK); 4715 if (status < 0) { 4716 dev_err(dev, "FW reset failed\n"); 4717 return status; 4718 } 4719 4720 status = lancer_wait_idle(adapter); 4721 if (status) 4722 return status; 4723 4724 if (!dump_present(adapter)) { 4725 dev_err(dev, "FW dump not generated\n"); 4726 return -EIO; 4727 } 4728 4729 return 0; 4730 } 4731 4732 int lancer_delete_dump(struct be_adapter *adapter) 4733 { 4734 int status; 4735 4736 status = lancer_cmd_delete_object(adapter, LANCER_FW_DUMP_FILE); 4737 return be_cmd_status(status); 4738 } 4739 4740 /* Uses sync mcc */ 4741 int be_cmd_enable_vf(struct be_adapter *adapter, u8 domain) 4742 { 4743 struct be_mcc_wrb *wrb; 4744 struct be_cmd_enable_disable_vf *req; 4745 int status; 4746 4747 if (BEx_chip(adapter)) 4748 return 0; 4749 4750 spin_lock_bh(&adapter->mcc_lock); 4751 4752 wrb = wrb_from_mccq(adapter); 4753 if (!wrb) { 4754 status = -EBUSY; 4755 goto err; 4756 } 4757 4758 req = embedded_payload(wrb); 4759 4760 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 4761 OPCODE_COMMON_ENABLE_DISABLE_VF, sizeof(*req), 4762 wrb, NULL); 4763 4764 req->hdr.domain = domain; 4765 req->enable = 1; 4766 status = be_mcc_notify_wait(adapter); 4767 err: 4768 spin_unlock_bh(&adapter->mcc_lock); 4769 return status; 4770 } 4771 4772 int be_cmd_intr_set(struct be_adapter *adapter, bool intr_enable) 4773 { 4774 struct be_mcc_wrb *wrb; 4775 struct be_cmd_req_intr_set *req; 4776 int status; 4777 4778 if (mutex_lock_interruptible(&adapter->mbox_lock)) 4779 return -1; 4780 4781 wrb = wrb_from_mbox(adapter); 4782 4783 req = embedded_payload(wrb); 4784 4785 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 4786 OPCODE_COMMON_SET_INTERRUPT_ENABLE, sizeof(*req), 4787 wrb, NULL); 4788 4789 req->intr_enabled = intr_enable; 4790 4791 status = be_mbox_notify_wait(adapter); 4792 4793 mutex_unlock(&adapter->mbox_lock); 4794 return status; 4795 } 4796 4797 /* Uses MBOX */ 4798 int be_cmd_get_active_profile(struct be_adapter *adapter, u16 *profile_id) 4799 { 4800 struct be_cmd_req_get_active_profile *req; 4801 struct be_mcc_wrb *wrb; 4802 int status; 4803 4804 if (mutex_lock_interruptible(&adapter->mbox_lock)) 4805 return -1; 4806 4807 wrb = wrb_from_mbox(adapter); 4808 if (!wrb) { 4809 status = -EBUSY; 4810 goto err; 4811 } 4812 4813 req = embedded_payload(wrb); 4814 4815 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 4816 OPCODE_COMMON_GET_ACTIVE_PROFILE, sizeof(*req), 4817 wrb, NULL); 4818 4819 status = be_mbox_notify_wait(adapter); 4820 if (!status) { 4821 struct be_cmd_resp_get_active_profile *resp = 4822 embedded_payload(wrb); 4823 4824 *profile_id = le16_to_cpu(resp->active_profile_id); 4825 } 4826 4827 err: 4828 mutex_unlock(&adapter->mbox_lock); 4829 return status; 4830 } 4831 4832 int __be_cmd_set_logical_link_config(struct be_adapter *adapter, 4833 int link_state, int version, u8 domain) 4834 { 4835 struct be_mcc_wrb *wrb; 4836 struct be_cmd_req_set_ll_link *req; 4837 int status; 4838 4839 spin_lock_bh(&adapter->mcc_lock); 4840 4841 wrb = wrb_from_mccq(adapter); 4842 if (!wrb) { 4843 status = -EBUSY; 4844 goto err; 4845 } 4846 4847 req = embedded_payload(wrb); 4848 4849 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 4850 OPCODE_COMMON_SET_LOGICAL_LINK_CONFIG, 4851 sizeof(*req), wrb, NULL); 4852 4853 req->hdr.version = version; 4854 req->hdr.domain = domain; 4855 4856 if (link_state == IFLA_VF_LINK_STATE_ENABLE || 4857 link_state == IFLA_VF_LINK_STATE_AUTO) 4858 req->link_config |= PLINK_ENABLE; 4859 4860 if (link_state == IFLA_VF_LINK_STATE_AUTO) 4861 req->link_config |= PLINK_TRACK; 4862 4863 status = be_mcc_notify_wait(adapter); 4864 err: 4865 spin_unlock_bh(&adapter->mcc_lock); 4866 return status; 4867 } 4868 4869 int be_cmd_set_logical_link_config(struct be_adapter *adapter, 4870 int link_state, u8 domain) 4871 { 4872 int status; 4873 4874 if (BEx_chip(adapter)) 4875 return -EOPNOTSUPP; 4876 4877 status = __be_cmd_set_logical_link_config(adapter, link_state, 4878 2, domain); 4879 4880 /* Version 2 of the command will not be recognized by older FW. 4881 * On such a failure issue version 1 of the command. 4882 */ 4883 if (base_status(status) == MCC_STATUS_ILLEGAL_REQUEST) 4884 status = __be_cmd_set_logical_link_config(adapter, link_state, 4885 1, domain); 4886 return status; 4887 } 4888 int be_roce_mcc_cmd(void *netdev_handle, void *wrb_payload, 4889 int wrb_payload_size, u16 *cmd_status, u16 *ext_status) 4890 { 4891 struct be_adapter *adapter = netdev_priv(netdev_handle); 4892 struct be_mcc_wrb *wrb; 4893 struct be_cmd_req_hdr *hdr = (struct be_cmd_req_hdr *)wrb_payload; 4894 struct be_cmd_req_hdr *req; 4895 struct be_cmd_resp_hdr *resp; 4896 int status; 4897 4898 spin_lock_bh(&adapter->mcc_lock); 4899 4900 wrb = wrb_from_mccq(adapter); 4901 if (!wrb) { 4902 status = -EBUSY; 4903 goto err; 4904 } 4905 req = embedded_payload(wrb); 4906 resp = embedded_payload(wrb); 4907 4908 be_wrb_cmd_hdr_prepare(req, hdr->subsystem, 4909 hdr->opcode, wrb_payload_size, wrb, NULL); 4910 memcpy(req, wrb_payload, wrb_payload_size); 4911 be_dws_cpu_to_le(req, wrb_payload_size); 4912 4913 status = be_mcc_notify_wait(adapter); 4914 if (cmd_status) 4915 *cmd_status = (status & 0xffff); 4916 if (ext_status) 4917 *ext_status = 0; 4918 memcpy(wrb_payload, resp, sizeof(*resp) + resp->response_length); 4919 be_dws_le_to_cpu(wrb_payload, sizeof(*resp) + resp->response_length); 4920 err: 4921 spin_unlock_bh(&adapter->mcc_lock); 4922 return status; 4923 } 4924 EXPORT_SYMBOL(be_roce_mcc_cmd); 4925