1 /* 2 * Copyright (C) 2005 - 2013 Emulex 3 * All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License version 2 7 * as published by the Free Software Foundation. The full GNU General 8 * Public License is included in this distribution in the file called COPYING. 9 * 10 * Contact Information: 11 * linux-drivers@emulex.com 12 * 13 * Emulex 14 * 3333 Susan Street 15 * Costa Mesa, CA 92626 16 */ 17 18 #include <linux/module.h> 19 #include "be.h" 20 #include "be_cmds.h" 21 22 static struct be_cmd_priv_map cmd_priv_map[] = { 23 { 24 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, 25 CMD_SUBSYSTEM_ETH, 26 BE_PRIV_LNKMGMT | BE_PRIV_VHADM | 27 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC 28 }, 29 { 30 OPCODE_COMMON_GET_FLOW_CONTROL, 31 CMD_SUBSYSTEM_COMMON, 32 BE_PRIV_LNKQUERY | BE_PRIV_VHADM | 33 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC 34 }, 35 { 36 OPCODE_COMMON_SET_FLOW_CONTROL, 37 CMD_SUBSYSTEM_COMMON, 38 BE_PRIV_LNKMGMT | BE_PRIV_VHADM | 39 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC 40 }, 41 { 42 OPCODE_ETH_GET_PPORT_STATS, 43 CMD_SUBSYSTEM_ETH, 44 BE_PRIV_LNKMGMT | BE_PRIV_VHADM | 45 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC 46 }, 47 { 48 OPCODE_COMMON_GET_PHY_DETAILS, 49 CMD_SUBSYSTEM_COMMON, 50 BE_PRIV_LNKMGMT | BE_PRIV_VHADM | 51 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC 52 } 53 }; 54 55 static bool be_cmd_allowed(struct be_adapter *adapter, u8 opcode, 56 u8 subsystem) 57 { 58 int i; 59 int num_entries = sizeof(cmd_priv_map)/sizeof(struct be_cmd_priv_map); 60 u32 cmd_privileges = adapter->cmd_privileges; 61 62 for (i = 0; i < num_entries; i++) 63 if (opcode == cmd_priv_map[i].opcode && 64 subsystem == cmd_priv_map[i].subsystem) 65 if (!(cmd_privileges & cmd_priv_map[i].priv_mask)) 66 return false; 67 68 return true; 69 } 70 71 static inline void *embedded_payload(struct be_mcc_wrb *wrb) 72 { 73 return wrb->payload.embedded_payload; 74 } 75 76 static void be_mcc_notify(struct be_adapter *adapter) 77 { 78 struct be_queue_info *mccq = &adapter->mcc_obj.q; 79 u32 val = 0; 80 81 if (be_error(adapter)) 82 return; 83 84 val |= mccq->id & DB_MCCQ_RING_ID_MASK; 85 val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT; 86 87 wmb(); 88 iowrite32(val, adapter->db + DB_MCCQ_OFFSET); 89 } 90 91 /* To check if valid bit is set, check the entire word as we don't know 92 * the endianness of the data (old entry is host endian while a new entry is 93 * little endian) */ 94 static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl) 95 { 96 u32 flags; 97 98 if (compl->flags != 0) { 99 flags = le32_to_cpu(compl->flags); 100 if (flags & CQE_FLAGS_VALID_MASK) { 101 compl->flags = flags; 102 return true; 103 } 104 } 105 return false; 106 } 107 108 /* Need to reset the entire word that houses the valid bit */ 109 static inline void be_mcc_compl_use(struct be_mcc_compl *compl) 110 { 111 compl->flags = 0; 112 } 113 114 static struct be_cmd_resp_hdr *be_decode_resp_hdr(u32 tag0, u32 tag1) 115 { 116 unsigned long addr; 117 118 addr = tag1; 119 addr = ((addr << 16) << 16) | tag0; 120 return (void *)addr; 121 } 122 123 static int be_mcc_compl_process(struct be_adapter *adapter, 124 struct be_mcc_compl *compl) 125 { 126 u16 compl_status, extd_status; 127 struct be_cmd_resp_hdr *resp_hdr; 128 u8 opcode = 0, subsystem = 0; 129 130 /* Just swap the status to host endian; mcc tag is opaquely copied 131 * from mcc_wrb */ 132 be_dws_le_to_cpu(compl, 4); 133 134 compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) & 135 CQE_STATUS_COMPL_MASK; 136 137 resp_hdr = be_decode_resp_hdr(compl->tag0, compl->tag1); 138 139 if (resp_hdr) { 140 opcode = resp_hdr->opcode; 141 subsystem = resp_hdr->subsystem; 142 } 143 144 if (((opcode == OPCODE_COMMON_WRITE_FLASHROM) || 145 (opcode == OPCODE_COMMON_WRITE_OBJECT)) && 146 (subsystem == CMD_SUBSYSTEM_COMMON)) { 147 adapter->flash_status = compl_status; 148 complete(&adapter->flash_compl); 149 } 150 151 if (compl_status == MCC_STATUS_SUCCESS) { 152 if (((opcode == OPCODE_ETH_GET_STATISTICS) || 153 (opcode == OPCODE_ETH_GET_PPORT_STATS)) && 154 (subsystem == CMD_SUBSYSTEM_ETH)) { 155 be_parse_stats(adapter); 156 adapter->stats_cmd_sent = false; 157 } 158 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES && 159 subsystem == CMD_SUBSYSTEM_COMMON) { 160 struct be_cmd_resp_get_cntl_addnl_attribs *resp = 161 (void *)resp_hdr; 162 adapter->drv_stats.be_on_die_temperature = 163 resp->on_die_temperature; 164 } 165 } else { 166 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES) 167 adapter->be_get_temp_freq = 0; 168 169 if (compl_status == MCC_STATUS_NOT_SUPPORTED || 170 compl_status == MCC_STATUS_ILLEGAL_REQUEST) 171 goto done; 172 173 if (compl_status == MCC_STATUS_UNAUTHORIZED_REQUEST) { 174 dev_warn(&adapter->pdev->dev, 175 "VF is not privileged to issue opcode %d-%d\n", 176 opcode, subsystem); 177 } else { 178 extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) & 179 CQE_STATUS_EXTD_MASK; 180 dev_err(&adapter->pdev->dev, 181 "opcode %d-%d failed:status %d-%d\n", 182 opcode, subsystem, compl_status, extd_status); 183 184 if (extd_status == MCC_ADDL_STS_INSUFFICIENT_RESOURCES) 185 return extd_status; 186 } 187 } 188 done: 189 return compl_status; 190 } 191 192 /* Link state evt is a string of bytes; no need for endian swapping */ 193 static void be_async_link_state_process(struct be_adapter *adapter, 194 struct be_async_event_link_state *evt) 195 { 196 /* When link status changes, link speed must be re-queried from FW */ 197 adapter->phy.link_speed = -1; 198 199 /* Ignore physical link event */ 200 if (lancer_chip(adapter) && 201 !(evt->port_link_status & LOGICAL_LINK_STATUS_MASK)) 202 return; 203 204 /* For the initial link status do not rely on the ASYNC event as 205 * it may not be received in some cases. 206 */ 207 if (adapter->flags & BE_FLAGS_LINK_STATUS_INIT) 208 be_link_status_update(adapter, evt->port_link_status); 209 } 210 211 /* Grp5 CoS Priority evt */ 212 static void be_async_grp5_cos_priority_process(struct be_adapter *adapter, 213 struct be_async_event_grp5_cos_priority *evt) 214 { 215 if (evt->valid) { 216 adapter->vlan_prio_bmap = evt->available_priority_bmap; 217 adapter->recommended_prio &= ~VLAN_PRIO_MASK; 218 adapter->recommended_prio = 219 evt->reco_default_priority << VLAN_PRIO_SHIFT; 220 } 221 } 222 223 /* Grp5 QOS Speed evt: qos_link_speed is in units of 10 Mbps */ 224 static void be_async_grp5_qos_speed_process(struct be_adapter *adapter, 225 struct be_async_event_grp5_qos_link_speed *evt) 226 { 227 if (adapter->phy.link_speed >= 0 && 228 evt->physical_port == adapter->port_num) 229 adapter->phy.link_speed = le16_to_cpu(evt->qos_link_speed) * 10; 230 } 231 232 /*Grp5 PVID evt*/ 233 static void be_async_grp5_pvid_state_process(struct be_adapter *adapter, 234 struct be_async_event_grp5_pvid_state *evt) 235 { 236 if (evt->enabled) 237 adapter->pvid = le16_to_cpu(evt->tag) & VLAN_VID_MASK; 238 else 239 adapter->pvid = 0; 240 } 241 242 static void be_async_grp5_evt_process(struct be_adapter *adapter, 243 u32 trailer, struct be_mcc_compl *evt) 244 { 245 u8 event_type = 0; 246 247 event_type = (trailer >> ASYNC_TRAILER_EVENT_TYPE_SHIFT) & 248 ASYNC_TRAILER_EVENT_TYPE_MASK; 249 250 switch (event_type) { 251 case ASYNC_EVENT_COS_PRIORITY: 252 be_async_grp5_cos_priority_process(adapter, 253 (struct be_async_event_grp5_cos_priority *)evt); 254 break; 255 case ASYNC_EVENT_QOS_SPEED: 256 be_async_grp5_qos_speed_process(adapter, 257 (struct be_async_event_grp5_qos_link_speed *)evt); 258 break; 259 case ASYNC_EVENT_PVID_STATE: 260 be_async_grp5_pvid_state_process(adapter, 261 (struct be_async_event_grp5_pvid_state *)evt); 262 break; 263 default: 264 dev_warn(&adapter->pdev->dev, "Unknown grp5 event 0x%x!\n", 265 event_type); 266 break; 267 } 268 } 269 270 static void be_async_dbg_evt_process(struct be_adapter *adapter, 271 u32 trailer, struct be_mcc_compl *cmp) 272 { 273 u8 event_type = 0; 274 struct be_async_event_qnq *evt = (struct be_async_event_qnq *) cmp; 275 276 event_type = (trailer >> ASYNC_TRAILER_EVENT_TYPE_SHIFT) & 277 ASYNC_TRAILER_EVENT_TYPE_MASK; 278 279 switch (event_type) { 280 case ASYNC_DEBUG_EVENT_TYPE_QNQ: 281 if (evt->valid) 282 adapter->qnq_vid = le16_to_cpu(evt->vlan_tag); 283 adapter->flags |= BE_FLAGS_QNQ_ASYNC_EVT_RCVD; 284 break; 285 default: 286 dev_warn(&adapter->pdev->dev, "Unknown debug event 0x%x!\n", 287 event_type); 288 break; 289 } 290 } 291 292 static inline bool is_link_state_evt(u32 trailer) 293 { 294 return ((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) & 295 ASYNC_TRAILER_EVENT_CODE_MASK) == 296 ASYNC_EVENT_CODE_LINK_STATE; 297 } 298 299 static inline bool is_grp5_evt(u32 trailer) 300 { 301 return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) & 302 ASYNC_TRAILER_EVENT_CODE_MASK) == 303 ASYNC_EVENT_CODE_GRP_5); 304 } 305 306 static inline bool is_dbg_evt(u32 trailer) 307 { 308 return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) & 309 ASYNC_TRAILER_EVENT_CODE_MASK) == 310 ASYNC_EVENT_CODE_QNQ); 311 } 312 313 static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter) 314 { 315 struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq; 316 struct be_mcc_compl *compl = queue_tail_node(mcc_cq); 317 318 if (be_mcc_compl_is_new(compl)) { 319 queue_tail_inc(mcc_cq); 320 return compl; 321 } 322 return NULL; 323 } 324 325 void be_async_mcc_enable(struct be_adapter *adapter) 326 { 327 spin_lock_bh(&adapter->mcc_cq_lock); 328 329 be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0); 330 adapter->mcc_obj.rearm_cq = true; 331 332 spin_unlock_bh(&adapter->mcc_cq_lock); 333 } 334 335 void be_async_mcc_disable(struct be_adapter *adapter) 336 { 337 spin_lock_bh(&adapter->mcc_cq_lock); 338 339 adapter->mcc_obj.rearm_cq = false; 340 be_cq_notify(adapter, adapter->mcc_obj.cq.id, false, 0); 341 342 spin_unlock_bh(&adapter->mcc_cq_lock); 343 } 344 345 int be_process_mcc(struct be_adapter *adapter) 346 { 347 struct be_mcc_compl *compl; 348 int num = 0, status = 0; 349 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj; 350 351 spin_lock(&adapter->mcc_cq_lock); 352 while ((compl = be_mcc_compl_get(adapter))) { 353 if (compl->flags & CQE_FLAGS_ASYNC_MASK) { 354 /* Interpret flags as an async trailer */ 355 if (is_link_state_evt(compl->flags)) 356 be_async_link_state_process(adapter, 357 (struct be_async_event_link_state *) compl); 358 else if (is_grp5_evt(compl->flags)) 359 be_async_grp5_evt_process(adapter, 360 compl->flags, compl); 361 else if (is_dbg_evt(compl->flags)) 362 be_async_dbg_evt_process(adapter, 363 compl->flags, compl); 364 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) { 365 status = be_mcc_compl_process(adapter, compl); 366 atomic_dec(&mcc_obj->q.used); 367 } 368 be_mcc_compl_use(compl); 369 num++; 370 } 371 372 if (num) 373 be_cq_notify(adapter, mcc_obj->cq.id, mcc_obj->rearm_cq, num); 374 375 spin_unlock(&adapter->mcc_cq_lock); 376 return status; 377 } 378 379 /* Wait till no more pending mcc requests are present */ 380 static int be_mcc_wait_compl(struct be_adapter *adapter) 381 { 382 #define mcc_timeout 120000 /* 12s timeout */ 383 int i, status = 0; 384 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj; 385 386 for (i = 0; i < mcc_timeout; i++) { 387 if (be_error(adapter)) 388 return -EIO; 389 390 local_bh_disable(); 391 status = be_process_mcc(adapter); 392 local_bh_enable(); 393 394 if (atomic_read(&mcc_obj->q.used) == 0) 395 break; 396 udelay(100); 397 } 398 if (i == mcc_timeout) { 399 dev_err(&adapter->pdev->dev, "FW not responding\n"); 400 adapter->fw_timeout = true; 401 return -EIO; 402 } 403 return status; 404 } 405 406 /* Notify MCC requests and wait for completion */ 407 static int be_mcc_notify_wait(struct be_adapter *adapter) 408 { 409 int status; 410 struct be_mcc_wrb *wrb; 411 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj; 412 u16 index = mcc_obj->q.head; 413 struct be_cmd_resp_hdr *resp; 414 415 index_dec(&index, mcc_obj->q.len); 416 wrb = queue_index_node(&mcc_obj->q, index); 417 418 resp = be_decode_resp_hdr(wrb->tag0, wrb->tag1); 419 420 be_mcc_notify(adapter); 421 422 status = be_mcc_wait_compl(adapter); 423 if (status == -EIO) 424 goto out; 425 426 status = resp->status; 427 out: 428 return status; 429 } 430 431 static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db) 432 { 433 int msecs = 0; 434 u32 ready; 435 436 do { 437 if (be_error(adapter)) 438 return -EIO; 439 440 ready = ioread32(db); 441 if (ready == 0xffffffff) 442 return -1; 443 444 ready &= MPU_MAILBOX_DB_RDY_MASK; 445 if (ready) 446 break; 447 448 if (msecs > 4000) { 449 dev_err(&adapter->pdev->dev, "FW not responding\n"); 450 adapter->fw_timeout = true; 451 be_detect_error(adapter); 452 return -1; 453 } 454 455 msleep(1); 456 msecs++; 457 } while (true); 458 459 return 0; 460 } 461 462 /* 463 * Insert the mailbox address into the doorbell in two steps 464 * Polls on the mbox doorbell till a command completion (or a timeout) occurs 465 */ 466 static int be_mbox_notify_wait(struct be_adapter *adapter) 467 { 468 int status; 469 u32 val = 0; 470 void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET; 471 struct be_dma_mem *mbox_mem = &adapter->mbox_mem; 472 struct be_mcc_mailbox *mbox = mbox_mem->va; 473 struct be_mcc_compl *compl = &mbox->compl; 474 475 /* wait for ready to be set */ 476 status = be_mbox_db_ready_wait(adapter, db); 477 if (status != 0) 478 return status; 479 480 val |= MPU_MAILBOX_DB_HI_MASK; 481 /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */ 482 val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2; 483 iowrite32(val, db); 484 485 /* wait for ready to be set */ 486 status = be_mbox_db_ready_wait(adapter, db); 487 if (status != 0) 488 return status; 489 490 val = 0; 491 /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */ 492 val |= (u32)(mbox_mem->dma >> 4) << 2; 493 iowrite32(val, db); 494 495 status = be_mbox_db_ready_wait(adapter, db); 496 if (status != 0) 497 return status; 498 499 /* A cq entry has been made now */ 500 if (be_mcc_compl_is_new(compl)) { 501 status = be_mcc_compl_process(adapter, &mbox->compl); 502 be_mcc_compl_use(compl); 503 if (status) 504 return status; 505 } else { 506 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n"); 507 return -1; 508 } 509 return 0; 510 } 511 512 static u16 be_POST_stage_get(struct be_adapter *adapter) 513 { 514 u32 sem; 515 516 if (BEx_chip(adapter)) 517 sem = ioread32(adapter->csr + SLIPORT_SEMAPHORE_OFFSET_BEx); 518 else 519 pci_read_config_dword(adapter->pdev, 520 SLIPORT_SEMAPHORE_OFFSET_SH, &sem); 521 522 return sem & POST_STAGE_MASK; 523 } 524 525 static int lancer_wait_ready(struct be_adapter *adapter) 526 { 527 #define SLIPORT_READY_TIMEOUT 30 528 u32 sliport_status; 529 int status = 0, i; 530 531 for (i = 0; i < SLIPORT_READY_TIMEOUT; i++) { 532 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET); 533 if (sliport_status & SLIPORT_STATUS_RDY_MASK) 534 break; 535 536 msleep(1000); 537 } 538 539 if (i == SLIPORT_READY_TIMEOUT) 540 status = -1; 541 542 return status; 543 } 544 545 static bool lancer_provisioning_error(struct be_adapter *adapter) 546 { 547 u32 sliport_status = 0, sliport_err1 = 0, sliport_err2 = 0; 548 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET); 549 if (sliport_status & SLIPORT_STATUS_ERR_MASK) { 550 sliport_err1 = ioread32(adapter->db + 551 SLIPORT_ERROR1_OFFSET); 552 sliport_err2 = ioread32(adapter->db + 553 SLIPORT_ERROR2_OFFSET); 554 555 if (sliport_err1 == SLIPORT_ERROR_NO_RESOURCE1 && 556 sliport_err2 == SLIPORT_ERROR_NO_RESOURCE2) 557 return true; 558 } 559 return false; 560 } 561 562 int lancer_test_and_set_rdy_state(struct be_adapter *adapter) 563 { 564 int status; 565 u32 sliport_status, err, reset_needed; 566 bool resource_error; 567 568 resource_error = lancer_provisioning_error(adapter); 569 if (resource_error) 570 return -EAGAIN; 571 572 status = lancer_wait_ready(adapter); 573 if (!status) { 574 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET); 575 err = sliport_status & SLIPORT_STATUS_ERR_MASK; 576 reset_needed = sliport_status & SLIPORT_STATUS_RN_MASK; 577 if (err && reset_needed) { 578 iowrite32(SLI_PORT_CONTROL_IP_MASK, 579 adapter->db + SLIPORT_CONTROL_OFFSET); 580 581 /* check adapter has corrected the error */ 582 status = lancer_wait_ready(adapter); 583 sliport_status = ioread32(adapter->db + 584 SLIPORT_STATUS_OFFSET); 585 sliport_status &= (SLIPORT_STATUS_ERR_MASK | 586 SLIPORT_STATUS_RN_MASK); 587 if (status || sliport_status) 588 status = -1; 589 } else if (err || reset_needed) { 590 status = -1; 591 } 592 } 593 /* Stop error recovery if error is not recoverable. 594 * No resource error is temporary errors and will go away 595 * when PF provisions resources. 596 */ 597 resource_error = lancer_provisioning_error(adapter); 598 if (resource_error) 599 status = -EAGAIN; 600 601 return status; 602 } 603 604 int be_fw_wait_ready(struct be_adapter *adapter) 605 { 606 u16 stage; 607 int status, timeout = 0; 608 struct device *dev = &adapter->pdev->dev; 609 610 if (lancer_chip(adapter)) { 611 status = lancer_wait_ready(adapter); 612 return status; 613 } 614 615 do { 616 stage = be_POST_stage_get(adapter); 617 if (stage == POST_STAGE_ARMFW_RDY) 618 return 0; 619 620 dev_info(dev, "Waiting for POST, %ds elapsed\n", 621 timeout); 622 if (msleep_interruptible(2000)) { 623 dev_err(dev, "Waiting for POST aborted\n"); 624 return -EINTR; 625 } 626 timeout += 2; 627 } while (timeout < 60); 628 629 dev_err(dev, "POST timeout; stage=0x%x\n", stage); 630 return -1; 631 } 632 633 634 static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb) 635 { 636 return &wrb->payload.sgl[0]; 637 } 638 639 static inline void fill_wrb_tags(struct be_mcc_wrb *wrb, 640 unsigned long addr) 641 { 642 wrb->tag0 = addr & 0xFFFFFFFF; 643 wrb->tag1 = upper_32_bits(addr); 644 } 645 646 /* Don't touch the hdr after it's prepared */ 647 /* mem will be NULL for embedded commands */ 648 static void be_wrb_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr, 649 u8 subsystem, u8 opcode, int cmd_len, 650 struct be_mcc_wrb *wrb, struct be_dma_mem *mem) 651 { 652 struct be_sge *sge; 653 654 req_hdr->opcode = opcode; 655 req_hdr->subsystem = subsystem; 656 req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr)); 657 req_hdr->version = 0; 658 fill_wrb_tags(wrb, (ulong) req_hdr); 659 wrb->payload_length = cmd_len; 660 if (mem) { 661 wrb->embedded |= (1 & MCC_WRB_SGE_CNT_MASK) << 662 MCC_WRB_SGE_CNT_SHIFT; 663 sge = nonembedded_sgl(wrb); 664 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma)); 665 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF); 666 sge->len = cpu_to_le32(mem->size); 667 } else 668 wrb->embedded |= MCC_WRB_EMBEDDED_MASK; 669 be_dws_cpu_to_le(wrb, 8); 670 } 671 672 static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages, 673 struct be_dma_mem *mem) 674 { 675 int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages); 676 u64 dma = (u64)mem->dma; 677 678 for (i = 0; i < buf_pages; i++) { 679 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF); 680 pages[i].hi = cpu_to_le32(upper_32_bits(dma)); 681 dma += PAGE_SIZE_4K; 682 } 683 } 684 685 static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter) 686 { 687 struct be_dma_mem *mbox_mem = &adapter->mbox_mem; 688 struct be_mcc_wrb *wrb 689 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb; 690 memset(wrb, 0, sizeof(*wrb)); 691 return wrb; 692 } 693 694 static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter) 695 { 696 struct be_queue_info *mccq = &adapter->mcc_obj.q; 697 struct be_mcc_wrb *wrb; 698 699 if (!mccq->created) 700 return NULL; 701 702 if (atomic_read(&mccq->used) >= mccq->len) 703 return NULL; 704 705 wrb = queue_head_node(mccq); 706 queue_head_inc(mccq); 707 atomic_inc(&mccq->used); 708 memset(wrb, 0, sizeof(*wrb)); 709 return wrb; 710 } 711 712 static bool use_mcc(struct be_adapter *adapter) 713 { 714 return adapter->mcc_obj.q.created; 715 } 716 717 /* Must be used only in process context */ 718 static int be_cmd_lock(struct be_adapter *adapter) 719 { 720 if (use_mcc(adapter)) { 721 spin_lock_bh(&adapter->mcc_lock); 722 return 0; 723 } else { 724 return mutex_lock_interruptible(&adapter->mbox_lock); 725 } 726 } 727 728 /* Must be used only in process context */ 729 static void be_cmd_unlock(struct be_adapter *adapter) 730 { 731 if (use_mcc(adapter)) 732 spin_unlock_bh(&adapter->mcc_lock); 733 else 734 return mutex_unlock(&adapter->mbox_lock); 735 } 736 737 static struct be_mcc_wrb *be_cmd_copy(struct be_adapter *adapter, 738 struct be_mcc_wrb *wrb) 739 { 740 struct be_mcc_wrb *dest_wrb; 741 742 if (use_mcc(adapter)) { 743 dest_wrb = wrb_from_mccq(adapter); 744 if (!dest_wrb) 745 return NULL; 746 } else { 747 dest_wrb = wrb_from_mbox(adapter); 748 } 749 750 memcpy(dest_wrb, wrb, sizeof(*wrb)); 751 if (wrb->embedded & cpu_to_le32(MCC_WRB_EMBEDDED_MASK)) 752 fill_wrb_tags(dest_wrb, (ulong) embedded_payload(wrb)); 753 754 return dest_wrb; 755 } 756 757 /* Must be used only in process context */ 758 static int be_cmd_notify_wait(struct be_adapter *adapter, 759 struct be_mcc_wrb *wrb) 760 { 761 struct be_mcc_wrb *dest_wrb; 762 int status; 763 764 status = be_cmd_lock(adapter); 765 if (status) 766 return status; 767 768 dest_wrb = be_cmd_copy(adapter, wrb); 769 if (!dest_wrb) 770 return -EBUSY; 771 772 if (use_mcc(adapter)) 773 status = be_mcc_notify_wait(adapter); 774 else 775 status = be_mbox_notify_wait(adapter); 776 777 if (!status) 778 memcpy(wrb, dest_wrb, sizeof(*wrb)); 779 780 be_cmd_unlock(adapter); 781 return status; 782 } 783 784 /* Tell fw we're about to start firing cmds by writing a 785 * special pattern across the wrb hdr; uses mbox 786 */ 787 int be_cmd_fw_init(struct be_adapter *adapter) 788 { 789 u8 *wrb; 790 int status; 791 792 if (lancer_chip(adapter)) 793 return 0; 794 795 if (mutex_lock_interruptible(&adapter->mbox_lock)) 796 return -1; 797 798 wrb = (u8 *)wrb_from_mbox(adapter); 799 *wrb++ = 0xFF; 800 *wrb++ = 0x12; 801 *wrb++ = 0x34; 802 *wrb++ = 0xFF; 803 *wrb++ = 0xFF; 804 *wrb++ = 0x56; 805 *wrb++ = 0x78; 806 *wrb = 0xFF; 807 808 status = be_mbox_notify_wait(adapter); 809 810 mutex_unlock(&adapter->mbox_lock); 811 return status; 812 } 813 814 /* Tell fw we're done with firing cmds by writing a 815 * special pattern across the wrb hdr; uses mbox 816 */ 817 int be_cmd_fw_clean(struct be_adapter *adapter) 818 { 819 u8 *wrb; 820 int status; 821 822 if (lancer_chip(adapter)) 823 return 0; 824 825 if (mutex_lock_interruptible(&adapter->mbox_lock)) 826 return -1; 827 828 wrb = (u8 *)wrb_from_mbox(adapter); 829 *wrb++ = 0xFF; 830 *wrb++ = 0xAA; 831 *wrb++ = 0xBB; 832 *wrb++ = 0xFF; 833 *wrb++ = 0xFF; 834 *wrb++ = 0xCC; 835 *wrb++ = 0xDD; 836 *wrb = 0xFF; 837 838 status = be_mbox_notify_wait(adapter); 839 840 mutex_unlock(&adapter->mbox_lock); 841 return status; 842 } 843 844 int be_cmd_eq_create(struct be_adapter *adapter, struct be_eq_obj *eqo) 845 { 846 struct be_mcc_wrb *wrb; 847 struct be_cmd_req_eq_create *req; 848 struct be_dma_mem *q_mem = &eqo->q.dma_mem; 849 int status, ver = 0; 850 851 if (mutex_lock_interruptible(&adapter->mbox_lock)) 852 return -1; 853 854 wrb = wrb_from_mbox(adapter); 855 req = embedded_payload(wrb); 856 857 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 858 OPCODE_COMMON_EQ_CREATE, sizeof(*req), wrb, NULL); 859 860 /* Support for EQ_CREATEv2 available only SH-R onwards */ 861 if (!(BEx_chip(adapter) || lancer_chip(adapter))) 862 ver = 2; 863 864 req->hdr.version = ver; 865 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size)); 866 867 AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1); 868 /* 4byte eqe*/ 869 AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0); 870 AMAP_SET_BITS(struct amap_eq_context, count, req->context, 871 __ilog2_u32(eqo->q.len / 256)); 872 be_dws_cpu_to_le(req->context, sizeof(req->context)); 873 874 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); 875 876 status = be_mbox_notify_wait(adapter); 877 if (!status) { 878 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb); 879 eqo->q.id = le16_to_cpu(resp->eq_id); 880 eqo->msix_idx = 881 (ver == 2) ? le16_to_cpu(resp->msix_idx) : eqo->idx; 882 eqo->q.created = true; 883 } 884 885 mutex_unlock(&adapter->mbox_lock); 886 return status; 887 } 888 889 /* Use MCC */ 890 int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr, 891 bool permanent, u32 if_handle, u32 pmac_id) 892 { 893 struct be_mcc_wrb *wrb; 894 struct be_cmd_req_mac_query *req; 895 int status; 896 897 spin_lock_bh(&adapter->mcc_lock); 898 899 wrb = wrb_from_mccq(adapter); 900 if (!wrb) { 901 status = -EBUSY; 902 goto err; 903 } 904 req = embedded_payload(wrb); 905 906 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 907 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req), wrb, NULL); 908 req->type = MAC_ADDRESS_TYPE_NETWORK; 909 if (permanent) { 910 req->permanent = 1; 911 } else { 912 req->if_id = cpu_to_le16((u16) if_handle); 913 req->pmac_id = cpu_to_le32(pmac_id); 914 req->permanent = 0; 915 } 916 917 status = be_mcc_notify_wait(adapter); 918 if (!status) { 919 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb); 920 memcpy(mac_addr, resp->mac.addr, ETH_ALEN); 921 } 922 923 err: 924 spin_unlock_bh(&adapter->mcc_lock); 925 return status; 926 } 927 928 /* Uses synchronous MCCQ */ 929 int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr, 930 u32 if_id, u32 *pmac_id, u32 domain) 931 { 932 struct be_mcc_wrb *wrb; 933 struct be_cmd_req_pmac_add *req; 934 int status; 935 936 spin_lock_bh(&adapter->mcc_lock); 937 938 wrb = wrb_from_mccq(adapter); 939 if (!wrb) { 940 status = -EBUSY; 941 goto err; 942 } 943 req = embedded_payload(wrb); 944 945 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 946 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req), wrb, NULL); 947 948 req->hdr.domain = domain; 949 req->if_id = cpu_to_le32(if_id); 950 memcpy(req->mac_address, mac_addr, ETH_ALEN); 951 952 status = be_mcc_notify_wait(adapter); 953 if (!status) { 954 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb); 955 *pmac_id = le32_to_cpu(resp->pmac_id); 956 } 957 958 err: 959 spin_unlock_bh(&adapter->mcc_lock); 960 961 if (status == MCC_STATUS_UNAUTHORIZED_REQUEST) 962 status = -EPERM; 963 964 return status; 965 } 966 967 /* Uses synchronous MCCQ */ 968 int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, int pmac_id, u32 dom) 969 { 970 struct be_mcc_wrb *wrb; 971 struct be_cmd_req_pmac_del *req; 972 int status; 973 974 if (pmac_id == -1) 975 return 0; 976 977 spin_lock_bh(&adapter->mcc_lock); 978 979 wrb = wrb_from_mccq(adapter); 980 if (!wrb) { 981 status = -EBUSY; 982 goto err; 983 } 984 req = embedded_payload(wrb); 985 986 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 987 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req), wrb, NULL); 988 989 req->hdr.domain = dom; 990 req->if_id = cpu_to_le32(if_id); 991 req->pmac_id = cpu_to_le32(pmac_id); 992 993 status = be_mcc_notify_wait(adapter); 994 995 err: 996 spin_unlock_bh(&adapter->mcc_lock); 997 return status; 998 } 999 1000 /* Uses Mbox */ 1001 int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq, 1002 struct be_queue_info *eq, bool no_delay, int coalesce_wm) 1003 { 1004 struct be_mcc_wrb *wrb; 1005 struct be_cmd_req_cq_create *req; 1006 struct be_dma_mem *q_mem = &cq->dma_mem; 1007 void *ctxt; 1008 int status; 1009 1010 if (mutex_lock_interruptible(&adapter->mbox_lock)) 1011 return -1; 1012 1013 wrb = wrb_from_mbox(adapter); 1014 req = embedded_payload(wrb); 1015 ctxt = &req->context; 1016 1017 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1018 OPCODE_COMMON_CQ_CREATE, sizeof(*req), wrb, NULL); 1019 1020 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size)); 1021 1022 if (BEx_chip(adapter)) { 1023 AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt, 1024 coalesce_wm); 1025 AMAP_SET_BITS(struct amap_cq_context_be, nodelay, 1026 ctxt, no_delay); 1027 AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt, 1028 __ilog2_u32(cq->len/256)); 1029 AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1); 1030 AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1); 1031 AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id); 1032 } else { 1033 req->hdr.version = 2; 1034 req->page_size = 1; /* 1 for 4K */ 1035 AMAP_SET_BITS(struct amap_cq_context_v2, nodelay, ctxt, 1036 no_delay); 1037 AMAP_SET_BITS(struct amap_cq_context_v2, count, ctxt, 1038 __ilog2_u32(cq->len/256)); 1039 AMAP_SET_BITS(struct amap_cq_context_v2, valid, ctxt, 1); 1040 AMAP_SET_BITS(struct amap_cq_context_v2, eventable, 1041 ctxt, 1); 1042 AMAP_SET_BITS(struct amap_cq_context_v2, eqid, 1043 ctxt, eq->id); 1044 } 1045 1046 be_dws_cpu_to_le(ctxt, sizeof(req->context)); 1047 1048 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); 1049 1050 status = be_mbox_notify_wait(adapter); 1051 if (!status) { 1052 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb); 1053 cq->id = le16_to_cpu(resp->cq_id); 1054 cq->created = true; 1055 } 1056 1057 mutex_unlock(&adapter->mbox_lock); 1058 1059 return status; 1060 } 1061 1062 static u32 be_encoded_q_len(int q_len) 1063 { 1064 u32 len_encoded = fls(q_len); /* log2(len) + 1 */ 1065 if (len_encoded == 16) 1066 len_encoded = 0; 1067 return len_encoded; 1068 } 1069 1070 static int be_cmd_mccq_ext_create(struct be_adapter *adapter, 1071 struct be_queue_info *mccq, 1072 struct be_queue_info *cq) 1073 { 1074 struct be_mcc_wrb *wrb; 1075 struct be_cmd_req_mcc_ext_create *req; 1076 struct be_dma_mem *q_mem = &mccq->dma_mem; 1077 void *ctxt; 1078 int status; 1079 1080 if (mutex_lock_interruptible(&adapter->mbox_lock)) 1081 return -1; 1082 1083 wrb = wrb_from_mbox(adapter); 1084 req = embedded_payload(wrb); 1085 ctxt = &req->context; 1086 1087 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1088 OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req), wrb, NULL); 1089 1090 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size)); 1091 if (lancer_chip(adapter)) { 1092 req->hdr.version = 1; 1093 req->cq_id = cpu_to_le16(cq->id); 1094 1095 AMAP_SET_BITS(struct amap_mcc_context_lancer, ring_size, ctxt, 1096 be_encoded_q_len(mccq->len)); 1097 AMAP_SET_BITS(struct amap_mcc_context_lancer, valid, ctxt, 1); 1098 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_id, 1099 ctxt, cq->id); 1100 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_valid, 1101 ctxt, 1); 1102 1103 } else { 1104 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1); 1105 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt, 1106 be_encoded_q_len(mccq->len)); 1107 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id); 1108 } 1109 1110 /* Subscribe to Link State and Group 5 Events(bits 1 and 5 set) */ 1111 req->async_event_bitmap[0] = cpu_to_le32(0x00000022); 1112 req->async_event_bitmap[0] |= cpu_to_le32(1 << ASYNC_EVENT_CODE_QNQ); 1113 be_dws_cpu_to_le(ctxt, sizeof(req->context)); 1114 1115 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); 1116 1117 status = be_mbox_notify_wait(adapter); 1118 if (!status) { 1119 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb); 1120 mccq->id = le16_to_cpu(resp->id); 1121 mccq->created = true; 1122 } 1123 mutex_unlock(&adapter->mbox_lock); 1124 1125 return status; 1126 } 1127 1128 static int be_cmd_mccq_org_create(struct be_adapter *adapter, 1129 struct be_queue_info *mccq, 1130 struct be_queue_info *cq) 1131 { 1132 struct be_mcc_wrb *wrb; 1133 struct be_cmd_req_mcc_create *req; 1134 struct be_dma_mem *q_mem = &mccq->dma_mem; 1135 void *ctxt; 1136 int status; 1137 1138 if (mutex_lock_interruptible(&adapter->mbox_lock)) 1139 return -1; 1140 1141 wrb = wrb_from_mbox(adapter); 1142 req = embedded_payload(wrb); 1143 ctxt = &req->context; 1144 1145 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1146 OPCODE_COMMON_MCC_CREATE, sizeof(*req), wrb, NULL); 1147 1148 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size)); 1149 1150 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1); 1151 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt, 1152 be_encoded_q_len(mccq->len)); 1153 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id); 1154 1155 be_dws_cpu_to_le(ctxt, sizeof(req->context)); 1156 1157 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); 1158 1159 status = be_mbox_notify_wait(adapter); 1160 if (!status) { 1161 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb); 1162 mccq->id = le16_to_cpu(resp->id); 1163 mccq->created = true; 1164 } 1165 1166 mutex_unlock(&adapter->mbox_lock); 1167 return status; 1168 } 1169 1170 int be_cmd_mccq_create(struct be_adapter *adapter, 1171 struct be_queue_info *mccq, 1172 struct be_queue_info *cq) 1173 { 1174 int status; 1175 1176 status = be_cmd_mccq_ext_create(adapter, mccq, cq); 1177 if (status && !lancer_chip(adapter)) { 1178 dev_warn(&adapter->pdev->dev, "Upgrade to F/W ver 2.102.235.0 " 1179 "or newer to avoid conflicting priorities between NIC " 1180 "and FCoE traffic"); 1181 status = be_cmd_mccq_org_create(adapter, mccq, cq); 1182 } 1183 return status; 1184 } 1185 1186 int be_cmd_txq_create(struct be_adapter *adapter, struct be_tx_obj *txo) 1187 { 1188 struct be_mcc_wrb wrb = {0}; 1189 struct be_cmd_req_eth_tx_create *req; 1190 struct be_queue_info *txq = &txo->q; 1191 struct be_queue_info *cq = &txo->cq; 1192 struct be_dma_mem *q_mem = &txq->dma_mem; 1193 int status, ver = 0; 1194 1195 req = embedded_payload(&wrb); 1196 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, 1197 OPCODE_ETH_TX_CREATE, sizeof(*req), &wrb, NULL); 1198 1199 if (lancer_chip(adapter)) { 1200 req->hdr.version = 1; 1201 } else if (BEx_chip(adapter)) { 1202 if (adapter->function_caps & BE_FUNCTION_CAPS_SUPER_NIC) 1203 req->hdr.version = 2; 1204 } else { /* For SH */ 1205 req->hdr.version = 2; 1206 } 1207 1208 if (req->hdr.version > 0) 1209 req->if_id = cpu_to_le16(adapter->if_handle); 1210 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size); 1211 req->ulp_num = BE_ULP1_NUM; 1212 req->type = BE_ETH_TX_RING_TYPE_STANDARD; 1213 req->cq_id = cpu_to_le16(cq->id); 1214 req->queue_size = be_encoded_q_len(txq->len); 1215 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); 1216 ver = req->hdr.version; 1217 1218 status = be_cmd_notify_wait(adapter, &wrb); 1219 if (!status) { 1220 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(&wrb); 1221 txq->id = le16_to_cpu(resp->cid); 1222 if (ver == 2) 1223 txo->db_offset = le32_to_cpu(resp->db_offset); 1224 else 1225 txo->db_offset = DB_TXULP1_OFFSET; 1226 txq->created = true; 1227 } 1228 1229 return status; 1230 } 1231 1232 /* Uses MCC */ 1233 int be_cmd_rxq_create(struct be_adapter *adapter, 1234 struct be_queue_info *rxq, u16 cq_id, u16 frag_size, 1235 u32 if_id, u32 rss, u8 *rss_id) 1236 { 1237 struct be_mcc_wrb *wrb; 1238 struct be_cmd_req_eth_rx_create *req; 1239 struct be_dma_mem *q_mem = &rxq->dma_mem; 1240 int status; 1241 1242 spin_lock_bh(&adapter->mcc_lock); 1243 1244 wrb = wrb_from_mccq(adapter); 1245 if (!wrb) { 1246 status = -EBUSY; 1247 goto err; 1248 } 1249 req = embedded_payload(wrb); 1250 1251 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, 1252 OPCODE_ETH_RX_CREATE, sizeof(*req), wrb, NULL); 1253 1254 req->cq_id = cpu_to_le16(cq_id); 1255 req->frag_size = fls(frag_size) - 1; 1256 req->num_pages = 2; 1257 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); 1258 req->interface_id = cpu_to_le32(if_id); 1259 req->max_frame_size = cpu_to_le16(BE_MAX_JUMBO_FRAME_SIZE); 1260 req->rss_queue = cpu_to_le32(rss); 1261 1262 status = be_mcc_notify_wait(adapter); 1263 if (!status) { 1264 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb); 1265 rxq->id = le16_to_cpu(resp->id); 1266 rxq->created = true; 1267 *rss_id = resp->rss_id; 1268 } 1269 1270 err: 1271 spin_unlock_bh(&adapter->mcc_lock); 1272 return status; 1273 } 1274 1275 /* Generic destroyer function for all types of queues 1276 * Uses Mbox 1277 */ 1278 int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q, 1279 int queue_type) 1280 { 1281 struct be_mcc_wrb *wrb; 1282 struct be_cmd_req_q_destroy *req; 1283 u8 subsys = 0, opcode = 0; 1284 int status; 1285 1286 if (mutex_lock_interruptible(&adapter->mbox_lock)) 1287 return -1; 1288 1289 wrb = wrb_from_mbox(adapter); 1290 req = embedded_payload(wrb); 1291 1292 switch (queue_type) { 1293 case QTYPE_EQ: 1294 subsys = CMD_SUBSYSTEM_COMMON; 1295 opcode = OPCODE_COMMON_EQ_DESTROY; 1296 break; 1297 case QTYPE_CQ: 1298 subsys = CMD_SUBSYSTEM_COMMON; 1299 opcode = OPCODE_COMMON_CQ_DESTROY; 1300 break; 1301 case QTYPE_TXQ: 1302 subsys = CMD_SUBSYSTEM_ETH; 1303 opcode = OPCODE_ETH_TX_DESTROY; 1304 break; 1305 case QTYPE_RXQ: 1306 subsys = CMD_SUBSYSTEM_ETH; 1307 opcode = OPCODE_ETH_RX_DESTROY; 1308 break; 1309 case QTYPE_MCCQ: 1310 subsys = CMD_SUBSYSTEM_COMMON; 1311 opcode = OPCODE_COMMON_MCC_DESTROY; 1312 break; 1313 default: 1314 BUG(); 1315 } 1316 1317 be_wrb_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req), wrb, 1318 NULL); 1319 req->id = cpu_to_le16(q->id); 1320 1321 status = be_mbox_notify_wait(adapter); 1322 q->created = false; 1323 1324 mutex_unlock(&adapter->mbox_lock); 1325 return status; 1326 } 1327 1328 /* Uses MCC */ 1329 int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q) 1330 { 1331 struct be_mcc_wrb *wrb; 1332 struct be_cmd_req_q_destroy *req; 1333 int status; 1334 1335 spin_lock_bh(&adapter->mcc_lock); 1336 1337 wrb = wrb_from_mccq(adapter); 1338 if (!wrb) { 1339 status = -EBUSY; 1340 goto err; 1341 } 1342 req = embedded_payload(wrb); 1343 1344 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, 1345 OPCODE_ETH_RX_DESTROY, sizeof(*req), wrb, NULL); 1346 req->id = cpu_to_le16(q->id); 1347 1348 status = be_mcc_notify_wait(adapter); 1349 q->created = false; 1350 1351 err: 1352 spin_unlock_bh(&adapter->mcc_lock); 1353 return status; 1354 } 1355 1356 /* Create an rx filtering policy configuration on an i/f 1357 * Will use MBOX only if MCCQ has not been created. 1358 */ 1359 int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags, 1360 u32 *if_handle, u32 domain) 1361 { 1362 struct be_mcc_wrb wrb = {0}; 1363 struct be_cmd_req_if_create *req; 1364 int status; 1365 1366 req = embedded_payload(&wrb); 1367 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1368 OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req), &wrb, NULL); 1369 req->hdr.domain = domain; 1370 req->capability_flags = cpu_to_le32(cap_flags); 1371 req->enable_flags = cpu_to_le32(en_flags); 1372 req->pmac_invalid = true; 1373 1374 status = be_cmd_notify_wait(adapter, &wrb); 1375 if (!status) { 1376 struct be_cmd_resp_if_create *resp = embedded_payload(&wrb); 1377 *if_handle = le32_to_cpu(resp->interface_id); 1378 1379 /* Hack to retrieve VF's pmac-id on BE3 */ 1380 if (BE3_chip(adapter) && !be_physfn(adapter)) 1381 adapter->pmac_id[0] = le32_to_cpu(resp->pmac_id); 1382 } 1383 return status; 1384 } 1385 1386 /* Uses MCCQ */ 1387 int be_cmd_if_destroy(struct be_adapter *adapter, int interface_id, u32 domain) 1388 { 1389 struct be_mcc_wrb *wrb; 1390 struct be_cmd_req_if_destroy *req; 1391 int status; 1392 1393 if (interface_id == -1) 1394 return 0; 1395 1396 spin_lock_bh(&adapter->mcc_lock); 1397 1398 wrb = wrb_from_mccq(adapter); 1399 if (!wrb) { 1400 status = -EBUSY; 1401 goto err; 1402 } 1403 req = embedded_payload(wrb); 1404 1405 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1406 OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req), wrb, NULL); 1407 req->hdr.domain = domain; 1408 req->interface_id = cpu_to_le32(interface_id); 1409 1410 status = be_mcc_notify_wait(adapter); 1411 err: 1412 spin_unlock_bh(&adapter->mcc_lock); 1413 return status; 1414 } 1415 1416 /* Get stats is a non embedded command: the request is not embedded inside 1417 * WRB but is a separate dma memory block 1418 * Uses asynchronous MCC 1419 */ 1420 int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd) 1421 { 1422 struct be_mcc_wrb *wrb; 1423 struct be_cmd_req_hdr *hdr; 1424 int status = 0; 1425 1426 spin_lock_bh(&adapter->mcc_lock); 1427 1428 wrb = wrb_from_mccq(adapter); 1429 if (!wrb) { 1430 status = -EBUSY; 1431 goto err; 1432 } 1433 hdr = nonemb_cmd->va; 1434 1435 be_wrb_cmd_hdr_prepare(hdr, CMD_SUBSYSTEM_ETH, 1436 OPCODE_ETH_GET_STATISTICS, nonemb_cmd->size, wrb, nonemb_cmd); 1437 1438 /* version 1 of the cmd is not supported only by BE2 */ 1439 if (BE2_chip(adapter)) 1440 hdr->version = 0; 1441 if (BE3_chip(adapter) || lancer_chip(adapter)) 1442 hdr->version = 1; 1443 else 1444 hdr->version = 2; 1445 1446 be_mcc_notify(adapter); 1447 adapter->stats_cmd_sent = true; 1448 1449 err: 1450 spin_unlock_bh(&adapter->mcc_lock); 1451 return status; 1452 } 1453 1454 /* Lancer Stats */ 1455 int lancer_cmd_get_pport_stats(struct be_adapter *adapter, 1456 struct be_dma_mem *nonemb_cmd) 1457 { 1458 1459 struct be_mcc_wrb *wrb; 1460 struct lancer_cmd_req_pport_stats *req; 1461 int status = 0; 1462 1463 if (!be_cmd_allowed(adapter, OPCODE_ETH_GET_PPORT_STATS, 1464 CMD_SUBSYSTEM_ETH)) 1465 return -EPERM; 1466 1467 spin_lock_bh(&adapter->mcc_lock); 1468 1469 wrb = wrb_from_mccq(adapter); 1470 if (!wrb) { 1471 status = -EBUSY; 1472 goto err; 1473 } 1474 req = nonemb_cmd->va; 1475 1476 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, 1477 OPCODE_ETH_GET_PPORT_STATS, nonemb_cmd->size, wrb, 1478 nonemb_cmd); 1479 1480 req->cmd_params.params.pport_num = cpu_to_le16(adapter->hba_port_num); 1481 req->cmd_params.params.reset_stats = 0; 1482 1483 be_mcc_notify(adapter); 1484 adapter->stats_cmd_sent = true; 1485 1486 err: 1487 spin_unlock_bh(&adapter->mcc_lock); 1488 return status; 1489 } 1490 1491 static int be_mac_to_link_speed(int mac_speed) 1492 { 1493 switch (mac_speed) { 1494 case PHY_LINK_SPEED_ZERO: 1495 return 0; 1496 case PHY_LINK_SPEED_10MBPS: 1497 return 10; 1498 case PHY_LINK_SPEED_100MBPS: 1499 return 100; 1500 case PHY_LINK_SPEED_1GBPS: 1501 return 1000; 1502 case PHY_LINK_SPEED_10GBPS: 1503 return 10000; 1504 case PHY_LINK_SPEED_20GBPS: 1505 return 20000; 1506 case PHY_LINK_SPEED_25GBPS: 1507 return 25000; 1508 case PHY_LINK_SPEED_40GBPS: 1509 return 40000; 1510 } 1511 return 0; 1512 } 1513 1514 /* Uses synchronous mcc 1515 * Returns link_speed in Mbps 1516 */ 1517 int be_cmd_link_status_query(struct be_adapter *adapter, u16 *link_speed, 1518 u8 *link_status, u32 dom) 1519 { 1520 struct be_mcc_wrb *wrb; 1521 struct be_cmd_req_link_status *req; 1522 int status; 1523 1524 spin_lock_bh(&adapter->mcc_lock); 1525 1526 if (link_status) 1527 *link_status = LINK_DOWN; 1528 1529 wrb = wrb_from_mccq(adapter); 1530 if (!wrb) { 1531 status = -EBUSY; 1532 goto err; 1533 } 1534 req = embedded_payload(wrb); 1535 1536 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1537 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req), wrb, NULL); 1538 1539 /* version 1 of the cmd is not supported only by BE2 */ 1540 if (!BE2_chip(adapter)) 1541 req->hdr.version = 1; 1542 1543 req->hdr.domain = dom; 1544 1545 status = be_mcc_notify_wait(adapter); 1546 if (!status) { 1547 struct be_cmd_resp_link_status *resp = embedded_payload(wrb); 1548 if (link_speed) { 1549 *link_speed = resp->link_speed ? 1550 le16_to_cpu(resp->link_speed) * 10 : 1551 be_mac_to_link_speed(resp->mac_speed); 1552 1553 if (!resp->logical_link_status) 1554 *link_speed = 0; 1555 } 1556 if (link_status) 1557 *link_status = resp->logical_link_status; 1558 } 1559 1560 err: 1561 spin_unlock_bh(&adapter->mcc_lock); 1562 return status; 1563 } 1564 1565 /* Uses synchronous mcc */ 1566 int be_cmd_get_die_temperature(struct be_adapter *adapter) 1567 { 1568 struct be_mcc_wrb *wrb; 1569 struct be_cmd_req_get_cntl_addnl_attribs *req; 1570 int status = 0; 1571 1572 spin_lock_bh(&adapter->mcc_lock); 1573 1574 wrb = wrb_from_mccq(adapter); 1575 if (!wrb) { 1576 status = -EBUSY; 1577 goto err; 1578 } 1579 req = embedded_payload(wrb); 1580 1581 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1582 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES, sizeof(*req), 1583 wrb, NULL); 1584 1585 be_mcc_notify(adapter); 1586 1587 err: 1588 spin_unlock_bh(&adapter->mcc_lock); 1589 return status; 1590 } 1591 1592 /* Uses synchronous mcc */ 1593 int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size) 1594 { 1595 struct be_mcc_wrb *wrb; 1596 struct be_cmd_req_get_fat *req; 1597 int status; 1598 1599 spin_lock_bh(&adapter->mcc_lock); 1600 1601 wrb = wrb_from_mccq(adapter); 1602 if (!wrb) { 1603 status = -EBUSY; 1604 goto err; 1605 } 1606 req = embedded_payload(wrb); 1607 1608 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1609 OPCODE_COMMON_MANAGE_FAT, sizeof(*req), wrb, NULL); 1610 req->fat_operation = cpu_to_le32(QUERY_FAT); 1611 status = be_mcc_notify_wait(adapter); 1612 if (!status) { 1613 struct be_cmd_resp_get_fat *resp = embedded_payload(wrb); 1614 if (log_size && resp->log_size) 1615 *log_size = le32_to_cpu(resp->log_size) - 1616 sizeof(u32); 1617 } 1618 err: 1619 spin_unlock_bh(&adapter->mcc_lock); 1620 return status; 1621 } 1622 1623 void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf) 1624 { 1625 struct be_dma_mem get_fat_cmd; 1626 struct be_mcc_wrb *wrb; 1627 struct be_cmd_req_get_fat *req; 1628 u32 offset = 0, total_size, buf_size, 1629 log_offset = sizeof(u32), payload_len; 1630 int status; 1631 1632 if (buf_len == 0) 1633 return; 1634 1635 total_size = buf_len; 1636 1637 get_fat_cmd.size = sizeof(struct be_cmd_req_get_fat) + 60*1024; 1638 get_fat_cmd.va = pci_alloc_consistent(adapter->pdev, 1639 get_fat_cmd.size, 1640 &get_fat_cmd.dma); 1641 if (!get_fat_cmd.va) { 1642 status = -ENOMEM; 1643 dev_err(&adapter->pdev->dev, 1644 "Memory allocation failure while retrieving FAT data\n"); 1645 return; 1646 } 1647 1648 spin_lock_bh(&adapter->mcc_lock); 1649 1650 while (total_size) { 1651 buf_size = min(total_size, (u32)60*1024); 1652 total_size -= buf_size; 1653 1654 wrb = wrb_from_mccq(adapter); 1655 if (!wrb) { 1656 status = -EBUSY; 1657 goto err; 1658 } 1659 req = get_fat_cmd.va; 1660 1661 payload_len = sizeof(struct be_cmd_req_get_fat) + buf_size; 1662 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1663 OPCODE_COMMON_MANAGE_FAT, payload_len, wrb, 1664 &get_fat_cmd); 1665 1666 req->fat_operation = cpu_to_le32(RETRIEVE_FAT); 1667 req->read_log_offset = cpu_to_le32(log_offset); 1668 req->read_log_length = cpu_to_le32(buf_size); 1669 req->data_buffer_size = cpu_to_le32(buf_size); 1670 1671 status = be_mcc_notify_wait(adapter); 1672 if (!status) { 1673 struct be_cmd_resp_get_fat *resp = get_fat_cmd.va; 1674 memcpy(buf + offset, 1675 resp->data_buffer, 1676 le32_to_cpu(resp->read_log_length)); 1677 } else { 1678 dev_err(&adapter->pdev->dev, "FAT Table Retrieve error\n"); 1679 goto err; 1680 } 1681 offset += buf_size; 1682 log_offset += buf_size; 1683 } 1684 err: 1685 pci_free_consistent(adapter->pdev, get_fat_cmd.size, 1686 get_fat_cmd.va, 1687 get_fat_cmd.dma); 1688 spin_unlock_bh(&adapter->mcc_lock); 1689 } 1690 1691 /* Uses synchronous mcc */ 1692 int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver, 1693 char *fw_on_flash) 1694 { 1695 struct be_mcc_wrb *wrb; 1696 struct be_cmd_req_get_fw_version *req; 1697 int status; 1698 1699 spin_lock_bh(&adapter->mcc_lock); 1700 1701 wrb = wrb_from_mccq(adapter); 1702 if (!wrb) { 1703 status = -EBUSY; 1704 goto err; 1705 } 1706 1707 req = embedded_payload(wrb); 1708 1709 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1710 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req), wrb, NULL); 1711 status = be_mcc_notify_wait(adapter); 1712 if (!status) { 1713 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb); 1714 strcpy(fw_ver, resp->firmware_version_string); 1715 if (fw_on_flash) 1716 strcpy(fw_on_flash, resp->fw_on_flash_version_string); 1717 } 1718 err: 1719 spin_unlock_bh(&adapter->mcc_lock); 1720 return status; 1721 } 1722 1723 /* set the EQ delay interval of an EQ to specified value 1724 * Uses async mcc 1725 */ 1726 int be_cmd_modify_eqd(struct be_adapter *adapter, struct be_set_eqd *set_eqd, 1727 int num) 1728 { 1729 struct be_mcc_wrb *wrb; 1730 struct be_cmd_req_modify_eq_delay *req; 1731 int status = 0, i; 1732 1733 spin_lock_bh(&adapter->mcc_lock); 1734 1735 wrb = wrb_from_mccq(adapter); 1736 if (!wrb) { 1737 status = -EBUSY; 1738 goto err; 1739 } 1740 req = embedded_payload(wrb); 1741 1742 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1743 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req), wrb, NULL); 1744 1745 req->num_eq = cpu_to_le32(num); 1746 for (i = 0; i < num; i++) { 1747 req->set_eqd[i].eq_id = cpu_to_le32(set_eqd[i].eq_id); 1748 req->set_eqd[i].phase = 0; 1749 req->set_eqd[i].delay_multiplier = 1750 cpu_to_le32(set_eqd[i].delay_multiplier); 1751 } 1752 1753 be_mcc_notify(adapter); 1754 err: 1755 spin_unlock_bh(&adapter->mcc_lock); 1756 return status; 1757 } 1758 1759 /* Uses sycnhronous mcc */ 1760 int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array, 1761 u32 num, bool promiscuous) 1762 { 1763 struct be_mcc_wrb *wrb; 1764 struct be_cmd_req_vlan_config *req; 1765 int status; 1766 1767 spin_lock_bh(&adapter->mcc_lock); 1768 1769 wrb = wrb_from_mccq(adapter); 1770 if (!wrb) { 1771 status = -EBUSY; 1772 goto err; 1773 } 1774 req = embedded_payload(wrb); 1775 1776 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1777 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req), wrb, NULL); 1778 1779 req->interface_id = if_id; 1780 req->promiscuous = promiscuous; 1781 req->untagged = BE_IF_FLAGS_UNTAGGED & be_if_cap_flags(adapter) ? 1 : 0; 1782 req->num_vlan = num; 1783 if (!promiscuous) { 1784 memcpy(req->normal_vlan, vtag_array, 1785 req->num_vlan * sizeof(vtag_array[0])); 1786 } 1787 1788 status = be_mcc_notify_wait(adapter); 1789 1790 err: 1791 spin_unlock_bh(&adapter->mcc_lock); 1792 return status; 1793 } 1794 1795 int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value) 1796 { 1797 struct be_mcc_wrb *wrb; 1798 struct be_dma_mem *mem = &adapter->rx_filter; 1799 struct be_cmd_req_rx_filter *req = mem->va; 1800 int status; 1801 1802 spin_lock_bh(&adapter->mcc_lock); 1803 1804 wrb = wrb_from_mccq(adapter); 1805 if (!wrb) { 1806 status = -EBUSY; 1807 goto err; 1808 } 1809 memset(req, 0, sizeof(*req)); 1810 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1811 OPCODE_COMMON_NTWK_RX_FILTER, sizeof(*req), 1812 wrb, mem); 1813 1814 req->if_id = cpu_to_le32(adapter->if_handle); 1815 if (flags & IFF_PROMISC) { 1816 req->if_flags_mask = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS | 1817 BE_IF_FLAGS_VLAN_PROMISCUOUS | 1818 BE_IF_FLAGS_MCAST_PROMISCUOUS); 1819 if (value == ON) 1820 req->if_flags = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS | 1821 BE_IF_FLAGS_VLAN_PROMISCUOUS | 1822 BE_IF_FLAGS_MCAST_PROMISCUOUS); 1823 } else if (flags & IFF_ALLMULTI) { 1824 req->if_flags_mask = req->if_flags = 1825 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS); 1826 } else if (flags & BE_FLAGS_VLAN_PROMISC) { 1827 req->if_flags_mask = cpu_to_le32(BE_IF_FLAGS_VLAN_PROMISCUOUS); 1828 1829 if (value == ON) 1830 req->if_flags = 1831 cpu_to_le32(BE_IF_FLAGS_VLAN_PROMISCUOUS); 1832 } else { 1833 struct netdev_hw_addr *ha; 1834 int i = 0; 1835 1836 req->if_flags_mask = req->if_flags = 1837 cpu_to_le32(BE_IF_FLAGS_MULTICAST); 1838 1839 /* Reset mcast promisc mode if already set by setting mask 1840 * and not setting flags field 1841 */ 1842 req->if_flags_mask |= 1843 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS & 1844 be_if_cap_flags(adapter)); 1845 req->mcast_num = cpu_to_le32(netdev_mc_count(adapter->netdev)); 1846 netdev_for_each_mc_addr(ha, adapter->netdev) 1847 memcpy(req->mcast_mac[i++].byte, ha->addr, ETH_ALEN); 1848 } 1849 1850 if ((req->if_flags_mask & cpu_to_le32(be_if_cap_flags(adapter))) != 1851 req->if_flags_mask) { 1852 dev_warn(&adapter->pdev->dev, 1853 "Cannot set rx filter flags 0x%x\n", 1854 req->if_flags_mask); 1855 dev_warn(&adapter->pdev->dev, 1856 "Interface is capable of 0x%x flags only\n", 1857 be_if_cap_flags(adapter)); 1858 } 1859 req->if_flags_mask &= cpu_to_le32(be_if_cap_flags(adapter)); 1860 1861 status = be_mcc_notify_wait(adapter); 1862 1863 err: 1864 spin_unlock_bh(&adapter->mcc_lock); 1865 return status; 1866 } 1867 1868 /* Uses synchrounous mcc */ 1869 int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc) 1870 { 1871 struct be_mcc_wrb *wrb; 1872 struct be_cmd_req_set_flow_control *req; 1873 int status; 1874 1875 if (!be_cmd_allowed(adapter, OPCODE_COMMON_SET_FLOW_CONTROL, 1876 CMD_SUBSYSTEM_COMMON)) 1877 return -EPERM; 1878 1879 spin_lock_bh(&adapter->mcc_lock); 1880 1881 wrb = wrb_from_mccq(adapter); 1882 if (!wrb) { 1883 status = -EBUSY; 1884 goto err; 1885 } 1886 req = embedded_payload(wrb); 1887 1888 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1889 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req), wrb, NULL); 1890 1891 req->tx_flow_control = cpu_to_le16((u16)tx_fc); 1892 req->rx_flow_control = cpu_to_le16((u16)rx_fc); 1893 1894 status = be_mcc_notify_wait(adapter); 1895 1896 err: 1897 spin_unlock_bh(&adapter->mcc_lock); 1898 return status; 1899 } 1900 1901 /* Uses sycn mcc */ 1902 int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc) 1903 { 1904 struct be_mcc_wrb *wrb; 1905 struct be_cmd_req_get_flow_control *req; 1906 int status; 1907 1908 if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_FLOW_CONTROL, 1909 CMD_SUBSYSTEM_COMMON)) 1910 return -EPERM; 1911 1912 spin_lock_bh(&adapter->mcc_lock); 1913 1914 wrb = wrb_from_mccq(adapter); 1915 if (!wrb) { 1916 status = -EBUSY; 1917 goto err; 1918 } 1919 req = embedded_payload(wrb); 1920 1921 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1922 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req), wrb, NULL); 1923 1924 status = be_mcc_notify_wait(adapter); 1925 if (!status) { 1926 struct be_cmd_resp_get_flow_control *resp = 1927 embedded_payload(wrb); 1928 *tx_fc = le16_to_cpu(resp->tx_flow_control); 1929 *rx_fc = le16_to_cpu(resp->rx_flow_control); 1930 } 1931 1932 err: 1933 spin_unlock_bh(&adapter->mcc_lock); 1934 return status; 1935 } 1936 1937 /* Uses mbox */ 1938 int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num, 1939 u32 *mode, u32 *caps, u16 *asic_rev) 1940 { 1941 struct be_mcc_wrb *wrb; 1942 struct be_cmd_req_query_fw_cfg *req; 1943 int status; 1944 1945 if (mutex_lock_interruptible(&adapter->mbox_lock)) 1946 return -1; 1947 1948 wrb = wrb_from_mbox(adapter); 1949 req = embedded_payload(wrb); 1950 1951 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1952 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req), wrb, NULL); 1953 1954 status = be_mbox_notify_wait(adapter); 1955 if (!status) { 1956 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb); 1957 *port_num = le32_to_cpu(resp->phys_port); 1958 *mode = le32_to_cpu(resp->function_mode); 1959 *caps = le32_to_cpu(resp->function_caps); 1960 *asic_rev = le32_to_cpu(resp->asic_revision) & 0xFF; 1961 } 1962 1963 mutex_unlock(&adapter->mbox_lock); 1964 return status; 1965 } 1966 1967 /* Uses mbox */ 1968 int be_cmd_reset_function(struct be_adapter *adapter) 1969 { 1970 struct be_mcc_wrb *wrb; 1971 struct be_cmd_req_hdr *req; 1972 int status; 1973 1974 if (lancer_chip(adapter)) { 1975 status = lancer_wait_ready(adapter); 1976 if (!status) { 1977 iowrite32(SLI_PORT_CONTROL_IP_MASK, 1978 adapter->db + SLIPORT_CONTROL_OFFSET); 1979 status = lancer_test_and_set_rdy_state(adapter); 1980 } 1981 if (status) { 1982 dev_err(&adapter->pdev->dev, 1983 "Adapter in non recoverable error\n"); 1984 } 1985 return status; 1986 } 1987 1988 if (mutex_lock_interruptible(&adapter->mbox_lock)) 1989 return -1; 1990 1991 wrb = wrb_from_mbox(adapter); 1992 req = embedded_payload(wrb); 1993 1994 be_wrb_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON, 1995 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req), wrb, NULL); 1996 1997 status = be_mbox_notify_wait(adapter); 1998 1999 mutex_unlock(&adapter->mbox_lock); 2000 return status; 2001 } 2002 2003 int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable, 2004 u32 rss_hash_opts, u16 table_size) 2005 { 2006 struct be_mcc_wrb *wrb; 2007 struct be_cmd_req_rss_config *req; 2008 u32 myhash[10] = {0x15d43fa5, 0x2534685a, 0x5f87693a, 0x5668494e, 2009 0x33cf6a53, 0x383334c6, 0x76ac4257, 0x59b242b2, 2010 0x3ea83c02, 0x4a110304}; 2011 int status; 2012 2013 if (mutex_lock_interruptible(&adapter->mbox_lock)) 2014 return -1; 2015 2016 wrb = wrb_from_mbox(adapter); 2017 req = embedded_payload(wrb); 2018 2019 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, 2020 OPCODE_ETH_RSS_CONFIG, sizeof(*req), wrb, NULL); 2021 2022 req->if_id = cpu_to_le32(adapter->if_handle); 2023 req->enable_rss = cpu_to_le16(rss_hash_opts); 2024 req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1); 2025 2026 if (lancer_chip(adapter) || skyhawk_chip(adapter)) 2027 req->hdr.version = 1; 2028 2029 memcpy(req->cpu_table, rsstable, table_size); 2030 memcpy(req->hash, myhash, sizeof(myhash)); 2031 be_dws_cpu_to_le(req->hash, sizeof(req->hash)); 2032 2033 status = be_mbox_notify_wait(adapter); 2034 2035 mutex_unlock(&adapter->mbox_lock); 2036 return status; 2037 } 2038 2039 /* Uses sync mcc */ 2040 int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num, 2041 u8 bcn, u8 sts, u8 state) 2042 { 2043 struct be_mcc_wrb *wrb; 2044 struct be_cmd_req_enable_disable_beacon *req; 2045 int status; 2046 2047 spin_lock_bh(&adapter->mcc_lock); 2048 2049 wrb = wrb_from_mccq(adapter); 2050 if (!wrb) { 2051 status = -EBUSY; 2052 goto err; 2053 } 2054 req = embedded_payload(wrb); 2055 2056 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2057 OPCODE_COMMON_ENABLE_DISABLE_BEACON, sizeof(*req), wrb, NULL); 2058 2059 req->port_num = port_num; 2060 req->beacon_state = state; 2061 req->beacon_duration = bcn; 2062 req->status_duration = sts; 2063 2064 status = be_mcc_notify_wait(adapter); 2065 2066 err: 2067 spin_unlock_bh(&adapter->mcc_lock); 2068 return status; 2069 } 2070 2071 /* Uses sync mcc */ 2072 int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state) 2073 { 2074 struct be_mcc_wrb *wrb; 2075 struct be_cmd_req_get_beacon_state *req; 2076 int status; 2077 2078 spin_lock_bh(&adapter->mcc_lock); 2079 2080 wrb = wrb_from_mccq(adapter); 2081 if (!wrb) { 2082 status = -EBUSY; 2083 goto err; 2084 } 2085 req = embedded_payload(wrb); 2086 2087 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2088 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req), wrb, NULL); 2089 2090 req->port_num = port_num; 2091 2092 status = be_mcc_notify_wait(adapter); 2093 if (!status) { 2094 struct be_cmd_resp_get_beacon_state *resp = 2095 embedded_payload(wrb); 2096 *state = resp->beacon_state; 2097 } 2098 2099 err: 2100 spin_unlock_bh(&adapter->mcc_lock); 2101 return status; 2102 } 2103 2104 int lancer_cmd_write_object(struct be_adapter *adapter, struct be_dma_mem *cmd, 2105 u32 data_size, u32 data_offset, 2106 const char *obj_name, u32 *data_written, 2107 u8 *change_status, u8 *addn_status) 2108 { 2109 struct be_mcc_wrb *wrb; 2110 struct lancer_cmd_req_write_object *req; 2111 struct lancer_cmd_resp_write_object *resp; 2112 void *ctxt = NULL; 2113 int status; 2114 2115 spin_lock_bh(&adapter->mcc_lock); 2116 adapter->flash_status = 0; 2117 2118 wrb = wrb_from_mccq(adapter); 2119 if (!wrb) { 2120 status = -EBUSY; 2121 goto err_unlock; 2122 } 2123 2124 req = embedded_payload(wrb); 2125 2126 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2127 OPCODE_COMMON_WRITE_OBJECT, 2128 sizeof(struct lancer_cmd_req_write_object), wrb, 2129 NULL); 2130 2131 ctxt = &req->context; 2132 AMAP_SET_BITS(struct amap_lancer_write_obj_context, 2133 write_length, ctxt, data_size); 2134 2135 if (data_size == 0) 2136 AMAP_SET_BITS(struct amap_lancer_write_obj_context, 2137 eof, ctxt, 1); 2138 else 2139 AMAP_SET_BITS(struct amap_lancer_write_obj_context, 2140 eof, ctxt, 0); 2141 2142 be_dws_cpu_to_le(ctxt, sizeof(req->context)); 2143 req->write_offset = cpu_to_le32(data_offset); 2144 strcpy(req->object_name, obj_name); 2145 req->descriptor_count = cpu_to_le32(1); 2146 req->buf_len = cpu_to_le32(data_size); 2147 req->addr_low = cpu_to_le32((cmd->dma + 2148 sizeof(struct lancer_cmd_req_write_object)) 2149 & 0xFFFFFFFF); 2150 req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma + 2151 sizeof(struct lancer_cmd_req_write_object))); 2152 2153 be_mcc_notify(adapter); 2154 spin_unlock_bh(&adapter->mcc_lock); 2155 2156 if (!wait_for_completion_timeout(&adapter->flash_compl, 2157 msecs_to_jiffies(60000))) 2158 status = -1; 2159 else 2160 status = adapter->flash_status; 2161 2162 resp = embedded_payload(wrb); 2163 if (!status) { 2164 *data_written = le32_to_cpu(resp->actual_write_len); 2165 *change_status = resp->change_status; 2166 } else { 2167 *addn_status = resp->additional_status; 2168 } 2169 2170 return status; 2171 2172 err_unlock: 2173 spin_unlock_bh(&adapter->mcc_lock); 2174 return status; 2175 } 2176 2177 int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd, 2178 u32 data_size, u32 data_offset, const char *obj_name, 2179 u32 *data_read, u32 *eof, u8 *addn_status) 2180 { 2181 struct be_mcc_wrb *wrb; 2182 struct lancer_cmd_req_read_object *req; 2183 struct lancer_cmd_resp_read_object *resp; 2184 int status; 2185 2186 spin_lock_bh(&adapter->mcc_lock); 2187 2188 wrb = wrb_from_mccq(adapter); 2189 if (!wrb) { 2190 status = -EBUSY; 2191 goto err_unlock; 2192 } 2193 2194 req = embedded_payload(wrb); 2195 2196 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2197 OPCODE_COMMON_READ_OBJECT, 2198 sizeof(struct lancer_cmd_req_read_object), wrb, 2199 NULL); 2200 2201 req->desired_read_len = cpu_to_le32(data_size); 2202 req->read_offset = cpu_to_le32(data_offset); 2203 strcpy(req->object_name, obj_name); 2204 req->descriptor_count = cpu_to_le32(1); 2205 req->buf_len = cpu_to_le32(data_size); 2206 req->addr_low = cpu_to_le32((cmd->dma & 0xFFFFFFFF)); 2207 req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma)); 2208 2209 status = be_mcc_notify_wait(adapter); 2210 2211 resp = embedded_payload(wrb); 2212 if (!status) { 2213 *data_read = le32_to_cpu(resp->actual_read_len); 2214 *eof = le32_to_cpu(resp->eof); 2215 } else { 2216 *addn_status = resp->additional_status; 2217 } 2218 2219 err_unlock: 2220 spin_unlock_bh(&adapter->mcc_lock); 2221 return status; 2222 } 2223 2224 int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd, 2225 u32 flash_type, u32 flash_opcode, u32 buf_size) 2226 { 2227 struct be_mcc_wrb *wrb; 2228 struct be_cmd_write_flashrom *req; 2229 int status; 2230 2231 spin_lock_bh(&adapter->mcc_lock); 2232 adapter->flash_status = 0; 2233 2234 wrb = wrb_from_mccq(adapter); 2235 if (!wrb) { 2236 status = -EBUSY; 2237 goto err_unlock; 2238 } 2239 req = cmd->va; 2240 2241 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2242 OPCODE_COMMON_WRITE_FLASHROM, cmd->size, wrb, cmd); 2243 2244 req->params.op_type = cpu_to_le32(flash_type); 2245 req->params.op_code = cpu_to_le32(flash_opcode); 2246 req->params.data_buf_size = cpu_to_le32(buf_size); 2247 2248 be_mcc_notify(adapter); 2249 spin_unlock_bh(&adapter->mcc_lock); 2250 2251 if (!wait_for_completion_timeout(&adapter->flash_compl, 2252 msecs_to_jiffies(40000))) 2253 status = -1; 2254 else 2255 status = adapter->flash_status; 2256 2257 return status; 2258 2259 err_unlock: 2260 spin_unlock_bh(&adapter->mcc_lock); 2261 return status; 2262 } 2263 2264 int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc, 2265 int offset) 2266 { 2267 struct be_mcc_wrb *wrb; 2268 struct be_cmd_read_flash_crc *req; 2269 int status; 2270 2271 spin_lock_bh(&adapter->mcc_lock); 2272 2273 wrb = wrb_from_mccq(adapter); 2274 if (!wrb) { 2275 status = -EBUSY; 2276 goto err; 2277 } 2278 req = embedded_payload(wrb); 2279 2280 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2281 OPCODE_COMMON_READ_FLASHROM, sizeof(*req), 2282 wrb, NULL); 2283 2284 req->params.op_type = cpu_to_le32(OPTYPE_REDBOOT); 2285 req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT); 2286 req->params.offset = cpu_to_le32(offset); 2287 req->params.data_buf_size = cpu_to_le32(0x4); 2288 2289 status = be_mcc_notify_wait(adapter); 2290 if (!status) 2291 memcpy(flashed_crc, req->crc, 4); 2292 2293 err: 2294 spin_unlock_bh(&adapter->mcc_lock); 2295 return status; 2296 } 2297 2298 int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac, 2299 struct be_dma_mem *nonemb_cmd) 2300 { 2301 struct be_mcc_wrb *wrb; 2302 struct be_cmd_req_acpi_wol_magic_config *req; 2303 int status; 2304 2305 spin_lock_bh(&adapter->mcc_lock); 2306 2307 wrb = wrb_from_mccq(adapter); 2308 if (!wrb) { 2309 status = -EBUSY; 2310 goto err; 2311 } 2312 req = nonemb_cmd->va; 2313 2314 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, 2315 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req), wrb, 2316 nonemb_cmd); 2317 memcpy(req->magic_mac, mac, ETH_ALEN); 2318 2319 status = be_mcc_notify_wait(adapter); 2320 2321 err: 2322 spin_unlock_bh(&adapter->mcc_lock); 2323 return status; 2324 } 2325 2326 int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num, 2327 u8 loopback_type, u8 enable) 2328 { 2329 struct be_mcc_wrb *wrb; 2330 struct be_cmd_req_set_lmode *req; 2331 int status; 2332 2333 spin_lock_bh(&adapter->mcc_lock); 2334 2335 wrb = wrb_from_mccq(adapter); 2336 if (!wrb) { 2337 status = -EBUSY; 2338 goto err; 2339 } 2340 2341 req = embedded_payload(wrb); 2342 2343 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL, 2344 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE, sizeof(*req), wrb, 2345 NULL); 2346 2347 req->src_port = port_num; 2348 req->dest_port = port_num; 2349 req->loopback_type = loopback_type; 2350 req->loopback_state = enable; 2351 2352 status = be_mcc_notify_wait(adapter); 2353 err: 2354 spin_unlock_bh(&adapter->mcc_lock); 2355 return status; 2356 } 2357 2358 int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num, 2359 u32 loopback_type, u32 pkt_size, u32 num_pkts, u64 pattern) 2360 { 2361 struct be_mcc_wrb *wrb; 2362 struct be_cmd_req_loopback_test *req; 2363 int status; 2364 2365 spin_lock_bh(&adapter->mcc_lock); 2366 2367 wrb = wrb_from_mccq(adapter); 2368 if (!wrb) { 2369 status = -EBUSY; 2370 goto err; 2371 } 2372 2373 req = embedded_payload(wrb); 2374 2375 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL, 2376 OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req), wrb, NULL); 2377 req->hdr.timeout = cpu_to_le32(4); 2378 2379 req->pattern = cpu_to_le64(pattern); 2380 req->src_port = cpu_to_le32(port_num); 2381 req->dest_port = cpu_to_le32(port_num); 2382 req->pkt_size = cpu_to_le32(pkt_size); 2383 req->num_pkts = cpu_to_le32(num_pkts); 2384 req->loopback_type = cpu_to_le32(loopback_type); 2385 2386 status = be_mcc_notify_wait(adapter); 2387 if (!status) { 2388 struct be_cmd_resp_loopback_test *resp = embedded_payload(wrb); 2389 status = le32_to_cpu(resp->status); 2390 } 2391 2392 err: 2393 spin_unlock_bh(&adapter->mcc_lock); 2394 return status; 2395 } 2396 2397 int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern, 2398 u32 byte_cnt, struct be_dma_mem *cmd) 2399 { 2400 struct be_mcc_wrb *wrb; 2401 struct be_cmd_req_ddrdma_test *req; 2402 int status; 2403 int i, j = 0; 2404 2405 spin_lock_bh(&adapter->mcc_lock); 2406 2407 wrb = wrb_from_mccq(adapter); 2408 if (!wrb) { 2409 status = -EBUSY; 2410 goto err; 2411 } 2412 req = cmd->va; 2413 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL, 2414 OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size, wrb, cmd); 2415 2416 req->pattern = cpu_to_le64(pattern); 2417 req->byte_count = cpu_to_le32(byte_cnt); 2418 for (i = 0; i < byte_cnt; i++) { 2419 req->snd_buff[i] = (u8)(pattern >> (j*8)); 2420 j++; 2421 if (j > 7) 2422 j = 0; 2423 } 2424 2425 status = be_mcc_notify_wait(adapter); 2426 2427 if (!status) { 2428 struct be_cmd_resp_ddrdma_test *resp; 2429 resp = cmd->va; 2430 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) || 2431 resp->snd_err) { 2432 status = -1; 2433 } 2434 } 2435 2436 err: 2437 spin_unlock_bh(&adapter->mcc_lock); 2438 return status; 2439 } 2440 2441 int be_cmd_get_seeprom_data(struct be_adapter *adapter, 2442 struct be_dma_mem *nonemb_cmd) 2443 { 2444 struct be_mcc_wrb *wrb; 2445 struct be_cmd_req_seeprom_read *req; 2446 int status; 2447 2448 spin_lock_bh(&adapter->mcc_lock); 2449 2450 wrb = wrb_from_mccq(adapter); 2451 if (!wrb) { 2452 status = -EBUSY; 2453 goto err; 2454 } 2455 req = nonemb_cmd->va; 2456 2457 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2458 OPCODE_COMMON_SEEPROM_READ, sizeof(*req), wrb, 2459 nonemb_cmd); 2460 2461 status = be_mcc_notify_wait(adapter); 2462 2463 err: 2464 spin_unlock_bh(&adapter->mcc_lock); 2465 return status; 2466 } 2467 2468 int be_cmd_get_phy_info(struct be_adapter *adapter) 2469 { 2470 struct be_mcc_wrb *wrb; 2471 struct be_cmd_req_get_phy_info *req; 2472 struct be_dma_mem cmd; 2473 int status; 2474 2475 if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_PHY_DETAILS, 2476 CMD_SUBSYSTEM_COMMON)) 2477 return -EPERM; 2478 2479 spin_lock_bh(&adapter->mcc_lock); 2480 2481 wrb = wrb_from_mccq(adapter); 2482 if (!wrb) { 2483 status = -EBUSY; 2484 goto err; 2485 } 2486 cmd.size = sizeof(struct be_cmd_req_get_phy_info); 2487 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, 2488 &cmd.dma); 2489 if (!cmd.va) { 2490 dev_err(&adapter->pdev->dev, "Memory alloc failure\n"); 2491 status = -ENOMEM; 2492 goto err; 2493 } 2494 2495 req = cmd.va; 2496 2497 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2498 OPCODE_COMMON_GET_PHY_DETAILS, sizeof(*req), 2499 wrb, &cmd); 2500 2501 status = be_mcc_notify_wait(adapter); 2502 if (!status) { 2503 struct be_phy_info *resp_phy_info = 2504 cmd.va + sizeof(struct be_cmd_req_hdr); 2505 adapter->phy.phy_type = le16_to_cpu(resp_phy_info->phy_type); 2506 adapter->phy.interface_type = 2507 le16_to_cpu(resp_phy_info->interface_type); 2508 adapter->phy.auto_speeds_supported = 2509 le16_to_cpu(resp_phy_info->auto_speeds_supported); 2510 adapter->phy.fixed_speeds_supported = 2511 le16_to_cpu(resp_phy_info->fixed_speeds_supported); 2512 adapter->phy.misc_params = 2513 le32_to_cpu(resp_phy_info->misc_params); 2514 2515 if (BE2_chip(adapter)) { 2516 adapter->phy.fixed_speeds_supported = 2517 BE_SUPPORTED_SPEED_10GBPS | 2518 BE_SUPPORTED_SPEED_1GBPS; 2519 } 2520 } 2521 pci_free_consistent(adapter->pdev, cmd.size, 2522 cmd.va, cmd.dma); 2523 err: 2524 spin_unlock_bh(&adapter->mcc_lock); 2525 return status; 2526 } 2527 2528 int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain) 2529 { 2530 struct be_mcc_wrb *wrb; 2531 struct be_cmd_req_set_qos *req; 2532 int status; 2533 2534 spin_lock_bh(&adapter->mcc_lock); 2535 2536 wrb = wrb_from_mccq(adapter); 2537 if (!wrb) { 2538 status = -EBUSY; 2539 goto err; 2540 } 2541 2542 req = embedded_payload(wrb); 2543 2544 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2545 OPCODE_COMMON_SET_QOS, sizeof(*req), wrb, NULL); 2546 2547 req->hdr.domain = domain; 2548 req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC); 2549 req->max_bps_nic = cpu_to_le32(bps); 2550 2551 status = be_mcc_notify_wait(adapter); 2552 2553 err: 2554 spin_unlock_bh(&adapter->mcc_lock); 2555 return status; 2556 } 2557 2558 int be_cmd_get_cntl_attributes(struct be_adapter *adapter) 2559 { 2560 struct be_mcc_wrb *wrb; 2561 struct be_cmd_req_cntl_attribs *req; 2562 struct be_cmd_resp_cntl_attribs *resp; 2563 int status; 2564 int payload_len = max(sizeof(*req), sizeof(*resp)); 2565 struct mgmt_controller_attrib *attribs; 2566 struct be_dma_mem attribs_cmd; 2567 2568 if (mutex_lock_interruptible(&adapter->mbox_lock)) 2569 return -1; 2570 2571 memset(&attribs_cmd, 0, sizeof(struct be_dma_mem)); 2572 attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs); 2573 attribs_cmd.va = pci_alloc_consistent(adapter->pdev, attribs_cmd.size, 2574 &attribs_cmd.dma); 2575 if (!attribs_cmd.va) { 2576 dev_err(&adapter->pdev->dev, 2577 "Memory allocation failure\n"); 2578 status = -ENOMEM; 2579 goto err; 2580 } 2581 2582 wrb = wrb_from_mbox(adapter); 2583 if (!wrb) { 2584 status = -EBUSY; 2585 goto err; 2586 } 2587 req = attribs_cmd.va; 2588 2589 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2590 OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len, wrb, 2591 &attribs_cmd); 2592 2593 status = be_mbox_notify_wait(adapter); 2594 if (!status) { 2595 attribs = attribs_cmd.va + sizeof(struct be_cmd_resp_hdr); 2596 adapter->hba_port_num = attribs->hba_attribs.phy_port; 2597 } 2598 2599 err: 2600 mutex_unlock(&adapter->mbox_lock); 2601 if (attribs_cmd.va) 2602 pci_free_consistent(adapter->pdev, attribs_cmd.size, 2603 attribs_cmd.va, attribs_cmd.dma); 2604 return status; 2605 } 2606 2607 /* Uses mbox */ 2608 int be_cmd_req_native_mode(struct be_adapter *adapter) 2609 { 2610 struct be_mcc_wrb *wrb; 2611 struct be_cmd_req_set_func_cap *req; 2612 int status; 2613 2614 if (mutex_lock_interruptible(&adapter->mbox_lock)) 2615 return -1; 2616 2617 wrb = wrb_from_mbox(adapter); 2618 if (!wrb) { 2619 status = -EBUSY; 2620 goto err; 2621 } 2622 2623 req = embedded_payload(wrb); 2624 2625 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2626 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP, sizeof(*req), wrb, NULL); 2627 2628 req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS | 2629 CAPABILITY_BE3_NATIVE_ERX_API); 2630 req->cap_flags = cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API); 2631 2632 status = be_mbox_notify_wait(adapter); 2633 if (!status) { 2634 struct be_cmd_resp_set_func_cap *resp = embedded_payload(wrb); 2635 adapter->be3_native = le32_to_cpu(resp->cap_flags) & 2636 CAPABILITY_BE3_NATIVE_ERX_API; 2637 if (!adapter->be3_native) 2638 dev_warn(&adapter->pdev->dev, 2639 "adapter not in advanced mode\n"); 2640 } 2641 err: 2642 mutex_unlock(&adapter->mbox_lock); 2643 return status; 2644 } 2645 2646 /* Get privilege(s) for a function */ 2647 int be_cmd_get_fn_privileges(struct be_adapter *adapter, u32 *privilege, 2648 u32 domain) 2649 { 2650 struct be_mcc_wrb *wrb; 2651 struct be_cmd_req_get_fn_privileges *req; 2652 int status; 2653 2654 spin_lock_bh(&adapter->mcc_lock); 2655 2656 wrb = wrb_from_mccq(adapter); 2657 if (!wrb) { 2658 status = -EBUSY; 2659 goto err; 2660 } 2661 2662 req = embedded_payload(wrb); 2663 2664 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2665 OPCODE_COMMON_GET_FN_PRIVILEGES, sizeof(*req), 2666 wrb, NULL); 2667 2668 req->hdr.domain = domain; 2669 2670 status = be_mcc_notify_wait(adapter); 2671 if (!status) { 2672 struct be_cmd_resp_get_fn_privileges *resp = 2673 embedded_payload(wrb); 2674 *privilege = le32_to_cpu(resp->privilege_mask); 2675 } 2676 2677 err: 2678 spin_unlock_bh(&adapter->mcc_lock); 2679 return status; 2680 } 2681 2682 /* Set privilege(s) for a function */ 2683 int be_cmd_set_fn_privileges(struct be_adapter *adapter, u32 privileges, 2684 u32 domain) 2685 { 2686 struct be_mcc_wrb *wrb; 2687 struct be_cmd_req_set_fn_privileges *req; 2688 int status; 2689 2690 spin_lock_bh(&adapter->mcc_lock); 2691 2692 wrb = wrb_from_mccq(adapter); 2693 if (!wrb) { 2694 status = -EBUSY; 2695 goto err; 2696 } 2697 2698 req = embedded_payload(wrb); 2699 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2700 OPCODE_COMMON_SET_FN_PRIVILEGES, sizeof(*req), 2701 wrb, NULL); 2702 req->hdr.domain = domain; 2703 if (lancer_chip(adapter)) 2704 req->privileges_lancer = cpu_to_le32(privileges); 2705 else 2706 req->privileges = cpu_to_le32(privileges); 2707 2708 status = be_mcc_notify_wait(adapter); 2709 err: 2710 spin_unlock_bh(&adapter->mcc_lock); 2711 return status; 2712 } 2713 2714 /* pmac_id_valid: true => pmac_id is supplied and MAC address is requested. 2715 * pmac_id_valid: false => pmac_id or MAC address is requested. 2716 * If pmac_id is returned, pmac_id_valid is returned as true 2717 */ 2718 int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac, 2719 bool *pmac_id_valid, u32 *pmac_id, u8 domain) 2720 { 2721 struct be_mcc_wrb *wrb; 2722 struct be_cmd_req_get_mac_list *req; 2723 int status; 2724 int mac_count; 2725 struct be_dma_mem get_mac_list_cmd; 2726 int i; 2727 2728 memset(&get_mac_list_cmd, 0, sizeof(struct be_dma_mem)); 2729 get_mac_list_cmd.size = sizeof(struct be_cmd_resp_get_mac_list); 2730 get_mac_list_cmd.va = pci_alloc_consistent(adapter->pdev, 2731 get_mac_list_cmd.size, 2732 &get_mac_list_cmd.dma); 2733 2734 if (!get_mac_list_cmd.va) { 2735 dev_err(&adapter->pdev->dev, 2736 "Memory allocation failure during GET_MAC_LIST\n"); 2737 return -ENOMEM; 2738 } 2739 2740 spin_lock_bh(&adapter->mcc_lock); 2741 2742 wrb = wrb_from_mccq(adapter); 2743 if (!wrb) { 2744 status = -EBUSY; 2745 goto out; 2746 } 2747 2748 req = get_mac_list_cmd.va; 2749 2750 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2751 OPCODE_COMMON_GET_MAC_LIST, 2752 get_mac_list_cmd.size, wrb, &get_mac_list_cmd); 2753 req->hdr.domain = domain; 2754 req->mac_type = MAC_ADDRESS_TYPE_NETWORK; 2755 if (*pmac_id_valid) { 2756 req->mac_id = cpu_to_le32(*pmac_id); 2757 req->iface_id = cpu_to_le16(adapter->if_handle); 2758 req->perm_override = 0; 2759 } else { 2760 req->perm_override = 1; 2761 } 2762 2763 status = be_mcc_notify_wait(adapter); 2764 if (!status) { 2765 struct be_cmd_resp_get_mac_list *resp = 2766 get_mac_list_cmd.va; 2767 2768 if (*pmac_id_valid) { 2769 memcpy(mac, resp->macid_macaddr.mac_addr_id.macaddr, 2770 ETH_ALEN); 2771 goto out; 2772 } 2773 2774 mac_count = resp->true_mac_count + resp->pseudo_mac_count; 2775 /* Mac list returned could contain one or more active mac_ids 2776 * or one or more true or pseudo permanant mac addresses. 2777 * If an active mac_id is present, return first active mac_id 2778 * found. 2779 */ 2780 for (i = 0; i < mac_count; i++) { 2781 struct get_list_macaddr *mac_entry; 2782 u16 mac_addr_size; 2783 u32 mac_id; 2784 2785 mac_entry = &resp->macaddr_list[i]; 2786 mac_addr_size = le16_to_cpu(mac_entry->mac_addr_size); 2787 /* mac_id is a 32 bit value and mac_addr size 2788 * is 6 bytes 2789 */ 2790 if (mac_addr_size == sizeof(u32)) { 2791 *pmac_id_valid = true; 2792 mac_id = mac_entry->mac_addr_id.s_mac_id.mac_id; 2793 *pmac_id = le32_to_cpu(mac_id); 2794 goto out; 2795 } 2796 } 2797 /* If no active mac_id found, return first mac addr */ 2798 *pmac_id_valid = false; 2799 memcpy(mac, resp->macaddr_list[0].mac_addr_id.macaddr, 2800 ETH_ALEN); 2801 } 2802 2803 out: 2804 spin_unlock_bh(&adapter->mcc_lock); 2805 pci_free_consistent(adapter->pdev, get_mac_list_cmd.size, 2806 get_mac_list_cmd.va, get_mac_list_cmd.dma); 2807 return status; 2808 } 2809 2810 int be_cmd_get_active_mac(struct be_adapter *adapter, u32 curr_pmac_id, u8 *mac) 2811 { 2812 bool active = true; 2813 2814 if (BEx_chip(adapter)) 2815 return be_cmd_mac_addr_query(adapter, mac, false, 2816 adapter->if_handle, curr_pmac_id); 2817 else 2818 /* Fetch the MAC address using pmac_id */ 2819 return be_cmd_get_mac_from_list(adapter, mac, &active, 2820 &curr_pmac_id, 0); 2821 } 2822 2823 int be_cmd_get_perm_mac(struct be_adapter *adapter, u8 *mac) 2824 { 2825 int status; 2826 bool pmac_valid = false; 2827 2828 memset(mac, 0, ETH_ALEN); 2829 2830 if (BEx_chip(adapter)) { 2831 if (be_physfn(adapter)) 2832 status = be_cmd_mac_addr_query(adapter, mac, true, 0, 2833 0); 2834 else 2835 status = be_cmd_mac_addr_query(adapter, mac, false, 2836 adapter->if_handle, 0); 2837 } else { 2838 status = be_cmd_get_mac_from_list(adapter, mac, &pmac_valid, 2839 NULL, 0); 2840 } 2841 2842 return status; 2843 } 2844 2845 /* Uses synchronous MCCQ */ 2846 int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array, 2847 u8 mac_count, u32 domain) 2848 { 2849 struct be_mcc_wrb *wrb; 2850 struct be_cmd_req_set_mac_list *req; 2851 int status; 2852 struct be_dma_mem cmd; 2853 2854 memset(&cmd, 0, sizeof(struct be_dma_mem)); 2855 cmd.size = sizeof(struct be_cmd_req_set_mac_list); 2856 cmd.va = dma_alloc_coherent(&adapter->pdev->dev, cmd.size, 2857 &cmd.dma, GFP_KERNEL); 2858 if (!cmd.va) 2859 return -ENOMEM; 2860 2861 spin_lock_bh(&adapter->mcc_lock); 2862 2863 wrb = wrb_from_mccq(adapter); 2864 if (!wrb) { 2865 status = -EBUSY; 2866 goto err; 2867 } 2868 2869 req = cmd.va; 2870 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2871 OPCODE_COMMON_SET_MAC_LIST, sizeof(*req), 2872 wrb, &cmd); 2873 2874 req->hdr.domain = domain; 2875 req->mac_count = mac_count; 2876 if (mac_count) 2877 memcpy(req->mac, mac_array, ETH_ALEN*mac_count); 2878 2879 status = be_mcc_notify_wait(adapter); 2880 2881 err: 2882 dma_free_coherent(&adapter->pdev->dev, cmd.size, 2883 cmd.va, cmd.dma); 2884 spin_unlock_bh(&adapter->mcc_lock); 2885 return status; 2886 } 2887 2888 /* Wrapper to delete any active MACs and provision the new mac. 2889 * Changes to MAC_LIST are allowed iff none of the MAC addresses in the 2890 * current list are active. 2891 */ 2892 int be_cmd_set_mac(struct be_adapter *adapter, u8 *mac, int if_id, u32 dom) 2893 { 2894 bool active_mac = false; 2895 u8 old_mac[ETH_ALEN]; 2896 u32 pmac_id; 2897 int status; 2898 2899 status = be_cmd_get_mac_from_list(adapter, old_mac, &active_mac, 2900 &pmac_id, dom); 2901 if (!status && active_mac) 2902 be_cmd_pmac_del(adapter, if_id, pmac_id, dom); 2903 2904 return be_cmd_set_mac_list(adapter, mac, mac ? 1 : 0, dom); 2905 } 2906 2907 int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid, 2908 u32 domain, u16 intf_id, u16 hsw_mode) 2909 { 2910 struct be_mcc_wrb *wrb; 2911 struct be_cmd_req_set_hsw_config *req; 2912 void *ctxt; 2913 int status; 2914 2915 spin_lock_bh(&adapter->mcc_lock); 2916 2917 wrb = wrb_from_mccq(adapter); 2918 if (!wrb) { 2919 status = -EBUSY; 2920 goto err; 2921 } 2922 2923 req = embedded_payload(wrb); 2924 ctxt = &req->context; 2925 2926 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2927 OPCODE_COMMON_SET_HSW_CONFIG, sizeof(*req), wrb, NULL); 2928 2929 req->hdr.domain = domain; 2930 AMAP_SET_BITS(struct amap_set_hsw_context, interface_id, ctxt, intf_id); 2931 if (pvid) { 2932 AMAP_SET_BITS(struct amap_set_hsw_context, pvid_valid, ctxt, 1); 2933 AMAP_SET_BITS(struct amap_set_hsw_context, pvid, ctxt, pvid); 2934 } 2935 if (!BEx_chip(adapter) && hsw_mode) { 2936 AMAP_SET_BITS(struct amap_set_hsw_context, interface_id, 2937 ctxt, adapter->hba_port_num); 2938 AMAP_SET_BITS(struct amap_set_hsw_context, pport, ctxt, 1); 2939 AMAP_SET_BITS(struct amap_set_hsw_context, port_fwd_type, 2940 ctxt, hsw_mode); 2941 } 2942 2943 be_dws_cpu_to_le(req->context, sizeof(req->context)); 2944 status = be_mcc_notify_wait(adapter); 2945 2946 err: 2947 spin_unlock_bh(&adapter->mcc_lock); 2948 return status; 2949 } 2950 2951 /* Get Hyper switch config */ 2952 int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid, 2953 u32 domain, u16 intf_id, u8 *mode) 2954 { 2955 struct be_mcc_wrb *wrb; 2956 struct be_cmd_req_get_hsw_config *req; 2957 void *ctxt; 2958 int status; 2959 u16 vid; 2960 2961 spin_lock_bh(&adapter->mcc_lock); 2962 2963 wrb = wrb_from_mccq(adapter); 2964 if (!wrb) { 2965 status = -EBUSY; 2966 goto err; 2967 } 2968 2969 req = embedded_payload(wrb); 2970 ctxt = &req->context; 2971 2972 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2973 OPCODE_COMMON_GET_HSW_CONFIG, sizeof(*req), wrb, NULL); 2974 2975 req->hdr.domain = domain; 2976 AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id, 2977 ctxt, intf_id); 2978 AMAP_SET_BITS(struct amap_get_hsw_req_context, pvid_valid, ctxt, 1); 2979 2980 if (!BEx_chip(adapter)) { 2981 AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id, 2982 ctxt, adapter->hba_port_num); 2983 AMAP_SET_BITS(struct amap_get_hsw_req_context, pport, ctxt, 1); 2984 } 2985 be_dws_cpu_to_le(req->context, sizeof(req->context)); 2986 2987 status = be_mcc_notify_wait(adapter); 2988 if (!status) { 2989 struct be_cmd_resp_get_hsw_config *resp = 2990 embedded_payload(wrb); 2991 be_dws_le_to_cpu(&resp->context, 2992 sizeof(resp->context)); 2993 vid = AMAP_GET_BITS(struct amap_get_hsw_resp_context, 2994 pvid, &resp->context); 2995 if (pvid) 2996 *pvid = le16_to_cpu(vid); 2997 if (mode) 2998 *mode = AMAP_GET_BITS(struct amap_get_hsw_resp_context, 2999 port_fwd_type, &resp->context); 3000 } 3001 3002 err: 3003 spin_unlock_bh(&adapter->mcc_lock); 3004 return status; 3005 } 3006 3007 int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter) 3008 { 3009 struct be_mcc_wrb *wrb; 3010 struct be_cmd_req_acpi_wol_magic_config_v1 *req; 3011 int status; 3012 int payload_len = sizeof(*req); 3013 struct be_dma_mem cmd; 3014 3015 if (!be_cmd_allowed(adapter, OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, 3016 CMD_SUBSYSTEM_ETH)) 3017 return -EPERM; 3018 3019 if (mutex_lock_interruptible(&adapter->mbox_lock)) 3020 return -1; 3021 3022 memset(&cmd, 0, sizeof(struct be_dma_mem)); 3023 cmd.size = sizeof(struct be_cmd_resp_acpi_wol_magic_config_v1); 3024 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, 3025 &cmd.dma); 3026 if (!cmd.va) { 3027 dev_err(&adapter->pdev->dev, 3028 "Memory allocation failure\n"); 3029 status = -ENOMEM; 3030 goto err; 3031 } 3032 3033 wrb = wrb_from_mbox(adapter); 3034 if (!wrb) { 3035 status = -EBUSY; 3036 goto err; 3037 } 3038 3039 req = cmd.va; 3040 3041 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, 3042 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, 3043 payload_len, wrb, &cmd); 3044 3045 req->hdr.version = 1; 3046 req->query_options = BE_GET_WOL_CAP; 3047 3048 status = be_mbox_notify_wait(adapter); 3049 if (!status) { 3050 struct be_cmd_resp_acpi_wol_magic_config_v1 *resp; 3051 resp = (struct be_cmd_resp_acpi_wol_magic_config_v1 *) cmd.va; 3052 3053 /* the command could succeed misleadingly on old f/w 3054 * which is not aware of the V1 version. fake an error. */ 3055 if (resp->hdr.response_length < payload_len) { 3056 status = -1; 3057 goto err; 3058 } 3059 adapter->wol_cap = resp->wol_settings; 3060 } 3061 err: 3062 mutex_unlock(&adapter->mbox_lock); 3063 if (cmd.va) 3064 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma); 3065 return status; 3066 3067 } 3068 int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter, 3069 struct be_dma_mem *cmd) 3070 { 3071 struct be_mcc_wrb *wrb; 3072 struct be_cmd_req_get_ext_fat_caps *req; 3073 int status; 3074 3075 if (mutex_lock_interruptible(&adapter->mbox_lock)) 3076 return -1; 3077 3078 wrb = wrb_from_mbox(adapter); 3079 if (!wrb) { 3080 status = -EBUSY; 3081 goto err; 3082 } 3083 3084 req = cmd->va; 3085 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 3086 OPCODE_COMMON_GET_EXT_FAT_CAPABILITES, 3087 cmd->size, wrb, cmd); 3088 req->parameter_type = cpu_to_le32(1); 3089 3090 status = be_mbox_notify_wait(adapter); 3091 err: 3092 mutex_unlock(&adapter->mbox_lock); 3093 return status; 3094 } 3095 3096 int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter, 3097 struct be_dma_mem *cmd, 3098 struct be_fat_conf_params *configs) 3099 { 3100 struct be_mcc_wrb *wrb; 3101 struct be_cmd_req_set_ext_fat_caps *req; 3102 int status; 3103 3104 spin_lock_bh(&adapter->mcc_lock); 3105 3106 wrb = wrb_from_mccq(adapter); 3107 if (!wrb) { 3108 status = -EBUSY; 3109 goto err; 3110 } 3111 3112 req = cmd->va; 3113 memcpy(&req->set_params, configs, sizeof(struct be_fat_conf_params)); 3114 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 3115 OPCODE_COMMON_SET_EXT_FAT_CAPABILITES, 3116 cmd->size, wrb, cmd); 3117 3118 status = be_mcc_notify_wait(adapter); 3119 err: 3120 spin_unlock_bh(&adapter->mcc_lock); 3121 return status; 3122 } 3123 3124 int be_cmd_query_port_name(struct be_adapter *adapter, u8 *port_name) 3125 { 3126 struct be_mcc_wrb *wrb; 3127 struct be_cmd_req_get_port_name *req; 3128 int status; 3129 3130 if (!lancer_chip(adapter)) { 3131 *port_name = adapter->hba_port_num + '0'; 3132 return 0; 3133 } 3134 3135 spin_lock_bh(&adapter->mcc_lock); 3136 3137 wrb = wrb_from_mccq(adapter); 3138 if (!wrb) { 3139 status = -EBUSY; 3140 goto err; 3141 } 3142 3143 req = embedded_payload(wrb); 3144 3145 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 3146 OPCODE_COMMON_GET_PORT_NAME, sizeof(*req), wrb, 3147 NULL); 3148 req->hdr.version = 1; 3149 3150 status = be_mcc_notify_wait(adapter); 3151 if (!status) { 3152 struct be_cmd_resp_get_port_name *resp = embedded_payload(wrb); 3153 *port_name = resp->port_name[adapter->hba_port_num]; 3154 } else { 3155 *port_name = adapter->hba_port_num + '0'; 3156 } 3157 err: 3158 spin_unlock_bh(&adapter->mcc_lock); 3159 return status; 3160 } 3161 3162 static struct be_nic_res_desc *be_get_nic_desc(u8 *buf, u32 desc_count) 3163 { 3164 struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf; 3165 int i; 3166 3167 for (i = 0; i < desc_count; i++) { 3168 if (hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V0 || 3169 hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V1) 3170 return (struct be_nic_res_desc *)hdr; 3171 3172 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0; 3173 hdr = (void *)hdr + hdr->desc_len; 3174 } 3175 return NULL; 3176 } 3177 3178 static struct be_pcie_res_desc *be_get_pcie_desc(u8 devfn, u8 *buf, 3179 u32 desc_count) 3180 { 3181 struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf; 3182 struct be_pcie_res_desc *pcie; 3183 int i; 3184 3185 for (i = 0; i < desc_count; i++) { 3186 if ((hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V0 || 3187 hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V1)) { 3188 pcie = (struct be_pcie_res_desc *)hdr; 3189 if (pcie->pf_num == devfn) 3190 return pcie; 3191 } 3192 3193 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0; 3194 hdr = (void *)hdr + hdr->desc_len; 3195 } 3196 return NULL; 3197 } 3198 3199 static void be_copy_nic_desc(struct be_resources *res, 3200 struct be_nic_res_desc *desc) 3201 { 3202 res->max_uc_mac = le16_to_cpu(desc->unicast_mac_count); 3203 res->max_vlans = le16_to_cpu(desc->vlan_count); 3204 res->max_mcast_mac = le16_to_cpu(desc->mcast_mac_count); 3205 res->max_tx_qs = le16_to_cpu(desc->txq_count); 3206 res->max_rss_qs = le16_to_cpu(desc->rssq_count); 3207 res->max_rx_qs = le16_to_cpu(desc->rq_count); 3208 res->max_evt_qs = le16_to_cpu(desc->eq_count); 3209 /* Clear flags that driver is not interested in */ 3210 res->if_cap_flags = le32_to_cpu(desc->cap_flags) & 3211 BE_IF_CAP_FLAGS_WANT; 3212 /* Need 1 RXQ as the default RXQ */ 3213 if (res->max_rss_qs && res->max_rss_qs == res->max_rx_qs) 3214 res->max_rss_qs -= 1; 3215 } 3216 3217 /* Uses Mbox */ 3218 int be_cmd_get_func_config(struct be_adapter *adapter, struct be_resources *res) 3219 { 3220 struct be_mcc_wrb *wrb; 3221 struct be_cmd_req_get_func_config *req; 3222 int status; 3223 struct be_dma_mem cmd; 3224 3225 if (mutex_lock_interruptible(&adapter->mbox_lock)) 3226 return -1; 3227 3228 memset(&cmd, 0, sizeof(struct be_dma_mem)); 3229 cmd.size = sizeof(struct be_cmd_resp_get_func_config); 3230 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, 3231 &cmd.dma); 3232 if (!cmd.va) { 3233 dev_err(&adapter->pdev->dev, "Memory alloc failure\n"); 3234 status = -ENOMEM; 3235 goto err; 3236 } 3237 3238 wrb = wrb_from_mbox(adapter); 3239 if (!wrb) { 3240 status = -EBUSY; 3241 goto err; 3242 } 3243 3244 req = cmd.va; 3245 3246 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 3247 OPCODE_COMMON_GET_FUNC_CONFIG, 3248 cmd.size, wrb, &cmd); 3249 3250 if (skyhawk_chip(adapter)) 3251 req->hdr.version = 1; 3252 3253 status = be_mbox_notify_wait(adapter); 3254 if (!status) { 3255 struct be_cmd_resp_get_func_config *resp = cmd.va; 3256 u32 desc_count = le32_to_cpu(resp->desc_count); 3257 struct be_nic_res_desc *desc; 3258 3259 desc = be_get_nic_desc(resp->func_param, desc_count); 3260 if (!desc) { 3261 status = -EINVAL; 3262 goto err; 3263 } 3264 3265 adapter->pf_number = desc->pf_num; 3266 be_copy_nic_desc(res, desc); 3267 } 3268 err: 3269 mutex_unlock(&adapter->mbox_lock); 3270 if (cmd.va) 3271 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma); 3272 return status; 3273 } 3274 3275 /* Uses mbox */ 3276 static int be_cmd_get_profile_config_mbox(struct be_adapter *adapter, 3277 u8 domain, struct be_dma_mem *cmd) 3278 { 3279 struct be_mcc_wrb *wrb; 3280 struct be_cmd_req_get_profile_config *req; 3281 int status; 3282 3283 if (mutex_lock_interruptible(&adapter->mbox_lock)) 3284 return -1; 3285 wrb = wrb_from_mbox(adapter); 3286 3287 req = cmd->va; 3288 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 3289 OPCODE_COMMON_GET_PROFILE_CONFIG, 3290 cmd->size, wrb, cmd); 3291 3292 req->type = ACTIVE_PROFILE_TYPE; 3293 req->hdr.domain = domain; 3294 if (!lancer_chip(adapter)) 3295 req->hdr.version = 1; 3296 3297 status = be_mbox_notify_wait(adapter); 3298 3299 mutex_unlock(&adapter->mbox_lock); 3300 return status; 3301 } 3302 3303 /* Uses sync mcc */ 3304 static int be_cmd_get_profile_config_mccq(struct be_adapter *adapter, 3305 u8 domain, struct be_dma_mem *cmd) 3306 { 3307 struct be_mcc_wrb *wrb; 3308 struct be_cmd_req_get_profile_config *req; 3309 int status; 3310 3311 spin_lock_bh(&adapter->mcc_lock); 3312 3313 wrb = wrb_from_mccq(adapter); 3314 if (!wrb) { 3315 status = -EBUSY; 3316 goto err; 3317 } 3318 3319 req = cmd->va; 3320 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 3321 OPCODE_COMMON_GET_PROFILE_CONFIG, 3322 cmd->size, wrb, cmd); 3323 3324 req->type = ACTIVE_PROFILE_TYPE; 3325 req->hdr.domain = domain; 3326 if (!lancer_chip(adapter)) 3327 req->hdr.version = 1; 3328 3329 status = be_mcc_notify_wait(adapter); 3330 3331 err: 3332 spin_unlock_bh(&adapter->mcc_lock); 3333 return status; 3334 } 3335 3336 /* Uses sync mcc, if MCCQ is already created otherwise mbox */ 3337 int be_cmd_get_profile_config(struct be_adapter *adapter, 3338 struct be_resources *res, u8 domain) 3339 { 3340 struct be_cmd_resp_get_profile_config *resp; 3341 struct be_pcie_res_desc *pcie; 3342 struct be_nic_res_desc *nic; 3343 struct be_queue_info *mccq = &adapter->mcc_obj.q; 3344 struct be_dma_mem cmd; 3345 u32 desc_count; 3346 int status; 3347 3348 memset(&cmd, 0, sizeof(struct be_dma_mem)); 3349 cmd.size = sizeof(struct be_cmd_resp_get_profile_config); 3350 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma); 3351 if (!cmd.va) 3352 return -ENOMEM; 3353 3354 if (!mccq->created) 3355 status = be_cmd_get_profile_config_mbox(adapter, domain, &cmd); 3356 else 3357 status = be_cmd_get_profile_config_mccq(adapter, domain, &cmd); 3358 if (status) 3359 goto err; 3360 3361 resp = cmd.va; 3362 desc_count = le32_to_cpu(resp->desc_count); 3363 3364 pcie = be_get_pcie_desc(adapter->pdev->devfn, resp->func_param, 3365 desc_count); 3366 if (pcie) 3367 res->max_vfs = le16_to_cpu(pcie->num_vfs); 3368 3369 nic = be_get_nic_desc(resp->func_param, desc_count); 3370 if (nic) 3371 be_copy_nic_desc(res, nic); 3372 3373 err: 3374 if (cmd.va) 3375 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma); 3376 return status; 3377 } 3378 3379 /* Currently only Lancer uses this command and it supports version 0 only 3380 * Uses sync mcc 3381 */ 3382 int be_cmd_set_profile_config(struct be_adapter *adapter, u32 bps, 3383 u8 domain) 3384 { 3385 struct be_mcc_wrb *wrb; 3386 struct be_cmd_req_set_profile_config *req; 3387 int status; 3388 3389 spin_lock_bh(&adapter->mcc_lock); 3390 3391 wrb = wrb_from_mccq(adapter); 3392 if (!wrb) { 3393 status = -EBUSY; 3394 goto err; 3395 } 3396 3397 req = embedded_payload(wrb); 3398 3399 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 3400 OPCODE_COMMON_SET_PROFILE_CONFIG, sizeof(*req), 3401 wrb, NULL); 3402 req->hdr.domain = domain; 3403 req->desc_count = cpu_to_le32(1); 3404 req->nic_desc.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V0; 3405 req->nic_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V0; 3406 req->nic_desc.flags = (1 << QUN) | (1 << IMM) | (1 << NOSV); 3407 req->nic_desc.pf_num = adapter->pf_number; 3408 req->nic_desc.vf_num = domain; 3409 3410 /* Mark fields invalid */ 3411 req->nic_desc.unicast_mac_count = 0xFFFF; 3412 req->nic_desc.mcc_count = 0xFFFF; 3413 req->nic_desc.vlan_count = 0xFFFF; 3414 req->nic_desc.mcast_mac_count = 0xFFFF; 3415 req->nic_desc.txq_count = 0xFFFF; 3416 req->nic_desc.rq_count = 0xFFFF; 3417 req->nic_desc.rssq_count = 0xFFFF; 3418 req->nic_desc.lro_count = 0xFFFF; 3419 req->nic_desc.cq_count = 0xFFFF; 3420 req->nic_desc.toe_conn_count = 0xFFFF; 3421 req->nic_desc.eq_count = 0xFFFF; 3422 req->nic_desc.link_param = 0xFF; 3423 req->nic_desc.bw_min = 0xFFFFFFFF; 3424 req->nic_desc.acpi_params = 0xFF; 3425 req->nic_desc.wol_param = 0x0F; 3426 3427 /* Change BW */ 3428 req->nic_desc.bw_min = cpu_to_le32(bps); 3429 req->nic_desc.bw_max = cpu_to_le32(bps); 3430 status = be_mcc_notify_wait(adapter); 3431 err: 3432 spin_unlock_bh(&adapter->mcc_lock); 3433 return status; 3434 } 3435 3436 int be_cmd_get_if_id(struct be_adapter *adapter, struct be_vf_cfg *vf_cfg, 3437 int vf_num) 3438 { 3439 struct be_mcc_wrb *wrb; 3440 struct be_cmd_req_get_iface_list *req; 3441 struct be_cmd_resp_get_iface_list *resp; 3442 int status; 3443 3444 spin_lock_bh(&adapter->mcc_lock); 3445 3446 wrb = wrb_from_mccq(adapter); 3447 if (!wrb) { 3448 status = -EBUSY; 3449 goto err; 3450 } 3451 req = embedded_payload(wrb); 3452 3453 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 3454 OPCODE_COMMON_GET_IFACE_LIST, sizeof(*resp), 3455 wrb, NULL); 3456 req->hdr.domain = vf_num + 1; 3457 3458 status = be_mcc_notify_wait(adapter); 3459 if (!status) { 3460 resp = (struct be_cmd_resp_get_iface_list *)req; 3461 vf_cfg->if_handle = le32_to_cpu(resp->if_desc.if_id); 3462 } 3463 3464 err: 3465 spin_unlock_bh(&adapter->mcc_lock); 3466 return status; 3467 } 3468 3469 static int lancer_wait_idle(struct be_adapter *adapter) 3470 { 3471 #define SLIPORT_IDLE_TIMEOUT 30 3472 u32 reg_val; 3473 int status = 0, i; 3474 3475 for (i = 0; i < SLIPORT_IDLE_TIMEOUT; i++) { 3476 reg_val = ioread32(adapter->db + PHYSDEV_CONTROL_OFFSET); 3477 if ((reg_val & PHYSDEV_CONTROL_INP_MASK) == 0) 3478 break; 3479 3480 ssleep(1); 3481 } 3482 3483 if (i == SLIPORT_IDLE_TIMEOUT) 3484 status = -1; 3485 3486 return status; 3487 } 3488 3489 int lancer_physdev_ctrl(struct be_adapter *adapter, u32 mask) 3490 { 3491 int status = 0; 3492 3493 status = lancer_wait_idle(adapter); 3494 if (status) 3495 return status; 3496 3497 iowrite32(mask, adapter->db + PHYSDEV_CONTROL_OFFSET); 3498 3499 return status; 3500 } 3501 3502 /* Routine to check whether dump image is present or not */ 3503 bool dump_present(struct be_adapter *adapter) 3504 { 3505 u32 sliport_status = 0; 3506 3507 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET); 3508 return !!(sliport_status & SLIPORT_STATUS_DIP_MASK); 3509 } 3510 3511 int lancer_initiate_dump(struct be_adapter *adapter) 3512 { 3513 int status; 3514 3515 /* give firmware reset and diagnostic dump */ 3516 status = lancer_physdev_ctrl(adapter, PHYSDEV_CONTROL_FW_RESET_MASK | 3517 PHYSDEV_CONTROL_DD_MASK); 3518 if (status < 0) { 3519 dev_err(&adapter->pdev->dev, "Firmware reset failed\n"); 3520 return status; 3521 } 3522 3523 status = lancer_wait_idle(adapter); 3524 if (status) 3525 return status; 3526 3527 if (!dump_present(adapter)) { 3528 dev_err(&adapter->pdev->dev, "Dump image not present\n"); 3529 return -1; 3530 } 3531 3532 return 0; 3533 } 3534 3535 /* Uses sync mcc */ 3536 int be_cmd_enable_vf(struct be_adapter *adapter, u8 domain) 3537 { 3538 struct be_mcc_wrb *wrb; 3539 struct be_cmd_enable_disable_vf *req; 3540 int status; 3541 3542 if (BEx_chip(adapter)) 3543 return 0; 3544 3545 spin_lock_bh(&adapter->mcc_lock); 3546 3547 wrb = wrb_from_mccq(adapter); 3548 if (!wrb) { 3549 status = -EBUSY; 3550 goto err; 3551 } 3552 3553 req = embedded_payload(wrb); 3554 3555 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 3556 OPCODE_COMMON_ENABLE_DISABLE_VF, sizeof(*req), 3557 wrb, NULL); 3558 3559 req->hdr.domain = domain; 3560 req->enable = 1; 3561 status = be_mcc_notify_wait(adapter); 3562 err: 3563 spin_unlock_bh(&adapter->mcc_lock); 3564 return status; 3565 } 3566 3567 int be_cmd_intr_set(struct be_adapter *adapter, bool intr_enable) 3568 { 3569 struct be_mcc_wrb *wrb; 3570 struct be_cmd_req_intr_set *req; 3571 int status; 3572 3573 if (mutex_lock_interruptible(&adapter->mbox_lock)) 3574 return -1; 3575 3576 wrb = wrb_from_mbox(adapter); 3577 3578 req = embedded_payload(wrb); 3579 3580 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 3581 OPCODE_COMMON_SET_INTERRUPT_ENABLE, sizeof(*req), 3582 wrb, NULL); 3583 3584 req->intr_enabled = intr_enable; 3585 3586 status = be_mbox_notify_wait(adapter); 3587 3588 mutex_unlock(&adapter->mbox_lock); 3589 return status; 3590 } 3591 3592 int be_roce_mcc_cmd(void *netdev_handle, void *wrb_payload, 3593 int wrb_payload_size, u16 *cmd_status, u16 *ext_status) 3594 { 3595 struct be_adapter *adapter = netdev_priv(netdev_handle); 3596 struct be_mcc_wrb *wrb; 3597 struct be_cmd_req_hdr *hdr = (struct be_cmd_req_hdr *) wrb_payload; 3598 struct be_cmd_req_hdr *req; 3599 struct be_cmd_resp_hdr *resp; 3600 int status; 3601 3602 spin_lock_bh(&adapter->mcc_lock); 3603 3604 wrb = wrb_from_mccq(adapter); 3605 if (!wrb) { 3606 status = -EBUSY; 3607 goto err; 3608 } 3609 req = embedded_payload(wrb); 3610 resp = embedded_payload(wrb); 3611 3612 be_wrb_cmd_hdr_prepare(req, hdr->subsystem, 3613 hdr->opcode, wrb_payload_size, wrb, NULL); 3614 memcpy(req, wrb_payload, wrb_payload_size); 3615 be_dws_cpu_to_le(req, wrb_payload_size); 3616 3617 status = be_mcc_notify_wait(adapter); 3618 if (cmd_status) 3619 *cmd_status = (status & 0xffff); 3620 if (ext_status) 3621 *ext_status = 0; 3622 memcpy(wrb_payload, resp, sizeof(*resp) + resp->response_length); 3623 be_dws_le_to_cpu(wrb_payload, sizeof(*resp) + resp->response_length); 3624 err: 3625 spin_unlock_bh(&adapter->mcc_lock); 3626 return status; 3627 } 3628 EXPORT_SYMBOL(be_roce_mcc_cmd); 3629