19aebddd1SJeff Kirsher /* 240263820SVasundhara Volam * Copyright (C) 2005 - 2014 Emulex 39aebddd1SJeff Kirsher * All rights reserved. 49aebddd1SJeff Kirsher * 59aebddd1SJeff Kirsher * This program is free software; you can redistribute it and/or 69aebddd1SJeff Kirsher * modify it under the terms of the GNU General Public License version 2 79aebddd1SJeff Kirsher * as published by the Free Software Foundation. The full GNU General 89aebddd1SJeff Kirsher * Public License is included in this distribution in the file called COPYING. 99aebddd1SJeff Kirsher * 109aebddd1SJeff Kirsher * Contact Information: 119aebddd1SJeff Kirsher * linux-drivers@emulex.com 129aebddd1SJeff Kirsher * 139aebddd1SJeff Kirsher * Emulex 149aebddd1SJeff Kirsher * 3333 Susan Street 159aebddd1SJeff Kirsher * Costa Mesa, CA 92626 169aebddd1SJeff Kirsher */ 179aebddd1SJeff Kirsher 186a4ab669SParav Pandit #include <linux/module.h> 199aebddd1SJeff Kirsher #include "be.h" 209aebddd1SJeff Kirsher #include "be_cmds.h" 219aebddd1SJeff Kirsher 22f25b119cSPadmanabh Ratnakar static struct be_cmd_priv_map cmd_priv_map[] = { 23f25b119cSPadmanabh Ratnakar { 24f25b119cSPadmanabh Ratnakar OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, 25f25b119cSPadmanabh Ratnakar CMD_SUBSYSTEM_ETH, 26f25b119cSPadmanabh Ratnakar BE_PRIV_LNKMGMT | BE_PRIV_VHADM | 27f25b119cSPadmanabh Ratnakar BE_PRIV_DEVCFG | BE_PRIV_DEVSEC 28f25b119cSPadmanabh Ratnakar }, 29f25b119cSPadmanabh Ratnakar { 30f25b119cSPadmanabh Ratnakar OPCODE_COMMON_GET_FLOW_CONTROL, 31f25b119cSPadmanabh Ratnakar CMD_SUBSYSTEM_COMMON, 32f25b119cSPadmanabh Ratnakar BE_PRIV_LNKQUERY | BE_PRIV_VHADM | 33f25b119cSPadmanabh Ratnakar BE_PRIV_DEVCFG | BE_PRIV_DEVSEC 34f25b119cSPadmanabh Ratnakar }, 35f25b119cSPadmanabh Ratnakar { 36f25b119cSPadmanabh Ratnakar OPCODE_COMMON_SET_FLOW_CONTROL, 37f25b119cSPadmanabh Ratnakar CMD_SUBSYSTEM_COMMON, 38f25b119cSPadmanabh Ratnakar BE_PRIV_LNKMGMT | BE_PRIV_VHADM | 39f25b119cSPadmanabh Ratnakar BE_PRIV_DEVCFG | BE_PRIV_DEVSEC 40f25b119cSPadmanabh Ratnakar }, 41f25b119cSPadmanabh Ratnakar { 42f25b119cSPadmanabh Ratnakar OPCODE_ETH_GET_PPORT_STATS, 43f25b119cSPadmanabh Ratnakar CMD_SUBSYSTEM_ETH, 44f25b119cSPadmanabh Ratnakar BE_PRIV_LNKMGMT | BE_PRIV_VHADM | 45f25b119cSPadmanabh Ratnakar BE_PRIV_DEVCFG | BE_PRIV_DEVSEC 46f25b119cSPadmanabh Ratnakar }, 47f25b119cSPadmanabh Ratnakar { 48f25b119cSPadmanabh Ratnakar OPCODE_COMMON_GET_PHY_DETAILS, 49f25b119cSPadmanabh Ratnakar CMD_SUBSYSTEM_COMMON, 50f25b119cSPadmanabh Ratnakar BE_PRIV_LNKMGMT | BE_PRIV_VHADM | 51f25b119cSPadmanabh Ratnakar BE_PRIV_DEVCFG | BE_PRIV_DEVSEC 52f25b119cSPadmanabh Ratnakar } 53f25b119cSPadmanabh Ratnakar }; 54f25b119cSPadmanabh Ratnakar 55a2cc4e0bSSathya Perla static bool be_cmd_allowed(struct be_adapter *adapter, u8 opcode, u8 subsystem) 56f25b119cSPadmanabh Ratnakar { 57f25b119cSPadmanabh Ratnakar int i; 58f25b119cSPadmanabh Ratnakar int num_entries = sizeof(cmd_priv_map)/sizeof(struct be_cmd_priv_map); 59f25b119cSPadmanabh Ratnakar u32 cmd_privileges = adapter->cmd_privileges; 60f25b119cSPadmanabh Ratnakar 61f25b119cSPadmanabh Ratnakar for (i = 0; i < num_entries; i++) 62f25b119cSPadmanabh Ratnakar if (opcode == cmd_priv_map[i].opcode && 63f25b119cSPadmanabh Ratnakar subsystem == cmd_priv_map[i].subsystem) 64f25b119cSPadmanabh Ratnakar if (!(cmd_privileges & cmd_priv_map[i].priv_mask)) 65f25b119cSPadmanabh Ratnakar return false; 66f25b119cSPadmanabh Ratnakar 67f25b119cSPadmanabh Ratnakar return true; 68f25b119cSPadmanabh Ratnakar } 69f25b119cSPadmanabh Ratnakar 703de09455SSomnath Kotur static inline void *embedded_payload(struct be_mcc_wrb *wrb) 713de09455SSomnath Kotur { 723de09455SSomnath Kotur return wrb->payload.embedded_payload; 733de09455SSomnath Kotur } 749aebddd1SJeff Kirsher 759aebddd1SJeff Kirsher static void be_mcc_notify(struct be_adapter *adapter) 769aebddd1SJeff Kirsher { 779aebddd1SJeff Kirsher struct be_queue_info *mccq = &adapter->mcc_obj.q; 789aebddd1SJeff Kirsher u32 val = 0; 799aebddd1SJeff Kirsher 806589ade0SSathya Perla if (be_error(adapter)) 819aebddd1SJeff Kirsher return; 829aebddd1SJeff Kirsher 839aebddd1SJeff Kirsher val |= mccq->id & DB_MCCQ_RING_ID_MASK; 849aebddd1SJeff Kirsher val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT; 859aebddd1SJeff Kirsher 869aebddd1SJeff Kirsher wmb(); 879aebddd1SJeff Kirsher iowrite32(val, adapter->db + DB_MCCQ_OFFSET); 889aebddd1SJeff Kirsher } 899aebddd1SJeff Kirsher 909aebddd1SJeff Kirsher /* To check if valid bit is set, check the entire word as we don't know 919aebddd1SJeff Kirsher * the endianness of the data (old entry is host endian while a new entry is 929aebddd1SJeff Kirsher * little endian) */ 939aebddd1SJeff Kirsher static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl) 949aebddd1SJeff Kirsher { 959e9ff4b7SSathya Perla u32 flags; 969e9ff4b7SSathya Perla 979aebddd1SJeff Kirsher if (compl->flags != 0) { 989e9ff4b7SSathya Perla flags = le32_to_cpu(compl->flags); 999e9ff4b7SSathya Perla if (flags & CQE_FLAGS_VALID_MASK) { 1009e9ff4b7SSathya Perla compl->flags = flags; 1019aebddd1SJeff Kirsher return true; 1029aebddd1SJeff Kirsher } 1039aebddd1SJeff Kirsher } 1049e9ff4b7SSathya Perla return false; 1059e9ff4b7SSathya Perla } 1069aebddd1SJeff Kirsher 1079aebddd1SJeff Kirsher /* Need to reset the entire word that houses the valid bit */ 1089aebddd1SJeff Kirsher static inline void be_mcc_compl_use(struct be_mcc_compl *compl) 1099aebddd1SJeff Kirsher { 1109aebddd1SJeff Kirsher compl->flags = 0; 1119aebddd1SJeff Kirsher } 1129aebddd1SJeff Kirsher 113652bf646SPadmanabh Ratnakar static struct be_cmd_resp_hdr *be_decode_resp_hdr(u32 tag0, u32 tag1) 114652bf646SPadmanabh Ratnakar { 115652bf646SPadmanabh Ratnakar unsigned long addr; 116652bf646SPadmanabh Ratnakar 117652bf646SPadmanabh Ratnakar addr = tag1; 118652bf646SPadmanabh Ratnakar addr = ((addr << 16) << 16) | tag0; 119652bf646SPadmanabh Ratnakar return (void *)addr; 120652bf646SPadmanabh Ratnakar } 121652bf646SPadmanabh Ratnakar 1224c60005fSKalesh AP static bool be_skip_err_log(u8 opcode, u16 base_status, u16 addl_status) 1234c60005fSKalesh AP { 1244c60005fSKalesh AP if (base_status == MCC_STATUS_NOT_SUPPORTED || 1254c60005fSKalesh AP base_status == MCC_STATUS_ILLEGAL_REQUEST || 1264c60005fSKalesh AP addl_status == MCC_ADDL_STATUS_TOO_MANY_INTERFACES || 1274c60005fSKalesh AP (opcode == OPCODE_COMMON_WRITE_FLASHROM && 1284c60005fSKalesh AP (base_status == MCC_STATUS_ILLEGAL_FIELD || 1294c60005fSKalesh AP addl_status == MCC_ADDL_STATUS_FLASH_IMAGE_CRC_MISMATCH))) 1304c60005fSKalesh AP return true; 1314c60005fSKalesh AP else 1324c60005fSKalesh AP return false; 1334c60005fSKalesh AP } 1344c60005fSKalesh AP 135559b633fSSathya Perla /* Place holder for all the async MCC cmds wherein the caller is not in a busy 136559b633fSSathya Perla * loop (has not issued be_mcc_notify_wait()) 137559b633fSSathya Perla */ 138559b633fSSathya Perla static void be_async_cmd_process(struct be_adapter *adapter, 139559b633fSSathya Perla struct be_mcc_compl *compl, 140559b633fSSathya Perla struct be_cmd_resp_hdr *resp_hdr) 141559b633fSSathya Perla { 142559b633fSSathya Perla enum mcc_base_status base_status = base_status(compl->status); 143559b633fSSathya Perla u8 opcode = 0, subsystem = 0; 144559b633fSSathya Perla 145559b633fSSathya Perla if (resp_hdr) { 146559b633fSSathya Perla opcode = resp_hdr->opcode; 147559b633fSSathya Perla subsystem = resp_hdr->subsystem; 148559b633fSSathya Perla } 149559b633fSSathya Perla 150559b633fSSathya Perla if (opcode == OPCODE_LOWLEVEL_LOOPBACK_TEST && 151559b633fSSathya Perla subsystem == CMD_SUBSYSTEM_LOWLEVEL) { 152559b633fSSathya Perla complete(&adapter->et_cmd_compl); 153559b633fSSathya Perla return; 154559b633fSSathya Perla } 155559b633fSSathya Perla 156559b633fSSathya Perla if ((opcode == OPCODE_COMMON_WRITE_FLASHROM || 157559b633fSSathya Perla opcode == OPCODE_COMMON_WRITE_OBJECT) && 158559b633fSSathya Perla subsystem == CMD_SUBSYSTEM_COMMON) { 159559b633fSSathya Perla adapter->flash_status = compl->status; 160559b633fSSathya Perla complete(&adapter->et_cmd_compl); 161559b633fSSathya Perla return; 162559b633fSSathya Perla } 163559b633fSSathya Perla 164559b633fSSathya Perla if ((opcode == OPCODE_ETH_GET_STATISTICS || 165559b633fSSathya Perla opcode == OPCODE_ETH_GET_PPORT_STATS) && 166559b633fSSathya Perla subsystem == CMD_SUBSYSTEM_ETH && 167559b633fSSathya Perla base_status == MCC_STATUS_SUCCESS) { 168559b633fSSathya Perla be_parse_stats(adapter); 169559b633fSSathya Perla adapter->stats_cmd_sent = false; 170559b633fSSathya Perla return; 171559b633fSSathya Perla } 172559b633fSSathya Perla 173559b633fSSathya Perla if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES && 174559b633fSSathya Perla subsystem == CMD_SUBSYSTEM_COMMON) { 175559b633fSSathya Perla if (base_status == MCC_STATUS_SUCCESS) { 176559b633fSSathya Perla struct be_cmd_resp_get_cntl_addnl_attribs *resp = 177559b633fSSathya Perla (void *)resp_hdr; 178559b633fSSathya Perla adapter->drv_stats.be_on_die_temperature = 179559b633fSSathya Perla resp->on_die_temperature; 180559b633fSSathya Perla } else { 181559b633fSSathya Perla adapter->be_get_temp_freq = 0; 182559b633fSSathya Perla } 183559b633fSSathya Perla return; 184559b633fSSathya Perla } 185559b633fSSathya Perla } 186559b633fSSathya Perla 1879aebddd1SJeff Kirsher static int be_mcc_compl_process(struct be_adapter *adapter, 1889aebddd1SJeff Kirsher struct be_mcc_compl *compl) 1899aebddd1SJeff Kirsher { 1904c60005fSKalesh AP enum mcc_base_status base_status; 1914c60005fSKalesh AP enum mcc_addl_status addl_status; 192652bf646SPadmanabh Ratnakar struct be_cmd_resp_hdr *resp_hdr; 193652bf646SPadmanabh Ratnakar u8 opcode = 0, subsystem = 0; 1949aebddd1SJeff Kirsher 1959aebddd1SJeff Kirsher /* Just swap the status to host endian; mcc tag is opaquely copied 1969aebddd1SJeff Kirsher * from mcc_wrb */ 1979aebddd1SJeff Kirsher be_dws_le_to_cpu(compl, 4); 1989aebddd1SJeff Kirsher 1994c60005fSKalesh AP base_status = base_status(compl->status); 2004c60005fSKalesh AP addl_status = addl_status(compl->status); 20196c9b2e4SVasundhara Volam 202652bf646SPadmanabh Ratnakar resp_hdr = be_decode_resp_hdr(compl->tag0, compl->tag1); 203652bf646SPadmanabh Ratnakar if (resp_hdr) { 204652bf646SPadmanabh Ratnakar opcode = resp_hdr->opcode; 205652bf646SPadmanabh Ratnakar subsystem = resp_hdr->subsystem; 206652bf646SPadmanabh Ratnakar } 207652bf646SPadmanabh Ratnakar 208559b633fSSathya Perla be_async_cmd_process(adapter, compl, resp_hdr); 2095eeff635SSuresh Reddy 210559b633fSSathya Perla if (base_status != MCC_STATUS_SUCCESS && 211559b633fSSathya Perla !be_skip_err_log(opcode, base_status, addl_status)) { 21296c9b2e4SVasundhara Volam 2134c60005fSKalesh AP if (base_status == MCC_STATUS_UNAUTHORIZED_REQUEST) { 21497f1d8cdSVasundhara Volam dev_warn(&adapter->pdev->dev, 215522609f2SVasundhara Volam "VF is not privileged to issue opcode %d-%d\n", 21697f1d8cdSVasundhara Volam opcode, subsystem); 2179aebddd1SJeff Kirsher } else { 21897f1d8cdSVasundhara Volam dev_err(&adapter->pdev->dev, 21997f1d8cdSVasundhara Volam "opcode %d-%d failed:status %d-%d\n", 2204c60005fSKalesh AP opcode, subsystem, base_status, addl_status); 2219aebddd1SJeff Kirsher } 2229aebddd1SJeff Kirsher } 2234c60005fSKalesh AP return compl->status; 2249aebddd1SJeff Kirsher } 2259aebddd1SJeff Kirsher 2269aebddd1SJeff Kirsher /* Link state evt is a string of bytes; no need for endian swapping */ 2279aebddd1SJeff Kirsher static void be_async_link_state_process(struct be_adapter *adapter, 2283acf19d9SSathya Perla struct be_mcc_compl *compl) 2299aebddd1SJeff Kirsher { 2303acf19d9SSathya Perla struct be_async_event_link_state *evt = 2313acf19d9SSathya Perla (struct be_async_event_link_state *)compl; 2323acf19d9SSathya Perla 233b236916aSAjit Khaparde /* When link status changes, link speed must be re-queried from FW */ 23442f11cf2SAjit Khaparde adapter->phy.link_speed = -1; 235b236916aSAjit Khaparde 236bdce2ad7SSuresh Reddy /* On BEx the FW does not send a separate link status 237bdce2ad7SSuresh Reddy * notification for physical and logical link. 238bdce2ad7SSuresh Reddy * On other chips just process the logical link 239bdce2ad7SSuresh Reddy * status notification 240bdce2ad7SSuresh Reddy */ 241bdce2ad7SSuresh Reddy if (!BEx_chip(adapter) && 2422e177a5cSPadmanabh Ratnakar !(evt->port_link_status & LOGICAL_LINK_STATUS_MASK)) 2432e177a5cSPadmanabh Ratnakar return; 2442e177a5cSPadmanabh Ratnakar 245b236916aSAjit Khaparde /* For the initial link status do not rely on the ASYNC event as 246b236916aSAjit Khaparde * it may not be received in some cases. 247b236916aSAjit Khaparde */ 248b236916aSAjit Khaparde if (adapter->flags & BE_FLAGS_LINK_STATUS_INIT) 249bdce2ad7SSuresh Reddy be_link_status_update(adapter, 250bdce2ad7SSuresh Reddy evt->port_link_status & LINK_STATUS_MASK); 2519aebddd1SJeff Kirsher } 2529aebddd1SJeff Kirsher 2539aebddd1SJeff Kirsher /* Grp5 CoS Priority evt */ 2549aebddd1SJeff Kirsher static void be_async_grp5_cos_priority_process(struct be_adapter *adapter, 2553acf19d9SSathya Perla struct be_mcc_compl *compl) 2569aebddd1SJeff Kirsher { 2573acf19d9SSathya Perla struct be_async_event_grp5_cos_priority *evt = 2583acf19d9SSathya Perla (struct be_async_event_grp5_cos_priority *)compl; 2593acf19d9SSathya Perla 2609aebddd1SJeff Kirsher if (evt->valid) { 2619aebddd1SJeff Kirsher adapter->vlan_prio_bmap = evt->available_priority_bmap; 2629aebddd1SJeff Kirsher adapter->recommended_prio &= ~VLAN_PRIO_MASK; 2639aebddd1SJeff Kirsher adapter->recommended_prio = 2649aebddd1SJeff Kirsher evt->reco_default_priority << VLAN_PRIO_SHIFT; 2659aebddd1SJeff Kirsher } 2669aebddd1SJeff Kirsher } 2679aebddd1SJeff Kirsher 268323ff71eSSathya Perla /* Grp5 QOS Speed evt: qos_link_speed is in units of 10 Mbps */ 2699aebddd1SJeff Kirsher static void be_async_grp5_qos_speed_process(struct be_adapter *adapter, 2703acf19d9SSathya Perla struct be_mcc_compl *compl) 2719aebddd1SJeff Kirsher { 2723acf19d9SSathya Perla struct be_async_event_grp5_qos_link_speed *evt = 2733acf19d9SSathya Perla (struct be_async_event_grp5_qos_link_speed *)compl; 2743acf19d9SSathya Perla 275323ff71eSSathya Perla if (adapter->phy.link_speed >= 0 && 276323ff71eSSathya Perla evt->physical_port == adapter->port_num) 277323ff71eSSathya Perla adapter->phy.link_speed = le16_to_cpu(evt->qos_link_speed) * 10; 2789aebddd1SJeff Kirsher } 2799aebddd1SJeff Kirsher 2809aebddd1SJeff Kirsher /*Grp5 PVID evt*/ 2819aebddd1SJeff Kirsher static void be_async_grp5_pvid_state_process(struct be_adapter *adapter, 2823acf19d9SSathya Perla struct be_mcc_compl *compl) 2839aebddd1SJeff Kirsher { 2843acf19d9SSathya Perla struct be_async_event_grp5_pvid_state *evt = 2853acf19d9SSathya Perla (struct be_async_event_grp5_pvid_state *)compl; 2863acf19d9SSathya Perla 287bdac85b5SRavikumar Nelavelli if (evt->enabled) { 288939cf306SSomnath Kotur adapter->pvid = le16_to_cpu(evt->tag) & VLAN_VID_MASK; 289bdac85b5SRavikumar Nelavelli dev_info(&adapter->pdev->dev, "LPVID: %d\n", adapter->pvid); 290bdac85b5SRavikumar Nelavelli } else { 2919aebddd1SJeff Kirsher adapter->pvid = 0; 2929aebddd1SJeff Kirsher } 293bdac85b5SRavikumar Nelavelli } 2949aebddd1SJeff Kirsher 2959aebddd1SJeff Kirsher static void be_async_grp5_evt_process(struct be_adapter *adapter, 2963acf19d9SSathya Perla struct be_mcc_compl *compl) 2979aebddd1SJeff Kirsher { 2983acf19d9SSathya Perla u8 event_type = (compl->flags >> ASYNC_EVENT_TYPE_SHIFT) & 2993acf19d9SSathya Perla ASYNC_EVENT_TYPE_MASK; 3009aebddd1SJeff Kirsher 3019aebddd1SJeff Kirsher switch (event_type) { 3029aebddd1SJeff Kirsher case ASYNC_EVENT_COS_PRIORITY: 3033acf19d9SSathya Perla be_async_grp5_cos_priority_process(adapter, compl); 3049aebddd1SJeff Kirsher break; 3059aebddd1SJeff Kirsher case ASYNC_EVENT_QOS_SPEED: 3063acf19d9SSathya Perla be_async_grp5_qos_speed_process(adapter, compl); 3079aebddd1SJeff Kirsher break; 3089aebddd1SJeff Kirsher case ASYNC_EVENT_PVID_STATE: 3093acf19d9SSathya Perla be_async_grp5_pvid_state_process(adapter, compl); 3109aebddd1SJeff Kirsher break; 3119aebddd1SJeff Kirsher default: 31205ccaa2bSVasundhara Volam dev_warn(&adapter->pdev->dev, "Unknown grp5 event 0x%x!\n", 31305ccaa2bSVasundhara Volam event_type); 3149aebddd1SJeff Kirsher break; 3159aebddd1SJeff Kirsher } 3169aebddd1SJeff Kirsher } 3179aebddd1SJeff Kirsher 318bc0c3405SAjit Khaparde static void be_async_dbg_evt_process(struct be_adapter *adapter, 3193acf19d9SSathya Perla struct be_mcc_compl *cmp) 320bc0c3405SAjit Khaparde { 321bc0c3405SAjit Khaparde u8 event_type = 0; 322bc0c3405SAjit Khaparde struct be_async_event_qnq *evt = (struct be_async_event_qnq *) cmp; 323bc0c3405SAjit Khaparde 3243acf19d9SSathya Perla event_type = (cmp->flags >> ASYNC_EVENT_TYPE_SHIFT) & 3253acf19d9SSathya Perla ASYNC_EVENT_TYPE_MASK; 326bc0c3405SAjit Khaparde 327bc0c3405SAjit Khaparde switch (event_type) { 328bc0c3405SAjit Khaparde case ASYNC_DEBUG_EVENT_TYPE_QNQ: 329bc0c3405SAjit Khaparde if (evt->valid) 330bc0c3405SAjit Khaparde adapter->qnq_vid = le16_to_cpu(evt->vlan_tag); 331bc0c3405SAjit Khaparde adapter->flags |= BE_FLAGS_QNQ_ASYNC_EVT_RCVD; 332bc0c3405SAjit Khaparde break; 333bc0c3405SAjit Khaparde default: 33405ccaa2bSVasundhara Volam dev_warn(&adapter->pdev->dev, "Unknown debug event 0x%x!\n", 33505ccaa2bSVasundhara Volam event_type); 336bc0c3405SAjit Khaparde break; 337bc0c3405SAjit Khaparde } 338bc0c3405SAjit Khaparde } 339bc0c3405SAjit Khaparde 3403acf19d9SSathya Perla static inline bool is_link_state_evt(u32 flags) 3419aebddd1SJeff Kirsher { 3423acf19d9SSathya Perla return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) == 3439aebddd1SJeff Kirsher ASYNC_EVENT_CODE_LINK_STATE; 3449aebddd1SJeff Kirsher } 3459aebddd1SJeff Kirsher 3463acf19d9SSathya Perla static inline bool is_grp5_evt(u32 flags) 3479aebddd1SJeff Kirsher { 3483acf19d9SSathya Perla return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) == 3493acf19d9SSathya Perla ASYNC_EVENT_CODE_GRP_5; 3509aebddd1SJeff Kirsher } 3519aebddd1SJeff Kirsher 3523acf19d9SSathya Perla static inline bool is_dbg_evt(u32 flags) 353bc0c3405SAjit Khaparde { 3543acf19d9SSathya Perla return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) == 3553acf19d9SSathya Perla ASYNC_EVENT_CODE_QNQ; 3563acf19d9SSathya Perla } 3573acf19d9SSathya Perla 3583acf19d9SSathya Perla static void be_mcc_event_process(struct be_adapter *adapter, 3593acf19d9SSathya Perla struct be_mcc_compl *compl) 3603acf19d9SSathya Perla { 3613acf19d9SSathya Perla if (is_link_state_evt(compl->flags)) 3623acf19d9SSathya Perla be_async_link_state_process(adapter, compl); 3633acf19d9SSathya Perla else if (is_grp5_evt(compl->flags)) 3643acf19d9SSathya Perla be_async_grp5_evt_process(adapter, compl); 3653acf19d9SSathya Perla else if (is_dbg_evt(compl->flags)) 3663acf19d9SSathya Perla be_async_dbg_evt_process(adapter, compl); 367bc0c3405SAjit Khaparde } 368bc0c3405SAjit Khaparde 3699aebddd1SJeff Kirsher static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter) 3709aebddd1SJeff Kirsher { 3719aebddd1SJeff Kirsher struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq; 3729aebddd1SJeff Kirsher struct be_mcc_compl *compl = queue_tail_node(mcc_cq); 3739aebddd1SJeff Kirsher 3749aebddd1SJeff Kirsher if (be_mcc_compl_is_new(compl)) { 3759aebddd1SJeff Kirsher queue_tail_inc(mcc_cq); 3769aebddd1SJeff Kirsher return compl; 3779aebddd1SJeff Kirsher } 3789aebddd1SJeff Kirsher return NULL; 3799aebddd1SJeff Kirsher } 3809aebddd1SJeff Kirsher 3819aebddd1SJeff Kirsher void be_async_mcc_enable(struct be_adapter *adapter) 3829aebddd1SJeff Kirsher { 3839aebddd1SJeff Kirsher spin_lock_bh(&adapter->mcc_cq_lock); 3849aebddd1SJeff Kirsher 3859aebddd1SJeff Kirsher be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0); 3869aebddd1SJeff Kirsher adapter->mcc_obj.rearm_cq = true; 3879aebddd1SJeff Kirsher 3889aebddd1SJeff Kirsher spin_unlock_bh(&adapter->mcc_cq_lock); 3899aebddd1SJeff Kirsher } 3909aebddd1SJeff Kirsher 3919aebddd1SJeff Kirsher void be_async_mcc_disable(struct be_adapter *adapter) 3929aebddd1SJeff Kirsher { 393a323d9bfSSathya Perla spin_lock_bh(&adapter->mcc_cq_lock); 394a323d9bfSSathya Perla 3959aebddd1SJeff Kirsher adapter->mcc_obj.rearm_cq = false; 396a323d9bfSSathya Perla be_cq_notify(adapter, adapter->mcc_obj.cq.id, false, 0); 397a323d9bfSSathya Perla 398a323d9bfSSathya Perla spin_unlock_bh(&adapter->mcc_cq_lock); 3999aebddd1SJeff Kirsher } 4009aebddd1SJeff Kirsher 40110ef9ab4SSathya Perla int be_process_mcc(struct be_adapter *adapter) 4029aebddd1SJeff Kirsher { 4039aebddd1SJeff Kirsher struct be_mcc_compl *compl; 40410ef9ab4SSathya Perla int num = 0, status = 0; 4059aebddd1SJeff Kirsher struct be_mcc_obj *mcc_obj = &adapter->mcc_obj; 4069aebddd1SJeff Kirsher 407072a9c48SAmerigo Wang spin_lock(&adapter->mcc_cq_lock); 4083acf19d9SSathya Perla 4099aebddd1SJeff Kirsher while ((compl = be_mcc_compl_get(adapter))) { 4109aebddd1SJeff Kirsher if (compl->flags & CQE_FLAGS_ASYNC_MASK) { 4113acf19d9SSathya Perla be_mcc_event_process(adapter, compl); 4129aebddd1SJeff Kirsher } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) { 41310ef9ab4SSathya Perla status = be_mcc_compl_process(adapter, compl); 4149aebddd1SJeff Kirsher atomic_dec(&mcc_obj->q.used); 4159aebddd1SJeff Kirsher } 4169aebddd1SJeff Kirsher be_mcc_compl_use(compl); 4179aebddd1SJeff Kirsher num++; 4189aebddd1SJeff Kirsher } 4199aebddd1SJeff Kirsher 42010ef9ab4SSathya Perla if (num) 42110ef9ab4SSathya Perla be_cq_notify(adapter, mcc_obj->cq.id, mcc_obj->rearm_cq, num); 42210ef9ab4SSathya Perla 423072a9c48SAmerigo Wang spin_unlock(&adapter->mcc_cq_lock); 42410ef9ab4SSathya Perla return status; 4259aebddd1SJeff Kirsher } 4269aebddd1SJeff Kirsher 4279aebddd1SJeff Kirsher /* Wait till no more pending mcc requests are present */ 4289aebddd1SJeff Kirsher static int be_mcc_wait_compl(struct be_adapter *adapter) 4299aebddd1SJeff Kirsher { 4309aebddd1SJeff Kirsher #define mcc_timeout 120000 /* 12s timeout */ 43110ef9ab4SSathya Perla int i, status = 0; 4329aebddd1SJeff Kirsher struct be_mcc_obj *mcc_obj = &adapter->mcc_obj; 4339aebddd1SJeff Kirsher 4346589ade0SSathya Perla for (i = 0; i < mcc_timeout; i++) { 4356589ade0SSathya Perla if (be_error(adapter)) 4369aebddd1SJeff Kirsher return -EIO; 4379aebddd1SJeff Kirsher 438072a9c48SAmerigo Wang local_bh_disable(); 43910ef9ab4SSathya Perla status = be_process_mcc(adapter); 440072a9c48SAmerigo Wang local_bh_enable(); 4419aebddd1SJeff Kirsher 4429aebddd1SJeff Kirsher if (atomic_read(&mcc_obj->q.used) == 0) 4439aebddd1SJeff Kirsher break; 4449aebddd1SJeff Kirsher udelay(100); 4459aebddd1SJeff Kirsher } 4469aebddd1SJeff Kirsher if (i == mcc_timeout) { 4476589ade0SSathya Perla dev_err(&adapter->pdev->dev, "FW not responding\n"); 4486589ade0SSathya Perla adapter->fw_timeout = true; 449652bf646SPadmanabh Ratnakar return -EIO; 4509aebddd1SJeff Kirsher } 4519aebddd1SJeff Kirsher return status; 4529aebddd1SJeff Kirsher } 4539aebddd1SJeff Kirsher 4549aebddd1SJeff Kirsher /* Notify MCC requests and wait for completion */ 4559aebddd1SJeff Kirsher static int be_mcc_notify_wait(struct be_adapter *adapter) 4569aebddd1SJeff Kirsher { 457652bf646SPadmanabh Ratnakar int status; 458652bf646SPadmanabh Ratnakar struct be_mcc_wrb *wrb; 459652bf646SPadmanabh Ratnakar struct be_mcc_obj *mcc_obj = &adapter->mcc_obj; 460652bf646SPadmanabh Ratnakar u16 index = mcc_obj->q.head; 461652bf646SPadmanabh Ratnakar struct be_cmd_resp_hdr *resp; 462652bf646SPadmanabh Ratnakar 463652bf646SPadmanabh Ratnakar index_dec(&index, mcc_obj->q.len); 464652bf646SPadmanabh Ratnakar wrb = queue_index_node(&mcc_obj->q, index); 465652bf646SPadmanabh Ratnakar 466652bf646SPadmanabh Ratnakar resp = be_decode_resp_hdr(wrb->tag0, wrb->tag1); 467652bf646SPadmanabh Ratnakar 4689aebddd1SJeff Kirsher be_mcc_notify(adapter); 469652bf646SPadmanabh Ratnakar 470652bf646SPadmanabh Ratnakar status = be_mcc_wait_compl(adapter); 471652bf646SPadmanabh Ratnakar if (status == -EIO) 472652bf646SPadmanabh Ratnakar goto out; 473652bf646SPadmanabh Ratnakar 4744c60005fSKalesh AP status = (resp->base_status | 4754c60005fSKalesh AP ((resp->addl_status & CQE_ADDL_STATUS_MASK) << 4764c60005fSKalesh AP CQE_ADDL_STATUS_SHIFT)); 477652bf646SPadmanabh Ratnakar out: 478652bf646SPadmanabh Ratnakar return status; 4799aebddd1SJeff Kirsher } 4809aebddd1SJeff Kirsher 4819aebddd1SJeff Kirsher static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db) 4829aebddd1SJeff Kirsher { 4839aebddd1SJeff Kirsher int msecs = 0; 4849aebddd1SJeff Kirsher u32 ready; 4859aebddd1SJeff Kirsher 4866589ade0SSathya Perla do { 4876589ade0SSathya Perla if (be_error(adapter)) 4889aebddd1SJeff Kirsher return -EIO; 4899aebddd1SJeff Kirsher 4909aebddd1SJeff Kirsher ready = ioread32(db); 491434b3648SSathya Perla if (ready == 0xffffffff) 4929aebddd1SJeff Kirsher return -1; 4939aebddd1SJeff Kirsher 4949aebddd1SJeff Kirsher ready &= MPU_MAILBOX_DB_RDY_MASK; 4959aebddd1SJeff Kirsher if (ready) 4969aebddd1SJeff Kirsher break; 4979aebddd1SJeff Kirsher 4989aebddd1SJeff Kirsher if (msecs > 4000) { 4996589ade0SSathya Perla dev_err(&adapter->pdev->dev, "FW not responding\n"); 5006589ade0SSathya Perla adapter->fw_timeout = true; 501f67ef7baSPadmanabh Ratnakar be_detect_error(adapter); 5029aebddd1SJeff Kirsher return -1; 5039aebddd1SJeff Kirsher } 5049aebddd1SJeff Kirsher 5059aebddd1SJeff Kirsher msleep(1); 5069aebddd1SJeff Kirsher msecs++; 5079aebddd1SJeff Kirsher } while (true); 5089aebddd1SJeff Kirsher 5099aebddd1SJeff Kirsher return 0; 5109aebddd1SJeff Kirsher } 5119aebddd1SJeff Kirsher 5129aebddd1SJeff Kirsher /* 5139aebddd1SJeff Kirsher * Insert the mailbox address into the doorbell in two steps 5149aebddd1SJeff Kirsher * Polls on the mbox doorbell till a command completion (or a timeout) occurs 5159aebddd1SJeff Kirsher */ 5169aebddd1SJeff Kirsher static int be_mbox_notify_wait(struct be_adapter *adapter) 5179aebddd1SJeff Kirsher { 5189aebddd1SJeff Kirsher int status; 5199aebddd1SJeff Kirsher u32 val = 0; 5209aebddd1SJeff Kirsher void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET; 5219aebddd1SJeff Kirsher struct be_dma_mem *mbox_mem = &adapter->mbox_mem; 5229aebddd1SJeff Kirsher struct be_mcc_mailbox *mbox = mbox_mem->va; 5239aebddd1SJeff Kirsher struct be_mcc_compl *compl = &mbox->compl; 5249aebddd1SJeff Kirsher 5259aebddd1SJeff Kirsher /* wait for ready to be set */ 5269aebddd1SJeff Kirsher status = be_mbox_db_ready_wait(adapter, db); 5279aebddd1SJeff Kirsher if (status != 0) 5289aebddd1SJeff Kirsher return status; 5299aebddd1SJeff Kirsher 5309aebddd1SJeff Kirsher val |= MPU_MAILBOX_DB_HI_MASK; 5319aebddd1SJeff Kirsher /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */ 5329aebddd1SJeff Kirsher val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2; 5339aebddd1SJeff Kirsher iowrite32(val, db); 5349aebddd1SJeff Kirsher 5359aebddd1SJeff Kirsher /* wait for ready to be set */ 5369aebddd1SJeff Kirsher status = be_mbox_db_ready_wait(adapter, db); 5379aebddd1SJeff Kirsher if (status != 0) 5389aebddd1SJeff Kirsher return status; 5399aebddd1SJeff Kirsher 5409aebddd1SJeff Kirsher val = 0; 5419aebddd1SJeff Kirsher /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */ 5429aebddd1SJeff Kirsher val |= (u32)(mbox_mem->dma >> 4) << 2; 5439aebddd1SJeff Kirsher iowrite32(val, db); 5449aebddd1SJeff Kirsher 5459aebddd1SJeff Kirsher status = be_mbox_db_ready_wait(adapter, db); 5469aebddd1SJeff Kirsher if (status != 0) 5479aebddd1SJeff Kirsher return status; 5489aebddd1SJeff Kirsher 5499aebddd1SJeff Kirsher /* A cq entry has been made now */ 5509aebddd1SJeff Kirsher if (be_mcc_compl_is_new(compl)) { 5519aebddd1SJeff Kirsher status = be_mcc_compl_process(adapter, &mbox->compl); 5529aebddd1SJeff Kirsher be_mcc_compl_use(compl); 5539aebddd1SJeff Kirsher if (status) 5549aebddd1SJeff Kirsher return status; 5559aebddd1SJeff Kirsher } else { 5569aebddd1SJeff Kirsher dev_err(&adapter->pdev->dev, "invalid mailbox completion\n"); 5579aebddd1SJeff Kirsher return -1; 5589aebddd1SJeff Kirsher } 5599aebddd1SJeff Kirsher return 0; 5609aebddd1SJeff Kirsher } 5619aebddd1SJeff Kirsher 562c5b3ad4cSSathya Perla static u16 be_POST_stage_get(struct be_adapter *adapter) 5639aebddd1SJeff Kirsher { 5649aebddd1SJeff Kirsher u32 sem; 5659aebddd1SJeff Kirsher 566c5b3ad4cSSathya Perla if (BEx_chip(adapter)) 567c5b3ad4cSSathya Perla sem = ioread32(adapter->csr + SLIPORT_SEMAPHORE_OFFSET_BEx); 5689aebddd1SJeff Kirsher else 569c5b3ad4cSSathya Perla pci_read_config_dword(adapter->pdev, 570c5b3ad4cSSathya Perla SLIPORT_SEMAPHORE_OFFSET_SH, &sem); 571c5b3ad4cSSathya Perla 572c5b3ad4cSSathya Perla return sem & POST_STAGE_MASK; 5739aebddd1SJeff Kirsher } 5749aebddd1SJeff Kirsher 57587f20c26SGavin Shan static int lancer_wait_ready(struct be_adapter *adapter) 576bf99e50dSPadmanabh Ratnakar { 577bf99e50dSPadmanabh Ratnakar #define SLIPORT_READY_TIMEOUT 30 578bf99e50dSPadmanabh Ratnakar u32 sliport_status; 579bf99e50dSPadmanabh Ratnakar int status = 0, i; 580bf99e50dSPadmanabh Ratnakar 581bf99e50dSPadmanabh Ratnakar for (i = 0; i < SLIPORT_READY_TIMEOUT; i++) { 582bf99e50dSPadmanabh Ratnakar sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET); 583bf99e50dSPadmanabh Ratnakar if (sliport_status & SLIPORT_STATUS_RDY_MASK) 584bf99e50dSPadmanabh Ratnakar break; 585bf99e50dSPadmanabh Ratnakar 586bf99e50dSPadmanabh Ratnakar msleep(1000); 587bf99e50dSPadmanabh Ratnakar } 588bf99e50dSPadmanabh Ratnakar 589bf99e50dSPadmanabh Ratnakar if (i == SLIPORT_READY_TIMEOUT) 590bf99e50dSPadmanabh Ratnakar status = -1; 591bf99e50dSPadmanabh Ratnakar 592bf99e50dSPadmanabh Ratnakar return status; 593bf99e50dSPadmanabh Ratnakar } 594bf99e50dSPadmanabh Ratnakar 59567297ad8SPadmanabh Ratnakar static bool lancer_provisioning_error(struct be_adapter *adapter) 59667297ad8SPadmanabh Ratnakar { 59767297ad8SPadmanabh Ratnakar u32 sliport_status = 0, sliport_err1 = 0, sliport_err2 = 0; 59867297ad8SPadmanabh Ratnakar sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET); 59967297ad8SPadmanabh Ratnakar if (sliport_status & SLIPORT_STATUS_ERR_MASK) { 600a2cc4e0bSSathya Perla sliport_err1 = ioread32(adapter->db + SLIPORT_ERROR1_OFFSET); 601a2cc4e0bSSathya Perla sliport_err2 = ioread32(adapter->db + SLIPORT_ERROR2_OFFSET); 60267297ad8SPadmanabh Ratnakar 60367297ad8SPadmanabh Ratnakar if (sliport_err1 == SLIPORT_ERROR_NO_RESOURCE1 && 60467297ad8SPadmanabh Ratnakar sliport_err2 == SLIPORT_ERROR_NO_RESOURCE2) 60567297ad8SPadmanabh Ratnakar return true; 60667297ad8SPadmanabh Ratnakar } 60767297ad8SPadmanabh Ratnakar return false; 60867297ad8SPadmanabh Ratnakar } 60967297ad8SPadmanabh Ratnakar 610bf99e50dSPadmanabh Ratnakar int lancer_test_and_set_rdy_state(struct be_adapter *adapter) 611bf99e50dSPadmanabh Ratnakar { 612bf99e50dSPadmanabh Ratnakar int status; 613bf99e50dSPadmanabh Ratnakar u32 sliport_status, err, reset_needed; 61467297ad8SPadmanabh Ratnakar bool resource_error; 61567297ad8SPadmanabh Ratnakar 61667297ad8SPadmanabh Ratnakar resource_error = lancer_provisioning_error(adapter); 61767297ad8SPadmanabh Ratnakar if (resource_error) 61801e5b2c4SSomnath Kotur return -EAGAIN; 61967297ad8SPadmanabh Ratnakar 620bf99e50dSPadmanabh Ratnakar status = lancer_wait_ready(adapter); 621bf99e50dSPadmanabh Ratnakar if (!status) { 622bf99e50dSPadmanabh Ratnakar sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET); 623bf99e50dSPadmanabh Ratnakar err = sliport_status & SLIPORT_STATUS_ERR_MASK; 624bf99e50dSPadmanabh Ratnakar reset_needed = sliport_status & SLIPORT_STATUS_RN_MASK; 625bf99e50dSPadmanabh Ratnakar if (err && reset_needed) { 626bf99e50dSPadmanabh Ratnakar iowrite32(SLI_PORT_CONTROL_IP_MASK, 627bf99e50dSPadmanabh Ratnakar adapter->db + SLIPORT_CONTROL_OFFSET); 628bf99e50dSPadmanabh Ratnakar 629bf99e50dSPadmanabh Ratnakar /* check adapter has corrected the error */ 630bf99e50dSPadmanabh Ratnakar status = lancer_wait_ready(adapter); 631bf99e50dSPadmanabh Ratnakar sliport_status = ioread32(adapter->db + 632bf99e50dSPadmanabh Ratnakar SLIPORT_STATUS_OFFSET); 633bf99e50dSPadmanabh Ratnakar sliport_status &= (SLIPORT_STATUS_ERR_MASK | 634bf99e50dSPadmanabh Ratnakar SLIPORT_STATUS_RN_MASK); 635bf99e50dSPadmanabh Ratnakar if (status || sliport_status) 636bf99e50dSPadmanabh Ratnakar status = -1; 637bf99e50dSPadmanabh Ratnakar } else if (err || reset_needed) { 638bf99e50dSPadmanabh Ratnakar status = -1; 639bf99e50dSPadmanabh Ratnakar } 640bf99e50dSPadmanabh Ratnakar } 64167297ad8SPadmanabh Ratnakar /* Stop error recovery if error is not recoverable. 64267297ad8SPadmanabh Ratnakar * No resource error is temporary errors and will go away 64367297ad8SPadmanabh Ratnakar * when PF provisions resources. 64467297ad8SPadmanabh Ratnakar */ 64567297ad8SPadmanabh Ratnakar resource_error = lancer_provisioning_error(adapter); 64601e5b2c4SSomnath Kotur if (resource_error) 64701e5b2c4SSomnath Kotur status = -EAGAIN; 64867297ad8SPadmanabh Ratnakar 649bf99e50dSPadmanabh Ratnakar return status; 650bf99e50dSPadmanabh Ratnakar } 651bf99e50dSPadmanabh Ratnakar 652bf99e50dSPadmanabh Ratnakar int be_fw_wait_ready(struct be_adapter *adapter) 6539aebddd1SJeff Kirsher { 6549aebddd1SJeff Kirsher u16 stage; 6559aebddd1SJeff Kirsher int status, timeout = 0; 6569aebddd1SJeff Kirsher struct device *dev = &adapter->pdev->dev; 6579aebddd1SJeff Kirsher 658bf99e50dSPadmanabh Ratnakar if (lancer_chip(adapter)) { 659bf99e50dSPadmanabh Ratnakar status = lancer_wait_ready(adapter); 660bf99e50dSPadmanabh Ratnakar return status; 661bf99e50dSPadmanabh Ratnakar } 662bf99e50dSPadmanabh Ratnakar 6639aebddd1SJeff Kirsher do { 664c5b3ad4cSSathya Perla stage = be_POST_stage_get(adapter); 66566d29cbcSGavin Shan if (stage == POST_STAGE_ARMFW_RDY) 66666d29cbcSGavin Shan return 0; 66766d29cbcSGavin Shan 668a2cc4e0bSSathya Perla dev_info(dev, "Waiting for POST, %ds elapsed\n", timeout); 6699aebddd1SJeff Kirsher if (msleep_interruptible(2000)) { 6709aebddd1SJeff Kirsher dev_err(dev, "Waiting for POST aborted\n"); 6719aebddd1SJeff Kirsher return -EINTR; 6729aebddd1SJeff Kirsher } 6739aebddd1SJeff Kirsher timeout += 2; 6743ab81b5fSSomnath Kotur } while (timeout < 60); 6759aebddd1SJeff Kirsher 6769aebddd1SJeff Kirsher dev_err(dev, "POST timeout; stage=0x%x\n", stage); 6779aebddd1SJeff Kirsher return -1; 6789aebddd1SJeff Kirsher } 6799aebddd1SJeff Kirsher 6809aebddd1SJeff Kirsher 6819aebddd1SJeff Kirsher static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb) 6829aebddd1SJeff Kirsher { 6839aebddd1SJeff Kirsher return &wrb->payload.sgl[0]; 6849aebddd1SJeff Kirsher } 6859aebddd1SJeff Kirsher 686a2cc4e0bSSathya Perla static inline void fill_wrb_tags(struct be_mcc_wrb *wrb, unsigned long addr) 687bea50988SSathya Perla { 688bea50988SSathya Perla wrb->tag0 = addr & 0xFFFFFFFF; 689bea50988SSathya Perla wrb->tag1 = upper_32_bits(addr); 690bea50988SSathya Perla } 6919aebddd1SJeff Kirsher 6929aebddd1SJeff Kirsher /* Don't touch the hdr after it's prepared */ 693106df1e3SSomnath Kotur /* mem will be NULL for embedded commands */ 694106df1e3SSomnath Kotur static void be_wrb_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr, 695106df1e3SSomnath Kotur u8 subsystem, u8 opcode, int cmd_len, 696a2cc4e0bSSathya Perla struct be_mcc_wrb *wrb, 697a2cc4e0bSSathya Perla struct be_dma_mem *mem) 6989aebddd1SJeff Kirsher { 699106df1e3SSomnath Kotur struct be_sge *sge; 700106df1e3SSomnath Kotur 7019aebddd1SJeff Kirsher req_hdr->opcode = opcode; 7029aebddd1SJeff Kirsher req_hdr->subsystem = subsystem; 7039aebddd1SJeff Kirsher req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr)); 7049aebddd1SJeff Kirsher req_hdr->version = 0; 705bea50988SSathya Perla fill_wrb_tags(wrb, (ulong) req_hdr); 706106df1e3SSomnath Kotur wrb->payload_length = cmd_len; 707106df1e3SSomnath Kotur if (mem) { 708106df1e3SSomnath Kotur wrb->embedded |= (1 & MCC_WRB_SGE_CNT_MASK) << 709106df1e3SSomnath Kotur MCC_WRB_SGE_CNT_SHIFT; 710106df1e3SSomnath Kotur sge = nonembedded_sgl(wrb); 711106df1e3SSomnath Kotur sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma)); 712106df1e3SSomnath Kotur sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF); 713106df1e3SSomnath Kotur sge->len = cpu_to_le32(mem->size); 714106df1e3SSomnath Kotur } else 715106df1e3SSomnath Kotur wrb->embedded |= MCC_WRB_EMBEDDED_MASK; 716106df1e3SSomnath Kotur be_dws_cpu_to_le(wrb, 8); 7179aebddd1SJeff Kirsher } 7189aebddd1SJeff Kirsher 7199aebddd1SJeff Kirsher static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages, 7209aebddd1SJeff Kirsher struct be_dma_mem *mem) 7219aebddd1SJeff Kirsher { 7229aebddd1SJeff Kirsher int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages); 7239aebddd1SJeff Kirsher u64 dma = (u64)mem->dma; 7249aebddd1SJeff Kirsher 7259aebddd1SJeff Kirsher for (i = 0; i < buf_pages; i++) { 7269aebddd1SJeff Kirsher pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF); 7279aebddd1SJeff Kirsher pages[i].hi = cpu_to_le32(upper_32_bits(dma)); 7289aebddd1SJeff Kirsher dma += PAGE_SIZE_4K; 7299aebddd1SJeff Kirsher } 7309aebddd1SJeff Kirsher } 7319aebddd1SJeff Kirsher 7329aebddd1SJeff Kirsher static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter) 7339aebddd1SJeff Kirsher { 7349aebddd1SJeff Kirsher struct be_dma_mem *mbox_mem = &adapter->mbox_mem; 7359aebddd1SJeff Kirsher struct be_mcc_wrb *wrb 7369aebddd1SJeff Kirsher = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb; 7379aebddd1SJeff Kirsher memset(wrb, 0, sizeof(*wrb)); 7389aebddd1SJeff Kirsher return wrb; 7399aebddd1SJeff Kirsher } 7409aebddd1SJeff Kirsher 7419aebddd1SJeff Kirsher static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter) 7429aebddd1SJeff Kirsher { 7439aebddd1SJeff Kirsher struct be_queue_info *mccq = &adapter->mcc_obj.q; 7449aebddd1SJeff Kirsher struct be_mcc_wrb *wrb; 7459aebddd1SJeff Kirsher 746aa790db9SPadmanabh Ratnakar if (!mccq->created) 747aa790db9SPadmanabh Ratnakar return NULL; 748aa790db9SPadmanabh Ratnakar 7494d277125SVasundhara Volam if (atomic_read(&mccq->used) >= mccq->len) 7509aebddd1SJeff Kirsher return NULL; 7519aebddd1SJeff Kirsher 7529aebddd1SJeff Kirsher wrb = queue_head_node(mccq); 7539aebddd1SJeff Kirsher queue_head_inc(mccq); 7549aebddd1SJeff Kirsher atomic_inc(&mccq->used); 7559aebddd1SJeff Kirsher memset(wrb, 0, sizeof(*wrb)); 7569aebddd1SJeff Kirsher return wrb; 7579aebddd1SJeff Kirsher } 7589aebddd1SJeff Kirsher 759bea50988SSathya Perla static bool use_mcc(struct be_adapter *adapter) 760bea50988SSathya Perla { 761bea50988SSathya Perla return adapter->mcc_obj.q.created; 762bea50988SSathya Perla } 763bea50988SSathya Perla 764bea50988SSathya Perla /* Must be used only in process context */ 765bea50988SSathya Perla static int be_cmd_lock(struct be_adapter *adapter) 766bea50988SSathya Perla { 767bea50988SSathya Perla if (use_mcc(adapter)) { 768bea50988SSathya Perla spin_lock_bh(&adapter->mcc_lock); 769bea50988SSathya Perla return 0; 770bea50988SSathya Perla } else { 771bea50988SSathya Perla return mutex_lock_interruptible(&adapter->mbox_lock); 772bea50988SSathya Perla } 773bea50988SSathya Perla } 774bea50988SSathya Perla 775bea50988SSathya Perla /* Must be used only in process context */ 776bea50988SSathya Perla static void be_cmd_unlock(struct be_adapter *adapter) 777bea50988SSathya Perla { 778bea50988SSathya Perla if (use_mcc(adapter)) 779bea50988SSathya Perla spin_unlock_bh(&adapter->mcc_lock); 780bea50988SSathya Perla else 781bea50988SSathya Perla return mutex_unlock(&adapter->mbox_lock); 782bea50988SSathya Perla } 783bea50988SSathya Perla 784bea50988SSathya Perla static struct be_mcc_wrb *be_cmd_copy(struct be_adapter *adapter, 785bea50988SSathya Perla struct be_mcc_wrb *wrb) 786bea50988SSathya Perla { 787bea50988SSathya Perla struct be_mcc_wrb *dest_wrb; 788bea50988SSathya Perla 789bea50988SSathya Perla if (use_mcc(adapter)) { 790bea50988SSathya Perla dest_wrb = wrb_from_mccq(adapter); 791bea50988SSathya Perla if (!dest_wrb) 792bea50988SSathya Perla return NULL; 793bea50988SSathya Perla } else { 794bea50988SSathya Perla dest_wrb = wrb_from_mbox(adapter); 795bea50988SSathya Perla } 796bea50988SSathya Perla 797bea50988SSathya Perla memcpy(dest_wrb, wrb, sizeof(*wrb)); 798bea50988SSathya Perla if (wrb->embedded & cpu_to_le32(MCC_WRB_EMBEDDED_MASK)) 799bea50988SSathya Perla fill_wrb_tags(dest_wrb, (ulong) embedded_payload(wrb)); 800bea50988SSathya Perla 801bea50988SSathya Perla return dest_wrb; 802bea50988SSathya Perla } 803bea50988SSathya Perla 804bea50988SSathya Perla /* Must be used only in process context */ 805bea50988SSathya Perla static int be_cmd_notify_wait(struct be_adapter *adapter, 806bea50988SSathya Perla struct be_mcc_wrb *wrb) 807bea50988SSathya Perla { 808bea50988SSathya Perla struct be_mcc_wrb *dest_wrb; 809bea50988SSathya Perla int status; 810bea50988SSathya Perla 811bea50988SSathya Perla status = be_cmd_lock(adapter); 812bea50988SSathya Perla if (status) 813bea50988SSathya Perla return status; 814bea50988SSathya Perla 815bea50988SSathya Perla dest_wrb = be_cmd_copy(adapter, wrb); 816bea50988SSathya Perla if (!dest_wrb) 817bea50988SSathya Perla return -EBUSY; 818bea50988SSathya Perla 819bea50988SSathya Perla if (use_mcc(adapter)) 820bea50988SSathya Perla status = be_mcc_notify_wait(adapter); 821bea50988SSathya Perla else 822bea50988SSathya Perla status = be_mbox_notify_wait(adapter); 823bea50988SSathya Perla 824bea50988SSathya Perla if (!status) 825bea50988SSathya Perla memcpy(wrb, dest_wrb, sizeof(*wrb)); 826bea50988SSathya Perla 827bea50988SSathya Perla be_cmd_unlock(adapter); 828bea50988SSathya Perla return status; 829bea50988SSathya Perla } 830bea50988SSathya Perla 8319aebddd1SJeff Kirsher /* Tell fw we're about to start firing cmds by writing a 8329aebddd1SJeff Kirsher * special pattern across the wrb hdr; uses mbox 8339aebddd1SJeff Kirsher */ 8349aebddd1SJeff Kirsher int be_cmd_fw_init(struct be_adapter *adapter) 8359aebddd1SJeff Kirsher { 8369aebddd1SJeff Kirsher u8 *wrb; 8379aebddd1SJeff Kirsher int status; 8389aebddd1SJeff Kirsher 839bf99e50dSPadmanabh Ratnakar if (lancer_chip(adapter)) 840bf99e50dSPadmanabh Ratnakar return 0; 841bf99e50dSPadmanabh Ratnakar 8429aebddd1SJeff Kirsher if (mutex_lock_interruptible(&adapter->mbox_lock)) 8439aebddd1SJeff Kirsher return -1; 8449aebddd1SJeff Kirsher 8459aebddd1SJeff Kirsher wrb = (u8 *)wrb_from_mbox(adapter); 8469aebddd1SJeff Kirsher *wrb++ = 0xFF; 8479aebddd1SJeff Kirsher *wrb++ = 0x12; 8489aebddd1SJeff Kirsher *wrb++ = 0x34; 8499aebddd1SJeff Kirsher *wrb++ = 0xFF; 8509aebddd1SJeff Kirsher *wrb++ = 0xFF; 8519aebddd1SJeff Kirsher *wrb++ = 0x56; 8529aebddd1SJeff Kirsher *wrb++ = 0x78; 8539aebddd1SJeff Kirsher *wrb = 0xFF; 8549aebddd1SJeff Kirsher 8559aebddd1SJeff Kirsher status = be_mbox_notify_wait(adapter); 8569aebddd1SJeff Kirsher 8579aebddd1SJeff Kirsher mutex_unlock(&adapter->mbox_lock); 8589aebddd1SJeff Kirsher return status; 8599aebddd1SJeff Kirsher } 8609aebddd1SJeff Kirsher 8619aebddd1SJeff Kirsher /* Tell fw we're done with firing cmds by writing a 8629aebddd1SJeff Kirsher * special pattern across the wrb hdr; uses mbox 8639aebddd1SJeff Kirsher */ 8649aebddd1SJeff Kirsher int be_cmd_fw_clean(struct be_adapter *adapter) 8659aebddd1SJeff Kirsher { 8669aebddd1SJeff Kirsher u8 *wrb; 8679aebddd1SJeff Kirsher int status; 8689aebddd1SJeff Kirsher 869bf99e50dSPadmanabh Ratnakar if (lancer_chip(adapter)) 870bf99e50dSPadmanabh Ratnakar return 0; 871bf99e50dSPadmanabh Ratnakar 8729aebddd1SJeff Kirsher if (mutex_lock_interruptible(&adapter->mbox_lock)) 8739aebddd1SJeff Kirsher return -1; 8749aebddd1SJeff Kirsher 8759aebddd1SJeff Kirsher wrb = (u8 *)wrb_from_mbox(adapter); 8769aebddd1SJeff Kirsher *wrb++ = 0xFF; 8779aebddd1SJeff Kirsher *wrb++ = 0xAA; 8789aebddd1SJeff Kirsher *wrb++ = 0xBB; 8799aebddd1SJeff Kirsher *wrb++ = 0xFF; 8809aebddd1SJeff Kirsher *wrb++ = 0xFF; 8819aebddd1SJeff Kirsher *wrb++ = 0xCC; 8829aebddd1SJeff Kirsher *wrb++ = 0xDD; 8839aebddd1SJeff Kirsher *wrb = 0xFF; 8849aebddd1SJeff Kirsher 8859aebddd1SJeff Kirsher status = be_mbox_notify_wait(adapter); 8869aebddd1SJeff Kirsher 8879aebddd1SJeff Kirsher mutex_unlock(&adapter->mbox_lock); 8889aebddd1SJeff Kirsher return status; 8899aebddd1SJeff Kirsher } 890bf99e50dSPadmanabh Ratnakar 891f2f781a7SSathya Perla int be_cmd_eq_create(struct be_adapter *adapter, struct be_eq_obj *eqo) 8929aebddd1SJeff Kirsher { 8939aebddd1SJeff Kirsher struct be_mcc_wrb *wrb; 8949aebddd1SJeff Kirsher struct be_cmd_req_eq_create *req; 895f2f781a7SSathya Perla struct be_dma_mem *q_mem = &eqo->q.dma_mem; 896f2f781a7SSathya Perla int status, ver = 0; 8979aebddd1SJeff Kirsher 8989aebddd1SJeff Kirsher if (mutex_lock_interruptible(&adapter->mbox_lock)) 8999aebddd1SJeff Kirsher return -1; 9009aebddd1SJeff Kirsher 9019aebddd1SJeff Kirsher wrb = wrb_from_mbox(adapter); 9029aebddd1SJeff Kirsher req = embedded_payload(wrb); 9039aebddd1SJeff Kirsher 904106df1e3SSomnath Kotur be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 905a2cc4e0bSSathya Perla OPCODE_COMMON_EQ_CREATE, sizeof(*req), wrb, 906a2cc4e0bSSathya Perla NULL); 9079aebddd1SJeff Kirsher 908f2f781a7SSathya Perla /* Support for EQ_CREATEv2 available only SH-R onwards */ 909f2f781a7SSathya Perla if (!(BEx_chip(adapter) || lancer_chip(adapter))) 910f2f781a7SSathya Perla ver = 2; 911f2f781a7SSathya Perla 912f2f781a7SSathya Perla req->hdr.version = ver; 9139aebddd1SJeff Kirsher req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size)); 9149aebddd1SJeff Kirsher 9159aebddd1SJeff Kirsher AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1); 9169aebddd1SJeff Kirsher /* 4byte eqe*/ 9179aebddd1SJeff Kirsher AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0); 9189aebddd1SJeff Kirsher AMAP_SET_BITS(struct amap_eq_context, count, req->context, 919f2f781a7SSathya Perla __ilog2_u32(eqo->q.len / 256)); 9209aebddd1SJeff Kirsher be_dws_cpu_to_le(req->context, sizeof(req->context)); 9219aebddd1SJeff Kirsher 9229aebddd1SJeff Kirsher be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); 9239aebddd1SJeff Kirsher 9249aebddd1SJeff Kirsher status = be_mbox_notify_wait(adapter); 9259aebddd1SJeff Kirsher if (!status) { 9269aebddd1SJeff Kirsher struct be_cmd_resp_eq_create *resp = embedded_payload(wrb); 927f2f781a7SSathya Perla eqo->q.id = le16_to_cpu(resp->eq_id); 928f2f781a7SSathya Perla eqo->msix_idx = 929f2f781a7SSathya Perla (ver == 2) ? le16_to_cpu(resp->msix_idx) : eqo->idx; 930f2f781a7SSathya Perla eqo->q.created = true; 9319aebddd1SJeff Kirsher } 9329aebddd1SJeff Kirsher 9339aebddd1SJeff Kirsher mutex_unlock(&adapter->mbox_lock); 9349aebddd1SJeff Kirsher return status; 9359aebddd1SJeff Kirsher } 9369aebddd1SJeff Kirsher 937f9449ab7SSathya Perla /* Use MCC */ 9389aebddd1SJeff Kirsher int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr, 9395ee4979bSSathya Perla bool permanent, u32 if_handle, u32 pmac_id) 9409aebddd1SJeff Kirsher { 9419aebddd1SJeff Kirsher struct be_mcc_wrb *wrb; 9429aebddd1SJeff Kirsher struct be_cmd_req_mac_query *req; 9439aebddd1SJeff Kirsher int status; 9449aebddd1SJeff Kirsher 945f9449ab7SSathya Perla spin_lock_bh(&adapter->mcc_lock); 9469aebddd1SJeff Kirsher 947f9449ab7SSathya Perla wrb = wrb_from_mccq(adapter); 948f9449ab7SSathya Perla if (!wrb) { 949f9449ab7SSathya Perla status = -EBUSY; 950f9449ab7SSathya Perla goto err; 951f9449ab7SSathya Perla } 9529aebddd1SJeff Kirsher req = embedded_payload(wrb); 9539aebddd1SJeff Kirsher 954106df1e3SSomnath Kotur be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 955a2cc4e0bSSathya Perla OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req), wrb, 956a2cc4e0bSSathya Perla NULL); 9575ee4979bSSathya Perla req->type = MAC_ADDRESS_TYPE_NETWORK; 9589aebddd1SJeff Kirsher if (permanent) { 9599aebddd1SJeff Kirsher req->permanent = 1; 9609aebddd1SJeff Kirsher } else { 9619aebddd1SJeff Kirsher req->if_id = cpu_to_le16((u16) if_handle); 962590c391dSPadmanabh Ratnakar req->pmac_id = cpu_to_le32(pmac_id); 9639aebddd1SJeff Kirsher req->permanent = 0; 9649aebddd1SJeff Kirsher } 9659aebddd1SJeff Kirsher 966f9449ab7SSathya Perla status = be_mcc_notify_wait(adapter); 9679aebddd1SJeff Kirsher if (!status) { 9689aebddd1SJeff Kirsher struct be_cmd_resp_mac_query *resp = embedded_payload(wrb); 9699aebddd1SJeff Kirsher memcpy(mac_addr, resp->mac.addr, ETH_ALEN); 9709aebddd1SJeff Kirsher } 9719aebddd1SJeff Kirsher 972f9449ab7SSathya Perla err: 973f9449ab7SSathya Perla spin_unlock_bh(&adapter->mcc_lock); 9749aebddd1SJeff Kirsher return status; 9759aebddd1SJeff Kirsher } 9769aebddd1SJeff Kirsher 9779aebddd1SJeff Kirsher /* Uses synchronous MCCQ */ 9789aebddd1SJeff Kirsher int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr, 9799aebddd1SJeff Kirsher u32 if_id, u32 *pmac_id, u32 domain) 9809aebddd1SJeff Kirsher { 9819aebddd1SJeff Kirsher struct be_mcc_wrb *wrb; 9829aebddd1SJeff Kirsher struct be_cmd_req_pmac_add *req; 9839aebddd1SJeff Kirsher int status; 9849aebddd1SJeff Kirsher 9859aebddd1SJeff Kirsher spin_lock_bh(&adapter->mcc_lock); 9869aebddd1SJeff Kirsher 9879aebddd1SJeff Kirsher wrb = wrb_from_mccq(adapter); 9889aebddd1SJeff Kirsher if (!wrb) { 9899aebddd1SJeff Kirsher status = -EBUSY; 9909aebddd1SJeff Kirsher goto err; 9919aebddd1SJeff Kirsher } 9929aebddd1SJeff Kirsher req = embedded_payload(wrb); 9939aebddd1SJeff Kirsher 994106df1e3SSomnath Kotur be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 995a2cc4e0bSSathya Perla OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req), wrb, 996a2cc4e0bSSathya Perla NULL); 9979aebddd1SJeff Kirsher 9989aebddd1SJeff Kirsher req->hdr.domain = domain; 9999aebddd1SJeff Kirsher req->if_id = cpu_to_le32(if_id); 10009aebddd1SJeff Kirsher memcpy(req->mac_address, mac_addr, ETH_ALEN); 10019aebddd1SJeff Kirsher 10029aebddd1SJeff Kirsher status = be_mcc_notify_wait(adapter); 10039aebddd1SJeff Kirsher if (!status) { 10049aebddd1SJeff Kirsher struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb); 10059aebddd1SJeff Kirsher *pmac_id = le32_to_cpu(resp->pmac_id); 10069aebddd1SJeff Kirsher } 10079aebddd1SJeff Kirsher 10089aebddd1SJeff Kirsher err: 10099aebddd1SJeff Kirsher spin_unlock_bh(&adapter->mcc_lock); 1010e3a7ae2cSSomnath Kotur 1011e3a7ae2cSSomnath Kotur if (status == MCC_STATUS_UNAUTHORIZED_REQUEST) 1012e3a7ae2cSSomnath Kotur status = -EPERM; 1013e3a7ae2cSSomnath Kotur 10149aebddd1SJeff Kirsher return status; 10159aebddd1SJeff Kirsher } 10169aebddd1SJeff Kirsher 10179aebddd1SJeff Kirsher /* Uses synchronous MCCQ */ 101830128031SSathya Perla int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, int pmac_id, u32 dom) 10199aebddd1SJeff Kirsher { 10209aebddd1SJeff Kirsher struct be_mcc_wrb *wrb; 10219aebddd1SJeff Kirsher struct be_cmd_req_pmac_del *req; 10229aebddd1SJeff Kirsher int status; 10239aebddd1SJeff Kirsher 102430128031SSathya Perla if (pmac_id == -1) 102530128031SSathya Perla return 0; 102630128031SSathya Perla 10279aebddd1SJeff Kirsher spin_lock_bh(&adapter->mcc_lock); 10289aebddd1SJeff Kirsher 10299aebddd1SJeff Kirsher wrb = wrb_from_mccq(adapter); 10309aebddd1SJeff Kirsher if (!wrb) { 10319aebddd1SJeff Kirsher status = -EBUSY; 10329aebddd1SJeff Kirsher goto err; 10339aebddd1SJeff Kirsher } 10349aebddd1SJeff Kirsher req = embedded_payload(wrb); 10359aebddd1SJeff Kirsher 1036106df1e3SSomnath Kotur be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1037106df1e3SSomnath Kotur OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req), wrb, NULL); 10389aebddd1SJeff Kirsher 10399aebddd1SJeff Kirsher req->hdr.domain = dom; 10409aebddd1SJeff Kirsher req->if_id = cpu_to_le32(if_id); 10419aebddd1SJeff Kirsher req->pmac_id = cpu_to_le32(pmac_id); 10429aebddd1SJeff Kirsher 10439aebddd1SJeff Kirsher status = be_mcc_notify_wait(adapter); 10449aebddd1SJeff Kirsher 10459aebddd1SJeff Kirsher err: 10469aebddd1SJeff Kirsher spin_unlock_bh(&adapter->mcc_lock); 10479aebddd1SJeff Kirsher return status; 10489aebddd1SJeff Kirsher } 10499aebddd1SJeff Kirsher 10509aebddd1SJeff Kirsher /* Uses Mbox */ 105110ef9ab4SSathya Perla int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq, 105210ef9ab4SSathya Perla struct be_queue_info *eq, bool no_delay, int coalesce_wm) 10539aebddd1SJeff Kirsher { 10549aebddd1SJeff Kirsher struct be_mcc_wrb *wrb; 10559aebddd1SJeff Kirsher struct be_cmd_req_cq_create *req; 10569aebddd1SJeff Kirsher struct be_dma_mem *q_mem = &cq->dma_mem; 10579aebddd1SJeff Kirsher void *ctxt; 10589aebddd1SJeff Kirsher int status; 10599aebddd1SJeff Kirsher 10609aebddd1SJeff Kirsher if (mutex_lock_interruptible(&adapter->mbox_lock)) 10619aebddd1SJeff Kirsher return -1; 10629aebddd1SJeff Kirsher 10639aebddd1SJeff Kirsher wrb = wrb_from_mbox(adapter); 10649aebddd1SJeff Kirsher req = embedded_payload(wrb); 10659aebddd1SJeff Kirsher ctxt = &req->context; 10669aebddd1SJeff Kirsher 1067106df1e3SSomnath Kotur be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1068a2cc4e0bSSathya Perla OPCODE_COMMON_CQ_CREATE, sizeof(*req), wrb, 1069a2cc4e0bSSathya Perla NULL); 10709aebddd1SJeff Kirsher 10719aebddd1SJeff Kirsher req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size)); 1072bbdc42f8SAjit Khaparde 1073bbdc42f8SAjit Khaparde if (BEx_chip(adapter)) { 10749aebddd1SJeff Kirsher AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt, 10759aebddd1SJeff Kirsher coalesce_wm); 10769aebddd1SJeff Kirsher AMAP_SET_BITS(struct amap_cq_context_be, nodelay, 10779aebddd1SJeff Kirsher ctxt, no_delay); 10789aebddd1SJeff Kirsher AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt, 10799aebddd1SJeff Kirsher __ilog2_u32(cq->len / 256)); 10809aebddd1SJeff Kirsher AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1); 10819aebddd1SJeff Kirsher AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1); 10829aebddd1SJeff Kirsher AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id); 1083bbdc42f8SAjit Khaparde } else { 1084bbdc42f8SAjit Khaparde req->hdr.version = 2; 1085bbdc42f8SAjit Khaparde req->page_size = 1; /* 1 for 4K */ 108609e83a9dSAjit Khaparde 108709e83a9dSAjit Khaparde /* coalesce-wm field in this cmd is not relevant to Lancer. 108809e83a9dSAjit Khaparde * Lancer uses COMMON_MODIFY_CQ to set this field 108909e83a9dSAjit Khaparde */ 109009e83a9dSAjit Khaparde if (!lancer_chip(adapter)) 109109e83a9dSAjit Khaparde AMAP_SET_BITS(struct amap_cq_context_v2, coalescwm, 109209e83a9dSAjit Khaparde ctxt, coalesce_wm); 1093bbdc42f8SAjit Khaparde AMAP_SET_BITS(struct amap_cq_context_v2, nodelay, ctxt, 1094bbdc42f8SAjit Khaparde no_delay); 1095bbdc42f8SAjit Khaparde AMAP_SET_BITS(struct amap_cq_context_v2, count, ctxt, 1096bbdc42f8SAjit Khaparde __ilog2_u32(cq->len / 256)); 1097bbdc42f8SAjit Khaparde AMAP_SET_BITS(struct amap_cq_context_v2, valid, ctxt, 1); 1098a2cc4e0bSSathya Perla AMAP_SET_BITS(struct amap_cq_context_v2, eventable, ctxt, 1); 1099a2cc4e0bSSathya Perla AMAP_SET_BITS(struct amap_cq_context_v2, eqid, ctxt, eq->id); 11009aebddd1SJeff Kirsher } 11019aebddd1SJeff Kirsher 11029aebddd1SJeff Kirsher be_dws_cpu_to_le(ctxt, sizeof(req->context)); 11039aebddd1SJeff Kirsher 11049aebddd1SJeff Kirsher be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); 11059aebddd1SJeff Kirsher 11069aebddd1SJeff Kirsher status = be_mbox_notify_wait(adapter); 11079aebddd1SJeff Kirsher if (!status) { 11089aebddd1SJeff Kirsher struct be_cmd_resp_cq_create *resp = embedded_payload(wrb); 11099aebddd1SJeff Kirsher cq->id = le16_to_cpu(resp->cq_id); 11109aebddd1SJeff Kirsher cq->created = true; 11119aebddd1SJeff Kirsher } 11129aebddd1SJeff Kirsher 11139aebddd1SJeff Kirsher mutex_unlock(&adapter->mbox_lock); 11149aebddd1SJeff Kirsher 11159aebddd1SJeff Kirsher return status; 11169aebddd1SJeff Kirsher } 11179aebddd1SJeff Kirsher 11189aebddd1SJeff Kirsher static u32 be_encoded_q_len(int q_len) 11199aebddd1SJeff Kirsher { 11209aebddd1SJeff Kirsher u32 len_encoded = fls(q_len); /* log2(len) + 1 */ 11219aebddd1SJeff Kirsher if (len_encoded == 16) 11229aebddd1SJeff Kirsher len_encoded = 0; 11239aebddd1SJeff Kirsher return len_encoded; 11249aebddd1SJeff Kirsher } 11259aebddd1SJeff Kirsher 11264188e7dfSJingoo Han static int be_cmd_mccq_ext_create(struct be_adapter *adapter, 11279aebddd1SJeff Kirsher struct be_queue_info *mccq, 11289aebddd1SJeff Kirsher struct be_queue_info *cq) 11299aebddd1SJeff Kirsher { 11309aebddd1SJeff Kirsher struct be_mcc_wrb *wrb; 11319aebddd1SJeff Kirsher struct be_cmd_req_mcc_ext_create *req; 11329aebddd1SJeff Kirsher struct be_dma_mem *q_mem = &mccq->dma_mem; 11339aebddd1SJeff Kirsher void *ctxt; 11349aebddd1SJeff Kirsher int status; 11359aebddd1SJeff Kirsher 11369aebddd1SJeff Kirsher if (mutex_lock_interruptible(&adapter->mbox_lock)) 11379aebddd1SJeff Kirsher return -1; 11389aebddd1SJeff Kirsher 11399aebddd1SJeff Kirsher wrb = wrb_from_mbox(adapter); 11409aebddd1SJeff Kirsher req = embedded_payload(wrb); 11419aebddd1SJeff Kirsher ctxt = &req->context; 11429aebddd1SJeff Kirsher 1143106df1e3SSomnath Kotur be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1144a2cc4e0bSSathya Perla OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req), wrb, 1145a2cc4e0bSSathya Perla NULL); 11469aebddd1SJeff Kirsher 11479aebddd1SJeff Kirsher req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size)); 1148666d39c7SVasundhara Volam if (BEx_chip(adapter)) { 11499aebddd1SJeff Kirsher AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1); 11509aebddd1SJeff Kirsher AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt, 11519aebddd1SJeff Kirsher be_encoded_q_len(mccq->len)); 11529aebddd1SJeff Kirsher AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id); 1153666d39c7SVasundhara Volam } else { 1154666d39c7SVasundhara Volam req->hdr.version = 1; 1155666d39c7SVasundhara Volam req->cq_id = cpu_to_le16(cq->id); 1156666d39c7SVasundhara Volam 1157666d39c7SVasundhara Volam AMAP_SET_BITS(struct amap_mcc_context_v1, ring_size, ctxt, 1158666d39c7SVasundhara Volam be_encoded_q_len(mccq->len)); 1159666d39c7SVasundhara Volam AMAP_SET_BITS(struct amap_mcc_context_v1, valid, ctxt, 1); 1160666d39c7SVasundhara Volam AMAP_SET_BITS(struct amap_mcc_context_v1, async_cq_id, 1161666d39c7SVasundhara Volam ctxt, cq->id); 1162666d39c7SVasundhara Volam AMAP_SET_BITS(struct amap_mcc_context_v1, async_cq_valid, 1163666d39c7SVasundhara Volam ctxt, 1); 11649aebddd1SJeff Kirsher } 11659aebddd1SJeff Kirsher 11669aebddd1SJeff Kirsher /* Subscribe to Link State and Group 5 Events(bits 1 and 5 set) */ 11679aebddd1SJeff Kirsher req->async_event_bitmap[0] = cpu_to_le32(0x00000022); 1168bc0c3405SAjit Khaparde req->async_event_bitmap[0] |= cpu_to_le32(1 << ASYNC_EVENT_CODE_QNQ); 11699aebddd1SJeff Kirsher be_dws_cpu_to_le(ctxt, sizeof(req->context)); 11709aebddd1SJeff Kirsher 11719aebddd1SJeff Kirsher be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); 11729aebddd1SJeff Kirsher 11739aebddd1SJeff Kirsher status = be_mbox_notify_wait(adapter); 11749aebddd1SJeff Kirsher if (!status) { 11759aebddd1SJeff Kirsher struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb); 11769aebddd1SJeff Kirsher mccq->id = le16_to_cpu(resp->id); 11779aebddd1SJeff Kirsher mccq->created = true; 11789aebddd1SJeff Kirsher } 11799aebddd1SJeff Kirsher mutex_unlock(&adapter->mbox_lock); 11809aebddd1SJeff Kirsher 11819aebddd1SJeff Kirsher return status; 11829aebddd1SJeff Kirsher } 11839aebddd1SJeff Kirsher 11844188e7dfSJingoo Han static int be_cmd_mccq_org_create(struct be_adapter *adapter, 11859aebddd1SJeff Kirsher struct be_queue_info *mccq, 11869aebddd1SJeff Kirsher struct be_queue_info *cq) 11879aebddd1SJeff Kirsher { 11889aebddd1SJeff Kirsher struct be_mcc_wrb *wrb; 11899aebddd1SJeff Kirsher struct be_cmd_req_mcc_create *req; 11909aebddd1SJeff Kirsher struct be_dma_mem *q_mem = &mccq->dma_mem; 11919aebddd1SJeff Kirsher void *ctxt; 11929aebddd1SJeff Kirsher int status; 11939aebddd1SJeff Kirsher 11949aebddd1SJeff Kirsher if (mutex_lock_interruptible(&adapter->mbox_lock)) 11959aebddd1SJeff Kirsher return -1; 11969aebddd1SJeff Kirsher 11979aebddd1SJeff Kirsher wrb = wrb_from_mbox(adapter); 11989aebddd1SJeff Kirsher req = embedded_payload(wrb); 11999aebddd1SJeff Kirsher ctxt = &req->context; 12009aebddd1SJeff Kirsher 1201106df1e3SSomnath Kotur be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1202a2cc4e0bSSathya Perla OPCODE_COMMON_MCC_CREATE, sizeof(*req), wrb, 1203a2cc4e0bSSathya Perla NULL); 12049aebddd1SJeff Kirsher 12059aebddd1SJeff Kirsher req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size)); 12069aebddd1SJeff Kirsher 12079aebddd1SJeff Kirsher AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1); 12089aebddd1SJeff Kirsher AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt, 12099aebddd1SJeff Kirsher be_encoded_q_len(mccq->len)); 12109aebddd1SJeff Kirsher AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id); 12119aebddd1SJeff Kirsher 12129aebddd1SJeff Kirsher be_dws_cpu_to_le(ctxt, sizeof(req->context)); 12139aebddd1SJeff Kirsher 12149aebddd1SJeff Kirsher be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); 12159aebddd1SJeff Kirsher 12169aebddd1SJeff Kirsher status = be_mbox_notify_wait(adapter); 12179aebddd1SJeff Kirsher if (!status) { 12189aebddd1SJeff Kirsher struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb); 12199aebddd1SJeff Kirsher mccq->id = le16_to_cpu(resp->id); 12209aebddd1SJeff Kirsher mccq->created = true; 12219aebddd1SJeff Kirsher } 12229aebddd1SJeff Kirsher 12239aebddd1SJeff Kirsher mutex_unlock(&adapter->mbox_lock); 12249aebddd1SJeff Kirsher return status; 12259aebddd1SJeff Kirsher } 12269aebddd1SJeff Kirsher 12279aebddd1SJeff Kirsher int be_cmd_mccq_create(struct be_adapter *adapter, 1228a2cc4e0bSSathya Perla struct be_queue_info *mccq, struct be_queue_info *cq) 12299aebddd1SJeff Kirsher { 12309aebddd1SJeff Kirsher int status; 12319aebddd1SJeff Kirsher 12329aebddd1SJeff Kirsher status = be_cmd_mccq_ext_create(adapter, mccq, cq); 1233666d39c7SVasundhara Volam if (status && BEx_chip(adapter)) { 12349aebddd1SJeff Kirsher dev_warn(&adapter->pdev->dev, "Upgrade to F/W ver 2.102.235.0 " 12359aebddd1SJeff Kirsher "or newer to avoid conflicting priorities between NIC " 12369aebddd1SJeff Kirsher "and FCoE traffic"); 12379aebddd1SJeff Kirsher status = be_cmd_mccq_org_create(adapter, mccq, cq); 12389aebddd1SJeff Kirsher } 12399aebddd1SJeff Kirsher return status; 12409aebddd1SJeff Kirsher } 12419aebddd1SJeff Kirsher 124294d73aaaSVasundhara Volam int be_cmd_txq_create(struct be_adapter *adapter, struct be_tx_obj *txo) 12439aebddd1SJeff Kirsher { 12447707133cSSathya Perla struct be_mcc_wrb wrb = {0}; 12459aebddd1SJeff Kirsher struct be_cmd_req_eth_tx_create *req; 124694d73aaaSVasundhara Volam struct be_queue_info *txq = &txo->q; 124794d73aaaSVasundhara Volam struct be_queue_info *cq = &txo->cq; 12489aebddd1SJeff Kirsher struct be_dma_mem *q_mem = &txq->dma_mem; 124994d73aaaSVasundhara Volam int status, ver = 0; 12509aebddd1SJeff Kirsher 12517707133cSSathya Perla req = embedded_payload(&wrb); 1252106df1e3SSomnath Kotur be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, 12537707133cSSathya Perla OPCODE_ETH_TX_CREATE, sizeof(*req), &wrb, NULL); 12549aebddd1SJeff Kirsher 12559aebddd1SJeff Kirsher if (lancer_chip(adapter)) { 12569aebddd1SJeff Kirsher req->hdr.version = 1; 125794d73aaaSVasundhara Volam } else if (BEx_chip(adapter)) { 125894d73aaaSVasundhara Volam if (adapter->function_caps & BE_FUNCTION_CAPS_SUPER_NIC) 125994d73aaaSVasundhara Volam req->hdr.version = 2; 126094d73aaaSVasundhara Volam } else { /* For SH */ 126194d73aaaSVasundhara Volam req->hdr.version = 2; 12629aebddd1SJeff Kirsher } 12639aebddd1SJeff Kirsher 126481b02655SVasundhara Volam if (req->hdr.version > 0) 126581b02655SVasundhara Volam req->if_id = cpu_to_le16(adapter->if_handle); 12669aebddd1SJeff Kirsher req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size); 12679aebddd1SJeff Kirsher req->ulp_num = BE_ULP1_NUM; 12689aebddd1SJeff Kirsher req->type = BE_ETH_TX_RING_TYPE_STANDARD; 126994d73aaaSVasundhara Volam req->cq_id = cpu_to_le16(cq->id); 127094d73aaaSVasundhara Volam req->queue_size = be_encoded_q_len(txq->len); 12719aebddd1SJeff Kirsher be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); 127294d73aaaSVasundhara Volam ver = req->hdr.version; 127394d73aaaSVasundhara Volam 12747707133cSSathya Perla status = be_cmd_notify_wait(adapter, &wrb); 12759aebddd1SJeff Kirsher if (!status) { 12767707133cSSathya Perla struct be_cmd_resp_eth_tx_create *resp = embedded_payload(&wrb); 12779aebddd1SJeff Kirsher txq->id = le16_to_cpu(resp->cid); 127894d73aaaSVasundhara Volam if (ver == 2) 127994d73aaaSVasundhara Volam txo->db_offset = le32_to_cpu(resp->db_offset); 128094d73aaaSVasundhara Volam else 128194d73aaaSVasundhara Volam txo->db_offset = DB_TXULP1_OFFSET; 12829aebddd1SJeff Kirsher txq->created = true; 12839aebddd1SJeff Kirsher } 12849aebddd1SJeff Kirsher 12859aebddd1SJeff Kirsher return status; 12869aebddd1SJeff Kirsher } 12879aebddd1SJeff Kirsher 12889aebddd1SJeff Kirsher /* Uses MCC */ 12899aebddd1SJeff Kirsher int be_cmd_rxq_create(struct be_adapter *adapter, 12909aebddd1SJeff Kirsher struct be_queue_info *rxq, u16 cq_id, u16 frag_size, 129110ef9ab4SSathya Perla u32 if_id, u32 rss, u8 *rss_id) 12929aebddd1SJeff Kirsher { 12939aebddd1SJeff Kirsher struct be_mcc_wrb *wrb; 12949aebddd1SJeff Kirsher struct be_cmd_req_eth_rx_create *req; 12959aebddd1SJeff Kirsher struct be_dma_mem *q_mem = &rxq->dma_mem; 12969aebddd1SJeff Kirsher int status; 12979aebddd1SJeff Kirsher 12989aebddd1SJeff Kirsher spin_lock_bh(&adapter->mcc_lock); 12999aebddd1SJeff Kirsher 13009aebddd1SJeff Kirsher wrb = wrb_from_mccq(adapter); 13019aebddd1SJeff Kirsher if (!wrb) { 13029aebddd1SJeff Kirsher status = -EBUSY; 13039aebddd1SJeff Kirsher goto err; 13049aebddd1SJeff Kirsher } 13059aebddd1SJeff Kirsher req = embedded_payload(wrb); 13069aebddd1SJeff Kirsher 1307106df1e3SSomnath Kotur be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, 1308106df1e3SSomnath Kotur OPCODE_ETH_RX_CREATE, sizeof(*req), wrb, NULL); 13099aebddd1SJeff Kirsher 13109aebddd1SJeff Kirsher req->cq_id = cpu_to_le16(cq_id); 13119aebddd1SJeff Kirsher req->frag_size = fls(frag_size) - 1; 13129aebddd1SJeff Kirsher req->num_pages = 2; 13139aebddd1SJeff Kirsher be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); 13149aebddd1SJeff Kirsher req->interface_id = cpu_to_le32(if_id); 131510ef9ab4SSathya Perla req->max_frame_size = cpu_to_le16(BE_MAX_JUMBO_FRAME_SIZE); 13169aebddd1SJeff Kirsher req->rss_queue = cpu_to_le32(rss); 13179aebddd1SJeff Kirsher 13189aebddd1SJeff Kirsher status = be_mcc_notify_wait(adapter); 13199aebddd1SJeff Kirsher if (!status) { 13209aebddd1SJeff Kirsher struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb); 13219aebddd1SJeff Kirsher rxq->id = le16_to_cpu(resp->id); 13229aebddd1SJeff Kirsher rxq->created = true; 13239aebddd1SJeff Kirsher *rss_id = resp->rss_id; 13249aebddd1SJeff Kirsher } 13259aebddd1SJeff Kirsher 13269aebddd1SJeff Kirsher err: 13279aebddd1SJeff Kirsher spin_unlock_bh(&adapter->mcc_lock); 13289aebddd1SJeff Kirsher return status; 13299aebddd1SJeff Kirsher } 13309aebddd1SJeff Kirsher 13319aebddd1SJeff Kirsher /* Generic destroyer function for all types of queues 13329aebddd1SJeff Kirsher * Uses Mbox 13339aebddd1SJeff Kirsher */ 13349aebddd1SJeff Kirsher int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q, 13359aebddd1SJeff Kirsher int queue_type) 13369aebddd1SJeff Kirsher { 13379aebddd1SJeff Kirsher struct be_mcc_wrb *wrb; 13389aebddd1SJeff Kirsher struct be_cmd_req_q_destroy *req; 13399aebddd1SJeff Kirsher u8 subsys = 0, opcode = 0; 13409aebddd1SJeff Kirsher int status; 13419aebddd1SJeff Kirsher 13429aebddd1SJeff Kirsher if (mutex_lock_interruptible(&adapter->mbox_lock)) 13439aebddd1SJeff Kirsher return -1; 13449aebddd1SJeff Kirsher 13459aebddd1SJeff Kirsher wrb = wrb_from_mbox(adapter); 13469aebddd1SJeff Kirsher req = embedded_payload(wrb); 13479aebddd1SJeff Kirsher 13489aebddd1SJeff Kirsher switch (queue_type) { 13499aebddd1SJeff Kirsher case QTYPE_EQ: 13509aebddd1SJeff Kirsher subsys = CMD_SUBSYSTEM_COMMON; 13519aebddd1SJeff Kirsher opcode = OPCODE_COMMON_EQ_DESTROY; 13529aebddd1SJeff Kirsher break; 13539aebddd1SJeff Kirsher case QTYPE_CQ: 13549aebddd1SJeff Kirsher subsys = CMD_SUBSYSTEM_COMMON; 13559aebddd1SJeff Kirsher opcode = OPCODE_COMMON_CQ_DESTROY; 13569aebddd1SJeff Kirsher break; 13579aebddd1SJeff Kirsher case QTYPE_TXQ: 13589aebddd1SJeff Kirsher subsys = CMD_SUBSYSTEM_ETH; 13599aebddd1SJeff Kirsher opcode = OPCODE_ETH_TX_DESTROY; 13609aebddd1SJeff Kirsher break; 13619aebddd1SJeff Kirsher case QTYPE_RXQ: 13629aebddd1SJeff Kirsher subsys = CMD_SUBSYSTEM_ETH; 13639aebddd1SJeff Kirsher opcode = OPCODE_ETH_RX_DESTROY; 13649aebddd1SJeff Kirsher break; 13659aebddd1SJeff Kirsher case QTYPE_MCCQ: 13669aebddd1SJeff Kirsher subsys = CMD_SUBSYSTEM_COMMON; 13679aebddd1SJeff Kirsher opcode = OPCODE_COMMON_MCC_DESTROY; 13689aebddd1SJeff Kirsher break; 13699aebddd1SJeff Kirsher default: 13709aebddd1SJeff Kirsher BUG(); 13719aebddd1SJeff Kirsher } 13729aebddd1SJeff Kirsher 1373106df1e3SSomnath Kotur be_wrb_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req), wrb, 1374106df1e3SSomnath Kotur NULL); 13759aebddd1SJeff Kirsher req->id = cpu_to_le16(q->id); 13769aebddd1SJeff Kirsher 13779aebddd1SJeff Kirsher status = be_mbox_notify_wait(adapter); 13789aebddd1SJeff Kirsher q->created = false; 13799aebddd1SJeff Kirsher 13809aebddd1SJeff Kirsher mutex_unlock(&adapter->mbox_lock); 13819aebddd1SJeff Kirsher return status; 13829aebddd1SJeff Kirsher } 13839aebddd1SJeff Kirsher 13849aebddd1SJeff Kirsher /* Uses MCC */ 13859aebddd1SJeff Kirsher int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q) 13869aebddd1SJeff Kirsher { 13879aebddd1SJeff Kirsher struct be_mcc_wrb *wrb; 13889aebddd1SJeff Kirsher struct be_cmd_req_q_destroy *req; 13899aebddd1SJeff Kirsher int status; 13909aebddd1SJeff Kirsher 13919aebddd1SJeff Kirsher spin_lock_bh(&adapter->mcc_lock); 13929aebddd1SJeff Kirsher 13939aebddd1SJeff Kirsher wrb = wrb_from_mccq(adapter); 13949aebddd1SJeff Kirsher if (!wrb) { 13959aebddd1SJeff Kirsher status = -EBUSY; 13969aebddd1SJeff Kirsher goto err; 13979aebddd1SJeff Kirsher } 13989aebddd1SJeff Kirsher req = embedded_payload(wrb); 13999aebddd1SJeff Kirsher 1400106df1e3SSomnath Kotur be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, 1401106df1e3SSomnath Kotur OPCODE_ETH_RX_DESTROY, sizeof(*req), wrb, NULL); 14029aebddd1SJeff Kirsher req->id = cpu_to_le16(q->id); 14039aebddd1SJeff Kirsher 14049aebddd1SJeff Kirsher status = be_mcc_notify_wait(adapter); 14059aebddd1SJeff Kirsher q->created = false; 14069aebddd1SJeff Kirsher 14079aebddd1SJeff Kirsher err: 14089aebddd1SJeff Kirsher spin_unlock_bh(&adapter->mcc_lock); 14099aebddd1SJeff Kirsher return status; 14109aebddd1SJeff Kirsher } 14119aebddd1SJeff Kirsher 14129aebddd1SJeff Kirsher /* Create an rx filtering policy configuration on an i/f 1413bea50988SSathya Perla * Will use MBOX only if MCCQ has not been created. 14149aebddd1SJeff Kirsher */ 14159aebddd1SJeff Kirsher int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags, 14161578e777SPadmanabh Ratnakar u32 *if_handle, u32 domain) 14179aebddd1SJeff Kirsher { 1418bea50988SSathya Perla struct be_mcc_wrb wrb = {0}; 14199aebddd1SJeff Kirsher struct be_cmd_req_if_create *req; 14209aebddd1SJeff Kirsher int status; 14219aebddd1SJeff Kirsher 1422bea50988SSathya Perla req = embedded_payload(&wrb); 1423106df1e3SSomnath Kotur be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1424a2cc4e0bSSathya Perla OPCODE_COMMON_NTWK_INTERFACE_CREATE, 1425a2cc4e0bSSathya Perla sizeof(*req), &wrb, NULL); 14269aebddd1SJeff Kirsher req->hdr.domain = domain; 14279aebddd1SJeff Kirsher req->capability_flags = cpu_to_le32(cap_flags); 14289aebddd1SJeff Kirsher req->enable_flags = cpu_to_le32(en_flags); 1429f9449ab7SSathya Perla req->pmac_invalid = true; 14309aebddd1SJeff Kirsher 1431bea50988SSathya Perla status = be_cmd_notify_wait(adapter, &wrb); 14329aebddd1SJeff Kirsher if (!status) { 1433bea50988SSathya Perla struct be_cmd_resp_if_create *resp = embedded_payload(&wrb); 14349aebddd1SJeff Kirsher *if_handle = le32_to_cpu(resp->interface_id); 1435b5bb9776SSathya Perla 1436b5bb9776SSathya Perla /* Hack to retrieve VF's pmac-id on BE3 */ 1437b5bb9776SSathya Perla if (BE3_chip(adapter) && !be_physfn(adapter)) 1438b5bb9776SSathya Perla adapter->pmac_id[0] = le32_to_cpu(resp->pmac_id); 14399aebddd1SJeff Kirsher } 14409aebddd1SJeff Kirsher return status; 14419aebddd1SJeff Kirsher } 14429aebddd1SJeff Kirsher 1443f9449ab7SSathya Perla /* Uses MCCQ */ 144430128031SSathya Perla int be_cmd_if_destroy(struct be_adapter *adapter, int interface_id, u32 domain) 14459aebddd1SJeff Kirsher { 14469aebddd1SJeff Kirsher struct be_mcc_wrb *wrb; 14479aebddd1SJeff Kirsher struct be_cmd_req_if_destroy *req; 14489aebddd1SJeff Kirsher int status; 14499aebddd1SJeff Kirsher 145030128031SSathya Perla if (interface_id == -1) 1451f9449ab7SSathya Perla return 0; 14529aebddd1SJeff Kirsher 1453f9449ab7SSathya Perla spin_lock_bh(&adapter->mcc_lock); 1454f9449ab7SSathya Perla 1455f9449ab7SSathya Perla wrb = wrb_from_mccq(adapter); 1456f9449ab7SSathya Perla if (!wrb) { 1457f9449ab7SSathya Perla status = -EBUSY; 1458f9449ab7SSathya Perla goto err; 1459f9449ab7SSathya Perla } 14609aebddd1SJeff Kirsher req = embedded_payload(wrb); 14619aebddd1SJeff Kirsher 1462106df1e3SSomnath Kotur be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1463a2cc4e0bSSathya Perla OPCODE_COMMON_NTWK_INTERFACE_DESTROY, 1464a2cc4e0bSSathya Perla sizeof(*req), wrb, NULL); 14659aebddd1SJeff Kirsher req->hdr.domain = domain; 14669aebddd1SJeff Kirsher req->interface_id = cpu_to_le32(interface_id); 14679aebddd1SJeff Kirsher 1468f9449ab7SSathya Perla status = be_mcc_notify_wait(adapter); 1469f9449ab7SSathya Perla err: 1470f9449ab7SSathya Perla spin_unlock_bh(&adapter->mcc_lock); 14719aebddd1SJeff Kirsher return status; 14729aebddd1SJeff Kirsher } 14739aebddd1SJeff Kirsher 14749aebddd1SJeff Kirsher /* Get stats is a non embedded command: the request is not embedded inside 14759aebddd1SJeff Kirsher * WRB but is a separate dma memory block 14769aebddd1SJeff Kirsher * Uses asynchronous MCC 14779aebddd1SJeff Kirsher */ 14789aebddd1SJeff Kirsher int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd) 14799aebddd1SJeff Kirsher { 14809aebddd1SJeff Kirsher struct be_mcc_wrb *wrb; 14819aebddd1SJeff Kirsher struct be_cmd_req_hdr *hdr; 14829aebddd1SJeff Kirsher int status = 0; 14839aebddd1SJeff Kirsher 14849aebddd1SJeff Kirsher spin_lock_bh(&adapter->mcc_lock); 14859aebddd1SJeff Kirsher 14869aebddd1SJeff Kirsher wrb = wrb_from_mccq(adapter); 14879aebddd1SJeff Kirsher if (!wrb) { 14889aebddd1SJeff Kirsher status = -EBUSY; 14899aebddd1SJeff Kirsher goto err; 14909aebddd1SJeff Kirsher } 14919aebddd1SJeff Kirsher hdr = nonemb_cmd->va; 14929aebddd1SJeff Kirsher 1493106df1e3SSomnath Kotur be_wrb_cmd_hdr_prepare(hdr, CMD_SUBSYSTEM_ETH, 1494a2cc4e0bSSathya Perla OPCODE_ETH_GET_STATISTICS, nonemb_cmd->size, wrb, 1495a2cc4e0bSSathya Perla nonemb_cmd); 14969aebddd1SJeff Kirsher 1497ca34fe38SSathya Perla /* version 1 of the cmd is not supported only by BE2 */ 149861000861SAjit Khaparde if (BE2_chip(adapter)) 149961000861SAjit Khaparde hdr->version = 0; 150061000861SAjit Khaparde if (BE3_chip(adapter) || lancer_chip(adapter)) 15019aebddd1SJeff Kirsher hdr->version = 1; 150261000861SAjit Khaparde else 150361000861SAjit Khaparde hdr->version = 2; 15049aebddd1SJeff Kirsher 15059aebddd1SJeff Kirsher be_mcc_notify(adapter); 15069aebddd1SJeff Kirsher adapter->stats_cmd_sent = true; 15079aebddd1SJeff Kirsher 15089aebddd1SJeff Kirsher err: 15099aebddd1SJeff Kirsher spin_unlock_bh(&adapter->mcc_lock); 15109aebddd1SJeff Kirsher return status; 15119aebddd1SJeff Kirsher } 15129aebddd1SJeff Kirsher 15139aebddd1SJeff Kirsher /* Lancer Stats */ 15149aebddd1SJeff Kirsher int lancer_cmd_get_pport_stats(struct be_adapter *adapter, 15159aebddd1SJeff Kirsher struct be_dma_mem *nonemb_cmd) 15169aebddd1SJeff Kirsher { 15179aebddd1SJeff Kirsher 15189aebddd1SJeff Kirsher struct be_mcc_wrb *wrb; 15199aebddd1SJeff Kirsher struct lancer_cmd_req_pport_stats *req; 15209aebddd1SJeff Kirsher int status = 0; 15219aebddd1SJeff Kirsher 1522f25b119cSPadmanabh Ratnakar if (!be_cmd_allowed(adapter, OPCODE_ETH_GET_PPORT_STATS, 1523f25b119cSPadmanabh Ratnakar CMD_SUBSYSTEM_ETH)) 1524f25b119cSPadmanabh Ratnakar return -EPERM; 1525f25b119cSPadmanabh Ratnakar 15269aebddd1SJeff Kirsher spin_lock_bh(&adapter->mcc_lock); 15279aebddd1SJeff Kirsher 15289aebddd1SJeff Kirsher wrb = wrb_from_mccq(adapter); 15299aebddd1SJeff Kirsher if (!wrb) { 15309aebddd1SJeff Kirsher status = -EBUSY; 15319aebddd1SJeff Kirsher goto err; 15329aebddd1SJeff Kirsher } 15339aebddd1SJeff Kirsher req = nonemb_cmd->va; 15349aebddd1SJeff Kirsher 1535106df1e3SSomnath Kotur be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, 1536a2cc4e0bSSathya Perla OPCODE_ETH_GET_PPORT_STATS, nonemb_cmd->size, 1537a2cc4e0bSSathya Perla wrb, nonemb_cmd); 15389aebddd1SJeff Kirsher 1539d51ebd33SPadmanabh Ratnakar req->cmd_params.params.pport_num = cpu_to_le16(adapter->hba_port_num); 15409aebddd1SJeff Kirsher req->cmd_params.params.reset_stats = 0; 15419aebddd1SJeff Kirsher 15429aebddd1SJeff Kirsher be_mcc_notify(adapter); 15439aebddd1SJeff Kirsher adapter->stats_cmd_sent = true; 15449aebddd1SJeff Kirsher 15459aebddd1SJeff Kirsher err: 15469aebddd1SJeff Kirsher spin_unlock_bh(&adapter->mcc_lock); 15479aebddd1SJeff Kirsher return status; 15489aebddd1SJeff Kirsher } 15499aebddd1SJeff Kirsher 1550323ff71eSSathya Perla static int be_mac_to_link_speed(int mac_speed) 1551323ff71eSSathya Perla { 1552323ff71eSSathya Perla switch (mac_speed) { 1553323ff71eSSathya Perla case PHY_LINK_SPEED_ZERO: 1554323ff71eSSathya Perla return 0; 1555323ff71eSSathya Perla case PHY_LINK_SPEED_10MBPS: 1556323ff71eSSathya Perla return 10; 1557323ff71eSSathya Perla case PHY_LINK_SPEED_100MBPS: 1558323ff71eSSathya Perla return 100; 1559323ff71eSSathya Perla case PHY_LINK_SPEED_1GBPS: 1560323ff71eSSathya Perla return 1000; 1561323ff71eSSathya Perla case PHY_LINK_SPEED_10GBPS: 1562323ff71eSSathya Perla return 10000; 1563b971f847SVasundhara Volam case PHY_LINK_SPEED_20GBPS: 1564b971f847SVasundhara Volam return 20000; 1565b971f847SVasundhara Volam case PHY_LINK_SPEED_25GBPS: 1566b971f847SVasundhara Volam return 25000; 1567b971f847SVasundhara Volam case PHY_LINK_SPEED_40GBPS: 1568b971f847SVasundhara Volam return 40000; 1569323ff71eSSathya Perla } 1570323ff71eSSathya Perla return 0; 1571323ff71eSSathya Perla } 1572323ff71eSSathya Perla 1573323ff71eSSathya Perla /* Uses synchronous mcc 1574323ff71eSSathya Perla * Returns link_speed in Mbps 1575323ff71eSSathya Perla */ 1576323ff71eSSathya Perla int be_cmd_link_status_query(struct be_adapter *adapter, u16 *link_speed, 1577323ff71eSSathya Perla u8 *link_status, u32 dom) 15789aebddd1SJeff Kirsher { 15799aebddd1SJeff Kirsher struct be_mcc_wrb *wrb; 15809aebddd1SJeff Kirsher struct be_cmd_req_link_status *req; 15819aebddd1SJeff Kirsher int status; 15829aebddd1SJeff Kirsher 15839aebddd1SJeff Kirsher spin_lock_bh(&adapter->mcc_lock); 15849aebddd1SJeff Kirsher 1585b236916aSAjit Khaparde if (link_status) 1586b236916aSAjit Khaparde *link_status = LINK_DOWN; 1587b236916aSAjit Khaparde 15889aebddd1SJeff Kirsher wrb = wrb_from_mccq(adapter); 15899aebddd1SJeff Kirsher if (!wrb) { 15909aebddd1SJeff Kirsher status = -EBUSY; 15919aebddd1SJeff Kirsher goto err; 15929aebddd1SJeff Kirsher } 15939aebddd1SJeff Kirsher req = embedded_payload(wrb); 15949aebddd1SJeff Kirsher 159557cd80d4SPadmanabh Ratnakar be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1596a2cc4e0bSSathya Perla OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, 1597a2cc4e0bSSathya Perla sizeof(*req), wrb, NULL); 159857cd80d4SPadmanabh Ratnakar 1599ca34fe38SSathya Perla /* version 1 of the cmd is not supported only by BE2 */ 1600ca34fe38SSathya Perla if (!BE2_chip(adapter)) 1601daad6167SPadmanabh Ratnakar req->hdr.version = 1; 1602daad6167SPadmanabh Ratnakar 160357cd80d4SPadmanabh Ratnakar req->hdr.domain = dom; 16049aebddd1SJeff Kirsher 16059aebddd1SJeff Kirsher status = be_mcc_notify_wait(adapter); 16069aebddd1SJeff Kirsher if (!status) { 16079aebddd1SJeff Kirsher struct be_cmd_resp_link_status *resp = embedded_payload(wrb); 1608323ff71eSSathya Perla if (link_speed) { 1609323ff71eSSathya Perla *link_speed = resp->link_speed ? 1610323ff71eSSathya Perla le16_to_cpu(resp->link_speed) * 10 : 1611323ff71eSSathya Perla be_mac_to_link_speed(resp->mac_speed); 1612323ff71eSSathya Perla 1613323ff71eSSathya Perla if (!resp->logical_link_status) 1614323ff71eSSathya Perla *link_speed = 0; 16159aebddd1SJeff Kirsher } 1616b236916aSAjit Khaparde if (link_status) 1617b236916aSAjit Khaparde *link_status = resp->logical_link_status; 16189aebddd1SJeff Kirsher } 16199aebddd1SJeff Kirsher 16209aebddd1SJeff Kirsher err: 16219aebddd1SJeff Kirsher spin_unlock_bh(&adapter->mcc_lock); 16229aebddd1SJeff Kirsher return status; 16239aebddd1SJeff Kirsher } 16249aebddd1SJeff Kirsher 16259aebddd1SJeff Kirsher /* Uses synchronous mcc */ 16269aebddd1SJeff Kirsher int be_cmd_get_die_temperature(struct be_adapter *adapter) 16279aebddd1SJeff Kirsher { 16289aebddd1SJeff Kirsher struct be_mcc_wrb *wrb; 16299aebddd1SJeff Kirsher struct be_cmd_req_get_cntl_addnl_attribs *req; 1630117affe3SVasundhara Volam int status = 0; 16319aebddd1SJeff Kirsher 16329aebddd1SJeff Kirsher spin_lock_bh(&adapter->mcc_lock); 16339aebddd1SJeff Kirsher 16349aebddd1SJeff Kirsher wrb = wrb_from_mccq(adapter); 16359aebddd1SJeff Kirsher if (!wrb) { 16369aebddd1SJeff Kirsher status = -EBUSY; 16379aebddd1SJeff Kirsher goto err; 16389aebddd1SJeff Kirsher } 16399aebddd1SJeff Kirsher req = embedded_payload(wrb); 16409aebddd1SJeff Kirsher 1641106df1e3SSomnath Kotur be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1642a2cc4e0bSSathya Perla OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES, 1643a2cc4e0bSSathya Perla sizeof(*req), wrb, NULL); 16449aebddd1SJeff Kirsher 16453de09455SSomnath Kotur be_mcc_notify(adapter); 16469aebddd1SJeff Kirsher 16479aebddd1SJeff Kirsher err: 16489aebddd1SJeff Kirsher spin_unlock_bh(&adapter->mcc_lock); 16499aebddd1SJeff Kirsher return status; 16509aebddd1SJeff Kirsher } 16519aebddd1SJeff Kirsher 16529aebddd1SJeff Kirsher /* Uses synchronous mcc */ 16539aebddd1SJeff Kirsher int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size) 16549aebddd1SJeff Kirsher { 16559aebddd1SJeff Kirsher struct be_mcc_wrb *wrb; 16569aebddd1SJeff Kirsher struct be_cmd_req_get_fat *req; 16579aebddd1SJeff Kirsher int status; 16589aebddd1SJeff Kirsher 16599aebddd1SJeff Kirsher spin_lock_bh(&adapter->mcc_lock); 16609aebddd1SJeff Kirsher 16619aebddd1SJeff Kirsher wrb = wrb_from_mccq(adapter); 16629aebddd1SJeff Kirsher if (!wrb) { 16639aebddd1SJeff Kirsher status = -EBUSY; 16649aebddd1SJeff Kirsher goto err; 16659aebddd1SJeff Kirsher } 16669aebddd1SJeff Kirsher req = embedded_payload(wrb); 16679aebddd1SJeff Kirsher 1668106df1e3SSomnath Kotur be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1669a2cc4e0bSSathya Perla OPCODE_COMMON_MANAGE_FAT, sizeof(*req), wrb, 1670a2cc4e0bSSathya Perla NULL); 16719aebddd1SJeff Kirsher req->fat_operation = cpu_to_le32(QUERY_FAT); 16729aebddd1SJeff Kirsher status = be_mcc_notify_wait(adapter); 16739aebddd1SJeff Kirsher if (!status) { 16749aebddd1SJeff Kirsher struct be_cmd_resp_get_fat *resp = embedded_payload(wrb); 16759aebddd1SJeff Kirsher if (log_size && resp->log_size) 16769aebddd1SJeff Kirsher *log_size = le32_to_cpu(resp->log_size) - 16779aebddd1SJeff Kirsher sizeof(u32); 16789aebddd1SJeff Kirsher } 16799aebddd1SJeff Kirsher err: 16809aebddd1SJeff Kirsher spin_unlock_bh(&adapter->mcc_lock); 16819aebddd1SJeff Kirsher return status; 16829aebddd1SJeff Kirsher } 16839aebddd1SJeff Kirsher 16849aebddd1SJeff Kirsher void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf) 16859aebddd1SJeff Kirsher { 16869aebddd1SJeff Kirsher struct be_dma_mem get_fat_cmd; 16879aebddd1SJeff Kirsher struct be_mcc_wrb *wrb; 16889aebddd1SJeff Kirsher struct be_cmd_req_get_fat *req; 16899aebddd1SJeff Kirsher u32 offset = 0, total_size, buf_size, 16909aebddd1SJeff Kirsher log_offset = sizeof(u32), payload_len; 16919aebddd1SJeff Kirsher int status; 16929aebddd1SJeff Kirsher 16939aebddd1SJeff Kirsher if (buf_len == 0) 16949aebddd1SJeff Kirsher return; 16959aebddd1SJeff Kirsher 16969aebddd1SJeff Kirsher total_size = buf_len; 16979aebddd1SJeff Kirsher 16989aebddd1SJeff Kirsher get_fat_cmd.size = sizeof(struct be_cmd_req_get_fat) + 60*1024; 16999aebddd1SJeff Kirsher get_fat_cmd.va = pci_alloc_consistent(adapter->pdev, 17009aebddd1SJeff Kirsher get_fat_cmd.size, 17019aebddd1SJeff Kirsher &get_fat_cmd.dma); 17029aebddd1SJeff Kirsher if (!get_fat_cmd.va) { 17039aebddd1SJeff Kirsher status = -ENOMEM; 17049aebddd1SJeff Kirsher dev_err(&adapter->pdev->dev, 17059aebddd1SJeff Kirsher "Memory allocation failure while retrieving FAT data\n"); 17069aebddd1SJeff Kirsher return; 17079aebddd1SJeff Kirsher } 17089aebddd1SJeff Kirsher 17099aebddd1SJeff Kirsher spin_lock_bh(&adapter->mcc_lock); 17109aebddd1SJeff Kirsher 17119aebddd1SJeff Kirsher while (total_size) { 17129aebddd1SJeff Kirsher buf_size = min(total_size, (u32)60*1024); 17139aebddd1SJeff Kirsher total_size -= buf_size; 17149aebddd1SJeff Kirsher 17159aebddd1SJeff Kirsher wrb = wrb_from_mccq(adapter); 17169aebddd1SJeff Kirsher if (!wrb) { 17179aebddd1SJeff Kirsher status = -EBUSY; 17189aebddd1SJeff Kirsher goto err; 17199aebddd1SJeff Kirsher } 17209aebddd1SJeff Kirsher req = get_fat_cmd.va; 17219aebddd1SJeff Kirsher 17229aebddd1SJeff Kirsher payload_len = sizeof(struct be_cmd_req_get_fat) + buf_size; 1723106df1e3SSomnath Kotur be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1724a2cc4e0bSSathya Perla OPCODE_COMMON_MANAGE_FAT, payload_len, 1725a2cc4e0bSSathya Perla wrb, &get_fat_cmd); 17269aebddd1SJeff Kirsher 17279aebddd1SJeff Kirsher req->fat_operation = cpu_to_le32(RETRIEVE_FAT); 17289aebddd1SJeff Kirsher req->read_log_offset = cpu_to_le32(log_offset); 17299aebddd1SJeff Kirsher req->read_log_length = cpu_to_le32(buf_size); 17309aebddd1SJeff Kirsher req->data_buffer_size = cpu_to_le32(buf_size); 17319aebddd1SJeff Kirsher 17329aebddd1SJeff Kirsher status = be_mcc_notify_wait(adapter); 17339aebddd1SJeff Kirsher if (!status) { 17349aebddd1SJeff Kirsher struct be_cmd_resp_get_fat *resp = get_fat_cmd.va; 17359aebddd1SJeff Kirsher memcpy(buf + offset, 17369aebddd1SJeff Kirsher resp->data_buffer, 173792aa9214SSomnath Kotur le32_to_cpu(resp->read_log_length)); 17389aebddd1SJeff Kirsher } else { 17399aebddd1SJeff Kirsher dev_err(&adapter->pdev->dev, "FAT Table Retrieve error\n"); 17409aebddd1SJeff Kirsher goto err; 17419aebddd1SJeff Kirsher } 17429aebddd1SJeff Kirsher offset += buf_size; 17439aebddd1SJeff Kirsher log_offset += buf_size; 17449aebddd1SJeff Kirsher } 17459aebddd1SJeff Kirsher err: 17469aebddd1SJeff Kirsher pci_free_consistent(adapter->pdev, get_fat_cmd.size, 1747a2cc4e0bSSathya Perla get_fat_cmd.va, get_fat_cmd.dma); 17489aebddd1SJeff Kirsher spin_unlock_bh(&adapter->mcc_lock); 17499aebddd1SJeff Kirsher } 17509aebddd1SJeff Kirsher 175104b71175SSathya Perla /* Uses synchronous mcc */ 1752e97e3cdaSKalesh AP int be_cmd_get_fw_ver(struct be_adapter *adapter) 17539aebddd1SJeff Kirsher { 17549aebddd1SJeff Kirsher struct be_mcc_wrb *wrb; 17559aebddd1SJeff Kirsher struct be_cmd_req_get_fw_version *req; 17569aebddd1SJeff Kirsher int status; 17579aebddd1SJeff Kirsher 175804b71175SSathya Perla spin_lock_bh(&adapter->mcc_lock); 17599aebddd1SJeff Kirsher 176004b71175SSathya Perla wrb = wrb_from_mccq(adapter); 176104b71175SSathya Perla if (!wrb) { 176204b71175SSathya Perla status = -EBUSY; 176304b71175SSathya Perla goto err; 176404b71175SSathya Perla } 176504b71175SSathya Perla 17669aebddd1SJeff Kirsher req = embedded_payload(wrb); 17679aebddd1SJeff Kirsher 1768106df1e3SSomnath Kotur be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1769a2cc4e0bSSathya Perla OPCODE_COMMON_GET_FW_VERSION, sizeof(*req), wrb, 1770a2cc4e0bSSathya Perla NULL); 177104b71175SSathya Perla status = be_mcc_notify_wait(adapter); 17729aebddd1SJeff Kirsher if (!status) { 17739aebddd1SJeff Kirsher struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb); 1774acbafeb1SSathya Perla 1775e97e3cdaSKalesh AP strcpy(adapter->fw_ver, resp->firmware_version_string); 1776e97e3cdaSKalesh AP strcpy(adapter->fw_on_flash, resp->fw_on_flash_version_string); 17779aebddd1SJeff Kirsher } 177804b71175SSathya Perla err: 177904b71175SSathya Perla spin_unlock_bh(&adapter->mcc_lock); 17809aebddd1SJeff Kirsher return status; 17819aebddd1SJeff Kirsher } 17829aebddd1SJeff Kirsher 17839aebddd1SJeff Kirsher /* set the EQ delay interval of an EQ to specified value 17849aebddd1SJeff Kirsher * Uses async mcc 17859aebddd1SJeff Kirsher */ 17862632bafdSSathya Perla int be_cmd_modify_eqd(struct be_adapter *adapter, struct be_set_eqd *set_eqd, 17872632bafdSSathya Perla int num) 17889aebddd1SJeff Kirsher { 17899aebddd1SJeff Kirsher struct be_mcc_wrb *wrb; 17909aebddd1SJeff Kirsher struct be_cmd_req_modify_eq_delay *req; 17912632bafdSSathya Perla int status = 0, i; 17929aebddd1SJeff Kirsher 17939aebddd1SJeff Kirsher spin_lock_bh(&adapter->mcc_lock); 17949aebddd1SJeff Kirsher 17959aebddd1SJeff Kirsher wrb = wrb_from_mccq(adapter); 17969aebddd1SJeff Kirsher if (!wrb) { 17979aebddd1SJeff Kirsher status = -EBUSY; 17989aebddd1SJeff Kirsher goto err; 17999aebddd1SJeff Kirsher } 18009aebddd1SJeff Kirsher req = embedded_payload(wrb); 18019aebddd1SJeff Kirsher 1802106df1e3SSomnath Kotur be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1803a2cc4e0bSSathya Perla OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req), wrb, 1804a2cc4e0bSSathya Perla NULL); 18059aebddd1SJeff Kirsher 18062632bafdSSathya Perla req->num_eq = cpu_to_le32(num); 18072632bafdSSathya Perla for (i = 0; i < num; i++) { 18082632bafdSSathya Perla req->set_eqd[i].eq_id = cpu_to_le32(set_eqd[i].eq_id); 18092632bafdSSathya Perla req->set_eqd[i].phase = 0; 18102632bafdSSathya Perla req->set_eqd[i].delay_multiplier = 18112632bafdSSathya Perla cpu_to_le32(set_eqd[i].delay_multiplier); 18122632bafdSSathya Perla } 18139aebddd1SJeff Kirsher 18149aebddd1SJeff Kirsher be_mcc_notify(adapter); 18159aebddd1SJeff Kirsher err: 18169aebddd1SJeff Kirsher spin_unlock_bh(&adapter->mcc_lock); 18179aebddd1SJeff Kirsher return status; 18189aebddd1SJeff Kirsher } 18199aebddd1SJeff Kirsher 18209aebddd1SJeff Kirsher /* Uses sycnhronous mcc */ 18219aebddd1SJeff Kirsher int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array, 18224d567d97SKalesh AP u32 num) 18239aebddd1SJeff Kirsher { 18249aebddd1SJeff Kirsher struct be_mcc_wrb *wrb; 18259aebddd1SJeff Kirsher struct be_cmd_req_vlan_config *req; 18269aebddd1SJeff Kirsher int status; 18279aebddd1SJeff Kirsher 18289aebddd1SJeff Kirsher spin_lock_bh(&adapter->mcc_lock); 18299aebddd1SJeff Kirsher 18309aebddd1SJeff Kirsher wrb = wrb_from_mccq(adapter); 18319aebddd1SJeff Kirsher if (!wrb) { 18329aebddd1SJeff Kirsher status = -EBUSY; 18339aebddd1SJeff Kirsher goto err; 18349aebddd1SJeff Kirsher } 18359aebddd1SJeff Kirsher req = embedded_payload(wrb); 18369aebddd1SJeff Kirsher 1837106df1e3SSomnath Kotur be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1838a2cc4e0bSSathya Perla OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req), 1839a2cc4e0bSSathya Perla wrb, NULL); 18409aebddd1SJeff Kirsher 18419aebddd1SJeff Kirsher req->interface_id = if_id; 1842012bd387SAjit Khaparde req->untagged = BE_IF_FLAGS_UNTAGGED & be_if_cap_flags(adapter) ? 1 : 0; 18439aebddd1SJeff Kirsher req->num_vlan = num; 18449aebddd1SJeff Kirsher memcpy(req->normal_vlan, vtag_array, 18459aebddd1SJeff Kirsher req->num_vlan * sizeof(vtag_array[0])); 18469aebddd1SJeff Kirsher 18479aebddd1SJeff Kirsher status = be_mcc_notify_wait(adapter); 18489aebddd1SJeff Kirsher err: 18499aebddd1SJeff Kirsher spin_unlock_bh(&adapter->mcc_lock); 18509aebddd1SJeff Kirsher return status; 18519aebddd1SJeff Kirsher } 18529aebddd1SJeff Kirsher 18539aebddd1SJeff Kirsher int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value) 18549aebddd1SJeff Kirsher { 18559aebddd1SJeff Kirsher struct be_mcc_wrb *wrb; 18569aebddd1SJeff Kirsher struct be_dma_mem *mem = &adapter->rx_filter; 18579aebddd1SJeff Kirsher struct be_cmd_req_rx_filter *req = mem->va; 18589aebddd1SJeff Kirsher int status; 18599aebddd1SJeff Kirsher 18609aebddd1SJeff Kirsher spin_lock_bh(&adapter->mcc_lock); 18619aebddd1SJeff Kirsher 18629aebddd1SJeff Kirsher wrb = wrb_from_mccq(adapter); 18639aebddd1SJeff Kirsher if (!wrb) { 18649aebddd1SJeff Kirsher status = -EBUSY; 18659aebddd1SJeff Kirsher goto err; 18669aebddd1SJeff Kirsher } 18679aebddd1SJeff Kirsher memset(req, 0, sizeof(*req)); 1868106df1e3SSomnath Kotur be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1869106df1e3SSomnath Kotur OPCODE_COMMON_NTWK_RX_FILTER, sizeof(*req), 1870106df1e3SSomnath Kotur wrb, mem); 18719aebddd1SJeff Kirsher 18729aebddd1SJeff Kirsher req->if_id = cpu_to_le32(adapter->if_handle); 18739aebddd1SJeff Kirsher if (flags & IFF_PROMISC) { 18749aebddd1SJeff Kirsher req->if_flags_mask = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS | 1875c5dae588SAjit Khaparde BE_IF_FLAGS_VLAN_PROMISCUOUS | 1876c5dae588SAjit Khaparde BE_IF_FLAGS_MCAST_PROMISCUOUS); 18779aebddd1SJeff Kirsher if (value == ON) 1878a2cc4e0bSSathya Perla req->if_flags = 1879a2cc4e0bSSathya Perla cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS | 1880c5dae588SAjit Khaparde BE_IF_FLAGS_VLAN_PROMISCUOUS | 1881c5dae588SAjit Khaparde BE_IF_FLAGS_MCAST_PROMISCUOUS); 18829aebddd1SJeff Kirsher } else if (flags & IFF_ALLMULTI) { 18839aebddd1SJeff Kirsher req->if_flags_mask = req->if_flags = 18849aebddd1SJeff Kirsher cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS); 1885d9d604f8SAjit Khaparde } else if (flags & BE_FLAGS_VLAN_PROMISC) { 1886d9d604f8SAjit Khaparde req->if_flags_mask = cpu_to_le32(BE_IF_FLAGS_VLAN_PROMISCUOUS); 1887d9d604f8SAjit Khaparde 1888d9d604f8SAjit Khaparde if (value == ON) 1889d9d604f8SAjit Khaparde req->if_flags = 1890d9d604f8SAjit Khaparde cpu_to_le32(BE_IF_FLAGS_VLAN_PROMISCUOUS); 18919aebddd1SJeff Kirsher } else { 18929aebddd1SJeff Kirsher struct netdev_hw_addr *ha; 18939aebddd1SJeff Kirsher int i = 0; 18949aebddd1SJeff Kirsher 18958e7d3f68SSathya Perla req->if_flags_mask = req->if_flags = 18968e7d3f68SSathya Perla cpu_to_le32(BE_IF_FLAGS_MULTICAST); 18971610c79fSPadmanabh Ratnakar 18981610c79fSPadmanabh Ratnakar /* Reset mcast promisc mode if already set by setting mask 18991610c79fSPadmanabh Ratnakar * and not setting flags field 19001610c79fSPadmanabh Ratnakar */ 19011610c79fSPadmanabh Ratnakar req->if_flags_mask |= 1902abb93951SPadmanabh Ratnakar cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS & 190392bf14abSSathya Perla be_if_cap_flags(adapter)); 1904016f97b1SPadmanabh Ratnakar req->mcast_num = cpu_to_le32(netdev_mc_count(adapter->netdev)); 19059aebddd1SJeff Kirsher netdev_for_each_mc_addr(ha, adapter->netdev) 19069aebddd1SJeff Kirsher memcpy(req->mcast_mac[i++].byte, ha->addr, ETH_ALEN); 19079aebddd1SJeff Kirsher } 19089aebddd1SJeff Kirsher 1909012bd387SAjit Khaparde if ((req->if_flags_mask & cpu_to_le32(be_if_cap_flags(adapter))) != 1910012bd387SAjit Khaparde req->if_flags_mask) { 1911012bd387SAjit Khaparde dev_warn(&adapter->pdev->dev, 1912012bd387SAjit Khaparde "Cannot set rx filter flags 0x%x\n", 1913012bd387SAjit Khaparde req->if_flags_mask); 1914012bd387SAjit Khaparde dev_warn(&adapter->pdev->dev, 1915012bd387SAjit Khaparde "Interface is capable of 0x%x flags only\n", 1916012bd387SAjit Khaparde be_if_cap_flags(adapter)); 1917012bd387SAjit Khaparde } 1918012bd387SAjit Khaparde req->if_flags_mask &= cpu_to_le32(be_if_cap_flags(adapter)); 1919012bd387SAjit Khaparde 19209aebddd1SJeff Kirsher status = be_mcc_notify_wait(adapter); 1921012bd387SAjit Khaparde 19229aebddd1SJeff Kirsher err: 19239aebddd1SJeff Kirsher spin_unlock_bh(&adapter->mcc_lock); 19249aebddd1SJeff Kirsher return status; 19259aebddd1SJeff Kirsher } 19269aebddd1SJeff Kirsher 19279aebddd1SJeff Kirsher /* Uses synchrounous mcc */ 19289aebddd1SJeff Kirsher int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc) 19299aebddd1SJeff Kirsher { 19309aebddd1SJeff Kirsher struct be_mcc_wrb *wrb; 19319aebddd1SJeff Kirsher struct be_cmd_req_set_flow_control *req; 19329aebddd1SJeff Kirsher int status; 19339aebddd1SJeff Kirsher 1934f25b119cSPadmanabh Ratnakar if (!be_cmd_allowed(adapter, OPCODE_COMMON_SET_FLOW_CONTROL, 1935f25b119cSPadmanabh Ratnakar CMD_SUBSYSTEM_COMMON)) 1936f25b119cSPadmanabh Ratnakar return -EPERM; 1937f25b119cSPadmanabh Ratnakar 19389aebddd1SJeff Kirsher spin_lock_bh(&adapter->mcc_lock); 19399aebddd1SJeff Kirsher 19409aebddd1SJeff Kirsher wrb = wrb_from_mccq(adapter); 19419aebddd1SJeff Kirsher if (!wrb) { 19429aebddd1SJeff Kirsher status = -EBUSY; 19439aebddd1SJeff Kirsher goto err; 19449aebddd1SJeff Kirsher } 19459aebddd1SJeff Kirsher req = embedded_payload(wrb); 19469aebddd1SJeff Kirsher 1947106df1e3SSomnath Kotur be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1948a2cc4e0bSSathya Perla OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req), 1949a2cc4e0bSSathya Perla wrb, NULL); 19509aebddd1SJeff Kirsher 19519aebddd1SJeff Kirsher req->tx_flow_control = cpu_to_le16((u16)tx_fc); 19529aebddd1SJeff Kirsher req->rx_flow_control = cpu_to_le16((u16)rx_fc); 19539aebddd1SJeff Kirsher 19549aebddd1SJeff Kirsher status = be_mcc_notify_wait(adapter); 19559aebddd1SJeff Kirsher 19569aebddd1SJeff Kirsher err: 19579aebddd1SJeff Kirsher spin_unlock_bh(&adapter->mcc_lock); 19589aebddd1SJeff Kirsher return status; 19599aebddd1SJeff Kirsher } 19609aebddd1SJeff Kirsher 19619aebddd1SJeff Kirsher /* Uses sycn mcc */ 19629aebddd1SJeff Kirsher int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc) 19639aebddd1SJeff Kirsher { 19649aebddd1SJeff Kirsher struct be_mcc_wrb *wrb; 19659aebddd1SJeff Kirsher struct be_cmd_req_get_flow_control *req; 19669aebddd1SJeff Kirsher int status; 19679aebddd1SJeff Kirsher 1968f25b119cSPadmanabh Ratnakar if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_FLOW_CONTROL, 1969f25b119cSPadmanabh Ratnakar CMD_SUBSYSTEM_COMMON)) 1970f25b119cSPadmanabh Ratnakar return -EPERM; 1971f25b119cSPadmanabh Ratnakar 19729aebddd1SJeff Kirsher spin_lock_bh(&adapter->mcc_lock); 19739aebddd1SJeff Kirsher 19749aebddd1SJeff Kirsher wrb = wrb_from_mccq(adapter); 19759aebddd1SJeff Kirsher if (!wrb) { 19769aebddd1SJeff Kirsher status = -EBUSY; 19779aebddd1SJeff Kirsher goto err; 19789aebddd1SJeff Kirsher } 19799aebddd1SJeff Kirsher req = embedded_payload(wrb); 19809aebddd1SJeff Kirsher 1981106df1e3SSomnath Kotur be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1982a2cc4e0bSSathya Perla OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req), 1983a2cc4e0bSSathya Perla wrb, NULL); 19849aebddd1SJeff Kirsher 19859aebddd1SJeff Kirsher status = be_mcc_notify_wait(adapter); 19869aebddd1SJeff Kirsher if (!status) { 19879aebddd1SJeff Kirsher struct be_cmd_resp_get_flow_control *resp = 19889aebddd1SJeff Kirsher embedded_payload(wrb); 19899aebddd1SJeff Kirsher *tx_fc = le16_to_cpu(resp->tx_flow_control); 19909aebddd1SJeff Kirsher *rx_fc = le16_to_cpu(resp->rx_flow_control); 19919aebddd1SJeff Kirsher } 19929aebddd1SJeff Kirsher 19939aebddd1SJeff Kirsher err: 19949aebddd1SJeff Kirsher spin_unlock_bh(&adapter->mcc_lock); 19959aebddd1SJeff Kirsher return status; 19969aebddd1SJeff Kirsher } 19979aebddd1SJeff Kirsher 19989aebddd1SJeff Kirsher /* Uses mbox */ 1999e97e3cdaSKalesh AP int be_cmd_query_fw_cfg(struct be_adapter *adapter) 20009aebddd1SJeff Kirsher { 20019aebddd1SJeff Kirsher struct be_mcc_wrb *wrb; 20029aebddd1SJeff Kirsher struct be_cmd_req_query_fw_cfg *req; 20039aebddd1SJeff Kirsher int status; 20049aebddd1SJeff Kirsher 20059aebddd1SJeff Kirsher if (mutex_lock_interruptible(&adapter->mbox_lock)) 20069aebddd1SJeff Kirsher return -1; 20079aebddd1SJeff Kirsher 20089aebddd1SJeff Kirsher wrb = wrb_from_mbox(adapter); 20099aebddd1SJeff Kirsher req = embedded_payload(wrb); 20109aebddd1SJeff Kirsher 2011106df1e3SSomnath Kotur be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2012a2cc4e0bSSathya Perla OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, 2013a2cc4e0bSSathya Perla sizeof(*req), wrb, NULL); 20149aebddd1SJeff Kirsher 20159aebddd1SJeff Kirsher status = be_mbox_notify_wait(adapter); 20169aebddd1SJeff Kirsher if (!status) { 20179aebddd1SJeff Kirsher struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb); 2018e97e3cdaSKalesh AP adapter->port_num = le32_to_cpu(resp->phys_port); 2019e97e3cdaSKalesh AP adapter->function_mode = le32_to_cpu(resp->function_mode); 2020e97e3cdaSKalesh AP adapter->function_caps = le32_to_cpu(resp->function_caps); 2021e97e3cdaSKalesh AP adapter->asic_rev = le32_to_cpu(resp->asic_revision) & 0xFF; 2022acbafeb1SSathya Perla dev_info(&adapter->pdev->dev, 2023acbafeb1SSathya Perla "FW config: function_mode=0x%x, function_caps=0x%x\n", 2024acbafeb1SSathya Perla adapter->function_mode, adapter->function_caps); 20259aebddd1SJeff Kirsher } 20269aebddd1SJeff Kirsher 20279aebddd1SJeff Kirsher mutex_unlock(&adapter->mbox_lock); 20289aebddd1SJeff Kirsher return status; 20299aebddd1SJeff Kirsher } 20309aebddd1SJeff Kirsher 20319aebddd1SJeff Kirsher /* Uses mbox */ 20329aebddd1SJeff Kirsher int be_cmd_reset_function(struct be_adapter *adapter) 20339aebddd1SJeff Kirsher { 20349aebddd1SJeff Kirsher struct be_mcc_wrb *wrb; 20359aebddd1SJeff Kirsher struct be_cmd_req_hdr *req; 20369aebddd1SJeff Kirsher int status; 20379aebddd1SJeff Kirsher 2038bf99e50dSPadmanabh Ratnakar if (lancer_chip(adapter)) { 2039bf99e50dSPadmanabh Ratnakar status = lancer_wait_ready(adapter); 2040bf99e50dSPadmanabh Ratnakar if (!status) { 2041bf99e50dSPadmanabh Ratnakar iowrite32(SLI_PORT_CONTROL_IP_MASK, 2042bf99e50dSPadmanabh Ratnakar adapter->db + SLIPORT_CONTROL_OFFSET); 2043bf99e50dSPadmanabh Ratnakar status = lancer_test_and_set_rdy_state(adapter); 2044bf99e50dSPadmanabh Ratnakar } 2045bf99e50dSPadmanabh Ratnakar if (status) { 2046bf99e50dSPadmanabh Ratnakar dev_err(&adapter->pdev->dev, 2047bf99e50dSPadmanabh Ratnakar "Adapter in non recoverable error\n"); 2048bf99e50dSPadmanabh Ratnakar } 2049bf99e50dSPadmanabh Ratnakar return status; 2050bf99e50dSPadmanabh Ratnakar } 2051bf99e50dSPadmanabh Ratnakar 20529aebddd1SJeff Kirsher if (mutex_lock_interruptible(&adapter->mbox_lock)) 20539aebddd1SJeff Kirsher return -1; 20549aebddd1SJeff Kirsher 20559aebddd1SJeff Kirsher wrb = wrb_from_mbox(adapter); 20569aebddd1SJeff Kirsher req = embedded_payload(wrb); 20579aebddd1SJeff Kirsher 2058106df1e3SSomnath Kotur be_wrb_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON, 2059a2cc4e0bSSathya Perla OPCODE_COMMON_FUNCTION_RESET, sizeof(*req), wrb, 2060a2cc4e0bSSathya Perla NULL); 20619aebddd1SJeff Kirsher 20629aebddd1SJeff Kirsher status = be_mbox_notify_wait(adapter); 20639aebddd1SJeff Kirsher 20649aebddd1SJeff Kirsher mutex_unlock(&adapter->mbox_lock); 20659aebddd1SJeff Kirsher return status; 20669aebddd1SJeff Kirsher } 20679aebddd1SJeff Kirsher 2068594ad54aSSuresh Reddy int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable, 206933cb0fa7SBen Hutchings u32 rss_hash_opts, u16 table_size, const u8 *rss_hkey) 20709aebddd1SJeff Kirsher { 20719aebddd1SJeff Kirsher struct be_mcc_wrb *wrb; 20729aebddd1SJeff Kirsher struct be_cmd_req_rss_config *req; 20739aebddd1SJeff Kirsher int status; 20749aebddd1SJeff Kirsher 2075da1388d6SVasundhara Volam if (!(be_if_cap_flags(adapter) & BE_IF_FLAGS_RSS)) 2076da1388d6SVasundhara Volam return 0; 2077da1388d6SVasundhara Volam 2078b51aa367SKalesh AP spin_lock_bh(&adapter->mcc_lock); 20799aebddd1SJeff Kirsher 2080b51aa367SKalesh AP wrb = wrb_from_mccq(adapter); 2081b51aa367SKalesh AP if (!wrb) { 2082b51aa367SKalesh AP status = -EBUSY; 2083b51aa367SKalesh AP goto err; 2084b51aa367SKalesh AP } 20859aebddd1SJeff Kirsher req = embedded_payload(wrb); 20869aebddd1SJeff Kirsher 2087106df1e3SSomnath Kotur be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, 2088106df1e3SSomnath Kotur OPCODE_ETH_RSS_CONFIG, sizeof(*req), wrb, NULL); 20899aebddd1SJeff Kirsher 20909aebddd1SJeff Kirsher req->if_id = cpu_to_le32(adapter->if_handle); 2091594ad54aSSuresh Reddy req->enable_rss = cpu_to_le16(rss_hash_opts); 20929aebddd1SJeff Kirsher req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1); 2093594ad54aSSuresh Reddy 2094b51aa367SKalesh AP if (!BEx_chip(adapter)) 2095594ad54aSSuresh Reddy req->hdr.version = 1; 2096594ad54aSSuresh Reddy 20979aebddd1SJeff Kirsher memcpy(req->cpu_table, rsstable, table_size); 2098e2557877SVenkata Duvvuru memcpy(req->hash, rss_hkey, RSS_HASH_KEY_LEN); 20999aebddd1SJeff Kirsher be_dws_cpu_to_le(req->hash, sizeof(req->hash)); 21009aebddd1SJeff Kirsher 2101b51aa367SKalesh AP status = be_mcc_notify_wait(adapter); 2102b51aa367SKalesh AP err: 2103b51aa367SKalesh AP spin_unlock_bh(&adapter->mcc_lock); 21049aebddd1SJeff Kirsher return status; 21059aebddd1SJeff Kirsher } 21069aebddd1SJeff Kirsher 21079aebddd1SJeff Kirsher /* Uses sync mcc */ 21089aebddd1SJeff Kirsher int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num, 21099aebddd1SJeff Kirsher u8 bcn, u8 sts, u8 state) 21109aebddd1SJeff Kirsher { 21119aebddd1SJeff Kirsher struct be_mcc_wrb *wrb; 21129aebddd1SJeff Kirsher struct be_cmd_req_enable_disable_beacon *req; 21139aebddd1SJeff Kirsher int status; 21149aebddd1SJeff Kirsher 21159aebddd1SJeff Kirsher spin_lock_bh(&adapter->mcc_lock); 21169aebddd1SJeff Kirsher 21179aebddd1SJeff Kirsher wrb = wrb_from_mccq(adapter); 21189aebddd1SJeff Kirsher if (!wrb) { 21199aebddd1SJeff Kirsher status = -EBUSY; 21209aebddd1SJeff Kirsher goto err; 21219aebddd1SJeff Kirsher } 21229aebddd1SJeff Kirsher req = embedded_payload(wrb); 21239aebddd1SJeff Kirsher 2124106df1e3SSomnath Kotur be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2125a2cc4e0bSSathya Perla OPCODE_COMMON_ENABLE_DISABLE_BEACON, 2126a2cc4e0bSSathya Perla sizeof(*req), wrb, NULL); 21279aebddd1SJeff Kirsher 21289aebddd1SJeff Kirsher req->port_num = port_num; 21299aebddd1SJeff Kirsher req->beacon_state = state; 21309aebddd1SJeff Kirsher req->beacon_duration = bcn; 21319aebddd1SJeff Kirsher req->status_duration = sts; 21329aebddd1SJeff Kirsher 21339aebddd1SJeff Kirsher status = be_mcc_notify_wait(adapter); 21349aebddd1SJeff Kirsher 21359aebddd1SJeff Kirsher err: 21369aebddd1SJeff Kirsher spin_unlock_bh(&adapter->mcc_lock); 21379aebddd1SJeff Kirsher return status; 21389aebddd1SJeff Kirsher } 21399aebddd1SJeff Kirsher 21409aebddd1SJeff Kirsher /* Uses sync mcc */ 21419aebddd1SJeff Kirsher int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state) 21429aebddd1SJeff Kirsher { 21439aebddd1SJeff Kirsher struct be_mcc_wrb *wrb; 21449aebddd1SJeff Kirsher struct be_cmd_req_get_beacon_state *req; 21459aebddd1SJeff Kirsher int status; 21469aebddd1SJeff Kirsher 21479aebddd1SJeff Kirsher spin_lock_bh(&adapter->mcc_lock); 21489aebddd1SJeff Kirsher 21499aebddd1SJeff Kirsher wrb = wrb_from_mccq(adapter); 21509aebddd1SJeff Kirsher if (!wrb) { 21519aebddd1SJeff Kirsher status = -EBUSY; 21529aebddd1SJeff Kirsher goto err; 21539aebddd1SJeff Kirsher } 21549aebddd1SJeff Kirsher req = embedded_payload(wrb); 21559aebddd1SJeff Kirsher 2156106df1e3SSomnath Kotur be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2157a2cc4e0bSSathya Perla OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req), 2158a2cc4e0bSSathya Perla wrb, NULL); 21599aebddd1SJeff Kirsher 21609aebddd1SJeff Kirsher req->port_num = port_num; 21619aebddd1SJeff Kirsher 21629aebddd1SJeff Kirsher status = be_mcc_notify_wait(adapter); 21639aebddd1SJeff Kirsher if (!status) { 21649aebddd1SJeff Kirsher struct be_cmd_resp_get_beacon_state *resp = 21659aebddd1SJeff Kirsher embedded_payload(wrb); 21669aebddd1SJeff Kirsher *state = resp->beacon_state; 21679aebddd1SJeff Kirsher } 21689aebddd1SJeff Kirsher 21699aebddd1SJeff Kirsher err: 21709aebddd1SJeff Kirsher spin_unlock_bh(&adapter->mcc_lock); 21719aebddd1SJeff Kirsher return status; 21729aebddd1SJeff Kirsher } 21739aebddd1SJeff Kirsher 21749aebddd1SJeff Kirsher int lancer_cmd_write_object(struct be_adapter *adapter, struct be_dma_mem *cmd, 2175f67ef7baSPadmanabh Ratnakar u32 data_size, u32 data_offset, 2176f67ef7baSPadmanabh Ratnakar const char *obj_name, u32 *data_written, 2177f67ef7baSPadmanabh Ratnakar u8 *change_status, u8 *addn_status) 21789aebddd1SJeff Kirsher { 21799aebddd1SJeff Kirsher struct be_mcc_wrb *wrb; 21809aebddd1SJeff Kirsher struct lancer_cmd_req_write_object *req; 21819aebddd1SJeff Kirsher struct lancer_cmd_resp_write_object *resp; 21829aebddd1SJeff Kirsher void *ctxt = NULL; 21839aebddd1SJeff Kirsher int status; 21849aebddd1SJeff Kirsher 21859aebddd1SJeff Kirsher spin_lock_bh(&adapter->mcc_lock); 21869aebddd1SJeff Kirsher adapter->flash_status = 0; 21879aebddd1SJeff Kirsher 21889aebddd1SJeff Kirsher wrb = wrb_from_mccq(adapter); 21899aebddd1SJeff Kirsher if (!wrb) { 21909aebddd1SJeff Kirsher status = -EBUSY; 21919aebddd1SJeff Kirsher goto err_unlock; 21929aebddd1SJeff Kirsher } 21939aebddd1SJeff Kirsher 21949aebddd1SJeff Kirsher req = embedded_payload(wrb); 21959aebddd1SJeff Kirsher 2196106df1e3SSomnath Kotur be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 21979aebddd1SJeff Kirsher OPCODE_COMMON_WRITE_OBJECT, 2198106df1e3SSomnath Kotur sizeof(struct lancer_cmd_req_write_object), wrb, 2199106df1e3SSomnath Kotur NULL); 22009aebddd1SJeff Kirsher 22019aebddd1SJeff Kirsher ctxt = &req->context; 22029aebddd1SJeff Kirsher AMAP_SET_BITS(struct amap_lancer_write_obj_context, 22039aebddd1SJeff Kirsher write_length, ctxt, data_size); 22049aebddd1SJeff Kirsher 22059aebddd1SJeff Kirsher if (data_size == 0) 22069aebddd1SJeff Kirsher AMAP_SET_BITS(struct amap_lancer_write_obj_context, 22079aebddd1SJeff Kirsher eof, ctxt, 1); 22089aebddd1SJeff Kirsher else 22099aebddd1SJeff Kirsher AMAP_SET_BITS(struct amap_lancer_write_obj_context, 22109aebddd1SJeff Kirsher eof, ctxt, 0); 22119aebddd1SJeff Kirsher 22129aebddd1SJeff Kirsher be_dws_cpu_to_le(ctxt, sizeof(req->context)); 22139aebddd1SJeff Kirsher req->write_offset = cpu_to_le32(data_offset); 22149aebddd1SJeff Kirsher strcpy(req->object_name, obj_name); 22159aebddd1SJeff Kirsher req->descriptor_count = cpu_to_le32(1); 22169aebddd1SJeff Kirsher req->buf_len = cpu_to_le32(data_size); 22179aebddd1SJeff Kirsher req->addr_low = cpu_to_le32((cmd->dma + 22189aebddd1SJeff Kirsher sizeof(struct lancer_cmd_req_write_object)) 22199aebddd1SJeff Kirsher & 0xFFFFFFFF); 22209aebddd1SJeff Kirsher req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma + 22219aebddd1SJeff Kirsher sizeof(struct lancer_cmd_req_write_object))); 22229aebddd1SJeff Kirsher 22239aebddd1SJeff Kirsher be_mcc_notify(adapter); 22249aebddd1SJeff Kirsher spin_unlock_bh(&adapter->mcc_lock); 22259aebddd1SJeff Kirsher 22265eeff635SSuresh Reddy if (!wait_for_completion_timeout(&adapter->et_cmd_compl, 2227701962d0SSomnath Kotur msecs_to_jiffies(60000))) 2228fd45160cSKalesh AP status = -ETIMEDOUT; 22299aebddd1SJeff Kirsher else 22309aebddd1SJeff Kirsher status = adapter->flash_status; 22319aebddd1SJeff Kirsher 22329aebddd1SJeff Kirsher resp = embedded_payload(wrb); 2233f67ef7baSPadmanabh Ratnakar if (!status) { 22349aebddd1SJeff Kirsher *data_written = le32_to_cpu(resp->actual_write_len); 2235f67ef7baSPadmanabh Ratnakar *change_status = resp->change_status; 2236f67ef7baSPadmanabh Ratnakar } else { 22379aebddd1SJeff Kirsher *addn_status = resp->additional_status; 2238f67ef7baSPadmanabh Ratnakar } 22399aebddd1SJeff Kirsher 22409aebddd1SJeff Kirsher return status; 22419aebddd1SJeff Kirsher 22429aebddd1SJeff Kirsher err_unlock: 22439aebddd1SJeff Kirsher spin_unlock_bh(&adapter->mcc_lock); 22449aebddd1SJeff Kirsher return status; 22459aebddd1SJeff Kirsher } 22469aebddd1SJeff Kirsher 2247f0613380SKalesh AP int lancer_cmd_delete_object(struct be_adapter *adapter, const char *obj_name) 2248f0613380SKalesh AP { 2249f0613380SKalesh AP struct lancer_cmd_req_delete_object *req; 2250f0613380SKalesh AP struct be_mcc_wrb *wrb; 2251f0613380SKalesh AP int status; 2252f0613380SKalesh AP 2253f0613380SKalesh AP spin_lock_bh(&adapter->mcc_lock); 2254f0613380SKalesh AP 2255f0613380SKalesh AP wrb = wrb_from_mccq(adapter); 2256f0613380SKalesh AP if (!wrb) { 2257f0613380SKalesh AP status = -EBUSY; 2258f0613380SKalesh AP goto err; 2259f0613380SKalesh AP } 2260f0613380SKalesh AP 2261f0613380SKalesh AP req = embedded_payload(wrb); 2262f0613380SKalesh AP 2263f0613380SKalesh AP be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2264f0613380SKalesh AP OPCODE_COMMON_DELETE_OBJECT, 2265f0613380SKalesh AP sizeof(*req), wrb, NULL); 2266f0613380SKalesh AP 2267f0613380SKalesh AP strcpy(req->object_name, obj_name); 2268f0613380SKalesh AP 2269f0613380SKalesh AP status = be_mcc_notify_wait(adapter); 2270f0613380SKalesh AP err: 2271f0613380SKalesh AP spin_unlock_bh(&adapter->mcc_lock); 2272f0613380SKalesh AP return status; 2273f0613380SKalesh AP } 2274f0613380SKalesh AP 2275de49bd5aSPadmanabh Ratnakar int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd, 2276de49bd5aSPadmanabh Ratnakar u32 data_size, u32 data_offset, const char *obj_name, 2277de49bd5aSPadmanabh Ratnakar u32 *data_read, u32 *eof, u8 *addn_status) 2278de49bd5aSPadmanabh Ratnakar { 2279de49bd5aSPadmanabh Ratnakar struct be_mcc_wrb *wrb; 2280de49bd5aSPadmanabh Ratnakar struct lancer_cmd_req_read_object *req; 2281de49bd5aSPadmanabh Ratnakar struct lancer_cmd_resp_read_object *resp; 2282de49bd5aSPadmanabh Ratnakar int status; 2283de49bd5aSPadmanabh Ratnakar 2284de49bd5aSPadmanabh Ratnakar spin_lock_bh(&adapter->mcc_lock); 2285de49bd5aSPadmanabh Ratnakar 2286de49bd5aSPadmanabh Ratnakar wrb = wrb_from_mccq(adapter); 2287de49bd5aSPadmanabh Ratnakar if (!wrb) { 2288de49bd5aSPadmanabh Ratnakar status = -EBUSY; 2289de49bd5aSPadmanabh Ratnakar goto err_unlock; 2290de49bd5aSPadmanabh Ratnakar } 2291de49bd5aSPadmanabh Ratnakar 2292de49bd5aSPadmanabh Ratnakar req = embedded_payload(wrb); 2293de49bd5aSPadmanabh Ratnakar 2294de49bd5aSPadmanabh Ratnakar be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2295de49bd5aSPadmanabh Ratnakar OPCODE_COMMON_READ_OBJECT, 2296de49bd5aSPadmanabh Ratnakar sizeof(struct lancer_cmd_req_read_object), wrb, 2297de49bd5aSPadmanabh Ratnakar NULL); 2298de49bd5aSPadmanabh Ratnakar 2299de49bd5aSPadmanabh Ratnakar req->desired_read_len = cpu_to_le32(data_size); 2300de49bd5aSPadmanabh Ratnakar req->read_offset = cpu_to_le32(data_offset); 2301de49bd5aSPadmanabh Ratnakar strcpy(req->object_name, obj_name); 2302de49bd5aSPadmanabh Ratnakar req->descriptor_count = cpu_to_le32(1); 2303de49bd5aSPadmanabh Ratnakar req->buf_len = cpu_to_le32(data_size); 2304de49bd5aSPadmanabh Ratnakar req->addr_low = cpu_to_le32((cmd->dma & 0xFFFFFFFF)); 2305de49bd5aSPadmanabh Ratnakar req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma)); 2306de49bd5aSPadmanabh Ratnakar 2307de49bd5aSPadmanabh Ratnakar status = be_mcc_notify_wait(adapter); 2308de49bd5aSPadmanabh Ratnakar 2309de49bd5aSPadmanabh Ratnakar resp = embedded_payload(wrb); 2310de49bd5aSPadmanabh Ratnakar if (!status) { 2311de49bd5aSPadmanabh Ratnakar *data_read = le32_to_cpu(resp->actual_read_len); 2312de49bd5aSPadmanabh Ratnakar *eof = le32_to_cpu(resp->eof); 2313de49bd5aSPadmanabh Ratnakar } else { 2314de49bd5aSPadmanabh Ratnakar *addn_status = resp->additional_status; 2315de49bd5aSPadmanabh Ratnakar } 2316de49bd5aSPadmanabh Ratnakar 2317de49bd5aSPadmanabh Ratnakar err_unlock: 2318de49bd5aSPadmanabh Ratnakar spin_unlock_bh(&adapter->mcc_lock); 2319de49bd5aSPadmanabh Ratnakar return status; 2320de49bd5aSPadmanabh Ratnakar } 2321de49bd5aSPadmanabh Ratnakar 23229aebddd1SJeff Kirsher int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd, 23239aebddd1SJeff Kirsher u32 flash_type, u32 flash_opcode, u32 buf_size) 23249aebddd1SJeff Kirsher { 23259aebddd1SJeff Kirsher struct be_mcc_wrb *wrb; 23269aebddd1SJeff Kirsher struct be_cmd_write_flashrom *req; 23279aebddd1SJeff Kirsher int status; 23289aebddd1SJeff Kirsher 23299aebddd1SJeff Kirsher spin_lock_bh(&adapter->mcc_lock); 23309aebddd1SJeff Kirsher adapter->flash_status = 0; 23319aebddd1SJeff Kirsher 23329aebddd1SJeff Kirsher wrb = wrb_from_mccq(adapter); 23339aebddd1SJeff Kirsher if (!wrb) { 23349aebddd1SJeff Kirsher status = -EBUSY; 23359aebddd1SJeff Kirsher goto err_unlock; 23369aebddd1SJeff Kirsher } 23379aebddd1SJeff Kirsher req = cmd->va; 23389aebddd1SJeff Kirsher 2339106df1e3SSomnath Kotur be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2340a2cc4e0bSSathya Perla OPCODE_COMMON_WRITE_FLASHROM, cmd->size, wrb, 2341a2cc4e0bSSathya Perla cmd); 23429aebddd1SJeff Kirsher 23439aebddd1SJeff Kirsher req->params.op_type = cpu_to_le32(flash_type); 23449aebddd1SJeff Kirsher req->params.op_code = cpu_to_le32(flash_opcode); 23459aebddd1SJeff Kirsher req->params.data_buf_size = cpu_to_le32(buf_size); 23469aebddd1SJeff Kirsher 23479aebddd1SJeff Kirsher be_mcc_notify(adapter); 23489aebddd1SJeff Kirsher spin_unlock_bh(&adapter->mcc_lock); 23499aebddd1SJeff Kirsher 23505eeff635SSuresh Reddy if (!wait_for_completion_timeout(&adapter->et_cmd_compl, 2351e2edb7d5SSathya Perla msecs_to_jiffies(40000))) 2352fd45160cSKalesh AP status = -ETIMEDOUT; 23539aebddd1SJeff Kirsher else 23549aebddd1SJeff Kirsher status = adapter->flash_status; 23559aebddd1SJeff Kirsher 23569aebddd1SJeff Kirsher return status; 23579aebddd1SJeff Kirsher 23589aebddd1SJeff Kirsher err_unlock: 23599aebddd1SJeff Kirsher spin_unlock_bh(&adapter->mcc_lock); 23609aebddd1SJeff Kirsher return status; 23619aebddd1SJeff Kirsher } 23629aebddd1SJeff Kirsher 23639aebddd1SJeff Kirsher int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc, 236496c9b2e4SVasundhara Volam u16 optype, int offset) 23659aebddd1SJeff Kirsher { 23669aebddd1SJeff Kirsher struct be_mcc_wrb *wrb; 2367be716446SPadmanabh Ratnakar struct be_cmd_read_flash_crc *req; 23689aebddd1SJeff Kirsher int status; 23699aebddd1SJeff Kirsher 23709aebddd1SJeff Kirsher spin_lock_bh(&adapter->mcc_lock); 23719aebddd1SJeff Kirsher 23729aebddd1SJeff Kirsher wrb = wrb_from_mccq(adapter); 23739aebddd1SJeff Kirsher if (!wrb) { 23749aebddd1SJeff Kirsher status = -EBUSY; 23759aebddd1SJeff Kirsher goto err; 23769aebddd1SJeff Kirsher } 23779aebddd1SJeff Kirsher req = embedded_payload(wrb); 23789aebddd1SJeff Kirsher 2379106df1e3SSomnath Kotur be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2380be716446SPadmanabh Ratnakar OPCODE_COMMON_READ_FLASHROM, sizeof(*req), 2381be716446SPadmanabh Ratnakar wrb, NULL); 23829aebddd1SJeff Kirsher 238396c9b2e4SVasundhara Volam req->params.op_type = cpu_to_le32(optype); 23849aebddd1SJeff Kirsher req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT); 23859aebddd1SJeff Kirsher req->params.offset = cpu_to_le32(offset); 23869aebddd1SJeff Kirsher req->params.data_buf_size = cpu_to_le32(0x4); 23879aebddd1SJeff Kirsher 23889aebddd1SJeff Kirsher status = be_mcc_notify_wait(adapter); 23899aebddd1SJeff Kirsher if (!status) 2390be716446SPadmanabh Ratnakar memcpy(flashed_crc, req->crc, 4); 23919aebddd1SJeff Kirsher 23929aebddd1SJeff Kirsher err: 23939aebddd1SJeff Kirsher spin_unlock_bh(&adapter->mcc_lock); 23949aebddd1SJeff Kirsher return status; 23959aebddd1SJeff Kirsher } 23969aebddd1SJeff Kirsher 23979aebddd1SJeff Kirsher int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac, 23989aebddd1SJeff Kirsher struct be_dma_mem *nonemb_cmd) 23999aebddd1SJeff Kirsher { 24009aebddd1SJeff Kirsher struct be_mcc_wrb *wrb; 24019aebddd1SJeff Kirsher struct be_cmd_req_acpi_wol_magic_config *req; 24029aebddd1SJeff Kirsher int status; 24039aebddd1SJeff Kirsher 24049aebddd1SJeff Kirsher spin_lock_bh(&adapter->mcc_lock); 24059aebddd1SJeff Kirsher 24069aebddd1SJeff Kirsher wrb = wrb_from_mccq(adapter); 24079aebddd1SJeff Kirsher if (!wrb) { 24089aebddd1SJeff Kirsher status = -EBUSY; 24099aebddd1SJeff Kirsher goto err; 24109aebddd1SJeff Kirsher } 24119aebddd1SJeff Kirsher req = nonemb_cmd->va; 24129aebddd1SJeff Kirsher 2413106df1e3SSomnath Kotur be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, 2414a2cc4e0bSSathya Perla OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req), 2415a2cc4e0bSSathya Perla wrb, nonemb_cmd); 24169aebddd1SJeff Kirsher memcpy(req->magic_mac, mac, ETH_ALEN); 24179aebddd1SJeff Kirsher 24189aebddd1SJeff Kirsher status = be_mcc_notify_wait(adapter); 24199aebddd1SJeff Kirsher 24209aebddd1SJeff Kirsher err: 24219aebddd1SJeff Kirsher spin_unlock_bh(&adapter->mcc_lock); 24229aebddd1SJeff Kirsher return status; 24239aebddd1SJeff Kirsher } 24249aebddd1SJeff Kirsher 24259aebddd1SJeff Kirsher int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num, 24269aebddd1SJeff Kirsher u8 loopback_type, u8 enable) 24279aebddd1SJeff Kirsher { 24289aebddd1SJeff Kirsher struct be_mcc_wrb *wrb; 24299aebddd1SJeff Kirsher struct be_cmd_req_set_lmode *req; 24309aebddd1SJeff Kirsher int status; 24319aebddd1SJeff Kirsher 24329aebddd1SJeff Kirsher spin_lock_bh(&adapter->mcc_lock); 24339aebddd1SJeff Kirsher 24349aebddd1SJeff Kirsher wrb = wrb_from_mccq(adapter); 24359aebddd1SJeff Kirsher if (!wrb) { 24369aebddd1SJeff Kirsher status = -EBUSY; 24379aebddd1SJeff Kirsher goto err; 24389aebddd1SJeff Kirsher } 24399aebddd1SJeff Kirsher 24409aebddd1SJeff Kirsher req = embedded_payload(wrb); 24419aebddd1SJeff Kirsher 2442106df1e3SSomnath Kotur be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL, 2443a2cc4e0bSSathya Perla OPCODE_LOWLEVEL_SET_LOOPBACK_MODE, sizeof(*req), 2444a2cc4e0bSSathya Perla wrb, NULL); 24459aebddd1SJeff Kirsher 24469aebddd1SJeff Kirsher req->src_port = port_num; 24479aebddd1SJeff Kirsher req->dest_port = port_num; 24489aebddd1SJeff Kirsher req->loopback_type = loopback_type; 24499aebddd1SJeff Kirsher req->loopback_state = enable; 24509aebddd1SJeff Kirsher 24519aebddd1SJeff Kirsher status = be_mcc_notify_wait(adapter); 24529aebddd1SJeff Kirsher err: 24539aebddd1SJeff Kirsher spin_unlock_bh(&adapter->mcc_lock); 24549aebddd1SJeff Kirsher return status; 24559aebddd1SJeff Kirsher } 24569aebddd1SJeff Kirsher 24579aebddd1SJeff Kirsher int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num, 2458a2cc4e0bSSathya Perla u32 loopback_type, u32 pkt_size, u32 num_pkts, 2459a2cc4e0bSSathya Perla u64 pattern) 24609aebddd1SJeff Kirsher { 24619aebddd1SJeff Kirsher struct be_mcc_wrb *wrb; 24629aebddd1SJeff Kirsher struct be_cmd_req_loopback_test *req; 24635eeff635SSuresh Reddy struct be_cmd_resp_loopback_test *resp; 24649aebddd1SJeff Kirsher int status; 24659aebddd1SJeff Kirsher 24669aebddd1SJeff Kirsher spin_lock_bh(&adapter->mcc_lock); 24679aebddd1SJeff Kirsher 24689aebddd1SJeff Kirsher wrb = wrb_from_mccq(adapter); 24699aebddd1SJeff Kirsher if (!wrb) { 24709aebddd1SJeff Kirsher status = -EBUSY; 24719aebddd1SJeff Kirsher goto err; 24729aebddd1SJeff Kirsher } 24739aebddd1SJeff Kirsher 24749aebddd1SJeff Kirsher req = embedded_payload(wrb); 24759aebddd1SJeff Kirsher 2476106df1e3SSomnath Kotur be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL, 2477a2cc4e0bSSathya Perla OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req), wrb, 2478a2cc4e0bSSathya Perla NULL); 24799aebddd1SJeff Kirsher 24805eeff635SSuresh Reddy req->hdr.timeout = cpu_to_le32(15); 24819aebddd1SJeff Kirsher req->pattern = cpu_to_le64(pattern); 24829aebddd1SJeff Kirsher req->src_port = cpu_to_le32(port_num); 24839aebddd1SJeff Kirsher req->dest_port = cpu_to_le32(port_num); 24849aebddd1SJeff Kirsher req->pkt_size = cpu_to_le32(pkt_size); 24859aebddd1SJeff Kirsher req->num_pkts = cpu_to_le32(num_pkts); 24869aebddd1SJeff Kirsher req->loopback_type = cpu_to_le32(loopback_type); 24879aebddd1SJeff Kirsher 24885eeff635SSuresh Reddy be_mcc_notify(adapter); 24899aebddd1SJeff Kirsher 24905eeff635SSuresh Reddy spin_unlock_bh(&adapter->mcc_lock); 24915eeff635SSuresh Reddy 24925eeff635SSuresh Reddy wait_for_completion(&adapter->et_cmd_compl); 24935eeff635SSuresh Reddy resp = embedded_payload(wrb); 24945eeff635SSuresh Reddy status = le32_to_cpu(resp->status); 24955eeff635SSuresh Reddy 24965eeff635SSuresh Reddy return status; 24979aebddd1SJeff Kirsher err: 24989aebddd1SJeff Kirsher spin_unlock_bh(&adapter->mcc_lock); 24999aebddd1SJeff Kirsher return status; 25009aebddd1SJeff Kirsher } 25019aebddd1SJeff Kirsher 25029aebddd1SJeff Kirsher int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern, 25039aebddd1SJeff Kirsher u32 byte_cnt, struct be_dma_mem *cmd) 25049aebddd1SJeff Kirsher { 25059aebddd1SJeff Kirsher struct be_mcc_wrb *wrb; 25069aebddd1SJeff Kirsher struct be_cmd_req_ddrdma_test *req; 25079aebddd1SJeff Kirsher int status; 25089aebddd1SJeff Kirsher int i, j = 0; 25099aebddd1SJeff Kirsher 25109aebddd1SJeff Kirsher spin_lock_bh(&adapter->mcc_lock); 25119aebddd1SJeff Kirsher 25129aebddd1SJeff Kirsher wrb = wrb_from_mccq(adapter); 25139aebddd1SJeff Kirsher if (!wrb) { 25149aebddd1SJeff Kirsher status = -EBUSY; 25159aebddd1SJeff Kirsher goto err; 25169aebddd1SJeff Kirsher } 25179aebddd1SJeff Kirsher req = cmd->va; 2518106df1e3SSomnath Kotur be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL, 2519a2cc4e0bSSathya Perla OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size, wrb, 2520a2cc4e0bSSathya Perla cmd); 25219aebddd1SJeff Kirsher 25229aebddd1SJeff Kirsher req->pattern = cpu_to_le64(pattern); 25239aebddd1SJeff Kirsher req->byte_count = cpu_to_le32(byte_cnt); 25249aebddd1SJeff Kirsher for (i = 0; i < byte_cnt; i++) { 25259aebddd1SJeff Kirsher req->snd_buff[i] = (u8)(pattern >> (j*8)); 25269aebddd1SJeff Kirsher j++; 25279aebddd1SJeff Kirsher if (j > 7) 25289aebddd1SJeff Kirsher j = 0; 25299aebddd1SJeff Kirsher } 25309aebddd1SJeff Kirsher 25319aebddd1SJeff Kirsher status = be_mcc_notify_wait(adapter); 25329aebddd1SJeff Kirsher 25339aebddd1SJeff Kirsher if (!status) { 25349aebddd1SJeff Kirsher struct be_cmd_resp_ddrdma_test *resp; 25359aebddd1SJeff Kirsher resp = cmd->va; 25369aebddd1SJeff Kirsher if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) || 25379aebddd1SJeff Kirsher resp->snd_err) { 25389aebddd1SJeff Kirsher status = -1; 25399aebddd1SJeff Kirsher } 25409aebddd1SJeff Kirsher } 25419aebddd1SJeff Kirsher 25429aebddd1SJeff Kirsher err: 25439aebddd1SJeff Kirsher spin_unlock_bh(&adapter->mcc_lock); 25449aebddd1SJeff Kirsher return status; 25459aebddd1SJeff Kirsher } 25469aebddd1SJeff Kirsher 25479aebddd1SJeff Kirsher int be_cmd_get_seeprom_data(struct be_adapter *adapter, 25489aebddd1SJeff Kirsher struct be_dma_mem *nonemb_cmd) 25499aebddd1SJeff Kirsher { 25509aebddd1SJeff Kirsher struct be_mcc_wrb *wrb; 25519aebddd1SJeff Kirsher struct be_cmd_req_seeprom_read *req; 25529aebddd1SJeff Kirsher int status; 25539aebddd1SJeff Kirsher 25549aebddd1SJeff Kirsher spin_lock_bh(&adapter->mcc_lock); 25559aebddd1SJeff Kirsher 25569aebddd1SJeff Kirsher wrb = wrb_from_mccq(adapter); 25579aebddd1SJeff Kirsher if (!wrb) { 25589aebddd1SJeff Kirsher status = -EBUSY; 25599aebddd1SJeff Kirsher goto err; 25609aebddd1SJeff Kirsher } 25619aebddd1SJeff Kirsher req = nonemb_cmd->va; 25629aebddd1SJeff Kirsher 2563106df1e3SSomnath Kotur be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2564106df1e3SSomnath Kotur OPCODE_COMMON_SEEPROM_READ, sizeof(*req), wrb, 2565106df1e3SSomnath Kotur nonemb_cmd); 25669aebddd1SJeff Kirsher 25679aebddd1SJeff Kirsher status = be_mcc_notify_wait(adapter); 25689aebddd1SJeff Kirsher 25699aebddd1SJeff Kirsher err: 25709aebddd1SJeff Kirsher spin_unlock_bh(&adapter->mcc_lock); 25719aebddd1SJeff Kirsher return status; 25729aebddd1SJeff Kirsher } 25739aebddd1SJeff Kirsher 257442f11cf2SAjit Khaparde int be_cmd_get_phy_info(struct be_adapter *adapter) 25759aebddd1SJeff Kirsher { 25769aebddd1SJeff Kirsher struct be_mcc_wrb *wrb; 25779aebddd1SJeff Kirsher struct be_cmd_req_get_phy_info *req; 25789aebddd1SJeff Kirsher struct be_dma_mem cmd; 25799aebddd1SJeff Kirsher int status; 25809aebddd1SJeff Kirsher 2581f25b119cSPadmanabh Ratnakar if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_PHY_DETAILS, 2582f25b119cSPadmanabh Ratnakar CMD_SUBSYSTEM_COMMON)) 2583f25b119cSPadmanabh Ratnakar return -EPERM; 2584f25b119cSPadmanabh Ratnakar 25859aebddd1SJeff Kirsher spin_lock_bh(&adapter->mcc_lock); 25869aebddd1SJeff Kirsher 25879aebddd1SJeff Kirsher wrb = wrb_from_mccq(adapter); 25889aebddd1SJeff Kirsher if (!wrb) { 25899aebddd1SJeff Kirsher status = -EBUSY; 25909aebddd1SJeff Kirsher goto err; 25919aebddd1SJeff Kirsher } 25929aebddd1SJeff Kirsher cmd.size = sizeof(struct be_cmd_req_get_phy_info); 2593a2cc4e0bSSathya Perla cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma); 25949aebddd1SJeff Kirsher if (!cmd.va) { 25959aebddd1SJeff Kirsher dev_err(&adapter->pdev->dev, "Memory alloc failure\n"); 25969aebddd1SJeff Kirsher status = -ENOMEM; 25979aebddd1SJeff Kirsher goto err; 25989aebddd1SJeff Kirsher } 25999aebddd1SJeff Kirsher 26009aebddd1SJeff Kirsher req = cmd.va; 26019aebddd1SJeff Kirsher 2602106df1e3SSomnath Kotur be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2603106df1e3SSomnath Kotur OPCODE_COMMON_GET_PHY_DETAILS, sizeof(*req), 2604106df1e3SSomnath Kotur wrb, &cmd); 26059aebddd1SJeff Kirsher 26069aebddd1SJeff Kirsher status = be_mcc_notify_wait(adapter); 26079aebddd1SJeff Kirsher if (!status) { 26089aebddd1SJeff Kirsher struct be_phy_info *resp_phy_info = 26099aebddd1SJeff Kirsher cmd.va + sizeof(struct be_cmd_req_hdr); 261042f11cf2SAjit Khaparde adapter->phy.phy_type = le16_to_cpu(resp_phy_info->phy_type); 261142f11cf2SAjit Khaparde adapter->phy.interface_type = 26129aebddd1SJeff Kirsher le16_to_cpu(resp_phy_info->interface_type); 261342f11cf2SAjit Khaparde adapter->phy.auto_speeds_supported = 261442f11cf2SAjit Khaparde le16_to_cpu(resp_phy_info->auto_speeds_supported); 261542f11cf2SAjit Khaparde adapter->phy.fixed_speeds_supported = 261642f11cf2SAjit Khaparde le16_to_cpu(resp_phy_info->fixed_speeds_supported); 261742f11cf2SAjit Khaparde adapter->phy.misc_params = 261842f11cf2SAjit Khaparde le32_to_cpu(resp_phy_info->misc_params); 261968cb7e47SVasundhara Volam 262068cb7e47SVasundhara Volam if (BE2_chip(adapter)) { 262168cb7e47SVasundhara Volam adapter->phy.fixed_speeds_supported = 262268cb7e47SVasundhara Volam BE_SUPPORTED_SPEED_10GBPS | 262368cb7e47SVasundhara Volam BE_SUPPORTED_SPEED_1GBPS; 262468cb7e47SVasundhara Volam } 26259aebddd1SJeff Kirsher } 2626a2cc4e0bSSathya Perla pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma); 26279aebddd1SJeff Kirsher err: 26289aebddd1SJeff Kirsher spin_unlock_bh(&adapter->mcc_lock); 26299aebddd1SJeff Kirsher return status; 26309aebddd1SJeff Kirsher } 26319aebddd1SJeff Kirsher 26329aebddd1SJeff Kirsher int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain) 26339aebddd1SJeff Kirsher { 26349aebddd1SJeff Kirsher struct be_mcc_wrb *wrb; 26359aebddd1SJeff Kirsher struct be_cmd_req_set_qos *req; 26369aebddd1SJeff Kirsher int status; 26379aebddd1SJeff Kirsher 26389aebddd1SJeff Kirsher spin_lock_bh(&adapter->mcc_lock); 26399aebddd1SJeff Kirsher 26409aebddd1SJeff Kirsher wrb = wrb_from_mccq(adapter); 26419aebddd1SJeff Kirsher if (!wrb) { 26429aebddd1SJeff Kirsher status = -EBUSY; 26439aebddd1SJeff Kirsher goto err; 26449aebddd1SJeff Kirsher } 26459aebddd1SJeff Kirsher 26469aebddd1SJeff Kirsher req = embedded_payload(wrb); 26479aebddd1SJeff Kirsher 2648106df1e3SSomnath Kotur be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2649106df1e3SSomnath Kotur OPCODE_COMMON_SET_QOS, sizeof(*req), wrb, NULL); 26509aebddd1SJeff Kirsher 26519aebddd1SJeff Kirsher req->hdr.domain = domain; 26529aebddd1SJeff Kirsher req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC); 26539aebddd1SJeff Kirsher req->max_bps_nic = cpu_to_le32(bps); 26549aebddd1SJeff Kirsher 26559aebddd1SJeff Kirsher status = be_mcc_notify_wait(adapter); 26569aebddd1SJeff Kirsher 26579aebddd1SJeff Kirsher err: 26589aebddd1SJeff Kirsher spin_unlock_bh(&adapter->mcc_lock); 26599aebddd1SJeff Kirsher return status; 26609aebddd1SJeff Kirsher } 26619aebddd1SJeff Kirsher 26629aebddd1SJeff Kirsher int be_cmd_get_cntl_attributes(struct be_adapter *adapter) 26639aebddd1SJeff Kirsher { 26649aebddd1SJeff Kirsher struct be_mcc_wrb *wrb; 26659aebddd1SJeff Kirsher struct be_cmd_req_cntl_attribs *req; 26669aebddd1SJeff Kirsher struct be_cmd_resp_cntl_attribs *resp; 26679aebddd1SJeff Kirsher int status; 26689aebddd1SJeff Kirsher int payload_len = max(sizeof(*req), sizeof(*resp)); 26699aebddd1SJeff Kirsher struct mgmt_controller_attrib *attribs; 26709aebddd1SJeff Kirsher struct be_dma_mem attribs_cmd; 26719aebddd1SJeff Kirsher 2672d98ef50fSSuresh Reddy if (mutex_lock_interruptible(&adapter->mbox_lock)) 2673d98ef50fSSuresh Reddy return -1; 2674d98ef50fSSuresh Reddy 26759aebddd1SJeff Kirsher memset(&attribs_cmd, 0, sizeof(struct be_dma_mem)); 26769aebddd1SJeff Kirsher attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs); 26779aebddd1SJeff Kirsher attribs_cmd.va = pci_alloc_consistent(adapter->pdev, attribs_cmd.size, 26789aebddd1SJeff Kirsher &attribs_cmd.dma); 26799aebddd1SJeff Kirsher if (!attribs_cmd.va) { 2680a2cc4e0bSSathya Perla dev_err(&adapter->pdev->dev, "Memory allocation failure\n"); 2681d98ef50fSSuresh Reddy status = -ENOMEM; 2682d98ef50fSSuresh Reddy goto err; 26839aebddd1SJeff Kirsher } 26849aebddd1SJeff Kirsher 26859aebddd1SJeff Kirsher wrb = wrb_from_mbox(adapter); 26869aebddd1SJeff Kirsher if (!wrb) { 26879aebddd1SJeff Kirsher status = -EBUSY; 26889aebddd1SJeff Kirsher goto err; 26899aebddd1SJeff Kirsher } 26909aebddd1SJeff Kirsher req = attribs_cmd.va; 26919aebddd1SJeff Kirsher 2692106df1e3SSomnath Kotur be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2693a2cc4e0bSSathya Perla OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len, 2694a2cc4e0bSSathya Perla wrb, &attribs_cmd); 26959aebddd1SJeff Kirsher 26969aebddd1SJeff Kirsher status = be_mbox_notify_wait(adapter); 26979aebddd1SJeff Kirsher if (!status) { 26989aebddd1SJeff Kirsher attribs = attribs_cmd.va + sizeof(struct be_cmd_resp_hdr); 26999aebddd1SJeff Kirsher adapter->hba_port_num = attribs->hba_attribs.phy_port; 27009aebddd1SJeff Kirsher } 27019aebddd1SJeff Kirsher 27029aebddd1SJeff Kirsher err: 27039aebddd1SJeff Kirsher mutex_unlock(&adapter->mbox_lock); 2704d98ef50fSSuresh Reddy if (attribs_cmd.va) 2705d98ef50fSSuresh Reddy pci_free_consistent(adapter->pdev, attribs_cmd.size, 2706d98ef50fSSuresh Reddy attribs_cmd.va, attribs_cmd.dma); 27079aebddd1SJeff Kirsher return status; 27089aebddd1SJeff Kirsher } 27099aebddd1SJeff Kirsher 27109aebddd1SJeff Kirsher /* Uses mbox */ 27119aebddd1SJeff Kirsher int be_cmd_req_native_mode(struct be_adapter *adapter) 27129aebddd1SJeff Kirsher { 27139aebddd1SJeff Kirsher struct be_mcc_wrb *wrb; 27149aebddd1SJeff Kirsher struct be_cmd_req_set_func_cap *req; 27159aebddd1SJeff Kirsher int status; 27169aebddd1SJeff Kirsher 27179aebddd1SJeff Kirsher if (mutex_lock_interruptible(&adapter->mbox_lock)) 27189aebddd1SJeff Kirsher return -1; 27199aebddd1SJeff Kirsher 27209aebddd1SJeff Kirsher wrb = wrb_from_mbox(adapter); 27219aebddd1SJeff Kirsher if (!wrb) { 27229aebddd1SJeff Kirsher status = -EBUSY; 27239aebddd1SJeff Kirsher goto err; 27249aebddd1SJeff Kirsher } 27259aebddd1SJeff Kirsher 27269aebddd1SJeff Kirsher req = embedded_payload(wrb); 27279aebddd1SJeff Kirsher 2728106df1e3SSomnath Kotur be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2729a2cc4e0bSSathya Perla OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP, 2730a2cc4e0bSSathya Perla sizeof(*req), wrb, NULL); 27319aebddd1SJeff Kirsher 27329aebddd1SJeff Kirsher req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS | 27339aebddd1SJeff Kirsher CAPABILITY_BE3_NATIVE_ERX_API); 27349aebddd1SJeff Kirsher req->cap_flags = cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API); 27359aebddd1SJeff Kirsher 27369aebddd1SJeff Kirsher status = be_mbox_notify_wait(adapter); 27379aebddd1SJeff Kirsher if (!status) { 27389aebddd1SJeff Kirsher struct be_cmd_resp_set_func_cap *resp = embedded_payload(wrb); 27399aebddd1SJeff Kirsher adapter->be3_native = le32_to_cpu(resp->cap_flags) & 27409aebddd1SJeff Kirsher CAPABILITY_BE3_NATIVE_ERX_API; 2741d379142bSSathya Perla if (!adapter->be3_native) 2742d379142bSSathya Perla dev_warn(&adapter->pdev->dev, 2743d379142bSSathya Perla "adapter not in advanced mode\n"); 27449aebddd1SJeff Kirsher } 27459aebddd1SJeff Kirsher err: 27469aebddd1SJeff Kirsher mutex_unlock(&adapter->mbox_lock); 27479aebddd1SJeff Kirsher return status; 27489aebddd1SJeff Kirsher } 2749590c391dSPadmanabh Ratnakar 2750f25b119cSPadmanabh Ratnakar /* Get privilege(s) for a function */ 2751f25b119cSPadmanabh Ratnakar int be_cmd_get_fn_privileges(struct be_adapter *adapter, u32 *privilege, 2752f25b119cSPadmanabh Ratnakar u32 domain) 2753f25b119cSPadmanabh Ratnakar { 2754f25b119cSPadmanabh Ratnakar struct be_mcc_wrb *wrb; 2755f25b119cSPadmanabh Ratnakar struct be_cmd_req_get_fn_privileges *req; 2756f25b119cSPadmanabh Ratnakar int status; 2757f25b119cSPadmanabh Ratnakar 2758f25b119cSPadmanabh Ratnakar spin_lock_bh(&adapter->mcc_lock); 2759f25b119cSPadmanabh Ratnakar 2760f25b119cSPadmanabh Ratnakar wrb = wrb_from_mccq(adapter); 2761f25b119cSPadmanabh Ratnakar if (!wrb) { 2762f25b119cSPadmanabh Ratnakar status = -EBUSY; 2763f25b119cSPadmanabh Ratnakar goto err; 2764f25b119cSPadmanabh Ratnakar } 2765f25b119cSPadmanabh Ratnakar 2766f25b119cSPadmanabh Ratnakar req = embedded_payload(wrb); 2767f25b119cSPadmanabh Ratnakar 2768f25b119cSPadmanabh Ratnakar be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2769f25b119cSPadmanabh Ratnakar OPCODE_COMMON_GET_FN_PRIVILEGES, sizeof(*req), 2770f25b119cSPadmanabh Ratnakar wrb, NULL); 2771f25b119cSPadmanabh Ratnakar 2772f25b119cSPadmanabh Ratnakar req->hdr.domain = domain; 2773f25b119cSPadmanabh Ratnakar 2774f25b119cSPadmanabh Ratnakar status = be_mcc_notify_wait(adapter); 2775f25b119cSPadmanabh Ratnakar if (!status) { 2776f25b119cSPadmanabh Ratnakar struct be_cmd_resp_get_fn_privileges *resp = 2777f25b119cSPadmanabh Ratnakar embedded_payload(wrb); 2778f25b119cSPadmanabh Ratnakar *privilege = le32_to_cpu(resp->privilege_mask); 277902308d74SSuresh Reddy 278002308d74SSuresh Reddy /* In UMC mode FW does not return right privileges. 278102308d74SSuresh Reddy * Override with correct privilege equivalent to PF. 278202308d74SSuresh Reddy */ 278302308d74SSuresh Reddy if (BEx_chip(adapter) && be_is_mc(adapter) && 278402308d74SSuresh Reddy be_physfn(adapter)) 278502308d74SSuresh Reddy *privilege = MAX_PRIVILEGES; 2786f25b119cSPadmanabh Ratnakar } 2787f25b119cSPadmanabh Ratnakar 2788f25b119cSPadmanabh Ratnakar err: 2789f25b119cSPadmanabh Ratnakar spin_unlock_bh(&adapter->mcc_lock); 2790f25b119cSPadmanabh Ratnakar return status; 2791f25b119cSPadmanabh Ratnakar } 2792f25b119cSPadmanabh Ratnakar 279304a06028SSathya Perla /* Set privilege(s) for a function */ 279404a06028SSathya Perla int be_cmd_set_fn_privileges(struct be_adapter *adapter, u32 privileges, 279504a06028SSathya Perla u32 domain) 279604a06028SSathya Perla { 279704a06028SSathya Perla struct be_mcc_wrb *wrb; 279804a06028SSathya Perla struct be_cmd_req_set_fn_privileges *req; 279904a06028SSathya Perla int status; 280004a06028SSathya Perla 280104a06028SSathya Perla spin_lock_bh(&adapter->mcc_lock); 280204a06028SSathya Perla 280304a06028SSathya Perla wrb = wrb_from_mccq(adapter); 280404a06028SSathya Perla if (!wrb) { 280504a06028SSathya Perla status = -EBUSY; 280604a06028SSathya Perla goto err; 280704a06028SSathya Perla } 280804a06028SSathya Perla 280904a06028SSathya Perla req = embedded_payload(wrb); 281004a06028SSathya Perla be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 281104a06028SSathya Perla OPCODE_COMMON_SET_FN_PRIVILEGES, sizeof(*req), 281204a06028SSathya Perla wrb, NULL); 281304a06028SSathya Perla req->hdr.domain = domain; 281404a06028SSathya Perla if (lancer_chip(adapter)) 281504a06028SSathya Perla req->privileges_lancer = cpu_to_le32(privileges); 281604a06028SSathya Perla else 281704a06028SSathya Perla req->privileges = cpu_to_le32(privileges); 281804a06028SSathya Perla 281904a06028SSathya Perla status = be_mcc_notify_wait(adapter); 282004a06028SSathya Perla err: 282104a06028SSathya Perla spin_unlock_bh(&adapter->mcc_lock); 282204a06028SSathya Perla return status; 282304a06028SSathya Perla } 282404a06028SSathya Perla 28255a712c13SSathya Perla /* pmac_id_valid: true => pmac_id is supplied and MAC address is requested. 28265a712c13SSathya Perla * pmac_id_valid: false => pmac_id or MAC address is requested. 28275a712c13SSathya Perla * If pmac_id is returned, pmac_id_valid is returned as true 28285a712c13SSathya Perla */ 28291578e777SPadmanabh Ratnakar int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac, 2830b188f090SSuresh Reddy bool *pmac_id_valid, u32 *pmac_id, u32 if_handle, 2831b188f090SSuresh Reddy u8 domain) 2832590c391dSPadmanabh Ratnakar { 2833590c391dSPadmanabh Ratnakar struct be_mcc_wrb *wrb; 2834590c391dSPadmanabh Ratnakar struct be_cmd_req_get_mac_list *req; 2835590c391dSPadmanabh Ratnakar int status; 2836590c391dSPadmanabh Ratnakar int mac_count; 2837e5e1ee89SPadmanabh Ratnakar struct be_dma_mem get_mac_list_cmd; 2838e5e1ee89SPadmanabh Ratnakar int i; 2839e5e1ee89SPadmanabh Ratnakar 2840e5e1ee89SPadmanabh Ratnakar memset(&get_mac_list_cmd, 0, sizeof(struct be_dma_mem)); 2841e5e1ee89SPadmanabh Ratnakar get_mac_list_cmd.size = sizeof(struct be_cmd_resp_get_mac_list); 2842e5e1ee89SPadmanabh Ratnakar get_mac_list_cmd.va = pci_alloc_consistent(adapter->pdev, 2843e5e1ee89SPadmanabh Ratnakar get_mac_list_cmd.size, 2844e5e1ee89SPadmanabh Ratnakar &get_mac_list_cmd.dma); 2845e5e1ee89SPadmanabh Ratnakar 2846e5e1ee89SPadmanabh Ratnakar if (!get_mac_list_cmd.va) { 2847e5e1ee89SPadmanabh Ratnakar dev_err(&adapter->pdev->dev, 2848e5e1ee89SPadmanabh Ratnakar "Memory allocation failure during GET_MAC_LIST\n"); 2849e5e1ee89SPadmanabh Ratnakar return -ENOMEM; 2850e5e1ee89SPadmanabh Ratnakar } 2851590c391dSPadmanabh Ratnakar 2852590c391dSPadmanabh Ratnakar spin_lock_bh(&adapter->mcc_lock); 2853590c391dSPadmanabh Ratnakar 2854590c391dSPadmanabh Ratnakar wrb = wrb_from_mccq(adapter); 2855590c391dSPadmanabh Ratnakar if (!wrb) { 2856590c391dSPadmanabh Ratnakar status = -EBUSY; 2857e5e1ee89SPadmanabh Ratnakar goto out; 2858590c391dSPadmanabh Ratnakar } 2859e5e1ee89SPadmanabh Ratnakar 2860e5e1ee89SPadmanabh Ratnakar req = get_mac_list_cmd.va; 2861590c391dSPadmanabh Ratnakar 2862590c391dSPadmanabh Ratnakar be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2863bf591f51SSathya Perla OPCODE_COMMON_GET_MAC_LIST, 2864bf591f51SSathya Perla get_mac_list_cmd.size, wrb, &get_mac_list_cmd); 2865590c391dSPadmanabh Ratnakar req->hdr.domain = domain; 2866e5e1ee89SPadmanabh Ratnakar req->mac_type = MAC_ADDRESS_TYPE_NETWORK; 28675a712c13SSathya Perla if (*pmac_id_valid) { 28685a712c13SSathya Perla req->mac_id = cpu_to_le32(*pmac_id); 2869b188f090SSuresh Reddy req->iface_id = cpu_to_le16(if_handle); 28705a712c13SSathya Perla req->perm_override = 0; 28715a712c13SSathya Perla } else { 2872e5e1ee89SPadmanabh Ratnakar req->perm_override = 1; 28735a712c13SSathya Perla } 2874590c391dSPadmanabh Ratnakar 2875590c391dSPadmanabh Ratnakar status = be_mcc_notify_wait(adapter); 2876590c391dSPadmanabh Ratnakar if (!status) { 2877590c391dSPadmanabh Ratnakar struct be_cmd_resp_get_mac_list *resp = 2878e5e1ee89SPadmanabh Ratnakar get_mac_list_cmd.va; 28795a712c13SSathya Perla 28805a712c13SSathya Perla if (*pmac_id_valid) { 28815a712c13SSathya Perla memcpy(mac, resp->macid_macaddr.mac_addr_id.macaddr, 28825a712c13SSathya Perla ETH_ALEN); 28835a712c13SSathya Perla goto out; 28845a712c13SSathya Perla } 28855a712c13SSathya Perla 2886e5e1ee89SPadmanabh Ratnakar mac_count = resp->true_mac_count + resp->pseudo_mac_count; 2887e5e1ee89SPadmanabh Ratnakar /* Mac list returned could contain one or more active mac_ids 28881578e777SPadmanabh Ratnakar * or one or more true or pseudo permanant mac addresses. 28891578e777SPadmanabh Ratnakar * If an active mac_id is present, return first active mac_id 28901578e777SPadmanabh Ratnakar * found. 2891e5e1ee89SPadmanabh Ratnakar */ 2892590c391dSPadmanabh Ratnakar for (i = 0; i < mac_count; i++) { 2893e5e1ee89SPadmanabh Ratnakar struct get_list_macaddr *mac_entry; 2894e5e1ee89SPadmanabh Ratnakar u16 mac_addr_size; 2895e5e1ee89SPadmanabh Ratnakar u32 mac_id; 2896e5e1ee89SPadmanabh Ratnakar 2897e5e1ee89SPadmanabh Ratnakar mac_entry = &resp->macaddr_list[i]; 2898e5e1ee89SPadmanabh Ratnakar mac_addr_size = le16_to_cpu(mac_entry->mac_addr_size); 2899e5e1ee89SPadmanabh Ratnakar /* mac_id is a 32 bit value and mac_addr size 2900e5e1ee89SPadmanabh Ratnakar * is 6 bytes 2901e5e1ee89SPadmanabh Ratnakar */ 2902e5e1ee89SPadmanabh Ratnakar if (mac_addr_size == sizeof(u32)) { 29035a712c13SSathya Perla *pmac_id_valid = true; 2904e5e1ee89SPadmanabh Ratnakar mac_id = mac_entry->mac_addr_id.s_mac_id.mac_id; 2905e5e1ee89SPadmanabh Ratnakar *pmac_id = le32_to_cpu(mac_id); 2906e5e1ee89SPadmanabh Ratnakar goto out; 2907590c391dSPadmanabh Ratnakar } 2908590c391dSPadmanabh Ratnakar } 29091578e777SPadmanabh Ratnakar /* If no active mac_id found, return first mac addr */ 29105a712c13SSathya Perla *pmac_id_valid = false; 2911e5e1ee89SPadmanabh Ratnakar memcpy(mac, resp->macaddr_list[0].mac_addr_id.macaddr, 2912e5e1ee89SPadmanabh Ratnakar ETH_ALEN); 2913590c391dSPadmanabh Ratnakar } 2914590c391dSPadmanabh Ratnakar 2915e5e1ee89SPadmanabh Ratnakar out: 2916590c391dSPadmanabh Ratnakar spin_unlock_bh(&adapter->mcc_lock); 2917e5e1ee89SPadmanabh Ratnakar pci_free_consistent(adapter->pdev, get_mac_list_cmd.size, 2918e5e1ee89SPadmanabh Ratnakar get_mac_list_cmd.va, get_mac_list_cmd.dma); 2919590c391dSPadmanabh Ratnakar return status; 2920590c391dSPadmanabh Ratnakar } 2921590c391dSPadmanabh Ratnakar 2922a2cc4e0bSSathya Perla int be_cmd_get_active_mac(struct be_adapter *adapter, u32 curr_pmac_id, 2923a2cc4e0bSSathya Perla u8 *mac, u32 if_handle, bool active, u32 domain) 29245a712c13SSathya Perla { 29255a712c13SSathya Perla 2926b188f090SSuresh Reddy if (!active) 2927b188f090SSuresh Reddy be_cmd_get_mac_from_list(adapter, mac, &active, &curr_pmac_id, 2928b188f090SSuresh Reddy if_handle, domain); 29293175d8c2SSathya Perla if (BEx_chip(adapter)) 29305a712c13SSathya Perla return be_cmd_mac_addr_query(adapter, mac, false, 2931b188f090SSuresh Reddy if_handle, curr_pmac_id); 29323175d8c2SSathya Perla else 29333175d8c2SSathya Perla /* Fetch the MAC address using pmac_id */ 29343175d8c2SSathya Perla return be_cmd_get_mac_from_list(adapter, mac, &active, 2935b188f090SSuresh Reddy &curr_pmac_id, 2936b188f090SSuresh Reddy if_handle, domain); 29375a712c13SSathya Perla } 29385a712c13SSathya Perla 293995046b92SSathya Perla int be_cmd_get_perm_mac(struct be_adapter *adapter, u8 *mac) 294095046b92SSathya Perla { 294195046b92SSathya Perla int status; 294295046b92SSathya Perla bool pmac_valid = false; 294395046b92SSathya Perla 294495046b92SSathya Perla memset(mac, 0, ETH_ALEN); 294595046b92SSathya Perla 29463175d8c2SSathya Perla if (BEx_chip(adapter)) { 29473175d8c2SSathya Perla if (be_physfn(adapter)) 29483175d8c2SSathya Perla status = be_cmd_mac_addr_query(adapter, mac, true, 0, 29493175d8c2SSathya Perla 0); 295095046b92SSathya Perla else 295195046b92SSathya Perla status = be_cmd_mac_addr_query(adapter, mac, false, 295295046b92SSathya Perla adapter->if_handle, 0); 29533175d8c2SSathya Perla } else { 29543175d8c2SSathya Perla status = be_cmd_get_mac_from_list(adapter, mac, &pmac_valid, 2955b188f090SSuresh Reddy NULL, adapter->if_handle, 0); 29563175d8c2SSathya Perla } 29573175d8c2SSathya Perla 295895046b92SSathya Perla return status; 295995046b92SSathya Perla } 296095046b92SSathya Perla 2961590c391dSPadmanabh Ratnakar /* Uses synchronous MCCQ */ 2962590c391dSPadmanabh Ratnakar int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array, 2963590c391dSPadmanabh Ratnakar u8 mac_count, u32 domain) 2964590c391dSPadmanabh Ratnakar { 2965590c391dSPadmanabh Ratnakar struct be_mcc_wrb *wrb; 2966590c391dSPadmanabh Ratnakar struct be_cmd_req_set_mac_list *req; 2967590c391dSPadmanabh Ratnakar int status; 2968590c391dSPadmanabh Ratnakar struct be_dma_mem cmd; 2969590c391dSPadmanabh Ratnakar 2970590c391dSPadmanabh Ratnakar memset(&cmd, 0, sizeof(struct be_dma_mem)); 2971590c391dSPadmanabh Ratnakar cmd.size = sizeof(struct be_cmd_req_set_mac_list); 2972590c391dSPadmanabh Ratnakar cmd.va = dma_alloc_coherent(&adapter->pdev->dev, cmd.size, 2973590c391dSPadmanabh Ratnakar &cmd.dma, GFP_KERNEL); 2974d0320f75SJoe Perches if (!cmd.va) 2975590c391dSPadmanabh Ratnakar return -ENOMEM; 2976590c391dSPadmanabh Ratnakar 2977590c391dSPadmanabh Ratnakar spin_lock_bh(&adapter->mcc_lock); 2978590c391dSPadmanabh Ratnakar 2979590c391dSPadmanabh Ratnakar wrb = wrb_from_mccq(adapter); 2980590c391dSPadmanabh Ratnakar if (!wrb) { 2981590c391dSPadmanabh Ratnakar status = -EBUSY; 2982590c391dSPadmanabh Ratnakar goto err; 2983590c391dSPadmanabh Ratnakar } 2984590c391dSPadmanabh Ratnakar 2985590c391dSPadmanabh Ratnakar req = cmd.va; 2986590c391dSPadmanabh Ratnakar be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2987590c391dSPadmanabh Ratnakar OPCODE_COMMON_SET_MAC_LIST, sizeof(*req), 2988590c391dSPadmanabh Ratnakar wrb, &cmd); 2989590c391dSPadmanabh Ratnakar 2990590c391dSPadmanabh Ratnakar req->hdr.domain = domain; 2991590c391dSPadmanabh Ratnakar req->mac_count = mac_count; 2992590c391dSPadmanabh Ratnakar if (mac_count) 2993590c391dSPadmanabh Ratnakar memcpy(req->mac, mac_array, ETH_ALEN*mac_count); 2994590c391dSPadmanabh Ratnakar 2995590c391dSPadmanabh Ratnakar status = be_mcc_notify_wait(adapter); 2996590c391dSPadmanabh Ratnakar 2997590c391dSPadmanabh Ratnakar err: 2998a2cc4e0bSSathya Perla dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, cmd.dma); 2999590c391dSPadmanabh Ratnakar spin_unlock_bh(&adapter->mcc_lock); 3000590c391dSPadmanabh Ratnakar return status; 3001590c391dSPadmanabh Ratnakar } 30024762f6ceSAjit Khaparde 30033175d8c2SSathya Perla /* Wrapper to delete any active MACs and provision the new mac. 30043175d8c2SSathya Perla * Changes to MAC_LIST are allowed iff none of the MAC addresses in the 30053175d8c2SSathya Perla * current list are active. 30063175d8c2SSathya Perla */ 30073175d8c2SSathya Perla int be_cmd_set_mac(struct be_adapter *adapter, u8 *mac, int if_id, u32 dom) 30083175d8c2SSathya Perla { 30093175d8c2SSathya Perla bool active_mac = false; 30103175d8c2SSathya Perla u8 old_mac[ETH_ALEN]; 30113175d8c2SSathya Perla u32 pmac_id; 30123175d8c2SSathya Perla int status; 30133175d8c2SSathya Perla 30143175d8c2SSathya Perla status = be_cmd_get_mac_from_list(adapter, old_mac, &active_mac, 3015b188f090SSuresh Reddy &pmac_id, if_id, dom); 3016b188f090SSuresh Reddy 30173175d8c2SSathya Perla if (!status && active_mac) 30183175d8c2SSathya Perla be_cmd_pmac_del(adapter, if_id, pmac_id, dom); 30193175d8c2SSathya Perla 30203175d8c2SSathya Perla return be_cmd_set_mac_list(adapter, mac, mac ? 1 : 0, dom); 30213175d8c2SSathya Perla } 30223175d8c2SSathya Perla 3023f1f3ee1bSAjit Khaparde int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid, 3024a77dcb8cSAjit Khaparde u32 domain, u16 intf_id, u16 hsw_mode) 3025f1f3ee1bSAjit Khaparde { 3026f1f3ee1bSAjit Khaparde struct be_mcc_wrb *wrb; 3027f1f3ee1bSAjit Khaparde struct be_cmd_req_set_hsw_config *req; 3028f1f3ee1bSAjit Khaparde void *ctxt; 3029f1f3ee1bSAjit Khaparde int status; 3030f1f3ee1bSAjit Khaparde 3031f1f3ee1bSAjit Khaparde spin_lock_bh(&adapter->mcc_lock); 3032f1f3ee1bSAjit Khaparde 3033f1f3ee1bSAjit Khaparde wrb = wrb_from_mccq(adapter); 3034f1f3ee1bSAjit Khaparde if (!wrb) { 3035f1f3ee1bSAjit Khaparde status = -EBUSY; 3036f1f3ee1bSAjit Khaparde goto err; 3037f1f3ee1bSAjit Khaparde } 3038f1f3ee1bSAjit Khaparde 3039f1f3ee1bSAjit Khaparde req = embedded_payload(wrb); 3040f1f3ee1bSAjit Khaparde ctxt = &req->context; 3041f1f3ee1bSAjit Khaparde 3042f1f3ee1bSAjit Khaparde be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 3043a2cc4e0bSSathya Perla OPCODE_COMMON_SET_HSW_CONFIG, sizeof(*req), wrb, 3044a2cc4e0bSSathya Perla NULL); 3045f1f3ee1bSAjit Khaparde 3046f1f3ee1bSAjit Khaparde req->hdr.domain = domain; 3047f1f3ee1bSAjit Khaparde AMAP_SET_BITS(struct amap_set_hsw_context, interface_id, ctxt, intf_id); 3048f1f3ee1bSAjit Khaparde if (pvid) { 3049f1f3ee1bSAjit Khaparde AMAP_SET_BITS(struct amap_set_hsw_context, pvid_valid, ctxt, 1); 3050f1f3ee1bSAjit Khaparde AMAP_SET_BITS(struct amap_set_hsw_context, pvid, ctxt, pvid); 3051f1f3ee1bSAjit Khaparde } 3052a77dcb8cSAjit Khaparde if (!BEx_chip(adapter) && hsw_mode) { 3053a77dcb8cSAjit Khaparde AMAP_SET_BITS(struct amap_set_hsw_context, interface_id, 3054a77dcb8cSAjit Khaparde ctxt, adapter->hba_port_num); 3055a77dcb8cSAjit Khaparde AMAP_SET_BITS(struct amap_set_hsw_context, pport, ctxt, 1); 3056a77dcb8cSAjit Khaparde AMAP_SET_BITS(struct amap_set_hsw_context, port_fwd_type, 3057a77dcb8cSAjit Khaparde ctxt, hsw_mode); 3058a77dcb8cSAjit Khaparde } 3059f1f3ee1bSAjit Khaparde 3060f1f3ee1bSAjit Khaparde be_dws_cpu_to_le(req->context, sizeof(req->context)); 3061f1f3ee1bSAjit Khaparde status = be_mcc_notify_wait(adapter); 3062f1f3ee1bSAjit Khaparde 3063f1f3ee1bSAjit Khaparde err: 3064f1f3ee1bSAjit Khaparde spin_unlock_bh(&adapter->mcc_lock); 3065f1f3ee1bSAjit Khaparde return status; 3066f1f3ee1bSAjit Khaparde } 3067f1f3ee1bSAjit Khaparde 3068f1f3ee1bSAjit Khaparde /* Get Hyper switch config */ 3069f1f3ee1bSAjit Khaparde int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid, 3070a77dcb8cSAjit Khaparde u32 domain, u16 intf_id, u8 *mode) 3071f1f3ee1bSAjit Khaparde { 3072f1f3ee1bSAjit Khaparde struct be_mcc_wrb *wrb; 3073f1f3ee1bSAjit Khaparde struct be_cmd_req_get_hsw_config *req; 3074f1f3ee1bSAjit Khaparde void *ctxt; 3075f1f3ee1bSAjit Khaparde int status; 3076f1f3ee1bSAjit Khaparde u16 vid; 3077f1f3ee1bSAjit Khaparde 3078f1f3ee1bSAjit Khaparde spin_lock_bh(&adapter->mcc_lock); 3079f1f3ee1bSAjit Khaparde 3080f1f3ee1bSAjit Khaparde wrb = wrb_from_mccq(adapter); 3081f1f3ee1bSAjit Khaparde if (!wrb) { 3082f1f3ee1bSAjit Khaparde status = -EBUSY; 3083f1f3ee1bSAjit Khaparde goto err; 3084f1f3ee1bSAjit Khaparde } 3085f1f3ee1bSAjit Khaparde 3086f1f3ee1bSAjit Khaparde req = embedded_payload(wrb); 3087f1f3ee1bSAjit Khaparde ctxt = &req->context; 3088f1f3ee1bSAjit Khaparde 3089f1f3ee1bSAjit Khaparde be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 3090a2cc4e0bSSathya Perla OPCODE_COMMON_GET_HSW_CONFIG, sizeof(*req), wrb, 3091a2cc4e0bSSathya Perla NULL); 3092f1f3ee1bSAjit Khaparde 3093f1f3ee1bSAjit Khaparde req->hdr.domain = domain; 3094a77dcb8cSAjit Khaparde AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id, 3095a77dcb8cSAjit Khaparde ctxt, intf_id); 3096f1f3ee1bSAjit Khaparde AMAP_SET_BITS(struct amap_get_hsw_req_context, pvid_valid, ctxt, 1); 3097a77dcb8cSAjit Khaparde 30982c07c1d7SVasundhara Volam if (!BEx_chip(adapter) && mode) { 3099a77dcb8cSAjit Khaparde AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id, 3100a77dcb8cSAjit Khaparde ctxt, adapter->hba_port_num); 3101a77dcb8cSAjit Khaparde AMAP_SET_BITS(struct amap_get_hsw_req_context, pport, ctxt, 1); 3102a77dcb8cSAjit Khaparde } 3103f1f3ee1bSAjit Khaparde be_dws_cpu_to_le(req->context, sizeof(req->context)); 3104f1f3ee1bSAjit Khaparde 3105f1f3ee1bSAjit Khaparde status = be_mcc_notify_wait(adapter); 3106f1f3ee1bSAjit Khaparde if (!status) { 3107f1f3ee1bSAjit Khaparde struct be_cmd_resp_get_hsw_config *resp = 3108f1f3ee1bSAjit Khaparde embedded_payload(wrb); 3109a2cc4e0bSSathya Perla be_dws_le_to_cpu(&resp->context, sizeof(resp->context)); 3110f1f3ee1bSAjit Khaparde vid = AMAP_GET_BITS(struct amap_get_hsw_resp_context, 3111f1f3ee1bSAjit Khaparde pvid, &resp->context); 3112a77dcb8cSAjit Khaparde if (pvid) 3113f1f3ee1bSAjit Khaparde *pvid = le16_to_cpu(vid); 3114a77dcb8cSAjit Khaparde if (mode) 3115a77dcb8cSAjit Khaparde *mode = AMAP_GET_BITS(struct amap_get_hsw_resp_context, 3116a77dcb8cSAjit Khaparde port_fwd_type, &resp->context); 3117f1f3ee1bSAjit Khaparde } 3118f1f3ee1bSAjit Khaparde 3119f1f3ee1bSAjit Khaparde err: 3120f1f3ee1bSAjit Khaparde spin_unlock_bh(&adapter->mcc_lock); 3121f1f3ee1bSAjit Khaparde return status; 3122f1f3ee1bSAjit Khaparde } 3123f1f3ee1bSAjit Khaparde 31244762f6ceSAjit Khaparde int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter) 31254762f6ceSAjit Khaparde { 31264762f6ceSAjit Khaparde struct be_mcc_wrb *wrb; 31274762f6ceSAjit Khaparde struct be_cmd_req_acpi_wol_magic_config_v1 *req; 312876a9e08eSSuresh Reddy int status = 0; 31294762f6ceSAjit Khaparde struct be_dma_mem cmd; 31304762f6ceSAjit Khaparde 3131f25b119cSPadmanabh Ratnakar if (!be_cmd_allowed(adapter, OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, 3132f25b119cSPadmanabh Ratnakar CMD_SUBSYSTEM_ETH)) 3133f25b119cSPadmanabh Ratnakar return -EPERM; 3134f25b119cSPadmanabh Ratnakar 313576a9e08eSSuresh Reddy if (be_is_wol_excluded(adapter)) 313676a9e08eSSuresh Reddy return status; 313776a9e08eSSuresh Reddy 3138d98ef50fSSuresh Reddy if (mutex_lock_interruptible(&adapter->mbox_lock)) 3139d98ef50fSSuresh Reddy return -1; 3140d98ef50fSSuresh Reddy 31414762f6ceSAjit Khaparde memset(&cmd, 0, sizeof(struct be_dma_mem)); 31424762f6ceSAjit Khaparde cmd.size = sizeof(struct be_cmd_resp_acpi_wol_magic_config_v1); 3143a2cc4e0bSSathya Perla cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma); 31444762f6ceSAjit Khaparde if (!cmd.va) { 3145a2cc4e0bSSathya Perla dev_err(&adapter->pdev->dev, "Memory allocation failure\n"); 3146d98ef50fSSuresh Reddy status = -ENOMEM; 3147d98ef50fSSuresh Reddy goto err; 31484762f6ceSAjit Khaparde } 31494762f6ceSAjit Khaparde 31504762f6ceSAjit Khaparde wrb = wrb_from_mbox(adapter); 31514762f6ceSAjit Khaparde if (!wrb) { 31524762f6ceSAjit Khaparde status = -EBUSY; 31534762f6ceSAjit Khaparde goto err; 31544762f6ceSAjit Khaparde } 31554762f6ceSAjit Khaparde 31564762f6ceSAjit Khaparde req = cmd.va; 31574762f6ceSAjit Khaparde 31584762f6ceSAjit Khaparde be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, 31594762f6ceSAjit Khaparde OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, 316076a9e08eSSuresh Reddy sizeof(*req), wrb, &cmd); 31614762f6ceSAjit Khaparde 31624762f6ceSAjit Khaparde req->hdr.version = 1; 31634762f6ceSAjit Khaparde req->query_options = BE_GET_WOL_CAP; 31644762f6ceSAjit Khaparde 31654762f6ceSAjit Khaparde status = be_mbox_notify_wait(adapter); 31664762f6ceSAjit Khaparde if (!status) { 31674762f6ceSAjit Khaparde struct be_cmd_resp_acpi_wol_magic_config_v1 *resp; 31684762f6ceSAjit Khaparde resp = (struct be_cmd_resp_acpi_wol_magic_config_v1 *) cmd.va; 31694762f6ceSAjit Khaparde 31704762f6ceSAjit Khaparde adapter->wol_cap = resp->wol_settings; 317176a9e08eSSuresh Reddy if (adapter->wol_cap & BE_WOL_CAP) 317276a9e08eSSuresh Reddy adapter->wol_en = true; 31734762f6ceSAjit Khaparde } 31744762f6ceSAjit Khaparde err: 31754762f6ceSAjit Khaparde mutex_unlock(&adapter->mbox_lock); 3176d98ef50fSSuresh Reddy if (cmd.va) 31774762f6ceSAjit Khaparde pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma); 31784762f6ceSAjit Khaparde return status; 3179941a77d5SSomnath Kotur 3180941a77d5SSomnath Kotur } 3181baaa08d1SVasundhara Volam 3182baaa08d1SVasundhara Volam int be_cmd_set_fw_log_level(struct be_adapter *adapter, u32 level) 3183baaa08d1SVasundhara Volam { 3184baaa08d1SVasundhara Volam struct be_dma_mem extfat_cmd; 3185baaa08d1SVasundhara Volam struct be_fat_conf_params *cfgs; 3186baaa08d1SVasundhara Volam int status; 3187baaa08d1SVasundhara Volam int i, j; 3188baaa08d1SVasundhara Volam 3189baaa08d1SVasundhara Volam memset(&extfat_cmd, 0, sizeof(struct be_dma_mem)); 3190baaa08d1SVasundhara Volam extfat_cmd.size = sizeof(struct be_cmd_resp_get_ext_fat_caps); 3191baaa08d1SVasundhara Volam extfat_cmd.va = pci_alloc_consistent(adapter->pdev, extfat_cmd.size, 3192baaa08d1SVasundhara Volam &extfat_cmd.dma); 3193baaa08d1SVasundhara Volam if (!extfat_cmd.va) 3194baaa08d1SVasundhara Volam return -ENOMEM; 3195baaa08d1SVasundhara Volam 3196baaa08d1SVasundhara Volam status = be_cmd_get_ext_fat_capabilites(adapter, &extfat_cmd); 3197baaa08d1SVasundhara Volam if (status) 3198baaa08d1SVasundhara Volam goto err; 3199baaa08d1SVasundhara Volam 3200baaa08d1SVasundhara Volam cfgs = (struct be_fat_conf_params *) 3201baaa08d1SVasundhara Volam (extfat_cmd.va + sizeof(struct be_cmd_resp_hdr)); 3202baaa08d1SVasundhara Volam for (i = 0; i < le32_to_cpu(cfgs->num_modules); i++) { 3203baaa08d1SVasundhara Volam u32 num_modes = le32_to_cpu(cfgs->module[i].num_modes); 3204baaa08d1SVasundhara Volam for (j = 0; j < num_modes; j++) { 3205baaa08d1SVasundhara Volam if (cfgs->module[i].trace_lvl[j].mode == MODE_UART) 3206baaa08d1SVasundhara Volam cfgs->module[i].trace_lvl[j].dbg_lvl = 3207baaa08d1SVasundhara Volam cpu_to_le32(level); 3208baaa08d1SVasundhara Volam } 3209baaa08d1SVasundhara Volam } 3210baaa08d1SVasundhara Volam 3211baaa08d1SVasundhara Volam status = be_cmd_set_ext_fat_capabilites(adapter, &extfat_cmd, cfgs); 3212baaa08d1SVasundhara Volam err: 3213baaa08d1SVasundhara Volam pci_free_consistent(adapter->pdev, extfat_cmd.size, extfat_cmd.va, 3214baaa08d1SVasundhara Volam extfat_cmd.dma); 3215baaa08d1SVasundhara Volam return status; 3216baaa08d1SVasundhara Volam } 3217baaa08d1SVasundhara Volam 3218baaa08d1SVasundhara Volam int be_cmd_get_fw_log_level(struct be_adapter *adapter) 3219baaa08d1SVasundhara Volam { 3220baaa08d1SVasundhara Volam struct be_dma_mem extfat_cmd; 3221baaa08d1SVasundhara Volam struct be_fat_conf_params *cfgs; 3222baaa08d1SVasundhara Volam int status, j; 3223baaa08d1SVasundhara Volam int level = 0; 3224baaa08d1SVasundhara Volam 3225baaa08d1SVasundhara Volam memset(&extfat_cmd, 0, sizeof(struct be_dma_mem)); 3226baaa08d1SVasundhara Volam extfat_cmd.size = sizeof(struct be_cmd_resp_get_ext_fat_caps); 3227baaa08d1SVasundhara Volam extfat_cmd.va = pci_alloc_consistent(adapter->pdev, extfat_cmd.size, 3228baaa08d1SVasundhara Volam &extfat_cmd.dma); 3229baaa08d1SVasundhara Volam 3230baaa08d1SVasundhara Volam if (!extfat_cmd.va) { 3231baaa08d1SVasundhara Volam dev_err(&adapter->pdev->dev, "%s: Memory allocation failure\n", 3232baaa08d1SVasundhara Volam __func__); 3233baaa08d1SVasundhara Volam goto err; 3234baaa08d1SVasundhara Volam } 3235baaa08d1SVasundhara Volam 3236baaa08d1SVasundhara Volam status = be_cmd_get_ext_fat_capabilites(adapter, &extfat_cmd); 3237baaa08d1SVasundhara Volam if (!status) { 3238baaa08d1SVasundhara Volam cfgs = (struct be_fat_conf_params *)(extfat_cmd.va + 3239baaa08d1SVasundhara Volam sizeof(struct be_cmd_resp_hdr)); 3240baaa08d1SVasundhara Volam for (j = 0; j < le32_to_cpu(cfgs->module[0].num_modes); j++) { 3241baaa08d1SVasundhara Volam if (cfgs->module[0].trace_lvl[j].mode == MODE_UART) 3242baaa08d1SVasundhara Volam level = cfgs->module[0].trace_lvl[j].dbg_lvl; 3243baaa08d1SVasundhara Volam } 3244baaa08d1SVasundhara Volam } 3245baaa08d1SVasundhara Volam pci_free_consistent(adapter->pdev, extfat_cmd.size, extfat_cmd.va, 3246baaa08d1SVasundhara Volam extfat_cmd.dma); 3247baaa08d1SVasundhara Volam err: 3248baaa08d1SVasundhara Volam return level; 3249baaa08d1SVasundhara Volam } 3250baaa08d1SVasundhara Volam 3251941a77d5SSomnath Kotur int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter, 3252941a77d5SSomnath Kotur struct be_dma_mem *cmd) 3253941a77d5SSomnath Kotur { 3254941a77d5SSomnath Kotur struct be_mcc_wrb *wrb; 3255941a77d5SSomnath Kotur struct be_cmd_req_get_ext_fat_caps *req; 3256941a77d5SSomnath Kotur int status; 3257941a77d5SSomnath Kotur 3258941a77d5SSomnath Kotur if (mutex_lock_interruptible(&adapter->mbox_lock)) 3259941a77d5SSomnath Kotur return -1; 3260941a77d5SSomnath Kotur 3261941a77d5SSomnath Kotur wrb = wrb_from_mbox(adapter); 3262941a77d5SSomnath Kotur if (!wrb) { 3263941a77d5SSomnath Kotur status = -EBUSY; 3264941a77d5SSomnath Kotur goto err; 3265941a77d5SSomnath Kotur } 3266941a77d5SSomnath Kotur 3267941a77d5SSomnath Kotur req = cmd->va; 3268941a77d5SSomnath Kotur be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 3269941a77d5SSomnath Kotur OPCODE_COMMON_GET_EXT_FAT_CAPABILITES, 3270941a77d5SSomnath Kotur cmd->size, wrb, cmd); 3271941a77d5SSomnath Kotur req->parameter_type = cpu_to_le32(1); 3272941a77d5SSomnath Kotur 3273941a77d5SSomnath Kotur status = be_mbox_notify_wait(adapter); 3274941a77d5SSomnath Kotur err: 3275941a77d5SSomnath Kotur mutex_unlock(&adapter->mbox_lock); 3276941a77d5SSomnath Kotur return status; 3277941a77d5SSomnath Kotur } 3278941a77d5SSomnath Kotur 3279941a77d5SSomnath Kotur int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter, 3280941a77d5SSomnath Kotur struct be_dma_mem *cmd, 3281941a77d5SSomnath Kotur struct be_fat_conf_params *configs) 3282941a77d5SSomnath Kotur { 3283941a77d5SSomnath Kotur struct be_mcc_wrb *wrb; 3284941a77d5SSomnath Kotur struct be_cmd_req_set_ext_fat_caps *req; 3285941a77d5SSomnath Kotur int status; 3286941a77d5SSomnath Kotur 3287941a77d5SSomnath Kotur spin_lock_bh(&adapter->mcc_lock); 3288941a77d5SSomnath Kotur 3289941a77d5SSomnath Kotur wrb = wrb_from_mccq(adapter); 3290941a77d5SSomnath Kotur if (!wrb) { 3291941a77d5SSomnath Kotur status = -EBUSY; 3292941a77d5SSomnath Kotur goto err; 3293941a77d5SSomnath Kotur } 3294941a77d5SSomnath Kotur 3295941a77d5SSomnath Kotur req = cmd->va; 3296941a77d5SSomnath Kotur memcpy(&req->set_params, configs, sizeof(struct be_fat_conf_params)); 3297941a77d5SSomnath Kotur be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 3298941a77d5SSomnath Kotur OPCODE_COMMON_SET_EXT_FAT_CAPABILITES, 3299941a77d5SSomnath Kotur cmd->size, wrb, cmd); 3300941a77d5SSomnath Kotur 3301941a77d5SSomnath Kotur status = be_mcc_notify_wait(adapter); 3302941a77d5SSomnath Kotur err: 3303941a77d5SSomnath Kotur spin_unlock_bh(&adapter->mcc_lock); 3304941a77d5SSomnath Kotur return status; 33054762f6ceSAjit Khaparde } 33066a4ab669SParav Pandit 3307b4e32a71SPadmanabh Ratnakar int be_cmd_query_port_name(struct be_adapter *adapter, u8 *port_name) 3308b4e32a71SPadmanabh Ratnakar { 3309b4e32a71SPadmanabh Ratnakar struct be_mcc_wrb *wrb; 3310b4e32a71SPadmanabh Ratnakar struct be_cmd_req_get_port_name *req; 3311b4e32a71SPadmanabh Ratnakar int status; 3312b4e32a71SPadmanabh Ratnakar 3313b4e32a71SPadmanabh Ratnakar if (!lancer_chip(adapter)) { 3314b4e32a71SPadmanabh Ratnakar *port_name = adapter->hba_port_num + '0'; 3315b4e32a71SPadmanabh Ratnakar return 0; 3316b4e32a71SPadmanabh Ratnakar } 3317b4e32a71SPadmanabh Ratnakar 3318b4e32a71SPadmanabh Ratnakar spin_lock_bh(&adapter->mcc_lock); 3319b4e32a71SPadmanabh Ratnakar 3320b4e32a71SPadmanabh Ratnakar wrb = wrb_from_mccq(adapter); 3321b4e32a71SPadmanabh Ratnakar if (!wrb) { 3322b4e32a71SPadmanabh Ratnakar status = -EBUSY; 3323b4e32a71SPadmanabh Ratnakar goto err; 3324b4e32a71SPadmanabh Ratnakar } 3325b4e32a71SPadmanabh Ratnakar 3326b4e32a71SPadmanabh Ratnakar req = embedded_payload(wrb); 3327b4e32a71SPadmanabh Ratnakar 3328b4e32a71SPadmanabh Ratnakar be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 3329b4e32a71SPadmanabh Ratnakar OPCODE_COMMON_GET_PORT_NAME, sizeof(*req), wrb, 3330b4e32a71SPadmanabh Ratnakar NULL); 3331b4e32a71SPadmanabh Ratnakar req->hdr.version = 1; 3332b4e32a71SPadmanabh Ratnakar 3333b4e32a71SPadmanabh Ratnakar status = be_mcc_notify_wait(adapter); 3334b4e32a71SPadmanabh Ratnakar if (!status) { 3335b4e32a71SPadmanabh Ratnakar struct be_cmd_resp_get_port_name *resp = embedded_payload(wrb); 3336b4e32a71SPadmanabh Ratnakar *port_name = resp->port_name[adapter->hba_port_num]; 3337b4e32a71SPadmanabh Ratnakar } else { 3338b4e32a71SPadmanabh Ratnakar *port_name = adapter->hba_port_num + '0'; 3339b4e32a71SPadmanabh Ratnakar } 3340b4e32a71SPadmanabh Ratnakar err: 3341b4e32a71SPadmanabh Ratnakar spin_unlock_bh(&adapter->mcc_lock); 3342b4e32a71SPadmanabh Ratnakar return status; 3343b4e32a71SPadmanabh Ratnakar } 3344b4e32a71SPadmanabh Ratnakar 334510cccf60SVasundhara Volam /* Descriptor type */ 334610cccf60SVasundhara Volam enum { 334710cccf60SVasundhara Volam FUNC_DESC = 1, 334810cccf60SVasundhara Volam VFT_DESC = 2 334910cccf60SVasundhara Volam }; 335010cccf60SVasundhara Volam 335110cccf60SVasundhara Volam static struct be_nic_res_desc *be_get_nic_desc(u8 *buf, u32 desc_count, 335210cccf60SVasundhara Volam int desc_type) 3353abb93951SPadmanabh Ratnakar { 3354150d58c7SVasundhara Volam struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf; 335510cccf60SVasundhara Volam struct be_nic_res_desc *nic; 3356abb93951SPadmanabh Ratnakar int i; 3357abb93951SPadmanabh Ratnakar 3358abb93951SPadmanabh Ratnakar for (i = 0; i < desc_count; i++) { 3359150d58c7SVasundhara Volam if (hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V0 || 336010cccf60SVasundhara Volam hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V1) { 336110cccf60SVasundhara Volam nic = (struct be_nic_res_desc *)hdr; 336210cccf60SVasundhara Volam if (desc_type == FUNC_DESC || 336310cccf60SVasundhara Volam (desc_type == VFT_DESC && 336410cccf60SVasundhara Volam nic->flags & (1 << VFT_SHIFT))) 336510cccf60SVasundhara Volam return nic; 336610cccf60SVasundhara Volam } 3367150d58c7SVasundhara Volam 3368150d58c7SVasundhara Volam hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0; 3369150d58c7SVasundhara Volam hdr = (void *)hdr + hdr->desc_len; 3370150d58c7SVasundhara Volam } 3371950e2958SWei Yang return NULL; 3372abb93951SPadmanabh Ratnakar } 3373abb93951SPadmanabh Ratnakar 337410cccf60SVasundhara Volam static struct be_nic_res_desc *be_get_vft_desc(u8 *buf, u32 desc_count) 337510cccf60SVasundhara Volam { 337610cccf60SVasundhara Volam return be_get_nic_desc(buf, desc_count, VFT_DESC); 337710cccf60SVasundhara Volam } 337810cccf60SVasundhara Volam 337910cccf60SVasundhara Volam static struct be_nic_res_desc *be_get_func_nic_desc(u8 *buf, u32 desc_count) 338010cccf60SVasundhara Volam { 338110cccf60SVasundhara Volam return be_get_nic_desc(buf, desc_count, FUNC_DESC); 338210cccf60SVasundhara Volam } 338310cccf60SVasundhara Volam 3384150d58c7SVasundhara Volam static struct be_pcie_res_desc *be_get_pcie_desc(u8 devfn, u8 *buf, 3385150d58c7SVasundhara Volam u32 desc_count) 3386150d58c7SVasundhara Volam { 3387150d58c7SVasundhara Volam struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf; 3388150d58c7SVasundhara Volam struct be_pcie_res_desc *pcie; 3389150d58c7SVasundhara Volam int i; 3390150d58c7SVasundhara Volam 3391150d58c7SVasundhara Volam for (i = 0; i < desc_count; i++) { 3392150d58c7SVasundhara Volam if ((hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V0 || 3393150d58c7SVasundhara Volam hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V1)) { 3394150d58c7SVasundhara Volam pcie = (struct be_pcie_res_desc *)hdr; 3395150d58c7SVasundhara Volam if (pcie->pf_num == devfn) 3396150d58c7SVasundhara Volam return pcie; 3397150d58c7SVasundhara Volam } 3398150d58c7SVasundhara Volam 3399150d58c7SVasundhara Volam hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0; 3400150d58c7SVasundhara Volam hdr = (void *)hdr + hdr->desc_len; 3401150d58c7SVasundhara Volam } 3402abb93951SPadmanabh Ratnakar return NULL; 3403abb93951SPadmanabh Ratnakar } 3404abb93951SPadmanabh Ratnakar 3405f93f160bSVasundhara Volam static struct be_port_res_desc *be_get_port_desc(u8 *buf, u32 desc_count) 3406f93f160bSVasundhara Volam { 3407f93f160bSVasundhara Volam struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf; 3408f93f160bSVasundhara Volam int i; 3409f93f160bSVasundhara Volam 3410f93f160bSVasundhara Volam for (i = 0; i < desc_count; i++) { 3411f93f160bSVasundhara Volam if (hdr->desc_type == PORT_RESOURCE_DESC_TYPE_V1) 3412f93f160bSVasundhara Volam return (struct be_port_res_desc *)hdr; 3413f93f160bSVasundhara Volam 3414f93f160bSVasundhara Volam hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0; 3415f93f160bSVasundhara Volam hdr = (void *)hdr + hdr->desc_len; 3416f93f160bSVasundhara Volam } 3417f93f160bSVasundhara Volam return NULL; 3418f93f160bSVasundhara Volam } 3419f93f160bSVasundhara Volam 342092bf14abSSathya Perla static void be_copy_nic_desc(struct be_resources *res, 342192bf14abSSathya Perla struct be_nic_res_desc *desc) 342292bf14abSSathya Perla { 342392bf14abSSathya Perla res->max_uc_mac = le16_to_cpu(desc->unicast_mac_count); 342492bf14abSSathya Perla res->max_vlans = le16_to_cpu(desc->vlan_count); 342592bf14abSSathya Perla res->max_mcast_mac = le16_to_cpu(desc->mcast_mac_count); 342692bf14abSSathya Perla res->max_tx_qs = le16_to_cpu(desc->txq_count); 342792bf14abSSathya Perla res->max_rss_qs = le16_to_cpu(desc->rssq_count); 342892bf14abSSathya Perla res->max_rx_qs = le16_to_cpu(desc->rq_count); 342992bf14abSSathya Perla res->max_evt_qs = le16_to_cpu(desc->eq_count); 343092bf14abSSathya Perla /* Clear flags that driver is not interested in */ 343192bf14abSSathya Perla res->if_cap_flags = le32_to_cpu(desc->cap_flags) & 343292bf14abSSathya Perla BE_IF_CAP_FLAGS_WANT; 343392bf14abSSathya Perla /* Need 1 RXQ as the default RXQ */ 343492bf14abSSathya Perla if (res->max_rss_qs && res->max_rss_qs == res->max_rx_qs) 343592bf14abSSathya Perla res->max_rss_qs -= 1; 343692bf14abSSathya Perla } 343792bf14abSSathya Perla 3438abb93951SPadmanabh Ratnakar /* Uses Mbox */ 343992bf14abSSathya Perla int be_cmd_get_func_config(struct be_adapter *adapter, struct be_resources *res) 3440abb93951SPadmanabh Ratnakar { 3441abb93951SPadmanabh Ratnakar struct be_mcc_wrb *wrb; 3442abb93951SPadmanabh Ratnakar struct be_cmd_req_get_func_config *req; 3443abb93951SPadmanabh Ratnakar int status; 3444abb93951SPadmanabh Ratnakar struct be_dma_mem cmd; 3445abb93951SPadmanabh Ratnakar 3446d98ef50fSSuresh Reddy if (mutex_lock_interruptible(&adapter->mbox_lock)) 3447d98ef50fSSuresh Reddy return -1; 3448d98ef50fSSuresh Reddy 3449abb93951SPadmanabh Ratnakar memset(&cmd, 0, sizeof(struct be_dma_mem)); 3450abb93951SPadmanabh Ratnakar cmd.size = sizeof(struct be_cmd_resp_get_func_config); 3451a2cc4e0bSSathya Perla cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma); 3452abb93951SPadmanabh Ratnakar if (!cmd.va) { 3453abb93951SPadmanabh Ratnakar dev_err(&adapter->pdev->dev, "Memory alloc failure\n"); 3454d98ef50fSSuresh Reddy status = -ENOMEM; 3455d98ef50fSSuresh Reddy goto err; 3456abb93951SPadmanabh Ratnakar } 3457abb93951SPadmanabh Ratnakar 3458abb93951SPadmanabh Ratnakar wrb = wrb_from_mbox(adapter); 3459abb93951SPadmanabh Ratnakar if (!wrb) { 3460abb93951SPadmanabh Ratnakar status = -EBUSY; 3461abb93951SPadmanabh Ratnakar goto err; 3462abb93951SPadmanabh Ratnakar } 3463abb93951SPadmanabh Ratnakar 3464abb93951SPadmanabh Ratnakar req = cmd.va; 3465abb93951SPadmanabh Ratnakar 3466abb93951SPadmanabh Ratnakar be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 3467abb93951SPadmanabh Ratnakar OPCODE_COMMON_GET_FUNC_CONFIG, 3468abb93951SPadmanabh Ratnakar cmd.size, wrb, &cmd); 3469abb93951SPadmanabh Ratnakar 347028710c55SKalesh AP if (skyhawk_chip(adapter)) 347128710c55SKalesh AP req->hdr.version = 1; 347228710c55SKalesh AP 3473abb93951SPadmanabh Ratnakar status = be_mbox_notify_wait(adapter); 3474abb93951SPadmanabh Ratnakar if (!status) { 3475abb93951SPadmanabh Ratnakar struct be_cmd_resp_get_func_config *resp = cmd.va; 3476abb93951SPadmanabh Ratnakar u32 desc_count = le32_to_cpu(resp->desc_count); 3477150d58c7SVasundhara Volam struct be_nic_res_desc *desc; 3478abb93951SPadmanabh Ratnakar 347910cccf60SVasundhara Volam desc = be_get_func_nic_desc(resp->func_param, desc_count); 3480abb93951SPadmanabh Ratnakar if (!desc) { 3481abb93951SPadmanabh Ratnakar status = -EINVAL; 3482abb93951SPadmanabh Ratnakar goto err; 3483abb93951SPadmanabh Ratnakar } 3484abb93951SPadmanabh Ratnakar 3485d5c18473SPadmanabh Ratnakar adapter->pf_number = desc->pf_num; 348692bf14abSSathya Perla be_copy_nic_desc(res, desc); 3487abb93951SPadmanabh Ratnakar } 3488abb93951SPadmanabh Ratnakar err: 3489abb93951SPadmanabh Ratnakar mutex_unlock(&adapter->mbox_lock); 3490d98ef50fSSuresh Reddy if (cmd.va) 3491d98ef50fSSuresh Reddy pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma); 3492abb93951SPadmanabh Ratnakar return status; 3493abb93951SPadmanabh Ratnakar } 3494abb93951SPadmanabh Ratnakar 3495ba48c0c9SVasundhara Volam /* Will use MBOX only if MCCQ has not been created */ 349692bf14abSSathya Perla int be_cmd_get_profile_config(struct be_adapter *adapter, 349792bf14abSSathya Perla struct be_resources *res, u8 domain) 3498a05f99dbSVasundhara Volam { 3499150d58c7SVasundhara Volam struct be_cmd_resp_get_profile_config *resp; 3500ba48c0c9SVasundhara Volam struct be_cmd_req_get_profile_config *req; 350110cccf60SVasundhara Volam struct be_nic_res_desc *vf_res; 3502150d58c7SVasundhara Volam struct be_pcie_res_desc *pcie; 3503f93f160bSVasundhara Volam struct be_port_res_desc *port; 3504150d58c7SVasundhara Volam struct be_nic_res_desc *nic; 3505ba48c0c9SVasundhara Volam struct be_mcc_wrb wrb = {0}; 3506a05f99dbSVasundhara Volam struct be_dma_mem cmd; 3507150d58c7SVasundhara Volam u32 desc_count; 3508a05f99dbSVasundhara Volam int status; 3509a05f99dbSVasundhara Volam 3510a05f99dbSVasundhara Volam memset(&cmd, 0, sizeof(struct be_dma_mem)); 3511a05f99dbSVasundhara Volam cmd.size = sizeof(struct be_cmd_resp_get_profile_config); 3512150d58c7SVasundhara Volam cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma); 3513150d58c7SVasundhara Volam if (!cmd.va) 3514a05f99dbSVasundhara Volam return -ENOMEM; 3515a05f99dbSVasundhara Volam 3516ba48c0c9SVasundhara Volam req = cmd.va; 3517ba48c0c9SVasundhara Volam be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 3518ba48c0c9SVasundhara Volam OPCODE_COMMON_GET_PROFILE_CONFIG, 3519ba48c0c9SVasundhara Volam cmd.size, &wrb, &cmd); 3520ba48c0c9SVasundhara Volam 3521ba48c0c9SVasundhara Volam req->hdr.domain = domain; 3522ba48c0c9SVasundhara Volam if (!lancer_chip(adapter)) 3523ba48c0c9SVasundhara Volam req->hdr.version = 1; 3524ba48c0c9SVasundhara Volam req->type = ACTIVE_PROFILE_TYPE; 3525ba48c0c9SVasundhara Volam 3526ba48c0c9SVasundhara Volam status = be_cmd_notify_wait(adapter, &wrb); 3527150d58c7SVasundhara Volam if (status) 3528abb93951SPadmanabh Ratnakar goto err; 3529150d58c7SVasundhara Volam 3530150d58c7SVasundhara Volam resp = cmd.va; 3531150d58c7SVasundhara Volam desc_count = le32_to_cpu(resp->desc_count); 3532150d58c7SVasundhara Volam 3533150d58c7SVasundhara Volam pcie = be_get_pcie_desc(adapter->pdev->devfn, resp->func_param, 3534150d58c7SVasundhara Volam desc_count); 3535150d58c7SVasundhara Volam if (pcie) 353692bf14abSSathya Perla res->max_vfs = le16_to_cpu(pcie->num_vfs); 3537150d58c7SVasundhara Volam 3538f93f160bSVasundhara Volam port = be_get_port_desc(resp->func_param, desc_count); 3539f93f160bSVasundhara Volam if (port) 3540f93f160bSVasundhara Volam adapter->mc_type = port->mc_type; 3541f93f160bSVasundhara Volam 354210cccf60SVasundhara Volam nic = be_get_func_nic_desc(resp->func_param, desc_count); 354392bf14abSSathya Perla if (nic) 354492bf14abSSathya Perla be_copy_nic_desc(res, nic); 354592bf14abSSathya Perla 354610cccf60SVasundhara Volam vf_res = be_get_vft_desc(resp->func_param, desc_count); 354710cccf60SVasundhara Volam if (vf_res) 354810cccf60SVasundhara Volam res->vf_if_cap_flags = vf_res->cap_flags; 3549abb93951SPadmanabh Ratnakar err: 3550a05f99dbSVasundhara Volam if (cmd.va) 3551150d58c7SVasundhara Volam pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma); 3552abb93951SPadmanabh Ratnakar return status; 3553abb93951SPadmanabh Ratnakar } 3554abb93951SPadmanabh Ratnakar 3555bec84e6bSVasundhara Volam /* Will use MBOX only if MCCQ has not been created */ 3556bec84e6bSVasundhara Volam static int be_cmd_set_profile_config(struct be_adapter *adapter, void *desc, 3557bec84e6bSVasundhara Volam int size, int count, u8 version, u8 domain) 3558d5c18473SPadmanabh Ratnakar { 3559d5c18473SPadmanabh Ratnakar struct be_cmd_req_set_profile_config *req; 3560bec84e6bSVasundhara Volam struct be_mcc_wrb wrb = {0}; 3561bec84e6bSVasundhara Volam struct be_dma_mem cmd; 3562d5c18473SPadmanabh Ratnakar int status; 3563d5c18473SPadmanabh Ratnakar 3564bec84e6bSVasundhara Volam memset(&cmd, 0, sizeof(struct be_dma_mem)); 3565bec84e6bSVasundhara Volam cmd.size = sizeof(struct be_cmd_req_set_profile_config); 3566bec84e6bSVasundhara Volam cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma); 3567bec84e6bSVasundhara Volam if (!cmd.va) 3568bec84e6bSVasundhara Volam return -ENOMEM; 3569d5c18473SPadmanabh Ratnakar 3570bec84e6bSVasundhara Volam req = cmd.va; 3571d5c18473SPadmanabh Ratnakar be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 3572bec84e6bSVasundhara Volam OPCODE_COMMON_SET_PROFILE_CONFIG, cmd.size, 3573bec84e6bSVasundhara Volam &wrb, &cmd); 3574a401801cSSathya Perla req->hdr.version = version; 3575d5c18473SPadmanabh Ratnakar req->hdr.domain = domain; 3576bec84e6bSVasundhara Volam req->desc_count = cpu_to_le32(count); 3577a401801cSSathya Perla memcpy(req->desc, desc, size); 3578d5c18473SPadmanabh Ratnakar 3579bec84e6bSVasundhara Volam status = be_cmd_notify_wait(adapter, &wrb); 3580bec84e6bSVasundhara Volam 3581bec84e6bSVasundhara Volam if (cmd.va) 3582bec84e6bSVasundhara Volam pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma); 3583d5c18473SPadmanabh Ratnakar return status; 3584d5c18473SPadmanabh Ratnakar } 3585d5c18473SPadmanabh Ratnakar 3586a401801cSSathya Perla /* Mark all fields invalid */ 3587bec84e6bSVasundhara Volam static void be_reset_nic_desc(struct be_nic_res_desc *nic) 3588a401801cSSathya Perla { 3589a401801cSSathya Perla memset(nic, 0, sizeof(*nic)); 3590a401801cSSathya Perla nic->unicast_mac_count = 0xFFFF; 3591a401801cSSathya Perla nic->mcc_count = 0xFFFF; 3592a401801cSSathya Perla nic->vlan_count = 0xFFFF; 3593a401801cSSathya Perla nic->mcast_mac_count = 0xFFFF; 3594a401801cSSathya Perla nic->txq_count = 0xFFFF; 3595a401801cSSathya Perla nic->rq_count = 0xFFFF; 3596a401801cSSathya Perla nic->rssq_count = 0xFFFF; 3597a401801cSSathya Perla nic->lro_count = 0xFFFF; 3598a401801cSSathya Perla nic->cq_count = 0xFFFF; 3599a401801cSSathya Perla nic->toe_conn_count = 0xFFFF; 3600a401801cSSathya Perla nic->eq_count = 0xFFFF; 36010f77ba73SRavikumar Nelavelli nic->iface_count = 0xFFFF; 3602a401801cSSathya Perla nic->link_param = 0xFF; 36030f77ba73SRavikumar Nelavelli nic->channel_id_param = cpu_to_le16(0xF000); 3604a401801cSSathya Perla nic->acpi_params = 0xFF; 3605a401801cSSathya Perla nic->wol_param = 0x0F; 36060f77ba73SRavikumar Nelavelli nic->tunnel_iface_count = 0xFFFF; 36070f77ba73SRavikumar Nelavelli nic->direct_tenant_iface_count = 0xFFFF; 3608bec84e6bSVasundhara Volam nic->bw_min = 0xFFFFFFFF; 3609a401801cSSathya Perla nic->bw_max = 0xFFFFFFFF; 3610a401801cSSathya Perla } 3611a401801cSSathya Perla 3612bec84e6bSVasundhara Volam /* Mark all fields invalid */ 3613bec84e6bSVasundhara Volam static void be_reset_pcie_desc(struct be_pcie_res_desc *pcie) 3614bec84e6bSVasundhara Volam { 3615bec84e6bSVasundhara Volam memset(pcie, 0, sizeof(*pcie)); 3616bec84e6bSVasundhara Volam pcie->sriov_state = 0xFF; 3617bec84e6bSVasundhara Volam pcie->pf_state = 0xFF; 3618bec84e6bSVasundhara Volam pcie->pf_type = 0xFF; 3619bec84e6bSVasundhara Volam pcie->num_vfs = 0xFFFF; 3620bec84e6bSVasundhara Volam } 3621bec84e6bSVasundhara Volam 36220f77ba73SRavikumar Nelavelli int be_cmd_config_qos(struct be_adapter *adapter, u32 max_rate, u16 link_speed, 36230f77ba73SRavikumar Nelavelli u8 domain) 3624a401801cSSathya Perla { 3625a401801cSSathya Perla struct be_nic_res_desc nic_desc; 36260f77ba73SRavikumar Nelavelli u32 bw_percent; 36270f77ba73SRavikumar Nelavelli u16 version = 0; 36280f77ba73SRavikumar Nelavelli 36290f77ba73SRavikumar Nelavelli if (BE3_chip(adapter)) 36300f77ba73SRavikumar Nelavelli return be_cmd_set_qos(adapter, max_rate / 10, domain); 3631a401801cSSathya Perla 3632a401801cSSathya Perla be_reset_nic_desc(&nic_desc); 36330f77ba73SRavikumar Nelavelli nic_desc.pf_num = adapter->pf_number; 36340f77ba73SRavikumar Nelavelli nic_desc.vf_num = domain; 36350f77ba73SRavikumar Nelavelli if (lancer_chip(adapter)) { 3636a401801cSSathya Perla nic_desc.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V0; 3637a401801cSSathya Perla nic_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V0; 3638a401801cSSathya Perla nic_desc.flags = (1 << QUN_SHIFT) | (1 << IMM_SHIFT) | 3639a401801cSSathya Perla (1 << NOSV_SHIFT); 36400f77ba73SRavikumar Nelavelli nic_desc.bw_max = cpu_to_le32(max_rate / 10); 36410f77ba73SRavikumar Nelavelli } else { 36420f77ba73SRavikumar Nelavelli version = 1; 36430f77ba73SRavikumar Nelavelli nic_desc.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V1; 36440f77ba73SRavikumar Nelavelli nic_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V1; 36450f77ba73SRavikumar Nelavelli nic_desc.flags = (1 << IMM_SHIFT) | (1 << NOSV_SHIFT); 36460f77ba73SRavikumar Nelavelli bw_percent = max_rate ? (max_rate * 100) / link_speed : 100; 36470f77ba73SRavikumar Nelavelli nic_desc.bw_max = cpu_to_le32(bw_percent); 36480f77ba73SRavikumar Nelavelli } 3649a401801cSSathya Perla 3650a401801cSSathya Perla return be_cmd_set_profile_config(adapter, &nic_desc, 36510f77ba73SRavikumar Nelavelli nic_desc.hdr.desc_len, 3652bec84e6bSVasundhara Volam 1, version, domain); 3653bec84e6bSVasundhara Volam } 3654bec84e6bSVasundhara Volam 3655bec84e6bSVasundhara Volam int be_cmd_set_sriov_config(struct be_adapter *adapter, 3656bec84e6bSVasundhara Volam struct be_resources res, u16 num_vfs) 3657bec84e6bSVasundhara Volam { 3658bec84e6bSVasundhara Volam struct { 3659bec84e6bSVasundhara Volam struct be_pcie_res_desc pcie; 3660bec84e6bSVasundhara Volam struct be_nic_res_desc nic_vft; 3661bec84e6bSVasundhara Volam } __packed desc; 3662bec84e6bSVasundhara Volam u16 vf_q_count; 3663bec84e6bSVasundhara Volam 3664bec84e6bSVasundhara Volam if (BEx_chip(adapter) || lancer_chip(adapter)) 3665bec84e6bSVasundhara Volam return 0; 3666bec84e6bSVasundhara Volam 3667bec84e6bSVasundhara Volam /* PF PCIE descriptor */ 3668bec84e6bSVasundhara Volam be_reset_pcie_desc(&desc.pcie); 3669bec84e6bSVasundhara Volam desc.pcie.hdr.desc_type = PCIE_RESOURCE_DESC_TYPE_V1; 3670bec84e6bSVasundhara Volam desc.pcie.hdr.desc_len = RESOURCE_DESC_SIZE_V1; 3671bec84e6bSVasundhara Volam desc.pcie.flags = (1 << IMM_SHIFT) | (1 << NOSV_SHIFT); 3672bec84e6bSVasundhara Volam desc.pcie.pf_num = adapter->pdev->devfn; 3673bec84e6bSVasundhara Volam desc.pcie.sriov_state = num_vfs ? 1 : 0; 3674bec84e6bSVasundhara Volam desc.pcie.num_vfs = cpu_to_le16(num_vfs); 3675bec84e6bSVasundhara Volam 3676bec84e6bSVasundhara Volam /* VF NIC Template descriptor */ 3677bec84e6bSVasundhara Volam be_reset_nic_desc(&desc.nic_vft); 3678bec84e6bSVasundhara Volam desc.nic_vft.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V1; 3679bec84e6bSVasundhara Volam desc.nic_vft.hdr.desc_len = RESOURCE_DESC_SIZE_V1; 3680bec84e6bSVasundhara Volam desc.nic_vft.flags = (1 << VFT_SHIFT) | (1 << IMM_SHIFT) | 3681bec84e6bSVasundhara Volam (1 << NOSV_SHIFT); 3682bec84e6bSVasundhara Volam desc.nic_vft.pf_num = adapter->pdev->devfn; 3683bec84e6bSVasundhara Volam desc.nic_vft.vf_num = 0; 3684bec84e6bSVasundhara Volam 3685bec84e6bSVasundhara Volam if (num_vfs && res.vf_if_cap_flags & BE_IF_FLAGS_RSS) { 3686bec84e6bSVasundhara Volam /* If number of VFs requested is 8 less than max supported, 3687bec84e6bSVasundhara Volam * assign 8 queue pairs to the PF and divide the remaining 3688bec84e6bSVasundhara Volam * resources evenly among the VFs 3689bec84e6bSVasundhara Volam */ 3690bec84e6bSVasundhara Volam if (num_vfs < (be_max_vfs(adapter) - 8)) 3691bec84e6bSVasundhara Volam vf_q_count = (res.max_rss_qs - 8) / num_vfs; 3692bec84e6bSVasundhara Volam else 3693bec84e6bSVasundhara Volam vf_q_count = res.max_rss_qs / num_vfs; 3694bec84e6bSVasundhara Volam 3695bec84e6bSVasundhara Volam desc.nic_vft.rq_count = cpu_to_le16(vf_q_count); 3696bec84e6bSVasundhara Volam desc.nic_vft.txq_count = cpu_to_le16(vf_q_count); 3697bec84e6bSVasundhara Volam desc.nic_vft.rssq_count = cpu_to_le16(vf_q_count - 1); 3698bec84e6bSVasundhara Volam desc.nic_vft.cq_count = cpu_to_le16(3 * vf_q_count); 3699bec84e6bSVasundhara Volam } else { 3700bec84e6bSVasundhara Volam desc.nic_vft.txq_count = cpu_to_le16(1); 3701bec84e6bSVasundhara Volam desc.nic_vft.rq_count = cpu_to_le16(1); 3702bec84e6bSVasundhara Volam desc.nic_vft.rssq_count = cpu_to_le16(0); 3703bec84e6bSVasundhara Volam /* One CQ for each TX, RX and MCCQ */ 3704bec84e6bSVasundhara Volam desc.nic_vft.cq_count = cpu_to_le16(3); 3705bec84e6bSVasundhara Volam } 3706bec84e6bSVasundhara Volam 3707bec84e6bSVasundhara Volam return be_cmd_set_profile_config(adapter, &desc, 3708bec84e6bSVasundhara Volam 2 * RESOURCE_DESC_SIZE_V1, 2, 1, 0); 3709a401801cSSathya Perla } 3710a401801cSSathya Perla 3711a401801cSSathya Perla int be_cmd_manage_iface(struct be_adapter *adapter, u32 iface, u8 op) 3712a401801cSSathya Perla { 3713a401801cSSathya Perla struct be_mcc_wrb *wrb; 3714a401801cSSathya Perla struct be_cmd_req_manage_iface_filters *req; 3715a401801cSSathya Perla int status; 3716a401801cSSathya Perla 3717a401801cSSathya Perla if (iface == 0xFFFFFFFF) 3718a401801cSSathya Perla return -1; 3719a401801cSSathya Perla 3720a401801cSSathya Perla spin_lock_bh(&adapter->mcc_lock); 3721a401801cSSathya Perla 3722a401801cSSathya Perla wrb = wrb_from_mccq(adapter); 3723a401801cSSathya Perla if (!wrb) { 3724a401801cSSathya Perla status = -EBUSY; 3725a401801cSSathya Perla goto err; 3726a401801cSSathya Perla } 3727a401801cSSathya Perla req = embedded_payload(wrb); 3728a401801cSSathya Perla 3729a401801cSSathya Perla be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 3730a401801cSSathya Perla OPCODE_COMMON_MANAGE_IFACE_FILTERS, sizeof(*req), 3731a401801cSSathya Perla wrb, NULL); 3732a401801cSSathya Perla req->op = op; 3733a401801cSSathya Perla req->target_iface_id = cpu_to_le32(iface); 3734a401801cSSathya Perla 3735a401801cSSathya Perla status = be_mcc_notify_wait(adapter); 3736a401801cSSathya Perla err: 3737a401801cSSathya Perla spin_unlock_bh(&adapter->mcc_lock); 3738a401801cSSathya Perla return status; 3739a401801cSSathya Perla } 3740a401801cSSathya Perla 3741a401801cSSathya Perla int be_cmd_set_vxlan_port(struct be_adapter *adapter, __be16 port) 3742a401801cSSathya Perla { 3743a401801cSSathya Perla struct be_port_res_desc port_desc; 3744a401801cSSathya Perla 3745a401801cSSathya Perla memset(&port_desc, 0, sizeof(port_desc)); 3746a401801cSSathya Perla port_desc.hdr.desc_type = PORT_RESOURCE_DESC_TYPE_V1; 3747a401801cSSathya Perla port_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V1; 3748a401801cSSathya Perla port_desc.flags = (1 << IMM_SHIFT) | (1 << NOSV_SHIFT); 3749a401801cSSathya Perla port_desc.link_num = adapter->hba_port_num; 3750a401801cSSathya Perla if (port) { 3751a401801cSSathya Perla port_desc.nv_flags = NV_TYPE_VXLAN | (1 << SOCVID_SHIFT) | 3752a401801cSSathya Perla (1 << RCVID_SHIFT); 3753a401801cSSathya Perla port_desc.nv_port = swab16(port); 3754a401801cSSathya Perla } else { 3755a401801cSSathya Perla port_desc.nv_flags = NV_TYPE_DISABLED; 3756a401801cSSathya Perla port_desc.nv_port = 0; 3757a401801cSSathya Perla } 3758a401801cSSathya Perla 3759a401801cSSathya Perla return be_cmd_set_profile_config(adapter, &port_desc, 3760bec84e6bSVasundhara Volam RESOURCE_DESC_SIZE_V1, 1, 1, 0); 3761a401801cSSathya Perla } 3762a401801cSSathya Perla 37634c876616SSathya Perla int be_cmd_get_if_id(struct be_adapter *adapter, struct be_vf_cfg *vf_cfg, 37644c876616SSathya Perla int vf_num) 37654c876616SSathya Perla { 37664c876616SSathya Perla struct be_mcc_wrb *wrb; 37674c876616SSathya Perla struct be_cmd_req_get_iface_list *req; 37684c876616SSathya Perla struct be_cmd_resp_get_iface_list *resp; 37694c876616SSathya Perla int status; 37704c876616SSathya Perla 37714c876616SSathya Perla spin_lock_bh(&adapter->mcc_lock); 37724c876616SSathya Perla 37734c876616SSathya Perla wrb = wrb_from_mccq(adapter); 37744c876616SSathya Perla if (!wrb) { 37754c876616SSathya Perla status = -EBUSY; 37764c876616SSathya Perla goto err; 37774c876616SSathya Perla } 37784c876616SSathya Perla req = embedded_payload(wrb); 37794c876616SSathya Perla 37804c876616SSathya Perla be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 37814c876616SSathya Perla OPCODE_COMMON_GET_IFACE_LIST, sizeof(*resp), 37824c876616SSathya Perla wrb, NULL); 37834c876616SSathya Perla req->hdr.domain = vf_num + 1; 37844c876616SSathya Perla 37854c876616SSathya Perla status = be_mcc_notify_wait(adapter); 37864c876616SSathya Perla if (!status) { 37874c876616SSathya Perla resp = (struct be_cmd_resp_get_iface_list *)req; 37884c876616SSathya Perla vf_cfg->if_handle = le32_to_cpu(resp->if_desc.if_id); 37894c876616SSathya Perla } 37904c876616SSathya Perla 37914c876616SSathya Perla err: 37924c876616SSathya Perla spin_unlock_bh(&adapter->mcc_lock); 37934c876616SSathya Perla return status; 37944c876616SSathya Perla } 37954c876616SSathya Perla 37965c510811SSomnath Kotur static int lancer_wait_idle(struct be_adapter *adapter) 37975c510811SSomnath Kotur { 37985c510811SSomnath Kotur #define SLIPORT_IDLE_TIMEOUT 30 37995c510811SSomnath Kotur u32 reg_val; 38005c510811SSomnath Kotur int status = 0, i; 38015c510811SSomnath Kotur 38025c510811SSomnath Kotur for (i = 0; i < SLIPORT_IDLE_TIMEOUT; i++) { 38035c510811SSomnath Kotur reg_val = ioread32(adapter->db + PHYSDEV_CONTROL_OFFSET); 38045c510811SSomnath Kotur if ((reg_val & PHYSDEV_CONTROL_INP_MASK) == 0) 38055c510811SSomnath Kotur break; 38065c510811SSomnath Kotur 38075c510811SSomnath Kotur ssleep(1); 38085c510811SSomnath Kotur } 38095c510811SSomnath Kotur 38105c510811SSomnath Kotur if (i == SLIPORT_IDLE_TIMEOUT) 38115c510811SSomnath Kotur status = -1; 38125c510811SSomnath Kotur 38135c510811SSomnath Kotur return status; 38145c510811SSomnath Kotur } 38155c510811SSomnath Kotur 38165c510811SSomnath Kotur int lancer_physdev_ctrl(struct be_adapter *adapter, u32 mask) 38175c510811SSomnath Kotur { 38185c510811SSomnath Kotur int status = 0; 38195c510811SSomnath Kotur 38205c510811SSomnath Kotur status = lancer_wait_idle(adapter); 38215c510811SSomnath Kotur if (status) 38225c510811SSomnath Kotur return status; 38235c510811SSomnath Kotur 38245c510811SSomnath Kotur iowrite32(mask, adapter->db + PHYSDEV_CONTROL_OFFSET); 38255c510811SSomnath Kotur 38265c510811SSomnath Kotur return status; 38275c510811SSomnath Kotur } 38285c510811SSomnath Kotur 38295c510811SSomnath Kotur /* Routine to check whether dump image is present or not */ 38305c510811SSomnath Kotur bool dump_present(struct be_adapter *adapter) 38315c510811SSomnath Kotur { 38325c510811SSomnath Kotur u32 sliport_status = 0; 38335c510811SSomnath Kotur 38345c510811SSomnath Kotur sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET); 38355c510811SSomnath Kotur return !!(sliport_status & SLIPORT_STATUS_DIP_MASK); 38365c510811SSomnath Kotur } 38375c510811SSomnath Kotur 38385c510811SSomnath Kotur int lancer_initiate_dump(struct be_adapter *adapter) 38395c510811SSomnath Kotur { 3840f0613380SKalesh AP struct device *dev = &adapter->pdev->dev; 38415c510811SSomnath Kotur int status; 38425c510811SSomnath Kotur 3843f0613380SKalesh AP if (dump_present(adapter)) { 3844f0613380SKalesh AP dev_info(dev, "Previous dump not cleared, not forcing dump\n"); 3845f0613380SKalesh AP return -EEXIST; 3846f0613380SKalesh AP } 3847f0613380SKalesh AP 38485c510811SSomnath Kotur /* give firmware reset and diagnostic dump */ 38495c510811SSomnath Kotur status = lancer_physdev_ctrl(adapter, PHYSDEV_CONTROL_FW_RESET_MASK | 38505c510811SSomnath Kotur PHYSDEV_CONTROL_DD_MASK); 38515c510811SSomnath Kotur if (status < 0) { 3852f0613380SKalesh AP dev_err(dev, "FW reset failed\n"); 38535c510811SSomnath Kotur return status; 38545c510811SSomnath Kotur } 38555c510811SSomnath Kotur 38565c510811SSomnath Kotur status = lancer_wait_idle(adapter); 38575c510811SSomnath Kotur if (status) 38585c510811SSomnath Kotur return status; 38595c510811SSomnath Kotur 38605c510811SSomnath Kotur if (!dump_present(adapter)) { 3861f0613380SKalesh AP dev_err(dev, "FW dump not generated\n"); 3862f0613380SKalesh AP return -EIO; 38635c510811SSomnath Kotur } 38645c510811SSomnath Kotur 38655c510811SSomnath Kotur return 0; 38665c510811SSomnath Kotur } 38675c510811SSomnath Kotur 3868f0613380SKalesh AP int lancer_delete_dump(struct be_adapter *adapter) 3869f0613380SKalesh AP { 3870f0613380SKalesh AP int status; 3871f0613380SKalesh AP 3872f0613380SKalesh AP status = lancer_cmd_delete_object(adapter, LANCER_FW_DUMP_FILE); 3873f0613380SKalesh AP return be_cmd_status(status); 3874f0613380SKalesh AP } 3875f0613380SKalesh AP 3876dcf7ebbaSPadmanabh Ratnakar /* Uses sync mcc */ 3877dcf7ebbaSPadmanabh Ratnakar int be_cmd_enable_vf(struct be_adapter *adapter, u8 domain) 3878dcf7ebbaSPadmanabh Ratnakar { 3879dcf7ebbaSPadmanabh Ratnakar struct be_mcc_wrb *wrb; 3880dcf7ebbaSPadmanabh Ratnakar struct be_cmd_enable_disable_vf *req; 3881dcf7ebbaSPadmanabh Ratnakar int status; 3882dcf7ebbaSPadmanabh Ratnakar 38830599863dSVasundhara Volam if (BEx_chip(adapter)) 3884dcf7ebbaSPadmanabh Ratnakar return 0; 3885dcf7ebbaSPadmanabh Ratnakar 3886dcf7ebbaSPadmanabh Ratnakar spin_lock_bh(&adapter->mcc_lock); 3887dcf7ebbaSPadmanabh Ratnakar 3888dcf7ebbaSPadmanabh Ratnakar wrb = wrb_from_mccq(adapter); 3889dcf7ebbaSPadmanabh Ratnakar if (!wrb) { 3890dcf7ebbaSPadmanabh Ratnakar status = -EBUSY; 3891dcf7ebbaSPadmanabh Ratnakar goto err; 3892dcf7ebbaSPadmanabh Ratnakar } 3893dcf7ebbaSPadmanabh Ratnakar 3894dcf7ebbaSPadmanabh Ratnakar req = embedded_payload(wrb); 3895dcf7ebbaSPadmanabh Ratnakar 3896dcf7ebbaSPadmanabh Ratnakar be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 3897dcf7ebbaSPadmanabh Ratnakar OPCODE_COMMON_ENABLE_DISABLE_VF, sizeof(*req), 3898dcf7ebbaSPadmanabh Ratnakar wrb, NULL); 3899dcf7ebbaSPadmanabh Ratnakar 3900dcf7ebbaSPadmanabh Ratnakar req->hdr.domain = domain; 3901dcf7ebbaSPadmanabh Ratnakar req->enable = 1; 3902dcf7ebbaSPadmanabh Ratnakar status = be_mcc_notify_wait(adapter); 3903dcf7ebbaSPadmanabh Ratnakar err: 3904dcf7ebbaSPadmanabh Ratnakar spin_unlock_bh(&adapter->mcc_lock); 3905dcf7ebbaSPadmanabh Ratnakar return status; 3906dcf7ebbaSPadmanabh Ratnakar } 3907dcf7ebbaSPadmanabh Ratnakar 390868c45a2dSSomnath Kotur int be_cmd_intr_set(struct be_adapter *adapter, bool intr_enable) 390968c45a2dSSomnath Kotur { 391068c45a2dSSomnath Kotur struct be_mcc_wrb *wrb; 391168c45a2dSSomnath Kotur struct be_cmd_req_intr_set *req; 391268c45a2dSSomnath Kotur int status; 391368c45a2dSSomnath Kotur 391468c45a2dSSomnath Kotur if (mutex_lock_interruptible(&adapter->mbox_lock)) 391568c45a2dSSomnath Kotur return -1; 391668c45a2dSSomnath Kotur 391768c45a2dSSomnath Kotur wrb = wrb_from_mbox(adapter); 391868c45a2dSSomnath Kotur 391968c45a2dSSomnath Kotur req = embedded_payload(wrb); 392068c45a2dSSomnath Kotur 392168c45a2dSSomnath Kotur be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 392268c45a2dSSomnath Kotur OPCODE_COMMON_SET_INTERRUPT_ENABLE, sizeof(*req), 392368c45a2dSSomnath Kotur wrb, NULL); 392468c45a2dSSomnath Kotur 392568c45a2dSSomnath Kotur req->intr_enabled = intr_enable; 392668c45a2dSSomnath Kotur 392768c45a2dSSomnath Kotur status = be_mbox_notify_wait(adapter); 392868c45a2dSSomnath Kotur 392968c45a2dSSomnath Kotur mutex_unlock(&adapter->mbox_lock); 393068c45a2dSSomnath Kotur return status; 393168c45a2dSSomnath Kotur } 393268c45a2dSSomnath Kotur 3933542963b7SVasundhara Volam /* Uses MBOX */ 3934542963b7SVasundhara Volam int be_cmd_get_active_profile(struct be_adapter *adapter, u16 *profile_id) 3935542963b7SVasundhara Volam { 3936542963b7SVasundhara Volam struct be_cmd_req_get_active_profile *req; 3937542963b7SVasundhara Volam struct be_mcc_wrb *wrb; 3938542963b7SVasundhara Volam int status; 3939542963b7SVasundhara Volam 3940542963b7SVasundhara Volam if (mutex_lock_interruptible(&adapter->mbox_lock)) 3941542963b7SVasundhara Volam return -1; 3942542963b7SVasundhara Volam 3943542963b7SVasundhara Volam wrb = wrb_from_mbox(adapter); 3944542963b7SVasundhara Volam if (!wrb) { 3945542963b7SVasundhara Volam status = -EBUSY; 3946542963b7SVasundhara Volam goto err; 3947542963b7SVasundhara Volam } 3948542963b7SVasundhara Volam 3949542963b7SVasundhara Volam req = embedded_payload(wrb); 3950542963b7SVasundhara Volam 3951542963b7SVasundhara Volam be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 3952542963b7SVasundhara Volam OPCODE_COMMON_GET_ACTIVE_PROFILE, sizeof(*req), 3953542963b7SVasundhara Volam wrb, NULL); 3954542963b7SVasundhara Volam 3955542963b7SVasundhara Volam status = be_mbox_notify_wait(adapter); 3956542963b7SVasundhara Volam if (!status) { 3957542963b7SVasundhara Volam struct be_cmd_resp_get_active_profile *resp = 3958542963b7SVasundhara Volam embedded_payload(wrb); 3959542963b7SVasundhara Volam *profile_id = le16_to_cpu(resp->active_profile_id); 3960542963b7SVasundhara Volam } 3961542963b7SVasundhara Volam 3962542963b7SVasundhara Volam err: 3963542963b7SVasundhara Volam mutex_unlock(&adapter->mbox_lock); 3964542963b7SVasundhara Volam return status; 3965542963b7SVasundhara Volam } 3966542963b7SVasundhara Volam 3967bdce2ad7SSuresh Reddy int be_cmd_set_logical_link_config(struct be_adapter *adapter, 3968bdce2ad7SSuresh Reddy int link_state, u8 domain) 3969bdce2ad7SSuresh Reddy { 3970bdce2ad7SSuresh Reddy struct be_mcc_wrb *wrb; 3971bdce2ad7SSuresh Reddy struct be_cmd_req_set_ll_link *req; 3972bdce2ad7SSuresh Reddy int status; 3973bdce2ad7SSuresh Reddy 3974bdce2ad7SSuresh Reddy if (BEx_chip(adapter) || lancer_chip(adapter)) 3975bdce2ad7SSuresh Reddy return 0; 3976bdce2ad7SSuresh Reddy 3977bdce2ad7SSuresh Reddy spin_lock_bh(&adapter->mcc_lock); 3978bdce2ad7SSuresh Reddy 3979bdce2ad7SSuresh Reddy wrb = wrb_from_mccq(adapter); 3980bdce2ad7SSuresh Reddy if (!wrb) { 3981bdce2ad7SSuresh Reddy status = -EBUSY; 3982bdce2ad7SSuresh Reddy goto err; 3983bdce2ad7SSuresh Reddy } 3984bdce2ad7SSuresh Reddy 3985bdce2ad7SSuresh Reddy req = embedded_payload(wrb); 3986bdce2ad7SSuresh Reddy 3987bdce2ad7SSuresh Reddy be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 3988bdce2ad7SSuresh Reddy OPCODE_COMMON_SET_LOGICAL_LINK_CONFIG, 3989bdce2ad7SSuresh Reddy sizeof(*req), wrb, NULL); 3990bdce2ad7SSuresh Reddy 3991bdce2ad7SSuresh Reddy req->hdr.version = 1; 3992bdce2ad7SSuresh Reddy req->hdr.domain = domain; 3993bdce2ad7SSuresh Reddy 3994bdce2ad7SSuresh Reddy if (link_state == IFLA_VF_LINK_STATE_ENABLE) 3995bdce2ad7SSuresh Reddy req->link_config |= 1; 3996bdce2ad7SSuresh Reddy 3997bdce2ad7SSuresh Reddy if (link_state == IFLA_VF_LINK_STATE_AUTO) 3998bdce2ad7SSuresh Reddy req->link_config |= 1 << PLINK_TRACK_SHIFT; 3999bdce2ad7SSuresh Reddy 4000bdce2ad7SSuresh Reddy status = be_mcc_notify_wait(adapter); 4001bdce2ad7SSuresh Reddy err: 4002bdce2ad7SSuresh Reddy spin_unlock_bh(&adapter->mcc_lock); 4003bdce2ad7SSuresh Reddy return status; 4004bdce2ad7SSuresh Reddy } 4005bdce2ad7SSuresh Reddy 40066a4ab669SParav Pandit int be_roce_mcc_cmd(void *netdev_handle, void *wrb_payload, 40076a4ab669SParav Pandit int wrb_payload_size, u16 *cmd_status, u16 *ext_status) 40086a4ab669SParav Pandit { 40096a4ab669SParav Pandit struct be_adapter *adapter = netdev_priv(netdev_handle); 40106a4ab669SParav Pandit struct be_mcc_wrb *wrb; 40116a4ab669SParav Pandit struct be_cmd_req_hdr *hdr = (struct be_cmd_req_hdr *) wrb_payload; 40126a4ab669SParav Pandit struct be_cmd_req_hdr *req; 40136a4ab669SParav Pandit struct be_cmd_resp_hdr *resp; 40146a4ab669SParav Pandit int status; 40156a4ab669SParav Pandit 40166a4ab669SParav Pandit spin_lock_bh(&adapter->mcc_lock); 40176a4ab669SParav Pandit 40186a4ab669SParav Pandit wrb = wrb_from_mccq(adapter); 40196a4ab669SParav Pandit if (!wrb) { 40206a4ab669SParav Pandit status = -EBUSY; 40216a4ab669SParav Pandit goto err; 40226a4ab669SParav Pandit } 40236a4ab669SParav Pandit req = embedded_payload(wrb); 40246a4ab669SParav Pandit resp = embedded_payload(wrb); 40256a4ab669SParav Pandit 40266a4ab669SParav Pandit be_wrb_cmd_hdr_prepare(req, hdr->subsystem, 40276a4ab669SParav Pandit hdr->opcode, wrb_payload_size, wrb, NULL); 40286a4ab669SParav Pandit memcpy(req, wrb_payload, wrb_payload_size); 40296a4ab669SParav Pandit be_dws_cpu_to_le(req, wrb_payload_size); 40306a4ab669SParav Pandit 40316a4ab669SParav Pandit status = be_mcc_notify_wait(adapter); 40326a4ab669SParav Pandit if (cmd_status) 40336a4ab669SParav Pandit *cmd_status = (status & 0xffff); 40346a4ab669SParav Pandit if (ext_status) 40356a4ab669SParav Pandit *ext_status = 0; 40366a4ab669SParav Pandit memcpy(wrb_payload, resp, sizeof(*resp) + resp->response_length); 40376a4ab669SParav Pandit be_dws_le_to_cpu(wrb_payload, sizeof(*resp) + resp->response_length); 40386a4ab669SParav Pandit err: 40396a4ab669SParav Pandit spin_unlock_bh(&adapter->mcc_lock); 40406a4ab669SParav Pandit return status; 40416a4ab669SParav Pandit } 40426a4ab669SParav Pandit EXPORT_SYMBOL(be_roce_mcc_cmd); 4043